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1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Brad Volkin <bradley.d.volkin@intel.com>
25 *
26 */
27
28#include "gt/intel_engine.h"
29#include "gt/intel_gpu_commands.h"
30
31#include "i915_drv.h"
32#include "i915_memcpy.h"
33
34/**
35 * DOC: batch buffer command parser
36 *
37 * Motivation:
38 * Certain OpenGL features (e.g. transform feedback, performance monitoring)
39 * require userspace code to submit batches containing commands such as
40 * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
41 * generations of the hardware will noop these commands in "unsecure" batches
42 * (which includes all userspace batches submitted via i915) even though the
43 * commands may be safe and represent the intended programming model of the
44 * device.
45 *
46 * The software command parser is similar in operation to the command parsing
47 * done in hardware for unsecure batches. However, the software parser allows
48 * some operations that would be noop'd by hardware, if the parser determines
49 * the operation is safe, and submits the batch as "secure" to prevent hardware
50 * parsing.
51 *
52 * Threats:
53 * At a high level, the hardware (and software) checks attempt to prevent
54 * granting userspace undue privileges. There are three categories of privilege.
55 *
56 * First, commands which are explicitly defined as privileged or which should
57 * only be used by the kernel driver. The parser rejects such commands
58 *
59 * Second, commands which access registers. To support correct/enhanced
60 * userspace functionality, particularly certain OpenGL extensions, the parser
61 * provides a whitelist of registers which userspace may safely access
62 *
63 * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc).
64 * The parser always rejects such commands.
65 *
66 * The majority of the problematic commands fall in the MI_* range, with only a
67 * few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW).
68 *
69 * Implementation:
70 * Each engine maintains tables of commands and registers which the parser
71 * uses in scanning batch buffers submitted to that engine.
72 *
73 * Since the set of commands that the parser must check for is significantly
74 * smaller than the number of commands supported, the parser tables contain only
75 * those commands required by the parser. This generally works because command
76 * opcode ranges have standard command length encodings. So for commands that
77 * the parser does not need to check, it can easily skip them. This is
78 * implemented via a per-engine length decoding vfunc.
79 *
80 * Unfortunately, there are a number of commands that do not follow the standard
81 * length encoding for their opcode range, primarily amongst the MI_* commands.
82 * To handle this, the parser provides a way to define explicit "skip" entries
83 * in the per-engine command tables.
84 *
85 * Other command table entries map fairly directly to high level categories
86 * mentioned above: rejected, register whitelist. The parser implements a number
87 * of checks, including the privileged memory checks, via a general bitmasking
88 * mechanism.
89 */
90
91/*
92 * A command that requires special handling by the command parser.
93 */
94struct drm_i915_cmd_descriptor {
95 /*
96 * Flags describing how the command parser processes the command.
97 *
98 * CMD_DESC_FIXED: The command has a fixed length if this is set,
99 * a length mask if not set
100 * CMD_DESC_SKIP: The command is allowed but does not follow the
101 * standard length encoding for the opcode range in
102 * which it falls
103 * CMD_DESC_REJECT: The command is never allowed
104 * CMD_DESC_REGISTER: The command should be checked against the
105 * register whitelist for the appropriate ring
106 */
107 u32 flags;
108#define CMD_DESC_FIXED (1<<0)
109#define CMD_DESC_SKIP (1<<1)
110#define CMD_DESC_REJECT (1<<2)
111#define CMD_DESC_REGISTER (1<<3)
112#define CMD_DESC_BITMASK (1<<4)
113
114 /*
115 * The command's unique identification bits and the bitmask to get them.
116 * This isn't strictly the opcode field as defined in the spec and may
117 * also include type, subtype, and/or subop fields.
118 */
119 struct {
120 u32 value;
121 u32 mask;
122 } cmd;
123
124 /*
125 * The command's length. The command is either fixed length (i.e. does
126 * not include a length field) or has a length field mask. The flag
127 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
128 * a length mask. All command entries in a command table must include
129 * length information.
130 */
131 union {
132 u32 fixed;
133 u32 mask;
134 } length;
135
136 /*
137 * Describes where to find a register address in the command to check
138 * against the ring's register whitelist. Only valid if flags has the
139 * CMD_DESC_REGISTER bit set.
140 *
141 * A non-zero step value implies that the command may access multiple
142 * registers in sequence (e.g. LRI), in that case step gives the
143 * distance in dwords between individual offset fields.
144 */
145 struct {
146 u32 offset;
147 u32 mask;
148 u32 step;
149 } reg;
150
151#define MAX_CMD_DESC_BITMASKS 3
152 /*
153 * Describes command checks where a particular dword is masked and
154 * compared against an expected value. If the command does not match
155 * the expected value, the parser rejects it. Only valid if flags has
156 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
157 * are valid.
158 *
159 * If the check specifies a non-zero condition_mask then the parser
160 * only performs the check when the bits specified by condition_mask
161 * are non-zero.
162 */
163 struct {
164 u32 offset;
165 u32 mask;
166 u32 expected;
167 u32 condition_offset;
168 u32 condition_mask;
169 } bits[MAX_CMD_DESC_BITMASKS];
170};
171
172/*
173 * A table of commands requiring special handling by the command parser.
174 *
175 * Each engine has an array of tables. Each table consists of an array of
176 * command descriptors, which must be sorted with command opcodes in
177 * ascending order.
178 */
179struct drm_i915_cmd_table {
180 const struct drm_i915_cmd_descriptor *table;
181 int count;
182};
183
184#define STD_MI_OPCODE_SHIFT (32 - 9)
185#define STD_3D_OPCODE_SHIFT (32 - 16)
186#define STD_2D_OPCODE_SHIFT (32 - 10)
187#define STD_MFX_OPCODE_SHIFT (32 - 16)
188#define MIN_OPCODE_SHIFT 16
189
190#define CMD(op, opm, f, lm, fl, ...) \
191 { \
192 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \
193 .cmd = { (op & ~0u << (opm)), ~0u << (opm) }, \
194 .length = { (lm) }, \
195 __VA_ARGS__ \
196 }
197
198/* Convenience macros to compress the tables */
199#define SMI STD_MI_OPCODE_SHIFT
200#define S3D STD_3D_OPCODE_SHIFT
201#define S2D STD_2D_OPCODE_SHIFT
202#define SMFX STD_MFX_OPCODE_SHIFT
203#define F true
204#define S CMD_DESC_SKIP
205#define R CMD_DESC_REJECT
206#define W CMD_DESC_REGISTER
207#define B CMD_DESC_BITMASK
208
209/* Command Mask Fixed Len Action
210 ---------------------------------------------------------- */
211static const struct drm_i915_cmd_descriptor gen7_common_cmds[] = {
212 CMD( MI_NOOP, SMI, F, 1, S ),
213 CMD( MI_USER_INTERRUPT, SMI, F, 1, R ),
214 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, R ),
215 CMD( MI_ARB_CHECK, SMI, F, 1, S ),
216 CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
217 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
218 CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ),
219 CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
220 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
221 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ),
222 CMD( MI_STORE_REGISTER_MEM, SMI, F, 3, W | B,
223 .reg = { .offset = 1, .mask = 0x007FFFFC },
224 .bits = {{
225 .offset = 0,
226 .mask = MI_GLOBAL_GTT,
227 .expected = 0,
228 }}, ),
229 CMD( MI_LOAD_REGISTER_MEM, SMI, F, 3, W | B,
230 .reg = { .offset = 1, .mask = 0x007FFFFC },
231 .bits = {{
232 .offset = 0,
233 .mask = MI_GLOBAL_GTT,
234 .expected = 0,
235 }}, ),
236 /*
237 * MI_BATCH_BUFFER_START requires some special handling. It's not
238 * really a 'skip' action but it doesn't seem like it's worth adding
239 * a new action. See intel_engine_cmd_parser().
240 */
241 CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
242};
243
244static const struct drm_i915_cmd_descriptor gen7_render_cmds[] = {
245 CMD( MI_FLUSH, SMI, F, 1, S ),
246 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
247 CMD( MI_PREDICATE, SMI, F, 1, S ),
248 CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ),
249 CMD( MI_SET_APPID, SMI, F, 1, S ),
250 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
251 CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ),
252 CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ),
253 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B,
254 .bits = {{
255 .offset = 0,
256 .mask = MI_GLOBAL_GTT,
257 .expected = 0,
258 }}, ),
259 CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ),
260 CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B,
261 .bits = {{
262 .offset = 0,
263 .mask = MI_GLOBAL_GTT,
264 .expected = 0,
265 }}, ),
266 CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B,
267 .bits = {{
268 .offset = 1,
269 .mask = MI_REPORT_PERF_COUNT_GGTT,
270 .expected = 0,
271 }}, ),
272 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
273 .bits = {{
274 .offset = 0,
275 .mask = MI_GLOBAL_GTT,
276 .expected = 0,
277 }}, ),
278 CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ),
279 CMD( PIPELINE_SELECT, S3D, F, 1, S ),
280 CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B,
281 .bits = {{
282 .offset = 2,
283 .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
284 .expected = 0,
285 }}, ),
286 CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ),
287 CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ),
288 CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ),
289 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B,
290 .bits = {{
291 .offset = 1,
292 .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),
293 .expected = 0,
294 },
295 {
296 .offset = 1,
297 .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB |
298 PIPE_CONTROL_STORE_DATA_INDEX),
299 .expected = 0,
300 .condition_offset = 1,
301 .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK,
302 }}, ),
303};
304
305static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
306 CMD( MI_SET_PREDICATE, SMI, F, 1, S ),
307 CMD( MI_RS_CONTROL, SMI, F, 1, S ),
308 CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ),
309 CMD( MI_SET_APPID, SMI, F, 1, S ),
310 CMD( MI_RS_CONTEXT, SMI, F, 1, S ),
311 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ),
312 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
313 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W,
314 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ),
315 CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ),
316 CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ),
317 CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ),
318 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ),
319 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ),
320
321 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ),
322 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ),
323 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ),
324 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ),
325 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ),
326};
327
328static const struct drm_i915_cmd_descriptor gen7_video_cmds[] = {
329 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
330 CMD( MI_SET_APPID, SMI, F, 1, S ),
331 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
332 .bits = {{
333 .offset = 0,
334 .mask = MI_GLOBAL_GTT,
335 .expected = 0,
336 }}, ),
337 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
338 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
339 .bits = {{
340 .offset = 0,
341 .mask = MI_FLUSH_DW_NOTIFY,
342 .expected = 0,
343 },
344 {
345 .offset = 1,
346 .mask = MI_FLUSH_DW_USE_GTT,
347 .expected = 0,
348 .condition_offset = 0,
349 .condition_mask = MI_FLUSH_DW_OP_MASK,
350 },
351 {
352 .offset = 0,
353 .mask = MI_FLUSH_DW_STORE_INDEX,
354 .expected = 0,
355 .condition_offset = 0,
356 .condition_mask = MI_FLUSH_DW_OP_MASK,
357 }}, ),
358 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
359 .bits = {{
360 .offset = 0,
361 .mask = MI_GLOBAL_GTT,
362 .expected = 0,
363 }}, ),
364 /*
365 * MFX_WAIT doesn't fit the way we handle length for most commands.
366 * It has a length field but it uses a non-standard length bias.
367 * It is always 1 dword though, so just treat it as fixed length.
368 */
369 CMD( MFX_WAIT, SMFX, F, 1, S ),
370};
371
372static const struct drm_i915_cmd_descriptor gen7_vecs_cmds[] = {
373 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
374 CMD( MI_SET_APPID, SMI, F, 1, S ),
375 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
376 .bits = {{
377 .offset = 0,
378 .mask = MI_GLOBAL_GTT,
379 .expected = 0,
380 }}, ),
381 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
382 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
383 .bits = {{
384 .offset = 0,
385 .mask = MI_FLUSH_DW_NOTIFY,
386 .expected = 0,
387 },
388 {
389 .offset = 1,
390 .mask = MI_FLUSH_DW_USE_GTT,
391 .expected = 0,
392 .condition_offset = 0,
393 .condition_mask = MI_FLUSH_DW_OP_MASK,
394 },
395 {
396 .offset = 0,
397 .mask = MI_FLUSH_DW_STORE_INDEX,
398 .expected = 0,
399 .condition_offset = 0,
400 .condition_mask = MI_FLUSH_DW_OP_MASK,
401 }}, ),
402 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
403 .bits = {{
404 .offset = 0,
405 .mask = MI_GLOBAL_GTT,
406 .expected = 0,
407 }}, ),
408};
409
410static const struct drm_i915_cmd_descriptor gen7_blt_cmds[] = {
411 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
412 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B,
413 .bits = {{
414 .offset = 0,
415 .mask = MI_GLOBAL_GTT,
416 .expected = 0,
417 }}, ),
418 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
419 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
420 .bits = {{
421 .offset = 0,
422 .mask = MI_FLUSH_DW_NOTIFY,
423 .expected = 0,
424 },
425 {
426 .offset = 1,
427 .mask = MI_FLUSH_DW_USE_GTT,
428 .expected = 0,
429 .condition_offset = 0,
430 .condition_mask = MI_FLUSH_DW_OP_MASK,
431 },
432 {
433 .offset = 0,
434 .mask = MI_FLUSH_DW_STORE_INDEX,
435 .expected = 0,
436 .condition_offset = 0,
437 .condition_mask = MI_FLUSH_DW_OP_MASK,
438 }}, ),
439 CMD( COLOR_BLT, S2D, !F, 0x3F, S ),
440 CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ),
441};
442
443static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = {
444 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ),
445 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
446};
447
448/*
449 * For Gen9 we can still rely on the h/w to enforce cmd security, and only
450 * need to re-enforce the register access checks. We therefore only need to
451 * teach the cmdparser how to find the end of each command, and identify
452 * register accesses. The table doesn't need to reject any commands, and so
453 * the only commands listed here are:
454 * 1) Those that touch registers
455 * 2) Those that do not have the default 8-bit length
456 *
457 * Note that the default MI length mask chosen for this table is 0xFF, not
458 * the 0x3F used on older devices. This is because the vast majority of MI
459 * cmds on Gen9 use a standard 8-bit Length field.
460 * All the Gen9 blitter instructions are standard 0xFF length mask, and
461 * none allow access to non-general registers, so in fact no BLT cmds are
462 * included in the table at all.
463 *
464 */
465static const struct drm_i915_cmd_descriptor gen9_blt_cmds[] = {
466 CMD( MI_NOOP, SMI, F, 1, S ),
467 CMD( MI_USER_INTERRUPT, SMI, F, 1, S ),
468 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, S ),
469 CMD( MI_FLUSH, SMI, F, 1, S ),
470 CMD( MI_ARB_CHECK, SMI, F, 1, S ),
471 CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
472 CMD( MI_ARB_ON_OFF, SMI, F, 1, S ),
473 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
474 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, S ),
475 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, S ),
476 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, S ),
477 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
478 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ),
479 CMD( MI_UPDATE_GTT, SMI, !F, 0x3FF, S ),
480 CMD( MI_STORE_REGISTER_MEM_GEN8, SMI, F, 4, W,
481 .reg = { .offset = 1, .mask = 0x007FFFFC } ),
482 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, S ),
483 CMD( MI_LOAD_REGISTER_MEM_GEN8, SMI, F, 4, W,
484 .reg = { .offset = 1, .mask = 0x007FFFFC } ),
485 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W,
486 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ),
487
488 /*
489 * We allow BB_START but apply further checks. We just sanitize the
490 * basic fields here.
491 */
492#define MI_BB_START_OPERAND_MASK GENMASK(SMI-1, 0)
493#define MI_BB_START_OPERAND_EXPECT (MI_BATCH_PPGTT_HSW | 1)
494 CMD( MI_BATCH_BUFFER_START_GEN8, SMI, !F, 0xFF, B,
495 .bits = {{
496 .offset = 0,
497 .mask = MI_BB_START_OPERAND_MASK,
498 .expected = MI_BB_START_OPERAND_EXPECT,
499 }}, ),
500};
501
502static const struct drm_i915_cmd_descriptor noop_desc =
503 CMD(MI_NOOP, SMI, F, 1, S);
504
505#undef CMD
506#undef SMI
507#undef S3D
508#undef S2D
509#undef SMFX
510#undef F
511#undef S
512#undef R
513#undef W
514#undef B
515
516static const struct drm_i915_cmd_table gen7_render_cmd_table[] = {
517 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
518 { gen7_render_cmds, ARRAY_SIZE(gen7_render_cmds) },
519};
520
521static const struct drm_i915_cmd_table hsw_render_ring_cmd_table[] = {
522 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
523 { gen7_render_cmds, ARRAY_SIZE(gen7_render_cmds) },
524 { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) },
525};
526
527static const struct drm_i915_cmd_table gen7_video_cmd_table[] = {
528 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
529 { gen7_video_cmds, ARRAY_SIZE(gen7_video_cmds) },
530};
531
532static const struct drm_i915_cmd_table hsw_vebox_cmd_table[] = {
533 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
534 { gen7_vecs_cmds, ARRAY_SIZE(gen7_vecs_cmds) },
535};
536
537static const struct drm_i915_cmd_table gen7_blt_cmd_table[] = {
538 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
539 { gen7_blt_cmds, ARRAY_SIZE(gen7_blt_cmds) },
540};
541
542static const struct drm_i915_cmd_table hsw_blt_ring_cmd_table[] = {
543 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
544 { gen7_blt_cmds, ARRAY_SIZE(gen7_blt_cmds) },
545 { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
546};
547
548static const struct drm_i915_cmd_table gen9_blt_cmd_table[] = {
549 { gen9_blt_cmds, ARRAY_SIZE(gen9_blt_cmds) },
550};
551
552
553/*
554 * Register whitelists, sorted by increasing register offset.
555 */
556
557/*
558 * An individual whitelist entry granting access to register addr. If
559 * mask is non-zero the argument of immediate register writes will be
560 * AND-ed with mask, and the command will be rejected if the result
561 * doesn't match value.
562 *
563 * Registers with non-zero mask are only allowed to be written using
564 * LRI.
565 */
566struct drm_i915_reg_descriptor {
567 i915_reg_t addr;
568 u32 mask;
569 u32 value;
570};
571
572/* Convenience macro for adding 32-bit registers. */
573#define REG32(_reg, ...) \
574 { .addr = (_reg), __VA_ARGS__ }
575
576#define REG32_IDX(_reg, idx) \
577 { .addr = _reg(idx) }
578
579/*
580 * Convenience macro for adding 64-bit registers.
581 *
582 * Some registers that userspace accesses are 64 bits. The register
583 * access commands only allow 32-bit accesses. Hence, we have to include
584 * entries for both halves of the 64-bit registers.
585 */
586#define REG64(_reg) \
587 { .addr = _reg }, \
588 { .addr = _reg ## _UDW }
589
590#define REG64_IDX(_reg, idx) \
591 { .addr = _reg(idx) }, \
592 { .addr = _reg ## _UDW(idx) }
593
594static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
595 REG64(GPGPU_THREADS_DISPATCHED),
596 REG64(HS_INVOCATION_COUNT),
597 REG64(DS_INVOCATION_COUNT),
598 REG64(IA_VERTICES_COUNT),
599 REG64(IA_PRIMITIVES_COUNT),
600 REG64(VS_INVOCATION_COUNT),
601 REG64(GS_INVOCATION_COUNT),
602 REG64(GS_PRIMITIVES_COUNT),
603 REG64(CL_INVOCATION_COUNT),
604 REG64(CL_PRIMITIVES_COUNT),
605 REG64(PS_INVOCATION_COUNT),
606 REG64(PS_DEPTH_COUNT),
607 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
608 REG64(MI_PREDICATE_SRC0),
609 REG64(MI_PREDICATE_SRC1),
610 REG32(GEN7_3DPRIM_END_OFFSET),
611 REG32(GEN7_3DPRIM_START_VERTEX),
612 REG32(GEN7_3DPRIM_VERTEX_COUNT),
613 REG32(GEN7_3DPRIM_INSTANCE_COUNT),
614 REG32(GEN7_3DPRIM_START_INSTANCE),
615 REG32(GEN7_3DPRIM_BASE_VERTEX),
616 REG32(GEN7_GPGPU_DISPATCHDIMX),
617 REG32(GEN7_GPGPU_DISPATCHDIMY),
618 REG32(GEN7_GPGPU_DISPATCHDIMZ),
619 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
620 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0),
621 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1),
622 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2),
623 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 3),
624 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 0),
625 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 1),
626 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 2),
627 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 3),
628 REG32(GEN7_SO_WRITE_OFFSET(0)),
629 REG32(GEN7_SO_WRITE_OFFSET(1)),
630 REG32(GEN7_SO_WRITE_OFFSET(2)),
631 REG32(GEN7_SO_WRITE_OFFSET(3)),
632 REG32(GEN7_L3SQCREG1),
633 REG32(GEN7_L3CNTLREG2),
634 REG32(GEN7_L3CNTLREG3),
635 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
636};
637
638static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
639 REG64_IDX(HSW_CS_GPR, 0),
640 REG64_IDX(HSW_CS_GPR, 1),
641 REG64_IDX(HSW_CS_GPR, 2),
642 REG64_IDX(HSW_CS_GPR, 3),
643 REG64_IDX(HSW_CS_GPR, 4),
644 REG64_IDX(HSW_CS_GPR, 5),
645 REG64_IDX(HSW_CS_GPR, 6),
646 REG64_IDX(HSW_CS_GPR, 7),
647 REG64_IDX(HSW_CS_GPR, 8),
648 REG64_IDX(HSW_CS_GPR, 9),
649 REG64_IDX(HSW_CS_GPR, 10),
650 REG64_IDX(HSW_CS_GPR, 11),
651 REG64_IDX(HSW_CS_GPR, 12),
652 REG64_IDX(HSW_CS_GPR, 13),
653 REG64_IDX(HSW_CS_GPR, 14),
654 REG64_IDX(HSW_CS_GPR, 15),
655 REG32(HSW_SCRATCH1,
656 .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
657 .value = 0),
658 REG32(HSW_ROW_CHICKEN3,
659 .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 |
660 HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
661 .value = 0),
662};
663
664static const struct drm_i915_reg_descriptor gen7_blt_regs[] = {
665 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
666 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
667 REG32(BCS_SWCTRL),
668 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
669};
670
671static const struct drm_i915_reg_descriptor gen9_blt_regs[] = {
672 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
673 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
674 REG32(BCS_SWCTRL),
675 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
676 REG32_IDX(RING_CTX_TIMESTAMP, BLT_RING_BASE),
677 REG64_IDX(BCS_GPR, 0),
678 REG64_IDX(BCS_GPR, 1),
679 REG64_IDX(BCS_GPR, 2),
680 REG64_IDX(BCS_GPR, 3),
681 REG64_IDX(BCS_GPR, 4),
682 REG64_IDX(BCS_GPR, 5),
683 REG64_IDX(BCS_GPR, 6),
684 REG64_IDX(BCS_GPR, 7),
685 REG64_IDX(BCS_GPR, 8),
686 REG64_IDX(BCS_GPR, 9),
687 REG64_IDX(BCS_GPR, 10),
688 REG64_IDX(BCS_GPR, 11),
689 REG64_IDX(BCS_GPR, 12),
690 REG64_IDX(BCS_GPR, 13),
691 REG64_IDX(BCS_GPR, 14),
692 REG64_IDX(BCS_GPR, 15),
693};
694
695#undef REG64
696#undef REG32
697
698struct drm_i915_reg_table {
699 const struct drm_i915_reg_descriptor *regs;
700 int num_regs;
701};
702
703static const struct drm_i915_reg_table ivb_render_reg_tables[] = {
704 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs) },
705};
706
707static const struct drm_i915_reg_table ivb_blt_reg_tables[] = {
708 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs) },
709};
710
711static const struct drm_i915_reg_table hsw_render_reg_tables[] = {
712 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs) },
713 { hsw_render_regs, ARRAY_SIZE(hsw_render_regs) },
714};
715
716static const struct drm_i915_reg_table hsw_blt_reg_tables[] = {
717 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs) },
718};
719
720static const struct drm_i915_reg_table gen9_blt_reg_tables[] = {
721 { gen9_blt_regs, ARRAY_SIZE(gen9_blt_regs) },
722};
723
724static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
725{
726 u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
727 u32 subclient =
728 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
729
730 if (client == INSTR_MI_CLIENT)
731 return 0x3F;
732 else if (client == INSTR_RC_CLIENT) {
733 if (subclient == INSTR_MEDIA_SUBCLIENT)
734 return 0xFFFF;
735 else
736 return 0xFF;
737 }
738
739 DRM_DEBUG("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header);
740 return 0;
741}
742
743static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)
744{
745 u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
746 u32 subclient =
747 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
748 u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT;
749
750 if (client == INSTR_MI_CLIENT)
751 return 0x3F;
752 else if (client == INSTR_RC_CLIENT) {
753 if (subclient == INSTR_MEDIA_SUBCLIENT) {
754 if (op == 6)
755 return 0xFFFF;
756 else
757 return 0xFFF;
758 } else
759 return 0xFF;
760 }
761
762 DRM_DEBUG("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header);
763 return 0;
764}
765
766static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
767{
768 u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
769
770 if (client == INSTR_MI_CLIENT)
771 return 0x3F;
772 else if (client == INSTR_BC_CLIENT)
773 return 0xFF;
774
775 DRM_DEBUG("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
776 return 0;
777}
778
779static u32 gen9_blt_get_cmd_length_mask(u32 cmd_header)
780{
781 u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
782
783 if (client == INSTR_MI_CLIENT || client == INSTR_BC_CLIENT)
784 return 0xFF;
785
786 DRM_DEBUG("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
787 return 0;
788}
789
790static bool validate_cmds_sorted(const struct intel_engine_cs *engine,
791 const struct drm_i915_cmd_table *cmd_tables,
792 int cmd_table_count)
793{
794 int i;
795 bool ret = true;
796
797 if (!cmd_tables || cmd_table_count == 0)
798 return true;
799
800 for (i = 0; i < cmd_table_count; i++) {
801 const struct drm_i915_cmd_table *table = &cmd_tables[i];
802 u32 previous = 0;
803 int j;
804
805 for (j = 0; j < table->count; j++) {
806 const struct drm_i915_cmd_descriptor *desc =
807 &table->table[j];
808 u32 curr = desc->cmd.value & desc->cmd.mask;
809
810 if (curr < previous) {
811 drm_err(&engine->i915->drm,
812 "CMD: %s [%d] command table not sorted: "
813 "table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
814 engine->name, engine->id,
815 i, j, curr, previous);
816 ret = false;
817 }
818
819 previous = curr;
820 }
821 }
822
823 return ret;
824}
825
826static bool check_sorted(const struct intel_engine_cs *engine,
827 const struct drm_i915_reg_descriptor *reg_table,
828 int reg_count)
829{
830 int i;
831 u32 previous = 0;
832 bool ret = true;
833
834 for (i = 0; i < reg_count; i++) {
835 u32 curr = i915_mmio_reg_offset(reg_table[i].addr);
836
837 if (curr < previous) {
838 drm_err(&engine->i915->drm,
839 "CMD: %s [%d] register table not sorted: "
840 "entry=%d reg=0x%08X prev=0x%08X\n",
841 engine->name, engine->id,
842 i, curr, previous);
843 ret = false;
844 }
845
846 previous = curr;
847 }
848
849 return ret;
850}
851
852static bool validate_regs_sorted(struct intel_engine_cs *engine)
853{
854 int i;
855 const struct drm_i915_reg_table *table;
856
857 for (i = 0; i < engine->reg_table_count; i++) {
858 table = &engine->reg_tables[i];
859 if (!check_sorted(engine, table->regs, table->num_regs))
860 return false;
861 }
862
863 return true;
864}
865
866struct cmd_node {
867 const struct drm_i915_cmd_descriptor *desc;
868 struct hlist_node node;
869};
870
871/*
872 * Different command ranges have different numbers of bits for the opcode. For
873 * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The
874 * problem is that, for example, MI commands use bits 22:16 for other fields
875 * such as GGTT vs PPGTT bits. If we include those bits in the mask then when
876 * we mask a command from a batch it could hash to the wrong bucket due to
877 * non-opcode bits being set. But if we don't include those bits, some 3D
878 * commands may hash to the same bucket due to not including opcode bits that
879 * make the command unique. For now, we will risk hashing to the same bucket.
880 */
881static inline u32 cmd_header_key(u32 x)
882{
883 switch (x >> INSTR_CLIENT_SHIFT) {
884 default:
885 case INSTR_MI_CLIENT:
886 return x >> STD_MI_OPCODE_SHIFT;
887 case INSTR_RC_CLIENT:
888 return x >> STD_3D_OPCODE_SHIFT;
889 case INSTR_BC_CLIENT:
890 return x >> STD_2D_OPCODE_SHIFT;
891 }
892}
893
894static int init_hash_table(struct intel_engine_cs *engine,
895 const struct drm_i915_cmd_table *cmd_tables,
896 int cmd_table_count)
897{
898 int i, j;
899
900 hash_init(engine->cmd_hash);
901
902 for (i = 0; i < cmd_table_count; i++) {
903 const struct drm_i915_cmd_table *table = &cmd_tables[i];
904
905 for (j = 0; j < table->count; j++) {
906 const struct drm_i915_cmd_descriptor *desc =
907 &table->table[j];
908 struct cmd_node *desc_node =
909 kmalloc(sizeof(*desc_node), GFP_KERNEL);
910
911 if (!desc_node)
912 return -ENOMEM;
913
914 desc_node->desc = desc;
915 hash_add(engine->cmd_hash, &desc_node->node,
916 cmd_header_key(desc->cmd.value));
917 }
918 }
919
920 return 0;
921}
922
923static void fini_hash_table(struct intel_engine_cs *engine)
924{
925 struct hlist_node *tmp;
926 struct cmd_node *desc_node;
927 int i;
928
929 hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) {
930 hash_del(&desc_node->node);
931 kfree(desc_node);
932 }
933}
934
935/**
936 * intel_engine_init_cmd_parser() - set cmd parser related fields for an engine
937 * @engine: the engine to initialize
938 *
939 * Optionally initializes fields related to batch buffer command parsing in the
940 * struct intel_engine_cs based on whether the platform requires software
941 * command parsing.
942 */
943int intel_engine_init_cmd_parser(struct intel_engine_cs *engine)
944{
945 const struct drm_i915_cmd_table *cmd_tables;
946 int cmd_table_count;
947 int ret;
948
949 if (GRAPHICS_VER(engine->i915) != 7 && !(GRAPHICS_VER(engine->i915) == 9 &&
950 engine->class == COPY_ENGINE_CLASS))
951 return 0;
952
953 switch (engine->class) {
954 case RENDER_CLASS:
955 if (IS_HASWELL(engine->i915)) {
956 cmd_tables = hsw_render_ring_cmd_table;
957 cmd_table_count =
958 ARRAY_SIZE(hsw_render_ring_cmd_table);
959 } else {
960 cmd_tables = gen7_render_cmd_table;
961 cmd_table_count = ARRAY_SIZE(gen7_render_cmd_table);
962 }
963
964 if (IS_HASWELL(engine->i915)) {
965 engine->reg_tables = hsw_render_reg_tables;
966 engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables);
967 } else {
968 engine->reg_tables = ivb_render_reg_tables;
969 engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables);
970 }
971 engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
972 break;
973 case VIDEO_DECODE_CLASS:
974 cmd_tables = gen7_video_cmd_table;
975 cmd_table_count = ARRAY_SIZE(gen7_video_cmd_table);
976 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
977 break;
978 case COPY_ENGINE_CLASS:
979 engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
980 if (GRAPHICS_VER(engine->i915) == 9) {
981 cmd_tables = gen9_blt_cmd_table;
982 cmd_table_count = ARRAY_SIZE(gen9_blt_cmd_table);
983 engine->get_cmd_length_mask =
984 gen9_blt_get_cmd_length_mask;
985
986 /* BCS Engine unsafe without parser */
987 engine->flags |= I915_ENGINE_REQUIRES_CMD_PARSER;
988 } else if (IS_HASWELL(engine->i915)) {
989 cmd_tables = hsw_blt_ring_cmd_table;
990 cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmd_table);
991 } else {
992 cmd_tables = gen7_blt_cmd_table;
993 cmd_table_count = ARRAY_SIZE(gen7_blt_cmd_table);
994 }
995
996 if (GRAPHICS_VER(engine->i915) == 9) {
997 engine->reg_tables = gen9_blt_reg_tables;
998 engine->reg_table_count =
999 ARRAY_SIZE(gen9_blt_reg_tables);
1000 } else if (IS_HASWELL(engine->i915)) {
1001 engine->reg_tables = hsw_blt_reg_tables;
1002 engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables);
1003 } else {
1004 engine->reg_tables = ivb_blt_reg_tables;
1005 engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables);
1006 }
1007 break;
1008 case VIDEO_ENHANCEMENT_CLASS:
1009 cmd_tables = hsw_vebox_cmd_table;
1010 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmd_table);
1011 /* VECS can use the same length_mask function as VCS */
1012 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
1013 break;
1014 default:
1015 MISSING_CASE(engine->class);
1016 goto out;
1017 }
1018
1019 if (!validate_cmds_sorted(engine, cmd_tables, cmd_table_count)) {
1020 drm_err(&engine->i915->drm,
1021 "%s: command descriptions are not sorted\n",
1022 engine->name);
1023 goto out;
1024 }
1025 if (!validate_regs_sorted(engine)) {
1026 drm_err(&engine->i915->drm,
1027 "%s: registers are not sorted\n", engine->name);
1028 goto out;
1029 }
1030
1031 ret = init_hash_table(engine, cmd_tables, cmd_table_count);
1032 if (ret) {
1033 drm_err(&engine->i915->drm,
1034 "%s: initialised failed!\n", engine->name);
1035 fini_hash_table(engine);
1036 goto out;
1037 }
1038
1039 engine->flags |= I915_ENGINE_USING_CMD_PARSER;
1040
1041out:
1042 if (intel_engine_requires_cmd_parser(engine) &&
1043 !intel_engine_using_cmd_parser(engine))
1044 return -EINVAL;
1045
1046 return 0;
1047}
1048
1049/**
1050 * intel_engine_cleanup_cmd_parser() - clean up cmd parser related fields
1051 * @engine: the engine to clean up
1052 *
1053 * Releases any resources related to command parsing that may have been
1054 * initialized for the specified engine.
1055 */
1056void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine)
1057{
1058 if (!intel_engine_using_cmd_parser(engine))
1059 return;
1060
1061 fini_hash_table(engine);
1062}
1063
1064static const struct drm_i915_cmd_descriptor*
1065find_cmd_in_table(struct intel_engine_cs *engine,
1066 u32 cmd_header)
1067{
1068 struct cmd_node *desc_node;
1069
1070 hash_for_each_possible(engine->cmd_hash, desc_node, node,
1071 cmd_header_key(cmd_header)) {
1072 const struct drm_i915_cmd_descriptor *desc = desc_node->desc;
1073 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0)
1074 return desc;
1075 }
1076
1077 return NULL;
1078}
1079
1080/*
1081 * Returns a pointer to a descriptor for the command specified by cmd_header.
1082 *
1083 * The caller must supply space for a default descriptor via the default_desc
1084 * parameter. If no descriptor for the specified command exists in the engine's
1085 * command parser tables, this function fills in default_desc based on the
1086 * engine's default length encoding and returns default_desc.
1087 */
1088static const struct drm_i915_cmd_descriptor*
1089find_cmd(struct intel_engine_cs *engine,
1090 u32 cmd_header,
1091 const struct drm_i915_cmd_descriptor *desc,
1092 struct drm_i915_cmd_descriptor *default_desc)
1093{
1094 u32 mask;
1095
1096 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0)
1097 return desc;
1098
1099 desc = find_cmd_in_table(engine, cmd_header);
1100 if (desc)
1101 return desc;
1102
1103 mask = engine->get_cmd_length_mask(cmd_header);
1104 if (!mask)
1105 return NULL;
1106
1107 default_desc->cmd.value = cmd_header;
1108 default_desc->cmd.mask = ~0u << MIN_OPCODE_SHIFT;
1109 default_desc->length.mask = mask;
1110 default_desc->flags = CMD_DESC_SKIP;
1111 return default_desc;
1112}
1113
1114static const struct drm_i915_reg_descriptor *
1115__find_reg(const struct drm_i915_reg_descriptor *table, int count, u32 addr)
1116{
1117 int start = 0, end = count;
1118 while (start < end) {
1119 int mid = start + (end - start) / 2;
1120 int ret = addr - i915_mmio_reg_offset(table[mid].addr);
1121 if (ret < 0)
1122 end = mid;
1123 else if (ret > 0)
1124 start = mid + 1;
1125 else
1126 return &table[mid];
1127 }
1128 return NULL;
1129}
1130
1131static const struct drm_i915_reg_descriptor *
1132find_reg(const struct intel_engine_cs *engine, u32 addr)
1133{
1134 const struct drm_i915_reg_table *table = engine->reg_tables;
1135 const struct drm_i915_reg_descriptor *reg = NULL;
1136 int count = engine->reg_table_count;
1137
1138 for (; !reg && (count > 0); ++table, --count)
1139 reg = __find_reg(table->regs, table->num_regs, addr);
1140
1141 return reg;
1142}
1143
1144/* Returns a vmap'd pointer to dst_obj, which the caller must unmap */
1145static u32 *copy_batch(struct drm_i915_gem_object *dst_obj,
1146 struct drm_i915_gem_object *src_obj,
1147 unsigned long offset, unsigned long length,
1148 bool *needs_clflush_after)
1149{
1150 unsigned int src_needs_clflush;
1151 unsigned int dst_needs_clflush;
1152 void *dst, *src;
1153 int ret;
1154
1155 ret = i915_gem_object_prepare_write(dst_obj, &dst_needs_clflush);
1156 if (ret)
1157 return ERR_PTR(ret);
1158
1159 dst = i915_gem_object_pin_map(dst_obj, I915_MAP_WB);
1160 i915_gem_object_finish_access(dst_obj);
1161 if (IS_ERR(dst))
1162 return dst;
1163
1164 ret = i915_gem_object_prepare_read(src_obj, &src_needs_clflush);
1165 if (ret) {
1166 i915_gem_object_unpin_map(dst_obj);
1167 return ERR_PTR(ret);
1168 }
1169
1170 src = ERR_PTR(-ENODEV);
1171 if (src_needs_clflush && i915_has_memcpy_from_wc()) {
1172 src = i915_gem_object_pin_map(src_obj, I915_MAP_WC);
1173 if (!IS_ERR(src)) {
1174 i915_unaligned_memcpy_from_wc(dst,
1175 src + offset,
1176 length);
1177 i915_gem_object_unpin_map(src_obj);
1178 }
1179 }
1180 if (IS_ERR(src)) {
1181 unsigned long x, n, remain;
1182 void *ptr;
1183
1184 /*
1185 * We can avoid clflushing partial cachelines before the write
1186 * if we only every write full cache-lines. Since we know that
1187 * both the source and destination are in multiples of
1188 * PAGE_SIZE, we can simply round up to the next cacheline.
1189 * We don't care about copying too much here as we only
1190 * validate up to the end of the batch.
1191 */
1192 remain = length;
1193 if (dst_needs_clflush & CLFLUSH_BEFORE)
1194 remain = round_up(remain,
1195 boot_cpu_data.x86_clflush_size);
1196
1197 ptr = dst;
1198 x = offset_in_page(offset);
1199 for (n = offset >> PAGE_SHIFT; remain; n++) {
1200 int len = min(remain, PAGE_SIZE - x);
1201
1202 src = kmap_atomic(i915_gem_object_get_page(src_obj, n));
1203 if (src_needs_clflush)
1204 drm_clflush_virt_range(src + x, len);
1205 memcpy(ptr, src + x, len);
1206 kunmap_atomic(src);
1207
1208 ptr += len;
1209 remain -= len;
1210 x = 0;
1211 }
1212 }
1213
1214 i915_gem_object_finish_access(src_obj);
1215
1216 memset32(dst + length, 0, (dst_obj->base.size - length) / sizeof(u32));
1217
1218 /* dst_obj is returned with vmap pinned */
1219 *needs_clflush_after = dst_needs_clflush & CLFLUSH_AFTER;
1220
1221 return dst;
1222}
1223
1224static inline bool cmd_desc_is(const struct drm_i915_cmd_descriptor * const desc,
1225 const u32 cmd)
1226{
1227 return desc->cmd.value == (cmd & desc->cmd.mask);
1228}
1229
1230static bool check_cmd(const struct intel_engine_cs *engine,
1231 const struct drm_i915_cmd_descriptor *desc,
1232 const u32 *cmd, u32 length)
1233{
1234 if (desc->flags & CMD_DESC_SKIP)
1235 return true;
1236
1237 if (desc->flags & CMD_DESC_REJECT) {
1238 DRM_DEBUG("CMD: Rejected command: 0x%08X\n", *cmd);
1239 return false;
1240 }
1241
1242 if (desc->flags & CMD_DESC_REGISTER) {
1243 /*
1244 * Get the distance between individual register offset
1245 * fields if the command can perform more than one
1246 * access at a time.
1247 */
1248 const u32 step = desc->reg.step ? desc->reg.step : length;
1249 u32 offset;
1250
1251 for (offset = desc->reg.offset; offset < length;
1252 offset += step) {
1253 const u32 reg_addr = cmd[offset] & desc->reg.mask;
1254 const struct drm_i915_reg_descriptor *reg =
1255 find_reg(engine, reg_addr);
1256
1257 if (!reg) {
1258 DRM_DEBUG("CMD: Rejected register 0x%08X in command: 0x%08X (%s)\n",
1259 reg_addr, *cmd, engine->name);
1260 return false;
1261 }
1262
1263 /*
1264 * Check the value written to the register against the
1265 * allowed mask/value pair given in the whitelist entry.
1266 */
1267 if (reg->mask) {
1268 if (cmd_desc_is(desc, MI_LOAD_REGISTER_MEM)) {
1269 DRM_DEBUG("CMD: Rejected LRM to masked register 0x%08X\n",
1270 reg_addr);
1271 return false;
1272 }
1273
1274 if (cmd_desc_is(desc, MI_LOAD_REGISTER_REG)) {
1275 DRM_DEBUG("CMD: Rejected LRR to masked register 0x%08X\n",
1276 reg_addr);
1277 return false;
1278 }
1279
1280 if (cmd_desc_is(desc, MI_LOAD_REGISTER_IMM(1)) &&
1281 (offset + 2 > length ||
1282 (cmd[offset + 1] & reg->mask) != reg->value)) {
1283 DRM_DEBUG("CMD: Rejected LRI to masked register 0x%08X\n",
1284 reg_addr);
1285 return false;
1286 }
1287 }
1288 }
1289 }
1290
1291 if (desc->flags & CMD_DESC_BITMASK) {
1292 int i;
1293
1294 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) {
1295 u32 dword;
1296
1297 if (desc->bits[i].mask == 0)
1298 break;
1299
1300 if (desc->bits[i].condition_mask != 0) {
1301 u32 offset =
1302 desc->bits[i].condition_offset;
1303 u32 condition = cmd[offset] &
1304 desc->bits[i].condition_mask;
1305
1306 if (condition == 0)
1307 continue;
1308 }
1309
1310 if (desc->bits[i].offset >= length) {
1311 DRM_DEBUG("CMD: Rejected command 0x%08X, too short to check bitmask (%s)\n",
1312 *cmd, engine->name);
1313 return false;
1314 }
1315
1316 dword = cmd[desc->bits[i].offset] &
1317 desc->bits[i].mask;
1318
1319 if (dword != desc->bits[i].expected) {
1320 DRM_DEBUG("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (%s)\n",
1321 *cmd,
1322 desc->bits[i].mask,
1323 desc->bits[i].expected,
1324 dword, engine->name);
1325 return false;
1326 }
1327 }
1328 }
1329
1330 return true;
1331}
1332
1333static int check_bbstart(u32 *cmd, u32 offset, u32 length,
1334 u32 batch_length,
1335 u64 batch_addr,
1336 u64 shadow_addr,
1337 const unsigned long *jump_whitelist)
1338{
1339 u64 jump_offset, jump_target;
1340 u32 target_cmd_offset, target_cmd_index;
1341
1342 /* For igt compatibility on older platforms */
1343 if (!jump_whitelist) {
1344 DRM_DEBUG("CMD: Rejecting BB_START for ggtt based submission\n");
1345 return -EACCES;
1346 }
1347
1348 if (length != 3) {
1349 DRM_DEBUG("CMD: Recursive BB_START with bad length(%u)\n",
1350 length);
1351 return -EINVAL;
1352 }
1353
1354 jump_target = *(u64 *)(cmd + 1);
1355 jump_offset = jump_target - batch_addr;
1356
1357 /*
1358 * Any underflow of jump_target is guaranteed to be outside the range
1359 * of a u32, so >= test catches both too large and too small
1360 */
1361 if (jump_offset >= batch_length) {
1362 DRM_DEBUG("CMD: BB_START to 0x%llx jumps out of BB\n",
1363 jump_target);
1364 return -EINVAL;
1365 }
1366
1367 /*
1368 * This cannot overflow a u32 because we already checked jump_offset
1369 * is within the BB, and the batch_length is a u32
1370 */
1371 target_cmd_offset = lower_32_bits(jump_offset);
1372 target_cmd_index = target_cmd_offset / sizeof(u32);
1373
1374 *(u64 *)(cmd + 1) = shadow_addr + target_cmd_offset;
1375
1376 if (target_cmd_index == offset)
1377 return 0;
1378
1379 if (IS_ERR(jump_whitelist))
1380 return PTR_ERR(jump_whitelist);
1381
1382 if (!test_bit(target_cmd_index, jump_whitelist)) {
1383 DRM_DEBUG("CMD: BB_START to 0x%llx not a previously executed cmd\n",
1384 jump_target);
1385 return -EINVAL;
1386 }
1387
1388 return 0;
1389}
1390
1391static unsigned long *alloc_whitelist(u32 batch_length)
1392{
1393 unsigned long *jmp;
1394
1395 /*
1396 * We expect batch_length to be less than 256KiB for known users,
1397 * i.e. we need at most an 8KiB bitmap allocation which should be
1398 * reasonably cheap due to kmalloc caches.
1399 */
1400
1401 /* Prefer to report transient allocation failure rather than hit oom */
1402 jmp = bitmap_zalloc(DIV_ROUND_UP(batch_length, sizeof(u32)),
1403 GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN);
1404 if (!jmp)
1405 return ERR_PTR(-ENOMEM);
1406
1407 return jmp;
1408}
1409
1410#define LENGTH_BIAS 2
1411
1412/**
1413 * intel_engine_cmd_parser() - parse a batch buffer for privilege violations
1414 * @engine: the engine on which the batch is to execute
1415 * @batch: the batch buffer in question
1416 * @batch_offset: byte offset in the batch at which execution starts
1417 * @batch_length: length of the commands in batch_obj
1418 * @shadow: validated copy of the batch buffer in question
1419 * @trampoline: true if we need to trampoline into privileged execution
1420 *
1421 * Parses the specified batch buffer looking for privilege violations as
1422 * described in the overview.
1423 *
1424 * Return: non-zero if the parser finds violations or otherwise fails; -EACCES
1425 * if the batch appears legal but should use hardware parsing
1426 */
1427
1428int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1429 struct i915_vma *batch,
1430 unsigned long batch_offset,
1431 unsigned long batch_length,
1432 struct i915_vma *shadow,
1433 bool trampoline)
1434{
1435 u32 *cmd, *batch_end, offset = 0;
1436 struct drm_i915_cmd_descriptor default_desc = noop_desc;
1437 const struct drm_i915_cmd_descriptor *desc = &default_desc;
1438 bool needs_clflush_after = false;
1439 unsigned long *jump_whitelist;
1440 u64 batch_addr, shadow_addr;
1441 int ret = 0;
1442
1443 GEM_BUG_ON(!IS_ALIGNED(batch_offset, sizeof(*cmd)));
1444 GEM_BUG_ON(!IS_ALIGNED(batch_length, sizeof(*cmd)));
1445 GEM_BUG_ON(range_overflows_t(u64, batch_offset, batch_length,
1446 batch->size));
1447 GEM_BUG_ON(!batch_length);
1448
1449 cmd = copy_batch(shadow->obj, batch->obj,
1450 batch_offset, batch_length,
1451 &needs_clflush_after);
1452 if (IS_ERR(cmd)) {
1453 DRM_DEBUG("CMD: Failed to copy batch\n");
1454 return PTR_ERR(cmd);
1455 }
1456
1457 jump_whitelist = NULL;
1458 if (!trampoline)
1459 /* Defer failure until attempted use */
1460 jump_whitelist = alloc_whitelist(batch_length);
1461
1462 shadow_addr = gen8_canonical_addr(shadow->node.start);
1463 batch_addr = gen8_canonical_addr(batch->node.start + batch_offset);
1464
1465 /*
1466 * We use the batch length as size because the shadow object is as
1467 * large or larger and copy_batch() will write MI_NOPs to the extra
1468 * space. Parsing should be faster in some cases this way.
1469 */
1470 batch_end = cmd + batch_length / sizeof(*batch_end);
1471 while (*cmd != MI_BATCH_BUFFER_END) {
1472 u32 length = 1;
1473
1474 if (*cmd != MI_NOOP) { /* MI_NOOP == 0 */
1475 desc = find_cmd(engine, *cmd, desc, &default_desc);
1476 if (!desc) {
1477 DRM_DEBUG("CMD: Unrecognized command: 0x%08X\n", *cmd);
1478 ret = -EINVAL;
1479 break;
1480 }
1481
1482 if (desc->flags & CMD_DESC_FIXED)
1483 length = desc->length.fixed;
1484 else
1485 length = (*cmd & desc->length.mask) + LENGTH_BIAS;
1486
1487 if ((batch_end - cmd) < length) {
1488 DRM_DEBUG("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n",
1489 *cmd,
1490 length,
1491 batch_end - cmd);
1492 ret = -EINVAL;
1493 break;
1494 }
1495
1496 if (!check_cmd(engine, desc, cmd, length)) {
1497 ret = -EACCES;
1498 break;
1499 }
1500
1501 if (cmd_desc_is(desc, MI_BATCH_BUFFER_START)) {
1502 ret = check_bbstart(cmd, offset, length, batch_length,
1503 batch_addr, shadow_addr,
1504 jump_whitelist);
1505 break;
1506 }
1507 }
1508
1509 if (!IS_ERR_OR_NULL(jump_whitelist))
1510 __set_bit(offset, jump_whitelist);
1511
1512 cmd += length;
1513 offset += length;
1514 if (cmd >= batch_end) {
1515 DRM_DEBUG("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
1516 ret = -EINVAL;
1517 break;
1518 }
1519 }
1520
1521 if (trampoline) {
1522 /*
1523 * With the trampoline, the shadow is executed twice.
1524 *
1525 * 1 - starting at offset 0, in privileged mode
1526 * 2 - starting at offset batch_len, as non-privileged
1527 *
1528 * Only if the batch is valid and safe to execute, do we
1529 * allow the first privileged execution to proceed. If not,
1530 * we terminate the first batch and use the second batchbuffer
1531 * entry to chain to the original unsafe non-privileged batch,
1532 * leaving it to the HW to validate.
1533 */
1534 *batch_end = MI_BATCH_BUFFER_END;
1535
1536 if (ret) {
1537 /* Batch unsafe to execute with privileges, cancel! */
1538 cmd = page_mask_bits(shadow->obj->mm.mapping);
1539 *cmd = MI_BATCH_BUFFER_END;
1540
1541 /* If batch is unsafe but valid, jump to the original */
1542 if (ret == -EACCES) {
1543 unsigned int flags;
1544
1545 flags = MI_BATCH_NON_SECURE_I965;
1546 if (IS_HASWELL(engine->i915))
1547 flags = MI_BATCH_NON_SECURE_HSW;
1548
1549 GEM_BUG_ON(!IS_GRAPHICS_VER(engine->i915, 6, 7));
1550 __gen6_emit_bb_start(batch_end,
1551 batch_addr,
1552 flags);
1553
1554 ret = 0; /* allow execution */
1555 }
1556 }
1557 }
1558
1559 i915_gem_object_flush_map(shadow->obj);
1560
1561 if (!IS_ERR_OR_NULL(jump_whitelist))
1562 kfree(jump_whitelist);
1563 i915_gem_object_unpin_map(shadow->obj);
1564 return ret;
1565}
1566
1567/**
1568 * i915_cmd_parser_get_version() - get the cmd parser version number
1569 * @dev_priv: i915 device private
1570 *
1571 * The cmd parser maintains a simple increasing integer version number suitable
1572 * for passing to userspace clients to determine what operations are permitted.
1573 *
1574 * Return: the current version number of the cmd parser
1575 */
1576int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv)
1577{
1578 struct intel_engine_cs *engine;
1579 bool active = false;
1580
1581 /* If the command parser is not enabled, report 0 - unsupported */
1582 for_each_uabi_engine(engine, dev_priv) {
1583 if (intel_engine_using_cmd_parser(engine)) {
1584 active = true;
1585 break;
1586 }
1587 }
1588 if (!active)
1589 return 0;
1590
1591 /*
1592 * Command parser version history
1593 *
1594 * 1. Initial version. Checks batches and reports violations, but leaves
1595 * hardware parsing enabled (so does not allow new use cases).
1596 * 2. Allow access to the MI_PREDICATE_SRC0 and
1597 * MI_PREDICATE_SRC1 registers.
1598 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
1599 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
1600 * 5. GPGPU dispatch compute indirect registers.
1601 * 6. TIMESTAMP register and Haswell CS GPR registers
1602 * 7. Allow MI_LOAD_REGISTER_REG between whitelisted registers.
1603 * 8. Don't report cmd_check() failures as EINVAL errors to userspace;
1604 * rely on the HW to NOOP disallowed commands as it would without
1605 * the parser enabled.
1606 * 9. Don't whitelist or handle oacontrol specially, as ownership
1607 * for oacontrol state is moving to i915-perf.
1608 * 10. Support for Gen9 BCS Parsing
1609 */
1610 return 10;
1611}