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1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Brad Volkin <bradley.d.volkin@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_ringbuffer.h"
30
31/**
32 * DOC: batch buffer command parser
33 *
34 * Motivation:
35 * Certain OpenGL features (e.g. transform feedback, performance monitoring)
36 * require userspace code to submit batches containing commands such as
37 * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
38 * generations of the hardware will noop these commands in "unsecure" batches
39 * (which includes all userspace batches submitted via i915) even though the
40 * commands may be safe and represent the intended programming model of the
41 * device.
42 *
43 * The software command parser is similar in operation to the command parsing
44 * done in hardware for unsecure batches. However, the software parser allows
45 * some operations that would be noop'd by hardware, if the parser determines
46 * the operation is safe, and submits the batch as "secure" to prevent hardware
47 * parsing.
48 *
49 * Threats:
50 * At a high level, the hardware (and software) checks attempt to prevent
51 * granting userspace undue privileges. There are three categories of privilege.
52 *
53 * First, commands which are explicitly defined as privileged or which should
54 * only be used by the kernel driver. The parser generally rejects such
55 * commands, though it may allow some from the drm master process.
56 *
57 * Second, commands which access registers. To support correct/enhanced
58 * userspace functionality, particularly certain OpenGL extensions, the parser
59 * provides a whitelist of registers which userspace may safely access (for both
60 * normal and drm master processes).
61 *
62 * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc).
63 * The parser always rejects such commands.
64 *
65 * The majority of the problematic commands fall in the MI_* range, with only a
66 * few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW).
67 *
68 * Implementation:
69 * Each engine maintains tables of commands and registers which the parser
70 * uses in scanning batch buffers submitted to that engine.
71 *
72 * Since the set of commands that the parser must check for is significantly
73 * smaller than the number of commands supported, the parser tables contain only
74 * those commands required by the parser. This generally works because command
75 * opcode ranges have standard command length encodings. So for commands that
76 * the parser does not need to check, it can easily skip them. This is
77 * implemented via a per-engine length decoding vfunc.
78 *
79 * Unfortunately, there are a number of commands that do not follow the standard
80 * length encoding for their opcode range, primarily amongst the MI_* commands.
81 * To handle this, the parser provides a way to define explicit "skip" entries
82 * in the per-engine command tables.
83 *
84 * Other command table entries map fairly directly to high level categories
85 * mentioned above: rejected, master-only, register whitelist. The parser
86 * implements a number of checks, including the privileged memory checks, via a
87 * general bitmasking mechanism.
88 */
89
90/*
91 * A command that requires special handling by the command parser.
92 */
93struct drm_i915_cmd_descriptor {
94 /*
95 * Flags describing how the command parser processes the command.
96 *
97 * CMD_DESC_FIXED: The command has a fixed length if this is set,
98 * a length mask if not set
99 * CMD_DESC_SKIP: The command is allowed but does not follow the
100 * standard length encoding for the opcode range in
101 * which it falls
102 * CMD_DESC_REJECT: The command is never allowed
103 * CMD_DESC_REGISTER: The command should be checked against the
104 * register whitelist for the appropriate ring
105 * CMD_DESC_MASTER: The command is allowed if the submitting process
106 * is the DRM master
107 */
108 u32 flags;
109#define CMD_DESC_FIXED (1<<0)
110#define CMD_DESC_SKIP (1<<1)
111#define CMD_DESC_REJECT (1<<2)
112#define CMD_DESC_REGISTER (1<<3)
113#define CMD_DESC_BITMASK (1<<4)
114#define CMD_DESC_MASTER (1<<5)
115
116 /*
117 * The command's unique identification bits and the bitmask to get them.
118 * This isn't strictly the opcode field as defined in the spec and may
119 * also include type, subtype, and/or subop fields.
120 */
121 struct {
122 u32 value;
123 u32 mask;
124 } cmd;
125
126 /*
127 * The command's length. The command is either fixed length (i.e. does
128 * not include a length field) or has a length field mask. The flag
129 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
130 * a length mask. All command entries in a command table must include
131 * length information.
132 */
133 union {
134 u32 fixed;
135 u32 mask;
136 } length;
137
138 /*
139 * Describes where to find a register address in the command to check
140 * against the ring's register whitelist. Only valid if flags has the
141 * CMD_DESC_REGISTER bit set.
142 *
143 * A non-zero step value implies that the command may access multiple
144 * registers in sequence (e.g. LRI), in that case step gives the
145 * distance in dwords between individual offset fields.
146 */
147 struct {
148 u32 offset;
149 u32 mask;
150 u32 step;
151 } reg;
152
153#define MAX_CMD_DESC_BITMASKS 3
154 /*
155 * Describes command checks where a particular dword is masked and
156 * compared against an expected value. If the command does not match
157 * the expected value, the parser rejects it. Only valid if flags has
158 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
159 * are valid.
160 *
161 * If the check specifies a non-zero condition_mask then the parser
162 * only performs the check when the bits specified by condition_mask
163 * are non-zero.
164 */
165 struct {
166 u32 offset;
167 u32 mask;
168 u32 expected;
169 u32 condition_offset;
170 u32 condition_mask;
171 } bits[MAX_CMD_DESC_BITMASKS];
172};
173
174/*
175 * A table of commands requiring special handling by the command parser.
176 *
177 * Each engine has an array of tables. Each table consists of an array of
178 * command descriptors, which must be sorted with command opcodes in
179 * ascending order.
180 */
181struct drm_i915_cmd_table {
182 const struct drm_i915_cmd_descriptor *table;
183 int count;
184};
185
186#define STD_MI_OPCODE_SHIFT (32 - 9)
187#define STD_3D_OPCODE_SHIFT (32 - 16)
188#define STD_2D_OPCODE_SHIFT (32 - 10)
189#define STD_MFX_OPCODE_SHIFT (32 - 16)
190#define MIN_OPCODE_SHIFT 16
191
192#define CMD(op, opm, f, lm, fl, ...) \
193 { \
194 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \
195 .cmd = { (op), ~0u << (opm) }, \
196 .length = { (lm) }, \
197 __VA_ARGS__ \
198 }
199
200/* Convenience macros to compress the tables */
201#define SMI STD_MI_OPCODE_SHIFT
202#define S3D STD_3D_OPCODE_SHIFT
203#define S2D STD_2D_OPCODE_SHIFT
204#define SMFX STD_MFX_OPCODE_SHIFT
205#define F true
206#define S CMD_DESC_SKIP
207#define R CMD_DESC_REJECT
208#define W CMD_DESC_REGISTER
209#define B CMD_DESC_BITMASK
210#define M CMD_DESC_MASTER
211
212/* Command Mask Fixed Len Action
213 ---------------------------------------------------------- */
214static const struct drm_i915_cmd_descriptor common_cmds[] = {
215 CMD( MI_NOOP, SMI, F, 1, S ),
216 CMD( MI_USER_INTERRUPT, SMI, F, 1, R ),
217 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, M ),
218 CMD( MI_ARB_CHECK, SMI, F, 1, S ),
219 CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
220 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
221 CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ),
222 CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
223 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
224 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ),
225 CMD( MI_STORE_REGISTER_MEM, SMI, F, 3, W | B,
226 .reg = { .offset = 1, .mask = 0x007FFFFC },
227 .bits = {{
228 .offset = 0,
229 .mask = MI_GLOBAL_GTT,
230 .expected = 0,
231 }}, ),
232 CMD( MI_LOAD_REGISTER_MEM, SMI, F, 3, W | B,
233 .reg = { .offset = 1, .mask = 0x007FFFFC },
234 .bits = {{
235 .offset = 0,
236 .mask = MI_GLOBAL_GTT,
237 .expected = 0,
238 }}, ),
239 /*
240 * MI_BATCH_BUFFER_START requires some special handling. It's not
241 * really a 'skip' action but it doesn't seem like it's worth adding
242 * a new action. See i915_parse_cmds().
243 */
244 CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
245};
246
247static const struct drm_i915_cmd_descriptor render_cmds[] = {
248 CMD( MI_FLUSH, SMI, F, 1, S ),
249 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
250 CMD( MI_PREDICATE, SMI, F, 1, S ),
251 CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ),
252 CMD( MI_SET_APPID, SMI, F, 1, S ),
253 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
254 CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ),
255 CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ),
256 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B,
257 .bits = {{
258 .offset = 0,
259 .mask = MI_GLOBAL_GTT,
260 .expected = 0,
261 }}, ),
262 CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ),
263 CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B,
264 .bits = {{
265 .offset = 0,
266 .mask = MI_GLOBAL_GTT,
267 .expected = 0,
268 }}, ),
269 CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B,
270 .bits = {{
271 .offset = 1,
272 .mask = MI_REPORT_PERF_COUNT_GGTT,
273 .expected = 0,
274 }}, ),
275 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
276 .bits = {{
277 .offset = 0,
278 .mask = MI_GLOBAL_GTT,
279 .expected = 0,
280 }}, ),
281 CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ),
282 CMD( PIPELINE_SELECT, S3D, F, 1, S ),
283 CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B,
284 .bits = {{
285 .offset = 2,
286 .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
287 .expected = 0,
288 }}, ),
289 CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ),
290 CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ),
291 CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ),
292 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B,
293 .bits = {{
294 .offset = 1,
295 .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),
296 .expected = 0,
297 },
298 {
299 .offset = 1,
300 .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB |
301 PIPE_CONTROL_STORE_DATA_INDEX),
302 .expected = 0,
303 .condition_offset = 1,
304 .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK,
305 }}, ),
306};
307
308static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
309 CMD( MI_SET_PREDICATE, SMI, F, 1, S ),
310 CMD( MI_RS_CONTROL, SMI, F, 1, S ),
311 CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ),
312 CMD( MI_SET_APPID, SMI, F, 1, S ),
313 CMD( MI_RS_CONTEXT, SMI, F, 1, S ),
314 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ),
315 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
316 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W,
317 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ),
318 CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ),
319 CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ),
320 CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ),
321 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ),
322 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ),
323
324 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ),
325 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ),
326 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ),
327 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ),
328 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ),
329};
330
331static const struct drm_i915_cmd_descriptor video_cmds[] = {
332 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
333 CMD( MI_SET_APPID, SMI, F, 1, S ),
334 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
335 .bits = {{
336 .offset = 0,
337 .mask = MI_GLOBAL_GTT,
338 .expected = 0,
339 }}, ),
340 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
341 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
342 .bits = {{
343 .offset = 0,
344 .mask = MI_FLUSH_DW_NOTIFY,
345 .expected = 0,
346 },
347 {
348 .offset = 1,
349 .mask = MI_FLUSH_DW_USE_GTT,
350 .expected = 0,
351 .condition_offset = 0,
352 .condition_mask = MI_FLUSH_DW_OP_MASK,
353 },
354 {
355 .offset = 0,
356 .mask = MI_FLUSH_DW_STORE_INDEX,
357 .expected = 0,
358 .condition_offset = 0,
359 .condition_mask = MI_FLUSH_DW_OP_MASK,
360 }}, ),
361 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
362 .bits = {{
363 .offset = 0,
364 .mask = MI_GLOBAL_GTT,
365 .expected = 0,
366 }}, ),
367 /*
368 * MFX_WAIT doesn't fit the way we handle length for most commands.
369 * It has a length field but it uses a non-standard length bias.
370 * It is always 1 dword though, so just treat it as fixed length.
371 */
372 CMD( MFX_WAIT, SMFX, F, 1, S ),
373};
374
375static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
376 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
377 CMD( MI_SET_APPID, SMI, F, 1, S ),
378 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
379 .bits = {{
380 .offset = 0,
381 .mask = MI_GLOBAL_GTT,
382 .expected = 0,
383 }}, ),
384 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
385 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
386 .bits = {{
387 .offset = 0,
388 .mask = MI_FLUSH_DW_NOTIFY,
389 .expected = 0,
390 },
391 {
392 .offset = 1,
393 .mask = MI_FLUSH_DW_USE_GTT,
394 .expected = 0,
395 .condition_offset = 0,
396 .condition_mask = MI_FLUSH_DW_OP_MASK,
397 },
398 {
399 .offset = 0,
400 .mask = MI_FLUSH_DW_STORE_INDEX,
401 .expected = 0,
402 .condition_offset = 0,
403 .condition_mask = MI_FLUSH_DW_OP_MASK,
404 }}, ),
405 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B,
406 .bits = {{
407 .offset = 0,
408 .mask = MI_GLOBAL_GTT,
409 .expected = 0,
410 }}, ),
411};
412
413static const struct drm_i915_cmd_descriptor blt_cmds[] = {
414 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
415 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B,
416 .bits = {{
417 .offset = 0,
418 .mask = MI_GLOBAL_GTT,
419 .expected = 0,
420 }}, ),
421 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ),
422 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B,
423 .bits = {{
424 .offset = 0,
425 .mask = MI_FLUSH_DW_NOTIFY,
426 .expected = 0,
427 },
428 {
429 .offset = 1,
430 .mask = MI_FLUSH_DW_USE_GTT,
431 .expected = 0,
432 .condition_offset = 0,
433 .condition_mask = MI_FLUSH_DW_OP_MASK,
434 },
435 {
436 .offset = 0,
437 .mask = MI_FLUSH_DW_STORE_INDEX,
438 .expected = 0,
439 .condition_offset = 0,
440 .condition_mask = MI_FLUSH_DW_OP_MASK,
441 }}, ),
442 CMD( COLOR_BLT, S2D, !F, 0x3F, S ),
443 CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ),
444};
445
446static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = {
447 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ),
448 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ),
449};
450
451static const struct drm_i915_cmd_descriptor noop_desc =
452 CMD(MI_NOOP, SMI, F, 1, S);
453
454#undef CMD
455#undef SMI
456#undef S3D
457#undef S2D
458#undef SMFX
459#undef F
460#undef S
461#undef R
462#undef W
463#undef B
464#undef M
465
466static const struct drm_i915_cmd_table gen7_render_cmds[] = {
467 { common_cmds, ARRAY_SIZE(common_cmds) },
468 { render_cmds, ARRAY_SIZE(render_cmds) },
469};
470
471static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = {
472 { common_cmds, ARRAY_SIZE(common_cmds) },
473 { render_cmds, ARRAY_SIZE(render_cmds) },
474 { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) },
475};
476
477static const struct drm_i915_cmd_table gen7_video_cmds[] = {
478 { common_cmds, ARRAY_SIZE(common_cmds) },
479 { video_cmds, ARRAY_SIZE(video_cmds) },
480};
481
482static const struct drm_i915_cmd_table hsw_vebox_cmds[] = {
483 { common_cmds, ARRAY_SIZE(common_cmds) },
484 { vecs_cmds, ARRAY_SIZE(vecs_cmds) },
485};
486
487static const struct drm_i915_cmd_table gen7_blt_cmds[] = {
488 { common_cmds, ARRAY_SIZE(common_cmds) },
489 { blt_cmds, ARRAY_SIZE(blt_cmds) },
490};
491
492static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = {
493 { common_cmds, ARRAY_SIZE(common_cmds) },
494 { blt_cmds, ARRAY_SIZE(blt_cmds) },
495 { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
496};
497
498/*
499 * Register whitelists, sorted by increasing register offset.
500 */
501
502/*
503 * An individual whitelist entry granting access to register addr. If
504 * mask is non-zero the argument of immediate register writes will be
505 * AND-ed with mask, and the command will be rejected if the result
506 * doesn't match value.
507 *
508 * Registers with non-zero mask are only allowed to be written using
509 * LRI.
510 */
511struct drm_i915_reg_descriptor {
512 i915_reg_t addr;
513 u32 mask;
514 u32 value;
515};
516
517/* Convenience macro for adding 32-bit registers. */
518#define REG32(_reg, ...) \
519 { .addr = (_reg), __VA_ARGS__ }
520
521/*
522 * Convenience macro for adding 64-bit registers.
523 *
524 * Some registers that userspace accesses are 64 bits. The register
525 * access commands only allow 32-bit accesses. Hence, we have to include
526 * entries for both halves of the 64-bit registers.
527 */
528#define REG64(_reg) \
529 { .addr = _reg }, \
530 { .addr = _reg ## _UDW }
531
532#define REG64_IDX(_reg, idx) \
533 { .addr = _reg(idx) }, \
534 { .addr = _reg ## _UDW(idx) }
535
536static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
537 REG64(GPGPU_THREADS_DISPATCHED),
538 REG64(HS_INVOCATION_COUNT),
539 REG64(DS_INVOCATION_COUNT),
540 REG64(IA_VERTICES_COUNT),
541 REG64(IA_PRIMITIVES_COUNT),
542 REG64(VS_INVOCATION_COUNT),
543 REG64(GS_INVOCATION_COUNT),
544 REG64(GS_PRIMITIVES_COUNT),
545 REG64(CL_INVOCATION_COUNT),
546 REG64(CL_PRIMITIVES_COUNT),
547 REG64(PS_INVOCATION_COUNT),
548 REG64(PS_DEPTH_COUNT),
549 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
550 REG64(MI_PREDICATE_SRC0),
551 REG64(MI_PREDICATE_SRC1),
552 REG32(GEN7_3DPRIM_END_OFFSET),
553 REG32(GEN7_3DPRIM_START_VERTEX),
554 REG32(GEN7_3DPRIM_VERTEX_COUNT),
555 REG32(GEN7_3DPRIM_INSTANCE_COUNT),
556 REG32(GEN7_3DPRIM_START_INSTANCE),
557 REG32(GEN7_3DPRIM_BASE_VERTEX),
558 REG32(GEN7_GPGPU_DISPATCHDIMX),
559 REG32(GEN7_GPGPU_DISPATCHDIMY),
560 REG32(GEN7_GPGPU_DISPATCHDIMZ),
561 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
562 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0),
563 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1),
564 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2),
565 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 3),
566 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 0),
567 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 1),
568 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 2),
569 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 3),
570 REG32(GEN7_SO_WRITE_OFFSET(0)),
571 REG32(GEN7_SO_WRITE_OFFSET(1)),
572 REG32(GEN7_SO_WRITE_OFFSET(2)),
573 REG32(GEN7_SO_WRITE_OFFSET(3)),
574 REG32(GEN7_L3SQCREG1),
575 REG32(GEN7_L3CNTLREG2),
576 REG32(GEN7_L3CNTLREG3),
577 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
578};
579
580static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
581 REG64_IDX(HSW_CS_GPR, 0),
582 REG64_IDX(HSW_CS_GPR, 1),
583 REG64_IDX(HSW_CS_GPR, 2),
584 REG64_IDX(HSW_CS_GPR, 3),
585 REG64_IDX(HSW_CS_GPR, 4),
586 REG64_IDX(HSW_CS_GPR, 5),
587 REG64_IDX(HSW_CS_GPR, 6),
588 REG64_IDX(HSW_CS_GPR, 7),
589 REG64_IDX(HSW_CS_GPR, 8),
590 REG64_IDX(HSW_CS_GPR, 9),
591 REG64_IDX(HSW_CS_GPR, 10),
592 REG64_IDX(HSW_CS_GPR, 11),
593 REG64_IDX(HSW_CS_GPR, 12),
594 REG64_IDX(HSW_CS_GPR, 13),
595 REG64_IDX(HSW_CS_GPR, 14),
596 REG64_IDX(HSW_CS_GPR, 15),
597 REG32(HSW_SCRATCH1,
598 .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
599 .value = 0),
600 REG32(HSW_ROW_CHICKEN3,
601 .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 |
602 HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
603 .value = 0),
604};
605
606static const struct drm_i915_reg_descriptor gen7_blt_regs[] = {
607 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
608 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE),
609 REG32(BCS_SWCTRL),
610 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
611};
612
613static const struct drm_i915_reg_descriptor ivb_master_regs[] = {
614 REG32(FORCEWAKE_MT),
615 REG32(DERRMR),
616 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)),
617 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_B)),
618 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_C)),
619};
620
621static const struct drm_i915_reg_descriptor hsw_master_regs[] = {
622 REG32(FORCEWAKE_MT),
623 REG32(DERRMR),
624};
625
626#undef REG64
627#undef REG32
628
629struct drm_i915_reg_table {
630 const struct drm_i915_reg_descriptor *regs;
631 int num_regs;
632 bool master;
633};
634
635static const struct drm_i915_reg_table ivb_render_reg_tables[] = {
636 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },
637 { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true },
638};
639
640static const struct drm_i915_reg_table ivb_blt_reg_tables[] = {
641 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false },
642 { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true },
643};
644
645static const struct drm_i915_reg_table hsw_render_reg_tables[] = {
646 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },
647 { hsw_render_regs, ARRAY_SIZE(hsw_render_regs), false },
648 { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },
649};
650
651static const struct drm_i915_reg_table hsw_blt_reg_tables[] = {
652 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false },
653 { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },
654};
655
656static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
657{
658 u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
659 u32 subclient =
660 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
661
662 if (client == INSTR_MI_CLIENT)
663 return 0x3F;
664 else if (client == INSTR_RC_CLIENT) {
665 if (subclient == INSTR_MEDIA_SUBCLIENT)
666 return 0xFFFF;
667 else
668 return 0xFF;
669 }
670
671 DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header);
672 return 0;
673}
674
675static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)
676{
677 u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
678 u32 subclient =
679 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
680 u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT;
681
682 if (client == INSTR_MI_CLIENT)
683 return 0x3F;
684 else if (client == INSTR_RC_CLIENT) {
685 if (subclient == INSTR_MEDIA_SUBCLIENT) {
686 if (op == 6)
687 return 0xFFFF;
688 else
689 return 0xFFF;
690 } else
691 return 0xFF;
692 }
693
694 DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header);
695 return 0;
696}
697
698static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
699{
700 u32 client = cmd_header >> INSTR_CLIENT_SHIFT;
701
702 if (client == INSTR_MI_CLIENT)
703 return 0x3F;
704 else if (client == INSTR_BC_CLIENT)
705 return 0xFF;
706
707 DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
708 return 0;
709}
710
711static bool validate_cmds_sorted(const struct intel_engine_cs *engine,
712 const struct drm_i915_cmd_table *cmd_tables,
713 int cmd_table_count)
714{
715 int i;
716 bool ret = true;
717
718 if (!cmd_tables || cmd_table_count == 0)
719 return true;
720
721 for (i = 0; i < cmd_table_count; i++) {
722 const struct drm_i915_cmd_table *table = &cmd_tables[i];
723 u32 previous = 0;
724 int j;
725
726 for (j = 0; j < table->count; j++) {
727 const struct drm_i915_cmd_descriptor *desc =
728 &table->table[j];
729 u32 curr = desc->cmd.value & desc->cmd.mask;
730
731 if (curr < previous) {
732 DRM_ERROR("CMD: %s [%d] command table not sorted: "
733 "table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
734 engine->name, engine->id,
735 i, j, curr, previous);
736 ret = false;
737 }
738
739 previous = curr;
740 }
741 }
742
743 return ret;
744}
745
746static bool check_sorted(const struct intel_engine_cs *engine,
747 const struct drm_i915_reg_descriptor *reg_table,
748 int reg_count)
749{
750 int i;
751 u32 previous = 0;
752 bool ret = true;
753
754 for (i = 0; i < reg_count; i++) {
755 u32 curr = i915_mmio_reg_offset(reg_table[i].addr);
756
757 if (curr < previous) {
758 DRM_ERROR("CMD: %s [%d] register table not sorted: "
759 "entry=%d reg=0x%08X prev=0x%08X\n",
760 engine->name, engine->id,
761 i, curr, previous);
762 ret = false;
763 }
764
765 previous = curr;
766 }
767
768 return ret;
769}
770
771static bool validate_regs_sorted(struct intel_engine_cs *engine)
772{
773 int i;
774 const struct drm_i915_reg_table *table;
775
776 for (i = 0; i < engine->reg_table_count; i++) {
777 table = &engine->reg_tables[i];
778 if (!check_sorted(engine, table->regs, table->num_regs))
779 return false;
780 }
781
782 return true;
783}
784
785struct cmd_node {
786 const struct drm_i915_cmd_descriptor *desc;
787 struct hlist_node node;
788};
789
790/*
791 * Different command ranges have different numbers of bits for the opcode. For
792 * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The
793 * problem is that, for example, MI commands use bits 22:16 for other fields
794 * such as GGTT vs PPGTT bits. If we include those bits in the mask then when
795 * we mask a command from a batch it could hash to the wrong bucket due to
796 * non-opcode bits being set. But if we don't include those bits, some 3D
797 * commands may hash to the same bucket due to not including opcode bits that
798 * make the command unique. For now, we will risk hashing to the same bucket.
799 */
800static inline u32 cmd_header_key(u32 x)
801{
802 switch (x >> INSTR_CLIENT_SHIFT) {
803 default:
804 case INSTR_MI_CLIENT:
805 return x >> STD_MI_OPCODE_SHIFT;
806 case INSTR_RC_CLIENT:
807 return x >> STD_3D_OPCODE_SHIFT;
808 case INSTR_BC_CLIENT:
809 return x >> STD_2D_OPCODE_SHIFT;
810 }
811}
812
813static int init_hash_table(struct intel_engine_cs *engine,
814 const struct drm_i915_cmd_table *cmd_tables,
815 int cmd_table_count)
816{
817 int i, j;
818
819 hash_init(engine->cmd_hash);
820
821 for (i = 0; i < cmd_table_count; i++) {
822 const struct drm_i915_cmd_table *table = &cmd_tables[i];
823
824 for (j = 0; j < table->count; j++) {
825 const struct drm_i915_cmd_descriptor *desc =
826 &table->table[j];
827 struct cmd_node *desc_node =
828 kmalloc(sizeof(*desc_node), GFP_KERNEL);
829
830 if (!desc_node)
831 return -ENOMEM;
832
833 desc_node->desc = desc;
834 hash_add(engine->cmd_hash, &desc_node->node,
835 cmd_header_key(desc->cmd.value));
836 }
837 }
838
839 return 0;
840}
841
842static void fini_hash_table(struct intel_engine_cs *engine)
843{
844 struct hlist_node *tmp;
845 struct cmd_node *desc_node;
846 int i;
847
848 hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) {
849 hash_del(&desc_node->node);
850 kfree(desc_node);
851 }
852}
853
854/**
855 * intel_engine_init_cmd_parser() - set cmd parser related fields for an engine
856 * @engine: the engine to initialize
857 *
858 * Optionally initializes fields related to batch buffer command parsing in the
859 * struct intel_engine_cs based on whether the platform requires software
860 * command parsing.
861 */
862void intel_engine_init_cmd_parser(struct intel_engine_cs *engine)
863{
864 const struct drm_i915_cmd_table *cmd_tables;
865 int cmd_table_count;
866 int ret;
867
868 if (!IS_GEN7(engine->i915))
869 return;
870
871 switch (engine->id) {
872 case RCS:
873 if (IS_HASWELL(engine->i915)) {
874 cmd_tables = hsw_render_ring_cmds;
875 cmd_table_count =
876 ARRAY_SIZE(hsw_render_ring_cmds);
877 } else {
878 cmd_tables = gen7_render_cmds;
879 cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
880 }
881
882 if (IS_HASWELL(engine->i915)) {
883 engine->reg_tables = hsw_render_reg_tables;
884 engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables);
885 } else {
886 engine->reg_tables = ivb_render_reg_tables;
887 engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables);
888 }
889
890 engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
891 break;
892 case VCS:
893 cmd_tables = gen7_video_cmds;
894 cmd_table_count = ARRAY_SIZE(gen7_video_cmds);
895 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
896 break;
897 case BCS:
898 if (IS_HASWELL(engine->i915)) {
899 cmd_tables = hsw_blt_ring_cmds;
900 cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);
901 } else {
902 cmd_tables = gen7_blt_cmds;
903 cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
904 }
905
906 if (IS_HASWELL(engine->i915)) {
907 engine->reg_tables = hsw_blt_reg_tables;
908 engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables);
909 } else {
910 engine->reg_tables = ivb_blt_reg_tables;
911 engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables);
912 }
913
914 engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
915 break;
916 case VECS:
917 cmd_tables = hsw_vebox_cmds;
918 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds);
919 /* VECS can use the same length_mask function as VCS */
920 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
921 break;
922 default:
923 MISSING_CASE(engine->id);
924 return;
925 }
926
927 if (!validate_cmds_sorted(engine, cmd_tables, cmd_table_count)) {
928 DRM_ERROR("%s: command descriptions are not sorted\n",
929 engine->name);
930 return;
931 }
932 if (!validate_regs_sorted(engine)) {
933 DRM_ERROR("%s: registers are not sorted\n", engine->name);
934 return;
935 }
936
937 ret = init_hash_table(engine, cmd_tables, cmd_table_count);
938 if (ret) {
939 DRM_ERROR("%s: initialised failed!\n", engine->name);
940 fini_hash_table(engine);
941 return;
942 }
943
944 engine->flags |= I915_ENGINE_NEEDS_CMD_PARSER;
945}
946
947/**
948 * intel_engine_cleanup_cmd_parser() - clean up cmd parser related fields
949 * @engine: the engine to clean up
950 *
951 * Releases any resources related to command parsing that may have been
952 * initialized for the specified engine.
953 */
954void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine)
955{
956 if (!intel_engine_needs_cmd_parser(engine))
957 return;
958
959 fini_hash_table(engine);
960}
961
962static const struct drm_i915_cmd_descriptor*
963find_cmd_in_table(struct intel_engine_cs *engine,
964 u32 cmd_header)
965{
966 struct cmd_node *desc_node;
967
968 hash_for_each_possible(engine->cmd_hash, desc_node, node,
969 cmd_header_key(cmd_header)) {
970 const struct drm_i915_cmd_descriptor *desc = desc_node->desc;
971 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0)
972 return desc;
973 }
974
975 return NULL;
976}
977
978/*
979 * Returns a pointer to a descriptor for the command specified by cmd_header.
980 *
981 * The caller must supply space for a default descriptor via the default_desc
982 * parameter. If no descriptor for the specified command exists in the engine's
983 * command parser tables, this function fills in default_desc based on the
984 * engine's default length encoding and returns default_desc.
985 */
986static const struct drm_i915_cmd_descriptor*
987find_cmd(struct intel_engine_cs *engine,
988 u32 cmd_header,
989 const struct drm_i915_cmd_descriptor *desc,
990 struct drm_i915_cmd_descriptor *default_desc)
991{
992 u32 mask;
993
994 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0)
995 return desc;
996
997 desc = find_cmd_in_table(engine, cmd_header);
998 if (desc)
999 return desc;
1000
1001 mask = engine->get_cmd_length_mask(cmd_header);
1002 if (!mask)
1003 return NULL;
1004
1005 default_desc->cmd.value = cmd_header;
1006 default_desc->cmd.mask = ~0u << MIN_OPCODE_SHIFT;
1007 default_desc->length.mask = mask;
1008 default_desc->flags = CMD_DESC_SKIP;
1009 return default_desc;
1010}
1011
1012static const struct drm_i915_reg_descriptor *
1013__find_reg(const struct drm_i915_reg_descriptor *table, int count, u32 addr)
1014{
1015 int start = 0, end = count;
1016 while (start < end) {
1017 int mid = start + (end - start) / 2;
1018 int ret = addr - i915_mmio_reg_offset(table[mid].addr);
1019 if (ret < 0)
1020 end = mid;
1021 else if (ret > 0)
1022 start = mid + 1;
1023 else
1024 return &table[mid];
1025 }
1026 return NULL;
1027}
1028
1029static const struct drm_i915_reg_descriptor *
1030find_reg(const struct intel_engine_cs *engine, bool is_master, u32 addr)
1031{
1032 const struct drm_i915_reg_table *table = engine->reg_tables;
1033 int count = engine->reg_table_count;
1034
1035 for (; count > 0; ++table, --count) {
1036 if (!table->master || is_master) {
1037 const struct drm_i915_reg_descriptor *reg;
1038
1039 reg = __find_reg(table->regs, table->num_regs, addr);
1040 if (reg != NULL)
1041 return reg;
1042 }
1043 }
1044
1045 return NULL;
1046}
1047
1048/* Returns a vmap'd pointer to dst_obj, which the caller must unmap */
1049static u32 *copy_batch(struct drm_i915_gem_object *dst_obj,
1050 struct drm_i915_gem_object *src_obj,
1051 u32 batch_start_offset,
1052 u32 batch_len,
1053 bool *needs_clflush_after)
1054{
1055 unsigned int src_needs_clflush;
1056 unsigned int dst_needs_clflush;
1057 void *dst, *src;
1058 int ret;
1059
1060 ret = i915_gem_obj_prepare_shmem_read(src_obj, &src_needs_clflush);
1061 if (ret)
1062 return ERR_PTR(ret);
1063
1064 ret = i915_gem_obj_prepare_shmem_write(dst_obj, &dst_needs_clflush);
1065 if (ret) {
1066 dst = ERR_PTR(ret);
1067 goto unpin_src;
1068 }
1069
1070 dst = i915_gem_object_pin_map(dst_obj, I915_MAP_FORCE_WB);
1071 if (IS_ERR(dst))
1072 goto unpin_dst;
1073
1074 src = ERR_PTR(-ENODEV);
1075 if (src_needs_clflush &&
1076 i915_can_memcpy_from_wc(NULL, batch_start_offset, 0)) {
1077 src = i915_gem_object_pin_map(src_obj, I915_MAP_WC);
1078 if (!IS_ERR(src)) {
1079 i915_memcpy_from_wc(dst,
1080 src + batch_start_offset,
1081 ALIGN(batch_len, 16));
1082 i915_gem_object_unpin_map(src_obj);
1083 }
1084 }
1085 if (IS_ERR(src)) {
1086 void *ptr;
1087 int offset, n;
1088
1089 offset = offset_in_page(batch_start_offset);
1090
1091 /* We can avoid clflushing partial cachelines before the write
1092 * if we only every write full cache-lines. Since we know that
1093 * both the source and destination are in multiples of
1094 * PAGE_SIZE, we can simply round up to the next cacheline.
1095 * We don't care about copying too much here as we only
1096 * validate up to the end of the batch.
1097 */
1098 if (dst_needs_clflush & CLFLUSH_BEFORE)
1099 batch_len = roundup(batch_len,
1100 boot_cpu_data.x86_clflush_size);
1101
1102 ptr = dst;
1103 for (n = batch_start_offset >> PAGE_SHIFT; batch_len; n++) {
1104 int len = min_t(int, batch_len, PAGE_SIZE - offset);
1105
1106 src = kmap_atomic(i915_gem_object_get_page(src_obj, n));
1107 if (src_needs_clflush)
1108 drm_clflush_virt_range(src + offset, len);
1109 memcpy(ptr, src + offset, len);
1110 kunmap_atomic(src);
1111
1112 ptr += len;
1113 batch_len -= len;
1114 offset = 0;
1115 }
1116 }
1117
1118 /* dst_obj is returned with vmap pinned */
1119 *needs_clflush_after = dst_needs_clflush & CLFLUSH_AFTER;
1120
1121unpin_dst:
1122 i915_gem_obj_finish_shmem_access(dst_obj);
1123unpin_src:
1124 i915_gem_obj_finish_shmem_access(src_obj);
1125 return dst;
1126}
1127
1128static bool check_cmd(const struct intel_engine_cs *engine,
1129 const struct drm_i915_cmd_descriptor *desc,
1130 const u32 *cmd, u32 length,
1131 const bool is_master)
1132{
1133 if (desc->flags & CMD_DESC_SKIP)
1134 return true;
1135
1136 if (desc->flags & CMD_DESC_REJECT) {
1137 DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd);
1138 return false;
1139 }
1140
1141 if ((desc->flags & CMD_DESC_MASTER) && !is_master) {
1142 DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n",
1143 *cmd);
1144 return false;
1145 }
1146
1147 if (desc->flags & CMD_DESC_REGISTER) {
1148 /*
1149 * Get the distance between individual register offset
1150 * fields if the command can perform more than one
1151 * access at a time.
1152 */
1153 const u32 step = desc->reg.step ? desc->reg.step : length;
1154 u32 offset;
1155
1156 for (offset = desc->reg.offset; offset < length;
1157 offset += step) {
1158 const u32 reg_addr = cmd[offset] & desc->reg.mask;
1159 const struct drm_i915_reg_descriptor *reg =
1160 find_reg(engine, is_master, reg_addr);
1161
1162 if (!reg) {
1163 DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (%s)\n",
1164 reg_addr, *cmd, engine->name);
1165 return false;
1166 }
1167
1168 /*
1169 * Check the value written to the register against the
1170 * allowed mask/value pair given in the whitelist entry.
1171 */
1172 if (reg->mask) {
1173 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
1174 DRM_DEBUG_DRIVER("CMD: Rejected LRM to masked register 0x%08X\n",
1175 reg_addr);
1176 return false;
1177 }
1178
1179 if (desc->cmd.value == MI_LOAD_REGISTER_REG) {
1180 DRM_DEBUG_DRIVER("CMD: Rejected LRR to masked register 0x%08X\n",
1181 reg_addr);
1182 return false;
1183 }
1184
1185 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) &&
1186 (offset + 2 > length ||
1187 (cmd[offset + 1] & reg->mask) != reg->value)) {
1188 DRM_DEBUG_DRIVER("CMD: Rejected LRI to masked register 0x%08X\n",
1189 reg_addr);
1190 return false;
1191 }
1192 }
1193 }
1194 }
1195
1196 if (desc->flags & CMD_DESC_BITMASK) {
1197 int i;
1198
1199 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) {
1200 u32 dword;
1201
1202 if (desc->bits[i].mask == 0)
1203 break;
1204
1205 if (desc->bits[i].condition_mask != 0) {
1206 u32 offset =
1207 desc->bits[i].condition_offset;
1208 u32 condition = cmd[offset] &
1209 desc->bits[i].condition_mask;
1210
1211 if (condition == 0)
1212 continue;
1213 }
1214
1215 if (desc->bits[i].offset >= length) {
1216 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X, too short to check bitmask (%s)\n",
1217 *cmd, engine->name);
1218 return false;
1219 }
1220
1221 dword = cmd[desc->bits[i].offset] &
1222 desc->bits[i].mask;
1223
1224 if (dword != desc->bits[i].expected) {
1225 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (%s)\n",
1226 *cmd,
1227 desc->bits[i].mask,
1228 desc->bits[i].expected,
1229 dword, engine->name);
1230 return false;
1231 }
1232 }
1233 }
1234
1235 return true;
1236}
1237
1238#define LENGTH_BIAS 2
1239
1240/**
1241 * i915_parse_cmds() - parse a submitted batch buffer for privilege violations
1242 * @engine: the engine on which the batch is to execute
1243 * @batch_obj: the batch buffer in question
1244 * @shadow_batch_obj: copy of the batch buffer in question
1245 * @batch_start_offset: byte offset in the batch at which execution starts
1246 * @batch_len: length of the commands in batch_obj
1247 * @is_master: is the submitting process the drm master?
1248 *
1249 * Parses the specified batch buffer looking for privilege violations as
1250 * described in the overview.
1251 *
1252 * Return: non-zero if the parser finds violations or otherwise fails; -EACCES
1253 * if the batch appears legal but should use hardware parsing
1254 */
1255int intel_engine_cmd_parser(struct intel_engine_cs *engine,
1256 struct drm_i915_gem_object *batch_obj,
1257 struct drm_i915_gem_object *shadow_batch_obj,
1258 u32 batch_start_offset,
1259 u32 batch_len,
1260 bool is_master)
1261{
1262 u32 *cmd, *batch_end;
1263 struct drm_i915_cmd_descriptor default_desc = noop_desc;
1264 const struct drm_i915_cmd_descriptor *desc = &default_desc;
1265 bool needs_clflush_after = false;
1266 int ret = 0;
1267
1268 cmd = copy_batch(shadow_batch_obj, batch_obj,
1269 batch_start_offset, batch_len,
1270 &needs_clflush_after);
1271 if (IS_ERR(cmd)) {
1272 DRM_DEBUG_DRIVER("CMD: Failed to copy batch\n");
1273 return PTR_ERR(cmd);
1274 }
1275
1276 /*
1277 * We use the batch length as size because the shadow object is as
1278 * large or larger and copy_batch() will write MI_NOPs to the extra
1279 * space. Parsing should be faster in some cases this way.
1280 */
1281 batch_end = cmd + (batch_len / sizeof(*batch_end));
1282 do {
1283 u32 length;
1284
1285 if (*cmd == MI_BATCH_BUFFER_END) {
1286 if (needs_clflush_after) {
1287 void *ptr = page_mask_bits(shadow_batch_obj->mm.mapping);
1288 drm_clflush_virt_range(ptr,
1289 (void *)(cmd + 1) - ptr);
1290 }
1291 break;
1292 }
1293
1294 desc = find_cmd(engine, *cmd, desc, &default_desc);
1295 if (!desc) {
1296 DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n",
1297 *cmd);
1298 ret = -EINVAL;
1299 break;
1300 }
1301
1302 /*
1303 * If the batch buffer contains a chained batch, return an
1304 * error that tells the caller to abort and dispatch the
1305 * workload as a non-secure batch.
1306 */
1307 if (desc->cmd.value == MI_BATCH_BUFFER_START) {
1308 ret = -EACCES;
1309 break;
1310 }
1311
1312 if (desc->flags & CMD_DESC_FIXED)
1313 length = desc->length.fixed;
1314 else
1315 length = ((*cmd & desc->length.mask) + LENGTH_BIAS);
1316
1317 if ((batch_end - cmd) < length) {
1318 DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n",
1319 *cmd,
1320 length,
1321 batch_end - cmd);
1322 ret = -EINVAL;
1323 break;
1324 }
1325
1326 if (!check_cmd(engine, desc, cmd, length, is_master)) {
1327 ret = -EACCES;
1328 break;
1329 }
1330
1331 cmd += length;
1332 if (cmd >= batch_end) {
1333 DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
1334 ret = -EINVAL;
1335 break;
1336 }
1337 } while (1);
1338
1339 i915_gem_object_unpin_map(shadow_batch_obj);
1340 return ret;
1341}
1342
1343/**
1344 * i915_cmd_parser_get_version() - get the cmd parser version number
1345 * @dev_priv: i915 device private
1346 *
1347 * The cmd parser maintains a simple increasing integer version number suitable
1348 * for passing to userspace clients to determine what operations are permitted.
1349 *
1350 * Return: the current version number of the cmd parser
1351 */
1352int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv)
1353{
1354 struct intel_engine_cs *engine;
1355 enum intel_engine_id id;
1356 bool active = false;
1357
1358 /* If the command parser is not enabled, report 0 - unsupported */
1359 for_each_engine(engine, dev_priv, id) {
1360 if (intel_engine_needs_cmd_parser(engine)) {
1361 active = true;
1362 break;
1363 }
1364 }
1365 if (!active)
1366 return 0;
1367
1368 /*
1369 * Command parser version history
1370 *
1371 * 1. Initial version. Checks batches and reports violations, but leaves
1372 * hardware parsing enabled (so does not allow new use cases).
1373 * 2. Allow access to the MI_PREDICATE_SRC0 and
1374 * MI_PREDICATE_SRC1 registers.
1375 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
1376 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
1377 * 5. GPGPU dispatch compute indirect registers.
1378 * 6. TIMESTAMP register and Haswell CS GPR registers
1379 * 7. Allow MI_LOAD_REGISTER_REG between whitelisted registers.
1380 * 8. Don't report cmd_check() failures as EINVAL errors to userspace;
1381 * rely on the HW to NOOP disallowed commands as it would without
1382 * the parser enabled.
1383 * 9. Don't whitelist or handle oacontrol specially, as ownership
1384 * for oacontrol state is moving to i915-perf.
1385 */
1386 return 9;
1387}