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1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
29#include <drm/drm_fixed.h>
30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
47 args.ucCRTC = radeon_crtc->crtc_id;
48
49 switch (radeon_crtc->rmx_type) {
50 case RMX_CENTER:
51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
55 break;
56 case RMX_ASPECT:
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60 if (a1 > a2) {
61 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
62 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
63 } else if (a2 > a1) {
64 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
65 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
66 }
67 break;
68 case RMX_FULL:
69 default:
70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
74 break;
75 }
76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
77}
78
79static void atombios_scaler_setup(struct drm_crtc *crtc)
80{
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
86
87 /* fixme - fill in enc_priv for atom dac */
88 enum radeon_tv_std tv_std = TV_STD_NTSC;
89 bool is_tv = false, is_cv = false;
90 struct drm_encoder *encoder;
91
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93 return;
94
95 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
96 /* find tv std */
97 if (encoder->crtc == crtc) {
98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 tv_std = tv_dac->tv_std;
102 is_tv = true;
103 }
104 }
105 }
106
107 memset(&args, 0, sizeof(args));
108
109 args.ucScaler = radeon_crtc->crtc_id;
110
111 if (is_tv) {
112 switch (tv_std) {
113 case TV_STD_NTSC:
114 default:
115 args.ucTVStandard = ATOM_TV_NTSC;
116 break;
117 case TV_STD_PAL:
118 args.ucTVStandard = ATOM_TV_PAL;
119 break;
120 case TV_STD_PAL_M:
121 args.ucTVStandard = ATOM_TV_PALM;
122 break;
123 case TV_STD_PAL_60:
124 args.ucTVStandard = ATOM_TV_PAL60;
125 break;
126 case TV_STD_NTSC_J:
127 args.ucTVStandard = ATOM_TV_NTSCJ;
128 break;
129 case TV_STD_SCART_PAL:
130 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
131 break;
132 case TV_STD_SECAM:
133 args.ucTVStandard = ATOM_TV_SECAM;
134 break;
135 case TV_STD_PAL_CN:
136 args.ucTVStandard = ATOM_TV_PALCN;
137 break;
138 }
139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
140 } else if (is_cv) {
141 args.ucTVStandard = ATOM_TV_CV;
142 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
143 } else {
144 switch (radeon_crtc->rmx_type) {
145 case RMX_FULL:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 case RMX_CENTER:
149 args.ucEnable = ATOM_SCALER_CENTER;
150 break;
151 case RMX_ASPECT:
152 args.ucEnable = ATOM_SCALER_EXPANSION;
153 break;
154 default:
155 if (ASIC_IS_AVIVO(rdev))
156 args.ucEnable = ATOM_SCALER_DISABLE;
157 else
158 args.ucEnable = ATOM_SCALER_CENTER;
159 break;
160 }
161 }
162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
163 if ((is_tv || is_cv)
164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
165 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
166 }
167}
168
169static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
170{
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 int index =
175 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
176 ENABLE_CRTC_PS_ALLOCATION args;
177
178 memset(&args, 0, sizeof(args));
179
180 args.ucCRTC = radeon_crtc->crtc_id;
181 args.ucEnable = lock;
182
183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
184}
185
186static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
187{
188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
189 struct drm_device *dev = crtc->dev;
190 struct radeon_device *rdev = dev->dev_private;
191 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
192 ENABLE_CRTC_PS_ALLOCATION args;
193
194 memset(&args, 0, sizeof(args));
195
196 args.ucCRTC = radeon_crtc->crtc_id;
197 args.ucEnable = state;
198
199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
200}
201
202static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
203{
204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
205 struct drm_device *dev = crtc->dev;
206 struct radeon_device *rdev = dev->dev_private;
207 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
208 ENABLE_CRTC_PS_ALLOCATION args;
209
210 memset(&args, 0, sizeof(args));
211
212 args.ucCRTC = radeon_crtc->crtc_id;
213 args.ucEnable = state;
214
215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
216}
217
218static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
219{
220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
221 struct drm_device *dev = crtc->dev;
222 struct radeon_device *rdev = dev->dev_private;
223 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
224 BLANK_CRTC_PS_ALLOCATION args;
225
226 memset(&args, 0, sizeof(args));
227
228 args.ucCRTC = radeon_crtc->crtc_id;
229 args.ucBlanking = state;
230
231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
232}
233
234void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
235{
236 struct drm_device *dev = crtc->dev;
237 struct radeon_device *rdev = dev->dev_private;
238 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
239
240 switch (mode) {
241 case DRM_MODE_DPMS_ON:
242 radeon_crtc->enabled = true;
243 /* adjust pm to dpms changes BEFORE enabling crtcs */
244 radeon_pm_compute_clocks(rdev);
245 atombios_enable_crtc(crtc, ATOM_ENABLE);
246 if (ASIC_IS_DCE3(rdev))
247 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
248 atombios_blank_crtc(crtc, ATOM_DISABLE);
249 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
250 radeon_crtc_load_lut(crtc);
251 break;
252 case DRM_MODE_DPMS_STANDBY:
253 case DRM_MODE_DPMS_SUSPEND:
254 case DRM_MODE_DPMS_OFF:
255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
256 if (radeon_crtc->enabled)
257 atombios_blank_crtc(crtc, ATOM_ENABLE);
258 if (ASIC_IS_DCE3(rdev))
259 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
260 atombios_enable_crtc(crtc, ATOM_DISABLE);
261 radeon_crtc->enabled = false;
262 /* adjust pm to dpms changes AFTER disabling crtcs */
263 radeon_pm_compute_clocks(rdev);
264 break;
265 }
266}
267
268static void
269atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
270 struct drm_display_mode *mode)
271{
272 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
273 struct drm_device *dev = crtc->dev;
274 struct radeon_device *rdev = dev->dev_private;
275 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
276 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
277 u16 misc = 0;
278
279 memset(&args, 0, sizeof(args));
280 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
281 args.usH_Blanking_Time =
282 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
283 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
284 args.usV_Blanking_Time =
285 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
286 args.usH_SyncOffset =
287 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
288 args.usH_SyncWidth =
289 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
290 args.usV_SyncOffset =
291 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
292 args.usV_SyncWidth =
293 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
294 args.ucH_Border = radeon_crtc->h_border;
295 args.ucV_Border = radeon_crtc->v_border;
296
297 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
298 misc |= ATOM_VSYNC_POLARITY;
299 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
300 misc |= ATOM_HSYNC_POLARITY;
301 if (mode->flags & DRM_MODE_FLAG_CSYNC)
302 misc |= ATOM_COMPOSITESYNC;
303 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
304 misc |= ATOM_INTERLACE;
305 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
306 misc |= ATOM_DOUBLE_CLOCK_MODE;
307
308 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
309 args.ucCRTC = radeon_crtc->crtc_id;
310
311 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
312}
313
314static void atombios_crtc_set_timing(struct drm_crtc *crtc,
315 struct drm_display_mode *mode)
316{
317 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
318 struct drm_device *dev = crtc->dev;
319 struct radeon_device *rdev = dev->dev_private;
320 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
321 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
322 u16 misc = 0;
323
324 memset(&args, 0, sizeof(args));
325 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
326 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
327 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
328 args.usH_SyncWidth =
329 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
330 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
331 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
332 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
333 args.usV_SyncWidth =
334 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
335
336 args.ucOverscanRight = radeon_crtc->h_border;
337 args.ucOverscanLeft = radeon_crtc->h_border;
338 args.ucOverscanBottom = radeon_crtc->v_border;
339 args.ucOverscanTop = radeon_crtc->v_border;
340
341 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
342 misc |= ATOM_VSYNC_POLARITY;
343 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
344 misc |= ATOM_HSYNC_POLARITY;
345 if (mode->flags & DRM_MODE_FLAG_CSYNC)
346 misc |= ATOM_COMPOSITESYNC;
347 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
348 misc |= ATOM_INTERLACE;
349 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
350 misc |= ATOM_DOUBLE_CLOCK_MODE;
351
352 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
353 args.ucCRTC = radeon_crtc->crtc_id;
354
355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
356}
357
358static void atombios_disable_ss(struct drm_crtc *crtc)
359{
360 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
361 struct drm_device *dev = crtc->dev;
362 struct radeon_device *rdev = dev->dev_private;
363 u32 ss_cntl;
364
365 if (ASIC_IS_DCE4(rdev)) {
366 switch (radeon_crtc->pll_id) {
367 case ATOM_PPLL1:
368 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
369 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
370 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
371 break;
372 case ATOM_PPLL2:
373 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
374 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
375 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
376 break;
377 case ATOM_DCPLL:
378 case ATOM_PPLL_INVALID:
379 return;
380 }
381 } else if (ASIC_IS_AVIVO(rdev)) {
382 switch (radeon_crtc->pll_id) {
383 case ATOM_PPLL1:
384 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
385 ss_cntl &= ~1;
386 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
387 break;
388 case ATOM_PPLL2:
389 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
390 ss_cntl &= ~1;
391 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
392 break;
393 case ATOM_DCPLL:
394 case ATOM_PPLL_INVALID:
395 return;
396 }
397 }
398}
399
400
401union atom_enable_ss {
402 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
403 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
404 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
405 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
406 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
407};
408
409static void atombios_crtc_program_ss(struct drm_crtc *crtc,
410 int enable,
411 int pll_id,
412 struct radeon_atom_ss *ss)
413{
414 struct drm_device *dev = crtc->dev;
415 struct radeon_device *rdev = dev->dev_private;
416 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
417 union atom_enable_ss args;
418
419 memset(&args, 0, sizeof(args));
420
421 if (ASIC_IS_DCE5(rdev)) {
422 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
423 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
424 switch (pll_id) {
425 case ATOM_PPLL1:
426 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
427 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
428 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
429 break;
430 case ATOM_PPLL2:
431 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
432 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
433 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
434 break;
435 case ATOM_DCPLL:
436 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
437 args.v3.usSpreadSpectrumAmount = cpu_to_le16(0);
438 args.v3.usSpreadSpectrumStep = cpu_to_le16(0);
439 break;
440 case ATOM_PPLL_INVALID:
441 return;
442 }
443 args.v3.ucEnable = enable;
444 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK))
445 args.v3.ucEnable = ATOM_DISABLE;
446 } else if (ASIC_IS_DCE4(rdev)) {
447 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
448 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
449 switch (pll_id) {
450 case ATOM_PPLL1:
451 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
452 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
453 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
454 break;
455 case ATOM_PPLL2:
456 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
457 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
458 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
459 break;
460 case ATOM_DCPLL:
461 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
462 args.v2.usSpreadSpectrumAmount = cpu_to_le16(0);
463 args.v2.usSpreadSpectrumStep = cpu_to_le16(0);
464 break;
465 case ATOM_PPLL_INVALID:
466 return;
467 }
468 args.v2.ucEnable = enable;
469 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev))
470 args.v2.ucEnable = ATOM_DISABLE;
471 } else if (ASIC_IS_DCE3(rdev)) {
472 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
473 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
474 args.v1.ucSpreadSpectrumStep = ss->step;
475 args.v1.ucSpreadSpectrumDelay = ss->delay;
476 args.v1.ucSpreadSpectrumRange = ss->range;
477 args.v1.ucPpll = pll_id;
478 args.v1.ucEnable = enable;
479 } else if (ASIC_IS_AVIVO(rdev)) {
480 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
481 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
482 atombios_disable_ss(crtc);
483 return;
484 }
485 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
486 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
487 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
488 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
489 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
490 args.lvds_ss_2.ucEnable = enable;
491 } else {
492 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
493 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
494 atombios_disable_ss(crtc);
495 return;
496 }
497 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
498 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
499 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
500 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
501 args.lvds_ss.ucEnable = enable;
502 }
503 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
504}
505
506union adjust_pixel_clock {
507 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
508 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
509};
510
511static u32 atombios_adjust_pll(struct drm_crtc *crtc,
512 struct drm_display_mode *mode,
513 struct radeon_pll *pll,
514 bool ss_enabled,
515 struct radeon_atom_ss *ss)
516{
517 struct drm_device *dev = crtc->dev;
518 struct radeon_device *rdev = dev->dev_private;
519 struct drm_encoder *encoder = NULL;
520 struct radeon_encoder *radeon_encoder = NULL;
521 struct drm_connector *connector = NULL;
522 u32 adjusted_clock = mode->clock;
523 int encoder_mode = 0;
524 u32 dp_clock = mode->clock;
525 int bpc = 8;
526
527 /* reset the pll flags */
528 pll->flags = 0;
529
530 if (ASIC_IS_AVIVO(rdev)) {
531 if ((rdev->family == CHIP_RS600) ||
532 (rdev->family == CHIP_RS690) ||
533 (rdev->family == CHIP_RS740))
534 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
535 RADEON_PLL_PREFER_CLOSEST_LOWER);
536
537 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
538 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
539 else
540 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
541
542 if (rdev->family < CHIP_RV770)
543 pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
544 } else {
545 pll->flags |= RADEON_PLL_LEGACY;
546
547 if (mode->clock > 200000) /* range limits??? */
548 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
549 else
550 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
551 }
552
553 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
554 if (encoder->crtc == crtc) {
555 radeon_encoder = to_radeon_encoder(encoder);
556 connector = radeon_get_connector_for_encoder(encoder);
557 if (connector)
558 bpc = connector->display_info.bpc;
559 encoder_mode = atombios_get_encoder_mode(encoder);
560 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
561 radeon_encoder_is_dp_bridge(encoder)) {
562 if (connector) {
563 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
564 struct radeon_connector_atom_dig *dig_connector =
565 radeon_connector->con_priv;
566
567 dp_clock = dig_connector->dp_clock;
568 }
569 }
570
571 /* use recommended ref_div for ss */
572 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
573 if (ss_enabled) {
574 if (ss->refdiv) {
575 pll->flags |= RADEON_PLL_USE_REF_DIV;
576 pll->reference_div = ss->refdiv;
577 if (ASIC_IS_AVIVO(rdev))
578 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
579 }
580 }
581 }
582
583 if (ASIC_IS_AVIVO(rdev)) {
584 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
585 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
586 adjusted_clock = mode->clock * 2;
587 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
588 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
589 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
590 pll->flags |= RADEON_PLL_IS_LCD;
591 } else {
592 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
593 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
594 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
595 pll->flags |= RADEON_PLL_USE_REF_DIV;
596 }
597 break;
598 }
599 }
600
601 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
602 * accordingly based on the encoder/transmitter to work around
603 * special hw requirements.
604 */
605 if (ASIC_IS_DCE3(rdev)) {
606 union adjust_pixel_clock args;
607 u8 frev, crev;
608 int index;
609
610 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
611 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
612 &crev))
613 return adjusted_clock;
614
615 memset(&args, 0, sizeof(args));
616
617 switch (frev) {
618 case 1:
619 switch (crev) {
620 case 1:
621 case 2:
622 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
623 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
624 args.v1.ucEncodeMode = encoder_mode;
625 if (ss_enabled && ss->percentage)
626 args.v1.ucConfig |=
627 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
628
629 atom_execute_table(rdev->mode_info.atom_context,
630 index, (uint32_t *)&args);
631 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
632 break;
633 case 3:
634 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
635 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
636 args.v3.sInput.ucEncodeMode = encoder_mode;
637 args.v3.sInput.ucDispPllConfig = 0;
638 if (ss_enabled && ss->percentage)
639 args.v3.sInput.ucDispPllConfig |=
640 DISPPLL_CONFIG_SS_ENABLE;
641 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT) ||
642 radeon_encoder_is_dp_bridge(encoder)) {
643 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
644 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
645 args.v3.sInput.ucDispPllConfig |=
646 DISPPLL_CONFIG_COHERENT_MODE;
647 /* 16200 or 27000 */
648 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
649 } else {
650 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
651 /* deep color support */
652 args.v3.sInput.usPixelClock =
653 cpu_to_le16((mode->clock * bpc / 8) / 10);
654 }
655 if (dig->coherent_mode)
656 args.v3.sInput.ucDispPllConfig |=
657 DISPPLL_CONFIG_COHERENT_MODE;
658 if (mode->clock > 165000)
659 args.v3.sInput.ucDispPllConfig |=
660 DISPPLL_CONFIG_DUAL_LINK;
661 }
662 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
663 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
664 args.v3.sInput.ucDispPllConfig |=
665 DISPPLL_CONFIG_COHERENT_MODE;
666 /* 16200 or 27000 */
667 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
668 } else if (encoder_mode != ATOM_ENCODER_MODE_LVDS) {
669 if (mode->clock > 165000)
670 args.v3.sInput.ucDispPllConfig |=
671 DISPPLL_CONFIG_DUAL_LINK;
672 }
673 }
674 if (radeon_encoder_is_dp_bridge(encoder)) {
675 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
676 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
677 args.v3.sInput.ucExtTransmitterID = ext_radeon_encoder->encoder_id;
678 } else
679 args.v3.sInput.ucExtTransmitterID = 0;
680
681 atom_execute_table(rdev->mode_info.atom_context,
682 index, (uint32_t *)&args);
683 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
684 if (args.v3.sOutput.ucRefDiv) {
685 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
686 pll->flags |= RADEON_PLL_USE_REF_DIV;
687 pll->reference_div = args.v3.sOutput.ucRefDiv;
688 }
689 if (args.v3.sOutput.ucPostDiv) {
690 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
691 pll->flags |= RADEON_PLL_USE_POST_DIV;
692 pll->post_div = args.v3.sOutput.ucPostDiv;
693 }
694 break;
695 default:
696 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
697 return adjusted_clock;
698 }
699 break;
700 default:
701 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
702 return adjusted_clock;
703 }
704 }
705 return adjusted_clock;
706}
707
708union set_pixel_clock {
709 SET_PIXEL_CLOCK_PS_ALLOCATION base;
710 PIXEL_CLOCK_PARAMETERS v1;
711 PIXEL_CLOCK_PARAMETERS_V2 v2;
712 PIXEL_CLOCK_PARAMETERS_V3 v3;
713 PIXEL_CLOCK_PARAMETERS_V5 v5;
714 PIXEL_CLOCK_PARAMETERS_V6 v6;
715};
716
717/* on DCE5, make sure the voltage is high enough to support the
718 * required disp clk.
719 */
720static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,
721 u32 dispclk)
722{
723 struct drm_device *dev = crtc->dev;
724 struct radeon_device *rdev = dev->dev_private;
725 u8 frev, crev;
726 int index;
727 union set_pixel_clock args;
728
729 memset(&args, 0, sizeof(args));
730
731 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
732 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
733 &crev))
734 return;
735
736 switch (frev) {
737 case 1:
738 switch (crev) {
739 case 5:
740 /* if the default dcpll clock is specified,
741 * SetPixelClock provides the dividers
742 */
743 args.v5.ucCRTC = ATOM_CRTC_INVALID;
744 args.v5.usPixelClock = cpu_to_le16(dispclk);
745 args.v5.ucPpll = ATOM_DCPLL;
746 break;
747 case 6:
748 /* if the default dcpll clock is specified,
749 * SetPixelClock provides the dividers
750 */
751 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
752 args.v6.ucPpll = ATOM_DCPLL;
753 break;
754 default:
755 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
756 return;
757 }
758 break;
759 default:
760 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
761 return;
762 }
763 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
764}
765
766static void atombios_crtc_program_pll(struct drm_crtc *crtc,
767 u32 crtc_id,
768 int pll_id,
769 u32 encoder_mode,
770 u32 encoder_id,
771 u32 clock,
772 u32 ref_div,
773 u32 fb_div,
774 u32 frac_fb_div,
775 u32 post_div,
776 int bpc,
777 bool ss_enabled,
778 struct radeon_atom_ss *ss)
779{
780 struct drm_device *dev = crtc->dev;
781 struct radeon_device *rdev = dev->dev_private;
782 u8 frev, crev;
783 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
784 union set_pixel_clock args;
785
786 memset(&args, 0, sizeof(args));
787
788 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
789 &crev))
790 return;
791
792 switch (frev) {
793 case 1:
794 switch (crev) {
795 case 1:
796 if (clock == ATOM_DISABLE)
797 return;
798 args.v1.usPixelClock = cpu_to_le16(clock / 10);
799 args.v1.usRefDiv = cpu_to_le16(ref_div);
800 args.v1.usFbDiv = cpu_to_le16(fb_div);
801 args.v1.ucFracFbDiv = frac_fb_div;
802 args.v1.ucPostDiv = post_div;
803 args.v1.ucPpll = pll_id;
804 args.v1.ucCRTC = crtc_id;
805 args.v1.ucRefDivSrc = 1;
806 break;
807 case 2:
808 args.v2.usPixelClock = cpu_to_le16(clock / 10);
809 args.v2.usRefDiv = cpu_to_le16(ref_div);
810 args.v2.usFbDiv = cpu_to_le16(fb_div);
811 args.v2.ucFracFbDiv = frac_fb_div;
812 args.v2.ucPostDiv = post_div;
813 args.v2.ucPpll = pll_id;
814 args.v2.ucCRTC = crtc_id;
815 args.v2.ucRefDivSrc = 1;
816 break;
817 case 3:
818 args.v3.usPixelClock = cpu_to_le16(clock / 10);
819 args.v3.usRefDiv = cpu_to_le16(ref_div);
820 args.v3.usFbDiv = cpu_to_le16(fb_div);
821 args.v3.ucFracFbDiv = frac_fb_div;
822 args.v3.ucPostDiv = post_div;
823 args.v3.ucPpll = pll_id;
824 args.v3.ucMiscInfo = (pll_id << 2);
825 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
826 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
827 args.v3.ucTransmitterId = encoder_id;
828 args.v3.ucEncoderMode = encoder_mode;
829 break;
830 case 5:
831 args.v5.ucCRTC = crtc_id;
832 args.v5.usPixelClock = cpu_to_le16(clock / 10);
833 args.v5.ucRefDiv = ref_div;
834 args.v5.usFbDiv = cpu_to_le16(fb_div);
835 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
836 args.v5.ucPostDiv = post_div;
837 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
838 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
839 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
840 switch (bpc) {
841 case 8:
842 default:
843 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
844 break;
845 case 10:
846 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
847 break;
848 }
849 args.v5.ucTransmitterID = encoder_id;
850 args.v5.ucEncoderMode = encoder_mode;
851 args.v5.ucPpll = pll_id;
852 break;
853 case 6:
854 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
855 args.v6.ucRefDiv = ref_div;
856 args.v6.usFbDiv = cpu_to_le16(fb_div);
857 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
858 args.v6.ucPostDiv = post_div;
859 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
860 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
861 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
862 switch (bpc) {
863 case 8:
864 default:
865 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
866 break;
867 case 10:
868 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
869 break;
870 case 12:
871 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
872 break;
873 case 16:
874 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
875 break;
876 }
877 args.v6.ucTransmitterID = encoder_id;
878 args.v6.ucEncoderMode = encoder_mode;
879 args.v6.ucPpll = pll_id;
880 break;
881 default:
882 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
883 return;
884 }
885 break;
886 default:
887 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
888 return;
889 }
890
891 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
892}
893
894static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
895{
896 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
897 struct drm_device *dev = crtc->dev;
898 struct radeon_device *rdev = dev->dev_private;
899 struct drm_encoder *encoder = NULL;
900 struct radeon_encoder *radeon_encoder = NULL;
901 u32 pll_clock = mode->clock;
902 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
903 struct radeon_pll *pll;
904 u32 adjusted_clock;
905 int encoder_mode = 0;
906 struct radeon_atom_ss ss;
907 bool ss_enabled = false;
908 int bpc = 8;
909
910 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
911 if (encoder->crtc == crtc) {
912 radeon_encoder = to_radeon_encoder(encoder);
913 encoder_mode = atombios_get_encoder_mode(encoder);
914 break;
915 }
916 }
917
918 if (!radeon_encoder)
919 return;
920
921 switch (radeon_crtc->pll_id) {
922 case ATOM_PPLL1:
923 pll = &rdev->clock.p1pll;
924 break;
925 case ATOM_PPLL2:
926 pll = &rdev->clock.p2pll;
927 break;
928 case ATOM_DCPLL:
929 case ATOM_PPLL_INVALID:
930 default:
931 pll = &rdev->clock.dcpll;
932 break;
933 }
934
935 if (radeon_encoder->active_device &
936 (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
937 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
938 struct drm_connector *connector =
939 radeon_get_connector_for_encoder(encoder);
940 struct radeon_connector *radeon_connector =
941 to_radeon_connector(connector);
942 struct radeon_connector_atom_dig *dig_connector =
943 radeon_connector->con_priv;
944 int dp_clock;
945 bpc = connector->display_info.bpc;
946
947 switch (encoder_mode) {
948 case ATOM_ENCODER_MODE_DP:
949 /* DP/eDP */
950 dp_clock = dig_connector->dp_clock / 10;
951 if (ASIC_IS_DCE4(rdev))
952 ss_enabled =
953 radeon_atombios_get_asic_ss_info(rdev, &ss,
954 ASIC_INTERNAL_SS_ON_DP,
955 dp_clock);
956 else {
957 if (dp_clock == 16200) {
958 ss_enabled =
959 radeon_atombios_get_ppll_ss_info(rdev, &ss,
960 ATOM_DP_SS_ID2);
961 if (!ss_enabled)
962 ss_enabled =
963 radeon_atombios_get_ppll_ss_info(rdev, &ss,
964 ATOM_DP_SS_ID1);
965 } else
966 ss_enabled =
967 radeon_atombios_get_ppll_ss_info(rdev, &ss,
968 ATOM_DP_SS_ID1);
969 }
970 break;
971 case ATOM_ENCODER_MODE_LVDS:
972 if (ASIC_IS_DCE4(rdev))
973 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
974 dig->lcd_ss_id,
975 mode->clock / 10);
976 else
977 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss,
978 dig->lcd_ss_id);
979 break;
980 case ATOM_ENCODER_MODE_DVI:
981 if (ASIC_IS_DCE4(rdev))
982 ss_enabled =
983 radeon_atombios_get_asic_ss_info(rdev, &ss,
984 ASIC_INTERNAL_SS_ON_TMDS,
985 mode->clock / 10);
986 break;
987 case ATOM_ENCODER_MODE_HDMI:
988 if (ASIC_IS_DCE4(rdev))
989 ss_enabled =
990 radeon_atombios_get_asic_ss_info(rdev, &ss,
991 ASIC_INTERNAL_SS_ON_HDMI,
992 mode->clock / 10);
993 break;
994 default:
995 break;
996 }
997 }
998
999 /* adjust pixel clock as needed */
1000 adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
1001
1002 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1003 /* TV seems to prefer the legacy algo on some boards */
1004 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1005 &ref_div, &post_div);
1006 else if (ASIC_IS_AVIVO(rdev))
1007 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1008 &ref_div, &post_div);
1009 else
1010 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1011 &ref_div, &post_div);
1012
1013 atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
1014
1015 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1016 encoder_mode, radeon_encoder->encoder_id, mode->clock,
1017 ref_div, fb_div, frac_fb_div, post_div, bpc, ss_enabled, &ss);
1018
1019 if (ss_enabled) {
1020 /* calculate ss amount and step size */
1021 if (ASIC_IS_DCE4(rdev)) {
1022 u32 step_size;
1023 u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
1024 ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1025 ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1026 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1027 if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1028 step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
1029 (125 * 25 * pll->reference_freq / 100);
1030 else
1031 step_size = (2 * amount * ref_div * (ss.rate * 2048)) /
1032 (125 * 25 * pll->reference_freq / 100);
1033 ss.step = step_size;
1034 }
1035
1036 atombios_crtc_program_ss(crtc, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
1037 }
1038}
1039
1040static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1041 struct drm_framebuffer *fb,
1042 int x, int y, int atomic)
1043{
1044 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1045 struct drm_device *dev = crtc->dev;
1046 struct radeon_device *rdev = dev->dev_private;
1047 struct radeon_framebuffer *radeon_fb;
1048 struct drm_framebuffer *target_fb;
1049 struct drm_gem_object *obj;
1050 struct radeon_bo *rbo;
1051 uint64_t fb_location;
1052 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1053 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1054 u32 tmp, viewport_w, viewport_h;
1055 int r;
1056
1057 /* no fb bound */
1058 if (!atomic && !crtc->fb) {
1059 DRM_DEBUG_KMS("No FB bound\n");
1060 return 0;
1061 }
1062
1063 if (atomic) {
1064 radeon_fb = to_radeon_framebuffer(fb);
1065 target_fb = fb;
1066 }
1067 else {
1068 radeon_fb = to_radeon_framebuffer(crtc->fb);
1069 target_fb = crtc->fb;
1070 }
1071
1072 /* If atomic, assume fb object is pinned & idle & fenced and
1073 * just update base pointers
1074 */
1075 obj = radeon_fb->obj;
1076 rbo = gem_to_radeon_bo(obj);
1077 r = radeon_bo_reserve(rbo, false);
1078 if (unlikely(r != 0))
1079 return r;
1080
1081 if (atomic)
1082 fb_location = radeon_bo_gpu_offset(rbo);
1083 else {
1084 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1085 if (unlikely(r != 0)) {
1086 radeon_bo_unreserve(rbo);
1087 return -EINVAL;
1088 }
1089 }
1090
1091 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1092 radeon_bo_unreserve(rbo);
1093
1094 switch (target_fb->bits_per_pixel) {
1095 case 8:
1096 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1097 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1098 break;
1099 case 15:
1100 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1101 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1102 break;
1103 case 16:
1104 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1105 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1106#ifdef __BIG_ENDIAN
1107 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1108#endif
1109 break;
1110 case 24:
1111 case 32:
1112 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1113 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1114#ifdef __BIG_ENDIAN
1115 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1116#endif
1117 break;
1118 default:
1119 DRM_ERROR("Unsupported screen depth %d\n",
1120 target_fb->bits_per_pixel);
1121 return -EINVAL;
1122 }
1123
1124 if (tiling_flags & RADEON_TILING_MACRO)
1125 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1126 else if (tiling_flags & RADEON_TILING_MICRO)
1127 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1128
1129 switch (radeon_crtc->crtc_id) {
1130 case 0:
1131 WREG32(AVIVO_D1VGA_CONTROL, 0);
1132 break;
1133 case 1:
1134 WREG32(AVIVO_D2VGA_CONTROL, 0);
1135 break;
1136 case 2:
1137 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1138 break;
1139 case 3:
1140 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1141 break;
1142 case 4:
1143 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1144 break;
1145 case 5:
1146 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1147 break;
1148 default:
1149 break;
1150 }
1151
1152 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1153 upper_32_bits(fb_location));
1154 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1155 upper_32_bits(fb_location));
1156 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1157 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1158 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1159 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1160 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1161 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1162
1163 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1164 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1165 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1166 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1167 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1168 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1169
1170 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
1171 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1172 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1173
1174 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1175 crtc->mode.vdisplay);
1176 x &= ~3;
1177 y &= ~1;
1178 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1179 (x << 16) | y);
1180 viewport_w = crtc->mode.hdisplay;
1181 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1182 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1183 (viewport_w << 16) | viewport_h);
1184
1185 /* pageflip setup */
1186 /* make sure flip is at vb rather than hb */
1187 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1188 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1189 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1190
1191 /* set pageflip to happen anywhere in vblank interval */
1192 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1193
1194 if (!atomic && fb && fb != crtc->fb) {
1195 radeon_fb = to_radeon_framebuffer(fb);
1196 rbo = gem_to_radeon_bo(radeon_fb->obj);
1197 r = radeon_bo_reserve(rbo, false);
1198 if (unlikely(r != 0))
1199 return r;
1200 radeon_bo_unpin(rbo);
1201 radeon_bo_unreserve(rbo);
1202 }
1203
1204 /* Bytes per pixel may have changed */
1205 radeon_bandwidth_update(rdev);
1206
1207 return 0;
1208}
1209
1210static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1211 struct drm_framebuffer *fb,
1212 int x, int y, int atomic)
1213{
1214 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1215 struct drm_device *dev = crtc->dev;
1216 struct radeon_device *rdev = dev->dev_private;
1217 struct radeon_framebuffer *radeon_fb;
1218 struct drm_gem_object *obj;
1219 struct radeon_bo *rbo;
1220 struct drm_framebuffer *target_fb;
1221 uint64_t fb_location;
1222 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1223 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1224 u32 tmp, viewport_w, viewport_h;
1225 int r;
1226
1227 /* no fb bound */
1228 if (!atomic && !crtc->fb) {
1229 DRM_DEBUG_KMS("No FB bound\n");
1230 return 0;
1231 }
1232
1233 if (atomic) {
1234 radeon_fb = to_radeon_framebuffer(fb);
1235 target_fb = fb;
1236 }
1237 else {
1238 radeon_fb = to_radeon_framebuffer(crtc->fb);
1239 target_fb = crtc->fb;
1240 }
1241
1242 obj = radeon_fb->obj;
1243 rbo = gem_to_radeon_bo(obj);
1244 r = radeon_bo_reserve(rbo, false);
1245 if (unlikely(r != 0))
1246 return r;
1247
1248 /* If atomic, assume fb object is pinned & idle & fenced and
1249 * just update base pointers
1250 */
1251 if (atomic)
1252 fb_location = radeon_bo_gpu_offset(rbo);
1253 else {
1254 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1255 if (unlikely(r != 0)) {
1256 radeon_bo_unreserve(rbo);
1257 return -EINVAL;
1258 }
1259 }
1260 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1261 radeon_bo_unreserve(rbo);
1262
1263 switch (target_fb->bits_per_pixel) {
1264 case 8:
1265 fb_format =
1266 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1267 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1268 break;
1269 case 15:
1270 fb_format =
1271 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1272 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1273 break;
1274 case 16:
1275 fb_format =
1276 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1277 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1278#ifdef __BIG_ENDIAN
1279 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1280#endif
1281 break;
1282 case 24:
1283 case 32:
1284 fb_format =
1285 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1286 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1287#ifdef __BIG_ENDIAN
1288 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1289#endif
1290 break;
1291 default:
1292 DRM_ERROR("Unsupported screen depth %d\n",
1293 target_fb->bits_per_pixel);
1294 return -EINVAL;
1295 }
1296
1297 if (rdev->family >= CHIP_R600) {
1298 if (tiling_flags & RADEON_TILING_MACRO)
1299 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1300 else if (tiling_flags & RADEON_TILING_MICRO)
1301 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1302 } else {
1303 if (tiling_flags & RADEON_TILING_MACRO)
1304 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1305
1306 if (tiling_flags & RADEON_TILING_MICRO)
1307 fb_format |= AVIVO_D1GRPH_TILED;
1308 }
1309
1310 if (radeon_crtc->crtc_id == 0)
1311 WREG32(AVIVO_D1VGA_CONTROL, 0);
1312 else
1313 WREG32(AVIVO_D2VGA_CONTROL, 0);
1314
1315 if (rdev->family >= CHIP_RV770) {
1316 if (radeon_crtc->crtc_id) {
1317 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1318 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1319 } else {
1320 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1321 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1322 }
1323 }
1324 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1325 (u32) fb_location);
1326 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1327 radeon_crtc->crtc_offset, (u32) fb_location);
1328 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1329 if (rdev->family >= CHIP_R600)
1330 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1331
1332 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1333 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1334 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1335 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1336 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1337 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1338
1339 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
1340 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1341 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1342
1343 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1344 crtc->mode.vdisplay);
1345 x &= ~3;
1346 y &= ~1;
1347 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1348 (x << 16) | y);
1349 viewport_w = crtc->mode.hdisplay;
1350 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1351 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1352 (viewport_w << 16) | viewport_h);
1353
1354 /* pageflip setup */
1355 /* make sure flip is at vb rather than hb */
1356 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1357 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1358 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1359
1360 /* set pageflip to happen anywhere in vblank interval */
1361 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1362
1363 if (!atomic && fb && fb != crtc->fb) {
1364 radeon_fb = to_radeon_framebuffer(fb);
1365 rbo = gem_to_radeon_bo(radeon_fb->obj);
1366 r = radeon_bo_reserve(rbo, false);
1367 if (unlikely(r != 0))
1368 return r;
1369 radeon_bo_unpin(rbo);
1370 radeon_bo_unreserve(rbo);
1371 }
1372
1373 /* Bytes per pixel may have changed */
1374 radeon_bandwidth_update(rdev);
1375
1376 return 0;
1377}
1378
1379int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1380 struct drm_framebuffer *old_fb)
1381{
1382 struct drm_device *dev = crtc->dev;
1383 struct radeon_device *rdev = dev->dev_private;
1384
1385 if (ASIC_IS_DCE4(rdev))
1386 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1387 else if (ASIC_IS_AVIVO(rdev))
1388 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1389 else
1390 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1391}
1392
1393int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1394 struct drm_framebuffer *fb,
1395 int x, int y, enum mode_set_atomic state)
1396{
1397 struct drm_device *dev = crtc->dev;
1398 struct radeon_device *rdev = dev->dev_private;
1399
1400 if (ASIC_IS_DCE4(rdev))
1401 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1402 else if (ASIC_IS_AVIVO(rdev))
1403 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1404 else
1405 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1406}
1407
1408/* properly set additional regs when using atombios */
1409static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1410{
1411 struct drm_device *dev = crtc->dev;
1412 struct radeon_device *rdev = dev->dev_private;
1413 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1414 u32 disp_merge_cntl;
1415
1416 switch (radeon_crtc->crtc_id) {
1417 case 0:
1418 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1419 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1420 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1421 break;
1422 case 1:
1423 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1424 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1425 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1426 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1427 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1428 break;
1429 }
1430}
1431
1432static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1433{
1434 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1435 struct drm_device *dev = crtc->dev;
1436 struct radeon_device *rdev = dev->dev_private;
1437 struct drm_encoder *test_encoder;
1438 struct drm_crtc *test_crtc;
1439 uint32_t pll_in_use = 0;
1440
1441 if (ASIC_IS_DCE4(rdev)) {
1442 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1443 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1444 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1445 * depending on the asic:
1446 * DCE4: PPLL or ext clock
1447 * DCE5: DCPLL or ext clock
1448 *
1449 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1450 * PPLL/DCPLL programming and only program the DP DTO for the
1451 * crtc virtual pixel clock.
1452 */
1453 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1454 if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk)
1455 return ATOM_PPLL_INVALID;
1456 }
1457 }
1458 }
1459
1460 /* otherwise, pick one of the plls */
1461 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1462 struct radeon_crtc *radeon_test_crtc;
1463
1464 if (crtc == test_crtc)
1465 continue;
1466
1467 radeon_test_crtc = to_radeon_crtc(test_crtc);
1468 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1469 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1470 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1471 }
1472 if (!(pll_in_use & 1))
1473 return ATOM_PPLL1;
1474 return ATOM_PPLL2;
1475 } else
1476 return radeon_crtc->crtc_id;
1477
1478}
1479
1480int atombios_crtc_mode_set(struct drm_crtc *crtc,
1481 struct drm_display_mode *mode,
1482 struct drm_display_mode *adjusted_mode,
1483 int x, int y, struct drm_framebuffer *old_fb)
1484{
1485 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1486 struct drm_device *dev = crtc->dev;
1487 struct radeon_device *rdev = dev->dev_private;
1488 struct drm_encoder *encoder;
1489 bool is_tvcv = false;
1490
1491 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1492 /* find tv std */
1493 if (encoder->crtc == crtc) {
1494 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1495 if (radeon_encoder->active_device &
1496 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1497 is_tvcv = true;
1498 }
1499 }
1500
1501 /* always set DCPLL */
1502 if (ASIC_IS_DCE4(rdev)) {
1503 struct radeon_atom_ss ss;
1504 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1505 ASIC_INTERNAL_SS_ON_DCPLL,
1506 rdev->clock.default_dispclk);
1507 if (ss_enabled)
1508 atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss);
1509 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1510 atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk);
1511 if (ss_enabled)
1512 atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss);
1513 }
1514 atombios_crtc_set_pll(crtc, adjusted_mode);
1515
1516 if (ASIC_IS_DCE4(rdev))
1517 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1518 else if (ASIC_IS_AVIVO(rdev)) {
1519 if (is_tvcv)
1520 atombios_crtc_set_timing(crtc, adjusted_mode);
1521 else
1522 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1523 } else {
1524 atombios_crtc_set_timing(crtc, adjusted_mode);
1525 if (radeon_crtc->crtc_id == 0)
1526 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1527 radeon_legacy_atom_fixup(crtc);
1528 }
1529 atombios_crtc_set_base(crtc, x, y, old_fb);
1530 atombios_overscan_setup(crtc, mode, adjusted_mode);
1531 atombios_scaler_setup(crtc);
1532 return 0;
1533}
1534
1535static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1536 struct drm_display_mode *mode,
1537 struct drm_display_mode *adjusted_mode)
1538{
1539 struct drm_device *dev = crtc->dev;
1540 struct radeon_device *rdev = dev->dev_private;
1541
1542 /* adjust pm to upcoming mode change */
1543 radeon_pm_compute_clocks(rdev);
1544
1545 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1546 return false;
1547 return true;
1548}
1549
1550static void atombios_crtc_prepare(struct drm_crtc *crtc)
1551{
1552 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1553
1554 /* pick pll */
1555 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1556
1557 atombios_lock_crtc(crtc, ATOM_ENABLE);
1558 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1559}
1560
1561static void atombios_crtc_commit(struct drm_crtc *crtc)
1562{
1563 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1564 atombios_lock_crtc(crtc, ATOM_DISABLE);
1565}
1566
1567static void atombios_crtc_disable(struct drm_crtc *crtc)
1568{
1569 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1570 struct radeon_atom_ss ss;
1571
1572 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1573
1574 switch (radeon_crtc->pll_id) {
1575 case ATOM_PPLL1:
1576 case ATOM_PPLL2:
1577 /* disable the ppll */
1578 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1579 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1580 break;
1581 default:
1582 break;
1583 }
1584 radeon_crtc->pll_id = -1;
1585}
1586
1587static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1588 .dpms = atombios_crtc_dpms,
1589 .mode_fixup = atombios_crtc_mode_fixup,
1590 .mode_set = atombios_crtc_mode_set,
1591 .mode_set_base = atombios_crtc_set_base,
1592 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
1593 .prepare = atombios_crtc_prepare,
1594 .commit = atombios_crtc_commit,
1595 .load_lut = radeon_crtc_load_lut,
1596 .disable = atombios_crtc_disable,
1597};
1598
1599void radeon_atombios_init_crtc(struct drm_device *dev,
1600 struct radeon_crtc *radeon_crtc)
1601{
1602 struct radeon_device *rdev = dev->dev_private;
1603
1604 if (ASIC_IS_DCE4(rdev)) {
1605 switch (radeon_crtc->crtc_id) {
1606 case 0:
1607 default:
1608 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1609 break;
1610 case 1:
1611 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1612 break;
1613 case 2:
1614 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1615 break;
1616 case 3:
1617 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1618 break;
1619 case 4:
1620 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1621 break;
1622 case 5:
1623 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1624 break;
1625 }
1626 } else {
1627 if (radeon_crtc->crtc_id == 1)
1628 radeon_crtc->crtc_offset =
1629 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1630 else
1631 radeon_crtc->crtc_offset = 0;
1632 }
1633 radeon_crtc->pll_id = -1;
1634 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1635}
1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27#include <drm/drm_crtc_helper.h>
28#include <drm/drm_fb_helper.h>
29#include <drm/drm_fixed.h>
30#include <drm/drm_fourcc.h>
31#include <drm/drm_vblank.h>
32#include <drm/radeon_drm.h>
33
34#include "radeon.h"
35#include "atom.h"
36#include "atom-bits.h"
37
38static void atombios_overscan_setup(struct drm_crtc *crtc,
39 struct drm_display_mode *mode,
40 struct drm_display_mode *adjusted_mode)
41{
42 struct drm_device *dev = crtc->dev;
43 struct radeon_device *rdev = dev->dev_private;
44 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
45 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
46 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
47 int a1, a2;
48
49 memset(&args, 0, sizeof(args));
50
51 args.ucCRTC = radeon_crtc->crtc_id;
52
53 switch (radeon_crtc->rmx_type) {
54 case RMX_CENTER:
55 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
56 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
57 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
58 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
59 break;
60 case RMX_ASPECT:
61 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
62 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
63
64 if (a1 > a2) {
65 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
66 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
67 } else if (a2 > a1) {
68 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
69 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
70 }
71 break;
72 case RMX_FULL:
73 default:
74 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
75 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
76 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
77 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
78 break;
79 }
80 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
81}
82
83static void atombios_scaler_setup(struct drm_crtc *crtc)
84{
85 struct drm_device *dev = crtc->dev;
86 struct radeon_device *rdev = dev->dev_private;
87 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
88 ENABLE_SCALER_PS_ALLOCATION args;
89 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
90 struct radeon_encoder *radeon_encoder =
91 to_radeon_encoder(radeon_crtc->encoder);
92 /* fixme - fill in enc_priv for atom dac */
93 enum radeon_tv_std tv_std = TV_STD_NTSC;
94 bool is_tv = false, is_cv = false;
95
96 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
97 return;
98
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 tv_std = tv_dac->tv_std;
102 is_tv = true;
103 }
104
105 memset(&args, 0, sizeof(args));
106
107 args.ucScaler = radeon_crtc->crtc_id;
108
109 if (is_tv) {
110 switch (tv_std) {
111 case TV_STD_NTSC:
112 default:
113 args.ucTVStandard = ATOM_TV_NTSC;
114 break;
115 case TV_STD_PAL:
116 args.ucTVStandard = ATOM_TV_PAL;
117 break;
118 case TV_STD_PAL_M:
119 args.ucTVStandard = ATOM_TV_PALM;
120 break;
121 case TV_STD_PAL_60:
122 args.ucTVStandard = ATOM_TV_PAL60;
123 break;
124 case TV_STD_NTSC_J:
125 args.ucTVStandard = ATOM_TV_NTSCJ;
126 break;
127 case TV_STD_SCART_PAL:
128 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
129 break;
130 case TV_STD_SECAM:
131 args.ucTVStandard = ATOM_TV_SECAM;
132 break;
133 case TV_STD_PAL_CN:
134 args.ucTVStandard = ATOM_TV_PALCN;
135 break;
136 }
137 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
138 } else if (is_cv) {
139 args.ucTVStandard = ATOM_TV_CV;
140 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
141 } else {
142 switch (radeon_crtc->rmx_type) {
143 case RMX_FULL:
144 args.ucEnable = ATOM_SCALER_EXPANSION;
145 break;
146 case RMX_CENTER:
147 args.ucEnable = ATOM_SCALER_CENTER;
148 break;
149 case RMX_ASPECT:
150 args.ucEnable = ATOM_SCALER_EXPANSION;
151 break;
152 default:
153 if (ASIC_IS_AVIVO(rdev))
154 args.ucEnable = ATOM_SCALER_DISABLE;
155 else
156 args.ucEnable = ATOM_SCALER_CENTER;
157 break;
158 }
159 }
160 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
161 if ((is_tv || is_cv)
162 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
163 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
164 }
165}
166
167static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
168{
169 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
170 struct drm_device *dev = crtc->dev;
171 struct radeon_device *rdev = dev->dev_private;
172 int index =
173 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
174 ENABLE_CRTC_PS_ALLOCATION args;
175
176 memset(&args, 0, sizeof(args));
177
178 args.ucCRTC = radeon_crtc->crtc_id;
179 args.ucEnable = lock;
180
181 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
182}
183
184static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
185{
186 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
187 struct drm_device *dev = crtc->dev;
188 struct radeon_device *rdev = dev->dev_private;
189 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
190 ENABLE_CRTC_PS_ALLOCATION args;
191
192 memset(&args, 0, sizeof(args));
193
194 args.ucCRTC = radeon_crtc->crtc_id;
195 args.ucEnable = state;
196
197 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
198}
199
200static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
201{
202 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
203 struct drm_device *dev = crtc->dev;
204 struct radeon_device *rdev = dev->dev_private;
205 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
206 ENABLE_CRTC_PS_ALLOCATION args;
207
208 memset(&args, 0, sizeof(args));
209
210 args.ucCRTC = radeon_crtc->crtc_id;
211 args.ucEnable = state;
212
213 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
214}
215
216static const u32 vga_control_regs[6] =
217{
218 AVIVO_D1VGA_CONTROL,
219 AVIVO_D2VGA_CONTROL,
220 EVERGREEN_D3VGA_CONTROL,
221 EVERGREEN_D4VGA_CONTROL,
222 EVERGREEN_D5VGA_CONTROL,
223 EVERGREEN_D6VGA_CONTROL,
224};
225
226static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
227{
228 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
229 struct drm_device *dev = crtc->dev;
230 struct radeon_device *rdev = dev->dev_private;
231 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
232 BLANK_CRTC_PS_ALLOCATION args;
233 u32 vga_control = 0;
234
235 memset(&args, 0, sizeof(args));
236
237 if (ASIC_IS_DCE8(rdev)) {
238 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
239 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
240 }
241
242 args.ucCRTC = radeon_crtc->crtc_id;
243 args.ucBlanking = state;
244
245 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
246
247 if (ASIC_IS_DCE8(rdev))
248 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
249}
250
251static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
252{
253 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
254 struct drm_device *dev = crtc->dev;
255 struct radeon_device *rdev = dev->dev_private;
256 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
257 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
258
259 memset(&args, 0, sizeof(args));
260
261 args.ucDispPipeId = radeon_crtc->crtc_id;
262 args.ucEnable = state;
263
264 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
265}
266
267void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
268{
269 struct drm_device *dev = crtc->dev;
270 struct radeon_device *rdev = dev->dev_private;
271 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
272
273 switch (mode) {
274 case DRM_MODE_DPMS_ON:
275 radeon_crtc->enabled = true;
276 atombios_enable_crtc(crtc, ATOM_ENABLE);
277 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
278 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
279 atombios_blank_crtc(crtc, ATOM_DISABLE);
280 if (dev->num_crtcs > radeon_crtc->crtc_id)
281 drm_crtc_vblank_on(crtc);
282 radeon_crtc_load_lut(crtc);
283 break;
284 case DRM_MODE_DPMS_STANDBY:
285 case DRM_MODE_DPMS_SUSPEND:
286 case DRM_MODE_DPMS_OFF:
287 if (dev->num_crtcs > radeon_crtc->crtc_id)
288 drm_crtc_vblank_off(crtc);
289 if (radeon_crtc->enabled)
290 atombios_blank_crtc(crtc, ATOM_ENABLE);
291 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
292 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
293 atombios_enable_crtc(crtc, ATOM_DISABLE);
294 radeon_crtc->enabled = false;
295 break;
296 }
297 /* adjust pm to dpms */
298 radeon_pm_compute_clocks(rdev);
299}
300
301static void
302atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
303 struct drm_display_mode *mode)
304{
305 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
306 struct drm_device *dev = crtc->dev;
307 struct radeon_device *rdev = dev->dev_private;
308 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
309 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
310 u16 misc = 0;
311
312 memset(&args, 0, sizeof(args));
313 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
314 args.usH_Blanking_Time =
315 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
316 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
317 args.usV_Blanking_Time =
318 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
319 args.usH_SyncOffset =
320 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
321 args.usH_SyncWidth =
322 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
323 args.usV_SyncOffset =
324 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
325 args.usV_SyncWidth =
326 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
327 args.ucH_Border = radeon_crtc->h_border;
328 args.ucV_Border = radeon_crtc->v_border;
329
330 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
331 misc |= ATOM_VSYNC_POLARITY;
332 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
333 misc |= ATOM_HSYNC_POLARITY;
334 if (mode->flags & DRM_MODE_FLAG_CSYNC)
335 misc |= ATOM_COMPOSITESYNC;
336 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
337 misc |= ATOM_INTERLACE;
338 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
339 misc |= ATOM_DOUBLE_CLOCK_MODE;
340 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
341 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
342
343 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
344 args.ucCRTC = radeon_crtc->crtc_id;
345
346 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
347}
348
349static void atombios_crtc_set_timing(struct drm_crtc *crtc,
350 struct drm_display_mode *mode)
351{
352 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
353 struct drm_device *dev = crtc->dev;
354 struct radeon_device *rdev = dev->dev_private;
355 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
356 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
357 u16 misc = 0;
358
359 memset(&args, 0, sizeof(args));
360 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
361 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
362 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
363 args.usH_SyncWidth =
364 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
365 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
366 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
367 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
368 args.usV_SyncWidth =
369 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
370
371 args.ucOverscanRight = radeon_crtc->h_border;
372 args.ucOverscanLeft = radeon_crtc->h_border;
373 args.ucOverscanBottom = radeon_crtc->v_border;
374 args.ucOverscanTop = radeon_crtc->v_border;
375
376 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
377 misc |= ATOM_VSYNC_POLARITY;
378 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
379 misc |= ATOM_HSYNC_POLARITY;
380 if (mode->flags & DRM_MODE_FLAG_CSYNC)
381 misc |= ATOM_COMPOSITESYNC;
382 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
383 misc |= ATOM_INTERLACE;
384 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
385 misc |= ATOM_DOUBLE_CLOCK_MODE;
386 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
387 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
388
389 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
390 args.ucCRTC = radeon_crtc->crtc_id;
391
392 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
393}
394
395static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
396{
397 u32 ss_cntl;
398
399 if (ASIC_IS_DCE4(rdev)) {
400 switch (pll_id) {
401 case ATOM_PPLL1:
402 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
403 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
404 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
405 break;
406 case ATOM_PPLL2:
407 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
408 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
409 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
410 break;
411 case ATOM_DCPLL:
412 case ATOM_PPLL_INVALID:
413 return;
414 }
415 } else if (ASIC_IS_AVIVO(rdev)) {
416 switch (pll_id) {
417 case ATOM_PPLL1:
418 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
419 ss_cntl &= ~1;
420 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
421 break;
422 case ATOM_PPLL2:
423 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
424 ss_cntl &= ~1;
425 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
426 break;
427 case ATOM_DCPLL:
428 case ATOM_PPLL_INVALID:
429 return;
430 }
431 }
432}
433
434
435union atom_enable_ss {
436 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
437 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
438 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
439 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
440 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
441};
442
443static void atombios_crtc_program_ss(struct radeon_device *rdev,
444 int enable,
445 int pll_id,
446 int crtc_id,
447 struct radeon_atom_ss *ss)
448{
449 unsigned i;
450 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
451 union atom_enable_ss args;
452
453 if (enable) {
454 /* Don't mess with SS if percentage is 0 or external ss.
455 * SS is already disabled previously, and disabling it
456 * again can cause display problems if the pll is already
457 * programmed.
458 */
459 if (ss->percentage == 0)
460 return;
461 if (ss->type & ATOM_EXTERNAL_SS_MASK)
462 return;
463 } else {
464 for (i = 0; i < rdev->num_crtc; i++) {
465 if (rdev->mode_info.crtcs[i] &&
466 rdev->mode_info.crtcs[i]->enabled &&
467 i != crtc_id &&
468 pll_id == rdev->mode_info.crtcs[i]->pll_id) {
469 /* one other crtc is using this pll don't turn
470 * off spread spectrum as it might turn off
471 * display on active crtc
472 */
473 return;
474 }
475 }
476 }
477
478 memset(&args, 0, sizeof(args));
479
480 if (ASIC_IS_DCE5(rdev)) {
481 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
482 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
483 switch (pll_id) {
484 case ATOM_PPLL1:
485 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
486 break;
487 case ATOM_PPLL2:
488 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
489 break;
490 case ATOM_DCPLL:
491 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
492 break;
493 case ATOM_PPLL_INVALID:
494 return;
495 }
496 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
497 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
498 args.v3.ucEnable = enable;
499 } else if (ASIC_IS_DCE4(rdev)) {
500 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
501 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
502 switch (pll_id) {
503 case ATOM_PPLL1:
504 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
505 break;
506 case ATOM_PPLL2:
507 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
508 break;
509 case ATOM_DCPLL:
510 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
511 break;
512 case ATOM_PPLL_INVALID:
513 return;
514 }
515 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
516 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
517 args.v2.ucEnable = enable;
518 } else if (ASIC_IS_DCE3(rdev)) {
519 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
520 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
521 args.v1.ucSpreadSpectrumStep = ss->step;
522 args.v1.ucSpreadSpectrumDelay = ss->delay;
523 args.v1.ucSpreadSpectrumRange = ss->range;
524 args.v1.ucPpll = pll_id;
525 args.v1.ucEnable = enable;
526 } else if (ASIC_IS_AVIVO(rdev)) {
527 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
528 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
529 atombios_disable_ss(rdev, pll_id);
530 return;
531 }
532 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
533 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
534 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
535 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
536 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
537 args.lvds_ss_2.ucEnable = enable;
538 } else {
539 if (enable == ATOM_DISABLE) {
540 atombios_disable_ss(rdev, pll_id);
541 return;
542 }
543 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
544 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
545 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
546 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
547 args.lvds_ss.ucEnable = enable;
548 }
549 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
550}
551
552union adjust_pixel_clock {
553 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
554 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
555};
556
557static u32 atombios_adjust_pll(struct drm_crtc *crtc,
558 struct drm_display_mode *mode)
559{
560 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
561 struct drm_device *dev = crtc->dev;
562 struct radeon_device *rdev = dev->dev_private;
563 struct drm_encoder *encoder = radeon_crtc->encoder;
564 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
565 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
566 u32 adjusted_clock = mode->clock;
567 int encoder_mode = atombios_get_encoder_mode(encoder);
568 u32 dp_clock = mode->clock;
569 u32 clock = mode->clock;
570 int bpc = radeon_crtc->bpc;
571 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
572
573 /* reset the pll flags */
574 radeon_crtc->pll_flags = 0;
575
576 if (ASIC_IS_AVIVO(rdev)) {
577 if ((rdev->family == CHIP_RS600) ||
578 (rdev->family == CHIP_RS690) ||
579 (rdev->family == CHIP_RS740))
580 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
581 RADEON_PLL_PREFER_CLOSEST_LOWER);
582
583 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
584 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
585 else
586 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
587
588 if (rdev->family < CHIP_RV770)
589 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
590 /* use frac fb div on APUs */
591 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
592 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
593 /* use frac fb div on RS780/RS880 */
594 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
595 && !radeon_crtc->ss_enabled)
596 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
597 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
598 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
599 } else {
600 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
601
602 if (mode->clock > 200000) /* range limits??? */
603 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
604 else
605 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
606 }
607
608 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
609 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
610 if (connector) {
611 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
612 struct radeon_connector_atom_dig *dig_connector =
613 radeon_connector->con_priv;
614
615 dp_clock = dig_connector->dp_clock;
616 }
617 }
618
619 if (radeon_encoder->is_mst_encoder) {
620 struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv;
621 struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv;
622
623 dp_clock = dig_connector->dp_clock;
624 }
625
626 /* use recommended ref_div for ss */
627 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
628 if (radeon_crtc->ss_enabled) {
629 if (radeon_crtc->ss.refdiv) {
630 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
631 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
632 if (ASIC_IS_AVIVO(rdev) &&
633 rdev->family != CHIP_RS780 &&
634 rdev->family != CHIP_RS880)
635 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
636 }
637 }
638 }
639
640 if (ASIC_IS_AVIVO(rdev)) {
641 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
642 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
643 adjusted_clock = mode->clock * 2;
644 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
645 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
646 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
647 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
648 } else {
649 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
650 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
651 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
652 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
653 }
654
655 /* adjust pll for deep color modes */
656 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
657 switch (bpc) {
658 case 8:
659 default:
660 break;
661 case 10:
662 clock = (clock * 5) / 4;
663 break;
664 case 12:
665 clock = (clock * 3) / 2;
666 break;
667 case 16:
668 clock = clock * 2;
669 break;
670 }
671 }
672
673 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
674 * accordingly based on the encoder/transmitter to work around
675 * special hw requirements.
676 */
677 if (ASIC_IS_DCE3(rdev)) {
678 union adjust_pixel_clock args;
679 u8 frev, crev;
680 int index;
681
682 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
683 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
684 &crev))
685 return adjusted_clock;
686
687 memset(&args, 0, sizeof(args));
688
689 switch (frev) {
690 case 1:
691 switch (crev) {
692 case 1:
693 case 2:
694 args.v1.usPixelClock = cpu_to_le16(clock / 10);
695 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
696 args.v1.ucEncodeMode = encoder_mode;
697 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
698 args.v1.ucConfig |=
699 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
700
701 atom_execute_table(rdev->mode_info.atom_context,
702 index, (uint32_t *)&args);
703 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
704 break;
705 case 3:
706 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
707 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
708 args.v3.sInput.ucEncodeMode = encoder_mode;
709 args.v3.sInput.ucDispPllConfig = 0;
710 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
711 args.v3.sInput.ucDispPllConfig |=
712 DISPPLL_CONFIG_SS_ENABLE;
713 if (ENCODER_MODE_IS_DP(encoder_mode)) {
714 args.v3.sInput.ucDispPllConfig |=
715 DISPPLL_CONFIG_COHERENT_MODE;
716 /* 16200 or 27000 */
717 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
718 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
719 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
720 if (dig->coherent_mode)
721 args.v3.sInput.ucDispPllConfig |=
722 DISPPLL_CONFIG_COHERENT_MODE;
723 if (is_duallink)
724 args.v3.sInput.ucDispPllConfig |=
725 DISPPLL_CONFIG_DUAL_LINK;
726 }
727 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
728 ENCODER_OBJECT_ID_NONE)
729 args.v3.sInput.ucExtTransmitterID =
730 radeon_encoder_get_dp_bridge_encoder_id(encoder);
731 else
732 args.v3.sInput.ucExtTransmitterID = 0;
733
734 atom_execute_table(rdev->mode_info.atom_context,
735 index, (uint32_t *)&args);
736 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
737 if (args.v3.sOutput.ucRefDiv) {
738 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
739 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
740 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
741 }
742 if (args.v3.sOutput.ucPostDiv) {
743 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
744 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
745 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
746 }
747 break;
748 default:
749 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
750 return adjusted_clock;
751 }
752 break;
753 default:
754 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
755 return adjusted_clock;
756 }
757 }
758 return adjusted_clock;
759}
760
761union set_pixel_clock {
762 SET_PIXEL_CLOCK_PS_ALLOCATION base;
763 PIXEL_CLOCK_PARAMETERS v1;
764 PIXEL_CLOCK_PARAMETERS_V2 v2;
765 PIXEL_CLOCK_PARAMETERS_V3 v3;
766 PIXEL_CLOCK_PARAMETERS_V5 v5;
767 PIXEL_CLOCK_PARAMETERS_V6 v6;
768};
769
770/* on DCE5, make sure the voltage is high enough to support the
771 * required disp clk.
772 */
773static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
774 u32 dispclk)
775{
776 u8 frev, crev;
777 int index;
778 union set_pixel_clock args;
779
780 memset(&args, 0, sizeof(args));
781
782 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
783 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
784 &crev))
785 return;
786
787 switch (frev) {
788 case 1:
789 switch (crev) {
790 case 5:
791 /* if the default dcpll clock is specified,
792 * SetPixelClock provides the dividers
793 */
794 args.v5.ucCRTC = ATOM_CRTC_INVALID;
795 args.v5.usPixelClock = cpu_to_le16(dispclk);
796 args.v5.ucPpll = ATOM_DCPLL;
797 break;
798 case 6:
799 /* if the default dcpll clock is specified,
800 * SetPixelClock provides the dividers
801 */
802 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
803 if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
804 args.v6.ucPpll = ATOM_EXT_PLL1;
805 else if (ASIC_IS_DCE6(rdev))
806 args.v6.ucPpll = ATOM_PPLL0;
807 else
808 args.v6.ucPpll = ATOM_DCPLL;
809 break;
810 default:
811 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
812 return;
813 }
814 break;
815 default:
816 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
817 return;
818 }
819 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
820}
821
822static void atombios_crtc_program_pll(struct drm_crtc *crtc,
823 u32 crtc_id,
824 int pll_id,
825 u32 encoder_mode,
826 u32 encoder_id,
827 u32 clock,
828 u32 ref_div,
829 u32 fb_div,
830 u32 frac_fb_div,
831 u32 post_div,
832 int bpc,
833 bool ss_enabled,
834 struct radeon_atom_ss *ss)
835{
836 struct drm_device *dev = crtc->dev;
837 struct radeon_device *rdev = dev->dev_private;
838 u8 frev, crev;
839 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
840 union set_pixel_clock args;
841
842 memset(&args, 0, sizeof(args));
843
844 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
845 &crev))
846 return;
847
848 switch (frev) {
849 case 1:
850 switch (crev) {
851 case 1:
852 if (clock == ATOM_DISABLE)
853 return;
854 args.v1.usPixelClock = cpu_to_le16(clock / 10);
855 args.v1.usRefDiv = cpu_to_le16(ref_div);
856 args.v1.usFbDiv = cpu_to_le16(fb_div);
857 args.v1.ucFracFbDiv = frac_fb_div;
858 args.v1.ucPostDiv = post_div;
859 args.v1.ucPpll = pll_id;
860 args.v1.ucCRTC = crtc_id;
861 args.v1.ucRefDivSrc = 1;
862 break;
863 case 2:
864 args.v2.usPixelClock = cpu_to_le16(clock / 10);
865 args.v2.usRefDiv = cpu_to_le16(ref_div);
866 args.v2.usFbDiv = cpu_to_le16(fb_div);
867 args.v2.ucFracFbDiv = frac_fb_div;
868 args.v2.ucPostDiv = post_div;
869 args.v2.ucPpll = pll_id;
870 args.v2.ucCRTC = crtc_id;
871 args.v2.ucRefDivSrc = 1;
872 break;
873 case 3:
874 args.v3.usPixelClock = cpu_to_le16(clock / 10);
875 args.v3.usRefDiv = cpu_to_le16(ref_div);
876 args.v3.usFbDiv = cpu_to_le16(fb_div);
877 args.v3.ucFracFbDiv = frac_fb_div;
878 args.v3.ucPostDiv = post_div;
879 args.v3.ucPpll = pll_id;
880 if (crtc_id == ATOM_CRTC2)
881 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
882 else
883 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
884 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
885 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
886 args.v3.ucTransmitterId = encoder_id;
887 args.v3.ucEncoderMode = encoder_mode;
888 break;
889 case 5:
890 args.v5.ucCRTC = crtc_id;
891 args.v5.usPixelClock = cpu_to_le16(clock / 10);
892 args.v5.ucRefDiv = ref_div;
893 args.v5.usFbDiv = cpu_to_le16(fb_div);
894 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
895 args.v5.ucPostDiv = post_div;
896 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
897 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
898 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
899 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
900 switch (bpc) {
901 case 8:
902 default:
903 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
904 break;
905 case 10:
906 /* yes this is correct, the atom define is wrong */
907 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
908 break;
909 case 12:
910 /* yes this is correct, the atom define is wrong */
911 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
912 break;
913 }
914 }
915 args.v5.ucTransmitterID = encoder_id;
916 args.v5.ucEncoderMode = encoder_mode;
917 args.v5.ucPpll = pll_id;
918 break;
919 case 6:
920 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
921 args.v6.ucRefDiv = ref_div;
922 args.v6.usFbDiv = cpu_to_le16(fb_div);
923 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
924 args.v6.ucPostDiv = post_div;
925 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
926 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
927 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
928 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
929 switch (bpc) {
930 case 8:
931 default:
932 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
933 break;
934 case 10:
935 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
936 break;
937 case 12:
938 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
939 break;
940 case 16:
941 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
942 break;
943 }
944 }
945 args.v6.ucTransmitterID = encoder_id;
946 args.v6.ucEncoderMode = encoder_mode;
947 args.v6.ucPpll = pll_id;
948 break;
949 default:
950 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
951 return;
952 }
953 break;
954 default:
955 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
956 return;
957 }
958
959 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
960}
961
962static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
963{
964 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
965 struct drm_device *dev = crtc->dev;
966 struct radeon_device *rdev = dev->dev_private;
967 struct radeon_encoder *radeon_encoder =
968 to_radeon_encoder(radeon_crtc->encoder);
969 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
970
971 radeon_crtc->bpc = 8;
972 radeon_crtc->ss_enabled = false;
973
974 if (radeon_encoder->is_mst_encoder) {
975 radeon_dp_mst_prepare_pll(crtc, mode);
976 } else if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
977 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
978 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
979 struct drm_connector *connector =
980 radeon_get_connector_for_encoder(radeon_crtc->encoder);
981 struct radeon_connector *radeon_connector =
982 to_radeon_connector(connector);
983 struct radeon_connector_atom_dig *dig_connector =
984 radeon_connector->con_priv;
985 int dp_clock;
986
987 /* Assign mode clock for hdmi deep color max clock limit check */
988 radeon_connector->pixelclock_for_modeset = mode->clock;
989 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
990
991 switch (encoder_mode) {
992 case ATOM_ENCODER_MODE_DP_MST:
993 case ATOM_ENCODER_MODE_DP:
994 /* DP/eDP */
995 dp_clock = dig_connector->dp_clock / 10;
996 if (ASIC_IS_DCE4(rdev))
997 radeon_crtc->ss_enabled =
998 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
999 ASIC_INTERNAL_SS_ON_DP,
1000 dp_clock);
1001 else {
1002 if (dp_clock == 16200) {
1003 radeon_crtc->ss_enabled =
1004 radeon_atombios_get_ppll_ss_info(rdev,
1005 &radeon_crtc->ss,
1006 ATOM_DP_SS_ID2);
1007 if (!radeon_crtc->ss_enabled)
1008 radeon_crtc->ss_enabled =
1009 radeon_atombios_get_ppll_ss_info(rdev,
1010 &radeon_crtc->ss,
1011 ATOM_DP_SS_ID1);
1012 } else {
1013 radeon_crtc->ss_enabled =
1014 radeon_atombios_get_ppll_ss_info(rdev,
1015 &radeon_crtc->ss,
1016 ATOM_DP_SS_ID1);
1017 }
1018 /* disable spread spectrum on DCE3 DP */
1019 radeon_crtc->ss_enabled = false;
1020 }
1021 break;
1022 case ATOM_ENCODER_MODE_LVDS:
1023 if (ASIC_IS_DCE4(rdev))
1024 radeon_crtc->ss_enabled =
1025 radeon_atombios_get_asic_ss_info(rdev,
1026 &radeon_crtc->ss,
1027 dig->lcd_ss_id,
1028 mode->clock / 10);
1029 else
1030 radeon_crtc->ss_enabled =
1031 radeon_atombios_get_ppll_ss_info(rdev,
1032 &radeon_crtc->ss,
1033 dig->lcd_ss_id);
1034 break;
1035 case ATOM_ENCODER_MODE_DVI:
1036 if (ASIC_IS_DCE4(rdev))
1037 radeon_crtc->ss_enabled =
1038 radeon_atombios_get_asic_ss_info(rdev,
1039 &radeon_crtc->ss,
1040 ASIC_INTERNAL_SS_ON_TMDS,
1041 mode->clock / 10);
1042 break;
1043 case ATOM_ENCODER_MODE_HDMI:
1044 if (ASIC_IS_DCE4(rdev))
1045 radeon_crtc->ss_enabled =
1046 radeon_atombios_get_asic_ss_info(rdev,
1047 &radeon_crtc->ss,
1048 ASIC_INTERNAL_SS_ON_HDMI,
1049 mode->clock / 10);
1050 break;
1051 default:
1052 break;
1053 }
1054 }
1055
1056 /* adjust pixel clock as needed */
1057 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
1058
1059 return true;
1060}
1061
1062static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
1063{
1064 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1065 struct drm_device *dev = crtc->dev;
1066 struct radeon_device *rdev = dev->dev_private;
1067 struct radeon_encoder *radeon_encoder =
1068 to_radeon_encoder(radeon_crtc->encoder);
1069 u32 pll_clock = mode->clock;
1070 u32 clock = mode->clock;
1071 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
1072 struct radeon_pll *pll;
1073 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
1074
1075 /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */
1076 if (ASIC_IS_DCE5(rdev) &&
1077 (encoder_mode == ATOM_ENCODER_MODE_HDMI) &&
1078 (radeon_crtc->bpc > 8))
1079 clock = radeon_crtc->adjusted_clock;
1080
1081 switch (radeon_crtc->pll_id) {
1082 case ATOM_PPLL1:
1083 pll = &rdev->clock.p1pll;
1084 break;
1085 case ATOM_PPLL2:
1086 pll = &rdev->clock.p2pll;
1087 break;
1088 case ATOM_DCPLL:
1089 case ATOM_PPLL_INVALID:
1090 default:
1091 pll = &rdev->clock.dcpll;
1092 break;
1093 }
1094
1095 /* update pll params */
1096 pll->flags = radeon_crtc->pll_flags;
1097 pll->reference_div = radeon_crtc->pll_reference_div;
1098 pll->post_div = radeon_crtc->pll_post_div;
1099
1100 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1101 /* TV seems to prefer the legacy algo on some boards */
1102 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1103 &fb_div, &frac_fb_div, &ref_div, &post_div);
1104 else if (ASIC_IS_AVIVO(rdev))
1105 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
1106 &fb_div, &frac_fb_div, &ref_div, &post_div);
1107 else
1108 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1109 &fb_div, &frac_fb_div, &ref_div, &post_div);
1110
1111 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1112 radeon_crtc->crtc_id, &radeon_crtc->ss);
1113
1114 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1115 encoder_mode, radeon_encoder->encoder_id, clock,
1116 ref_div, fb_div, frac_fb_div, post_div,
1117 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1118
1119 if (radeon_crtc->ss_enabled) {
1120 /* calculate ss amount and step size */
1121 if (ASIC_IS_DCE4(rdev)) {
1122 u32 step_size;
1123 u32 amount = (((fb_div * 10) + frac_fb_div) *
1124 (u32)radeon_crtc->ss.percentage) /
1125 (100 * (u32)radeon_crtc->ss.percentage_divider);
1126 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1127 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1128 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1129 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1130 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1131 (125 * 25 * pll->reference_freq / 100);
1132 else
1133 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1134 (125 * 25 * pll->reference_freq / 100);
1135 radeon_crtc->ss.step = step_size;
1136 }
1137
1138 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1139 radeon_crtc->crtc_id, &radeon_crtc->ss);
1140 }
1141}
1142
1143static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1144 struct drm_framebuffer *fb,
1145 int x, int y, int atomic)
1146{
1147 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1148 struct drm_device *dev = crtc->dev;
1149 struct radeon_device *rdev = dev->dev_private;
1150 struct drm_framebuffer *target_fb;
1151 struct drm_gem_object *obj;
1152 struct radeon_bo *rbo;
1153 uint64_t fb_location;
1154 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1155 unsigned bankw, bankh, mtaspect, tile_split;
1156 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1157 u32 tmp, viewport_w, viewport_h;
1158 int r;
1159 bool bypass_lut = false;
1160
1161 /* no fb bound */
1162 if (!atomic && !crtc->primary->fb) {
1163 DRM_DEBUG_KMS("No FB bound\n");
1164 return 0;
1165 }
1166
1167 if (atomic)
1168 target_fb = fb;
1169 else
1170 target_fb = crtc->primary->fb;
1171
1172 /* If atomic, assume fb object is pinned & idle & fenced and
1173 * just update base pointers
1174 */
1175 obj = target_fb->obj[0];
1176 rbo = gem_to_radeon_bo(obj);
1177 r = radeon_bo_reserve(rbo, false);
1178 if (unlikely(r != 0))
1179 return r;
1180
1181 if (atomic)
1182 fb_location = radeon_bo_gpu_offset(rbo);
1183 else {
1184 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1185 if (unlikely(r != 0)) {
1186 radeon_bo_unreserve(rbo);
1187 return -EINVAL;
1188 }
1189 }
1190
1191 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1192 radeon_bo_unreserve(rbo);
1193
1194 switch (target_fb->format->format) {
1195 case DRM_FORMAT_C8:
1196 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1197 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1198 break;
1199 case DRM_FORMAT_XRGB4444:
1200 case DRM_FORMAT_ARGB4444:
1201 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1202 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444));
1203#ifdef __BIG_ENDIAN
1204 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1205#endif
1206 break;
1207 case DRM_FORMAT_XRGB1555:
1208 case DRM_FORMAT_ARGB1555:
1209 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1210 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1211#ifdef __BIG_ENDIAN
1212 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1213#endif
1214 break;
1215 case DRM_FORMAT_BGRX5551:
1216 case DRM_FORMAT_BGRA5551:
1217 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1218 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551));
1219#ifdef __BIG_ENDIAN
1220 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1221#endif
1222 break;
1223 case DRM_FORMAT_RGB565:
1224 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1225 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1226#ifdef __BIG_ENDIAN
1227 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1228#endif
1229 break;
1230 case DRM_FORMAT_XRGB8888:
1231 case DRM_FORMAT_ARGB8888:
1232 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1233 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1234#ifdef __BIG_ENDIAN
1235 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1236#endif
1237 break;
1238 case DRM_FORMAT_XRGB2101010:
1239 case DRM_FORMAT_ARGB2101010:
1240 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1241 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010));
1242#ifdef __BIG_ENDIAN
1243 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1244#endif
1245 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1246 bypass_lut = true;
1247 break;
1248 case DRM_FORMAT_BGRX1010102:
1249 case DRM_FORMAT_BGRA1010102:
1250 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1251 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102));
1252#ifdef __BIG_ENDIAN
1253 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1254#endif
1255 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1256 bypass_lut = true;
1257 break;
1258 case DRM_FORMAT_XBGR8888:
1259 case DRM_FORMAT_ABGR8888:
1260 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1261 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1262 fb_swap = (EVERGREEN_GRPH_RED_CROSSBAR(EVERGREEN_GRPH_RED_SEL_B) |
1263 EVERGREEN_GRPH_BLUE_CROSSBAR(EVERGREEN_GRPH_BLUE_SEL_R));
1264#ifdef __BIG_ENDIAN
1265 fb_swap |= EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1266#endif
1267 break;
1268 default:
1269 DRM_ERROR("Unsupported screen format %p4cc\n",
1270 &target_fb->format->format);
1271 return -EINVAL;
1272 }
1273
1274 if (tiling_flags & RADEON_TILING_MACRO) {
1275 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1276
1277 /* Set NUM_BANKS. */
1278 if (rdev->family >= CHIP_TAHITI) {
1279 unsigned index, num_banks;
1280
1281 if (rdev->family >= CHIP_BONAIRE) {
1282 unsigned tileb, tile_split_bytes;
1283
1284 /* Calculate the macrotile mode index. */
1285 tile_split_bytes = 64 << tile_split;
1286 tileb = 8 * 8 * target_fb->format->cpp[0];
1287 tileb = min(tile_split_bytes, tileb);
1288
1289 for (index = 0; tileb > 64; index++)
1290 tileb >>= 1;
1291
1292 if (index >= 16) {
1293 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
1294 target_fb->format->cpp[0] * 8,
1295 tile_split);
1296 return -EINVAL;
1297 }
1298
1299 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1300 } else {
1301 switch (target_fb->format->cpp[0] * 8) {
1302 case 8:
1303 index = 10;
1304 break;
1305 case 16:
1306 index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
1307 break;
1308 default:
1309 case 32:
1310 index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
1311 break;
1312 }
1313
1314 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
1315 }
1316
1317 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1318 } else {
1319 /* NI and older. */
1320 if (rdev->family >= CHIP_CAYMAN)
1321 tmp = rdev->config.cayman.tile_config;
1322 else
1323 tmp = rdev->config.evergreen.tile_config;
1324
1325 switch ((tmp & 0xf0) >> 4) {
1326 case 0: /* 4 banks */
1327 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1328 break;
1329 case 1: /* 8 banks */
1330 default:
1331 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1332 break;
1333 case 2: /* 16 banks */
1334 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1335 break;
1336 }
1337 }
1338
1339 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1340 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1341 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1342 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1343 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1344 if (rdev->family >= CHIP_BONAIRE) {
1345 /* XXX need to know more about the surface tiling mode */
1346 fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
1347 }
1348 } else if (tiling_flags & RADEON_TILING_MICRO)
1349 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1350
1351 if (rdev->family >= CHIP_BONAIRE) {
1352 /* Read the pipe config from the 2D TILED SCANOUT mode.
1353 * It should be the same for the other modes too, but not all
1354 * modes set the pipe config field. */
1355 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
1356
1357 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
1358 } else if ((rdev->family == CHIP_TAHITI) ||
1359 (rdev->family == CHIP_PITCAIRN))
1360 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1361 else if ((rdev->family == CHIP_VERDE) ||
1362 (rdev->family == CHIP_OLAND) ||
1363 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */
1364 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1365
1366 switch (radeon_crtc->crtc_id) {
1367 case 0:
1368 WREG32(AVIVO_D1VGA_CONTROL, 0);
1369 break;
1370 case 1:
1371 WREG32(AVIVO_D2VGA_CONTROL, 0);
1372 break;
1373 case 2:
1374 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1375 break;
1376 case 3:
1377 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1378 break;
1379 case 4:
1380 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1381 break;
1382 case 5:
1383 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1384 break;
1385 default:
1386 break;
1387 }
1388
1389 /* Make sure surface address is updated at vertical blank rather than
1390 * horizontal blank
1391 */
1392 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);
1393
1394 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1395 upper_32_bits(fb_location));
1396 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1397 upper_32_bits(fb_location));
1398 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1399 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1400 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1401 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1402 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1403 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1404
1405 /*
1406 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1407 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1408 * retain the full precision throughout the pipeline.
1409 */
1410 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,
1411 (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0),
1412 ~EVERGREEN_LUT_10BIT_BYPASS_EN);
1413
1414 if (bypass_lut)
1415 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1416
1417 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1418 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1419 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1420 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1421 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1422 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1423
1424 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
1425 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1426 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1427
1428 if (rdev->family >= CHIP_BONAIRE)
1429 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1430 target_fb->height);
1431 else
1432 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1433 target_fb->height);
1434 x &= ~3;
1435 y &= ~1;
1436 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1437 (x << 16) | y);
1438 viewport_w = crtc->mode.hdisplay;
1439 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1440 if ((rdev->family >= CHIP_BONAIRE) &&
1441 (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE))
1442 viewport_h *= 2;
1443 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1444 (viewport_w << 16) | viewport_h);
1445
1446 /* set pageflip to happen anywhere in vblank interval */
1447 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1448
1449 if (!atomic && fb && fb != crtc->primary->fb) {
1450 rbo = gem_to_radeon_bo(fb->obj[0]);
1451 r = radeon_bo_reserve(rbo, false);
1452 if (unlikely(r != 0))
1453 return r;
1454 radeon_bo_unpin(rbo);
1455 radeon_bo_unreserve(rbo);
1456 }
1457
1458 /* Bytes per pixel may have changed */
1459 radeon_bandwidth_update(rdev);
1460
1461 return 0;
1462}
1463
1464static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1465 struct drm_framebuffer *fb,
1466 int x, int y, int atomic)
1467{
1468 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1469 struct drm_device *dev = crtc->dev;
1470 struct radeon_device *rdev = dev->dev_private;
1471 struct drm_gem_object *obj;
1472 struct radeon_bo *rbo;
1473 struct drm_framebuffer *target_fb;
1474 uint64_t fb_location;
1475 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1476 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1477 u32 viewport_w, viewport_h;
1478 int r;
1479 bool bypass_lut = false;
1480
1481 /* no fb bound */
1482 if (!atomic && !crtc->primary->fb) {
1483 DRM_DEBUG_KMS("No FB bound\n");
1484 return 0;
1485 }
1486
1487 if (atomic)
1488 target_fb = fb;
1489 else
1490 target_fb = crtc->primary->fb;
1491
1492 obj = target_fb->obj[0];
1493 rbo = gem_to_radeon_bo(obj);
1494 r = radeon_bo_reserve(rbo, false);
1495 if (unlikely(r != 0))
1496 return r;
1497
1498 /* If atomic, assume fb object is pinned & idle & fenced and
1499 * just update base pointers
1500 */
1501 if (atomic)
1502 fb_location = radeon_bo_gpu_offset(rbo);
1503 else {
1504 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1505 if (unlikely(r != 0)) {
1506 radeon_bo_unreserve(rbo);
1507 return -EINVAL;
1508 }
1509 }
1510 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1511 radeon_bo_unreserve(rbo);
1512
1513 switch (target_fb->format->format) {
1514 case DRM_FORMAT_C8:
1515 fb_format =
1516 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1517 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1518 break;
1519 case DRM_FORMAT_XRGB4444:
1520 case DRM_FORMAT_ARGB4444:
1521 fb_format =
1522 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1523 AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444;
1524#ifdef __BIG_ENDIAN
1525 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1526#endif
1527 break;
1528 case DRM_FORMAT_XRGB1555:
1529 fb_format =
1530 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1531 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1532#ifdef __BIG_ENDIAN
1533 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1534#endif
1535 break;
1536 case DRM_FORMAT_RGB565:
1537 fb_format =
1538 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1539 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1540#ifdef __BIG_ENDIAN
1541 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1542#endif
1543 break;
1544 case DRM_FORMAT_XRGB8888:
1545 case DRM_FORMAT_ARGB8888:
1546 fb_format =
1547 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1548 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1549#ifdef __BIG_ENDIAN
1550 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1551#endif
1552 break;
1553 case DRM_FORMAT_XRGB2101010:
1554 case DRM_FORMAT_ARGB2101010:
1555 fb_format =
1556 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1557 AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010;
1558#ifdef __BIG_ENDIAN
1559 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1560#endif
1561 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1562 bypass_lut = true;
1563 break;
1564 case DRM_FORMAT_XBGR8888:
1565 case DRM_FORMAT_ABGR8888:
1566 fb_format =
1567 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1568 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1569 if (rdev->family >= CHIP_R600)
1570 fb_swap =
1571 (R600_D1GRPH_RED_CROSSBAR(R600_D1GRPH_RED_SEL_B) |
1572 R600_D1GRPH_BLUE_CROSSBAR(R600_D1GRPH_BLUE_SEL_R));
1573 else /* DCE1 (R5xx) */
1574 fb_format |= AVIVO_D1GRPH_SWAP_RB;
1575#ifdef __BIG_ENDIAN
1576 fb_swap |= R600_D1GRPH_SWAP_ENDIAN_32BIT;
1577#endif
1578 break;
1579 default:
1580 DRM_ERROR("Unsupported screen format %p4cc\n",
1581 &target_fb->format->format);
1582 return -EINVAL;
1583 }
1584
1585 if (rdev->family >= CHIP_R600) {
1586 if (tiling_flags & RADEON_TILING_MACRO)
1587 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1588 else if (tiling_flags & RADEON_TILING_MICRO)
1589 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1590 } else {
1591 if (tiling_flags & RADEON_TILING_MACRO)
1592 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1593
1594 if (tiling_flags & RADEON_TILING_MICRO)
1595 fb_format |= AVIVO_D1GRPH_TILED;
1596 }
1597
1598 if (radeon_crtc->crtc_id == 0)
1599 WREG32(AVIVO_D1VGA_CONTROL, 0);
1600 else
1601 WREG32(AVIVO_D2VGA_CONTROL, 0);
1602
1603 /* Make sure surface address is update at vertical blank rather than
1604 * horizontal blank
1605 */
1606 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);
1607
1608 if (rdev->family >= CHIP_RV770) {
1609 if (radeon_crtc->crtc_id) {
1610 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1611 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1612 } else {
1613 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1614 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1615 }
1616 }
1617 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1618 (u32) fb_location);
1619 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1620 radeon_crtc->crtc_offset, (u32) fb_location);
1621 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1622 if (rdev->family >= CHIP_R600)
1623 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1624
1625 /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */
1626 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,
1627 (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN);
1628
1629 if (bypass_lut)
1630 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1631
1632 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1633 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1634 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1635 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1636 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1637 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1638
1639 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
1640 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1641 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1642
1643 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1644 target_fb->height);
1645 x &= ~3;
1646 y &= ~1;
1647 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1648 (x << 16) | y);
1649 viewport_w = crtc->mode.hdisplay;
1650 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1651 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1652 (viewport_w << 16) | viewport_h);
1653
1654 /* set pageflip to happen only at start of vblank interval (front porch) */
1655 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1656
1657 if (!atomic && fb && fb != crtc->primary->fb) {
1658 rbo = gem_to_radeon_bo(fb->obj[0]);
1659 r = radeon_bo_reserve(rbo, false);
1660 if (unlikely(r != 0))
1661 return r;
1662 radeon_bo_unpin(rbo);
1663 radeon_bo_unreserve(rbo);
1664 }
1665
1666 /* Bytes per pixel may have changed */
1667 radeon_bandwidth_update(rdev);
1668
1669 return 0;
1670}
1671
1672int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1673 struct drm_framebuffer *old_fb)
1674{
1675 struct drm_device *dev = crtc->dev;
1676 struct radeon_device *rdev = dev->dev_private;
1677
1678 if (ASIC_IS_DCE4(rdev))
1679 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1680 else if (ASIC_IS_AVIVO(rdev))
1681 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1682 else
1683 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1684}
1685
1686int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1687 struct drm_framebuffer *fb,
1688 int x, int y, enum mode_set_atomic state)
1689{
1690 struct drm_device *dev = crtc->dev;
1691 struct radeon_device *rdev = dev->dev_private;
1692
1693 if (ASIC_IS_DCE4(rdev))
1694 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1695 else if (ASIC_IS_AVIVO(rdev))
1696 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1697 else
1698 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1699}
1700
1701/* properly set additional regs when using atombios */
1702static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1703{
1704 struct drm_device *dev = crtc->dev;
1705 struct radeon_device *rdev = dev->dev_private;
1706 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1707 u32 disp_merge_cntl;
1708
1709 switch (radeon_crtc->crtc_id) {
1710 case 0:
1711 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1712 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1713 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1714 break;
1715 case 1:
1716 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1717 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1718 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1719 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1720 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1721 break;
1722 }
1723}
1724
1725/**
1726 * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1727 *
1728 * @crtc: drm crtc
1729 *
1730 * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1731 */
1732static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1733{
1734 struct drm_device *dev = crtc->dev;
1735 struct drm_crtc *test_crtc;
1736 struct radeon_crtc *test_radeon_crtc;
1737 u32 pll_in_use = 0;
1738
1739 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1740 if (crtc == test_crtc)
1741 continue;
1742
1743 test_radeon_crtc = to_radeon_crtc(test_crtc);
1744 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1745 pll_in_use |= (1 << test_radeon_crtc->pll_id);
1746 }
1747 return pll_in_use;
1748}
1749
1750/**
1751 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1752 *
1753 * @crtc: drm crtc
1754 *
1755 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1756 * also in DP mode. For DP, a single PPLL can be used for all DP
1757 * crtcs/encoders.
1758 */
1759static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1760{
1761 struct drm_device *dev = crtc->dev;
1762 struct radeon_device *rdev = dev->dev_private;
1763 struct drm_crtc *test_crtc;
1764 struct radeon_crtc *test_radeon_crtc;
1765
1766 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1767 if (crtc == test_crtc)
1768 continue;
1769 test_radeon_crtc = to_radeon_crtc(test_crtc);
1770 if (test_radeon_crtc->encoder &&
1771 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1772 /* PPLL2 is exclusive to UNIPHYA on DCE61 */
1773 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1774 test_radeon_crtc->pll_id == ATOM_PPLL2)
1775 continue;
1776 /* for DP use the same PLL for all */
1777 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1778 return test_radeon_crtc->pll_id;
1779 }
1780 }
1781 return ATOM_PPLL_INVALID;
1782}
1783
1784/**
1785 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1786 *
1787 * @crtc: drm crtc
1788 *
1789 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1790 * be shared (i.e., same clock).
1791 */
1792static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
1793{
1794 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1795 struct drm_device *dev = crtc->dev;
1796 struct radeon_device *rdev = dev->dev_private;
1797 struct drm_crtc *test_crtc;
1798 struct radeon_crtc *test_radeon_crtc;
1799 u32 adjusted_clock, test_adjusted_clock;
1800
1801 adjusted_clock = radeon_crtc->adjusted_clock;
1802
1803 if (adjusted_clock == 0)
1804 return ATOM_PPLL_INVALID;
1805
1806 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1807 if (crtc == test_crtc)
1808 continue;
1809 test_radeon_crtc = to_radeon_crtc(test_crtc);
1810 if (test_radeon_crtc->encoder &&
1811 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1812 /* PPLL2 is exclusive to UNIPHYA on DCE61 */
1813 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1814 test_radeon_crtc->pll_id == ATOM_PPLL2)
1815 continue;
1816 /* check if we are already driving this connector with another crtc */
1817 if (test_radeon_crtc->connector == radeon_crtc->connector) {
1818 /* if we are, return that pll */
1819 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1820 return test_radeon_crtc->pll_id;
1821 }
1822 /* for non-DP check the clock */
1823 test_adjusted_clock = test_radeon_crtc->adjusted_clock;
1824 if ((crtc->mode.clock == test_crtc->mode.clock) &&
1825 (adjusted_clock == test_adjusted_clock) &&
1826 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
1827 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
1828 return test_radeon_crtc->pll_id;
1829 }
1830 }
1831 return ATOM_PPLL_INVALID;
1832}
1833
1834/**
1835 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1836 *
1837 * @crtc: drm crtc
1838 *
1839 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1840 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1841 * monitors a dedicated PPLL must be used. If a particular board has
1842 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1843 * as there is no need to program the PLL itself. If we are not able to
1844 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1845 * avoid messing up an existing monitor.
1846 *
1847 * Asic specific PLL information
1848 *
1849 * DCE 8.x
1850 * KB/KV
1851 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1852 * CI
1853 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1854 *
1855 * DCE 6.1
1856 * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1857 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1858 *
1859 * DCE 6.0
1860 * - PPLL0 is available to all UNIPHY (DP only)
1861 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1862 *
1863 * DCE 5.0
1864 * - DCPLL is available to all UNIPHY (DP only)
1865 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1866 *
1867 * DCE 3.0/4.0/4.1
1868 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1869 *
1870 */
1871static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1872{
1873 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1874 struct drm_device *dev = crtc->dev;
1875 struct radeon_device *rdev = dev->dev_private;
1876 struct radeon_encoder *radeon_encoder =
1877 to_radeon_encoder(radeon_crtc->encoder);
1878 u32 pll_in_use;
1879 int pll;
1880
1881 if (ASIC_IS_DCE8(rdev)) {
1882 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1883 if (rdev->clock.dp_extclk)
1884 /* skip PPLL programming if using ext clock */
1885 return ATOM_PPLL_INVALID;
1886 else {
1887 /* use the same PPLL for all DP monitors */
1888 pll = radeon_get_shared_dp_ppll(crtc);
1889 if (pll != ATOM_PPLL_INVALID)
1890 return pll;
1891 }
1892 } else {
1893 /* use the same PPLL for all monitors with the same clock */
1894 pll = radeon_get_shared_nondp_ppll(crtc);
1895 if (pll != ATOM_PPLL_INVALID)
1896 return pll;
1897 }
1898 /* otherwise, pick one of the plls */
1899 if ((rdev->family == CHIP_KABINI) ||
1900 (rdev->family == CHIP_MULLINS)) {
1901 /* KB/ML has PPLL1 and PPLL2 */
1902 pll_in_use = radeon_get_pll_use_mask(crtc);
1903 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1904 return ATOM_PPLL2;
1905 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1906 return ATOM_PPLL1;
1907 DRM_ERROR("unable to allocate a PPLL\n");
1908 return ATOM_PPLL_INVALID;
1909 } else {
1910 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
1911 pll_in_use = radeon_get_pll_use_mask(crtc);
1912 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1913 return ATOM_PPLL2;
1914 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1915 return ATOM_PPLL1;
1916 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1917 return ATOM_PPLL0;
1918 DRM_ERROR("unable to allocate a PPLL\n");
1919 return ATOM_PPLL_INVALID;
1920 }
1921 } else if (ASIC_IS_DCE61(rdev)) {
1922 struct radeon_encoder_atom_dig *dig =
1923 radeon_encoder->enc_priv;
1924
1925 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1926 (dig->linkb == false))
1927 /* UNIPHY A uses PPLL2 */
1928 return ATOM_PPLL2;
1929 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1930 /* UNIPHY B/C/D/E/F */
1931 if (rdev->clock.dp_extclk)
1932 /* skip PPLL programming if using ext clock */
1933 return ATOM_PPLL_INVALID;
1934 else {
1935 /* use the same PPLL for all DP monitors */
1936 pll = radeon_get_shared_dp_ppll(crtc);
1937 if (pll != ATOM_PPLL_INVALID)
1938 return pll;
1939 }
1940 } else {
1941 /* use the same PPLL for all monitors with the same clock */
1942 pll = radeon_get_shared_nondp_ppll(crtc);
1943 if (pll != ATOM_PPLL_INVALID)
1944 return pll;
1945 }
1946 /* UNIPHY B/C/D/E/F */
1947 pll_in_use = radeon_get_pll_use_mask(crtc);
1948 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1949 return ATOM_PPLL0;
1950 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1951 return ATOM_PPLL1;
1952 DRM_ERROR("unable to allocate a PPLL\n");
1953 return ATOM_PPLL_INVALID;
1954 } else if (ASIC_IS_DCE41(rdev)) {
1955 /* Don't share PLLs on DCE4.1 chips */
1956 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1957 if (rdev->clock.dp_extclk)
1958 /* skip PPLL programming if using ext clock */
1959 return ATOM_PPLL_INVALID;
1960 }
1961 pll_in_use = radeon_get_pll_use_mask(crtc);
1962 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1963 return ATOM_PPLL1;
1964 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1965 return ATOM_PPLL2;
1966 DRM_ERROR("unable to allocate a PPLL\n");
1967 return ATOM_PPLL_INVALID;
1968 } else if (ASIC_IS_DCE4(rdev)) {
1969 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1970 * depending on the asic:
1971 * DCE4: PPLL or ext clock
1972 * DCE5: PPLL, DCPLL, or ext clock
1973 * DCE6: PPLL, PPLL0, or ext clock
1974 *
1975 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1976 * PPLL/DCPLL programming and only program the DP DTO for the
1977 * crtc virtual pixel clock.
1978 */
1979 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1980 if (rdev->clock.dp_extclk)
1981 /* skip PPLL programming if using ext clock */
1982 return ATOM_PPLL_INVALID;
1983 else if (ASIC_IS_DCE6(rdev))
1984 /* use PPLL0 for all DP */
1985 return ATOM_PPLL0;
1986 else if (ASIC_IS_DCE5(rdev))
1987 /* use DCPLL for all DP */
1988 return ATOM_DCPLL;
1989 else {
1990 /* use the same PPLL for all DP monitors */
1991 pll = radeon_get_shared_dp_ppll(crtc);
1992 if (pll != ATOM_PPLL_INVALID)
1993 return pll;
1994 }
1995 } else {
1996 /* use the same PPLL for all monitors with the same clock */
1997 pll = radeon_get_shared_nondp_ppll(crtc);
1998 if (pll != ATOM_PPLL_INVALID)
1999 return pll;
2000 }
2001 /* all other cases */
2002 pll_in_use = radeon_get_pll_use_mask(crtc);
2003 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2004 return ATOM_PPLL1;
2005 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2006 return ATOM_PPLL2;
2007 DRM_ERROR("unable to allocate a PPLL\n");
2008 return ATOM_PPLL_INVALID;
2009 } else {
2010 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
2011 /* some atombios (observed in some DCE2/DCE3) code have a bug,
2012 * the matching btw pll and crtc is done through
2013 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
2014 * pll (1 or 2) to select which register to write. ie if using
2015 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
2016 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
2017 * choose which value to write. Which is reverse order from
2018 * register logic. So only case that works is when pllid is
2019 * same as crtcid or when both pll and crtc are enabled and
2020 * both use same clock.
2021 *
2022 * So just return crtc id as if crtc and pll were hard linked
2023 * together even if they aren't
2024 */
2025 return radeon_crtc->crtc_id;
2026 }
2027}
2028
2029void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
2030{
2031 /* always set DCPLL */
2032 if (ASIC_IS_DCE6(rdev))
2033 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2034 else if (ASIC_IS_DCE4(rdev)) {
2035 struct radeon_atom_ss ss;
2036 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
2037 ASIC_INTERNAL_SS_ON_DCPLL,
2038 rdev->clock.default_dispclk);
2039 if (ss_enabled)
2040 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
2041 /* XXX: DCE5, make sure voltage, dispclk is high enough */
2042 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2043 if (ss_enabled)
2044 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
2045 }
2046
2047}
2048
2049int atombios_crtc_mode_set(struct drm_crtc *crtc,
2050 struct drm_display_mode *mode,
2051 struct drm_display_mode *adjusted_mode,
2052 int x, int y, struct drm_framebuffer *old_fb)
2053{
2054 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2055 struct drm_device *dev = crtc->dev;
2056 struct radeon_device *rdev = dev->dev_private;
2057 struct radeon_encoder *radeon_encoder =
2058 to_radeon_encoder(radeon_crtc->encoder);
2059 bool is_tvcv = false;
2060
2061 if (radeon_encoder->active_device &
2062 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2063 is_tvcv = true;
2064
2065 if (!radeon_crtc->adjusted_clock)
2066 return -EINVAL;
2067
2068 atombios_crtc_set_pll(crtc, adjusted_mode);
2069
2070 if (ASIC_IS_DCE4(rdev))
2071 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2072 else if (ASIC_IS_AVIVO(rdev)) {
2073 if (is_tvcv)
2074 atombios_crtc_set_timing(crtc, adjusted_mode);
2075 else
2076 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2077 } else {
2078 atombios_crtc_set_timing(crtc, adjusted_mode);
2079 if (radeon_crtc->crtc_id == 0)
2080 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2081 radeon_legacy_atom_fixup(crtc);
2082 }
2083 atombios_crtc_set_base(crtc, x, y, old_fb);
2084 atombios_overscan_setup(crtc, mode, adjusted_mode);
2085 atombios_scaler_setup(crtc);
2086 radeon_cursor_reset(crtc);
2087 /* update the hw version fpr dpm */
2088 radeon_crtc->hw_mode = *adjusted_mode;
2089
2090 return 0;
2091}
2092
2093static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
2094 const struct drm_display_mode *mode,
2095 struct drm_display_mode *adjusted_mode)
2096{
2097 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2098 struct drm_device *dev = crtc->dev;
2099 struct drm_encoder *encoder;
2100
2101 /* assign the encoder to the radeon crtc to avoid repeated lookups later */
2102 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2103 if (encoder->crtc == crtc) {
2104 radeon_crtc->encoder = encoder;
2105 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
2106 break;
2107 }
2108 }
2109 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
2110 radeon_crtc->encoder = NULL;
2111 radeon_crtc->connector = NULL;
2112 return false;
2113 }
2114 if (radeon_crtc->encoder) {
2115 struct radeon_encoder *radeon_encoder =
2116 to_radeon_encoder(radeon_crtc->encoder);
2117
2118 radeon_crtc->output_csc = radeon_encoder->output_csc;
2119 }
2120 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2121 return false;
2122 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
2123 return false;
2124 /* pick pll */
2125 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
2126 /* if we can't get a PPLL for a non-DP encoder, fail */
2127 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
2128 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
2129 return false;
2130
2131 return true;
2132}
2133
2134static void atombios_crtc_prepare(struct drm_crtc *crtc)
2135{
2136 struct drm_device *dev = crtc->dev;
2137 struct radeon_device *rdev = dev->dev_private;
2138
2139 /* disable crtc pair power gating before programming */
2140 if (ASIC_IS_DCE6(rdev))
2141 atombios_powergate_crtc(crtc, ATOM_DISABLE);
2142
2143 atombios_lock_crtc(crtc, ATOM_ENABLE);
2144 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2145}
2146
2147static void atombios_crtc_commit(struct drm_crtc *crtc)
2148{
2149 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2150 atombios_lock_crtc(crtc, ATOM_DISABLE);
2151}
2152
2153static void atombios_crtc_disable(struct drm_crtc *crtc)
2154{
2155 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2156 struct drm_device *dev = crtc->dev;
2157 struct radeon_device *rdev = dev->dev_private;
2158 struct radeon_atom_ss ss;
2159 int i;
2160
2161 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2162 if (crtc->primary->fb) {
2163 int r;
2164 struct radeon_bo *rbo;
2165
2166 rbo = gem_to_radeon_bo(crtc->primary->fb->obj[0]);
2167 r = radeon_bo_reserve(rbo, false);
2168 if (unlikely(r))
2169 DRM_ERROR("failed to reserve rbo before unpin\n");
2170 else {
2171 radeon_bo_unpin(rbo);
2172 radeon_bo_unreserve(rbo);
2173 }
2174 }
2175 /* disable the GRPH */
2176 if (ASIC_IS_DCE4(rdev))
2177 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2178 else if (ASIC_IS_AVIVO(rdev))
2179 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2180
2181 if (ASIC_IS_DCE6(rdev))
2182 atombios_powergate_crtc(crtc, ATOM_ENABLE);
2183
2184 for (i = 0; i < rdev->num_crtc; i++) {
2185 if (rdev->mode_info.crtcs[i] &&
2186 rdev->mode_info.crtcs[i]->enabled &&
2187 i != radeon_crtc->crtc_id &&
2188 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
2189 /* one other crtc is using this pll don't turn
2190 * off the pll
2191 */
2192 goto done;
2193 }
2194 }
2195
2196 switch (radeon_crtc->pll_id) {
2197 case ATOM_PPLL1:
2198 case ATOM_PPLL2:
2199 /* disable the ppll */
2200 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2201 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2202 break;
2203 case ATOM_PPLL0:
2204 /* disable the ppll */
2205 if ((rdev->family == CHIP_ARUBA) ||
2206 (rdev->family == CHIP_KAVERI) ||
2207 (rdev->family == CHIP_BONAIRE) ||
2208 (rdev->family == CHIP_HAWAII))
2209 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2210 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2211 break;
2212 default:
2213 break;
2214 }
2215done:
2216 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2217 radeon_crtc->adjusted_clock = 0;
2218 radeon_crtc->encoder = NULL;
2219 radeon_crtc->connector = NULL;
2220}
2221
2222static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
2223 .dpms = atombios_crtc_dpms,
2224 .mode_fixup = atombios_crtc_mode_fixup,
2225 .mode_set = atombios_crtc_mode_set,
2226 .mode_set_base = atombios_crtc_set_base,
2227 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
2228 .prepare = atombios_crtc_prepare,
2229 .commit = atombios_crtc_commit,
2230 .disable = atombios_crtc_disable,
2231 .get_scanout_position = radeon_get_crtc_scanout_position,
2232};
2233
2234void radeon_atombios_init_crtc(struct drm_device *dev,
2235 struct radeon_crtc *radeon_crtc)
2236{
2237 struct radeon_device *rdev = dev->dev_private;
2238
2239 if (ASIC_IS_DCE4(rdev)) {
2240 switch (radeon_crtc->crtc_id) {
2241 case 0:
2242 default:
2243 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
2244 break;
2245 case 1:
2246 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
2247 break;
2248 case 2:
2249 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
2250 break;
2251 case 3:
2252 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
2253 break;
2254 case 4:
2255 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
2256 break;
2257 case 5:
2258 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
2259 break;
2260 }
2261 } else {
2262 if (radeon_crtc->crtc_id == 1)
2263 radeon_crtc->crtc_offset =
2264 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
2265 else
2266 radeon_crtc->crtc_offset = 0;
2267 }
2268 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2269 radeon_crtc->adjusted_clock = 0;
2270 radeon_crtc->encoder = NULL;
2271 radeon_crtc->connector = NULL;
2272 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
2273}