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1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2/*
3 * core.h - DesignWare HS OTG Controller common declarations
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#ifndef __DWC2_CORE_H__
39#define __DWC2_CORE_H__
40
41#include <linux/acpi.h>
42#include <linux/phy/phy.h>
43#include <linux/regulator/consumer.h>
44#include <linux/usb/gadget.h>
45#include <linux/usb/otg.h>
46#include <linux/usb/phy.h>
47#include "hw.h"
48
49/*
50 * Suggested defines for tracers:
51 * - no_printk: Disable tracing
52 * - pr_info: Print this info to the console
53 * - trace_printk: Print this info to trace buffer (good for verbose logging)
54 */
55
56#define DWC2_TRACE_SCHEDULER no_printk
57#define DWC2_TRACE_SCHEDULER_VB no_printk
58
59/* Detailed scheduler tracing, but won't overwhelm console */
60#define dwc2_sch_dbg(hsotg, fmt, ...) \
61 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \
62 dev_name(hsotg->dev), ##__VA_ARGS__)
63
64/* Verbose scheduler tracing */
65#define dwc2_sch_vdbg(hsotg, fmt, ...) \
66 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \
67 dev_name(hsotg->dev), ##__VA_ARGS__)
68
69/* Maximum number of Endpoints/HostChannels */
70#define MAX_EPS_CHANNELS 16
71
72/* dwc2-hsotg declarations */
73static const char * const dwc2_hsotg_supply_names[] = {
74 "vusb_d", /* digital USB supply, 1.2V */
75 "vusb_a", /* analog USB supply, 1.1V */
76};
77
78#define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names)
79
80/*
81 * EP0_MPS_LIMIT
82 *
83 * Unfortunately there seems to be a limit of the amount of data that can
84 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
85 * packets (which practically means 1 packet and 63 bytes of data) when the
86 * MPS is set to 64.
87 *
88 * This means if we are wanting to move >127 bytes of data, we need to
89 * split the transactions up, but just doing one packet at a time does
90 * not work (this may be an implicit DATA0 PID on first packet of the
91 * transaction) and doing 2 packets is outside the controller's limits.
92 *
93 * If we try to lower the MPS size for EP0, then no transfers work properly
94 * for EP0, and the system will fail basic enumeration. As no cause for this
95 * has currently been found, we cannot support any large IN transfers for
96 * EP0.
97 */
98#define EP0_MPS_LIMIT 64
99
100struct dwc2_hsotg;
101struct dwc2_hsotg_req;
102
103/**
104 * struct dwc2_hsotg_ep - driver endpoint definition.
105 * @ep: The gadget layer representation of the endpoint.
106 * @name: The driver generated name for the endpoint.
107 * @queue: Queue of requests for this endpoint.
108 * @parent: Reference back to the parent device structure.
109 * @req: The current request that the endpoint is processing. This is
110 * used to indicate an request has been loaded onto the endpoint
111 * and has yet to be completed (maybe due to data move, or simply
112 * awaiting an ack from the core all the data has been completed).
113 * @debugfs: File entry for debugfs file for this endpoint.
114 * @dir_in: Set to true if this endpoint is of the IN direction, which
115 * means that it is sending data to the Host.
116 * @map_dir: Set to the value of dir_in when the DMA buffer is mapped.
117 * @index: The index for the endpoint registers.
118 * @mc: Multi Count - number of transactions per microframe
119 * @interval: Interval for periodic endpoints, in frames or microframes.
120 * @name: The name array passed to the USB core.
121 * @halted: Set if the endpoint has been halted.
122 * @periodic: Set if this is a periodic ep, such as Interrupt
123 * @isochronous: Set if this is a isochronous ep
124 * @send_zlp: Set if we need to send a zero-length packet.
125 * @desc_list_dma: The DMA address of descriptor chain currently in use.
126 * @desc_list: Pointer to descriptor DMA chain head currently in use.
127 * @desc_count: Count of entries within the DMA descriptor chain of EP.
128 * @next_desc: index of next free descriptor in the ISOC chain under SW control.
129 * @compl_desc: index of next descriptor to be completed by xFerComplete
130 * @total_data: The total number of data bytes done.
131 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
132 * @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0.
133 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
134 * @last_load: The offset of data for the last start of request.
135 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
136 * @target_frame: Targeted frame num to setup next ISOC transfer
137 * @frame_overrun: Indicates SOF number overrun in DSTS
138 *
139 * This is the driver's state for each registered endpoint, allowing it
140 * to keep track of transactions that need doing. Each endpoint has a
141 * lock to protect the state, to try and avoid using an overall lock
142 * for the host controller as much as possible.
143 *
144 * For periodic IN endpoints, we have fifo_size and fifo_load to try
145 * and keep track of the amount of data in the periodic FIFO for each
146 * of these as we don't have a status register that tells us how much
147 * is in each of them. (note, this may actually be useless information
148 * as in shared-fifo mode periodic in acts like a single-frame packet
149 * buffer than a fifo)
150 */
151struct dwc2_hsotg_ep {
152 struct usb_ep ep;
153 struct list_head queue;
154 struct dwc2_hsotg *parent;
155 struct dwc2_hsotg_req *req;
156 struct dentry *debugfs;
157
158 unsigned long total_data;
159 unsigned int size_loaded;
160 unsigned int last_load;
161 unsigned int fifo_load;
162 unsigned short fifo_size;
163 unsigned short fifo_index;
164
165 unsigned char dir_in;
166 unsigned char map_dir;
167 unsigned char index;
168 unsigned char mc;
169 u16 interval;
170
171 unsigned int halted:1;
172 unsigned int periodic:1;
173 unsigned int isochronous:1;
174 unsigned int send_zlp:1;
175 unsigned int target_frame;
176#define TARGET_FRAME_INITIAL 0xFFFFFFFF
177 bool frame_overrun;
178
179 dma_addr_t desc_list_dma;
180 struct dwc2_dma_desc *desc_list;
181 u8 desc_count;
182
183 unsigned int next_desc;
184 unsigned int compl_desc;
185
186 char name[10];
187};
188
189/**
190 * struct dwc2_hsotg_req - data transfer request
191 * @req: The USB gadget request
192 * @queue: The list of requests for the endpoint this is queued for.
193 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
194 */
195struct dwc2_hsotg_req {
196 struct usb_request req;
197 struct list_head queue;
198 void *saved_req_buf;
199};
200
201#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
202 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
203#define call_gadget(_hs, _entry) \
204do { \
205 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
206 (_hs)->driver && (_hs)->driver->_entry) { \
207 spin_unlock(&_hs->lock); \
208 (_hs)->driver->_entry(&(_hs)->gadget); \
209 spin_lock(&_hs->lock); \
210 } \
211} while (0)
212#else
213#define call_gadget(_hs, _entry) do {} while (0)
214#endif
215
216struct dwc2_hsotg;
217struct dwc2_host_chan;
218
219/* Device States */
220enum dwc2_lx_state {
221 DWC2_L0, /* On state */
222 DWC2_L1, /* LPM sleep state */
223 DWC2_L2, /* USB suspend state */
224 DWC2_L3, /* Off state */
225};
226
227/* Gadget ep0 states */
228enum dwc2_ep0_state {
229 DWC2_EP0_SETUP,
230 DWC2_EP0_DATA_IN,
231 DWC2_EP0_DATA_OUT,
232 DWC2_EP0_STATUS_IN,
233 DWC2_EP0_STATUS_OUT,
234};
235
236/**
237 * struct dwc2_core_params - Parameters for configuring the core
238 *
239 * @otg_cap: Specifies the OTG capabilities.
240 * 0 - HNP and SRP capable
241 * 1 - SRP Only capable
242 * 2 - No HNP/SRP capable (always available)
243 * Defaults to best available option (0, 1, then 2)
244 * @host_dma: Specifies whether to use slave or DMA mode for accessing
245 * the data FIFOs. The driver will automatically detect the
246 * value for this parameter if none is specified.
247 * 0 - Slave (always available)
248 * 1 - DMA (default, if available)
249 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
250 * address DMA mode or descriptor DMA mode for accessing
251 * the data FIFOs. The driver will automatically detect the
252 * value for this if none is specified.
253 * 0 - Address DMA
254 * 1 - Descriptor DMA (default, if available)
255 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
256 * address DMA mode or descriptor DMA mode for accessing
257 * the data FIFOs in Full Speed mode only. The driver
258 * will automatically detect the value for this if none is
259 * specified.
260 * 0 - Address DMA
261 * 1 - Descriptor DMA in FS (default, if available)
262 * @speed: Specifies the maximum speed of operation in host and
263 * device mode. The actual speed depends on the speed of
264 * the attached device and the value of phy_type.
265 * 0 - High Speed
266 * (default when phy_type is UTMI+ or ULPI)
267 * 1 - Full Speed
268 * (default when phy_type is Full Speed)
269 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
270 * 1 - Allow dynamic FIFO sizing (default, if available)
271 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
272 * are enabled for non-periodic IN endpoints in device
273 * mode.
274 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
275 * dynamic FIFO sizing is enabled
276 * 16 to 32768
277 * Actual maximum value is autodetected and also
278 * the default.
279 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
280 * in host mode when dynamic FIFO sizing is enabled
281 * 16 to 32768
282 * Actual maximum value is autodetected and also
283 * the default.
284 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
285 * host mode when dynamic FIFO sizing is enabled
286 * 16 to 32768
287 * Actual maximum value is autodetected and also
288 * the default.
289 * @max_transfer_size: The maximum transfer size supported, in bytes
290 * 2047 to 65,535
291 * Actual maximum value is autodetected and also
292 * the default.
293 * @max_packet_count: The maximum number of packets in a transfer
294 * 15 to 511
295 * Actual maximum value is autodetected and also
296 * the default.
297 * @host_channels: The number of host channel registers to use
298 * 1 to 16
299 * Actual maximum value is autodetected and also
300 * the default.
301 * @phy_type: Specifies the type of PHY interface to use. By default,
302 * the driver will automatically detect the phy_type.
303 * 0 - Full Speed Phy
304 * 1 - UTMI+ Phy
305 * 2 - ULPI Phy
306 * Defaults to best available option (2, 1, then 0)
307 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
308 * is applicable for a phy_type of UTMI+ or ULPI. (For a
309 * ULPI phy_type, this parameter indicates the data width
310 * between the MAC and the ULPI Wrapper.) Also, this
311 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
312 * parameter was set to "8 and 16 bits", meaning that the
313 * core has been configured to work at either data path
314 * width.
315 * 8 or 16 (default 16 if available)
316 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
317 * data rate. This parameter is only applicable if phy_type
318 * is ULPI.
319 * 0 - single data rate ULPI interface with 8 bit wide
320 * data bus (default)
321 * 1 - double data rate ULPI interface with 4 bit wide
322 * data bus
323 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
324 * external supply to drive the VBus
325 * 0 - Internal supply (default)
326 * 1 - External supply
327 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
328 * speed PHY. This parameter is only applicable if phy_type
329 * is FS.
330 * 0 - No (default)
331 * 1 - Yes
332 * @ipg_isoc_en: Indicates the IPG supports is enabled or disabled.
333 * 0 - Disable (default)
334 * 1 - Enable
335 * @acg_enable: For enabling Active Clock Gating in the controller
336 * 0 - No
337 * 1 - Yes
338 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
339 * 0 - No (default)
340 * 1 - Yes
341 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
342 * when attached to a Full Speed or Low Speed device in
343 * host mode.
344 * 0 - Don't support low power mode (default)
345 * 1 - Support low power mode
346 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
347 * when connected to a Low Speed device in host
348 * mode. This parameter is applicable only if
349 * host_support_fs_ls_low_power is enabled.
350 * 0 - 48 MHz
351 * (default when phy_type is UTMI+ or ULPI)
352 * 1 - 6 MHz
353 * (default when phy_type is Full Speed)
354 * @oc_disable: Flag to disable overcurrent condition.
355 * 0 - Allow overcurrent condition to get detected
356 * 1 - Disable overcurrent condtion to get detected
357 * @ts_dline: Enable Term Select Dline pulsing
358 * 0 - No (default)
359 * 1 - Yes
360 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
361 * 0 - No (default for core < 2.92a)
362 * 1 - Yes (default for core >= 2.92a)
363 * @ahbcfg: This field allows the default value of the GAHBCFG
364 * register to be overridden
365 * -1 - GAHBCFG value will be set to 0x06
366 * (INCR, default)
367 * all others - GAHBCFG value will be overridden with
368 * this value
369 * Not all bits can be controlled like this, the
370 * bits defined by GAHBCFG_CTRL_MASK are controlled
371 * by the driver and are ignored in this
372 * configuration value.
373 * @uframe_sched: True to enable the microframe scheduler
374 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
375 * Disable CONIDSTSCHNG controller interrupt in such
376 * case.
377 * 0 - No (default)
378 * 1 - Yes
379 * @power_down: Specifies whether the controller support power_down.
380 * If power_down is enabled, the controller will enter
381 * power_down in both peripheral and host mode when
382 * needed.
383 * 0 - No (default)
384 * 1 - Partial power down
385 * 2 - Hibernation
386 * @no_clock_gating: Specifies whether to avoid clock gating feature.
387 * 0 - No (use clock gating)
388 * 1 - Yes (avoid it)
389 * @lpm: Enable LPM support.
390 * 0 - No
391 * 1 - Yes
392 * @lpm_clock_gating: Enable core PHY clock gating.
393 * 0 - No
394 * 1 - Yes
395 * @besl: Enable LPM Errata support.
396 * 0 - No
397 * 1 - Yes
398 * @hird_threshold_en: HIRD or HIRD Threshold enable.
399 * 0 - No
400 * 1 - Yes
401 * @hird_threshold: Value of BESL or HIRD Threshold.
402 * @ref_clk_per: Indicates in terms of pico seconds the period
403 * of ref_clk.
404 * 62500 - 16MHz
405 * 58823 - 17MHz
406 * 52083 - 19.2MHz
407 * 50000 - 20MHz
408 * 41666 - 24MHz
409 * 33333 - 30MHz (default)
410 * 25000 - 40MHz
411 * @sof_cnt_wkup_alert: Indicates in term of number of SOF's after which
412 * the controller should generate an interrupt if the
413 * device had been in L1 state until that period.
414 * This is used by SW to initiate Remote WakeUp in the
415 * controller so as to sync to the uF number from the host.
416 * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO
417 * register.
418 * 0 - Deactivate the transceiver (default)
419 * 1 - Activate the transceiver
420 * @activate_stm_id_vb_detection: Activate external ID pin and Vbus level
421 * detection using GGPIO register.
422 * 0 - Deactivate the external level detection (default)
423 * 1 - Activate the external level detection
424 * @g_dma: Enables gadget dma usage (default: autodetect).
425 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect).
426 * @g_rx_fifo_size: The periodic rx fifo size for the device, in
427 * DWORDS from 16-32768 (default: 2048 if
428 * possible, otherwise autodetect).
429 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in
430 * DWORDS from 16-32768 (default: 1024 if
431 * possible, otherwise autodetect).
432 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo
433 * mode. Each value corresponds to one EP
434 * starting from EP1 (max 15 values). Sizes are
435 * in DWORDS with possible values from
436 * 16-32768 (default: 256, 256, 256, 256, 768,
437 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
438 * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL
439 * while full&low speed device connect. And change speed
440 * back to DWC2_SPEED_PARAM_HIGH while device is gone.
441 * 0 - No (default)
442 * 1 - Yes
443 * @service_interval: Enable service interval based scheduling.
444 * 0 - No
445 * 1 - Yes
446 *
447 * The following parameters may be specified when starting the module. These
448 * parameters define how the DWC_otg controller should be configured. A
449 * value of -1 (or any other out of range value) for any parameter means
450 * to read the value from hardware (if possible) or use the builtin
451 * default described above.
452 */
453struct dwc2_core_params {
454 u8 otg_cap;
455#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
456#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
457#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
458
459 u8 phy_type;
460#define DWC2_PHY_TYPE_PARAM_FS 0
461#define DWC2_PHY_TYPE_PARAM_UTMI 1
462#define DWC2_PHY_TYPE_PARAM_ULPI 2
463
464 u8 speed;
465#define DWC2_SPEED_PARAM_HIGH 0
466#define DWC2_SPEED_PARAM_FULL 1
467#define DWC2_SPEED_PARAM_LOW 2
468
469 u8 phy_utmi_width;
470 bool phy_ulpi_ddr;
471 bool phy_ulpi_ext_vbus;
472 bool enable_dynamic_fifo;
473 bool en_multiple_tx_fifo;
474 bool i2c_enable;
475 bool acg_enable;
476 bool ulpi_fs_ls;
477 bool ts_dline;
478 bool reload_ctl;
479 bool uframe_sched;
480 bool external_id_pin_ctl;
481
482 int power_down;
483#define DWC2_POWER_DOWN_PARAM_NONE 0
484#define DWC2_POWER_DOWN_PARAM_PARTIAL 1
485#define DWC2_POWER_DOWN_PARAM_HIBERNATION 2
486 bool no_clock_gating;
487
488 bool lpm;
489 bool lpm_clock_gating;
490 bool besl;
491 bool hird_threshold_en;
492 bool service_interval;
493 u8 hird_threshold;
494 bool activate_stm_fs_transceiver;
495 bool activate_stm_id_vb_detection;
496 bool ipg_isoc_en;
497 u16 max_packet_count;
498 u32 max_transfer_size;
499 u32 ahbcfg;
500
501 /* GREFCLK parameters */
502 u32 ref_clk_per;
503 u16 sof_cnt_wkup_alert;
504
505 /* Host parameters */
506 bool host_dma;
507 bool dma_desc_enable;
508 bool dma_desc_fs_enable;
509 bool host_support_fs_ls_low_power;
510 bool host_ls_low_power_phy_clk;
511 bool oc_disable;
512
513 u8 host_channels;
514 u16 host_rx_fifo_size;
515 u16 host_nperio_tx_fifo_size;
516 u16 host_perio_tx_fifo_size;
517
518 /* Gadget parameters */
519 bool g_dma;
520 bool g_dma_desc;
521 u32 g_rx_fifo_size;
522 u32 g_np_tx_fifo_size;
523 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
524
525 bool change_speed_quirk;
526};
527
528/**
529 * struct dwc2_hw_params - Autodetected parameters.
530 *
531 * These parameters are the various parameters read from hardware
532 * registers during initialization. They typically contain the best
533 * supported or maximum value that can be configured in the
534 * corresponding dwc2_core_params value.
535 *
536 * The values that are not in dwc2_core_params are documented below.
537 *
538 * @op_mode: Mode of Operation
539 * 0 - HNP- and SRP-Capable OTG (Host & Device)
540 * 1 - SRP-Capable OTG (Host & Device)
541 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
542 * 3 - SRP-Capable Device
543 * 4 - Non-OTG Device
544 * 5 - SRP-Capable Host
545 * 6 - Non-OTG Host
546 * @arch: Architecture
547 * 0 - Slave only
548 * 1 - External DMA
549 * 2 - Internal DMA
550 * @ipg_isoc_en: This feature indicates that the controller supports
551 * the worst-case scenario of Rx followed by Rx
552 * Interpacket Gap (IPG) (32 bitTimes) as per the utmi
553 * specification for any token following ISOC OUT token.
554 * 0 - Don't support
555 * 1 - Support
556 * @power_optimized: Are power optimizations enabled?
557 * @num_dev_ep: Number of device endpoints available
558 * @num_dev_in_eps: Number of device IN endpoints available
559 * @num_dev_perio_in_ep: Number of device periodic IN endpoints
560 * available
561 * @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue
562 * Depth
563 * 0 to 30
564 * @host_perio_tx_q_depth:
565 * Host Mode Periodic Request Queue Depth
566 * 2, 4 or 8
567 * @nperio_tx_q_depth:
568 * Non-Periodic Request Queue Depth
569 * 2, 4 or 8
570 * @hs_phy_type: High-speed PHY interface type
571 * 0 - High-speed interface not supported
572 * 1 - UTMI+
573 * 2 - ULPI
574 * 3 - UTMI+ and ULPI
575 * @fs_phy_type: Full-speed PHY interface type
576 * 0 - Full speed interface not supported
577 * 1 - Dedicated full speed interface
578 * 2 - FS pins shared with UTMI+ pins
579 * 3 - FS pins shared with ULPI pins
580 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
581 * @hibernation: Is hibernation enabled?
582 * @utmi_phy_data_width: UTMI+ PHY data width
583 * 0 - 8 bits
584 * 1 - 16 bits
585 * 2 - 8 or 16 bits
586 * @snpsid: Value from SNPSID register
587 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
588 * @g_tx_fifo_size: Power-on values of TxFIFO sizes
589 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
590 * address DMA mode or descriptor DMA mode for accessing
591 * the data FIFOs. The driver will automatically detect the
592 * value for this if none is specified.
593 * 0 - Address DMA
594 * 1 - Descriptor DMA (default, if available)
595 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
596 * 1 - Allow dynamic FIFO sizing (default, if available)
597 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
598 * are enabled for non-periodic IN endpoints in device
599 * mode.
600 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
601 * in host mode when dynamic FIFO sizing is enabled
602 * 16 to 32768
603 * Actual maximum value is autodetected and also
604 * the default.
605 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
606 * host mode when dynamic FIFO sizing is enabled
607 * 16 to 32768
608 * Actual maximum value is autodetected and also
609 * the default.
610 * @max_transfer_size: The maximum transfer size supported, in bytes
611 * 2047 to 65,535
612 * Actual maximum value is autodetected and also
613 * the default.
614 * @max_packet_count: The maximum number of packets in a transfer
615 * 15 to 511
616 * Actual maximum value is autodetected and also
617 * the default.
618 * @host_channels: The number of host channel registers to use
619 * 1 to 16
620 * Actual maximum value is autodetected and also
621 * the default.
622 * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
623 * in device mode when dynamic FIFO sizing is enabled
624 * 16 to 32768
625 * Actual maximum value is autodetected and also
626 * the default.
627 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
628 * speed PHY. This parameter is only applicable if phy_type
629 * is FS.
630 * 0 - No (default)
631 * 1 - Yes
632 * @acg_enable: For enabling Active Clock Gating in the controller
633 * 0 - Disable
634 * 1 - Enable
635 * @lpm_mode: For enabling Link Power Management in the controller
636 * 0 - Disable
637 * 1 - Enable
638 * @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic
639 * FIFO sizing is enabled 16 to 32768
640 * Actual maximum value is autodetected and also
641 * the default.
642 * @service_interval_mode: For enabling service interval based scheduling in the
643 * controller.
644 * 0 - Disable
645 * 1 - Enable
646 */
647struct dwc2_hw_params {
648 unsigned op_mode:3;
649 unsigned arch:2;
650 unsigned dma_desc_enable:1;
651 unsigned enable_dynamic_fifo:1;
652 unsigned en_multiple_tx_fifo:1;
653 unsigned rx_fifo_size:16;
654 unsigned host_nperio_tx_fifo_size:16;
655 unsigned dev_nperio_tx_fifo_size:16;
656 unsigned host_perio_tx_fifo_size:16;
657 unsigned nperio_tx_q_depth:3;
658 unsigned host_perio_tx_q_depth:3;
659 unsigned dev_token_q_depth:5;
660 unsigned max_transfer_size:26;
661 unsigned max_packet_count:11;
662 unsigned host_channels:5;
663 unsigned hs_phy_type:2;
664 unsigned fs_phy_type:2;
665 unsigned i2c_enable:1;
666 unsigned acg_enable:1;
667 unsigned num_dev_ep:4;
668 unsigned num_dev_in_eps : 4;
669 unsigned num_dev_perio_in_ep:4;
670 unsigned total_fifo_size:16;
671 unsigned power_optimized:1;
672 unsigned hibernation:1;
673 unsigned utmi_phy_data_width:2;
674 unsigned lpm_mode:1;
675 unsigned ipg_isoc_en:1;
676 unsigned service_interval_mode:1;
677 u32 snpsid;
678 u32 dev_ep_dirs;
679 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
680};
681
682/* Size of control and EP0 buffers */
683#define DWC2_CTRL_BUFF_SIZE 8
684
685/**
686 * struct dwc2_gregs_backup - Holds global registers state before
687 * entering partial power down
688 * @gotgctl: Backup of GOTGCTL register
689 * @gintmsk: Backup of GINTMSK register
690 * @gahbcfg: Backup of GAHBCFG register
691 * @gusbcfg: Backup of GUSBCFG register
692 * @grxfsiz: Backup of GRXFSIZ register
693 * @gnptxfsiz: Backup of GNPTXFSIZ register
694 * @gi2cctl: Backup of GI2CCTL register
695 * @glpmcfg: Backup of GLPMCFG register
696 * @gdfifocfg: Backup of GDFIFOCFG register
697 * @pcgcctl: Backup of PCGCCTL register
698 * @pcgcctl1: Backup of PCGCCTL1 register
699 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
700 * @gpwrdn: Backup of GPWRDN register
701 * @valid: True if registers values backuped.
702 */
703struct dwc2_gregs_backup {
704 u32 gotgctl;
705 u32 gintmsk;
706 u32 gahbcfg;
707 u32 gusbcfg;
708 u32 grxfsiz;
709 u32 gnptxfsiz;
710 u32 gi2cctl;
711 u32 glpmcfg;
712 u32 pcgcctl;
713 u32 pcgcctl1;
714 u32 gdfifocfg;
715 u32 gpwrdn;
716 bool valid;
717};
718
719/**
720 * struct dwc2_dregs_backup - Holds device registers state before
721 * entering partial power down
722 * @dcfg: Backup of DCFG register
723 * @dctl: Backup of DCTL register
724 * @daintmsk: Backup of DAINTMSK register
725 * @diepmsk: Backup of DIEPMSK register
726 * @doepmsk: Backup of DOEPMSK register
727 * @diepctl: Backup of DIEPCTL register
728 * @dieptsiz: Backup of DIEPTSIZ register
729 * @diepdma: Backup of DIEPDMA register
730 * @doepctl: Backup of DOEPCTL register
731 * @doeptsiz: Backup of DOEPTSIZ register
732 * @doepdma: Backup of DOEPDMA register
733 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
734 * @valid: True if registers values backuped.
735 */
736struct dwc2_dregs_backup {
737 u32 dcfg;
738 u32 dctl;
739 u32 daintmsk;
740 u32 diepmsk;
741 u32 doepmsk;
742 u32 diepctl[MAX_EPS_CHANNELS];
743 u32 dieptsiz[MAX_EPS_CHANNELS];
744 u32 diepdma[MAX_EPS_CHANNELS];
745 u32 doepctl[MAX_EPS_CHANNELS];
746 u32 doeptsiz[MAX_EPS_CHANNELS];
747 u32 doepdma[MAX_EPS_CHANNELS];
748 u32 dtxfsiz[MAX_EPS_CHANNELS];
749 bool valid;
750};
751
752/**
753 * struct dwc2_hregs_backup - Holds host registers state before
754 * entering partial power down
755 * @hcfg: Backup of HCFG register
756 * @haintmsk: Backup of HAINTMSK register
757 * @hcintmsk: Backup of HCINTMSK register
758 * @hprt0: Backup of HPTR0 register
759 * @hfir: Backup of HFIR register
760 * @hptxfsiz: Backup of HPTXFSIZ register
761 * @valid: True if registers values backuped.
762 */
763struct dwc2_hregs_backup {
764 u32 hcfg;
765 u32 haintmsk;
766 u32 hcintmsk[MAX_EPS_CHANNELS];
767 u32 hprt0;
768 u32 hfir;
769 u32 hptxfsiz;
770 bool valid;
771};
772
773/*
774 * Constants related to high speed periodic scheduling
775 *
776 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a
777 * reservation point of view it's assumed that the schedule goes right back to
778 * the beginning after the end of the schedule.
779 *
780 * What does that mean for scheduling things with a long interval? It means
781 * we'll reserve time for them in every possible microframe that they could
782 * ever be scheduled in. ...but we'll still only actually schedule them as
783 * often as they were requested.
784 *
785 * We keep our schedule in a "bitmap" structure. This simplifies having
786 * to keep track of and merge intervals: we just let the bitmap code do most
787 * of the heavy lifting. In a way scheduling is much like memory allocation.
788 *
789 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're
790 * supposed to schedule for periodic transfers). That's according to spec.
791 *
792 * Note that though we only schedule 80% of each microframe, the bitmap that we
793 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of
794 * space for each uFrame).
795 *
796 * Requirements:
797 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
798 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
799 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might
800 * be bugs). The 8 comes from the USB spec: number of microframes per frame.
801 */
802#define DWC2_US_PER_UFRAME 125
803#define DWC2_HS_PERIODIC_US_PER_UFRAME 100
804
805#define DWC2_HS_SCHEDULE_UFRAMES 8
806#define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \
807 DWC2_HS_PERIODIC_US_PER_UFRAME)
808
809/*
810 * Constants related to low speed scheduling
811 *
812 * For high speed we schedule every 1us. For low speed that's a bit overkill,
813 * so we make up a unit called a "slice" that's worth 25us. There are 40
814 * slices in a full frame and we can schedule 36 of those (90%) for periodic
815 * transfers.
816 *
817 * Our low speed schedule can be as short as 1 frame or could be longer. When
818 * we only schedule 1 frame it means that we'll need to reserve a time every
819 * frame even for things that only transfer very rarely, so something that runs
820 * every 2048 frames will get time reserved in every frame. Our low speed
821 * schedule can be longer and we'll be able to handle more overlap, but that
822 * will come at increased memory cost and increased time to schedule.
823 *
824 * Note: one other advantage of a short low speed schedule is that if we mess
825 * up and miss scheduling we can jump in and use any of the slots that we
826 * happened to reserve.
827 *
828 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for
829 * the schedule. There will be one schedule per TT.
830 *
831 * Requirements:
832 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
833 */
834#define DWC2_US_PER_SLICE 25
835#define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE)
836
837#define DWC2_ROUND_US_TO_SLICE(us) \
838 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \
839 DWC2_US_PER_SLICE)
840
841#define DWC2_LS_PERIODIC_US_PER_FRAME \
842 900
843#define DWC2_LS_PERIODIC_SLICES_PER_FRAME \
844 (DWC2_LS_PERIODIC_US_PER_FRAME / \
845 DWC2_US_PER_SLICE)
846
847#define DWC2_LS_SCHEDULE_FRAMES 1
848#define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \
849 DWC2_LS_PERIODIC_SLICES_PER_FRAME)
850
851/**
852 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
853 * and periodic schedules
854 *
855 * These are common for both host and peripheral modes:
856 *
857 * @dev: The struct device pointer
858 * @regs: Pointer to controller regs
859 * @hw_params: Parameters that were autodetected from the
860 * hardware registers
861 * @params: Parameters that define how the core should be configured
862 * @op_state: The operational State, during transitions (a_host=>
863 * a_peripheral and b_device=>b_host) this may not match
864 * the core, but allows the software to determine
865 * transitions
866 * @dr_mode: Requested mode of operation, one of following:
867 * - USB_DR_MODE_PERIPHERAL
868 * - USB_DR_MODE_HOST
869 * - USB_DR_MODE_OTG
870 * @role_sw: usb_role_switch handle
871 * @hcd_enabled: Host mode sub-driver initialization indicator.
872 * @gadget_enabled: Peripheral mode sub-driver initialization indicator.
873 * @ll_hw_enabled: Status of low-level hardware resources.
874 * @hibernated: True if core is hibernated
875 * @in_ppd: True if core is partial power down mode.
876 * @bus_suspended: True if bus is suspended
877 * @reset_phy_on_wake: Quirk saying that we should assert PHY reset on a
878 * remote wakeup.
879 * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend.
880 * @need_phy_for_wake: Quirk saying that we should keep the PHY on at
881 * suspend if we need USB to wake us up.
882 * @frame_number: Frame number read from the core. For both device
883 * and host modes. The value ranges are from 0
884 * to HFNUM_MAX_FRNUM.
885 * @phy: The otg phy transceiver structure for phy control.
886 * @uphy: The otg phy transceiver structure for old USB phy
887 * control.
888 * @plat: The platform specific configuration data. This can be
889 * removed once all SoCs support usb transceiver.
890 * @supplies: Definition of USB power supplies
891 * @vbus_supply: Regulator supplying vbus.
892 * @usb33d: Optional 3.3v regulator used on some stm32 devices to
893 * supply ID and VBUS detection hardware.
894 * @lock: Spinlock that protects all the driver data structures
895 * @priv: Stores a pointer to the struct usb_hcd
896 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
897 * transfer are in process of being queued
898 * @srp_success: Stores status of SRP request in the case of a FS PHY
899 * with an I2C interface
900 * @wq_otg: Workqueue object used for handling of some interrupts
901 * @wf_otg: Work object for handling Connector ID Status Change
902 * interrupt
903 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
904 * @lx_state: Lx state of connected device
905 * @gr_backup: Backup of global registers during suspend
906 * @dr_backup: Backup of device registers during suspend
907 * @hr_backup: Backup of host registers during suspend
908 * @needs_byte_swap: Specifies whether the opposite endianness.
909 *
910 * These are for host mode:
911 *
912 * @flags: Flags for handling root port state changes
913 * @flags.d32: Contain all root port flags
914 * @flags.b: Separate root port flags from each other
915 * @flags.b.port_connect_status_change: True if root port connect status
916 * changed
917 * @flags.b.port_connect_status: True if device connected to root port
918 * @flags.b.port_reset_change: True if root port reset status changed
919 * @flags.b.port_enable_change: True if root port enable status changed
920 * @flags.b.port_suspend_change: True if root port suspend status changed
921 * @flags.b.port_over_current_change: True if root port over current state
922 * changed.
923 * @flags.b.port_l1_change: True if root port l1 status changed
924 * @flags.b.reserved: Reserved bits of root port register
925 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
926 * Transfers associated with these QHs are not currently
927 * assigned to a host channel.
928 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
929 * Transfers associated with these QHs are currently
930 * assigned to a host channel.
931 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
932 * non-periodic schedule
933 * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule.
934 * Transfers associated with these QHs are not currently
935 * assigned to a host channel.
936 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
937 * list of QHs for periodic transfers that are _not_
938 * scheduled for the next frame. Each QH in the list has an
939 * interval counter that determines when it needs to be
940 * scheduled for execution. This scheduling mechanism
941 * allows only a simple calculation for periodic bandwidth
942 * used (i.e. must assume that all periodic transfers may
943 * need to execute in the same frame). However, it greatly
944 * simplifies scheduling and should be sufficient for the
945 * vast majority of OTG hosts, which need to connect to a
946 * small number of peripherals at one time. Items move from
947 * this list to periodic_sched_ready when the QH interval
948 * counter is 0 at SOF.
949 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
950 * the next frame, but have not yet been assigned to host
951 * channels. Items move from this list to
952 * periodic_sched_assigned as host channels become
953 * available during the current frame.
954 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
955 * frame that are assigned to host channels. Items move
956 * from this list to periodic_sched_queued as the
957 * transactions for the QH are queued to the DWC_otg
958 * controller.
959 * @periodic_sched_queued: List of periodic QHs that have been queued for
960 * execution. Items move from this list to either
961 * periodic_sched_inactive or periodic_sched_ready when the
962 * channel associated with the transfer is released. If the
963 * interval for the QH is 1, the item moves to
964 * periodic_sched_ready because it must be rescheduled for
965 * the next frame. Otherwise, the item moves to
966 * periodic_sched_inactive.
967 * @split_order: List keeping track of channels doing splits, in order.
968 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
969 * This value is in microseconds per (micro)frame. The
970 * assumption is that all periodic transfers may occur in
971 * the same (micro)frame.
972 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
973 * host is in high speed mode; low speed schedules are
974 * stored elsewhere since we need one per TT.
975 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
976 * SOF enable/disable.
977 * @free_hc_list: Free host channels in the controller. This is a list of
978 * struct dwc2_host_chan items.
979 * @periodic_channels: Number of host channels assigned to periodic transfers.
980 * Currently assuming that there is a dedicated host
981 * channel for each periodic transaction and at least one
982 * host channel is available for non-periodic transactions.
983 * @non_periodic_channels: Number of host channels assigned to non-periodic
984 * transfers
985 * @available_host_channels: Number of host channels available for the
986 * microframe scheduler to use
987 * @hc_ptr_array: Array of pointers to the host channel descriptors.
988 * Allows accessing a host channel descriptor given the
989 * host channel number. This is useful in interrupt
990 * handlers.
991 * @status_buf: Buffer used for data received during the status phase of
992 * a control transfer.
993 * @status_buf_dma: DMA address for status_buf
994 * @start_work: Delayed work for handling host A-cable connection
995 * @reset_work: Delayed work for handling a port reset
996 * @phy_reset_work: Work structure for doing a PHY reset
997 * @otg_port: OTG port number
998 * @frame_list: Frame list
999 * @frame_list_dma: Frame list DMA address
1000 * @frame_list_sz: Frame list size
1001 * @desc_gen_cache: Kmem cache for generic descriptors
1002 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
1003 * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf
1004 *
1005 * These are for peripheral mode:
1006 *
1007 * @driver: USB gadget driver
1008 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
1009 * @num_of_eps: Number of available EPs (excluding EP0)
1010 * @debug_root: Root directrory for debugfs.
1011 * @ep0_reply: Request used for ep0 reply.
1012 * @ep0_buff: Buffer for EP0 reply data, if needed.
1013 * @ctrl_buff: Buffer for EP0 control requests.
1014 * @ctrl_req: Request for EP0 control packets.
1015 * @ep0_state: EP0 control transfers state
1016 * @delayed_status: true when gadget driver asks for delayed status
1017 * @test_mode: USB test mode requested by the host
1018 * @remote_wakeup_allowed: True if device is allowed to wake-up host by
1019 * remote-wakeup signalling
1020 * @setup_desc_dma: EP0 setup stage desc chain DMA address
1021 * @setup_desc: EP0 setup stage desc chain pointer
1022 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address
1023 * @ctrl_in_desc: EP0 IN data phase desc chain pointer
1024 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address
1025 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer
1026 * @irq: Interrupt request line number
1027 * @clk: Pointer to otg clock
1028 * @reset: Pointer to dwc2 reset controller
1029 * @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10.
1030 * @regset: A pointer to a struct debugfs_regset32, which contains
1031 * a pointer to an array of register definitions, the
1032 * array size and the base address where the register bank
1033 * is to be found.
1034 * @last_frame_num: Number of last frame. Range from 0 to 32768
1035 * @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
1036 * defined, for missed SOFs tracking. Array holds that
1037 * frame numbers, which not equal to last_frame_num +1
1038 * @last_frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
1039 * defined, for missed SOFs tracking.
1040 * If current_frame_number != last_frame_num+1
1041 * then last_frame_num added to this array
1042 * @frame_num_idx: Actual size of frame_num_array and last_frame_num_array
1043 * @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed
1044 * 0 - if missed SOFs frame numbers not dumbed
1045 * @fifo_mem: Total internal RAM for FIFOs (bytes)
1046 * @fifo_map: Each bit intend for concrete fifo. If that bit is set,
1047 * then that fifo is used
1048 * @gadget: Represents a usb gadget device
1049 * @connected: Used in slave mode. True if device connected with host
1050 * @eps_in: The IN endpoints being supplied to the gadget framework
1051 * @eps_out: The OUT endpoints being supplied to the gadget framework
1052 * @new_connection: Used in host mode. True if there are new connected
1053 * device
1054 * @enabled: Indicates the enabling state of controller
1055 *
1056 */
1057struct dwc2_hsotg {
1058 struct device *dev;
1059 void __iomem *regs;
1060 /** Params detected from hardware */
1061 struct dwc2_hw_params hw_params;
1062 /** Params to actually use */
1063 struct dwc2_core_params params;
1064 enum usb_otg_state op_state;
1065 enum usb_dr_mode dr_mode;
1066 struct usb_role_switch *role_sw;
1067 unsigned int hcd_enabled:1;
1068 unsigned int gadget_enabled:1;
1069 unsigned int ll_hw_enabled:1;
1070 unsigned int hibernated:1;
1071 unsigned int in_ppd:1;
1072 bool bus_suspended;
1073 unsigned int reset_phy_on_wake:1;
1074 unsigned int need_phy_for_wake:1;
1075 unsigned int phy_off_for_suspend:1;
1076 u16 frame_number;
1077
1078 struct phy *phy;
1079 struct usb_phy *uphy;
1080 struct dwc2_hsotg_plat *plat;
1081 struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES];
1082 struct regulator *vbus_supply;
1083 struct regulator *usb33d;
1084
1085 spinlock_t lock;
1086 void *priv;
1087 int irq;
1088 struct clk *clk;
1089 struct reset_control *reset;
1090 struct reset_control *reset_ecc;
1091
1092 unsigned int queuing_high_bandwidth:1;
1093 unsigned int srp_success:1;
1094
1095 struct workqueue_struct *wq_otg;
1096 struct work_struct wf_otg;
1097 struct timer_list wkp_timer;
1098 enum dwc2_lx_state lx_state;
1099 struct dwc2_gregs_backup gr_backup;
1100 struct dwc2_dregs_backup dr_backup;
1101 struct dwc2_hregs_backup hr_backup;
1102
1103 struct dentry *debug_root;
1104 struct debugfs_regset32 *regset;
1105 bool needs_byte_swap;
1106
1107 /* DWC OTG HW Release versions */
1108#define DWC2_CORE_REV_2_71a 0x4f54271a
1109#define DWC2_CORE_REV_2_72a 0x4f54272a
1110#define DWC2_CORE_REV_2_80a 0x4f54280a
1111#define DWC2_CORE_REV_2_90a 0x4f54290a
1112#define DWC2_CORE_REV_2_91a 0x4f54291a
1113#define DWC2_CORE_REV_2_92a 0x4f54292a
1114#define DWC2_CORE_REV_2_94a 0x4f54294a
1115#define DWC2_CORE_REV_3_00a 0x4f54300a
1116#define DWC2_CORE_REV_3_10a 0x4f54310a
1117#define DWC2_CORE_REV_4_00a 0x4f54400a
1118#define DWC2_CORE_REV_4_20a 0x4f54420a
1119#define DWC2_FS_IOT_REV_1_00a 0x5531100a
1120#define DWC2_HS_IOT_REV_1_00a 0x5532100a
1121#define DWC2_CORE_REV_MASK 0x0000ffff
1122
1123 /* DWC OTG HW Core ID */
1124#define DWC2_OTG_ID 0x4f540000
1125#define DWC2_FS_IOT_ID 0x55310000
1126#define DWC2_HS_IOT_ID 0x55320000
1127
1128#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1129 union dwc2_hcd_internal_flags {
1130 u32 d32;
1131 struct {
1132 unsigned port_connect_status_change:1;
1133 unsigned port_connect_status:1;
1134 unsigned port_reset_change:1;
1135 unsigned port_enable_change:1;
1136 unsigned port_suspend_change:1;
1137 unsigned port_over_current_change:1;
1138 unsigned port_l1_change:1;
1139 unsigned reserved:25;
1140 } b;
1141 } flags;
1142
1143 struct list_head non_periodic_sched_inactive;
1144 struct list_head non_periodic_sched_waiting;
1145 struct list_head non_periodic_sched_active;
1146 struct list_head *non_periodic_qh_ptr;
1147 struct list_head periodic_sched_inactive;
1148 struct list_head periodic_sched_ready;
1149 struct list_head periodic_sched_assigned;
1150 struct list_head periodic_sched_queued;
1151 struct list_head split_order;
1152 u16 periodic_usecs;
1153 unsigned long hs_periodic_bitmap[
1154 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)];
1155 u16 periodic_qh_count;
1156 bool new_connection;
1157
1158 u16 last_frame_num;
1159
1160#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
1161#define FRAME_NUM_ARRAY_SIZE 1000
1162 u16 *frame_num_array;
1163 u16 *last_frame_num_array;
1164 int frame_num_idx;
1165 int dumped_frame_num_array;
1166#endif
1167
1168 struct list_head free_hc_list;
1169 int periodic_channels;
1170 int non_periodic_channels;
1171 int available_host_channels;
1172 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
1173 u8 *status_buf;
1174 dma_addr_t status_buf_dma;
1175#define DWC2_HCD_STATUS_BUF_SIZE 64
1176
1177 struct delayed_work start_work;
1178 struct delayed_work reset_work;
1179 struct work_struct phy_reset_work;
1180 u8 otg_port;
1181 u32 *frame_list;
1182 dma_addr_t frame_list_dma;
1183 u32 frame_list_sz;
1184 struct kmem_cache *desc_gen_cache;
1185 struct kmem_cache *desc_hsisoc_cache;
1186 struct kmem_cache *unaligned_cache;
1187#define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024
1188
1189#endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
1190
1191#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1192 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1193 /* Gadget structures */
1194 struct usb_gadget_driver *driver;
1195 int fifo_mem;
1196 unsigned int dedicated_fifos:1;
1197 unsigned char num_of_eps;
1198 u32 fifo_map;
1199
1200 struct usb_request *ep0_reply;
1201 struct usb_request *ctrl_req;
1202 void *ep0_buff;
1203 void *ctrl_buff;
1204 enum dwc2_ep0_state ep0_state;
1205 unsigned delayed_status : 1;
1206 u8 test_mode;
1207
1208 dma_addr_t setup_desc_dma[2];
1209 struct dwc2_dma_desc *setup_desc[2];
1210 dma_addr_t ctrl_in_desc_dma;
1211 struct dwc2_dma_desc *ctrl_in_desc;
1212 dma_addr_t ctrl_out_desc_dma;
1213 struct dwc2_dma_desc *ctrl_out_desc;
1214
1215 struct usb_gadget gadget;
1216 unsigned int enabled:1;
1217 unsigned int connected:1;
1218 unsigned int remote_wakeup_allowed:1;
1219 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
1220 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
1221#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
1222};
1223
1224/* Normal architectures just use readl/write */
1225static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset)
1226{
1227 u32 val;
1228
1229 val = readl(hsotg->regs + offset);
1230 if (hsotg->needs_byte_swap)
1231 return swab32(val);
1232 else
1233 return val;
1234}
1235
1236static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset)
1237{
1238 if (hsotg->needs_byte_swap)
1239 writel(swab32(value), hsotg->regs + offset);
1240 else
1241 writel(value, hsotg->regs + offset);
1242
1243#ifdef DWC2_LOG_WRITES
1244 pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset);
1245#endif
1246}
1247
1248static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset,
1249 void *buffer, unsigned int count)
1250{
1251 if (count) {
1252 u32 *buf = buffer;
1253
1254 do {
1255 u32 x = dwc2_readl(hsotg, offset);
1256 *buf++ = x;
1257 } while (--count);
1258 }
1259}
1260
1261static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset,
1262 const void *buffer, unsigned int count)
1263{
1264 if (count) {
1265 const u32 *buf = buffer;
1266
1267 do {
1268 dwc2_writel(hsotg, *buf++, offset);
1269 } while (--count);
1270 }
1271}
1272
1273/* Reasons for halting a host channel */
1274enum dwc2_halt_status {
1275 DWC2_HC_XFER_NO_HALT_STATUS,
1276 DWC2_HC_XFER_COMPLETE,
1277 DWC2_HC_XFER_URB_COMPLETE,
1278 DWC2_HC_XFER_ACK,
1279 DWC2_HC_XFER_NAK,
1280 DWC2_HC_XFER_NYET,
1281 DWC2_HC_XFER_STALL,
1282 DWC2_HC_XFER_XACT_ERR,
1283 DWC2_HC_XFER_FRAME_OVERRUN,
1284 DWC2_HC_XFER_BABBLE_ERR,
1285 DWC2_HC_XFER_DATA_TOGGLE_ERR,
1286 DWC2_HC_XFER_AHB_ERR,
1287 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
1288 DWC2_HC_XFER_URB_DEQUEUE,
1289};
1290
1291/* Core version information */
1292static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg)
1293{
1294 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000;
1295}
1296
1297static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg)
1298{
1299 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000;
1300}
1301
1302static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg)
1303{
1304 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000;
1305}
1306
1307/*
1308 * The following functions support initialization of the core driver component
1309 * and the DWC_otg controller
1310 */
1311int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait);
1312int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg);
1313int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup,
1314 bool restore);
1315int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host);
1316int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
1317 int reset, int is_host);
1318void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg);
1319int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy);
1320
1321void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host);
1322void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
1323
1324bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
1325
1326int dwc2_check_core_version(struct dwc2_hsotg *hsotg);
1327
1328/*
1329 * Common core Functions.
1330 * The following functions support managing the DWC_otg controller in either
1331 * device or host mode.
1332 */
1333void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
1334void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
1335void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
1336
1337void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
1338void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
1339
1340void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
1341 int is_host);
1342int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg);
1343int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg);
1344
1345void dwc2_enable_acg(struct dwc2_hsotg *hsotg);
1346
1347/* This function should be called on every hardware interrupt. */
1348irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
1349
1350/* The device ID match table */
1351extern const struct of_device_id dwc2_of_match_table[];
1352extern const struct acpi_device_id dwc2_acpi_match[];
1353
1354int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1355int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
1356
1357/* Common polling functions */
1358int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
1359 u32 timeout);
1360int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
1361 u32 timeout);
1362/* Parameters */
1363int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
1364int dwc2_init_params(struct dwc2_hsotg *hsotg);
1365
1366/*
1367 * The following functions check the controller's OTG operation mode
1368 * capability (GHWCFG2.OTG_MODE).
1369 *
1370 * These functions can be used before the internal hsotg->hw_params
1371 * are read in and cached so they always read directly from the
1372 * GHWCFG2 register.
1373 */
1374unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg);
1375bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1376bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1377bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1378
1379/*
1380 * Returns the mode of operation, host or device
1381 */
1382static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1383{
1384 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1385}
1386
1387static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1388{
1389 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1390}
1391
1392int dwc2_drd_init(struct dwc2_hsotg *hsotg);
1393void dwc2_drd_suspend(struct dwc2_hsotg *hsotg);
1394void dwc2_drd_resume(struct dwc2_hsotg *hsotg);
1395void dwc2_drd_exit(struct dwc2_hsotg *hsotg);
1396
1397/*
1398 * Dump core registers and SPRAM
1399 */
1400void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1401void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1402void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
1403
1404/* Gadget defines */
1405#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1406 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1407int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1408int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1409int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
1410int dwc2_gadget_init(struct dwc2_hsotg *hsotg);
1411void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1412 bool reset);
1413void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg);
1414void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1415void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1416int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
1417#define dwc2_is_device_connected(hsotg) (hsotg->connected)
1418int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
1419int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup);
1420int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg);
1421int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
1422 int rem_wakeup, int reset);
1423int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg);
1424int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1425 bool restore);
1426void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg);
1427void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg,
1428 int rem_wakeup);
1429int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg);
1430int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg);
1431int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg);
1432void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg);
1433void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg);
1434static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg)
1435{ hsotg->fifo_map = 0; }
1436#else
1437static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
1438{ return 0; }
1439static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
1440{ return 0; }
1441static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
1442{ return 0; }
1443static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
1444{ return 0; }
1445static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1446 bool reset) {}
1447static inline void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) {}
1448static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
1449static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
1450static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
1451 int testmode)
1452{ return 0; }
1453#define dwc2_is_device_connected(hsotg) (0)
1454static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
1455{ return 0; }
1456static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg,
1457 int remote_wakeup)
1458{ return 0; }
1459static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
1460{ return 0; }
1461static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
1462 int rem_wakeup, int reset)
1463{ return 0; }
1464static inline int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg)
1465{ return 0; }
1466static inline int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1467 bool restore)
1468{ return 0; }
1469static inline void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg) {}
1470static inline void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg,
1471 int rem_wakeup) {}
1472static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
1473{ return 0; }
1474static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
1475{ return 0; }
1476static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
1477{ return 0; }
1478static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {}
1479static inline void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) {}
1480static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg) {}
1481#endif
1482
1483#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1484int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1485int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
1486void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1487void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
1488void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
1489int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup);
1490int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex);
1491int dwc2_port_resume(struct dwc2_hsotg *hsotg);
1492int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
1493int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
1494int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg);
1495int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
1496 int rem_wakeup, int reset);
1497int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg);
1498int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1499 int rem_wakeup, bool restore);
1500void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg);
1501void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup);
1502bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2);
1503static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg)
1504{ schedule_work(&hsotg->phy_reset_work); }
1505#else
1506static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1507{ return 0; }
1508static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg,
1509 int us)
1510{ return 0; }
1511static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
1512static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
1513static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
1514static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
1515static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
1516{ return 0; }
1517static inline int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
1518{ return 0; }
1519static inline int dwc2_port_resume(struct dwc2_hsotg *hsotg)
1520{ return 0; }
1521static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
1522{ return 0; }
1523static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
1524{ return 0; }
1525static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
1526{ return 0; }
1527static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
1528{ return 0; }
1529static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
1530 int rem_wakeup, int reset)
1531{ return 0; }
1532static inline int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg)
1533{ return 0; }
1534static inline int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg,
1535 int rem_wakeup, bool restore)
1536{ return 0; }
1537static inline void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg) {}
1538static inline void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg,
1539 int rem_wakeup) {}
1540static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2)
1541{ return false; }
1542static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {}
1543
1544#endif
1545
1546#endif /* __DWC2_CORE_H__ */