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1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * core.h - DesignWare HS OTG Controller common declarations
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#ifndef __DWC2_CORE_H__
39#define __DWC2_CORE_H__
40
41#include <linux/phy/phy.h>
42#include <linux/regulator/consumer.h>
43#include <linux/usb/gadget.h>
44#include <linux/usb/otg.h>
45#include <linux/usb/phy.h>
46#include "hw.h"
47
48/*
49 * Suggested defines for tracers:
50 * - no_printk: Disable tracing
51 * - pr_info: Print this info to the console
52 * - trace_printk: Print this info to trace buffer (good for verbose logging)
53 */
54
55#define DWC2_TRACE_SCHEDULER no_printk
56#define DWC2_TRACE_SCHEDULER_VB no_printk
57
58/* Detailed scheduler tracing, but won't overwhelm console */
59#define dwc2_sch_dbg(hsotg, fmt, ...) \
60 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \
61 dev_name(hsotg->dev), ##__VA_ARGS__)
62
63/* Verbose scheduler tracing */
64#define dwc2_sch_vdbg(hsotg, fmt, ...) \
65 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \
66 dev_name(hsotg->dev), ##__VA_ARGS__)
67
68#ifdef CONFIG_MIPS
69/*
70 * There are some MIPS machines that can run in either big-endian
71 * or little-endian mode and that use the dwc2 register without
72 * a byteswap in both ways.
73 * Unlike other architectures, MIPS apparently does not require a
74 * barrier before the __raw_writel() to synchronize with DMA but does
75 * require the barrier after the __raw_writel() to serialize a set of
76 * writes. This set of operations was added specifically for MIPS and
77 * should only be used there.
78 */
79static inline u32 dwc2_readl(const void __iomem *addr)
80{
81 u32 value = __raw_readl(addr);
82
83 /* In order to preserve endianness __raw_* operation is used. Therefore
84 * a barrier is needed to ensure IO access is not re-ordered across
85 * reads or writes
86 */
87 mb();
88 return value;
89}
90
91static inline void dwc2_writel(u32 value, void __iomem *addr)
92{
93 __raw_writel(value, addr);
94
95 /*
96 * In order to preserve endianness __raw_* operation is used. Therefore
97 * a barrier is needed to ensure IO access is not re-ordered across
98 * reads or writes
99 */
100 mb();
101#ifdef DWC2_LOG_WRITES
102 pr_info("INFO:: wrote %08x to %p\n", value, addr);
103#endif
104}
105#else
106/* Normal architectures just use readl/write */
107static inline u32 dwc2_readl(const void __iomem *addr)
108{
109 return readl(addr);
110}
111
112static inline void dwc2_writel(u32 value, void __iomem *addr)
113{
114 writel(value, addr);
115
116#ifdef DWC2_LOG_WRITES
117 pr_info("info:: wrote %08x to %p\n", value, addr);
118#endif
119}
120#endif
121
122/* Maximum number of Endpoints/HostChannels */
123#define MAX_EPS_CHANNELS 16
124
125/* dwc2-hsotg declarations */
126static const char * const dwc2_hsotg_supply_names[] = {
127 "vusb_d", /* digital USB supply, 1.2V */
128 "vusb_a", /* analog USB supply, 1.1V */
129};
130
131#define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names)
132
133/*
134 * EP0_MPS_LIMIT
135 *
136 * Unfortunately there seems to be a limit of the amount of data that can
137 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
138 * packets (which practically means 1 packet and 63 bytes of data) when the
139 * MPS is set to 64.
140 *
141 * This means if we are wanting to move >127 bytes of data, we need to
142 * split the transactions up, but just doing one packet at a time does
143 * not work (this may be an implicit DATA0 PID on first packet of the
144 * transaction) and doing 2 packets is outside the controller's limits.
145 *
146 * If we try to lower the MPS size for EP0, then no transfers work properly
147 * for EP0, and the system will fail basic enumeration. As no cause for this
148 * has currently been found, we cannot support any large IN transfers for
149 * EP0.
150 */
151#define EP0_MPS_LIMIT 64
152
153struct dwc2_hsotg;
154struct dwc2_hsotg_req;
155
156/**
157 * struct dwc2_hsotg_ep - driver endpoint definition.
158 * @ep: The gadget layer representation of the endpoint.
159 * @name: The driver generated name for the endpoint.
160 * @queue: Queue of requests for this endpoint.
161 * @parent: Reference back to the parent device structure.
162 * @req: The current request that the endpoint is processing. This is
163 * used to indicate an request has been loaded onto the endpoint
164 * and has yet to be completed (maybe due to data move, or simply
165 * awaiting an ack from the core all the data has been completed).
166 * @debugfs: File entry for debugfs file for this endpoint.
167 * @lock: State lock to protect contents of endpoint.
168 * @dir_in: Set to true if this endpoint is of the IN direction, which
169 * means that it is sending data to the Host.
170 * @index: The index for the endpoint registers.
171 * @mc: Multi Count - number of transactions per microframe
172 * @interval - Interval for periodic endpoints, in frames or microframes.
173 * @name: The name array passed to the USB core.
174 * @halted: Set if the endpoint has been halted.
175 * @periodic: Set if this is a periodic ep, such as Interrupt
176 * @isochronous: Set if this is a isochronous ep
177 * @send_zlp: Set if we need to send a zero-length packet.
178 * @desc_list_dma: The DMA address of descriptor chain currently in use.
179 * @desc_list: Pointer to descriptor DMA chain head currently in use.
180 * @desc_count: Count of entries within the DMA descriptor chain of EP.
181 * @isoc_chain_num: Number of ISOC chain currently in use - either 0 or 1.
182 * @next_desc: index of next free descriptor in the ISOC chain under SW control.
183 * @total_data: The total number of data bytes done.
184 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
185 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
186 * @last_load: The offset of data for the last start of request.
187 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
188 * @target_frame: Targeted frame num to setup next ISOC transfer
189 * @frame_overrun: Indicates SOF number overrun in DSTS
190 *
191 * This is the driver's state for each registered enpoint, allowing it
192 * to keep track of transactions that need doing. Each endpoint has a
193 * lock to protect the state, to try and avoid using an overall lock
194 * for the host controller as much as possible.
195 *
196 * For periodic IN endpoints, we have fifo_size and fifo_load to try
197 * and keep track of the amount of data in the periodic FIFO for each
198 * of these as we don't have a status register that tells us how much
199 * is in each of them. (note, this may actually be useless information
200 * as in shared-fifo mode periodic in acts like a single-frame packet
201 * buffer than a fifo)
202 */
203struct dwc2_hsotg_ep {
204 struct usb_ep ep;
205 struct list_head queue;
206 struct dwc2_hsotg *parent;
207 struct dwc2_hsotg_req *req;
208 struct dentry *debugfs;
209
210 unsigned long total_data;
211 unsigned int size_loaded;
212 unsigned int last_load;
213 unsigned int fifo_load;
214 unsigned short fifo_size;
215 unsigned short fifo_index;
216
217 unsigned char dir_in;
218 unsigned char index;
219 unsigned char mc;
220 u16 interval;
221
222 unsigned int halted:1;
223 unsigned int periodic:1;
224 unsigned int isochronous:1;
225 unsigned int send_zlp:1;
226 unsigned int target_frame;
227#define TARGET_FRAME_INITIAL 0xFFFFFFFF
228 bool frame_overrun;
229
230 dma_addr_t desc_list_dma;
231 struct dwc2_dma_desc *desc_list;
232 u8 desc_count;
233
234 unsigned char isoc_chain_num;
235 unsigned int next_desc;
236
237 char name[10];
238};
239
240/**
241 * struct dwc2_hsotg_req - data transfer request
242 * @req: The USB gadget request
243 * @queue: The list of requests for the endpoint this is queued for.
244 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
245 */
246struct dwc2_hsotg_req {
247 struct usb_request req;
248 struct list_head queue;
249 void *saved_req_buf;
250};
251
252#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
253 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
254#define call_gadget(_hs, _entry) \
255do { \
256 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
257 (_hs)->driver && (_hs)->driver->_entry) { \
258 spin_unlock(&_hs->lock); \
259 (_hs)->driver->_entry(&(_hs)->gadget); \
260 spin_lock(&_hs->lock); \
261 } \
262} while (0)
263#else
264#define call_gadget(_hs, _entry) do {} while (0)
265#endif
266
267struct dwc2_hsotg;
268struct dwc2_host_chan;
269
270/* Device States */
271enum dwc2_lx_state {
272 DWC2_L0, /* On state */
273 DWC2_L1, /* LPM sleep state */
274 DWC2_L2, /* USB suspend state */
275 DWC2_L3, /* Off state */
276};
277
278/* Gadget ep0 states */
279enum dwc2_ep0_state {
280 DWC2_EP0_SETUP,
281 DWC2_EP0_DATA_IN,
282 DWC2_EP0_DATA_OUT,
283 DWC2_EP0_STATUS_IN,
284 DWC2_EP0_STATUS_OUT,
285};
286
287/**
288 * struct dwc2_core_params - Parameters for configuring the core
289 *
290 * @otg_cap: Specifies the OTG capabilities.
291 * 0 - HNP and SRP capable
292 * 1 - SRP Only capable
293 * 2 - No HNP/SRP capable (always available)
294 * Defaults to best available option (0, 1, then 2)
295 * @host_dma: Specifies whether to use slave or DMA mode for accessing
296 * the data FIFOs. The driver will automatically detect the
297 * value for this parameter if none is specified.
298 * 0 - Slave (always available)
299 * 1 - DMA (default, if available)
300 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
301 * address DMA mode or descriptor DMA mode for accessing
302 * the data FIFOs. The driver will automatically detect the
303 * value for this if none is specified.
304 * 0 - Address DMA
305 * 1 - Descriptor DMA (default, if available)
306 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
307 * address DMA mode or descriptor DMA mode for accessing
308 * the data FIFOs in Full Speed mode only. The driver
309 * will automatically detect the value for this if none is
310 * specified.
311 * 0 - Address DMA
312 * 1 - Descriptor DMA in FS (default, if available)
313 * @speed: Specifies the maximum speed of operation in host and
314 * device mode. The actual speed depends on the speed of
315 * the attached device and the value of phy_type.
316 * 0 - High Speed
317 * (default when phy_type is UTMI+ or ULPI)
318 * 1 - Full Speed
319 * (default when phy_type is Full Speed)
320 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
321 * 1 - Allow dynamic FIFO sizing (default, if available)
322 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
323 * are enabled for non-periodic IN endpoints in device
324 * mode.
325 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
326 * dynamic FIFO sizing is enabled
327 * 16 to 32768
328 * Actual maximum value is autodetected and also
329 * the default.
330 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
331 * in host mode when dynamic FIFO sizing is enabled
332 * 16 to 32768
333 * Actual maximum value is autodetected and also
334 * the default.
335 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
336 * host mode when dynamic FIFO sizing is enabled
337 * 16 to 32768
338 * Actual maximum value is autodetected and also
339 * the default.
340 * @max_transfer_size: The maximum transfer size supported, in bytes
341 * 2047 to 65,535
342 * Actual maximum value is autodetected and also
343 * the default.
344 * @max_packet_count: The maximum number of packets in a transfer
345 * 15 to 511
346 * Actual maximum value is autodetected and also
347 * the default.
348 * @host_channels: The number of host channel registers to use
349 * 1 to 16
350 * Actual maximum value is autodetected and also
351 * the default.
352 * @phy_type: Specifies the type of PHY interface to use. By default,
353 * the driver will automatically detect the phy_type.
354 * 0 - Full Speed Phy
355 * 1 - UTMI+ Phy
356 * 2 - ULPI Phy
357 * Defaults to best available option (2, 1, then 0)
358 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
359 * is applicable for a phy_type of UTMI+ or ULPI. (For a
360 * ULPI phy_type, this parameter indicates the data width
361 * between the MAC and the ULPI Wrapper.) Also, this
362 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
363 * parameter was set to "8 and 16 bits", meaning that the
364 * core has been configured to work at either data path
365 * width.
366 * 8 or 16 (default 16 if available)
367 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
368 * data rate. This parameter is only applicable if phy_type
369 * is ULPI.
370 * 0 - single data rate ULPI interface with 8 bit wide
371 * data bus (default)
372 * 1 - double data rate ULPI interface with 4 bit wide
373 * data bus
374 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
375 * external supply to drive the VBus
376 * 0 - Internal supply (default)
377 * 1 - External supply
378 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
379 * speed PHY. This parameter is only applicable if phy_type
380 * is FS.
381 * 0 - No (default)
382 * 1 - Yes
383 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
384 * 0 - No (default)
385 * 1 - Yes
386 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
387 * when attached to a Full Speed or Low Speed device in
388 * host mode.
389 * 0 - Don't support low power mode (default)
390 * 1 - Support low power mode
391 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
392 * when connected to a Low Speed device in host
393 * mode. This parameter is applicable only if
394 * host_support_fs_ls_low_power is enabled.
395 * 0 - 48 MHz
396 * (default when phy_type is UTMI+ or ULPI)
397 * 1 - 6 MHz
398 * (default when phy_type is Full Speed)
399 * @oc_disable: Flag to disable overcurrent condition.
400 * 0 - Allow overcurrent condition to get detected
401 * 1 - Disable overcurrent condtion to get detected
402 * @ts_dline: Enable Term Select Dline pulsing
403 * 0 - No (default)
404 * 1 - Yes
405 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
406 * 0 - No (default for core < 2.92a)
407 * 1 - Yes (default for core >= 2.92a)
408 * @ahbcfg: This field allows the default value of the GAHBCFG
409 * register to be overridden
410 * -1 - GAHBCFG value will be set to 0x06
411 * (INCR, default)
412 * all others - GAHBCFG value will be overridden with
413 * this value
414 * Not all bits can be controlled like this, the
415 * bits defined by GAHBCFG_CTRL_MASK are controlled
416 * by the driver and are ignored in this
417 * configuration value.
418 * @uframe_sched: True to enable the microframe scheduler
419 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
420 * Disable CONIDSTSCHNG controller interrupt in such
421 * case.
422 * 0 - No (default)
423 * 1 - Yes
424 * @power_down: Specifies whether the controller support power_down.
425 * If power_down is enabled, the controller will enter
426 * power_down in both peripheral and host mode when
427 * needed.
428 * 0 - No (default)
429 * 1 - Partial power down
430 * 2 - Hibernation
431 * @lpm: Enable LPM support.
432 * 0 - No
433 * 1 - Yes
434 * @lpm_clock_gating: Enable core PHY clock gating.
435 * 0 - No
436 * 1 - Yes
437 * @besl: Enable LPM Errata support.
438 * 0 - No
439 * 1 - Yes
440 * @hird_threshold_en: HIRD or HIRD Threshold enable.
441 * 0 - No
442 * 1 - Yes
443 * @hird_threshold: Value of BESL or HIRD Threshold.
444 * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO
445 * register.
446 * 0 - Deactivate the transceiver (default)
447 * 1 - Activate the transceiver
448 * @g_dma: Enables gadget dma usage (default: autodetect).
449 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect).
450 * @g_rx_fifo_size: The periodic rx fifo size for the device, in
451 * DWORDS from 16-32768 (default: 2048 if
452 * possible, otherwise autodetect).
453 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in
454 * DWORDS from 16-32768 (default: 1024 if
455 * possible, otherwise autodetect).
456 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo
457 * mode. Each value corresponds to one EP
458 * starting from EP1 (max 15 values). Sizes are
459 * in DWORDS with possible values from from
460 * 16-32768 (default: 256, 256, 256, 256, 768,
461 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
462 * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL
463 * while full&low speed device connect. And change speed
464 * back to DWC2_SPEED_PARAM_HIGH while device is gone.
465 * 0 - No (default)
466 * 1 - Yes
467 *
468 * The following parameters may be specified when starting the module. These
469 * parameters define how the DWC_otg controller should be configured. A
470 * value of -1 (or any other out of range value) for any parameter means
471 * to read the value from hardware (if possible) or use the builtin
472 * default described above.
473 */
474struct dwc2_core_params {
475 u8 otg_cap;
476#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
477#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
478#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
479
480 u8 phy_type;
481#define DWC2_PHY_TYPE_PARAM_FS 0
482#define DWC2_PHY_TYPE_PARAM_UTMI 1
483#define DWC2_PHY_TYPE_PARAM_ULPI 2
484
485 u8 speed;
486#define DWC2_SPEED_PARAM_HIGH 0
487#define DWC2_SPEED_PARAM_FULL 1
488#define DWC2_SPEED_PARAM_LOW 2
489
490 u8 phy_utmi_width;
491 bool phy_ulpi_ddr;
492 bool phy_ulpi_ext_vbus;
493 bool enable_dynamic_fifo;
494 bool en_multiple_tx_fifo;
495 bool i2c_enable;
496 bool acg_enable;
497 bool ulpi_fs_ls;
498 bool ts_dline;
499 bool reload_ctl;
500 bool uframe_sched;
501 bool external_id_pin_ctl;
502
503 int power_down;
504#define DWC2_POWER_DOWN_PARAM_NONE 0
505#define DWC2_POWER_DOWN_PARAM_PARTIAL 1
506#define DWC2_POWER_DOWN_PARAM_HIBERNATION 2
507
508 bool lpm;
509 bool lpm_clock_gating;
510 bool besl;
511 bool hird_threshold_en;
512 u8 hird_threshold;
513 bool activate_stm_fs_transceiver;
514 u16 max_packet_count;
515 u32 max_transfer_size;
516 u32 ahbcfg;
517
518 /* Host parameters */
519 bool host_dma;
520 bool dma_desc_enable;
521 bool dma_desc_fs_enable;
522 bool host_support_fs_ls_low_power;
523 bool host_ls_low_power_phy_clk;
524 bool oc_disable;
525
526 u8 host_channels;
527 u16 host_rx_fifo_size;
528 u16 host_nperio_tx_fifo_size;
529 u16 host_perio_tx_fifo_size;
530
531 /* Gadget parameters */
532 bool g_dma;
533 bool g_dma_desc;
534 u32 g_rx_fifo_size;
535 u32 g_np_tx_fifo_size;
536 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
537
538 bool change_speed_quirk;
539};
540
541/**
542 * struct dwc2_hw_params - Autodetected parameters.
543 *
544 * These parameters are the various parameters read from hardware
545 * registers during initialization. They typically contain the best
546 * supported or maximum value that can be configured in the
547 * corresponding dwc2_core_params value.
548 *
549 * The values that are not in dwc2_core_params are documented below.
550 *
551 * @op_mode Mode of Operation
552 * 0 - HNP- and SRP-Capable OTG (Host & Device)
553 * 1 - SRP-Capable OTG (Host & Device)
554 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
555 * 3 - SRP-Capable Device
556 * 4 - Non-OTG Device
557 * 5 - SRP-Capable Host
558 * 6 - Non-OTG Host
559 * @arch Architecture
560 * 0 - Slave only
561 * 1 - External DMA
562 * 2 - Internal DMA
563 * @power_optimized Are power optimizations enabled?
564 * @num_dev_ep Number of device endpoints available
565 * @num_dev_in_eps Number of device IN endpoints available
566 * @num_dev_perio_in_ep Number of device periodic IN endpoints
567 * available
568 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
569 * Depth
570 * 0 to 30
571 * @host_perio_tx_q_depth
572 * Host Mode Periodic Request Queue Depth
573 * 2, 4 or 8
574 * @nperio_tx_q_depth
575 * Non-Periodic Request Queue Depth
576 * 2, 4 or 8
577 * @hs_phy_type High-speed PHY interface type
578 * 0 - High-speed interface not supported
579 * 1 - UTMI+
580 * 2 - ULPI
581 * 3 - UTMI+ and ULPI
582 * @fs_phy_type Full-speed PHY interface type
583 * 0 - Full speed interface not supported
584 * 1 - Dedicated full speed interface
585 * 2 - FS pins shared with UTMI+ pins
586 * 3 - FS pins shared with ULPI pins
587 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
588 * @hibernation Is hibernation enabled?
589 * @utmi_phy_data_width UTMI+ PHY data width
590 * 0 - 8 bits
591 * 1 - 16 bits
592 * 2 - 8 or 16 bits
593 * @snpsid: Value from SNPSID register
594 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
595 * @g_tx_fifo_size[] Power-on values of TxFIFO sizes
596 */
597struct dwc2_hw_params {
598 unsigned op_mode:3;
599 unsigned arch:2;
600 unsigned dma_desc_enable:1;
601 unsigned enable_dynamic_fifo:1;
602 unsigned en_multiple_tx_fifo:1;
603 unsigned rx_fifo_size:16;
604 unsigned host_nperio_tx_fifo_size:16;
605 unsigned dev_nperio_tx_fifo_size:16;
606 unsigned host_perio_tx_fifo_size:16;
607 unsigned nperio_tx_q_depth:3;
608 unsigned host_perio_tx_q_depth:3;
609 unsigned dev_token_q_depth:5;
610 unsigned max_transfer_size:26;
611 unsigned max_packet_count:11;
612 unsigned host_channels:5;
613 unsigned hs_phy_type:2;
614 unsigned fs_phy_type:2;
615 unsigned i2c_enable:1;
616 unsigned acg_enable:1;
617 unsigned num_dev_ep:4;
618 unsigned num_dev_in_eps : 4;
619 unsigned num_dev_perio_in_ep:4;
620 unsigned total_fifo_size:16;
621 unsigned power_optimized:1;
622 unsigned hibernation:1;
623 unsigned utmi_phy_data_width:2;
624 unsigned lpm_mode:1;
625 u32 snpsid;
626 u32 dev_ep_dirs;
627 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
628};
629
630/* Size of control and EP0 buffers */
631#define DWC2_CTRL_BUFF_SIZE 8
632
633/**
634 * struct dwc2_gregs_backup - Holds global registers state before
635 * entering partial power down
636 * @gotgctl: Backup of GOTGCTL register
637 * @gintmsk: Backup of GINTMSK register
638 * @gahbcfg: Backup of GAHBCFG register
639 * @gusbcfg: Backup of GUSBCFG register
640 * @grxfsiz: Backup of GRXFSIZ register
641 * @gnptxfsiz: Backup of GNPTXFSIZ register
642 * @gi2cctl: Backup of GI2CCTL register
643 * @glpmcfg: Backup of GLPMCFG register
644 * @gdfifocfg: Backup of GDFIFOCFG register
645 * @gpwrdn: Backup of GPWRDN register
646 */
647struct dwc2_gregs_backup {
648 u32 gotgctl;
649 u32 gintmsk;
650 u32 gahbcfg;
651 u32 gusbcfg;
652 u32 grxfsiz;
653 u32 gnptxfsiz;
654 u32 gi2cctl;
655 u32 glpmcfg;
656 u32 pcgcctl;
657 u32 pcgcctl1;
658 u32 gdfifocfg;
659 u32 gpwrdn;
660 bool valid;
661};
662
663/**
664 * struct dwc2_dregs_backup - Holds device registers state before
665 * entering partial power down
666 * @dcfg: Backup of DCFG register
667 * @dctl: Backup of DCTL register
668 * @daintmsk: Backup of DAINTMSK register
669 * @diepmsk: Backup of DIEPMSK register
670 * @doepmsk: Backup of DOEPMSK register
671 * @diepctl: Backup of DIEPCTL register
672 * @dieptsiz: Backup of DIEPTSIZ register
673 * @diepdma: Backup of DIEPDMA register
674 * @doepctl: Backup of DOEPCTL register
675 * @doeptsiz: Backup of DOEPTSIZ register
676 * @doepdma: Backup of DOEPDMA register
677 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
678 */
679struct dwc2_dregs_backup {
680 u32 dcfg;
681 u32 dctl;
682 u32 daintmsk;
683 u32 diepmsk;
684 u32 doepmsk;
685 u32 diepctl[MAX_EPS_CHANNELS];
686 u32 dieptsiz[MAX_EPS_CHANNELS];
687 u32 diepdma[MAX_EPS_CHANNELS];
688 u32 doepctl[MAX_EPS_CHANNELS];
689 u32 doeptsiz[MAX_EPS_CHANNELS];
690 u32 doepdma[MAX_EPS_CHANNELS];
691 u32 dtxfsiz[MAX_EPS_CHANNELS];
692 bool valid;
693};
694
695/**
696 * struct dwc2_hregs_backup - Holds host registers state before
697 * entering partial power down
698 * @hcfg: Backup of HCFG register
699 * @haintmsk: Backup of HAINTMSK register
700 * @hcintmsk: Backup of HCINTMSK register
701 * @hptr0: Backup of HPTR0 register
702 * @hfir: Backup of HFIR register
703 * @hptxfsiz: Backup of HPTXFSIZ register
704 */
705struct dwc2_hregs_backup {
706 u32 hcfg;
707 u32 haintmsk;
708 u32 hcintmsk[MAX_EPS_CHANNELS];
709 u32 hprt0;
710 u32 hfir;
711 u32 hptxfsiz;
712 bool valid;
713};
714
715/*
716 * Constants related to high speed periodic scheduling
717 *
718 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a
719 * reservation point of view it's assumed that the schedule goes right back to
720 * the beginning after the end of the schedule.
721 *
722 * What does that mean for scheduling things with a long interval? It means
723 * we'll reserve time for them in every possible microframe that they could
724 * ever be scheduled in. ...but we'll still only actually schedule them as
725 * often as they were requested.
726 *
727 * We keep our schedule in a "bitmap" structure. This simplifies having
728 * to keep track of and merge intervals: we just let the bitmap code do most
729 * of the heavy lifting. In a way scheduling is much like memory allocation.
730 *
731 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're
732 * supposed to schedule for periodic transfers). That's according to spec.
733 *
734 * Note that though we only schedule 80% of each microframe, the bitmap that we
735 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of
736 * space for each uFrame).
737 *
738 * Requirements:
739 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
740 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
741 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might
742 * be bugs). The 8 comes from the USB spec: number of microframes per frame.
743 */
744#define DWC2_US_PER_UFRAME 125
745#define DWC2_HS_PERIODIC_US_PER_UFRAME 100
746
747#define DWC2_HS_SCHEDULE_UFRAMES 8
748#define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \
749 DWC2_HS_PERIODIC_US_PER_UFRAME)
750
751/*
752 * Constants related to low speed scheduling
753 *
754 * For high speed we schedule every 1us. For low speed that's a bit overkill,
755 * so we make up a unit called a "slice" that's worth 25us. There are 40
756 * slices in a full frame and we can schedule 36 of those (90%) for periodic
757 * transfers.
758 *
759 * Our low speed schedule can be as short as 1 frame or could be longer. When
760 * we only schedule 1 frame it means that we'll need to reserve a time every
761 * frame even for things that only transfer very rarely, so something that runs
762 * every 2048 frames will get time reserved in every frame. Our low speed
763 * schedule can be longer and we'll be able to handle more overlap, but that
764 * will come at increased memory cost and increased time to schedule.
765 *
766 * Note: one other advantage of a short low speed schedule is that if we mess
767 * up and miss scheduling we can jump in and use any of the slots that we
768 * happened to reserve.
769 *
770 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for
771 * the schedule. There will be one schedule per TT.
772 *
773 * Requirements:
774 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
775 */
776#define DWC2_US_PER_SLICE 25
777#define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE)
778
779#define DWC2_ROUND_US_TO_SLICE(us) \
780 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \
781 DWC2_US_PER_SLICE)
782
783#define DWC2_LS_PERIODIC_US_PER_FRAME \
784 900
785#define DWC2_LS_PERIODIC_SLICES_PER_FRAME \
786 (DWC2_LS_PERIODIC_US_PER_FRAME / \
787 DWC2_US_PER_SLICE)
788
789#define DWC2_LS_SCHEDULE_FRAMES 1
790#define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \
791 DWC2_LS_PERIODIC_SLICES_PER_FRAME)
792
793/**
794 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
795 * and periodic schedules
796 *
797 * These are common for both host and peripheral modes:
798 *
799 * @dev: The struct device pointer
800 * @regs: Pointer to controller regs
801 * @hw_params: Parameters that were autodetected from the
802 * hardware registers
803 * @core_params: Parameters that define how the core should be configured
804 * @op_state: The operational State, during transitions (a_host=>
805 * a_peripheral and b_device=>b_host) this may not match
806 * the core, but allows the software to determine
807 * transitions
808 * @dr_mode: Requested mode of operation, one of following:
809 * - USB_DR_MODE_PERIPHERAL
810 * - USB_DR_MODE_HOST
811 * - USB_DR_MODE_OTG
812 * @hcd_enabled Host mode sub-driver initialization indicator.
813 * @gadget_enabled Peripheral mode sub-driver initialization indicator.
814 * @ll_hw_enabled Status of low-level hardware resources.
815 * @hibernated: True if core is hibernated
816 * @phy: The otg phy transceiver structure for phy control.
817 * @uphy: The otg phy transceiver structure for old USB phy
818 * control.
819 * @plat: The platform specific configuration data. This can be
820 * removed once all SoCs support usb transceiver.
821 * @supplies: Definition of USB power supplies
822 * @vbus_supply: Regulator supplying vbus.
823 * @phyif: PHY interface width
824 * @lock: Spinlock that protects all the driver data structures
825 * @priv: Stores a pointer to the struct usb_hcd
826 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
827 * transfer are in process of being queued
828 * @srp_success: Stores status of SRP request in the case of a FS PHY
829 * with an I2C interface
830 * @wq_otg: Workqueue object used for handling of some interrupts
831 * @wf_otg: Work object for handling Connector ID Status Change
832 * interrupt
833 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
834 * @lx_state: Lx state of connected device
835 * @gregs_backup: Backup of global registers during suspend
836 * @dregs_backup: Backup of device registers during suspend
837 * @hregs_backup: Backup of host registers during suspend
838 *
839 * These are for host mode:
840 *
841 * @flags: Flags for handling root port state changes
842 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
843 * Transfers associated with these QHs are not currently
844 * assigned to a host channel.
845 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
846 * Transfers associated with these QHs are currently
847 * assigned to a host channel.
848 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
849 * non-periodic schedule
850 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
851 * list of QHs for periodic transfers that are _not_
852 * scheduled for the next frame. Each QH in the list has an
853 * interval counter that determines when it needs to be
854 * scheduled for execution. This scheduling mechanism
855 * allows only a simple calculation for periodic bandwidth
856 * used (i.e. must assume that all periodic transfers may
857 * need to execute in the same frame). However, it greatly
858 * simplifies scheduling and should be sufficient for the
859 * vast majority of OTG hosts, which need to connect to a
860 * small number of peripherals at one time. Items move from
861 * this list to periodic_sched_ready when the QH interval
862 * counter is 0 at SOF.
863 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
864 * the next frame, but have not yet been assigned to host
865 * channels. Items move from this list to
866 * periodic_sched_assigned as host channels become
867 * available during the current frame.
868 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
869 * frame that are assigned to host channels. Items move
870 * from this list to periodic_sched_queued as the
871 * transactions for the QH are queued to the DWC_otg
872 * controller.
873 * @periodic_sched_queued: List of periodic QHs that have been queued for
874 * execution. Items move from this list to either
875 * periodic_sched_inactive or periodic_sched_ready when the
876 * channel associated with the transfer is released. If the
877 * interval for the QH is 1, the item moves to
878 * periodic_sched_ready because it must be rescheduled for
879 * the next frame. Otherwise, the item moves to
880 * periodic_sched_inactive.
881 * @split_order: List keeping track of channels doing splits, in order.
882 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
883 * This value is in microseconds per (micro)frame. The
884 * assumption is that all periodic transfers may occur in
885 * the same (micro)frame.
886 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
887 * host is in high speed mode; low speed schedules are
888 * stored elsewhere since we need one per TT.
889 * @frame_number: Frame number read from the core at SOF. The value ranges
890 * from 0 to HFNUM_MAX_FRNUM.
891 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
892 * SOF enable/disable.
893 * @free_hc_list: Free host channels in the controller. This is a list of
894 * struct dwc2_host_chan items.
895 * @periodic_channels: Number of host channels assigned to periodic transfers.
896 * Currently assuming that there is a dedicated host
897 * channel for each periodic transaction and at least one
898 * host channel is available for non-periodic transactions.
899 * @non_periodic_channels: Number of host channels assigned to non-periodic
900 * transfers
901 * @available_host_channels Number of host channels available for the microframe
902 * scheduler to use
903 * @hc_ptr_array: Array of pointers to the host channel descriptors.
904 * Allows accessing a host channel descriptor given the
905 * host channel number. This is useful in interrupt
906 * handlers.
907 * @status_buf: Buffer used for data received during the status phase of
908 * a control transfer.
909 * @status_buf_dma: DMA address for status_buf
910 * @start_work: Delayed work for handling host A-cable connection
911 * @reset_work: Delayed work for handling a port reset
912 * @otg_port: OTG port number
913 * @frame_list: Frame list
914 * @frame_list_dma: Frame list DMA address
915 * @frame_list_sz: Frame list size
916 * @desc_gen_cache: Kmem cache for generic descriptors
917 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
918 *
919 * These are for peripheral mode:
920 *
921 * @driver: USB gadget driver
922 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
923 * @num_of_eps: Number of available EPs (excluding EP0)
924 * @debug_root: Root directrory for debugfs.
925 * @debug_file: Main status file for debugfs.
926 * @debug_testmode: Testmode status file for debugfs.
927 * @debug_fifo: FIFO status file for debugfs.
928 * @ep0_reply: Request used for ep0 reply.
929 * @ep0_buff: Buffer for EP0 reply data, if needed.
930 * @ctrl_buff: Buffer for EP0 control requests.
931 * @ctrl_req: Request for EP0 control packets.
932 * @ep0_state: EP0 control transfers state
933 * @test_mode: USB test mode requested by the host
934 * @remote_wakeup_allowed: True if device is allowed to wake-up host by
935 * remote-wakeup signalling
936 * @setup_desc_dma: EP0 setup stage desc chain DMA address
937 * @setup_desc: EP0 setup stage desc chain pointer
938 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address
939 * @ctrl_in_desc: EP0 IN data phase desc chain pointer
940 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address
941 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer
942 * @eps: The endpoints being supplied to the gadget framework
943 */
944struct dwc2_hsotg {
945 struct device *dev;
946 void __iomem *regs;
947 /** Params detected from hardware */
948 struct dwc2_hw_params hw_params;
949 /** Params to actually use */
950 struct dwc2_core_params params;
951 enum usb_otg_state op_state;
952 enum usb_dr_mode dr_mode;
953 unsigned int hcd_enabled:1;
954 unsigned int gadget_enabled:1;
955 unsigned int ll_hw_enabled:1;
956 unsigned int hibernated:1;
957
958 struct phy *phy;
959 struct usb_phy *uphy;
960 struct dwc2_hsotg_plat *plat;
961 struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES];
962 struct regulator *vbus_supply;
963 u32 phyif;
964
965 spinlock_t lock;
966 void *priv;
967 int irq;
968 struct clk *clk;
969 struct reset_control *reset;
970 struct reset_control *reset_ecc;
971
972 unsigned int queuing_high_bandwidth:1;
973 unsigned int srp_success:1;
974
975 struct workqueue_struct *wq_otg;
976 struct work_struct wf_otg;
977 struct timer_list wkp_timer;
978 enum dwc2_lx_state lx_state;
979 struct dwc2_gregs_backup gr_backup;
980 struct dwc2_dregs_backup dr_backup;
981 struct dwc2_hregs_backup hr_backup;
982
983 struct dentry *debug_root;
984 struct debugfs_regset32 *regset;
985
986 /* DWC OTG HW Release versions */
987#define DWC2_CORE_REV_2_71a 0x4f54271a
988#define DWC2_CORE_REV_2_72a 0x4f54272a
989#define DWC2_CORE_REV_2_80a 0x4f54280a
990#define DWC2_CORE_REV_2_90a 0x4f54290a
991#define DWC2_CORE_REV_2_91a 0x4f54291a
992#define DWC2_CORE_REV_2_92a 0x4f54292a
993#define DWC2_CORE_REV_2_94a 0x4f54294a
994#define DWC2_CORE_REV_3_00a 0x4f54300a
995#define DWC2_CORE_REV_3_10a 0x4f54310a
996#define DWC2_CORE_REV_4_00a 0x4f54400a
997#define DWC2_FS_IOT_REV_1_00a 0x5531100a
998#define DWC2_HS_IOT_REV_1_00a 0x5532100a
999
1000 /* DWC OTG HW Core ID */
1001#define DWC2_OTG_ID 0x4f540000
1002#define DWC2_FS_IOT_ID 0x55310000
1003#define DWC2_HS_IOT_ID 0x55320000
1004
1005#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1006 union dwc2_hcd_internal_flags {
1007 u32 d32;
1008 struct {
1009 unsigned port_connect_status_change:1;
1010 unsigned port_connect_status:1;
1011 unsigned port_reset_change:1;
1012 unsigned port_enable_change:1;
1013 unsigned port_suspend_change:1;
1014 unsigned port_over_current_change:1;
1015 unsigned port_l1_change:1;
1016 unsigned reserved:25;
1017 } b;
1018 } flags;
1019
1020 struct list_head non_periodic_sched_inactive;
1021 struct list_head non_periodic_sched_waiting;
1022 struct list_head non_periodic_sched_active;
1023 struct list_head *non_periodic_qh_ptr;
1024 struct list_head periodic_sched_inactive;
1025 struct list_head periodic_sched_ready;
1026 struct list_head periodic_sched_assigned;
1027 struct list_head periodic_sched_queued;
1028 struct list_head split_order;
1029 u16 periodic_usecs;
1030 unsigned long hs_periodic_bitmap[
1031 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)];
1032 u16 frame_number;
1033 u16 periodic_qh_count;
1034 bool bus_suspended;
1035 bool new_connection;
1036
1037 u16 last_frame_num;
1038
1039#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
1040#define FRAME_NUM_ARRAY_SIZE 1000
1041 u16 *frame_num_array;
1042 u16 *last_frame_num_array;
1043 int frame_num_idx;
1044 int dumped_frame_num_array;
1045#endif
1046
1047 struct list_head free_hc_list;
1048 int periodic_channels;
1049 int non_periodic_channels;
1050 int available_host_channels;
1051 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
1052 u8 *status_buf;
1053 dma_addr_t status_buf_dma;
1054#define DWC2_HCD_STATUS_BUF_SIZE 64
1055
1056 struct delayed_work start_work;
1057 struct delayed_work reset_work;
1058 u8 otg_port;
1059 u32 *frame_list;
1060 dma_addr_t frame_list_dma;
1061 u32 frame_list_sz;
1062 struct kmem_cache *desc_gen_cache;
1063 struct kmem_cache *desc_hsisoc_cache;
1064
1065#endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
1066
1067#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1068 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1069 /* Gadget structures */
1070 struct usb_gadget_driver *driver;
1071 int fifo_mem;
1072 unsigned int dedicated_fifos:1;
1073 unsigned char num_of_eps;
1074 u32 fifo_map;
1075
1076 struct usb_request *ep0_reply;
1077 struct usb_request *ctrl_req;
1078 void *ep0_buff;
1079 void *ctrl_buff;
1080 enum dwc2_ep0_state ep0_state;
1081 u8 test_mode;
1082
1083 dma_addr_t setup_desc_dma[2];
1084 struct dwc2_dma_desc *setup_desc[2];
1085 dma_addr_t ctrl_in_desc_dma;
1086 struct dwc2_dma_desc *ctrl_in_desc;
1087 dma_addr_t ctrl_out_desc_dma;
1088 struct dwc2_dma_desc *ctrl_out_desc;
1089
1090 struct usb_gadget gadget;
1091 unsigned int enabled:1;
1092 unsigned int connected:1;
1093 unsigned int remote_wakeup_allowed:1;
1094 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
1095 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
1096#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
1097};
1098
1099/* Reasons for halting a host channel */
1100enum dwc2_halt_status {
1101 DWC2_HC_XFER_NO_HALT_STATUS,
1102 DWC2_HC_XFER_COMPLETE,
1103 DWC2_HC_XFER_URB_COMPLETE,
1104 DWC2_HC_XFER_ACK,
1105 DWC2_HC_XFER_NAK,
1106 DWC2_HC_XFER_NYET,
1107 DWC2_HC_XFER_STALL,
1108 DWC2_HC_XFER_XACT_ERR,
1109 DWC2_HC_XFER_FRAME_OVERRUN,
1110 DWC2_HC_XFER_BABBLE_ERR,
1111 DWC2_HC_XFER_DATA_TOGGLE_ERR,
1112 DWC2_HC_XFER_AHB_ERR,
1113 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
1114 DWC2_HC_XFER_URB_DEQUEUE,
1115};
1116
1117/* Core version information */
1118static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg)
1119{
1120 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000;
1121}
1122
1123static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg)
1124{
1125 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000;
1126}
1127
1128static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg)
1129{
1130 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000;
1131}
1132
1133/*
1134 * The following functions support initialization of the core driver component
1135 * and the DWC_otg controller
1136 */
1137int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait);
1138int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg);
1139int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore);
1140int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host);
1141int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
1142 int reset, int is_host);
1143
1144void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host);
1145void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
1146
1147bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
1148
1149/*
1150 * Common core Functions.
1151 * The following functions support managing the DWC_otg controller in either
1152 * device or host mode.
1153 */
1154void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
1155void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
1156void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
1157
1158void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
1159void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
1160
1161void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
1162 int is_host);
1163int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg);
1164int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg);
1165
1166void dwc2_enable_acg(struct dwc2_hsotg *hsotg);
1167
1168/* This function should be called on every hardware interrupt. */
1169irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
1170
1171/* The device ID match table */
1172extern const struct of_device_id dwc2_of_match_table[];
1173
1174int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1175int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
1176
1177/* Common polling functions */
1178int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
1179 u32 timeout);
1180int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
1181 u32 timeout);
1182/* Parameters */
1183int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
1184int dwc2_init_params(struct dwc2_hsotg *hsotg);
1185
1186/*
1187 * The following functions check the controller's OTG operation mode
1188 * capability (GHWCFG2.OTG_MODE).
1189 *
1190 * These functions can be used before the internal hsotg->hw_params
1191 * are read in and cached so they always read directly from the
1192 * GHWCFG2 register.
1193 */
1194unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg);
1195bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1196bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1197bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1198
1199/*
1200 * Returns the mode of operation, host or device
1201 */
1202static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1203{
1204 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1205}
1206
1207static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1208{
1209 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1210}
1211
1212/*
1213 * Dump core registers and SPRAM
1214 */
1215void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1216void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1217void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
1218
1219/* Gadget defines */
1220#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1221 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1222int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1223int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1224int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
1225int dwc2_gadget_init(struct dwc2_hsotg *hsotg);
1226void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1227 bool reset);
1228void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1229void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1230int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
1231#define dwc2_is_device_connected(hsotg) (hsotg->connected)
1232int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
1233int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup);
1234int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg);
1235int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
1236 int rem_wakeup, int reset);
1237int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg);
1238int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg);
1239int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg);
1240void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg);
1241#else
1242static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
1243{ return 0; }
1244static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
1245{ return 0; }
1246static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
1247{ return 0; }
1248static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
1249{ return 0; }
1250static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1251 bool reset) {}
1252static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
1253static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
1254static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
1255 int testmode)
1256{ return 0; }
1257#define dwc2_is_device_connected(hsotg) (0)
1258static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
1259{ return 0; }
1260static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg,
1261 int remote_wakeup)
1262{ return 0; }
1263static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
1264{ return 0; }
1265static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
1266 int rem_wakeup, int reset)
1267{ return 0; }
1268static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
1269{ return 0; }
1270static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
1271{ return 0; }
1272static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
1273{ return 0; }
1274static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {}
1275#endif
1276
1277#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1278int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1279int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
1280void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1281void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
1282void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
1283int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup);
1284int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
1285int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
1286int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg);
1287int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
1288 int rem_wakeup, int reset);
1289#else
1290static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1291{ return 0; }
1292static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg,
1293 int us)
1294{ return 0; }
1295static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
1296static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
1297static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
1298static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
1299static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
1300{ return 0; }
1301static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
1302{ return 0; }
1303static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
1304{ return 0; }
1305static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
1306{ return 0; }
1307static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
1308{ return 0; }
1309static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
1310 int rem_wakeup, int reset)
1311{ return 0; }
1312
1313#endif
1314
1315#endif /* __DWC2_CORE_H__ */