Loading...
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63#include <linux/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
72#include <ttm/ttm_execbuf_util.h>
73
74#include "radeon_family.h"
75#include "radeon_mode.h"
76#include "radeon_reg.h"
77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
89extern int radeon_testing;
90extern int radeon_connector_table;
91extern int radeon_tv;
92extern int radeon_audio;
93extern int radeon_disp_priority;
94extern int radeon_hw_i2c;
95extern int radeon_pcie_gen2;
96
97/*
98 * Copy from radeon_drv.h so we don't have to include both and have conflicting
99 * symbol;
100 */
101#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
102#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
103/* RADEON_IB_POOL_SIZE must be a power of 2 */
104#define RADEON_IB_POOL_SIZE 16
105#define RADEON_DEBUGFS_MAX_NUM_FILES 32
106#define RADEONFB_CONN_LIMIT 4
107#define RADEON_BIOS_NUM_SCRATCH 8
108
109/*
110 * Errata workarounds.
111 */
112enum radeon_pll_errata {
113 CHIP_ERRATA_R300_CG = 0x00000001,
114 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
115 CHIP_ERRATA_PLL_DELAY = 0x00000004
116};
117
118
119struct radeon_device;
120
121
122/*
123 * BIOS.
124 */
125#define ATRM_BIOS_PAGE 4096
126
127#if defined(CONFIG_VGA_SWITCHEROO)
128bool radeon_atrm_supported(struct pci_dev *pdev);
129int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
130#else
131static inline bool radeon_atrm_supported(struct pci_dev *pdev)
132{
133 return false;
134}
135
136static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
137 return -EINVAL;
138}
139#endif
140bool radeon_get_bios(struct radeon_device *rdev);
141
142
143/*
144 * Dummy page
145 */
146struct radeon_dummy_page {
147 struct page *page;
148 dma_addr_t addr;
149};
150int radeon_dummy_page_init(struct radeon_device *rdev);
151void radeon_dummy_page_fini(struct radeon_device *rdev);
152
153
154/*
155 * Clocks
156 */
157struct radeon_clock {
158 struct radeon_pll p1pll;
159 struct radeon_pll p2pll;
160 struct radeon_pll dcpll;
161 struct radeon_pll spll;
162 struct radeon_pll mpll;
163 /* 10 Khz units */
164 uint32_t default_mclk;
165 uint32_t default_sclk;
166 uint32_t default_dispclk;
167 uint32_t dp_extclk;
168 uint32_t max_pixel_clock;
169};
170
171/*
172 * Power management
173 */
174int radeon_pm_init(struct radeon_device *rdev);
175void radeon_pm_fini(struct radeon_device *rdev);
176void radeon_pm_compute_clocks(struct radeon_device *rdev);
177void radeon_pm_suspend(struct radeon_device *rdev);
178void radeon_pm_resume(struct radeon_device *rdev);
179void radeon_combios_get_power_modes(struct radeon_device *rdev);
180void radeon_atombios_get_power_modes(struct radeon_device *rdev);
181void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
182int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
183void rs690_pm_info(struct radeon_device *rdev);
184extern int rv6xx_get_temp(struct radeon_device *rdev);
185extern int rv770_get_temp(struct radeon_device *rdev);
186extern int evergreen_get_temp(struct radeon_device *rdev);
187extern int sumo_get_temp(struct radeon_device *rdev);
188
189/*
190 * Fences.
191 */
192struct radeon_fence_driver {
193 uint32_t scratch_reg;
194 atomic_t seq;
195 uint32_t last_seq;
196 unsigned long last_jiffies;
197 unsigned long last_timeout;
198 wait_queue_head_t queue;
199 rwlock_t lock;
200 struct list_head created;
201 struct list_head emited;
202 struct list_head signaled;
203 bool initialized;
204};
205
206struct radeon_fence {
207 struct radeon_device *rdev;
208 struct kref kref;
209 struct list_head list;
210 /* protected by radeon_fence.lock */
211 uint32_t seq;
212 bool emited;
213 bool signaled;
214};
215
216int radeon_fence_driver_init(struct radeon_device *rdev);
217void radeon_fence_driver_fini(struct radeon_device *rdev);
218int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
219int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
220void radeon_fence_process(struct radeon_device *rdev);
221bool radeon_fence_signaled(struct radeon_fence *fence);
222int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
223int radeon_fence_wait_next(struct radeon_device *rdev);
224int radeon_fence_wait_last(struct radeon_device *rdev);
225struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
226void radeon_fence_unref(struct radeon_fence **fence);
227
228/*
229 * Tiling registers
230 */
231struct radeon_surface_reg {
232 struct radeon_bo *bo;
233};
234
235#define RADEON_GEM_MAX_SURFACES 8
236
237/*
238 * TTM.
239 */
240struct radeon_mman {
241 struct ttm_bo_global_ref bo_global_ref;
242 struct drm_global_reference mem_global_ref;
243 struct ttm_bo_device bdev;
244 bool mem_global_referenced;
245 bool initialized;
246};
247
248struct radeon_bo {
249 /* Protected by gem.mutex */
250 struct list_head list;
251 /* Protected by tbo.reserved */
252 u32 placements[3];
253 struct ttm_placement placement;
254 struct ttm_buffer_object tbo;
255 struct ttm_bo_kmap_obj kmap;
256 unsigned pin_count;
257 void *kptr;
258 u32 tiling_flags;
259 u32 pitch;
260 int surface_reg;
261 /* Constant after initialization */
262 struct radeon_device *rdev;
263 struct drm_gem_object gem_base;
264};
265#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
266
267struct radeon_bo_list {
268 struct ttm_validate_buffer tv;
269 struct radeon_bo *bo;
270 uint64_t gpu_offset;
271 unsigned rdomain;
272 unsigned wdomain;
273 u32 tiling_flags;
274};
275
276/*
277 * GEM objects.
278 */
279struct radeon_gem {
280 struct mutex mutex;
281 struct list_head objects;
282};
283
284int radeon_gem_init(struct radeon_device *rdev);
285void radeon_gem_fini(struct radeon_device *rdev);
286int radeon_gem_object_create(struct radeon_device *rdev, int size,
287 int alignment, int initial_domain,
288 bool discardable, bool kernel,
289 struct drm_gem_object **obj);
290int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
291 uint64_t *gpu_addr);
292void radeon_gem_object_unpin(struct drm_gem_object *obj);
293
294int radeon_mode_dumb_create(struct drm_file *file_priv,
295 struct drm_device *dev,
296 struct drm_mode_create_dumb *args);
297int radeon_mode_dumb_mmap(struct drm_file *filp,
298 struct drm_device *dev,
299 uint32_t handle, uint64_t *offset_p);
300int radeon_mode_dumb_destroy(struct drm_file *file_priv,
301 struct drm_device *dev,
302 uint32_t handle);
303
304/*
305 * GART structures, functions & helpers
306 */
307struct radeon_mc;
308
309struct radeon_gart_table_ram {
310 volatile uint32_t *ptr;
311};
312
313struct radeon_gart_table_vram {
314 struct radeon_bo *robj;
315 volatile uint32_t *ptr;
316};
317
318union radeon_gart_table {
319 struct radeon_gart_table_ram ram;
320 struct radeon_gart_table_vram vram;
321};
322
323#define RADEON_GPU_PAGE_SIZE 4096
324#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
325#define RADEON_GPU_PAGE_SHIFT 12
326
327struct radeon_gart {
328 dma_addr_t table_addr;
329 unsigned num_gpu_pages;
330 unsigned num_cpu_pages;
331 unsigned table_size;
332 union radeon_gart_table table;
333 struct page **pages;
334 dma_addr_t *pages_addr;
335 bool *ttm_alloced;
336 bool ready;
337};
338
339int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
340void radeon_gart_table_ram_free(struct radeon_device *rdev);
341int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
342void radeon_gart_table_vram_free(struct radeon_device *rdev);
343int radeon_gart_init(struct radeon_device *rdev);
344void radeon_gart_fini(struct radeon_device *rdev);
345void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
346 int pages);
347int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
348 int pages, struct page **pagelist,
349 dma_addr_t *dma_addr);
350
351
352/*
353 * GPU MC structures, functions & helpers
354 */
355struct radeon_mc {
356 resource_size_t aper_size;
357 resource_size_t aper_base;
358 resource_size_t agp_base;
359 /* for some chips with <= 32MB we need to lie
360 * about vram size near mc fb location */
361 u64 mc_vram_size;
362 u64 visible_vram_size;
363 u64 gtt_size;
364 u64 gtt_start;
365 u64 gtt_end;
366 u64 vram_start;
367 u64 vram_end;
368 unsigned vram_width;
369 u64 real_vram_size;
370 int vram_mtrr;
371 bool vram_is_ddr;
372 bool igp_sideport_enabled;
373 u64 gtt_base_align;
374};
375
376bool radeon_combios_sideport_present(struct radeon_device *rdev);
377bool radeon_atombios_sideport_present(struct radeon_device *rdev);
378
379/*
380 * GPU scratch registers structures, functions & helpers
381 */
382struct radeon_scratch {
383 unsigned num_reg;
384 uint32_t reg_base;
385 bool free[32];
386 uint32_t reg[32];
387};
388
389int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
390void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
391
392
393/*
394 * IRQS.
395 */
396
397struct radeon_unpin_work {
398 struct work_struct work;
399 struct radeon_device *rdev;
400 int crtc_id;
401 struct radeon_fence *fence;
402 struct drm_pending_vblank_event *event;
403 struct radeon_bo *old_rbo;
404 u64 new_crtc_base;
405};
406
407struct r500_irq_stat_regs {
408 u32 disp_int;
409};
410
411struct r600_irq_stat_regs {
412 u32 disp_int;
413 u32 disp_int_cont;
414 u32 disp_int_cont2;
415 u32 d1grph_int;
416 u32 d2grph_int;
417};
418
419struct evergreen_irq_stat_regs {
420 u32 disp_int;
421 u32 disp_int_cont;
422 u32 disp_int_cont2;
423 u32 disp_int_cont3;
424 u32 disp_int_cont4;
425 u32 disp_int_cont5;
426 u32 d1grph_int;
427 u32 d2grph_int;
428 u32 d3grph_int;
429 u32 d4grph_int;
430 u32 d5grph_int;
431 u32 d6grph_int;
432};
433
434union radeon_irq_stat_regs {
435 struct r500_irq_stat_regs r500;
436 struct r600_irq_stat_regs r600;
437 struct evergreen_irq_stat_regs evergreen;
438};
439
440struct radeon_irq {
441 bool installed;
442 bool sw_int;
443 /* FIXME: use a define max crtc rather than hardcode it */
444 bool crtc_vblank_int[6];
445 bool pflip[6];
446 wait_queue_head_t vblank_queue;
447 /* FIXME: use defines for max hpd/dacs */
448 bool hpd[6];
449 bool gui_idle;
450 bool gui_idle_acked;
451 wait_queue_head_t idle_queue;
452 /* FIXME: use defines for max HDMI blocks */
453 bool hdmi[2];
454 spinlock_t sw_lock;
455 int sw_refcount;
456 union radeon_irq_stat_regs stat_regs;
457 spinlock_t pflip_lock[6];
458 int pflip_refcount[6];
459};
460
461int radeon_irq_kms_init(struct radeon_device *rdev);
462void radeon_irq_kms_fini(struct radeon_device *rdev);
463void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
464void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
465void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
466void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
467
468/*
469 * CP & ring.
470 */
471struct radeon_ib {
472 struct list_head list;
473 unsigned idx;
474 uint64_t gpu_addr;
475 struct radeon_fence *fence;
476 uint32_t *ptr;
477 uint32_t length_dw;
478 bool free;
479};
480
481/*
482 * locking -
483 * mutex protects scheduled_ibs, ready, alloc_bm
484 */
485struct radeon_ib_pool {
486 struct mutex mutex;
487 struct radeon_bo *robj;
488 struct list_head bogus_ib;
489 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
490 bool ready;
491 unsigned head_id;
492};
493
494struct radeon_cp {
495 struct radeon_bo *ring_obj;
496 volatile uint32_t *ring;
497 unsigned rptr;
498 unsigned wptr;
499 unsigned wptr_old;
500 unsigned ring_size;
501 unsigned ring_free_dw;
502 int count_dw;
503 uint64_t gpu_addr;
504 uint32_t align_mask;
505 uint32_t ptr_mask;
506 struct mutex mutex;
507 bool ready;
508};
509
510/*
511 * R6xx+ IH ring
512 */
513struct r600_ih {
514 struct radeon_bo *ring_obj;
515 volatile uint32_t *ring;
516 unsigned rptr;
517 unsigned wptr;
518 unsigned wptr_old;
519 unsigned ring_size;
520 uint64_t gpu_addr;
521 uint32_t ptr_mask;
522 spinlock_t lock;
523 bool enabled;
524};
525
526struct r600_blit {
527 struct mutex mutex;
528 struct radeon_bo *shader_obj;
529 u64 shader_gpu_addr;
530 u32 vs_offset, ps_offset;
531 u32 state_offset;
532 u32 state_len;
533 u32 vb_used, vb_total;
534 struct radeon_ib *vb_ib;
535};
536
537int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
538void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
539int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
540int radeon_ib_pool_init(struct radeon_device *rdev);
541void radeon_ib_pool_fini(struct radeon_device *rdev);
542int radeon_ib_test(struct radeon_device *rdev);
543extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
544/* Ring access between begin & end cannot sleep */
545void radeon_ring_free_size(struct radeon_device *rdev);
546int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
547int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
548void radeon_ring_commit(struct radeon_device *rdev);
549void radeon_ring_unlock_commit(struct radeon_device *rdev);
550void radeon_ring_unlock_undo(struct radeon_device *rdev);
551int radeon_ring_test(struct radeon_device *rdev);
552int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
553void radeon_ring_fini(struct radeon_device *rdev);
554
555
556/*
557 * CS.
558 */
559struct radeon_cs_reloc {
560 struct drm_gem_object *gobj;
561 struct radeon_bo *robj;
562 struct radeon_bo_list lobj;
563 uint32_t handle;
564 uint32_t flags;
565};
566
567struct radeon_cs_chunk {
568 uint32_t chunk_id;
569 uint32_t length_dw;
570 int kpage_idx[2];
571 uint32_t *kpage[2];
572 uint32_t *kdata;
573 void __user *user_ptr;
574 int last_copied_page;
575 int last_page_index;
576};
577
578struct radeon_cs_parser {
579 struct device *dev;
580 struct radeon_device *rdev;
581 struct drm_file *filp;
582 /* chunks */
583 unsigned nchunks;
584 struct radeon_cs_chunk *chunks;
585 uint64_t *chunks_array;
586 /* IB */
587 unsigned idx;
588 /* relocations */
589 unsigned nrelocs;
590 struct radeon_cs_reloc *relocs;
591 struct radeon_cs_reloc **relocs_ptr;
592 struct list_head validated;
593 /* indices of various chunks */
594 int chunk_ib_idx;
595 int chunk_relocs_idx;
596 struct radeon_ib *ib;
597 void *track;
598 unsigned family;
599 int parser_error;
600};
601
602extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
603extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
604
605
606static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
607{
608 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
609 u32 pg_idx, pg_offset;
610 u32 idx_value = 0;
611 int new_page;
612
613 pg_idx = (idx * 4) / PAGE_SIZE;
614 pg_offset = (idx * 4) % PAGE_SIZE;
615
616 if (ibc->kpage_idx[0] == pg_idx)
617 return ibc->kpage[0][pg_offset/4];
618 if (ibc->kpage_idx[1] == pg_idx)
619 return ibc->kpage[1][pg_offset/4];
620
621 new_page = radeon_cs_update_pages(p, pg_idx);
622 if (new_page < 0) {
623 p->parser_error = new_page;
624 return 0;
625 }
626
627 idx_value = ibc->kpage[new_page][pg_offset/4];
628 return idx_value;
629}
630
631struct radeon_cs_packet {
632 unsigned idx;
633 unsigned type;
634 unsigned reg;
635 unsigned opcode;
636 int count;
637 unsigned one_reg_wr;
638};
639
640typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
641 struct radeon_cs_packet *pkt,
642 unsigned idx, unsigned reg);
643typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
644 struct radeon_cs_packet *pkt);
645
646
647/*
648 * AGP
649 */
650int radeon_agp_init(struct radeon_device *rdev);
651void radeon_agp_resume(struct radeon_device *rdev);
652void radeon_agp_suspend(struct radeon_device *rdev);
653void radeon_agp_fini(struct radeon_device *rdev);
654
655
656/*
657 * Writeback
658 */
659struct radeon_wb {
660 struct radeon_bo *wb_obj;
661 volatile uint32_t *wb;
662 uint64_t gpu_addr;
663 bool enabled;
664 bool use_event;
665};
666
667#define RADEON_WB_SCRATCH_OFFSET 0
668#define RADEON_WB_CP_RPTR_OFFSET 1024
669#define RADEON_WB_CP1_RPTR_OFFSET 1280
670#define RADEON_WB_CP2_RPTR_OFFSET 1536
671#define R600_WB_IH_WPTR_OFFSET 2048
672#define R600_WB_EVENT_OFFSET 3072
673
674/**
675 * struct radeon_pm - power management datas
676 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
677 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
678 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
679 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
680 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
681 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
682 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
683 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
684 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
685 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
686 * @needed_bandwidth: current bandwidth needs
687 *
688 * It keeps track of various data needed to take powermanagement decision.
689 * Bandwidth need is used to determine minimun clock of the GPU and memory.
690 * Equation between gpu/memory clock and available bandwidth is hw dependent
691 * (type of memory, bus size, efficiency, ...)
692 */
693
694enum radeon_pm_method {
695 PM_METHOD_PROFILE,
696 PM_METHOD_DYNPM,
697};
698
699enum radeon_dynpm_state {
700 DYNPM_STATE_DISABLED,
701 DYNPM_STATE_MINIMUM,
702 DYNPM_STATE_PAUSED,
703 DYNPM_STATE_ACTIVE,
704 DYNPM_STATE_SUSPENDED,
705};
706enum radeon_dynpm_action {
707 DYNPM_ACTION_NONE,
708 DYNPM_ACTION_MINIMUM,
709 DYNPM_ACTION_DOWNCLOCK,
710 DYNPM_ACTION_UPCLOCK,
711 DYNPM_ACTION_DEFAULT
712};
713
714enum radeon_voltage_type {
715 VOLTAGE_NONE = 0,
716 VOLTAGE_GPIO,
717 VOLTAGE_VDDC,
718 VOLTAGE_SW
719};
720
721enum radeon_pm_state_type {
722 POWER_STATE_TYPE_DEFAULT,
723 POWER_STATE_TYPE_POWERSAVE,
724 POWER_STATE_TYPE_BATTERY,
725 POWER_STATE_TYPE_BALANCED,
726 POWER_STATE_TYPE_PERFORMANCE,
727};
728
729enum radeon_pm_profile_type {
730 PM_PROFILE_DEFAULT,
731 PM_PROFILE_AUTO,
732 PM_PROFILE_LOW,
733 PM_PROFILE_MID,
734 PM_PROFILE_HIGH,
735};
736
737#define PM_PROFILE_DEFAULT_IDX 0
738#define PM_PROFILE_LOW_SH_IDX 1
739#define PM_PROFILE_MID_SH_IDX 2
740#define PM_PROFILE_HIGH_SH_IDX 3
741#define PM_PROFILE_LOW_MH_IDX 4
742#define PM_PROFILE_MID_MH_IDX 5
743#define PM_PROFILE_HIGH_MH_IDX 6
744#define PM_PROFILE_MAX 7
745
746struct radeon_pm_profile {
747 int dpms_off_ps_idx;
748 int dpms_on_ps_idx;
749 int dpms_off_cm_idx;
750 int dpms_on_cm_idx;
751};
752
753enum radeon_int_thermal_type {
754 THERMAL_TYPE_NONE,
755 THERMAL_TYPE_RV6XX,
756 THERMAL_TYPE_RV770,
757 THERMAL_TYPE_EVERGREEN,
758 THERMAL_TYPE_SUMO,
759 THERMAL_TYPE_NI,
760};
761
762struct radeon_voltage {
763 enum radeon_voltage_type type;
764 /* gpio voltage */
765 struct radeon_gpio_rec gpio;
766 u32 delay; /* delay in usec from voltage drop to sclk change */
767 bool active_high; /* voltage drop is active when bit is high */
768 /* VDDC voltage */
769 u8 vddc_id; /* index into vddc voltage table */
770 u8 vddci_id; /* index into vddci voltage table */
771 bool vddci_enabled;
772 /* r6xx+ sw */
773 u16 voltage;
774 /* evergreen+ vddci */
775 u16 vddci;
776};
777
778/* clock mode flags */
779#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
780
781struct radeon_pm_clock_info {
782 /* memory clock */
783 u32 mclk;
784 /* engine clock */
785 u32 sclk;
786 /* voltage info */
787 struct radeon_voltage voltage;
788 /* standardized clock flags */
789 u32 flags;
790};
791
792/* state flags */
793#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
794
795struct radeon_power_state {
796 enum radeon_pm_state_type type;
797 /* XXX: use a define for num clock modes */
798 struct radeon_pm_clock_info clock_info[8];
799 /* number of valid clock modes in this power state */
800 int num_clock_modes;
801 struct radeon_pm_clock_info *default_clock_mode;
802 /* standardized state flags */
803 u32 flags;
804 u32 misc; /* vbios specific flags */
805 u32 misc2; /* vbios specific flags */
806 int pcie_lanes; /* pcie lanes */
807};
808
809/*
810 * Some modes are overclocked by very low value, accept them
811 */
812#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
813
814struct radeon_pm {
815 struct mutex mutex;
816 u32 active_crtcs;
817 int active_crtc_count;
818 int req_vblank;
819 bool vblank_sync;
820 bool gui_idle;
821 fixed20_12 max_bandwidth;
822 fixed20_12 igp_sideport_mclk;
823 fixed20_12 igp_system_mclk;
824 fixed20_12 igp_ht_link_clk;
825 fixed20_12 igp_ht_link_width;
826 fixed20_12 k8_bandwidth;
827 fixed20_12 sideport_bandwidth;
828 fixed20_12 ht_bandwidth;
829 fixed20_12 core_bandwidth;
830 fixed20_12 sclk;
831 fixed20_12 mclk;
832 fixed20_12 needed_bandwidth;
833 struct radeon_power_state *power_state;
834 /* number of valid power states */
835 int num_power_states;
836 int current_power_state_index;
837 int current_clock_mode_index;
838 int requested_power_state_index;
839 int requested_clock_mode_index;
840 int default_power_state_index;
841 u32 current_sclk;
842 u32 current_mclk;
843 u16 current_vddc;
844 u16 current_vddci;
845 u32 default_sclk;
846 u32 default_mclk;
847 u16 default_vddc;
848 u16 default_vddci;
849 struct radeon_i2c_chan *i2c_bus;
850 /* selected pm method */
851 enum radeon_pm_method pm_method;
852 /* dynpm power management */
853 struct delayed_work dynpm_idle_work;
854 enum radeon_dynpm_state dynpm_state;
855 enum radeon_dynpm_action dynpm_planned_action;
856 unsigned long dynpm_action_timeout;
857 bool dynpm_can_upclock;
858 bool dynpm_can_downclock;
859 /* profile-based power management */
860 enum radeon_pm_profile_type profile;
861 int profile_index;
862 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
863 /* internal thermal controller on rv6xx+ */
864 enum radeon_int_thermal_type int_thermal_type;
865 struct device *int_hwmon_dev;
866};
867
868
869/*
870 * Benchmarking
871 */
872void radeon_benchmark(struct radeon_device *rdev);
873
874
875/*
876 * Testing
877 */
878void radeon_test_moves(struct radeon_device *rdev);
879
880
881/*
882 * Debugfs
883 */
884int radeon_debugfs_add_files(struct radeon_device *rdev,
885 struct drm_info_list *files,
886 unsigned nfiles);
887int radeon_debugfs_fence_init(struct radeon_device *rdev);
888
889
890/*
891 * ASIC specific functions.
892 */
893struct radeon_asic {
894 int (*init)(struct radeon_device *rdev);
895 void (*fini)(struct radeon_device *rdev);
896 int (*resume)(struct radeon_device *rdev);
897 int (*suspend)(struct radeon_device *rdev);
898 void (*vga_set_state)(struct radeon_device *rdev, bool state);
899 bool (*gpu_is_lockup)(struct radeon_device *rdev);
900 int (*asic_reset)(struct radeon_device *rdev);
901 void (*gart_tlb_flush)(struct radeon_device *rdev);
902 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
903 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
904 void (*cp_fini)(struct radeon_device *rdev);
905 void (*cp_disable)(struct radeon_device *rdev);
906 void (*cp_commit)(struct radeon_device *rdev);
907 void (*ring_start)(struct radeon_device *rdev);
908 int (*ring_test)(struct radeon_device *rdev);
909 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
910 int (*irq_set)(struct radeon_device *rdev);
911 int (*irq_process)(struct radeon_device *rdev);
912 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
913 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
914 int (*cs_parse)(struct radeon_cs_parser *p);
915 int (*copy_blit)(struct radeon_device *rdev,
916 uint64_t src_offset,
917 uint64_t dst_offset,
918 unsigned num_gpu_pages,
919 struct radeon_fence *fence);
920 int (*copy_dma)(struct radeon_device *rdev,
921 uint64_t src_offset,
922 uint64_t dst_offset,
923 unsigned num_gpu_pages,
924 struct radeon_fence *fence);
925 int (*copy)(struct radeon_device *rdev,
926 uint64_t src_offset,
927 uint64_t dst_offset,
928 unsigned num_gpu_pages,
929 struct radeon_fence *fence);
930 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
931 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
932 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
933 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
934 int (*get_pcie_lanes)(struct radeon_device *rdev);
935 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
936 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
937 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
938 uint32_t tiling_flags, uint32_t pitch,
939 uint32_t offset, uint32_t obj_size);
940 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
941 void (*bandwidth_update)(struct radeon_device *rdev);
942 void (*hpd_init)(struct radeon_device *rdev);
943 void (*hpd_fini)(struct radeon_device *rdev);
944 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
945 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
946 /* ioctl hw specific callback. Some hw might want to perform special
947 * operation on specific ioctl. For instance on wait idle some hw
948 * might want to perform and HDP flush through MMIO as it seems that
949 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
950 * through ring.
951 */
952 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
953 bool (*gui_idle)(struct radeon_device *rdev);
954 /* power management */
955 void (*pm_misc)(struct radeon_device *rdev);
956 void (*pm_prepare)(struct radeon_device *rdev);
957 void (*pm_finish)(struct radeon_device *rdev);
958 void (*pm_init_profile)(struct radeon_device *rdev);
959 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
960 /* pageflipping */
961 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
962 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
963 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
964};
965
966/*
967 * Asic structures
968 */
969struct r100_gpu_lockup {
970 unsigned long last_jiffies;
971 u32 last_cp_rptr;
972};
973
974struct r100_asic {
975 const unsigned *reg_safe_bm;
976 unsigned reg_safe_bm_size;
977 u32 hdp_cntl;
978 struct r100_gpu_lockup lockup;
979};
980
981struct r300_asic {
982 const unsigned *reg_safe_bm;
983 unsigned reg_safe_bm_size;
984 u32 resync_scratch;
985 u32 hdp_cntl;
986 struct r100_gpu_lockup lockup;
987};
988
989struct r600_asic {
990 unsigned max_pipes;
991 unsigned max_tile_pipes;
992 unsigned max_simds;
993 unsigned max_backends;
994 unsigned max_gprs;
995 unsigned max_threads;
996 unsigned max_stack_entries;
997 unsigned max_hw_contexts;
998 unsigned max_gs_threads;
999 unsigned sx_max_export_size;
1000 unsigned sx_max_export_pos_size;
1001 unsigned sx_max_export_smx_size;
1002 unsigned sq_num_cf_insts;
1003 unsigned tiling_nbanks;
1004 unsigned tiling_npipes;
1005 unsigned tiling_group_size;
1006 unsigned tile_config;
1007 unsigned backend_map;
1008 struct r100_gpu_lockup lockup;
1009};
1010
1011struct rv770_asic {
1012 unsigned max_pipes;
1013 unsigned max_tile_pipes;
1014 unsigned max_simds;
1015 unsigned max_backends;
1016 unsigned max_gprs;
1017 unsigned max_threads;
1018 unsigned max_stack_entries;
1019 unsigned max_hw_contexts;
1020 unsigned max_gs_threads;
1021 unsigned sx_max_export_size;
1022 unsigned sx_max_export_pos_size;
1023 unsigned sx_max_export_smx_size;
1024 unsigned sq_num_cf_insts;
1025 unsigned sx_num_of_sets;
1026 unsigned sc_prim_fifo_size;
1027 unsigned sc_hiz_tile_fifo_size;
1028 unsigned sc_earlyz_tile_fifo_fize;
1029 unsigned tiling_nbanks;
1030 unsigned tiling_npipes;
1031 unsigned tiling_group_size;
1032 unsigned tile_config;
1033 unsigned backend_map;
1034 struct r100_gpu_lockup lockup;
1035};
1036
1037struct evergreen_asic {
1038 unsigned num_ses;
1039 unsigned max_pipes;
1040 unsigned max_tile_pipes;
1041 unsigned max_simds;
1042 unsigned max_backends;
1043 unsigned max_gprs;
1044 unsigned max_threads;
1045 unsigned max_stack_entries;
1046 unsigned max_hw_contexts;
1047 unsigned max_gs_threads;
1048 unsigned sx_max_export_size;
1049 unsigned sx_max_export_pos_size;
1050 unsigned sx_max_export_smx_size;
1051 unsigned sq_num_cf_insts;
1052 unsigned sx_num_of_sets;
1053 unsigned sc_prim_fifo_size;
1054 unsigned sc_hiz_tile_fifo_size;
1055 unsigned sc_earlyz_tile_fifo_size;
1056 unsigned tiling_nbanks;
1057 unsigned tiling_npipes;
1058 unsigned tiling_group_size;
1059 unsigned tile_config;
1060 unsigned backend_map;
1061 struct r100_gpu_lockup lockup;
1062};
1063
1064struct cayman_asic {
1065 unsigned max_shader_engines;
1066 unsigned max_pipes_per_simd;
1067 unsigned max_tile_pipes;
1068 unsigned max_simds_per_se;
1069 unsigned max_backends_per_se;
1070 unsigned max_texture_channel_caches;
1071 unsigned max_gprs;
1072 unsigned max_threads;
1073 unsigned max_gs_threads;
1074 unsigned max_stack_entries;
1075 unsigned sx_num_of_sets;
1076 unsigned sx_max_export_size;
1077 unsigned sx_max_export_pos_size;
1078 unsigned sx_max_export_smx_size;
1079 unsigned max_hw_contexts;
1080 unsigned sq_num_cf_insts;
1081 unsigned sc_prim_fifo_size;
1082 unsigned sc_hiz_tile_fifo_size;
1083 unsigned sc_earlyz_tile_fifo_size;
1084
1085 unsigned num_shader_engines;
1086 unsigned num_shader_pipes_per_simd;
1087 unsigned num_tile_pipes;
1088 unsigned num_simds_per_se;
1089 unsigned num_backends_per_se;
1090 unsigned backend_disable_mask_per_asic;
1091 unsigned backend_map;
1092 unsigned num_texture_channel_caches;
1093 unsigned mem_max_burst_length_bytes;
1094 unsigned mem_row_size_in_kb;
1095 unsigned shader_engine_tile_size;
1096 unsigned num_gpus;
1097 unsigned multi_gpu_tile_size;
1098
1099 unsigned tile_config;
1100 struct r100_gpu_lockup lockup;
1101};
1102
1103union radeon_asic_config {
1104 struct r300_asic r300;
1105 struct r100_asic r100;
1106 struct r600_asic r600;
1107 struct rv770_asic rv770;
1108 struct evergreen_asic evergreen;
1109 struct cayman_asic cayman;
1110};
1111
1112/*
1113 * asic initizalization from radeon_asic.c
1114 */
1115void radeon_agp_disable(struct radeon_device *rdev);
1116int radeon_asic_init(struct radeon_device *rdev);
1117
1118
1119/*
1120 * IOCTL.
1121 */
1122int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1123 struct drm_file *filp);
1124int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1125 struct drm_file *filp);
1126int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1127 struct drm_file *file_priv);
1128int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1129 struct drm_file *file_priv);
1130int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1131 struct drm_file *file_priv);
1132int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1133 struct drm_file *file_priv);
1134int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1135 struct drm_file *filp);
1136int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1137 struct drm_file *filp);
1138int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1139 struct drm_file *filp);
1140int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1141 struct drm_file *filp);
1142int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1143int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1144 struct drm_file *filp);
1145int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1146 struct drm_file *filp);
1147
1148/* VRAM scratch page for HDP bug */
1149struct r700_vram_scratch {
1150 struct radeon_bo *robj;
1151 volatile uint32_t *ptr;
1152};
1153
1154/*
1155 * Core structure, functions and helpers.
1156 */
1157typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1158typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1159
1160struct radeon_device {
1161 struct device *dev;
1162 struct drm_device *ddev;
1163 struct pci_dev *pdev;
1164 /* ASIC */
1165 union radeon_asic_config config;
1166 enum radeon_family family;
1167 unsigned long flags;
1168 int usec_timeout;
1169 enum radeon_pll_errata pll_errata;
1170 int num_gb_pipes;
1171 int num_z_pipes;
1172 int disp_priority;
1173 /* BIOS */
1174 uint8_t *bios;
1175 bool is_atom_bios;
1176 uint16_t bios_header_start;
1177 struct radeon_bo *stollen_vga_memory;
1178 /* Register mmio */
1179 resource_size_t rmmio_base;
1180 resource_size_t rmmio_size;
1181 void __iomem *rmmio;
1182 radeon_rreg_t mc_rreg;
1183 radeon_wreg_t mc_wreg;
1184 radeon_rreg_t pll_rreg;
1185 radeon_wreg_t pll_wreg;
1186 uint32_t pcie_reg_mask;
1187 radeon_rreg_t pciep_rreg;
1188 radeon_wreg_t pciep_wreg;
1189 /* io port */
1190 void __iomem *rio_mem;
1191 resource_size_t rio_mem_size;
1192 struct radeon_clock clock;
1193 struct radeon_mc mc;
1194 struct radeon_gart gart;
1195 struct radeon_mode_info mode_info;
1196 struct radeon_scratch scratch;
1197 struct radeon_mman mman;
1198 struct radeon_fence_driver fence_drv;
1199 struct radeon_cp cp;
1200 /* cayman compute rings */
1201 struct radeon_cp cp1;
1202 struct radeon_cp cp2;
1203 struct radeon_ib_pool ib_pool;
1204 struct radeon_irq irq;
1205 struct radeon_asic *asic;
1206 struct radeon_gem gem;
1207 struct radeon_pm pm;
1208 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1209 struct mutex cs_mutex;
1210 struct radeon_wb wb;
1211 struct radeon_dummy_page dummy_page;
1212 bool gpu_lockup;
1213 bool shutdown;
1214 bool suspend;
1215 bool need_dma32;
1216 bool accel_working;
1217 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1218 const struct firmware *me_fw; /* all family ME firmware */
1219 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1220 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1221 const struct firmware *mc_fw; /* NI MC firmware */
1222 struct r600_blit r600_blit;
1223 struct r700_vram_scratch vram_scratch;
1224 int msi_enabled; /* msi enabled */
1225 struct r600_ih ih; /* r6/700 interrupt ring */
1226 struct work_struct hotplug_work;
1227 int num_crtc; /* number of crtcs */
1228 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1229 struct mutex vram_mutex;
1230
1231 /* audio stuff */
1232 bool audio_enabled;
1233 struct timer_list audio_timer;
1234 int audio_channels;
1235 int audio_rate;
1236 int audio_bits_per_sample;
1237 uint8_t audio_status_bits;
1238 uint8_t audio_category_code;
1239
1240 struct notifier_block acpi_nb;
1241 /* only one userspace can use Hyperz features or CMASK at a time */
1242 struct drm_file *hyperz_filp;
1243 struct drm_file *cmask_filp;
1244 /* i2c buses */
1245 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1246};
1247
1248int radeon_device_init(struct radeon_device *rdev,
1249 struct drm_device *ddev,
1250 struct pci_dev *pdev,
1251 uint32_t flags);
1252void radeon_device_fini(struct radeon_device *rdev);
1253int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1254
1255static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1256{
1257 if (reg < rdev->rmmio_size)
1258 return readl((rdev->rmmio) + reg);
1259 else {
1260 writel(reg, (rdev->rmmio) + RADEON_MM_INDEX);
1261 return readl((rdev->rmmio) + RADEON_MM_DATA);
1262 }
1263}
1264
1265static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1266{
1267 if (reg < rdev->rmmio_size)
1268 writel(v, (rdev->rmmio) + reg);
1269 else {
1270 writel(reg, (rdev->rmmio) + RADEON_MM_INDEX);
1271 writel(v, (rdev->rmmio) + RADEON_MM_DATA);
1272 }
1273}
1274
1275static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
1276{
1277 if (reg < rdev->rio_mem_size)
1278 return ioread32(rdev->rio_mem + reg);
1279 else {
1280 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1281 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
1282 }
1283}
1284
1285static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1286{
1287 if (reg < rdev->rio_mem_size)
1288 iowrite32(v, rdev->rio_mem + reg);
1289 else {
1290 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1291 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
1292 }
1293}
1294
1295/*
1296 * Cast helper
1297 */
1298#define to_radeon_fence(p) ((struct radeon_fence *)(p))
1299
1300/*
1301 * Registers read & write functions.
1302 */
1303#define RREG8(reg) readb((rdev->rmmio) + (reg))
1304#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1305#define RREG16(reg) readw((rdev->rmmio) + (reg))
1306#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1307#define RREG32(reg) r100_mm_rreg(rdev, (reg))
1308#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1309#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1310#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1311#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1312#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1313#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1314#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1315#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1316#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1317#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1318#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1319#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1320#define WREG32_P(reg, val, mask) \
1321 do { \
1322 uint32_t tmp_ = RREG32(reg); \
1323 tmp_ &= (mask); \
1324 tmp_ |= ((val) & ~(mask)); \
1325 WREG32(reg, tmp_); \
1326 } while (0)
1327#define WREG32_PLL_P(reg, val, mask) \
1328 do { \
1329 uint32_t tmp_ = RREG32_PLL(reg); \
1330 tmp_ &= (mask); \
1331 tmp_ |= ((val) & ~(mask)); \
1332 WREG32_PLL(reg, tmp_); \
1333 } while (0)
1334#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1335#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1336#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1337
1338/*
1339 * Indirect registers accessor
1340 */
1341static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1342{
1343 uint32_t r;
1344
1345 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1346 r = RREG32(RADEON_PCIE_DATA);
1347 return r;
1348}
1349
1350static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1351{
1352 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1353 WREG32(RADEON_PCIE_DATA, (v));
1354}
1355
1356void r100_pll_errata_after_index(struct radeon_device *rdev);
1357
1358
1359/*
1360 * ASICs helpers.
1361 */
1362#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1363 (rdev->pdev->device == 0x5969))
1364#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1365 (rdev->family == CHIP_RV200) || \
1366 (rdev->family == CHIP_RS100) || \
1367 (rdev->family == CHIP_RS200) || \
1368 (rdev->family == CHIP_RV250) || \
1369 (rdev->family == CHIP_RV280) || \
1370 (rdev->family == CHIP_RS300))
1371#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1372 (rdev->family == CHIP_RV350) || \
1373 (rdev->family == CHIP_R350) || \
1374 (rdev->family == CHIP_RV380) || \
1375 (rdev->family == CHIP_R420) || \
1376 (rdev->family == CHIP_R423) || \
1377 (rdev->family == CHIP_RV410) || \
1378 (rdev->family == CHIP_RS400) || \
1379 (rdev->family == CHIP_RS480))
1380#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1381 (rdev->ddev->pdev->device == 0x9443) || \
1382 (rdev->ddev->pdev->device == 0x944B) || \
1383 (rdev->ddev->pdev->device == 0x9506) || \
1384 (rdev->ddev->pdev->device == 0x9509) || \
1385 (rdev->ddev->pdev->device == 0x950F) || \
1386 (rdev->ddev->pdev->device == 0x689C) || \
1387 (rdev->ddev->pdev->device == 0x689D))
1388#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1389#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1390 (rdev->family == CHIP_RS690) || \
1391 (rdev->family == CHIP_RS740) || \
1392 (rdev->family >= CHIP_R600))
1393#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1394#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1395#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1396#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1397 (rdev->flags & RADEON_IS_IGP))
1398#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1399
1400/*
1401 * BIOS helpers.
1402 */
1403#define RBIOS8(i) (rdev->bios[i])
1404#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1405#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1406
1407int radeon_combios_init(struct radeon_device *rdev);
1408void radeon_combios_fini(struct radeon_device *rdev);
1409int radeon_atombios_init(struct radeon_device *rdev);
1410void radeon_atombios_fini(struct radeon_device *rdev);
1411
1412
1413/*
1414 * RING helpers.
1415 */
1416static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1417{
1418#if DRM_DEBUG_CODE
1419 if (rdev->cp.count_dw <= 0) {
1420 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1421 }
1422#endif
1423 rdev->cp.ring[rdev->cp.wptr++] = v;
1424 rdev->cp.wptr &= rdev->cp.ptr_mask;
1425 rdev->cp.count_dw--;
1426 rdev->cp.ring_free_dw--;
1427}
1428
1429
1430/*
1431 * ASICs macro.
1432 */
1433#define radeon_init(rdev) (rdev)->asic->init((rdev))
1434#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1435#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1436#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1437#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1438#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1439#define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
1440#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1441#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1442#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1443#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1444#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1445#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1446#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1447#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1448#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1449#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1450#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1451#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1452#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1453#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1454#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1455#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1456#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1457#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1458#define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1459#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1460#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1461#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1462#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1463#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1464#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1465#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1466#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1467#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1468#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1469#define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1470#define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1471#define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1472#define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1473#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1474#define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
1475#define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
1476#define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
1477
1478/* Common functions */
1479/* AGP */
1480extern int radeon_gpu_reset(struct radeon_device *rdev);
1481extern void radeon_agp_disable(struct radeon_device *rdev);
1482extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1483extern void radeon_gart_restore(struct radeon_device *rdev);
1484extern int radeon_modeset_init(struct radeon_device *rdev);
1485extern void radeon_modeset_fini(struct radeon_device *rdev);
1486extern bool radeon_card_posted(struct radeon_device *rdev);
1487extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1488extern void radeon_update_display_priority(struct radeon_device *rdev);
1489extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1490extern void radeon_scratch_init(struct radeon_device *rdev);
1491extern void radeon_wb_fini(struct radeon_device *rdev);
1492extern int radeon_wb_init(struct radeon_device *rdev);
1493extern void radeon_wb_disable(struct radeon_device *rdev);
1494extern void radeon_surface_init(struct radeon_device *rdev);
1495extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1496extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1497extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1498extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1499extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1500extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1501extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1502extern int radeon_resume_kms(struct drm_device *dev);
1503extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1504extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1505
1506/*
1507 * r600 functions used by radeon_encoder.c
1508 */
1509extern void r600_hdmi_enable(struct drm_encoder *encoder);
1510extern void r600_hdmi_disable(struct drm_encoder *encoder);
1511extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1512
1513extern int ni_init_microcode(struct radeon_device *rdev);
1514extern int ni_mc_load_microcode(struct radeon_device *rdev);
1515
1516/* radeon_acpi.c */
1517#if defined(CONFIG_ACPI)
1518extern int radeon_acpi_init(struct radeon_device *rdev);
1519#else
1520static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1521#endif
1522
1523#include "radeon_object.h"
1524
1525#endif
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63#include <linux/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67#include <linux/interval_tree.h>
68#include <linux/hashtable.h>
69#include <linux/fence.h>
70
71#include <ttm/ttm_bo_api.h>
72#include <ttm/ttm_bo_driver.h>
73#include <ttm/ttm_placement.h>
74#include <ttm/ttm_module.h>
75#include <ttm/ttm_execbuf_util.h>
76
77#include <drm/drm_gem.h>
78
79#include "radeon_family.h"
80#include "radeon_mode.h"
81#include "radeon_reg.h"
82
83/*
84 * Modules parameters.
85 */
86extern int radeon_no_wb;
87extern int radeon_modeset;
88extern int radeon_dynclks;
89extern int radeon_r4xx_atom;
90extern int radeon_agpmode;
91extern int radeon_vram_limit;
92extern int radeon_gart_size;
93extern int radeon_benchmarking;
94extern int radeon_testing;
95extern int radeon_connector_table;
96extern int radeon_tv;
97extern int radeon_audio;
98extern int radeon_disp_priority;
99extern int radeon_hw_i2c;
100extern int radeon_pcie_gen2;
101extern int radeon_msi;
102extern int radeon_lockup_timeout;
103extern int radeon_fastfb;
104extern int radeon_dpm;
105extern int radeon_aspm;
106extern int radeon_runtime_pm;
107extern int radeon_hard_reset;
108extern int radeon_vm_size;
109extern int radeon_vm_block_size;
110extern int radeon_deep_color;
111extern int radeon_use_pflipirq;
112extern int radeon_bapm;
113extern int radeon_backlight;
114extern int radeon_auxch;
115extern int radeon_mst;
116
117/*
118 * Copy from radeon_drv.h so we don't have to include both and have conflicting
119 * symbol;
120 */
121#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
122#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
123#define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */
124/* RADEON_IB_POOL_SIZE must be a power of 2 */
125#define RADEON_IB_POOL_SIZE 16
126#define RADEON_DEBUGFS_MAX_COMPONENTS 32
127#define RADEONFB_CONN_LIMIT 4
128#define RADEON_BIOS_NUM_SCRATCH 8
129
130/* internal ring indices */
131/* r1xx+ has gfx CP ring */
132#define RADEON_RING_TYPE_GFX_INDEX 0
133
134/* cayman has 2 compute CP rings */
135#define CAYMAN_RING_TYPE_CP1_INDEX 1
136#define CAYMAN_RING_TYPE_CP2_INDEX 2
137
138/* R600+ has an async dma ring */
139#define R600_RING_TYPE_DMA_INDEX 3
140/* cayman add a second async dma ring */
141#define CAYMAN_RING_TYPE_DMA1_INDEX 4
142
143/* R600+ */
144#define R600_RING_TYPE_UVD_INDEX 5
145
146/* TN+ */
147#define TN_RING_TYPE_VCE1_INDEX 6
148#define TN_RING_TYPE_VCE2_INDEX 7
149
150/* max number of rings */
151#define RADEON_NUM_RINGS 8
152
153/* number of hw syncs before falling back on blocking */
154#define RADEON_NUM_SYNCS 4
155
156/* hardcode those limit for now */
157#define RADEON_VA_IB_OFFSET (1 << 20)
158#define RADEON_VA_RESERVED_SIZE (8 << 20)
159#define RADEON_IB_VM_MAX_SIZE (64 << 10)
160
161/* hard reset data */
162#define RADEON_ASIC_RESET_DATA 0x39d5e86b
163
164/* reset flags */
165#define RADEON_RESET_GFX (1 << 0)
166#define RADEON_RESET_COMPUTE (1 << 1)
167#define RADEON_RESET_DMA (1 << 2)
168#define RADEON_RESET_CP (1 << 3)
169#define RADEON_RESET_GRBM (1 << 4)
170#define RADEON_RESET_DMA1 (1 << 5)
171#define RADEON_RESET_RLC (1 << 6)
172#define RADEON_RESET_SEM (1 << 7)
173#define RADEON_RESET_IH (1 << 8)
174#define RADEON_RESET_VMC (1 << 9)
175#define RADEON_RESET_MC (1 << 10)
176#define RADEON_RESET_DISPLAY (1 << 11)
177
178/* CG block flags */
179#define RADEON_CG_BLOCK_GFX (1 << 0)
180#define RADEON_CG_BLOCK_MC (1 << 1)
181#define RADEON_CG_BLOCK_SDMA (1 << 2)
182#define RADEON_CG_BLOCK_UVD (1 << 3)
183#define RADEON_CG_BLOCK_VCE (1 << 4)
184#define RADEON_CG_BLOCK_HDP (1 << 5)
185#define RADEON_CG_BLOCK_BIF (1 << 6)
186
187/* CG flags */
188#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
189#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
190#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
191#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
192#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
193#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
194#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
195#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
196#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
197#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
198#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
199#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
200#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
201#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
202#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
203#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
204#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
205
206/* PG flags */
207#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
208#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
209#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
210#define RADEON_PG_SUPPORT_UVD (1 << 3)
211#define RADEON_PG_SUPPORT_VCE (1 << 4)
212#define RADEON_PG_SUPPORT_CP (1 << 5)
213#define RADEON_PG_SUPPORT_GDS (1 << 6)
214#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
215#define RADEON_PG_SUPPORT_SDMA (1 << 8)
216#define RADEON_PG_SUPPORT_ACP (1 << 9)
217#define RADEON_PG_SUPPORT_SAMU (1 << 10)
218
219/* max cursor sizes (in pixels) */
220#define CURSOR_WIDTH 64
221#define CURSOR_HEIGHT 64
222
223#define CIK_CURSOR_WIDTH 128
224#define CIK_CURSOR_HEIGHT 128
225
226/*
227 * Errata workarounds.
228 */
229enum radeon_pll_errata {
230 CHIP_ERRATA_R300_CG = 0x00000001,
231 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
232 CHIP_ERRATA_PLL_DELAY = 0x00000004
233};
234
235
236struct radeon_device;
237
238
239/*
240 * BIOS.
241 */
242bool radeon_get_bios(struct radeon_device *rdev);
243
244/*
245 * Dummy page
246 */
247struct radeon_dummy_page {
248 uint64_t entry;
249 struct page *page;
250 dma_addr_t addr;
251};
252int radeon_dummy_page_init(struct radeon_device *rdev);
253void radeon_dummy_page_fini(struct radeon_device *rdev);
254
255
256/*
257 * Clocks
258 */
259struct radeon_clock {
260 struct radeon_pll p1pll;
261 struct radeon_pll p2pll;
262 struct radeon_pll dcpll;
263 struct radeon_pll spll;
264 struct radeon_pll mpll;
265 /* 10 Khz units */
266 uint32_t default_mclk;
267 uint32_t default_sclk;
268 uint32_t default_dispclk;
269 uint32_t current_dispclk;
270 uint32_t dp_extclk;
271 uint32_t max_pixel_clock;
272 uint32_t vco_freq;
273};
274
275/*
276 * Power management
277 */
278int radeon_pm_init(struct radeon_device *rdev);
279int radeon_pm_late_init(struct radeon_device *rdev);
280void radeon_pm_fini(struct radeon_device *rdev);
281void radeon_pm_compute_clocks(struct radeon_device *rdev);
282void radeon_pm_suspend(struct radeon_device *rdev);
283void radeon_pm_resume(struct radeon_device *rdev);
284void radeon_combios_get_power_modes(struct radeon_device *rdev);
285void radeon_atombios_get_power_modes(struct radeon_device *rdev);
286int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
287 u8 clock_type,
288 u32 clock,
289 bool strobe_mode,
290 struct atom_clock_dividers *dividers);
291int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
292 u32 clock,
293 bool strobe_mode,
294 struct atom_mpll_param *mpll_param);
295void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
296int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
297 u16 voltage_level, u8 voltage_type,
298 u32 *gpio_value, u32 *gpio_mask);
299void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
300 u32 eng_clock, u32 mem_clock);
301int radeon_atom_get_voltage_step(struct radeon_device *rdev,
302 u8 voltage_type, u16 *voltage_step);
303int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
304 u16 voltage_id, u16 *voltage);
305int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
306 u16 *voltage,
307 u16 leakage_idx);
308int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
309 u16 *leakage_id);
310int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
311 u16 *vddc, u16 *vddci,
312 u16 virtual_voltage_id,
313 u16 vbios_voltage_id);
314int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
315 u16 virtual_voltage_id,
316 u16 *voltage);
317int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
318 u8 voltage_type,
319 u16 nominal_voltage,
320 u16 *true_voltage);
321int radeon_atom_get_min_voltage(struct radeon_device *rdev,
322 u8 voltage_type, u16 *min_voltage);
323int radeon_atom_get_max_voltage(struct radeon_device *rdev,
324 u8 voltage_type, u16 *max_voltage);
325int radeon_atom_get_voltage_table(struct radeon_device *rdev,
326 u8 voltage_type, u8 voltage_mode,
327 struct atom_voltage_table *voltage_table);
328bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
329 u8 voltage_type, u8 voltage_mode);
330int radeon_atom_get_svi2_info(struct radeon_device *rdev,
331 u8 voltage_type,
332 u8 *svd_gpio_id, u8 *svc_gpio_id);
333void radeon_atom_update_memory_dll(struct radeon_device *rdev,
334 u32 mem_clock);
335void radeon_atom_set_ac_timing(struct radeon_device *rdev,
336 u32 mem_clock);
337int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
338 u8 module_index,
339 struct atom_mc_reg_table *reg_table);
340int radeon_atom_get_memory_info(struct radeon_device *rdev,
341 u8 module_index, struct atom_memory_info *mem_info);
342int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
343 bool gddr5, u8 module_index,
344 struct atom_memory_clock_range_table *mclk_range_table);
345int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
346 u16 voltage_id, u16 *voltage);
347void rs690_pm_info(struct radeon_device *rdev);
348extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
349 unsigned *bankh, unsigned *mtaspect,
350 unsigned *tile_split);
351
352/*
353 * Fences.
354 */
355struct radeon_fence_driver {
356 struct radeon_device *rdev;
357 uint32_t scratch_reg;
358 uint64_t gpu_addr;
359 volatile uint32_t *cpu_addr;
360 /* sync_seq is protected by ring emission lock */
361 uint64_t sync_seq[RADEON_NUM_RINGS];
362 atomic64_t last_seq;
363 bool initialized, delayed_irq;
364 struct delayed_work lockup_work;
365};
366
367struct radeon_fence {
368 struct fence base;
369
370 struct radeon_device *rdev;
371 uint64_t seq;
372 /* RB, DMA, etc. */
373 unsigned ring;
374 bool is_vm_update;
375
376 wait_queue_t fence_wake;
377};
378
379int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
380int radeon_fence_driver_init(struct radeon_device *rdev);
381void radeon_fence_driver_fini(struct radeon_device *rdev);
382void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
383int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
384void radeon_fence_process(struct radeon_device *rdev, int ring);
385bool radeon_fence_signaled(struct radeon_fence *fence);
386long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
387int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
388int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
389int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
390int radeon_fence_wait_any(struct radeon_device *rdev,
391 struct radeon_fence **fences,
392 bool intr);
393struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
394void radeon_fence_unref(struct radeon_fence **fence);
395unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
396bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
397void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
398static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
399 struct radeon_fence *b)
400{
401 if (!a) {
402 return b;
403 }
404
405 if (!b) {
406 return a;
407 }
408
409 BUG_ON(a->ring != b->ring);
410
411 if (a->seq > b->seq) {
412 return a;
413 } else {
414 return b;
415 }
416}
417
418static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
419 struct radeon_fence *b)
420{
421 if (!a) {
422 return false;
423 }
424
425 if (!b) {
426 return true;
427 }
428
429 BUG_ON(a->ring != b->ring);
430
431 return a->seq < b->seq;
432}
433
434/*
435 * Tiling registers
436 */
437struct radeon_surface_reg {
438 struct radeon_bo *bo;
439};
440
441#define RADEON_GEM_MAX_SURFACES 8
442
443/*
444 * TTM.
445 */
446struct radeon_mman {
447 struct ttm_bo_global_ref bo_global_ref;
448 struct drm_global_reference mem_global_ref;
449 struct ttm_bo_device bdev;
450 bool mem_global_referenced;
451 bool initialized;
452
453#if defined(CONFIG_DEBUG_FS)
454 struct dentry *vram;
455 struct dentry *gtt;
456#endif
457};
458
459struct radeon_bo_list {
460 struct radeon_bo *robj;
461 struct ttm_validate_buffer tv;
462 uint64_t gpu_offset;
463 unsigned prefered_domains;
464 unsigned allowed_domains;
465 uint32_t tiling_flags;
466};
467
468/* bo virtual address in a specific vm */
469struct radeon_bo_va {
470 /* protected by bo being reserved */
471 struct list_head bo_list;
472 uint32_t flags;
473 struct radeon_fence *last_pt_update;
474 unsigned ref_count;
475
476 /* protected by vm mutex */
477 struct interval_tree_node it;
478 struct list_head vm_status;
479
480 /* constant after initialization */
481 struct radeon_vm *vm;
482 struct radeon_bo *bo;
483};
484
485struct radeon_bo {
486 /* Protected by gem.mutex */
487 struct list_head list;
488 /* Protected by tbo.reserved */
489 u32 initial_domain;
490 struct ttm_place placements[4];
491 struct ttm_placement placement;
492 struct ttm_buffer_object tbo;
493 struct ttm_bo_kmap_obj kmap;
494 u32 flags;
495 unsigned pin_count;
496 void *kptr;
497 u32 tiling_flags;
498 u32 pitch;
499 int surface_reg;
500 /* list of all virtual address to which this bo
501 * is associated to
502 */
503 struct list_head va;
504 /* Constant after initialization */
505 struct radeon_device *rdev;
506 struct drm_gem_object gem_base;
507
508 struct ttm_bo_kmap_obj dma_buf_vmap;
509 pid_t pid;
510
511 struct radeon_mn *mn;
512 struct list_head mn_list;
513};
514#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
515
516int radeon_gem_debugfs_init(struct radeon_device *rdev);
517
518/* sub-allocation manager, it has to be protected by another lock.
519 * By conception this is an helper for other part of the driver
520 * like the indirect buffer or semaphore, which both have their
521 * locking.
522 *
523 * Principe is simple, we keep a list of sub allocation in offset
524 * order (first entry has offset == 0, last entry has the highest
525 * offset).
526 *
527 * When allocating new object we first check if there is room at
528 * the end total_size - (last_object_offset + last_object_size) >=
529 * alloc_size. If so we allocate new object there.
530 *
531 * When there is not enough room at the end, we start waiting for
532 * each sub object until we reach object_offset+object_size >=
533 * alloc_size, this object then become the sub object we return.
534 *
535 * Alignment can't be bigger than page size.
536 *
537 * Hole are not considered for allocation to keep things simple.
538 * Assumption is that there won't be hole (all object on same
539 * alignment).
540 */
541struct radeon_sa_manager {
542 wait_queue_head_t wq;
543 struct radeon_bo *bo;
544 struct list_head *hole;
545 struct list_head flist[RADEON_NUM_RINGS];
546 struct list_head olist;
547 unsigned size;
548 uint64_t gpu_addr;
549 void *cpu_ptr;
550 uint32_t domain;
551 uint32_t align;
552};
553
554struct radeon_sa_bo;
555
556/* sub-allocation buffer */
557struct radeon_sa_bo {
558 struct list_head olist;
559 struct list_head flist;
560 struct radeon_sa_manager *manager;
561 unsigned soffset;
562 unsigned eoffset;
563 struct radeon_fence *fence;
564};
565
566/*
567 * GEM objects.
568 */
569struct radeon_gem {
570 struct mutex mutex;
571 struct list_head objects;
572};
573
574int radeon_gem_init(struct radeon_device *rdev);
575void radeon_gem_fini(struct radeon_device *rdev);
576int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
577 int alignment, int initial_domain,
578 u32 flags, bool kernel,
579 struct drm_gem_object **obj);
580
581int radeon_mode_dumb_create(struct drm_file *file_priv,
582 struct drm_device *dev,
583 struct drm_mode_create_dumb *args);
584int radeon_mode_dumb_mmap(struct drm_file *filp,
585 struct drm_device *dev,
586 uint32_t handle, uint64_t *offset_p);
587
588/*
589 * Semaphores.
590 */
591struct radeon_semaphore {
592 struct radeon_sa_bo *sa_bo;
593 signed waiters;
594 uint64_t gpu_addr;
595};
596
597int radeon_semaphore_create(struct radeon_device *rdev,
598 struct radeon_semaphore **semaphore);
599bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
600 struct radeon_semaphore *semaphore);
601bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
602 struct radeon_semaphore *semaphore);
603void radeon_semaphore_free(struct radeon_device *rdev,
604 struct radeon_semaphore **semaphore,
605 struct radeon_fence *fence);
606
607/*
608 * Synchronization
609 */
610struct radeon_sync {
611 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
612 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
613 struct radeon_fence *last_vm_update;
614};
615
616void radeon_sync_create(struct radeon_sync *sync);
617void radeon_sync_fence(struct radeon_sync *sync,
618 struct radeon_fence *fence);
619int radeon_sync_resv(struct radeon_device *rdev,
620 struct radeon_sync *sync,
621 struct reservation_object *resv,
622 bool shared);
623int radeon_sync_rings(struct radeon_device *rdev,
624 struct radeon_sync *sync,
625 int waiting_ring);
626void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
627 struct radeon_fence *fence);
628
629/*
630 * GART structures, functions & helpers
631 */
632struct radeon_mc;
633
634#define RADEON_GPU_PAGE_SIZE 4096
635#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
636#define RADEON_GPU_PAGE_SHIFT 12
637#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
638
639#define RADEON_GART_PAGE_DUMMY 0
640#define RADEON_GART_PAGE_VALID (1 << 0)
641#define RADEON_GART_PAGE_READ (1 << 1)
642#define RADEON_GART_PAGE_WRITE (1 << 2)
643#define RADEON_GART_PAGE_SNOOP (1 << 3)
644
645struct radeon_gart {
646 dma_addr_t table_addr;
647 struct radeon_bo *robj;
648 void *ptr;
649 unsigned num_gpu_pages;
650 unsigned num_cpu_pages;
651 unsigned table_size;
652 struct page **pages;
653 uint64_t *pages_entry;
654 bool ready;
655};
656
657int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
658void radeon_gart_table_ram_free(struct radeon_device *rdev);
659int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
660void radeon_gart_table_vram_free(struct radeon_device *rdev);
661int radeon_gart_table_vram_pin(struct radeon_device *rdev);
662void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
663int radeon_gart_init(struct radeon_device *rdev);
664void radeon_gart_fini(struct radeon_device *rdev);
665void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
666 int pages);
667int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
668 int pages, struct page **pagelist,
669 dma_addr_t *dma_addr, uint32_t flags);
670
671
672/*
673 * GPU MC structures, functions & helpers
674 */
675struct radeon_mc {
676 resource_size_t aper_size;
677 resource_size_t aper_base;
678 resource_size_t agp_base;
679 /* for some chips with <= 32MB we need to lie
680 * about vram size near mc fb location */
681 u64 mc_vram_size;
682 u64 visible_vram_size;
683 u64 gtt_size;
684 u64 gtt_start;
685 u64 gtt_end;
686 u64 vram_start;
687 u64 vram_end;
688 unsigned vram_width;
689 u64 real_vram_size;
690 int vram_mtrr;
691 bool vram_is_ddr;
692 bool igp_sideport_enabled;
693 u64 gtt_base_align;
694 u64 mc_mask;
695};
696
697bool radeon_combios_sideport_present(struct radeon_device *rdev);
698bool radeon_atombios_sideport_present(struct radeon_device *rdev);
699
700/*
701 * GPU scratch registers structures, functions & helpers
702 */
703struct radeon_scratch {
704 unsigned num_reg;
705 uint32_t reg_base;
706 bool free[32];
707 uint32_t reg[32];
708};
709
710int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
711void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
712
713/*
714 * GPU doorbell structures, functions & helpers
715 */
716#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
717
718struct radeon_doorbell {
719 /* doorbell mmio */
720 resource_size_t base;
721 resource_size_t size;
722 u32 __iomem *ptr;
723 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
724 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
725};
726
727int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
728void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
729void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
730 phys_addr_t *aperture_base,
731 size_t *aperture_size,
732 size_t *start_offset);
733
734/*
735 * IRQS.
736 */
737
738struct radeon_flip_work {
739 struct work_struct flip_work;
740 struct work_struct unpin_work;
741 struct radeon_device *rdev;
742 int crtc_id;
743 uint64_t base;
744 struct drm_pending_vblank_event *event;
745 struct radeon_bo *old_rbo;
746 struct fence *fence;
747};
748
749struct r500_irq_stat_regs {
750 u32 disp_int;
751 u32 hdmi0_status;
752};
753
754struct r600_irq_stat_regs {
755 u32 disp_int;
756 u32 disp_int_cont;
757 u32 disp_int_cont2;
758 u32 d1grph_int;
759 u32 d2grph_int;
760 u32 hdmi0_status;
761 u32 hdmi1_status;
762};
763
764struct evergreen_irq_stat_regs {
765 u32 disp_int;
766 u32 disp_int_cont;
767 u32 disp_int_cont2;
768 u32 disp_int_cont3;
769 u32 disp_int_cont4;
770 u32 disp_int_cont5;
771 u32 d1grph_int;
772 u32 d2grph_int;
773 u32 d3grph_int;
774 u32 d4grph_int;
775 u32 d5grph_int;
776 u32 d6grph_int;
777 u32 afmt_status1;
778 u32 afmt_status2;
779 u32 afmt_status3;
780 u32 afmt_status4;
781 u32 afmt_status5;
782 u32 afmt_status6;
783};
784
785struct cik_irq_stat_regs {
786 u32 disp_int;
787 u32 disp_int_cont;
788 u32 disp_int_cont2;
789 u32 disp_int_cont3;
790 u32 disp_int_cont4;
791 u32 disp_int_cont5;
792 u32 disp_int_cont6;
793 u32 d1grph_int;
794 u32 d2grph_int;
795 u32 d3grph_int;
796 u32 d4grph_int;
797 u32 d5grph_int;
798 u32 d6grph_int;
799};
800
801union radeon_irq_stat_regs {
802 struct r500_irq_stat_regs r500;
803 struct r600_irq_stat_regs r600;
804 struct evergreen_irq_stat_regs evergreen;
805 struct cik_irq_stat_regs cik;
806};
807
808struct radeon_irq {
809 bool installed;
810 spinlock_t lock;
811 atomic_t ring_int[RADEON_NUM_RINGS];
812 bool crtc_vblank_int[RADEON_MAX_CRTCS];
813 atomic_t pflip[RADEON_MAX_CRTCS];
814 wait_queue_head_t vblank_queue;
815 bool hpd[RADEON_MAX_HPD_PINS];
816 bool afmt[RADEON_MAX_AFMT_BLOCKS];
817 union radeon_irq_stat_regs stat_regs;
818 bool dpm_thermal;
819};
820
821int radeon_irq_kms_init(struct radeon_device *rdev);
822void radeon_irq_kms_fini(struct radeon_device *rdev);
823void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
824bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
825void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
826void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
827void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
828void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
829void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
830void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
831void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
832
833/*
834 * CP & rings.
835 */
836
837struct radeon_ib {
838 struct radeon_sa_bo *sa_bo;
839 uint32_t length_dw;
840 uint64_t gpu_addr;
841 uint32_t *ptr;
842 int ring;
843 struct radeon_fence *fence;
844 struct radeon_vm *vm;
845 bool is_const_ib;
846 struct radeon_sync sync;
847};
848
849struct radeon_ring {
850 struct radeon_bo *ring_obj;
851 volatile uint32_t *ring;
852 unsigned rptr_offs;
853 unsigned rptr_save_reg;
854 u64 next_rptr_gpu_addr;
855 volatile u32 *next_rptr_cpu_addr;
856 unsigned wptr;
857 unsigned wptr_old;
858 unsigned ring_size;
859 unsigned ring_free_dw;
860 int count_dw;
861 atomic_t last_rptr;
862 atomic64_t last_activity;
863 uint64_t gpu_addr;
864 uint32_t align_mask;
865 uint32_t ptr_mask;
866 bool ready;
867 u32 nop;
868 u32 idx;
869 u64 last_semaphore_signal_addr;
870 u64 last_semaphore_wait_addr;
871 /* for CIK queues */
872 u32 me;
873 u32 pipe;
874 u32 queue;
875 struct radeon_bo *mqd_obj;
876 u32 doorbell_index;
877 unsigned wptr_offs;
878};
879
880struct radeon_mec {
881 struct radeon_bo *hpd_eop_obj;
882 u64 hpd_eop_gpu_addr;
883 u32 num_pipe;
884 u32 num_mec;
885 u32 num_queue;
886};
887
888/*
889 * VM
890 */
891
892/* maximum number of VMIDs */
893#define RADEON_NUM_VM 16
894
895/* number of entries in page table */
896#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
897
898/* PTBs (Page Table Blocks) need to be aligned to 32K */
899#define RADEON_VM_PTB_ALIGN_SIZE 32768
900#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
901#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
902
903#define R600_PTE_VALID (1 << 0)
904#define R600_PTE_SYSTEM (1 << 1)
905#define R600_PTE_SNOOPED (1 << 2)
906#define R600_PTE_READABLE (1 << 5)
907#define R600_PTE_WRITEABLE (1 << 6)
908
909/* PTE (Page Table Entry) fragment field for different page sizes */
910#define R600_PTE_FRAG_4KB (0 << 7)
911#define R600_PTE_FRAG_64KB (4 << 7)
912#define R600_PTE_FRAG_256KB (6 << 7)
913
914/* flags needed to be set so we can copy directly from the GART table */
915#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
916 R600_PTE_SYSTEM | R600_PTE_VALID )
917
918struct radeon_vm_pt {
919 struct radeon_bo *bo;
920 uint64_t addr;
921};
922
923struct radeon_vm_id {
924 unsigned id;
925 uint64_t pd_gpu_addr;
926 /* last flushed PD/PT update */
927 struct radeon_fence *flushed_updates;
928 /* last use of vmid */
929 struct radeon_fence *last_id_use;
930};
931
932struct radeon_vm {
933 struct mutex mutex;
934
935 struct rb_root va;
936
937 /* protecting invalidated and freed */
938 spinlock_t status_lock;
939
940 /* BOs moved, but not yet updated in the PT */
941 struct list_head invalidated;
942
943 /* BOs freed, but not yet updated in the PT */
944 struct list_head freed;
945
946 /* BOs cleared in the PT */
947 struct list_head cleared;
948
949 /* contains the page directory */
950 struct radeon_bo *page_directory;
951 unsigned max_pde_used;
952
953 /* array of page tables, one for each page directory entry */
954 struct radeon_vm_pt *page_tables;
955
956 struct radeon_bo_va *ib_bo_va;
957
958 /* for id and flush management per ring */
959 struct radeon_vm_id ids[RADEON_NUM_RINGS];
960};
961
962struct radeon_vm_manager {
963 struct radeon_fence *active[RADEON_NUM_VM];
964 uint32_t max_pfn;
965 /* number of VMIDs */
966 unsigned nvm;
967 /* vram base address for page table entry */
968 u64 vram_base_offset;
969 /* is vm enabled? */
970 bool enabled;
971 /* for hw to save the PD addr on suspend/resume */
972 uint32_t saved_table_addr[RADEON_NUM_VM];
973};
974
975/*
976 * file private structure
977 */
978struct radeon_fpriv {
979 struct radeon_vm vm;
980};
981
982/*
983 * R6xx+ IH ring
984 */
985struct r600_ih {
986 struct radeon_bo *ring_obj;
987 volatile uint32_t *ring;
988 unsigned rptr;
989 unsigned ring_size;
990 uint64_t gpu_addr;
991 uint32_t ptr_mask;
992 atomic_t lock;
993 bool enabled;
994};
995
996/*
997 * RLC stuff
998 */
999#include "clearstate_defs.h"
1000
1001struct radeon_rlc {
1002 /* for power gating */
1003 struct radeon_bo *save_restore_obj;
1004 uint64_t save_restore_gpu_addr;
1005 volatile uint32_t *sr_ptr;
1006 const u32 *reg_list;
1007 u32 reg_list_size;
1008 /* for clear state */
1009 struct radeon_bo *clear_state_obj;
1010 uint64_t clear_state_gpu_addr;
1011 volatile uint32_t *cs_ptr;
1012 const struct cs_section_def *cs_data;
1013 u32 clear_state_size;
1014 /* for cp tables */
1015 struct radeon_bo *cp_table_obj;
1016 uint64_t cp_table_gpu_addr;
1017 volatile uint32_t *cp_table_ptr;
1018 u32 cp_table_size;
1019};
1020
1021int radeon_ib_get(struct radeon_device *rdev, int ring,
1022 struct radeon_ib *ib, struct radeon_vm *vm,
1023 unsigned size);
1024void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
1025int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1026 struct radeon_ib *const_ib, bool hdp_flush);
1027int radeon_ib_pool_init(struct radeon_device *rdev);
1028void radeon_ib_pool_fini(struct radeon_device *rdev);
1029int radeon_ib_ring_tests(struct radeon_device *rdev);
1030/* Ring access between begin & end cannot sleep */
1031bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1032 struct radeon_ring *ring);
1033void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1034int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1035int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1036void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1037 bool hdp_flush);
1038void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1039 bool hdp_flush);
1040void radeon_ring_undo(struct radeon_ring *ring);
1041void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1042int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1043void radeon_ring_lockup_update(struct radeon_device *rdev,
1044 struct radeon_ring *ring);
1045bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1046unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1047 uint32_t **data);
1048int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1049 unsigned size, uint32_t *data);
1050int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1051 unsigned rptr_offs, u32 nop);
1052void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1053
1054
1055/* r600 async dma */
1056void r600_dma_stop(struct radeon_device *rdev);
1057int r600_dma_resume(struct radeon_device *rdev);
1058void r600_dma_fini(struct radeon_device *rdev);
1059
1060void cayman_dma_stop(struct radeon_device *rdev);
1061int cayman_dma_resume(struct radeon_device *rdev);
1062void cayman_dma_fini(struct radeon_device *rdev);
1063
1064/*
1065 * CS.
1066 */
1067struct radeon_cs_chunk {
1068 uint32_t length_dw;
1069 uint32_t *kdata;
1070 void __user *user_ptr;
1071};
1072
1073struct radeon_cs_parser {
1074 struct device *dev;
1075 struct radeon_device *rdev;
1076 struct drm_file *filp;
1077 /* chunks */
1078 unsigned nchunks;
1079 struct radeon_cs_chunk *chunks;
1080 uint64_t *chunks_array;
1081 /* IB */
1082 unsigned idx;
1083 /* relocations */
1084 unsigned nrelocs;
1085 struct radeon_bo_list *relocs;
1086 struct radeon_bo_list *vm_bos;
1087 struct list_head validated;
1088 unsigned dma_reloc_idx;
1089 /* indices of various chunks */
1090 struct radeon_cs_chunk *chunk_ib;
1091 struct radeon_cs_chunk *chunk_relocs;
1092 struct radeon_cs_chunk *chunk_flags;
1093 struct radeon_cs_chunk *chunk_const_ib;
1094 struct radeon_ib ib;
1095 struct radeon_ib const_ib;
1096 void *track;
1097 unsigned family;
1098 int parser_error;
1099 u32 cs_flags;
1100 u32 ring;
1101 s32 priority;
1102 struct ww_acquire_ctx ticket;
1103};
1104
1105static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1106{
1107 struct radeon_cs_chunk *ibc = p->chunk_ib;
1108
1109 if (ibc->kdata)
1110 return ibc->kdata[idx];
1111 return p->ib.ptr[idx];
1112}
1113
1114
1115struct radeon_cs_packet {
1116 unsigned idx;
1117 unsigned type;
1118 unsigned reg;
1119 unsigned opcode;
1120 int count;
1121 unsigned one_reg_wr;
1122};
1123
1124typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1125 struct radeon_cs_packet *pkt,
1126 unsigned idx, unsigned reg);
1127typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1128 struct radeon_cs_packet *pkt);
1129
1130
1131/*
1132 * AGP
1133 */
1134int radeon_agp_init(struct radeon_device *rdev);
1135void radeon_agp_resume(struct radeon_device *rdev);
1136void radeon_agp_suspend(struct radeon_device *rdev);
1137void radeon_agp_fini(struct radeon_device *rdev);
1138
1139
1140/*
1141 * Writeback
1142 */
1143struct radeon_wb {
1144 struct radeon_bo *wb_obj;
1145 volatile uint32_t *wb;
1146 uint64_t gpu_addr;
1147 bool enabled;
1148 bool use_event;
1149};
1150
1151#define RADEON_WB_SCRATCH_OFFSET 0
1152#define RADEON_WB_RING0_NEXT_RPTR 256
1153#define RADEON_WB_CP_RPTR_OFFSET 1024
1154#define RADEON_WB_CP1_RPTR_OFFSET 1280
1155#define RADEON_WB_CP2_RPTR_OFFSET 1536
1156#define R600_WB_DMA_RPTR_OFFSET 1792
1157#define R600_WB_IH_WPTR_OFFSET 2048
1158#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1159#define R600_WB_EVENT_OFFSET 3072
1160#define CIK_WB_CP1_WPTR_OFFSET 3328
1161#define CIK_WB_CP2_WPTR_OFFSET 3584
1162#define R600_WB_DMA_RING_TEST_OFFSET 3588
1163#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1164
1165/**
1166 * struct radeon_pm - power management datas
1167 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1168 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1169 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1170 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1171 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1172 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1173 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1174 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1175 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1176 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1177 * @needed_bandwidth: current bandwidth needs
1178 *
1179 * It keeps track of various data needed to take powermanagement decision.
1180 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1181 * Equation between gpu/memory clock and available bandwidth is hw dependent
1182 * (type of memory, bus size, efficiency, ...)
1183 */
1184
1185enum radeon_pm_method {
1186 PM_METHOD_PROFILE,
1187 PM_METHOD_DYNPM,
1188 PM_METHOD_DPM,
1189};
1190
1191enum radeon_dynpm_state {
1192 DYNPM_STATE_DISABLED,
1193 DYNPM_STATE_MINIMUM,
1194 DYNPM_STATE_PAUSED,
1195 DYNPM_STATE_ACTIVE,
1196 DYNPM_STATE_SUSPENDED,
1197};
1198enum radeon_dynpm_action {
1199 DYNPM_ACTION_NONE,
1200 DYNPM_ACTION_MINIMUM,
1201 DYNPM_ACTION_DOWNCLOCK,
1202 DYNPM_ACTION_UPCLOCK,
1203 DYNPM_ACTION_DEFAULT
1204};
1205
1206enum radeon_voltage_type {
1207 VOLTAGE_NONE = 0,
1208 VOLTAGE_GPIO,
1209 VOLTAGE_VDDC,
1210 VOLTAGE_SW
1211};
1212
1213enum radeon_pm_state_type {
1214 /* not used for dpm */
1215 POWER_STATE_TYPE_DEFAULT,
1216 POWER_STATE_TYPE_POWERSAVE,
1217 /* user selectable states */
1218 POWER_STATE_TYPE_BATTERY,
1219 POWER_STATE_TYPE_BALANCED,
1220 POWER_STATE_TYPE_PERFORMANCE,
1221 /* internal states */
1222 POWER_STATE_TYPE_INTERNAL_UVD,
1223 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1224 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1225 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1226 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1227 POWER_STATE_TYPE_INTERNAL_BOOT,
1228 POWER_STATE_TYPE_INTERNAL_THERMAL,
1229 POWER_STATE_TYPE_INTERNAL_ACPI,
1230 POWER_STATE_TYPE_INTERNAL_ULV,
1231 POWER_STATE_TYPE_INTERNAL_3DPERF,
1232};
1233
1234enum radeon_pm_profile_type {
1235 PM_PROFILE_DEFAULT,
1236 PM_PROFILE_AUTO,
1237 PM_PROFILE_LOW,
1238 PM_PROFILE_MID,
1239 PM_PROFILE_HIGH,
1240};
1241
1242#define PM_PROFILE_DEFAULT_IDX 0
1243#define PM_PROFILE_LOW_SH_IDX 1
1244#define PM_PROFILE_MID_SH_IDX 2
1245#define PM_PROFILE_HIGH_SH_IDX 3
1246#define PM_PROFILE_LOW_MH_IDX 4
1247#define PM_PROFILE_MID_MH_IDX 5
1248#define PM_PROFILE_HIGH_MH_IDX 6
1249#define PM_PROFILE_MAX 7
1250
1251struct radeon_pm_profile {
1252 int dpms_off_ps_idx;
1253 int dpms_on_ps_idx;
1254 int dpms_off_cm_idx;
1255 int dpms_on_cm_idx;
1256};
1257
1258enum radeon_int_thermal_type {
1259 THERMAL_TYPE_NONE,
1260 THERMAL_TYPE_EXTERNAL,
1261 THERMAL_TYPE_EXTERNAL_GPIO,
1262 THERMAL_TYPE_RV6XX,
1263 THERMAL_TYPE_RV770,
1264 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1265 THERMAL_TYPE_EVERGREEN,
1266 THERMAL_TYPE_SUMO,
1267 THERMAL_TYPE_NI,
1268 THERMAL_TYPE_SI,
1269 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1270 THERMAL_TYPE_CI,
1271 THERMAL_TYPE_KV,
1272};
1273
1274struct radeon_voltage {
1275 enum radeon_voltage_type type;
1276 /* gpio voltage */
1277 struct radeon_gpio_rec gpio;
1278 u32 delay; /* delay in usec from voltage drop to sclk change */
1279 bool active_high; /* voltage drop is active when bit is high */
1280 /* VDDC voltage */
1281 u8 vddc_id; /* index into vddc voltage table */
1282 u8 vddci_id; /* index into vddci voltage table */
1283 bool vddci_enabled;
1284 /* r6xx+ sw */
1285 u16 voltage;
1286 /* evergreen+ vddci */
1287 u16 vddci;
1288};
1289
1290/* clock mode flags */
1291#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1292
1293struct radeon_pm_clock_info {
1294 /* memory clock */
1295 u32 mclk;
1296 /* engine clock */
1297 u32 sclk;
1298 /* voltage info */
1299 struct radeon_voltage voltage;
1300 /* standardized clock flags */
1301 u32 flags;
1302};
1303
1304/* state flags */
1305#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1306
1307struct radeon_power_state {
1308 enum radeon_pm_state_type type;
1309 struct radeon_pm_clock_info *clock_info;
1310 /* number of valid clock modes in this power state */
1311 int num_clock_modes;
1312 struct radeon_pm_clock_info *default_clock_mode;
1313 /* standardized state flags */
1314 u32 flags;
1315 u32 misc; /* vbios specific flags */
1316 u32 misc2; /* vbios specific flags */
1317 int pcie_lanes; /* pcie lanes */
1318};
1319
1320/*
1321 * Some modes are overclocked by very low value, accept them
1322 */
1323#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1324
1325enum radeon_dpm_auto_throttle_src {
1326 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1327 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1328};
1329
1330enum radeon_dpm_event_src {
1331 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1332 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1333 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1334 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1335 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1336};
1337
1338#define RADEON_MAX_VCE_LEVELS 6
1339
1340enum radeon_vce_level {
1341 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1342 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1343 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1344 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1345 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1346 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1347};
1348
1349struct radeon_ps {
1350 u32 caps; /* vbios flags */
1351 u32 class; /* vbios flags */
1352 u32 class2; /* vbios flags */
1353 /* UVD clocks */
1354 u32 vclk;
1355 u32 dclk;
1356 /* VCE clocks */
1357 u32 evclk;
1358 u32 ecclk;
1359 bool vce_active;
1360 enum radeon_vce_level vce_level;
1361 /* asic priv */
1362 void *ps_priv;
1363};
1364
1365struct radeon_dpm_thermal {
1366 /* thermal interrupt work */
1367 struct work_struct work;
1368 /* low temperature threshold */
1369 int min_temp;
1370 /* high temperature threshold */
1371 int max_temp;
1372 /* was interrupt low to high or high to low */
1373 bool high_to_low;
1374};
1375
1376enum radeon_clk_action
1377{
1378 RADEON_SCLK_UP = 1,
1379 RADEON_SCLK_DOWN
1380};
1381
1382struct radeon_blacklist_clocks
1383{
1384 u32 sclk;
1385 u32 mclk;
1386 enum radeon_clk_action action;
1387};
1388
1389struct radeon_clock_and_voltage_limits {
1390 u32 sclk;
1391 u32 mclk;
1392 u16 vddc;
1393 u16 vddci;
1394};
1395
1396struct radeon_clock_array {
1397 u32 count;
1398 u32 *values;
1399};
1400
1401struct radeon_clock_voltage_dependency_entry {
1402 u32 clk;
1403 u16 v;
1404};
1405
1406struct radeon_clock_voltage_dependency_table {
1407 u32 count;
1408 struct radeon_clock_voltage_dependency_entry *entries;
1409};
1410
1411union radeon_cac_leakage_entry {
1412 struct {
1413 u16 vddc;
1414 u32 leakage;
1415 };
1416 struct {
1417 u16 vddc1;
1418 u16 vddc2;
1419 u16 vddc3;
1420 };
1421};
1422
1423struct radeon_cac_leakage_table {
1424 u32 count;
1425 union radeon_cac_leakage_entry *entries;
1426};
1427
1428struct radeon_phase_shedding_limits_entry {
1429 u16 voltage;
1430 u32 sclk;
1431 u32 mclk;
1432};
1433
1434struct radeon_phase_shedding_limits_table {
1435 u32 count;
1436 struct radeon_phase_shedding_limits_entry *entries;
1437};
1438
1439struct radeon_uvd_clock_voltage_dependency_entry {
1440 u32 vclk;
1441 u32 dclk;
1442 u16 v;
1443};
1444
1445struct radeon_uvd_clock_voltage_dependency_table {
1446 u8 count;
1447 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1448};
1449
1450struct radeon_vce_clock_voltage_dependency_entry {
1451 u32 ecclk;
1452 u32 evclk;
1453 u16 v;
1454};
1455
1456struct radeon_vce_clock_voltage_dependency_table {
1457 u8 count;
1458 struct radeon_vce_clock_voltage_dependency_entry *entries;
1459};
1460
1461struct radeon_ppm_table {
1462 u8 ppm_design;
1463 u16 cpu_core_number;
1464 u32 platform_tdp;
1465 u32 small_ac_platform_tdp;
1466 u32 platform_tdc;
1467 u32 small_ac_platform_tdc;
1468 u32 apu_tdp;
1469 u32 dgpu_tdp;
1470 u32 dgpu_ulv_power;
1471 u32 tj_max;
1472};
1473
1474struct radeon_cac_tdp_table {
1475 u16 tdp;
1476 u16 configurable_tdp;
1477 u16 tdc;
1478 u16 battery_power_limit;
1479 u16 small_power_limit;
1480 u16 low_cac_leakage;
1481 u16 high_cac_leakage;
1482 u16 maximum_power_delivery_limit;
1483};
1484
1485struct radeon_dpm_dynamic_state {
1486 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1487 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1488 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1489 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1490 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1491 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1492 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1493 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1494 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1495 struct radeon_clock_array valid_sclk_values;
1496 struct radeon_clock_array valid_mclk_values;
1497 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1498 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1499 u32 mclk_sclk_ratio;
1500 u32 sclk_mclk_delta;
1501 u16 vddc_vddci_delta;
1502 u16 min_vddc_for_pcie_gen2;
1503 struct radeon_cac_leakage_table cac_leakage_table;
1504 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1505 struct radeon_ppm_table *ppm_table;
1506 struct radeon_cac_tdp_table *cac_tdp_table;
1507};
1508
1509struct radeon_dpm_fan {
1510 u16 t_min;
1511 u16 t_med;
1512 u16 t_high;
1513 u16 pwm_min;
1514 u16 pwm_med;
1515 u16 pwm_high;
1516 u8 t_hyst;
1517 u32 cycle_delay;
1518 u16 t_max;
1519 u8 control_mode;
1520 u16 default_max_fan_pwm;
1521 u16 default_fan_output_sensitivity;
1522 u16 fan_output_sensitivity;
1523 bool ucode_fan_control;
1524};
1525
1526enum radeon_pcie_gen {
1527 RADEON_PCIE_GEN1 = 0,
1528 RADEON_PCIE_GEN2 = 1,
1529 RADEON_PCIE_GEN3 = 2,
1530 RADEON_PCIE_GEN_INVALID = 0xffff
1531};
1532
1533enum radeon_dpm_forced_level {
1534 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1535 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1536 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1537};
1538
1539struct radeon_vce_state {
1540 /* vce clocks */
1541 u32 evclk;
1542 u32 ecclk;
1543 /* gpu clocks */
1544 u32 sclk;
1545 u32 mclk;
1546 u8 clk_idx;
1547 u8 pstate;
1548};
1549
1550struct radeon_dpm {
1551 struct radeon_ps *ps;
1552 /* number of valid power states */
1553 int num_ps;
1554 /* current power state that is active */
1555 struct radeon_ps *current_ps;
1556 /* requested power state */
1557 struct radeon_ps *requested_ps;
1558 /* boot up power state */
1559 struct radeon_ps *boot_ps;
1560 /* default uvd power state */
1561 struct radeon_ps *uvd_ps;
1562 /* vce requirements */
1563 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1564 enum radeon_vce_level vce_level;
1565 enum radeon_pm_state_type state;
1566 enum radeon_pm_state_type user_state;
1567 u32 platform_caps;
1568 u32 voltage_response_time;
1569 u32 backbias_response_time;
1570 void *priv;
1571 u32 new_active_crtcs;
1572 int new_active_crtc_count;
1573 u32 current_active_crtcs;
1574 int current_active_crtc_count;
1575 bool single_display;
1576 struct radeon_dpm_dynamic_state dyn_state;
1577 struct radeon_dpm_fan fan;
1578 u32 tdp_limit;
1579 u32 near_tdp_limit;
1580 u32 near_tdp_limit_adjusted;
1581 u32 sq_ramping_threshold;
1582 u32 cac_leakage;
1583 u16 tdp_od_limit;
1584 u32 tdp_adjustment;
1585 u16 load_line_slope;
1586 bool power_control;
1587 bool ac_power;
1588 /* special states active */
1589 bool thermal_active;
1590 bool uvd_active;
1591 bool vce_active;
1592 /* thermal handling */
1593 struct radeon_dpm_thermal thermal;
1594 /* forced levels */
1595 enum radeon_dpm_forced_level forced_level;
1596 /* track UVD streams */
1597 unsigned sd;
1598 unsigned hd;
1599};
1600
1601void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1602void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1603
1604struct radeon_pm {
1605 struct mutex mutex;
1606 /* write locked while reprogramming mclk */
1607 struct rw_semaphore mclk_lock;
1608 u32 active_crtcs;
1609 int active_crtc_count;
1610 int req_vblank;
1611 bool vblank_sync;
1612 fixed20_12 max_bandwidth;
1613 fixed20_12 igp_sideport_mclk;
1614 fixed20_12 igp_system_mclk;
1615 fixed20_12 igp_ht_link_clk;
1616 fixed20_12 igp_ht_link_width;
1617 fixed20_12 k8_bandwidth;
1618 fixed20_12 sideport_bandwidth;
1619 fixed20_12 ht_bandwidth;
1620 fixed20_12 core_bandwidth;
1621 fixed20_12 sclk;
1622 fixed20_12 mclk;
1623 fixed20_12 needed_bandwidth;
1624 struct radeon_power_state *power_state;
1625 /* number of valid power states */
1626 int num_power_states;
1627 int current_power_state_index;
1628 int current_clock_mode_index;
1629 int requested_power_state_index;
1630 int requested_clock_mode_index;
1631 int default_power_state_index;
1632 u32 current_sclk;
1633 u32 current_mclk;
1634 u16 current_vddc;
1635 u16 current_vddci;
1636 u32 default_sclk;
1637 u32 default_mclk;
1638 u16 default_vddc;
1639 u16 default_vddci;
1640 struct radeon_i2c_chan *i2c_bus;
1641 /* selected pm method */
1642 enum radeon_pm_method pm_method;
1643 /* dynpm power management */
1644 struct delayed_work dynpm_idle_work;
1645 enum radeon_dynpm_state dynpm_state;
1646 enum radeon_dynpm_action dynpm_planned_action;
1647 unsigned long dynpm_action_timeout;
1648 bool dynpm_can_upclock;
1649 bool dynpm_can_downclock;
1650 /* profile-based power management */
1651 enum radeon_pm_profile_type profile;
1652 int profile_index;
1653 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1654 /* internal thermal controller on rv6xx+ */
1655 enum radeon_int_thermal_type int_thermal_type;
1656 struct device *int_hwmon_dev;
1657 /* fan control parameters */
1658 bool no_fan;
1659 u8 fan_pulses_per_revolution;
1660 u8 fan_min_rpm;
1661 u8 fan_max_rpm;
1662 /* dpm */
1663 bool dpm_enabled;
1664 bool sysfs_initialized;
1665 struct radeon_dpm dpm;
1666};
1667
1668int radeon_pm_get_type_index(struct radeon_device *rdev,
1669 enum radeon_pm_state_type ps_type,
1670 int instance);
1671/*
1672 * UVD
1673 */
1674#define RADEON_MAX_UVD_HANDLES 10
1675#define RADEON_UVD_STACK_SIZE (1024*1024)
1676#define RADEON_UVD_HEAP_SIZE (1024*1024)
1677
1678struct radeon_uvd {
1679 struct radeon_bo *vcpu_bo;
1680 void *cpu_addr;
1681 uint64_t gpu_addr;
1682 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1683 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1684 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1685 struct delayed_work idle_work;
1686};
1687
1688int radeon_uvd_init(struct radeon_device *rdev);
1689void radeon_uvd_fini(struct radeon_device *rdev);
1690int radeon_uvd_suspend(struct radeon_device *rdev);
1691int radeon_uvd_resume(struct radeon_device *rdev);
1692int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1693 uint32_t handle, struct radeon_fence **fence);
1694int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1695 uint32_t handle, struct radeon_fence **fence);
1696void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1697 uint32_t allowed_domains);
1698void radeon_uvd_free_handles(struct radeon_device *rdev,
1699 struct drm_file *filp);
1700int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1701void radeon_uvd_note_usage(struct radeon_device *rdev);
1702int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1703 unsigned vclk, unsigned dclk,
1704 unsigned vco_min, unsigned vco_max,
1705 unsigned fb_factor, unsigned fb_mask,
1706 unsigned pd_min, unsigned pd_max,
1707 unsigned pd_even,
1708 unsigned *optimal_fb_div,
1709 unsigned *optimal_vclk_div,
1710 unsigned *optimal_dclk_div);
1711int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1712 unsigned cg_upll_func_cntl);
1713
1714/*
1715 * VCE
1716 */
1717#define RADEON_MAX_VCE_HANDLES 16
1718
1719struct radeon_vce {
1720 struct radeon_bo *vcpu_bo;
1721 uint64_t gpu_addr;
1722 unsigned fw_version;
1723 unsigned fb_version;
1724 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1725 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1726 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1727 struct delayed_work idle_work;
1728 uint32_t keyselect;
1729};
1730
1731int radeon_vce_init(struct radeon_device *rdev);
1732void radeon_vce_fini(struct radeon_device *rdev);
1733int radeon_vce_suspend(struct radeon_device *rdev);
1734int radeon_vce_resume(struct radeon_device *rdev);
1735int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1736 uint32_t handle, struct radeon_fence **fence);
1737int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1738 uint32_t handle, struct radeon_fence **fence);
1739void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1740void radeon_vce_note_usage(struct radeon_device *rdev);
1741int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1742int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1743bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1744 struct radeon_ring *ring,
1745 struct radeon_semaphore *semaphore,
1746 bool emit_wait);
1747void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1748void radeon_vce_fence_emit(struct radeon_device *rdev,
1749 struct radeon_fence *fence);
1750int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1751int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1752
1753struct r600_audio_pin {
1754 int channels;
1755 int rate;
1756 int bits_per_sample;
1757 u8 status_bits;
1758 u8 category_code;
1759 u32 offset;
1760 bool connected;
1761 u32 id;
1762};
1763
1764struct r600_audio {
1765 bool enabled;
1766 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1767 int num_pins;
1768 struct radeon_audio_funcs *hdmi_funcs;
1769 struct radeon_audio_funcs *dp_funcs;
1770 struct radeon_audio_basic_funcs *funcs;
1771};
1772
1773/*
1774 * Benchmarking
1775 */
1776void radeon_benchmark(struct radeon_device *rdev, int test_number);
1777
1778
1779/*
1780 * Testing
1781 */
1782void radeon_test_moves(struct radeon_device *rdev);
1783void radeon_test_ring_sync(struct radeon_device *rdev,
1784 struct radeon_ring *cpA,
1785 struct radeon_ring *cpB);
1786void radeon_test_syncing(struct radeon_device *rdev);
1787
1788/*
1789 * MMU Notifier
1790 */
1791#if defined(CONFIG_MMU_NOTIFIER)
1792int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1793void radeon_mn_unregister(struct radeon_bo *bo);
1794#else
1795static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1796{
1797 return -ENODEV;
1798}
1799static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1800#endif
1801
1802/*
1803 * Debugfs
1804 */
1805struct radeon_debugfs {
1806 struct drm_info_list *files;
1807 unsigned num_files;
1808};
1809
1810int radeon_debugfs_add_files(struct radeon_device *rdev,
1811 struct drm_info_list *files,
1812 unsigned nfiles);
1813int radeon_debugfs_fence_init(struct radeon_device *rdev);
1814
1815/*
1816 * ASIC ring specific functions.
1817 */
1818struct radeon_asic_ring {
1819 /* ring read/write ptr handling */
1820 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1821 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1822 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1823
1824 /* validating and patching of IBs */
1825 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1826 int (*cs_parse)(struct radeon_cs_parser *p);
1827
1828 /* command emmit functions */
1829 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1830 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1831 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1832 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1833 struct radeon_semaphore *semaphore, bool emit_wait);
1834 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1835 unsigned vm_id, uint64_t pd_addr);
1836
1837 /* testing functions */
1838 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1839 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1840 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1841
1842 /* deprecated */
1843 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1844};
1845
1846/*
1847 * ASIC specific functions.
1848 */
1849struct radeon_asic {
1850 int (*init)(struct radeon_device *rdev);
1851 void (*fini)(struct radeon_device *rdev);
1852 int (*resume)(struct radeon_device *rdev);
1853 int (*suspend)(struct radeon_device *rdev);
1854 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1855 int (*asic_reset)(struct radeon_device *rdev);
1856 /* Flush the HDP cache via MMIO */
1857 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1858 /* check if 3D engine is idle */
1859 bool (*gui_idle)(struct radeon_device *rdev);
1860 /* wait for mc_idle */
1861 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1862 /* get the reference clock */
1863 u32 (*get_xclk)(struct radeon_device *rdev);
1864 /* get the gpu clock counter */
1865 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1866 /* get register for info ioctl */
1867 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
1868 /* gart */
1869 struct {
1870 void (*tlb_flush)(struct radeon_device *rdev);
1871 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
1872 void (*set_page)(struct radeon_device *rdev, unsigned i,
1873 uint64_t entry);
1874 } gart;
1875 struct {
1876 int (*init)(struct radeon_device *rdev);
1877 void (*fini)(struct radeon_device *rdev);
1878 void (*copy_pages)(struct radeon_device *rdev,
1879 struct radeon_ib *ib,
1880 uint64_t pe, uint64_t src,
1881 unsigned count);
1882 void (*write_pages)(struct radeon_device *rdev,
1883 struct radeon_ib *ib,
1884 uint64_t pe,
1885 uint64_t addr, unsigned count,
1886 uint32_t incr, uint32_t flags);
1887 void (*set_pages)(struct radeon_device *rdev,
1888 struct radeon_ib *ib,
1889 uint64_t pe,
1890 uint64_t addr, unsigned count,
1891 uint32_t incr, uint32_t flags);
1892 void (*pad_ib)(struct radeon_ib *ib);
1893 } vm;
1894 /* ring specific callbacks */
1895 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1896 /* irqs */
1897 struct {
1898 int (*set)(struct radeon_device *rdev);
1899 int (*process)(struct radeon_device *rdev);
1900 } irq;
1901 /* displays */
1902 struct {
1903 /* display watermarks */
1904 void (*bandwidth_update)(struct radeon_device *rdev);
1905 /* get frame count */
1906 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1907 /* wait for vblank */
1908 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1909 /* set backlight level */
1910 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1911 /* get backlight level */
1912 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1913 /* audio callbacks */
1914 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1915 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1916 } display;
1917 /* copy functions for bo handling */
1918 struct {
1919 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1920 uint64_t src_offset,
1921 uint64_t dst_offset,
1922 unsigned num_gpu_pages,
1923 struct reservation_object *resv);
1924 u32 blit_ring_index;
1925 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1926 uint64_t src_offset,
1927 uint64_t dst_offset,
1928 unsigned num_gpu_pages,
1929 struct reservation_object *resv);
1930 u32 dma_ring_index;
1931 /* method used for bo copy */
1932 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1933 uint64_t src_offset,
1934 uint64_t dst_offset,
1935 unsigned num_gpu_pages,
1936 struct reservation_object *resv);
1937 /* ring used for bo copies */
1938 u32 copy_ring_index;
1939 } copy;
1940 /* surfaces */
1941 struct {
1942 int (*set_reg)(struct radeon_device *rdev, int reg,
1943 uint32_t tiling_flags, uint32_t pitch,
1944 uint32_t offset, uint32_t obj_size);
1945 void (*clear_reg)(struct radeon_device *rdev, int reg);
1946 } surface;
1947 /* hotplug detect */
1948 struct {
1949 void (*init)(struct radeon_device *rdev);
1950 void (*fini)(struct radeon_device *rdev);
1951 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1952 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1953 } hpd;
1954 /* static power management */
1955 struct {
1956 void (*misc)(struct radeon_device *rdev);
1957 void (*prepare)(struct radeon_device *rdev);
1958 void (*finish)(struct radeon_device *rdev);
1959 void (*init_profile)(struct radeon_device *rdev);
1960 void (*get_dynpm_state)(struct radeon_device *rdev);
1961 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1962 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1963 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1964 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1965 int (*get_pcie_lanes)(struct radeon_device *rdev);
1966 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1967 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1968 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1969 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1970 int (*get_temperature)(struct radeon_device *rdev);
1971 } pm;
1972 /* dynamic power management */
1973 struct {
1974 int (*init)(struct radeon_device *rdev);
1975 void (*setup_asic)(struct radeon_device *rdev);
1976 int (*enable)(struct radeon_device *rdev);
1977 int (*late_enable)(struct radeon_device *rdev);
1978 void (*disable)(struct radeon_device *rdev);
1979 int (*pre_set_power_state)(struct radeon_device *rdev);
1980 int (*set_power_state)(struct radeon_device *rdev);
1981 void (*post_set_power_state)(struct radeon_device *rdev);
1982 void (*display_configuration_changed)(struct radeon_device *rdev);
1983 void (*fini)(struct radeon_device *rdev);
1984 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1985 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1986 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1987 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1988 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1989 bool (*vblank_too_short)(struct radeon_device *rdev);
1990 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1991 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1992 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
1993 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
1994 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
1995 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
1996 u32 (*get_current_sclk)(struct radeon_device *rdev);
1997 u32 (*get_current_mclk)(struct radeon_device *rdev);
1998 } dpm;
1999 /* pageflipping */
2000 struct {
2001 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
2002 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
2003 } pflip;
2004};
2005
2006/*
2007 * Asic structures
2008 */
2009struct r100_asic {
2010 const unsigned *reg_safe_bm;
2011 unsigned reg_safe_bm_size;
2012 u32 hdp_cntl;
2013};
2014
2015struct r300_asic {
2016 const unsigned *reg_safe_bm;
2017 unsigned reg_safe_bm_size;
2018 u32 resync_scratch;
2019 u32 hdp_cntl;
2020};
2021
2022struct r600_asic {
2023 unsigned max_pipes;
2024 unsigned max_tile_pipes;
2025 unsigned max_simds;
2026 unsigned max_backends;
2027 unsigned max_gprs;
2028 unsigned max_threads;
2029 unsigned max_stack_entries;
2030 unsigned max_hw_contexts;
2031 unsigned max_gs_threads;
2032 unsigned sx_max_export_size;
2033 unsigned sx_max_export_pos_size;
2034 unsigned sx_max_export_smx_size;
2035 unsigned sq_num_cf_insts;
2036 unsigned tiling_nbanks;
2037 unsigned tiling_npipes;
2038 unsigned tiling_group_size;
2039 unsigned tile_config;
2040 unsigned backend_map;
2041 unsigned active_simds;
2042};
2043
2044struct rv770_asic {
2045 unsigned max_pipes;
2046 unsigned max_tile_pipes;
2047 unsigned max_simds;
2048 unsigned max_backends;
2049 unsigned max_gprs;
2050 unsigned max_threads;
2051 unsigned max_stack_entries;
2052 unsigned max_hw_contexts;
2053 unsigned max_gs_threads;
2054 unsigned sx_max_export_size;
2055 unsigned sx_max_export_pos_size;
2056 unsigned sx_max_export_smx_size;
2057 unsigned sq_num_cf_insts;
2058 unsigned sx_num_of_sets;
2059 unsigned sc_prim_fifo_size;
2060 unsigned sc_hiz_tile_fifo_size;
2061 unsigned sc_earlyz_tile_fifo_fize;
2062 unsigned tiling_nbanks;
2063 unsigned tiling_npipes;
2064 unsigned tiling_group_size;
2065 unsigned tile_config;
2066 unsigned backend_map;
2067 unsigned active_simds;
2068};
2069
2070struct evergreen_asic {
2071 unsigned num_ses;
2072 unsigned max_pipes;
2073 unsigned max_tile_pipes;
2074 unsigned max_simds;
2075 unsigned max_backends;
2076 unsigned max_gprs;
2077 unsigned max_threads;
2078 unsigned max_stack_entries;
2079 unsigned max_hw_contexts;
2080 unsigned max_gs_threads;
2081 unsigned sx_max_export_size;
2082 unsigned sx_max_export_pos_size;
2083 unsigned sx_max_export_smx_size;
2084 unsigned sq_num_cf_insts;
2085 unsigned sx_num_of_sets;
2086 unsigned sc_prim_fifo_size;
2087 unsigned sc_hiz_tile_fifo_size;
2088 unsigned sc_earlyz_tile_fifo_size;
2089 unsigned tiling_nbanks;
2090 unsigned tiling_npipes;
2091 unsigned tiling_group_size;
2092 unsigned tile_config;
2093 unsigned backend_map;
2094 unsigned active_simds;
2095};
2096
2097struct cayman_asic {
2098 unsigned max_shader_engines;
2099 unsigned max_pipes_per_simd;
2100 unsigned max_tile_pipes;
2101 unsigned max_simds_per_se;
2102 unsigned max_backends_per_se;
2103 unsigned max_texture_channel_caches;
2104 unsigned max_gprs;
2105 unsigned max_threads;
2106 unsigned max_gs_threads;
2107 unsigned max_stack_entries;
2108 unsigned sx_num_of_sets;
2109 unsigned sx_max_export_size;
2110 unsigned sx_max_export_pos_size;
2111 unsigned sx_max_export_smx_size;
2112 unsigned max_hw_contexts;
2113 unsigned sq_num_cf_insts;
2114 unsigned sc_prim_fifo_size;
2115 unsigned sc_hiz_tile_fifo_size;
2116 unsigned sc_earlyz_tile_fifo_size;
2117
2118 unsigned num_shader_engines;
2119 unsigned num_shader_pipes_per_simd;
2120 unsigned num_tile_pipes;
2121 unsigned num_simds_per_se;
2122 unsigned num_backends_per_se;
2123 unsigned backend_disable_mask_per_asic;
2124 unsigned backend_map;
2125 unsigned num_texture_channel_caches;
2126 unsigned mem_max_burst_length_bytes;
2127 unsigned mem_row_size_in_kb;
2128 unsigned shader_engine_tile_size;
2129 unsigned num_gpus;
2130 unsigned multi_gpu_tile_size;
2131
2132 unsigned tile_config;
2133 unsigned active_simds;
2134};
2135
2136struct si_asic {
2137 unsigned max_shader_engines;
2138 unsigned max_tile_pipes;
2139 unsigned max_cu_per_sh;
2140 unsigned max_sh_per_se;
2141 unsigned max_backends_per_se;
2142 unsigned max_texture_channel_caches;
2143 unsigned max_gprs;
2144 unsigned max_gs_threads;
2145 unsigned max_hw_contexts;
2146 unsigned sc_prim_fifo_size_frontend;
2147 unsigned sc_prim_fifo_size_backend;
2148 unsigned sc_hiz_tile_fifo_size;
2149 unsigned sc_earlyz_tile_fifo_size;
2150
2151 unsigned num_tile_pipes;
2152 unsigned backend_enable_mask;
2153 unsigned backend_disable_mask_per_asic;
2154 unsigned backend_map;
2155 unsigned num_texture_channel_caches;
2156 unsigned mem_max_burst_length_bytes;
2157 unsigned mem_row_size_in_kb;
2158 unsigned shader_engine_tile_size;
2159 unsigned num_gpus;
2160 unsigned multi_gpu_tile_size;
2161
2162 unsigned tile_config;
2163 uint32_t tile_mode_array[32];
2164 uint32_t active_cus;
2165};
2166
2167struct cik_asic {
2168 unsigned max_shader_engines;
2169 unsigned max_tile_pipes;
2170 unsigned max_cu_per_sh;
2171 unsigned max_sh_per_se;
2172 unsigned max_backends_per_se;
2173 unsigned max_texture_channel_caches;
2174 unsigned max_gprs;
2175 unsigned max_gs_threads;
2176 unsigned max_hw_contexts;
2177 unsigned sc_prim_fifo_size_frontend;
2178 unsigned sc_prim_fifo_size_backend;
2179 unsigned sc_hiz_tile_fifo_size;
2180 unsigned sc_earlyz_tile_fifo_size;
2181
2182 unsigned num_tile_pipes;
2183 unsigned backend_enable_mask;
2184 unsigned backend_disable_mask_per_asic;
2185 unsigned backend_map;
2186 unsigned num_texture_channel_caches;
2187 unsigned mem_max_burst_length_bytes;
2188 unsigned mem_row_size_in_kb;
2189 unsigned shader_engine_tile_size;
2190 unsigned num_gpus;
2191 unsigned multi_gpu_tile_size;
2192
2193 unsigned tile_config;
2194 uint32_t tile_mode_array[32];
2195 uint32_t macrotile_mode_array[16];
2196 uint32_t active_cus;
2197};
2198
2199union radeon_asic_config {
2200 struct r300_asic r300;
2201 struct r100_asic r100;
2202 struct r600_asic r600;
2203 struct rv770_asic rv770;
2204 struct evergreen_asic evergreen;
2205 struct cayman_asic cayman;
2206 struct si_asic si;
2207 struct cik_asic cik;
2208};
2209
2210/*
2211 * asic initizalization from radeon_asic.c
2212 */
2213void radeon_agp_disable(struct radeon_device *rdev);
2214int radeon_asic_init(struct radeon_device *rdev);
2215
2216
2217/*
2218 * IOCTL.
2219 */
2220int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2221 struct drm_file *filp);
2222int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2223 struct drm_file *filp);
2224int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2225 struct drm_file *filp);
2226int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2227 struct drm_file *file_priv);
2228int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2229 struct drm_file *file_priv);
2230int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2231 struct drm_file *file_priv);
2232int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2233 struct drm_file *file_priv);
2234int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2235 struct drm_file *filp);
2236int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2237 struct drm_file *filp);
2238int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2239 struct drm_file *filp);
2240int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2241 struct drm_file *filp);
2242int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2243 struct drm_file *filp);
2244int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2245 struct drm_file *filp);
2246int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2247int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2248 struct drm_file *filp);
2249int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2250 struct drm_file *filp);
2251
2252/* VRAM scratch page for HDP bug, default vram page */
2253struct r600_vram_scratch {
2254 struct radeon_bo *robj;
2255 volatile uint32_t *ptr;
2256 u64 gpu_addr;
2257};
2258
2259/*
2260 * ACPI
2261 */
2262struct radeon_atif_notification_cfg {
2263 bool enabled;
2264 int command_code;
2265};
2266
2267struct radeon_atif_notifications {
2268 bool display_switch;
2269 bool expansion_mode_change;
2270 bool thermal_state;
2271 bool forced_power_state;
2272 bool system_power_state;
2273 bool display_conf_change;
2274 bool px_gfx_switch;
2275 bool brightness_change;
2276 bool dgpu_display_event;
2277};
2278
2279struct radeon_atif_functions {
2280 bool system_params;
2281 bool sbios_requests;
2282 bool select_active_disp;
2283 bool lid_state;
2284 bool get_tv_standard;
2285 bool set_tv_standard;
2286 bool get_panel_expansion_mode;
2287 bool set_panel_expansion_mode;
2288 bool temperature_change;
2289 bool graphics_device_types;
2290};
2291
2292struct radeon_atif {
2293 struct radeon_atif_notifications notifications;
2294 struct radeon_atif_functions functions;
2295 struct radeon_atif_notification_cfg notification_cfg;
2296 struct radeon_encoder *encoder_for_bl;
2297};
2298
2299struct radeon_atcs_functions {
2300 bool get_ext_state;
2301 bool pcie_perf_req;
2302 bool pcie_dev_rdy;
2303 bool pcie_bus_width;
2304};
2305
2306struct radeon_atcs {
2307 struct radeon_atcs_functions functions;
2308};
2309
2310/*
2311 * Core structure, functions and helpers.
2312 */
2313typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2314typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2315
2316struct radeon_device {
2317 struct device *dev;
2318 struct drm_device *ddev;
2319 struct pci_dev *pdev;
2320 struct rw_semaphore exclusive_lock;
2321 /* ASIC */
2322 union radeon_asic_config config;
2323 enum radeon_family family;
2324 unsigned long flags;
2325 int usec_timeout;
2326 enum radeon_pll_errata pll_errata;
2327 int num_gb_pipes;
2328 int num_z_pipes;
2329 int disp_priority;
2330 /* BIOS */
2331 uint8_t *bios;
2332 bool is_atom_bios;
2333 uint16_t bios_header_start;
2334 struct radeon_bo *stollen_vga_memory;
2335 /* Register mmio */
2336 resource_size_t rmmio_base;
2337 resource_size_t rmmio_size;
2338 /* protects concurrent MM_INDEX/DATA based register access */
2339 spinlock_t mmio_idx_lock;
2340 /* protects concurrent SMC based register access */
2341 spinlock_t smc_idx_lock;
2342 /* protects concurrent PLL register access */
2343 spinlock_t pll_idx_lock;
2344 /* protects concurrent MC register access */
2345 spinlock_t mc_idx_lock;
2346 /* protects concurrent PCIE register access */
2347 spinlock_t pcie_idx_lock;
2348 /* protects concurrent PCIE_PORT register access */
2349 spinlock_t pciep_idx_lock;
2350 /* protects concurrent PIF register access */
2351 spinlock_t pif_idx_lock;
2352 /* protects concurrent CG register access */
2353 spinlock_t cg_idx_lock;
2354 /* protects concurrent UVD register access */
2355 spinlock_t uvd_idx_lock;
2356 /* protects concurrent RCU register access */
2357 spinlock_t rcu_idx_lock;
2358 /* protects concurrent DIDT register access */
2359 spinlock_t didt_idx_lock;
2360 /* protects concurrent ENDPOINT (audio) register access */
2361 spinlock_t end_idx_lock;
2362 void __iomem *rmmio;
2363 radeon_rreg_t mc_rreg;
2364 radeon_wreg_t mc_wreg;
2365 radeon_rreg_t pll_rreg;
2366 radeon_wreg_t pll_wreg;
2367 uint32_t pcie_reg_mask;
2368 radeon_rreg_t pciep_rreg;
2369 radeon_wreg_t pciep_wreg;
2370 /* io port */
2371 void __iomem *rio_mem;
2372 resource_size_t rio_mem_size;
2373 struct radeon_clock clock;
2374 struct radeon_mc mc;
2375 struct radeon_gart gart;
2376 struct radeon_mode_info mode_info;
2377 struct radeon_scratch scratch;
2378 struct radeon_doorbell doorbell;
2379 struct radeon_mman mman;
2380 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2381 wait_queue_head_t fence_queue;
2382 unsigned fence_context;
2383 struct mutex ring_lock;
2384 struct radeon_ring ring[RADEON_NUM_RINGS];
2385 bool ib_pool_ready;
2386 struct radeon_sa_manager ring_tmp_bo;
2387 struct radeon_irq irq;
2388 struct radeon_asic *asic;
2389 struct radeon_gem gem;
2390 struct radeon_pm pm;
2391 struct radeon_uvd uvd;
2392 struct radeon_vce vce;
2393 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2394 struct radeon_wb wb;
2395 struct radeon_dummy_page dummy_page;
2396 bool shutdown;
2397 bool suspend;
2398 bool need_dma32;
2399 bool accel_working;
2400 bool fastfb_working; /* IGP feature*/
2401 bool needs_reset, in_reset;
2402 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2403 const struct firmware *me_fw; /* all family ME firmware */
2404 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2405 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2406 const struct firmware *mc_fw; /* NI MC firmware */
2407 const struct firmware *ce_fw; /* SI CE firmware */
2408 const struct firmware *mec_fw; /* CIK MEC firmware */
2409 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2410 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2411 const struct firmware *smc_fw; /* SMC firmware */
2412 const struct firmware *uvd_fw; /* UVD firmware */
2413 const struct firmware *vce_fw; /* VCE firmware */
2414 bool new_fw;
2415 struct r600_vram_scratch vram_scratch;
2416 int msi_enabled; /* msi enabled */
2417 struct r600_ih ih; /* r6/700 interrupt ring */
2418 struct radeon_rlc rlc;
2419 struct radeon_mec mec;
2420 struct delayed_work hotplug_work;
2421 struct work_struct dp_work;
2422 struct work_struct audio_work;
2423 int num_crtc; /* number of crtcs */
2424 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2425 bool has_uvd;
2426 struct r600_audio audio; /* audio stuff */
2427 struct notifier_block acpi_nb;
2428 /* only one userspace can use Hyperz features or CMASK at a time */
2429 struct drm_file *hyperz_filp;
2430 struct drm_file *cmask_filp;
2431 /* i2c buses */
2432 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2433 /* debugfs */
2434 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2435 unsigned debugfs_count;
2436 /* virtual memory */
2437 struct radeon_vm_manager vm_manager;
2438 struct mutex gpu_clock_mutex;
2439 /* memory stats */
2440 atomic64_t vram_usage;
2441 atomic64_t gtt_usage;
2442 atomic64_t num_bytes_moved;
2443 atomic_t gpu_reset_counter;
2444 /* ACPI interface */
2445 struct radeon_atif atif;
2446 struct radeon_atcs atcs;
2447 /* srbm instance registers */
2448 struct mutex srbm_mutex;
2449 /* GRBM index mutex. Protects concurrents access to GRBM index */
2450 struct mutex grbm_idx_mutex;
2451 /* clock, powergating flags */
2452 u32 cg_flags;
2453 u32 pg_flags;
2454
2455 struct dev_pm_domain vga_pm_domain;
2456 bool have_disp_power_ref;
2457 u32 px_quirk_flags;
2458
2459 /* tracking pinned memory */
2460 u64 vram_pin_size;
2461 u64 gart_pin_size;
2462
2463 /* amdkfd interface */
2464 struct kfd_dev *kfd;
2465
2466 struct mutex mn_lock;
2467 DECLARE_HASHTABLE(mn_hash, 7);
2468};
2469
2470bool radeon_is_px(struct drm_device *dev);
2471int radeon_device_init(struct radeon_device *rdev,
2472 struct drm_device *ddev,
2473 struct pci_dev *pdev,
2474 uint32_t flags);
2475void radeon_device_fini(struct radeon_device *rdev);
2476int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2477
2478#define RADEON_MIN_MMIO_SIZE 0x10000
2479
2480uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2481void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2482static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2483 bool always_indirect)
2484{
2485 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2486 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2487 return readl(((void __iomem *)rdev->rmmio) + reg);
2488 else
2489 return r100_mm_rreg_slow(rdev, reg);
2490}
2491static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2492 bool always_indirect)
2493{
2494 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2495 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2496 else
2497 r100_mm_wreg_slow(rdev, reg, v);
2498}
2499
2500u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2501void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2502
2503u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2504void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2505
2506/*
2507 * Cast helper
2508 */
2509extern const struct fence_ops radeon_fence_ops;
2510
2511static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2512{
2513 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2514
2515 if (__f->base.ops == &radeon_fence_ops)
2516 return __f;
2517
2518 return NULL;
2519}
2520
2521/*
2522 * Registers read & write functions.
2523 */
2524#define RREG8(reg) readb((rdev->rmmio) + (reg))
2525#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2526#define RREG16(reg) readw((rdev->rmmio) + (reg))
2527#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2528#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2529#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2530#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2531#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2532#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2533#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2534#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2535#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2536#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2537#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2538#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2539#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2540#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2541#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2542#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2543#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2544#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2545#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2546#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2547#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2548#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2549#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2550#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2551#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2552#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2553#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2554#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2555#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2556#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2557#define WREG32_P(reg, val, mask) \
2558 do { \
2559 uint32_t tmp_ = RREG32(reg); \
2560 tmp_ &= (mask); \
2561 tmp_ |= ((val) & ~(mask)); \
2562 WREG32(reg, tmp_); \
2563 } while (0)
2564#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2565#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2566#define WREG32_PLL_P(reg, val, mask) \
2567 do { \
2568 uint32_t tmp_ = RREG32_PLL(reg); \
2569 tmp_ &= (mask); \
2570 tmp_ |= ((val) & ~(mask)); \
2571 WREG32_PLL(reg, tmp_); \
2572 } while (0)
2573#define WREG32_SMC_P(reg, val, mask) \
2574 do { \
2575 uint32_t tmp_ = RREG32_SMC(reg); \
2576 tmp_ &= (mask); \
2577 tmp_ |= ((val) & ~(mask)); \
2578 WREG32_SMC(reg, tmp_); \
2579 } while (0)
2580#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2581#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2582#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2583
2584#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2585#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2586
2587/*
2588 * Indirect registers accessors.
2589 * They used to be inlined, but this increases code size by ~65 kbytes.
2590 * Since each performs a pair of MMIO ops
2591 * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2592 * the cost of call+ret is almost negligible. MMIO and locking
2593 * costs several dozens of cycles each at best, call+ret is ~5 cycles.
2594 */
2595uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2596void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2597u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2598void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2599u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2600void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2601u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2602void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2603u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2604void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2605u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2606void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2607u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2608void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2609u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2610void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2611
2612void r100_pll_errata_after_index(struct radeon_device *rdev);
2613
2614
2615/*
2616 * ASICs helpers.
2617 */
2618#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2619 (rdev->pdev->device == 0x5969))
2620#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2621 (rdev->family == CHIP_RV200) || \
2622 (rdev->family == CHIP_RS100) || \
2623 (rdev->family == CHIP_RS200) || \
2624 (rdev->family == CHIP_RV250) || \
2625 (rdev->family == CHIP_RV280) || \
2626 (rdev->family == CHIP_RS300))
2627#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2628 (rdev->family == CHIP_RV350) || \
2629 (rdev->family == CHIP_R350) || \
2630 (rdev->family == CHIP_RV380) || \
2631 (rdev->family == CHIP_R420) || \
2632 (rdev->family == CHIP_R423) || \
2633 (rdev->family == CHIP_RV410) || \
2634 (rdev->family == CHIP_RS400) || \
2635 (rdev->family == CHIP_RS480))
2636#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2637 (rdev->ddev->pdev->device == 0x9443) || \
2638 (rdev->ddev->pdev->device == 0x944B) || \
2639 (rdev->ddev->pdev->device == 0x9506) || \
2640 (rdev->ddev->pdev->device == 0x9509) || \
2641 (rdev->ddev->pdev->device == 0x950F) || \
2642 (rdev->ddev->pdev->device == 0x689C) || \
2643 (rdev->ddev->pdev->device == 0x689D))
2644#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2645#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2646 (rdev->family == CHIP_RS690) || \
2647 (rdev->family == CHIP_RS740) || \
2648 (rdev->family >= CHIP_R600))
2649#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2650#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2651#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2652#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2653 (rdev->flags & RADEON_IS_IGP))
2654#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2655#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2656#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2657 (rdev->flags & RADEON_IS_IGP))
2658#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2659#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2660#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2661#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2662#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2663#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2664 (rdev->family == CHIP_MULLINS))
2665
2666#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2667 (rdev->ddev->pdev->device == 0x6850) || \
2668 (rdev->ddev->pdev->device == 0x6858) || \
2669 (rdev->ddev->pdev->device == 0x6859) || \
2670 (rdev->ddev->pdev->device == 0x6840) || \
2671 (rdev->ddev->pdev->device == 0x6841) || \
2672 (rdev->ddev->pdev->device == 0x6842) || \
2673 (rdev->ddev->pdev->device == 0x6843))
2674
2675/*
2676 * BIOS helpers.
2677 */
2678#define RBIOS8(i) (rdev->bios[i])
2679#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2680#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2681
2682int radeon_combios_init(struct radeon_device *rdev);
2683void radeon_combios_fini(struct radeon_device *rdev);
2684int radeon_atombios_init(struct radeon_device *rdev);
2685void radeon_atombios_fini(struct radeon_device *rdev);
2686
2687
2688/*
2689 * RING helpers.
2690 */
2691
2692/**
2693 * radeon_ring_write - write a value to the ring
2694 *
2695 * @ring: radeon_ring structure holding ring information
2696 * @v: dword (dw) value to write
2697 *
2698 * Write a value to the requested ring buffer (all asics).
2699 */
2700static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2701{
2702 if (ring->count_dw <= 0)
2703 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2704
2705 ring->ring[ring->wptr++] = v;
2706 ring->wptr &= ring->ptr_mask;
2707 ring->count_dw--;
2708 ring->ring_free_dw--;
2709}
2710
2711/*
2712 * ASICs macro.
2713 */
2714#define radeon_init(rdev) (rdev)->asic->init((rdev))
2715#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2716#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2717#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2718#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2719#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2720#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2721#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2722#define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2723#define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2724#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2725#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2726#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2727#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2728#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2729#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2730#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2731#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2732#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2733#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2734#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2735#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2736#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2737#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2738#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2739#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2740#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2741#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2742#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2743#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2744#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2745#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2746#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2747#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2748#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2749#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2750#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2751#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2752#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2753#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2754#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2755#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2756#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2757#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2758#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2759#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2760#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2761#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2762#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2763#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2764#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2765#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2766#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2767#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2768#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2769#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2770#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2771#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2772#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2773#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2774#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2775#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2776#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2777#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2778#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2779#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2780#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2781#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2782#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2783#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2784#define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
2785#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2786#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2787#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2788#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2789#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2790#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2791#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2792#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2793#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2794#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2795#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2796#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2797#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2798#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2799#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2800#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2801#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2802#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2803#define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2804#define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
2805
2806/* Common functions */
2807/* AGP */
2808extern int radeon_gpu_reset(struct radeon_device *rdev);
2809extern void radeon_pci_config_reset(struct radeon_device *rdev);
2810extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2811extern void radeon_agp_disable(struct radeon_device *rdev);
2812extern int radeon_modeset_init(struct radeon_device *rdev);
2813extern void radeon_modeset_fini(struct radeon_device *rdev);
2814extern bool radeon_card_posted(struct radeon_device *rdev);
2815extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2816extern void radeon_update_display_priority(struct radeon_device *rdev);
2817extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2818extern void radeon_scratch_init(struct radeon_device *rdev);
2819extern void radeon_wb_fini(struct radeon_device *rdev);
2820extern int radeon_wb_init(struct radeon_device *rdev);
2821extern void radeon_wb_disable(struct radeon_device *rdev);
2822extern void radeon_surface_init(struct radeon_device *rdev);
2823extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2824extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2825extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2826extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2827extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2828extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2829 uint32_t flags);
2830extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2831extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
2832extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2833extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2834extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2835extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2836extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2837extern void radeon_program_register_sequence(struct radeon_device *rdev,
2838 const u32 *registers,
2839 const u32 array_size);
2840
2841/*
2842 * vm
2843 */
2844int radeon_vm_manager_init(struct radeon_device *rdev);
2845void radeon_vm_manager_fini(struct radeon_device *rdev);
2846int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2847void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2848struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
2849 struct radeon_vm *vm,
2850 struct list_head *head);
2851struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2852 struct radeon_vm *vm, int ring);
2853void radeon_vm_flush(struct radeon_device *rdev,
2854 struct radeon_vm *vm,
2855 int ring, struct radeon_fence *fence);
2856void radeon_vm_fence(struct radeon_device *rdev,
2857 struct radeon_vm *vm,
2858 struct radeon_fence *fence);
2859uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2860int radeon_vm_update_page_directory(struct radeon_device *rdev,
2861 struct radeon_vm *vm);
2862int radeon_vm_clear_freed(struct radeon_device *rdev,
2863 struct radeon_vm *vm);
2864int radeon_vm_clear_invalids(struct radeon_device *rdev,
2865 struct radeon_vm *vm);
2866int radeon_vm_bo_update(struct radeon_device *rdev,
2867 struct radeon_bo_va *bo_va,
2868 struct ttm_mem_reg *mem);
2869void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2870 struct radeon_bo *bo);
2871struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2872 struct radeon_bo *bo);
2873struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2874 struct radeon_vm *vm,
2875 struct radeon_bo *bo);
2876int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2877 struct radeon_bo_va *bo_va,
2878 uint64_t offset,
2879 uint32_t flags);
2880void radeon_vm_bo_rmv(struct radeon_device *rdev,
2881 struct radeon_bo_va *bo_va);
2882
2883/* audio */
2884void r600_audio_update_hdmi(struct work_struct *work);
2885struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2886struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2887void r600_audio_enable(struct radeon_device *rdev,
2888 struct r600_audio_pin *pin,
2889 u8 enable_mask);
2890void dce6_audio_enable(struct radeon_device *rdev,
2891 struct r600_audio_pin *pin,
2892 u8 enable_mask);
2893
2894/*
2895 * R600 vram scratch functions
2896 */
2897int r600_vram_scratch_init(struct radeon_device *rdev);
2898void r600_vram_scratch_fini(struct radeon_device *rdev);
2899
2900/*
2901 * r600 cs checking helper
2902 */
2903unsigned r600_mip_minify(unsigned size, unsigned level);
2904bool r600_fmt_is_valid_color(u32 format);
2905bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2906int r600_fmt_get_blocksize(u32 format);
2907int r600_fmt_get_nblocksx(u32 format, u32 w);
2908int r600_fmt_get_nblocksy(u32 format, u32 h);
2909
2910/*
2911 * r600 functions used by radeon_encoder.c
2912 */
2913struct radeon_hdmi_acr {
2914 u32 clock;
2915
2916 int n_32khz;
2917 int cts_32khz;
2918
2919 int n_44_1khz;
2920 int cts_44_1khz;
2921
2922 int n_48khz;
2923 int cts_48khz;
2924
2925};
2926
2927extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2928
2929extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2930 u32 tiling_pipe_num,
2931 u32 max_rb_num,
2932 u32 total_max_rb_num,
2933 u32 enabled_rb_mask);
2934
2935/*
2936 * evergreen functions used by radeon_encoder.c
2937 */
2938
2939extern int ni_init_microcode(struct radeon_device *rdev);
2940extern int ni_mc_load_microcode(struct radeon_device *rdev);
2941
2942/* radeon_acpi.c */
2943#if defined(CONFIG_ACPI)
2944extern int radeon_acpi_init(struct radeon_device *rdev);
2945extern void radeon_acpi_fini(struct radeon_device *rdev);
2946extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2947extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2948 u8 perf_req, bool advertise);
2949extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2950#else
2951static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2952static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2953#endif
2954
2955int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2956 struct radeon_cs_packet *pkt,
2957 unsigned idx);
2958bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2959void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2960 struct radeon_cs_packet *pkt);
2961int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2962 struct radeon_bo_list **cs_reloc,
2963 int nomm);
2964int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2965 uint32_t *vline_start_end,
2966 uint32_t *vline_status);
2967
2968#include "radeon_object.h"
2969
2970#endif