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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * core.h - DesignWare USB3 DRD Core Header
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#ifndef __DRIVERS_USB_DWC3_CORE_H
12#define __DRIVERS_USB_DWC3_CORE_H
13
14#include <linux/device.h>
15#include <linux/spinlock.h>
16#include <linux/ioport.h>
17#include <linux/list.h>
18#include <linux/bitops.h>
19#include <linux/dma-mapping.h>
20#include <linux/mm.h>
21#include <linux/debugfs.h>
22#include <linux/wait.h>
23#include <linux/workqueue.h>
24
25#include <linux/usb/ch9.h>
26#include <linux/usb/gadget.h>
27#include <linux/usb/otg.h>
28#include <linux/ulpi/interface.h>
29
30#include <linux/phy/phy.h>
31
32#define DWC3_MSG_MAX 500
33
34/* Global constants */
35#define DWC3_PULL_UP_TIMEOUT 500 /* ms */
36#define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */
37#define DWC3_EP0_SETUP_SIZE 512
38#define DWC3_ENDPOINTS_NUM 32
39#define DWC3_XHCI_RESOURCES_NUM 2
40
41#define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
42#define DWC3_EVENT_BUFFERS_SIZE 4096
43#define DWC3_EVENT_TYPE_MASK 0xfe
44
45#define DWC3_EVENT_TYPE_DEV 0
46#define DWC3_EVENT_TYPE_CARKIT 3
47#define DWC3_EVENT_TYPE_I2C 4
48
49#define DWC3_DEVICE_EVENT_DISCONNECT 0
50#define DWC3_DEVICE_EVENT_RESET 1
51#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
52#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
53#define DWC3_DEVICE_EVENT_WAKEUP 4
54#define DWC3_DEVICE_EVENT_HIBER_REQ 5
55#define DWC3_DEVICE_EVENT_EOPF 6
56#define DWC3_DEVICE_EVENT_SOF 7
57#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
58#define DWC3_DEVICE_EVENT_CMD_CMPL 10
59#define DWC3_DEVICE_EVENT_OVERFLOW 11
60
61/* Controller's role while using the OTG block */
62#define DWC3_OTG_ROLE_IDLE 0
63#define DWC3_OTG_ROLE_HOST 1
64#define DWC3_OTG_ROLE_DEVICE 2
65
66#define DWC3_GEVNTCOUNT_MASK 0xfffc
67#define DWC3_GEVNTCOUNT_EHB BIT(31)
68#define DWC3_GSNPSID_MASK 0xffff0000
69#define DWC3_GSNPSREV_MASK 0xffff
70
71/* DWC3 registers memory space boundries */
72#define DWC3_XHCI_REGS_START 0x0
73#define DWC3_XHCI_REGS_END 0x7fff
74#define DWC3_GLOBALS_REGS_START 0xc100
75#define DWC3_GLOBALS_REGS_END 0xc6ff
76#define DWC3_DEVICE_REGS_START 0xc700
77#define DWC3_DEVICE_REGS_END 0xcbff
78#define DWC3_OTG_REGS_START 0xcc00
79#define DWC3_OTG_REGS_END 0xccff
80
81/* Global Registers */
82#define DWC3_GSBUSCFG0 0xc100
83#define DWC3_GSBUSCFG1 0xc104
84#define DWC3_GTXTHRCFG 0xc108
85#define DWC3_GRXTHRCFG 0xc10c
86#define DWC3_GCTL 0xc110
87#define DWC3_GEVTEN 0xc114
88#define DWC3_GSTS 0xc118
89#define DWC3_GUCTL1 0xc11c
90#define DWC3_GSNPSID 0xc120
91#define DWC3_GGPIO 0xc124
92#define DWC3_GUID 0xc128
93#define DWC3_GUCTL 0xc12c
94#define DWC3_GBUSERRADDR0 0xc130
95#define DWC3_GBUSERRADDR1 0xc134
96#define DWC3_GPRTBIMAP0 0xc138
97#define DWC3_GPRTBIMAP1 0xc13c
98#define DWC3_GHWPARAMS0 0xc140
99#define DWC3_GHWPARAMS1 0xc144
100#define DWC3_GHWPARAMS2 0xc148
101#define DWC3_GHWPARAMS3 0xc14c
102#define DWC3_GHWPARAMS4 0xc150
103#define DWC3_GHWPARAMS5 0xc154
104#define DWC3_GHWPARAMS6 0xc158
105#define DWC3_GHWPARAMS7 0xc15c
106#define DWC3_GDBGFIFOSPACE 0xc160
107#define DWC3_GDBGLTSSM 0xc164
108#define DWC3_GDBGBMU 0xc16c
109#define DWC3_GDBGLSPMUX 0xc170
110#define DWC3_GDBGLSP 0xc174
111#define DWC3_GDBGEPINFO0 0xc178
112#define DWC3_GDBGEPINFO1 0xc17c
113#define DWC3_GPRTBIMAP_HS0 0xc180
114#define DWC3_GPRTBIMAP_HS1 0xc184
115#define DWC3_GPRTBIMAP_FS0 0xc188
116#define DWC3_GPRTBIMAP_FS1 0xc18c
117#define DWC3_GUCTL2 0xc19c
118
119#define DWC3_VER_NUMBER 0xc1a0
120#define DWC3_VER_TYPE 0xc1a4
121
122#define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04))
123#define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04))
124
125#define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04))
126
127#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04))
128
129#define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04))
130#define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04))
131
132#define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10))
133#define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10))
134#define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10))
135#define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10))
136
137#define DWC3_GHWPARAMS8 0xc600
138#define DWC3_GFLADJ 0xc630
139
140/* Device Registers */
141#define DWC3_DCFG 0xc700
142#define DWC3_DCTL 0xc704
143#define DWC3_DEVTEN 0xc708
144#define DWC3_DSTS 0xc70c
145#define DWC3_DGCMDPAR 0xc710
146#define DWC3_DGCMD 0xc714
147#define DWC3_DALEPENA 0xc720
148
149#define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10))
150#define DWC3_DEPCMDPAR2 0x00
151#define DWC3_DEPCMDPAR1 0x04
152#define DWC3_DEPCMDPAR0 0x08
153#define DWC3_DEPCMD 0x0c
154
155#define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4))
156
157/* OTG Registers */
158#define DWC3_OCFG 0xcc00
159#define DWC3_OCTL 0xcc04
160#define DWC3_OEVT 0xcc08
161#define DWC3_OEVTEN 0xcc0C
162#define DWC3_OSTS 0xcc10
163
164/* Bit fields */
165
166/* Global Debug Queue/FIFO Space Available Register */
167#define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
168#define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
169#define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
170
171#define DWC3_TXFIFOQ 0
172#define DWC3_RXFIFOQ 1
173#define DWC3_TXREQQ 2
174#define DWC3_RXREQQ 3
175#define DWC3_RXINFOQ 4
176#define DWC3_PSTATQ 5
177#define DWC3_DESCFETCHQ 6
178#define DWC3_EVENTQ 7
179#define DWC3_AUXEVENTQ 8
180
181/* Global RX Threshold Configuration Register */
182#define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
183#define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
184#define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
185
186/* Global RX Threshold Configuration Register for DWC_usb31 only */
187#define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16)
188#define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21)
189#define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26)
190#define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15)
191#define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
192#define DWC31_RXTHRNUMPKTSEL_PRD BIT(10)
193#define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
194#define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f)
195
196/* Global TX Threshold Configuration Register for DWC_usb31 only */
197#define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16)
198#define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21)
199#define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26)
200#define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15)
201#define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
202#define DWC31_TXTHRNUMPKTSEL_PRD BIT(10)
203#define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
204#define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f)
205
206/* Global Configuration Register */
207#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
208#define DWC3_GCTL_U2RSTECN BIT(16)
209#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
210#define DWC3_GCTL_CLK_BUS (0)
211#define DWC3_GCTL_CLK_PIPE (1)
212#define DWC3_GCTL_CLK_PIPEHALF (2)
213#define DWC3_GCTL_CLK_MASK (3)
214
215#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
216#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
217#define DWC3_GCTL_PRTCAP_HOST 1
218#define DWC3_GCTL_PRTCAP_DEVICE 2
219#define DWC3_GCTL_PRTCAP_OTG 3
220
221#define DWC3_GCTL_CORESOFTRESET BIT(11)
222#define DWC3_GCTL_SOFITPSYNC BIT(10)
223#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
224#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
225#define DWC3_GCTL_DISSCRAMBLE BIT(3)
226#define DWC3_GCTL_U2EXIT_LFPS BIT(2)
227#define DWC3_GCTL_GBLHIBERNATIONEN BIT(1)
228#define DWC3_GCTL_DSBLCLKGTNG BIT(0)
229
230/* Global User Control 1 Register */
231#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
232#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
233
234/* Global Status Register */
235#define DWC3_GSTS_OTG_IP BIT(10)
236#define DWC3_GSTS_BC_IP BIT(9)
237#define DWC3_GSTS_ADP_IP BIT(8)
238#define DWC3_GSTS_HOST_IP BIT(7)
239#define DWC3_GSTS_DEVICE_IP BIT(6)
240#define DWC3_GSTS_CSR_TIMEOUT BIT(5)
241#define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4)
242
243/* Global USB2 PHY Configuration Register */
244#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31)
245#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30)
246#define DWC3_GUSB2PHYCFG_SUSPHY BIT(6)
247#define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4)
248#define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8)
249#define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3)
250#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
251#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10)
252#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
253#define USBTRDTIM_UTMI_8_BIT 9
254#define USBTRDTIM_UTMI_16_BIT 5
255#define UTMI_PHYIF_16_BIT 1
256#define UTMI_PHYIF_8_BIT 0
257
258/* Global USB2 PHY Vendor Control Register */
259#define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25)
260#define DWC3_GUSB2PHYACC_BUSY BIT(23)
261#define DWC3_GUSB2PHYACC_WRITE BIT(22)
262#define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
263#define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
264#define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
265
266/* Global USB3 PIPE Control Register */
267#define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31)
268#define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29)
269#define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28)
270#define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27)
271#define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24)
272#define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
273#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
274#define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
275#define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18)
276#define DWC3_GUSB3PIPECTL_SUSPHY BIT(17)
277#define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9)
278#define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8)
279#define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
280#define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
281
282/* Global TX Fifo Size Register */
283#define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */
284#define DWC31_GTXFIFOSIZ_TXFDEF(n) ((n) & 0x7fff) /* DWC_usb31 only */
285#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
286#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
287
288/* Global Event Size Registers */
289#define DWC3_GEVNTSIZ_INTMASK BIT(31)
290#define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
291
292/* Global HWPARAMS0 Register */
293#define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3)
294#define DWC3_GHWPARAMS0_MODE_GADGET 0
295#define DWC3_GHWPARAMS0_MODE_HOST 1
296#define DWC3_GHWPARAMS0_MODE_DRD 2
297#define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7)
298#define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3)
299#define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff)
300#define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff)
301#define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff)
302
303/* Global HWPARAMS1 Register */
304#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
305#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
306#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
307#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
308#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
309#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
310
311/* Global HWPARAMS3 Register */
312#define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
313#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
314#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1
315#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */
316#define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
317#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
318#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
319#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
320#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
321#define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
322#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
323#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
324
325/* Global HWPARAMS4 Register */
326#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
327#define DWC3_MAX_HIBER_SCRATCHBUFS 15
328
329/* Global HWPARAMS6 Register */
330#define DWC3_GHWPARAMS6_BCSUPPORT BIT(14)
331#define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13)
332#define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12)
333#define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11)
334#define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10)
335#define DWC3_GHWPARAMS6_EN_FPGA BIT(7)
336
337/* Global HWPARAMS7 Register */
338#define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff)
339#define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff)
340
341/* Global Frame Length Adjustment Register */
342#define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7)
343#define DWC3_GFLADJ_30MHZ_MASK 0x3f
344
345/* Global User Control Register 2 */
346#define DWC3_GUCTL2_RST_ACTBITLATER BIT(14)
347
348/* Device Configuration Register */
349#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
350#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
351
352#define DWC3_DCFG_SPEED_MASK (7 << 0)
353#define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
354#define DWC3_DCFG_SUPERSPEED (4 << 0)
355#define DWC3_DCFG_HIGHSPEED (0 << 0)
356#define DWC3_DCFG_FULLSPEED BIT(0)
357#define DWC3_DCFG_LOWSPEED (2 << 0)
358
359#define DWC3_DCFG_NUMP_SHIFT 17
360#define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
361#define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT)
362#define DWC3_DCFG_LPM_CAP BIT(22)
363
364/* Device Control Register */
365#define DWC3_DCTL_RUN_STOP BIT(31)
366#define DWC3_DCTL_CSFTRST BIT(30)
367#define DWC3_DCTL_LSFTRST BIT(29)
368
369#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
370#define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
371
372#define DWC3_DCTL_APPL1RES BIT(23)
373
374/* These apply for core versions 1.87a and earlier */
375#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
376#define DWC3_DCTL_TRGTULST(n) ((n) << 17)
377#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
378#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
379#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
380#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
381#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
382
383/* These apply for core versions 1.94a and later */
384#define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
385#define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
386
387#define DWC3_DCTL_KEEP_CONNECT BIT(19)
388#define DWC3_DCTL_L1_HIBER_EN BIT(18)
389#define DWC3_DCTL_CRS BIT(17)
390#define DWC3_DCTL_CSS BIT(16)
391
392#define DWC3_DCTL_INITU2ENA BIT(12)
393#define DWC3_DCTL_ACCEPTU2ENA BIT(11)
394#define DWC3_DCTL_INITU1ENA BIT(10)
395#define DWC3_DCTL_ACCEPTU1ENA BIT(9)
396#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
397
398#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
399#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
400
401#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
402#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
403#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
404#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
405#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
406#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
407#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
408
409/* Device Event Enable Register */
410#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12)
411#define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11)
412#define DWC3_DEVTEN_CMDCMPLTEN BIT(10)
413#define DWC3_DEVTEN_ERRTICERREN BIT(9)
414#define DWC3_DEVTEN_SOFEN BIT(7)
415#define DWC3_DEVTEN_EOPFEN BIT(6)
416#define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5)
417#define DWC3_DEVTEN_WKUPEVTEN BIT(4)
418#define DWC3_DEVTEN_ULSTCNGEN BIT(3)
419#define DWC3_DEVTEN_CONNECTDONEEN BIT(2)
420#define DWC3_DEVTEN_USBRSTEN BIT(1)
421#define DWC3_DEVTEN_DISCONNEVTEN BIT(0)
422
423/* Device Status Register */
424#define DWC3_DSTS_DCNRD BIT(29)
425
426/* This applies for core versions 1.87a and earlier */
427#define DWC3_DSTS_PWRUPREQ BIT(24)
428
429/* These apply for core versions 1.94a and later */
430#define DWC3_DSTS_RSS BIT(25)
431#define DWC3_DSTS_SSS BIT(24)
432
433#define DWC3_DSTS_COREIDLE BIT(23)
434#define DWC3_DSTS_DEVCTRLHLT BIT(22)
435
436#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
437#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
438
439#define DWC3_DSTS_RXFIFOEMPTY BIT(17)
440
441#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
442#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
443
444#define DWC3_DSTS_CONNECTSPD (7 << 0)
445
446#define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
447#define DWC3_DSTS_SUPERSPEED (4 << 0)
448#define DWC3_DSTS_HIGHSPEED (0 << 0)
449#define DWC3_DSTS_FULLSPEED BIT(0)
450#define DWC3_DSTS_LOWSPEED (2 << 0)
451
452/* Device Generic Command Register */
453#define DWC3_DGCMD_SET_LMP 0x01
454#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
455#define DWC3_DGCMD_XMIT_FUNCTION 0x03
456
457/* These apply for core versions 1.94a and later */
458#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
459#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
460
461#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
462#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
463#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
464#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
465
466#define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
467#define DWC3_DGCMD_CMDACT BIT(10)
468#define DWC3_DGCMD_CMDIOC BIT(8)
469
470/* Device Generic Command Parameter Register */
471#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0)
472#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
473#define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
474#define DWC3_DGCMDPAR_TX_FIFO BIT(5)
475#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
476#define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0)
477
478/* Device Endpoint Command Register */
479#define DWC3_DEPCMD_PARAM_SHIFT 16
480#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
481#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
482#define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
483#define DWC3_DEPCMD_HIPRI_FORCERM BIT(11)
484#define DWC3_DEPCMD_CLEARPENDIN BIT(11)
485#define DWC3_DEPCMD_CMDACT BIT(10)
486#define DWC3_DEPCMD_CMDIOC BIT(8)
487
488#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
489#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
490#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
491#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
492#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
493#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
494/* This applies for core versions 1.90a and earlier */
495#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
496/* This applies for core versions 1.94a and later */
497#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
498#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
499#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
500
501#define DWC3_DEPCMD_CMD(x) ((x) & 0xf)
502
503/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
504#define DWC3_DALEPENA_EP(n) BIT(n)
505
506#define DWC3_DEPCMD_TYPE_CONTROL 0
507#define DWC3_DEPCMD_TYPE_ISOC 1
508#define DWC3_DEPCMD_TYPE_BULK 2
509#define DWC3_DEPCMD_TYPE_INTR 3
510
511#define DWC3_DEV_IMOD_COUNT_SHIFT 16
512#define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16)
513#define DWC3_DEV_IMOD_INTERVAL_SHIFT 0
514#define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0)
515
516/* OTG Configuration Register */
517#define DWC3_OCFG_DISPWRCUTTOFF BIT(5)
518#define DWC3_OCFG_HIBDISMASK BIT(4)
519#define DWC3_OCFG_SFTRSTMASK BIT(3)
520#define DWC3_OCFG_OTGVERSION BIT(2)
521#define DWC3_OCFG_HNPCAP BIT(1)
522#define DWC3_OCFG_SRPCAP BIT(0)
523
524/* OTG CTL Register */
525#define DWC3_OCTL_OTG3GOERR BIT(7)
526#define DWC3_OCTL_PERIMODE BIT(6)
527#define DWC3_OCTL_PRTPWRCTL BIT(5)
528#define DWC3_OCTL_HNPREQ BIT(4)
529#define DWC3_OCTL_SESREQ BIT(3)
530#define DWC3_OCTL_TERMSELIDPULSE BIT(2)
531#define DWC3_OCTL_DEVSETHNPEN BIT(1)
532#define DWC3_OCTL_HSTSETHNPEN BIT(0)
533
534/* OTG Event Register */
535#define DWC3_OEVT_DEVICEMODE BIT(31)
536#define DWC3_OEVT_XHCIRUNSTPSET BIT(27)
537#define DWC3_OEVT_DEVRUNSTPSET BIT(26)
538#define DWC3_OEVT_HIBENTRY BIT(25)
539#define DWC3_OEVT_CONIDSTSCHNG BIT(24)
540#define DWC3_OEVT_HRRCONFNOTIF BIT(23)
541#define DWC3_OEVT_HRRINITNOTIF BIT(22)
542#define DWC3_OEVT_ADEVIDLE BIT(21)
543#define DWC3_OEVT_ADEVBHOSTEND BIT(20)
544#define DWC3_OEVT_ADEVHOST BIT(19)
545#define DWC3_OEVT_ADEVHNPCHNG BIT(18)
546#define DWC3_OEVT_ADEVSRPDET BIT(17)
547#define DWC3_OEVT_ADEVSESSENDDET BIT(16)
548#define DWC3_OEVT_BDEVBHOSTEND BIT(11)
549#define DWC3_OEVT_BDEVHNPCHNG BIT(10)
550#define DWC3_OEVT_BDEVSESSVLDDET BIT(9)
551#define DWC3_OEVT_BDEVVBUSCHNG BIT(8)
552#define DWC3_OEVT_BSESSVLD BIT(3)
553#define DWC3_OEVT_HSTNEGSTS BIT(2)
554#define DWC3_OEVT_SESREQSTS BIT(1)
555#define DWC3_OEVT_ERROR BIT(0)
556
557/* OTG Event Enable Register */
558#define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27)
559#define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26)
560#define DWC3_OEVTEN_HIBENTRYEN BIT(25)
561#define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24)
562#define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23)
563#define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22)
564#define DWC3_OEVTEN_ADEVIDLEEN BIT(21)
565#define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20)
566#define DWC3_OEVTEN_ADEVHOSTEN BIT(19)
567#define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18)
568#define DWC3_OEVTEN_ADEVSRPDETEN BIT(17)
569#define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16)
570#define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11)
571#define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10)
572#define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9)
573#define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8)
574
575/* OTG Status Register */
576#define DWC3_OSTS_DEVRUNSTP BIT(13)
577#define DWC3_OSTS_XHCIRUNSTP BIT(12)
578#define DWC3_OSTS_PERIPHERALSTATE BIT(4)
579#define DWC3_OSTS_XHCIPRTPOWER BIT(3)
580#define DWC3_OSTS_BSESVLD BIT(2)
581#define DWC3_OSTS_VBUSVLD BIT(1)
582#define DWC3_OSTS_CONIDSTS BIT(0)
583
584/* Structures */
585
586struct dwc3_trb;
587
588/**
589 * struct dwc3_event_buffer - Software event buffer representation
590 * @buf: _THE_ buffer
591 * @cache: The buffer cache used in the threaded interrupt
592 * @length: size of this buffer
593 * @lpos: event offset
594 * @count: cache of last read event count register
595 * @flags: flags related to this event buffer
596 * @dma: dma_addr_t
597 * @dwc: pointer to DWC controller
598 */
599struct dwc3_event_buffer {
600 void *buf;
601 void *cache;
602 unsigned length;
603 unsigned int lpos;
604 unsigned int count;
605 unsigned int flags;
606
607#define DWC3_EVENT_PENDING BIT(0)
608
609 dma_addr_t dma;
610
611 struct dwc3 *dwc;
612};
613
614#define DWC3_EP_FLAG_STALLED BIT(0)
615#define DWC3_EP_FLAG_WEDGED BIT(1)
616
617#define DWC3_EP_DIRECTION_TX true
618#define DWC3_EP_DIRECTION_RX false
619
620#define DWC3_TRB_NUM 256
621
622/**
623 * struct dwc3_ep - device side endpoint representation
624 * @endpoint: usb endpoint
625 * @pending_list: list of pending requests for this endpoint
626 * @started_list: list of started requests on this endpoint
627 * @wait_end_transfer: wait_queue_head_t for waiting on End Transfer complete
628 * @lock: spinlock for endpoint request queue traversal
629 * @regs: pointer to first endpoint register
630 * @trb_pool: array of transaction buffers
631 * @trb_pool_dma: dma address of @trb_pool
632 * @trb_enqueue: enqueue 'pointer' into TRB array
633 * @trb_dequeue: dequeue 'pointer' into TRB array
634 * @dwc: pointer to DWC controller
635 * @saved_state: ep state saved during hibernation
636 * @flags: endpoint flags (wedged, stalled, ...)
637 * @number: endpoint number (1 - 15)
638 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
639 * @resource_index: Resource transfer index
640 * @frame_number: set to the frame number we want this transfer to start (ISOC)
641 * @interval: the interval on which the ISOC transfer is started
642 * @allocated_requests: number of requests allocated
643 * @queued_requests: number of requests queued for transfer
644 * @name: a human readable name e.g. ep1out-bulk
645 * @direction: true for TX, false for RX
646 * @stream_capable: true when streams are enabled
647 */
648struct dwc3_ep {
649 struct usb_ep endpoint;
650 struct list_head pending_list;
651 struct list_head started_list;
652
653 wait_queue_head_t wait_end_transfer;
654
655 spinlock_t lock;
656 void __iomem *regs;
657
658 struct dwc3_trb *trb_pool;
659 dma_addr_t trb_pool_dma;
660 struct dwc3 *dwc;
661
662 u32 saved_state;
663 unsigned flags;
664#define DWC3_EP_ENABLED BIT(0)
665#define DWC3_EP_STALL BIT(1)
666#define DWC3_EP_WEDGE BIT(2)
667#define DWC3_EP_BUSY BIT(4)
668#define DWC3_EP_PENDING_REQUEST BIT(5)
669#define DWC3_EP_MISSED_ISOC BIT(6)
670#define DWC3_EP_END_TRANSFER_PENDING BIT(7)
671#define DWC3_EP_TRANSFER_STARTED BIT(8)
672
673 /* This last one is specific to EP0 */
674#define DWC3_EP0_DIR_IN BIT(31)
675
676 /*
677 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will
678 * use a u8 type here. If anybody decides to increase number of TRBs to
679 * anything larger than 256 - I can't see why people would want to do
680 * this though - then this type needs to be changed.
681 *
682 * By using u8 types we ensure that our % operator when incrementing
683 * enqueue and dequeue get optimized away by the compiler.
684 */
685 u8 trb_enqueue;
686 u8 trb_dequeue;
687
688 u8 number;
689 u8 type;
690 u8 resource_index;
691 u32 allocated_requests;
692 u32 queued_requests;
693 u32 frame_number;
694 u32 interval;
695
696 char name[20];
697
698 unsigned direction:1;
699 unsigned stream_capable:1;
700};
701
702enum dwc3_phy {
703 DWC3_PHY_UNKNOWN = 0,
704 DWC3_PHY_USB3,
705 DWC3_PHY_USB2,
706};
707
708enum dwc3_ep0_next {
709 DWC3_EP0_UNKNOWN = 0,
710 DWC3_EP0_COMPLETE,
711 DWC3_EP0_NRDY_DATA,
712 DWC3_EP0_NRDY_STATUS,
713};
714
715enum dwc3_ep0_state {
716 EP0_UNCONNECTED = 0,
717 EP0_SETUP_PHASE,
718 EP0_DATA_PHASE,
719 EP0_STATUS_PHASE,
720};
721
722enum dwc3_link_state {
723 /* In SuperSpeed */
724 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
725 DWC3_LINK_STATE_U1 = 0x01,
726 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
727 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
728 DWC3_LINK_STATE_SS_DIS = 0x04,
729 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
730 DWC3_LINK_STATE_SS_INACT = 0x06,
731 DWC3_LINK_STATE_POLL = 0x07,
732 DWC3_LINK_STATE_RECOV = 0x08,
733 DWC3_LINK_STATE_HRESET = 0x09,
734 DWC3_LINK_STATE_CMPLY = 0x0a,
735 DWC3_LINK_STATE_LPBK = 0x0b,
736 DWC3_LINK_STATE_RESET = 0x0e,
737 DWC3_LINK_STATE_RESUME = 0x0f,
738 DWC3_LINK_STATE_MASK = 0x0f,
739};
740
741/* TRB Length, PCM and Status */
742#define DWC3_TRB_SIZE_MASK (0x00ffffff)
743#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
744#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
745#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
746
747#define DWC3_TRBSTS_OK 0
748#define DWC3_TRBSTS_MISSED_ISOC 1
749#define DWC3_TRBSTS_SETUP_PENDING 2
750#define DWC3_TRB_STS_XFER_IN_PROG 4
751
752/* TRB Control */
753#define DWC3_TRB_CTRL_HWO BIT(0)
754#define DWC3_TRB_CTRL_LST BIT(1)
755#define DWC3_TRB_CTRL_CHN BIT(2)
756#define DWC3_TRB_CTRL_CSP BIT(3)
757#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
758#define DWC3_TRB_CTRL_ISP_IMI BIT(10)
759#define DWC3_TRB_CTRL_IOC BIT(11)
760#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
761
762#define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4))
763#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
764#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
765#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
766#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
767#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
768#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
769#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
770#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
771
772/**
773 * struct dwc3_trb - transfer request block (hw format)
774 * @bpl: DW0-3
775 * @bph: DW4-7
776 * @size: DW8-B
777 * @ctrl: DWC-F
778 */
779struct dwc3_trb {
780 u32 bpl;
781 u32 bph;
782 u32 size;
783 u32 ctrl;
784} __packed;
785
786/**
787 * struct dwc3_hwparams - copy of HWPARAMS registers
788 * @hwparams0: GHWPARAMS0
789 * @hwparams1: GHWPARAMS1
790 * @hwparams2: GHWPARAMS2
791 * @hwparams3: GHWPARAMS3
792 * @hwparams4: GHWPARAMS4
793 * @hwparams5: GHWPARAMS5
794 * @hwparams6: GHWPARAMS6
795 * @hwparams7: GHWPARAMS7
796 * @hwparams8: GHWPARAMS8
797 */
798struct dwc3_hwparams {
799 u32 hwparams0;
800 u32 hwparams1;
801 u32 hwparams2;
802 u32 hwparams3;
803 u32 hwparams4;
804 u32 hwparams5;
805 u32 hwparams6;
806 u32 hwparams7;
807 u32 hwparams8;
808};
809
810/* HWPARAMS0 */
811#define DWC3_MODE(n) ((n) & 0x7)
812
813#define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
814
815/* HWPARAMS1 */
816#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
817
818/* HWPARAMS3 */
819#define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
820#define DWC3_NUM_EPS_MASK (0x3f << 12)
821#define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
822 (DWC3_NUM_EPS_MASK)) >> 12)
823#define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
824 (DWC3_NUM_IN_EPS_MASK)) >> 18)
825
826/* HWPARAMS7 */
827#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
828
829/**
830 * struct dwc3_request - representation of a transfer request
831 * @request: struct usb_request to be transferred
832 * @list: a list_head used for request queueing
833 * @dep: struct dwc3_ep owning this request
834 * @sg: pointer to first incomplete sg
835 * @num_pending_sgs: counter to pending sgs
836 * @remaining: amount of data remaining
837 * @epnum: endpoint number to which this request refers
838 * @trb: pointer to struct dwc3_trb
839 * @trb_dma: DMA address of @trb
840 * @unaligned: true for OUT endpoints with length not divisible by maxp
841 * @direction: IN or OUT direction flag
842 * @mapped: true when request has been dma-mapped
843 * @started: request is started
844 * @zero: wants a ZLP
845 */
846struct dwc3_request {
847 struct usb_request request;
848 struct list_head list;
849 struct dwc3_ep *dep;
850 struct scatterlist *sg;
851
852 unsigned num_pending_sgs;
853 unsigned remaining;
854 u8 epnum;
855 struct dwc3_trb *trb;
856 dma_addr_t trb_dma;
857
858 unsigned unaligned:1;
859 unsigned direction:1;
860 unsigned mapped:1;
861 unsigned started:1;
862 unsigned zero:1;
863};
864
865/*
866 * struct dwc3_scratchpad_array - hibernation scratchpad array
867 * (format defined by hw)
868 */
869struct dwc3_scratchpad_array {
870 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
871};
872
873/**
874 * struct dwc3 - representation of our controller
875 * @drd_work: workqueue used for role swapping
876 * @ep0_trb: trb which is used for the ctrl_req
877 * @bounce: address of bounce buffer
878 * @scratchbuf: address of scratch buffer
879 * @setup_buf: used while precessing STD USB requests
880 * @ep0_trb_addr: dma address of @ep0_trb
881 * @bounce_addr: dma address of @bounce
882 * @ep0_usb_req: dummy req used while handling STD USB requests
883 * @scratch_addr: dma address of scratchbuf
884 * @ep0_in_setup: one control transfer is completed and enter setup phase
885 * @lock: for synchronizing
886 * @dev: pointer to our struct device
887 * @sysdev: pointer to the DMA-capable device
888 * @xhci: pointer to our xHCI child
889 * @xhci_resources: struct resources for our @xhci child
890 * @ev_buf: struct dwc3_event_buffer pointer
891 * @eps: endpoint array
892 * @gadget: device side representation of the peripheral controller
893 * @gadget_driver: pointer to the gadget driver
894 * @regs: base address for our registers
895 * @regs_size: address space size
896 * @fladj: frame length adjustment
897 * @irq_gadget: peripheral controller's IRQ number
898 * @otg_irq: IRQ number for OTG IRQs
899 * @current_otg_role: current role of operation while using the OTG block
900 * @desired_otg_role: desired role of operation while using the OTG block
901 * @otg_restart_host: flag that OTG controller needs to restart host
902 * @nr_scratch: number of scratch buffers
903 * @u1u2: only used on revisions <1.83a for workaround
904 * @maximum_speed: maximum speed requested (mainly for testing purposes)
905 * @revision: revision register contents
906 * @dr_mode: requested mode of operation
907 * @current_dr_role: current role of operation when in dual-role mode
908 * @desired_dr_role: desired role of operation when in dual-role mode
909 * @edev: extcon handle
910 * @edev_nb: extcon notifier
911 * @hsphy_mode: UTMI phy mode, one of following:
912 * - USBPHY_INTERFACE_MODE_UTMI
913 * - USBPHY_INTERFACE_MODE_UTMIW
914 * @usb2_phy: pointer to USB2 PHY
915 * @usb3_phy: pointer to USB3 PHY
916 * @usb2_generic_phy: pointer to USB2 PHY
917 * @usb3_generic_phy: pointer to USB3 PHY
918 * @phys_ready: flag to indicate that PHYs are ready
919 * @ulpi: pointer to ulpi interface
920 * @ulpi_ready: flag to indicate that ULPI is initialized
921 * @u2sel: parameter from Set SEL request.
922 * @u2pel: parameter from Set SEL request.
923 * @u1sel: parameter from Set SEL request.
924 * @u1pel: parameter from Set SEL request.
925 * @num_eps: number of endpoints
926 * @ep0_next_event: hold the next expected event
927 * @ep0state: state of endpoint zero
928 * @link_state: link state
929 * @speed: device speed (super, high, full, low)
930 * @hwparams: copy of hwparams registers
931 * @root: debugfs root folder pointer
932 * @regset: debugfs pointer to regdump file
933 * @test_mode: true when we're entering a USB test mode
934 * @test_mode_nr: test feature selector
935 * @lpm_nyet_threshold: LPM NYET response threshold
936 * @hird_threshold: HIRD threshold
937 * @rx_thr_num_pkt_prd: periodic ESS receive packet count
938 * @rx_max_burst_prd: max periodic ESS receive burst size
939 * @tx_thr_num_pkt_prd: periodic ESS transmit packet count
940 * @tx_max_burst_prd: max periodic ESS transmit burst size
941 * @hsphy_interface: "utmi" or "ulpi"
942 * @connected: true when we're connected to a host, false otherwise
943 * @delayed_status: true when gadget driver asks for delayed status
944 * @ep0_bounced: true when we used bounce buffer
945 * @ep0_expect_in: true when we expect a DATA IN transfer
946 * @has_hibernation: true when dwc3 was configured with Hibernation
947 * @sysdev_is_parent: true when dwc3 device has a parent driver
948 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
949 * there's now way for software to detect this in runtime.
950 * @is_utmi_l1_suspend: the core asserts output signal
951 * 0 - utmi_sleep_n
952 * 1 - utmi_l1_suspend_n
953 * @is_fpga: true when we are using the FPGA board
954 * @pending_events: true when we have pending IRQs to be handled
955 * @pullups_connected: true when Run/Stop bit is set
956 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
957 * @three_stage_setup: set if we perform a three phase setup
958 * @usb3_lpm_capable: set if hadrware supports Link Power Management
959 * @disable_scramble_quirk: set if we enable the disable scramble quirk
960 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
961 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
962 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
963 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
964 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
965 * @lfps_filter_quirk: set if we enable LFPS filter quirk
966 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
967 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
968 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
969 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
970 * disabling the suspend signal to the PHY.
971 * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3
972 * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
973 * in GUSB2PHYCFG, specify that USB2 PHY doesn't
974 * provide a free-running PHY clock.
975 * @dis_del_phy_power_chg_quirk: set if we disable delay phy power
976 * change quirk.
977 * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
978 * check during HS transmit.
979 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
980 * @tx_de_emphasis: Tx de-emphasis value
981 * 0 - -6dB de-emphasis
982 * 1 - -3.5dB de-emphasis
983 * 2 - No de-emphasis
984 * 3 - Reserved
985 * @dis_metastability_quirk: set to disable metastability quirk.
986 * @imod_interval: set the interrupt moderation interval in 250ns
987 * increments or 0 to disable.
988 */
989struct dwc3 {
990 struct work_struct drd_work;
991 struct dwc3_trb *ep0_trb;
992 void *bounce;
993 void *scratchbuf;
994 u8 *setup_buf;
995 dma_addr_t ep0_trb_addr;
996 dma_addr_t bounce_addr;
997 dma_addr_t scratch_addr;
998 struct dwc3_request ep0_usb_req;
999 struct completion ep0_in_setup;
1000
1001 /* device lock */
1002 spinlock_t lock;
1003
1004 struct device *dev;
1005 struct device *sysdev;
1006
1007 struct platform_device *xhci;
1008 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
1009
1010 struct dwc3_event_buffer *ev_buf;
1011 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
1012
1013 struct usb_gadget gadget;
1014 struct usb_gadget_driver *gadget_driver;
1015
1016 struct usb_phy *usb2_phy;
1017 struct usb_phy *usb3_phy;
1018
1019 struct phy *usb2_generic_phy;
1020 struct phy *usb3_generic_phy;
1021
1022 bool phys_ready;
1023
1024 struct ulpi *ulpi;
1025 bool ulpi_ready;
1026
1027 void __iomem *regs;
1028 size_t regs_size;
1029
1030 enum usb_dr_mode dr_mode;
1031 u32 current_dr_role;
1032 u32 desired_dr_role;
1033 struct extcon_dev *edev;
1034 struct notifier_block edev_nb;
1035 enum usb_phy_interface hsphy_mode;
1036
1037 u32 fladj;
1038 u32 irq_gadget;
1039 u32 otg_irq;
1040 u32 current_otg_role;
1041 u32 desired_otg_role;
1042 bool otg_restart_host;
1043 u32 nr_scratch;
1044 u32 u1u2;
1045 u32 maximum_speed;
1046
1047 /*
1048 * All 3.1 IP version constants are greater than the 3.0 IP
1049 * version constants. This works for most version checks in
1050 * dwc3. However, in the future, this may not apply as
1051 * features may be developed on newer versions of the 3.0 IP
1052 * that are not in the 3.1 IP.
1053 */
1054 u32 revision;
1055
1056#define DWC3_REVISION_173A 0x5533173a
1057#define DWC3_REVISION_175A 0x5533175a
1058#define DWC3_REVISION_180A 0x5533180a
1059#define DWC3_REVISION_183A 0x5533183a
1060#define DWC3_REVISION_185A 0x5533185a
1061#define DWC3_REVISION_187A 0x5533187a
1062#define DWC3_REVISION_188A 0x5533188a
1063#define DWC3_REVISION_190A 0x5533190a
1064#define DWC3_REVISION_194A 0x5533194a
1065#define DWC3_REVISION_200A 0x5533200a
1066#define DWC3_REVISION_202A 0x5533202a
1067#define DWC3_REVISION_210A 0x5533210a
1068#define DWC3_REVISION_220A 0x5533220a
1069#define DWC3_REVISION_230A 0x5533230a
1070#define DWC3_REVISION_240A 0x5533240a
1071#define DWC3_REVISION_250A 0x5533250a
1072#define DWC3_REVISION_260A 0x5533260a
1073#define DWC3_REVISION_270A 0x5533270a
1074#define DWC3_REVISION_280A 0x5533280a
1075#define DWC3_REVISION_290A 0x5533290a
1076#define DWC3_REVISION_300A 0x5533300a
1077#define DWC3_REVISION_310A 0x5533310a
1078
1079/*
1080 * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really
1081 * just so dwc31 revisions are always larger than dwc3.
1082 */
1083#define DWC3_REVISION_IS_DWC31 0x80000000
1084#define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_DWC31)
1085#define DWC3_USB31_REVISION_120A (0x3132302a | DWC3_REVISION_IS_DWC31)
1086
1087 enum dwc3_ep0_next ep0_next_event;
1088 enum dwc3_ep0_state ep0state;
1089 enum dwc3_link_state link_state;
1090
1091 u16 u2sel;
1092 u16 u2pel;
1093 u8 u1sel;
1094 u8 u1pel;
1095
1096 u8 speed;
1097
1098 u8 num_eps;
1099
1100 struct dwc3_hwparams hwparams;
1101 struct dentry *root;
1102 struct debugfs_regset32 *regset;
1103
1104 u8 test_mode;
1105 u8 test_mode_nr;
1106 u8 lpm_nyet_threshold;
1107 u8 hird_threshold;
1108 u8 rx_thr_num_pkt_prd;
1109 u8 rx_max_burst_prd;
1110 u8 tx_thr_num_pkt_prd;
1111 u8 tx_max_burst_prd;
1112
1113 const char *hsphy_interface;
1114
1115 unsigned connected:1;
1116 unsigned delayed_status:1;
1117 unsigned ep0_bounced:1;
1118 unsigned ep0_expect_in:1;
1119 unsigned has_hibernation:1;
1120 unsigned sysdev_is_parent:1;
1121 unsigned has_lpm_erratum:1;
1122 unsigned is_utmi_l1_suspend:1;
1123 unsigned is_fpga:1;
1124 unsigned pending_events:1;
1125 unsigned pullups_connected:1;
1126 unsigned setup_packet_pending:1;
1127 unsigned three_stage_setup:1;
1128 unsigned usb3_lpm_capable:1;
1129
1130 unsigned disable_scramble_quirk:1;
1131 unsigned u2exit_lfps_quirk:1;
1132 unsigned u2ss_inp3_quirk:1;
1133 unsigned req_p1p2p3_quirk:1;
1134 unsigned del_p1p2p3_quirk:1;
1135 unsigned del_phy_power_chg_quirk:1;
1136 unsigned lfps_filter_quirk:1;
1137 unsigned rx_detect_poll_quirk:1;
1138 unsigned dis_u3_susphy_quirk:1;
1139 unsigned dis_u2_susphy_quirk:1;
1140 unsigned dis_enblslpm_quirk:1;
1141 unsigned dis_rxdet_inp3_quirk:1;
1142 unsigned dis_u2_freeclk_exists_quirk:1;
1143 unsigned dis_del_phy_power_chg_quirk:1;
1144 unsigned dis_tx_ipgap_linecheck_quirk:1;
1145
1146 unsigned tx_de_emphasis_quirk:1;
1147 unsigned tx_de_emphasis:2;
1148
1149 unsigned dis_metastability_quirk:1;
1150
1151 u16 imod_interval;
1152};
1153
1154#define work_to_dwc(w) (container_of((w), struct dwc3, drd_work))
1155
1156/* -------------------------------------------------------------------------- */
1157
1158struct dwc3_event_type {
1159 u32 is_devspec:1;
1160 u32 type:7;
1161 u32 reserved8_31:24;
1162} __packed;
1163
1164#define DWC3_DEPEVT_XFERCOMPLETE 0x01
1165#define DWC3_DEPEVT_XFERINPROGRESS 0x02
1166#define DWC3_DEPEVT_XFERNOTREADY 0x03
1167#define DWC3_DEPEVT_RXTXFIFOEVT 0x04
1168#define DWC3_DEPEVT_STREAMEVT 0x06
1169#define DWC3_DEPEVT_EPCMDCMPLT 0x07
1170
1171/**
1172 * struct dwc3_event_depvt - Device Endpoint Events
1173 * @one_bit: indicates this is an endpoint event (not used)
1174 * @endpoint_number: number of the endpoint
1175 * @endpoint_event: The event we have:
1176 * 0x00 - Reserved
1177 * 0x01 - XferComplete
1178 * 0x02 - XferInProgress
1179 * 0x03 - XferNotReady
1180 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
1181 * 0x05 - Reserved
1182 * 0x06 - StreamEvt
1183 * 0x07 - EPCmdCmplt
1184 * @reserved11_10: Reserved, don't use.
1185 * @status: Indicates the status of the event. Refer to databook for
1186 * more information.
1187 * @parameters: Parameters of the current event. Refer to databook for
1188 * more information.
1189 */
1190struct dwc3_event_depevt {
1191 u32 one_bit:1;
1192 u32 endpoint_number:5;
1193 u32 endpoint_event:4;
1194 u32 reserved11_10:2;
1195 u32 status:4;
1196
1197/* Within XferNotReady */
1198#define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3)
1199
1200/* Within XferComplete */
1201#define DEPEVT_STATUS_BUSERR BIT(0)
1202#define DEPEVT_STATUS_SHORT BIT(1)
1203#define DEPEVT_STATUS_IOC BIT(2)
1204#define DEPEVT_STATUS_LST BIT(3)
1205
1206/* Stream event only */
1207#define DEPEVT_STREAMEVT_FOUND 1
1208#define DEPEVT_STREAMEVT_NOTFOUND 2
1209
1210/* Control-only Status */
1211#define DEPEVT_STATUS_CONTROL_DATA 1
1212#define DEPEVT_STATUS_CONTROL_STATUS 2
1213#define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3)
1214
1215/* In response to Start Transfer */
1216#define DEPEVT_TRANSFER_NO_RESOURCE 1
1217#define DEPEVT_TRANSFER_BUS_EXPIRY 2
1218
1219 u32 parameters:16;
1220
1221/* For Command Complete Events */
1222#define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8)
1223} __packed;
1224
1225/**
1226 * struct dwc3_event_devt - Device Events
1227 * @one_bit: indicates this is a non-endpoint event (not used)
1228 * @device_event: indicates it's a device event. Should read as 0x00
1229 * @type: indicates the type of device event.
1230 * 0 - DisconnEvt
1231 * 1 - USBRst
1232 * 2 - ConnectDone
1233 * 3 - ULStChng
1234 * 4 - WkUpEvt
1235 * 5 - Reserved
1236 * 6 - EOPF
1237 * 7 - SOF
1238 * 8 - Reserved
1239 * 9 - ErrticErr
1240 * 10 - CmdCmplt
1241 * 11 - EvntOverflow
1242 * 12 - VndrDevTstRcved
1243 * @reserved15_12: Reserved, not used
1244 * @event_info: Information about this event
1245 * @reserved31_25: Reserved, not used
1246 */
1247struct dwc3_event_devt {
1248 u32 one_bit:1;
1249 u32 device_event:7;
1250 u32 type:4;
1251 u32 reserved15_12:4;
1252 u32 event_info:9;
1253 u32 reserved31_25:7;
1254} __packed;
1255
1256/**
1257 * struct dwc3_event_gevt - Other Core Events
1258 * @one_bit: indicates this is a non-endpoint event (not used)
1259 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1260 * @phy_port_number: self-explanatory
1261 * @reserved31_12: Reserved, not used.
1262 */
1263struct dwc3_event_gevt {
1264 u32 one_bit:1;
1265 u32 device_event:7;
1266 u32 phy_port_number:4;
1267 u32 reserved31_12:20;
1268} __packed;
1269
1270/**
1271 * union dwc3_event - representation of Event Buffer contents
1272 * @raw: raw 32-bit event
1273 * @type: the type of the event
1274 * @depevt: Device Endpoint Event
1275 * @devt: Device Event
1276 * @gevt: Global Event
1277 */
1278union dwc3_event {
1279 u32 raw;
1280 struct dwc3_event_type type;
1281 struct dwc3_event_depevt depevt;
1282 struct dwc3_event_devt devt;
1283 struct dwc3_event_gevt gevt;
1284};
1285
1286/**
1287 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1288 * parameters
1289 * @param2: third parameter
1290 * @param1: second parameter
1291 * @param0: first parameter
1292 */
1293struct dwc3_gadget_ep_cmd_params {
1294 u32 param2;
1295 u32 param1;
1296 u32 param0;
1297};
1298
1299/*
1300 * DWC3 Features to be used as Driver Data
1301 */
1302
1303#define DWC3_HAS_PERIPHERAL BIT(0)
1304#define DWC3_HAS_XHCI BIT(1)
1305#define DWC3_HAS_OTG BIT(3)
1306
1307/* prototypes */
1308void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode);
1309void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1310u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
1311
1312/* check whether we are on the DWC_usb3 core */
1313static inline bool dwc3_is_usb3(struct dwc3 *dwc)
1314{
1315 return !(dwc->revision & DWC3_REVISION_IS_DWC31);
1316}
1317
1318/* check whether we are on the DWC_usb31 core */
1319static inline bool dwc3_is_usb31(struct dwc3 *dwc)
1320{
1321 return !!(dwc->revision & DWC3_REVISION_IS_DWC31);
1322}
1323
1324bool dwc3_has_imod(struct dwc3 *dwc);
1325
1326int dwc3_event_buffers_setup(struct dwc3 *dwc);
1327void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
1328
1329#if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1330int dwc3_host_init(struct dwc3 *dwc);
1331void dwc3_host_exit(struct dwc3 *dwc);
1332#else
1333static inline int dwc3_host_init(struct dwc3 *dwc)
1334{ return 0; }
1335static inline void dwc3_host_exit(struct dwc3 *dwc)
1336{ }
1337#endif
1338
1339#if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1340int dwc3_gadget_init(struct dwc3 *dwc);
1341void dwc3_gadget_exit(struct dwc3 *dwc);
1342int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1343int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1344int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1345int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1346 struct dwc3_gadget_ep_cmd_params *params);
1347int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1348#else
1349static inline int dwc3_gadget_init(struct dwc3 *dwc)
1350{ return 0; }
1351static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1352{ }
1353static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1354{ return 0; }
1355static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1356{ return 0; }
1357static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1358 enum dwc3_link_state state)
1359{ return 0; }
1360
1361static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1362 struct dwc3_gadget_ep_cmd_params *params)
1363{ return 0; }
1364static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1365 int cmd, u32 param)
1366{ return 0; }
1367#endif
1368
1369#if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1370int dwc3_drd_init(struct dwc3 *dwc);
1371void dwc3_drd_exit(struct dwc3 *dwc);
1372void dwc3_otg_init(struct dwc3 *dwc);
1373void dwc3_otg_exit(struct dwc3 *dwc);
1374void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus);
1375void dwc3_otg_host_init(struct dwc3 *dwc);
1376#else
1377static inline int dwc3_drd_init(struct dwc3 *dwc)
1378{ return 0; }
1379static inline void dwc3_drd_exit(struct dwc3 *dwc)
1380{ }
1381static inline void dwc3_otg_init(struct dwc3 *dwc)
1382{ }
1383static inline void dwc3_otg_exit(struct dwc3 *dwc)
1384{ }
1385static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
1386{ }
1387static inline void dwc3_otg_host_init(struct dwc3 *dwc)
1388{ }
1389#endif
1390
1391/* power management interface */
1392#if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1393int dwc3_gadget_suspend(struct dwc3 *dwc);
1394int dwc3_gadget_resume(struct dwc3 *dwc);
1395void dwc3_gadget_process_pending_events(struct dwc3 *dwc);
1396#else
1397static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1398{
1399 return 0;
1400}
1401
1402static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1403{
1404 return 0;
1405}
1406
1407static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
1408{
1409}
1410#endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1411
1412#if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1413int dwc3_ulpi_init(struct dwc3 *dwc);
1414void dwc3_ulpi_exit(struct dwc3 *dwc);
1415#else
1416static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1417{ return 0; }
1418static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1419{ }
1420#endif
1421
1422#endif /* __DRIVERS_USB_DWC3_CORE_H */