Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * core.h - DesignWare USB3 DRD Core Header
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#ifndef __DRIVERS_USB_DWC3_CORE_H
12#define __DRIVERS_USB_DWC3_CORE_H
13
14#include <linux/device.h>
15#include <linux/spinlock.h>
16#include <linux/ioport.h>
17#include <linux/list.h>
18#include <linux/bitops.h>
19#include <linux/dma-mapping.h>
20#include <linux/mm.h>
21#include <linux/debugfs.h>
22#include <linux/wait.h>
23#include <linux/workqueue.h>
24
25#include <linux/usb/ch9.h>
26#include <linux/usb/gadget.h>
27#include <linux/usb/otg.h>
28#include <linux/ulpi/interface.h>
29
30#include <linux/phy/phy.h>
31
32#define DWC3_MSG_MAX 500
33
34/* Global constants */
35#define DWC3_PULL_UP_TIMEOUT 500 /* ms */
36#define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */
37#define DWC3_EP0_SETUP_SIZE 512
38#define DWC3_ENDPOINTS_NUM 32
39#define DWC3_XHCI_RESOURCES_NUM 2
40#define DWC3_ISOC_MAX_RETRIES 5
41
42#define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
43#define DWC3_EVENT_BUFFERS_SIZE 4096
44#define DWC3_EVENT_TYPE_MASK 0xfe
45
46#define DWC3_EVENT_TYPE_DEV 0
47#define DWC3_EVENT_TYPE_CARKIT 3
48#define DWC3_EVENT_TYPE_I2C 4
49
50#define DWC3_DEVICE_EVENT_DISCONNECT 0
51#define DWC3_DEVICE_EVENT_RESET 1
52#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
53#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
54#define DWC3_DEVICE_EVENT_WAKEUP 4
55#define DWC3_DEVICE_EVENT_HIBER_REQ 5
56#define DWC3_DEVICE_EVENT_EOPF 6
57#define DWC3_DEVICE_EVENT_SOF 7
58#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
59#define DWC3_DEVICE_EVENT_CMD_CMPL 10
60#define DWC3_DEVICE_EVENT_OVERFLOW 11
61
62/* Controller's role while using the OTG block */
63#define DWC3_OTG_ROLE_IDLE 0
64#define DWC3_OTG_ROLE_HOST 1
65#define DWC3_OTG_ROLE_DEVICE 2
66
67#define DWC3_GEVNTCOUNT_MASK 0xfffc
68#define DWC3_GEVNTCOUNT_EHB BIT(31)
69#define DWC3_GSNPSID_MASK 0xffff0000
70#define DWC3_GSNPSREV_MASK 0xffff
71
72/* DWC3 registers memory space boundries */
73#define DWC3_XHCI_REGS_START 0x0
74#define DWC3_XHCI_REGS_END 0x7fff
75#define DWC3_GLOBALS_REGS_START 0xc100
76#define DWC3_GLOBALS_REGS_END 0xc6ff
77#define DWC3_DEVICE_REGS_START 0xc700
78#define DWC3_DEVICE_REGS_END 0xcbff
79#define DWC3_OTG_REGS_START 0xcc00
80#define DWC3_OTG_REGS_END 0xccff
81
82/* Global Registers */
83#define DWC3_GSBUSCFG0 0xc100
84#define DWC3_GSBUSCFG1 0xc104
85#define DWC3_GTXTHRCFG 0xc108
86#define DWC3_GRXTHRCFG 0xc10c
87#define DWC3_GCTL 0xc110
88#define DWC3_GEVTEN 0xc114
89#define DWC3_GSTS 0xc118
90#define DWC3_GUCTL1 0xc11c
91#define DWC3_GSNPSID 0xc120
92#define DWC3_GGPIO 0xc124
93#define DWC3_GUID 0xc128
94#define DWC3_GUCTL 0xc12c
95#define DWC3_GBUSERRADDR0 0xc130
96#define DWC3_GBUSERRADDR1 0xc134
97#define DWC3_GPRTBIMAP0 0xc138
98#define DWC3_GPRTBIMAP1 0xc13c
99#define DWC3_GHWPARAMS0 0xc140
100#define DWC3_GHWPARAMS1 0xc144
101#define DWC3_GHWPARAMS2 0xc148
102#define DWC3_GHWPARAMS3 0xc14c
103#define DWC3_GHWPARAMS4 0xc150
104#define DWC3_GHWPARAMS5 0xc154
105#define DWC3_GHWPARAMS6 0xc158
106#define DWC3_GHWPARAMS7 0xc15c
107#define DWC3_GDBGFIFOSPACE 0xc160
108#define DWC3_GDBGLTSSM 0xc164
109#define DWC3_GDBGBMU 0xc16c
110#define DWC3_GDBGLSPMUX 0xc170
111#define DWC3_GDBGLSP 0xc174
112#define DWC3_GDBGEPINFO0 0xc178
113#define DWC3_GDBGEPINFO1 0xc17c
114#define DWC3_GPRTBIMAP_HS0 0xc180
115#define DWC3_GPRTBIMAP_HS1 0xc184
116#define DWC3_GPRTBIMAP_FS0 0xc188
117#define DWC3_GPRTBIMAP_FS1 0xc18c
118#define DWC3_GUCTL2 0xc19c
119
120#define DWC3_VER_NUMBER 0xc1a0
121#define DWC3_VER_TYPE 0xc1a4
122
123#define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04))
124#define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04))
125
126#define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04))
127
128#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04))
129
130#define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04))
131#define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04))
132
133#define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10))
134#define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10))
135#define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10))
136#define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10))
137
138#define DWC3_GHWPARAMS8 0xc600
139#define DWC3_GFLADJ 0xc630
140
141/* Device Registers */
142#define DWC3_DCFG 0xc700
143#define DWC3_DCTL 0xc704
144#define DWC3_DEVTEN 0xc708
145#define DWC3_DSTS 0xc70c
146#define DWC3_DGCMDPAR 0xc710
147#define DWC3_DGCMD 0xc714
148#define DWC3_DALEPENA 0xc720
149
150#define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10))
151#define DWC3_DEPCMDPAR2 0x00
152#define DWC3_DEPCMDPAR1 0x04
153#define DWC3_DEPCMDPAR0 0x08
154#define DWC3_DEPCMD 0x0c
155
156#define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4))
157
158/* OTG Registers */
159#define DWC3_OCFG 0xcc00
160#define DWC3_OCTL 0xcc04
161#define DWC3_OEVT 0xcc08
162#define DWC3_OEVTEN 0xcc0C
163#define DWC3_OSTS 0xcc10
164
165/* Bit fields */
166
167/* Global SoC Bus Configuration INCRx Register 0 */
168#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
169#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
170#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
171#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */
172#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */
173#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */
174#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */
175#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
176#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
177
178/* Global Debug LSP MUX Select */
179#define DWC3_GDBGLSPMUX_ENDBC BIT(15) /* Host only */
180#define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff)
181#define DWC3_GDBGLSPMUX_DEVSELECT(n) (((n) & 0xf) << 4)
182#define DWC3_GDBGLSPMUX_EPSELECT(n) ((n) & 0xf)
183
184/* Global Debug Queue/FIFO Space Available Register */
185#define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
186#define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
187#define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
188
189#define DWC3_TXFIFO 0
190#define DWC3_RXFIFO 1
191#define DWC3_TXREQQ 2
192#define DWC3_RXREQQ 3
193#define DWC3_RXINFOQ 4
194#define DWC3_PSTATQ 5
195#define DWC3_DESCFETCHQ 6
196#define DWC3_EVENTQ 7
197#define DWC3_AUXEVENTQ 8
198
199/* Global RX Threshold Configuration Register */
200#define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
201#define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
202#define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
203
204/* Global RX Threshold Configuration Register for DWC_usb31 only */
205#define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16)
206#define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21)
207#define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26)
208#define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15)
209#define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
210#define DWC31_RXTHRNUMPKTSEL_PRD BIT(10)
211#define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
212#define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f)
213
214/* Global TX Threshold Configuration Register for DWC_usb31 only */
215#define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16)
216#define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21)
217#define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26)
218#define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15)
219#define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
220#define DWC31_TXTHRNUMPKTSEL_PRD BIT(10)
221#define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
222#define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f)
223
224/* Global Configuration Register */
225#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
226#define DWC3_GCTL_U2RSTECN BIT(16)
227#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
228#define DWC3_GCTL_CLK_BUS (0)
229#define DWC3_GCTL_CLK_PIPE (1)
230#define DWC3_GCTL_CLK_PIPEHALF (2)
231#define DWC3_GCTL_CLK_MASK (3)
232
233#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
234#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
235#define DWC3_GCTL_PRTCAP_HOST 1
236#define DWC3_GCTL_PRTCAP_DEVICE 2
237#define DWC3_GCTL_PRTCAP_OTG 3
238
239#define DWC3_GCTL_CORESOFTRESET BIT(11)
240#define DWC3_GCTL_SOFITPSYNC BIT(10)
241#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
242#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
243#define DWC3_GCTL_DISSCRAMBLE BIT(3)
244#define DWC3_GCTL_U2EXIT_LFPS BIT(2)
245#define DWC3_GCTL_GBLHIBERNATIONEN BIT(1)
246#define DWC3_GCTL_DSBLCLKGTNG BIT(0)
247
248/* Global User Control Register */
249#define DWC3_GUCTL_HSTINAUTORETRY BIT(14)
250
251/* Global User Control 1 Register */
252#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
253#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
254
255/* Global Status Register */
256#define DWC3_GSTS_OTG_IP BIT(10)
257#define DWC3_GSTS_BC_IP BIT(9)
258#define DWC3_GSTS_ADP_IP BIT(8)
259#define DWC3_GSTS_HOST_IP BIT(7)
260#define DWC3_GSTS_DEVICE_IP BIT(6)
261#define DWC3_GSTS_CSR_TIMEOUT BIT(5)
262#define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4)
263#define DWC3_GSTS_CURMOD(n) ((n) & 0x3)
264#define DWC3_GSTS_CURMOD_DEVICE 0
265#define DWC3_GSTS_CURMOD_HOST 1
266
267/* Global USB2 PHY Configuration Register */
268#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31)
269#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30)
270#define DWC3_GUSB2PHYCFG_SUSPHY BIT(6)
271#define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4)
272#define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8)
273#define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3)
274#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
275#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10)
276#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
277#define USBTRDTIM_UTMI_8_BIT 9
278#define USBTRDTIM_UTMI_16_BIT 5
279#define UTMI_PHYIF_16_BIT 1
280#define UTMI_PHYIF_8_BIT 0
281
282/* Global USB2 PHY Vendor Control Register */
283#define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25)
284#define DWC3_GUSB2PHYACC_BUSY BIT(23)
285#define DWC3_GUSB2PHYACC_WRITE BIT(22)
286#define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
287#define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
288#define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
289
290/* Global USB3 PIPE Control Register */
291#define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31)
292#define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29)
293#define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28)
294#define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27)
295#define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24)
296#define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
297#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
298#define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
299#define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18)
300#define DWC3_GUSB3PIPECTL_SUSPHY BIT(17)
301#define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9)
302#define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8)
303#define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
304#define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
305
306/* Global TX Fifo Size Register */
307#define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */
308#define DWC31_GTXFIFOSIZ_TXFDEF(n) ((n) & 0x7fff) /* DWC_usb31 only */
309#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
310#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
311
312/* Global Event Size Registers */
313#define DWC3_GEVNTSIZ_INTMASK BIT(31)
314#define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
315
316/* Global HWPARAMS0 Register */
317#define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3)
318#define DWC3_GHWPARAMS0_MODE_GADGET 0
319#define DWC3_GHWPARAMS0_MODE_HOST 1
320#define DWC3_GHWPARAMS0_MODE_DRD 2
321#define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7)
322#define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3)
323#define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff)
324#define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff)
325#define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff)
326
327/* Global HWPARAMS1 Register */
328#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
329#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
330#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
331#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
332#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
333#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
334#define DWC3_GHWPARAMS1_ENDBC BIT(31)
335
336/* Global HWPARAMS3 Register */
337#define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
338#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
339#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1
340#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */
341#define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
342#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
343#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
344#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
345#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
346#define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
347#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
348#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
349
350/* Global HWPARAMS4 Register */
351#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
352#define DWC3_MAX_HIBER_SCRATCHBUFS 15
353
354/* Global HWPARAMS6 Register */
355#define DWC3_GHWPARAMS6_BCSUPPORT BIT(14)
356#define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13)
357#define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12)
358#define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11)
359#define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10)
360#define DWC3_GHWPARAMS6_EN_FPGA BIT(7)
361
362/* Global HWPARAMS7 Register */
363#define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff)
364#define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff)
365
366/* Global Frame Length Adjustment Register */
367#define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7)
368#define DWC3_GFLADJ_30MHZ_MASK 0x3f
369
370/* Global User Control Register 2 */
371#define DWC3_GUCTL2_RST_ACTBITLATER BIT(14)
372
373/* Device Configuration Register */
374#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
375#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
376
377#define DWC3_DCFG_SPEED_MASK (7 << 0)
378#define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
379#define DWC3_DCFG_SUPERSPEED (4 << 0)
380#define DWC3_DCFG_HIGHSPEED (0 << 0)
381#define DWC3_DCFG_FULLSPEED BIT(0)
382#define DWC3_DCFG_LOWSPEED (2 << 0)
383
384#define DWC3_DCFG_NUMP_SHIFT 17
385#define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
386#define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT)
387#define DWC3_DCFG_LPM_CAP BIT(22)
388
389/* Device Control Register */
390#define DWC3_DCTL_RUN_STOP BIT(31)
391#define DWC3_DCTL_CSFTRST BIT(30)
392#define DWC3_DCTL_LSFTRST BIT(29)
393
394#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
395#define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
396
397#define DWC3_DCTL_APPL1RES BIT(23)
398
399/* These apply for core versions 1.87a and earlier */
400#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
401#define DWC3_DCTL_TRGTULST(n) ((n) << 17)
402#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
403#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
404#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
405#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
406#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
407
408/* These apply for core versions 1.94a and later */
409#define DWC3_DCTL_NYET_THRES(n) (((n) & 0xf) << 20)
410
411#define DWC3_DCTL_KEEP_CONNECT BIT(19)
412#define DWC3_DCTL_L1_HIBER_EN BIT(18)
413#define DWC3_DCTL_CRS BIT(17)
414#define DWC3_DCTL_CSS BIT(16)
415
416#define DWC3_DCTL_INITU2ENA BIT(12)
417#define DWC3_DCTL_ACCEPTU2ENA BIT(11)
418#define DWC3_DCTL_INITU1ENA BIT(10)
419#define DWC3_DCTL_ACCEPTU1ENA BIT(9)
420#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
421
422#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
423#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
424
425#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
426#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
427#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
428#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
429#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
430#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
431#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
432
433/* Device Event Enable Register */
434#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12)
435#define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11)
436#define DWC3_DEVTEN_CMDCMPLTEN BIT(10)
437#define DWC3_DEVTEN_ERRTICERREN BIT(9)
438#define DWC3_DEVTEN_SOFEN BIT(7)
439#define DWC3_DEVTEN_EOPFEN BIT(6)
440#define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5)
441#define DWC3_DEVTEN_WKUPEVTEN BIT(4)
442#define DWC3_DEVTEN_ULSTCNGEN BIT(3)
443#define DWC3_DEVTEN_CONNECTDONEEN BIT(2)
444#define DWC3_DEVTEN_USBRSTEN BIT(1)
445#define DWC3_DEVTEN_DISCONNEVTEN BIT(0)
446
447/* Device Status Register */
448#define DWC3_DSTS_DCNRD BIT(29)
449
450/* This applies for core versions 1.87a and earlier */
451#define DWC3_DSTS_PWRUPREQ BIT(24)
452
453/* These apply for core versions 1.94a and later */
454#define DWC3_DSTS_RSS BIT(25)
455#define DWC3_DSTS_SSS BIT(24)
456
457#define DWC3_DSTS_COREIDLE BIT(23)
458#define DWC3_DSTS_DEVCTRLHLT BIT(22)
459
460#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
461#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
462
463#define DWC3_DSTS_RXFIFOEMPTY BIT(17)
464
465#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
466#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
467
468#define DWC3_DSTS_CONNECTSPD (7 << 0)
469
470#define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
471#define DWC3_DSTS_SUPERSPEED (4 << 0)
472#define DWC3_DSTS_HIGHSPEED (0 << 0)
473#define DWC3_DSTS_FULLSPEED BIT(0)
474#define DWC3_DSTS_LOWSPEED (2 << 0)
475
476/* Device Generic Command Register */
477#define DWC3_DGCMD_SET_LMP 0x01
478#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
479#define DWC3_DGCMD_XMIT_FUNCTION 0x03
480
481/* These apply for core versions 1.94a and later */
482#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
483#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
484
485#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
486#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
487#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
488#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
489
490#define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
491#define DWC3_DGCMD_CMDACT BIT(10)
492#define DWC3_DGCMD_CMDIOC BIT(8)
493
494/* Device Generic Command Parameter Register */
495#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0)
496#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
497#define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
498#define DWC3_DGCMDPAR_TX_FIFO BIT(5)
499#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
500#define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0)
501
502/* Device Endpoint Command Register */
503#define DWC3_DEPCMD_PARAM_SHIFT 16
504#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
505#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
506#define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
507#define DWC3_DEPCMD_HIPRI_FORCERM BIT(11)
508#define DWC3_DEPCMD_CLEARPENDIN BIT(11)
509#define DWC3_DEPCMD_CMDACT BIT(10)
510#define DWC3_DEPCMD_CMDIOC BIT(8)
511
512#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
513#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
514#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
515#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
516#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
517#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
518/* This applies for core versions 1.90a and earlier */
519#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
520/* This applies for core versions 1.94a and later */
521#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
522#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
523#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
524
525#define DWC3_DEPCMD_CMD(x) ((x) & 0xf)
526
527/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
528#define DWC3_DALEPENA_EP(n) BIT(n)
529
530#define DWC3_DEPCMD_TYPE_CONTROL 0
531#define DWC3_DEPCMD_TYPE_ISOC 1
532#define DWC3_DEPCMD_TYPE_BULK 2
533#define DWC3_DEPCMD_TYPE_INTR 3
534
535#define DWC3_DEV_IMOD_COUNT_SHIFT 16
536#define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16)
537#define DWC3_DEV_IMOD_INTERVAL_SHIFT 0
538#define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0)
539
540/* OTG Configuration Register */
541#define DWC3_OCFG_DISPWRCUTTOFF BIT(5)
542#define DWC3_OCFG_HIBDISMASK BIT(4)
543#define DWC3_OCFG_SFTRSTMASK BIT(3)
544#define DWC3_OCFG_OTGVERSION BIT(2)
545#define DWC3_OCFG_HNPCAP BIT(1)
546#define DWC3_OCFG_SRPCAP BIT(0)
547
548/* OTG CTL Register */
549#define DWC3_OCTL_OTG3GOERR BIT(7)
550#define DWC3_OCTL_PERIMODE BIT(6)
551#define DWC3_OCTL_PRTPWRCTL BIT(5)
552#define DWC3_OCTL_HNPREQ BIT(4)
553#define DWC3_OCTL_SESREQ BIT(3)
554#define DWC3_OCTL_TERMSELIDPULSE BIT(2)
555#define DWC3_OCTL_DEVSETHNPEN BIT(1)
556#define DWC3_OCTL_HSTSETHNPEN BIT(0)
557
558/* OTG Event Register */
559#define DWC3_OEVT_DEVICEMODE BIT(31)
560#define DWC3_OEVT_XHCIRUNSTPSET BIT(27)
561#define DWC3_OEVT_DEVRUNSTPSET BIT(26)
562#define DWC3_OEVT_HIBENTRY BIT(25)
563#define DWC3_OEVT_CONIDSTSCHNG BIT(24)
564#define DWC3_OEVT_HRRCONFNOTIF BIT(23)
565#define DWC3_OEVT_HRRINITNOTIF BIT(22)
566#define DWC3_OEVT_ADEVIDLE BIT(21)
567#define DWC3_OEVT_ADEVBHOSTEND BIT(20)
568#define DWC3_OEVT_ADEVHOST BIT(19)
569#define DWC3_OEVT_ADEVHNPCHNG BIT(18)
570#define DWC3_OEVT_ADEVSRPDET BIT(17)
571#define DWC3_OEVT_ADEVSESSENDDET BIT(16)
572#define DWC3_OEVT_BDEVBHOSTEND BIT(11)
573#define DWC3_OEVT_BDEVHNPCHNG BIT(10)
574#define DWC3_OEVT_BDEVSESSVLDDET BIT(9)
575#define DWC3_OEVT_BDEVVBUSCHNG BIT(8)
576#define DWC3_OEVT_BSESSVLD BIT(3)
577#define DWC3_OEVT_HSTNEGSTS BIT(2)
578#define DWC3_OEVT_SESREQSTS BIT(1)
579#define DWC3_OEVT_ERROR BIT(0)
580
581/* OTG Event Enable Register */
582#define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27)
583#define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26)
584#define DWC3_OEVTEN_HIBENTRYEN BIT(25)
585#define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24)
586#define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23)
587#define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22)
588#define DWC3_OEVTEN_ADEVIDLEEN BIT(21)
589#define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20)
590#define DWC3_OEVTEN_ADEVHOSTEN BIT(19)
591#define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18)
592#define DWC3_OEVTEN_ADEVSRPDETEN BIT(17)
593#define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16)
594#define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11)
595#define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10)
596#define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9)
597#define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8)
598
599/* OTG Status Register */
600#define DWC3_OSTS_DEVRUNSTP BIT(13)
601#define DWC3_OSTS_XHCIRUNSTP BIT(12)
602#define DWC3_OSTS_PERIPHERALSTATE BIT(4)
603#define DWC3_OSTS_XHCIPRTPOWER BIT(3)
604#define DWC3_OSTS_BSESVLD BIT(2)
605#define DWC3_OSTS_VBUSVLD BIT(1)
606#define DWC3_OSTS_CONIDSTS BIT(0)
607
608/* Structures */
609
610struct dwc3_trb;
611
612/**
613 * struct dwc3_event_buffer - Software event buffer representation
614 * @buf: _THE_ buffer
615 * @cache: The buffer cache used in the threaded interrupt
616 * @length: size of this buffer
617 * @lpos: event offset
618 * @count: cache of last read event count register
619 * @flags: flags related to this event buffer
620 * @dma: dma_addr_t
621 * @dwc: pointer to DWC controller
622 */
623struct dwc3_event_buffer {
624 void *buf;
625 void *cache;
626 unsigned length;
627 unsigned int lpos;
628 unsigned int count;
629 unsigned int flags;
630
631#define DWC3_EVENT_PENDING BIT(0)
632
633 dma_addr_t dma;
634
635 struct dwc3 *dwc;
636};
637
638#define DWC3_EP_FLAG_STALLED BIT(0)
639#define DWC3_EP_FLAG_WEDGED BIT(1)
640
641#define DWC3_EP_DIRECTION_TX true
642#define DWC3_EP_DIRECTION_RX false
643
644#define DWC3_TRB_NUM 256
645
646/**
647 * struct dwc3_ep - device side endpoint representation
648 * @endpoint: usb endpoint
649 * @cancelled_list: list of cancelled requests for this endpoint
650 * @pending_list: list of pending requests for this endpoint
651 * @started_list: list of started requests on this endpoint
652 * @regs: pointer to first endpoint register
653 * @trb_pool: array of transaction buffers
654 * @trb_pool_dma: dma address of @trb_pool
655 * @trb_enqueue: enqueue 'pointer' into TRB array
656 * @trb_dequeue: dequeue 'pointer' into TRB array
657 * @dwc: pointer to DWC controller
658 * @saved_state: ep state saved during hibernation
659 * @flags: endpoint flags (wedged, stalled, ...)
660 * @number: endpoint number (1 - 15)
661 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
662 * @resource_index: Resource transfer index
663 * @frame_number: set to the frame number we want this transfer to start (ISOC)
664 * @interval: the interval on which the ISOC transfer is started
665 * @name: a human readable name e.g. ep1out-bulk
666 * @direction: true for TX, false for RX
667 * @stream_capable: true when streams are enabled
668 * @combo_num: the test combination BIT[15:14] of the frame number to test
669 * isochronous START TRANSFER command failure workaround
670 * @start_cmd_status: the status of testing START TRANSFER command with
671 * combo_num = 'b00
672 */
673struct dwc3_ep {
674 struct usb_ep endpoint;
675 struct list_head cancelled_list;
676 struct list_head pending_list;
677 struct list_head started_list;
678
679 void __iomem *regs;
680
681 struct dwc3_trb *trb_pool;
682 dma_addr_t trb_pool_dma;
683 struct dwc3 *dwc;
684
685 u32 saved_state;
686 unsigned flags;
687#define DWC3_EP_ENABLED BIT(0)
688#define DWC3_EP_STALL BIT(1)
689#define DWC3_EP_WEDGE BIT(2)
690#define DWC3_EP_TRANSFER_STARTED BIT(3)
691#define DWC3_EP_PENDING_REQUEST BIT(5)
692
693 /* This last one is specific to EP0 */
694#define DWC3_EP0_DIR_IN BIT(31)
695
696 /*
697 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will
698 * use a u8 type here. If anybody decides to increase number of TRBs to
699 * anything larger than 256 - I can't see why people would want to do
700 * this though - then this type needs to be changed.
701 *
702 * By using u8 types we ensure that our % operator when incrementing
703 * enqueue and dequeue get optimized away by the compiler.
704 */
705 u8 trb_enqueue;
706 u8 trb_dequeue;
707
708 u8 number;
709 u8 type;
710 u8 resource_index;
711 u32 frame_number;
712 u32 interval;
713
714 char name[20];
715
716 unsigned direction:1;
717 unsigned stream_capable:1;
718
719 /* For isochronous START TRANSFER workaround only */
720 u8 combo_num;
721 int start_cmd_status;
722};
723
724enum dwc3_phy {
725 DWC3_PHY_UNKNOWN = 0,
726 DWC3_PHY_USB3,
727 DWC3_PHY_USB2,
728};
729
730enum dwc3_ep0_next {
731 DWC3_EP0_UNKNOWN = 0,
732 DWC3_EP0_COMPLETE,
733 DWC3_EP0_NRDY_DATA,
734 DWC3_EP0_NRDY_STATUS,
735};
736
737enum dwc3_ep0_state {
738 EP0_UNCONNECTED = 0,
739 EP0_SETUP_PHASE,
740 EP0_DATA_PHASE,
741 EP0_STATUS_PHASE,
742};
743
744enum dwc3_link_state {
745 /* In SuperSpeed */
746 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
747 DWC3_LINK_STATE_U1 = 0x01,
748 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
749 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
750 DWC3_LINK_STATE_SS_DIS = 0x04,
751 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
752 DWC3_LINK_STATE_SS_INACT = 0x06,
753 DWC3_LINK_STATE_POLL = 0x07,
754 DWC3_LINK_STATE_RECOV = 0x08,
755 DWC3_LINK_STATE_HRESET = 0x09,
756 DWC3_LINK_STATE_CMPLY = 0x0a,
757 DWC3_LINK_STATE_LPBK = 0x0b,
758 DWC3_LINK_STATE_RESET = 0x0e,
759 DWC3_LINK_STATE_RESUME = 0x0f,
760 DWC3_LINK_STATE_MASK = 0x0f,
761};
762
763/* TRB Length, PCM and Status */
764#define DWC3_TRB_SIZE_MASK (0x00ffffff)
765#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
766#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
767#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
768
769#define DWC3_TRBSTS_OK 0
770#define DWC3_TRBSTS_MISSED_ISOC 1
771#define DWC3_TRBSTS_SETUP_PENDING 2
772#define DWC3_TRB_STS_XFER_IN_PROG 4
773
774/* TRB Control */
775#define DWC3_TRB_CTRL_HWO BIT(0)
776#define DWC3_TRB_CTRL_LST BIT(1)
777#define DWC3_TRB_CTRL_CHN BIT(2)
778#define DWC3_TRB_CTRL_CSP BIT(3)
779#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
780#define DWC3_TRB_CTRL_ISP_IMI BIT(10)
781#define DWC3_TRB_CTRL_IOC BIT(11)
782#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
783#define DWC3_TRB_CTRL_GET_SID_SOFN(n) (((n) & (0xffff << 14)) >> 14)
784
785#define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4))
786#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
787#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
788#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
789#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
790#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
791#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
792#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
793#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
794
795/**
796 * struct dwc3_trb - transfer request block (hw format)
797 * @bpl: DW0-3
798 * @bph: DW4-7
799 * @size: DW8-B
800 * @ctrl: DWC-F
801 */
802struct dwc3_trb {
803 u32 bpl;
804 u32 bph;
805 u32 size;
806 u32 ctrl;
807} __packed;
808
809/**
810 * struct dwc3_hwparams - copy of HWPARAMS registers
811 * @hwparams0: GHWPARAMS0
812 * @hwparams1: GHWPARAMS1
813 * @hwparams2: GHWPARAMS2
814 * @hwparams3: GHWPARAMS3
815 * @hwparams4: GHWPARAMS4
816 * @hwparams5: GHWPARAMS5
817 * @hwparams6: GHWPARAMS6
818 * @hwparams7: GHWPARAMS7
819 * @hwparams8: GHWPARAMS8
820 */
821struct dwc3_hwparams {
822 u32 hwparams0;
823 u32 hwparams1;
824 u32 hwparams2;
825 u32 hwparams3;
826 u32 hwparams4;
827 u32 hwparams5;
828 u32 hwparams6;
829 u32 hwparams7;
830 u32 hwparams8;
831};
832
833/* HWPARAMS0 */
834#define DWC3_MODE(n) ((n) & 0x7)
835
836#define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
837
838/* HWPARAMS1 */
839#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
840
841/* HWPARAMS3 */
842#define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
843#define DWC3_NUM_EPS_MASK (0x3f << 12)
844#define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
845 (DWC3_NUM_EPS_MASK)) >> 12)
846#define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
847 (DWC3_NUM_IN_EPS_MASK)) >> 18)
848
849/* HWPARAMS7 */
850#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
851
852/**
853 * struct dwc3_request - representation of a transfer request
854 * @request: struct usb_request to be transferred
855 * @list: a list_head used for request queueing
856 * @dep: struct dwc3_ep owning this request
857 * @sg: pointer to first incomplete sg
858 * @start_sg: pointer to the sg which should be queued next
859 * @num_pending_sgs: counter to pending sgs
860 * @num_queued_sgs: counter to the number of sgs which already got queued
861 * @remaining: amount of data remaining
862 * @status: internal dwc3 request status tracking
863 * @epnum: endpoint number to which this request refers
864 * @trb: pointer to struct dwc3_trb
865 * @trb_dma: DMA address of @trb
866 * @num_trbs: number of TRBs used by this request
867 * @needs_extra_trb: true when request needs one extra TRB (either due to ZLP
868 * or unaligned OUT)
869 * @direction: IN or OUT direction flag
870 * @mapped: true when request has been dma-mapped
871 */
872struct dwc3_request {
873 struct usb_request request;
874 struct list_head list;
875 struct dwc3_ep *dep;
876 struct scatterlist *sg;
877 struct scatterlist *start_sg;
878
879 unsigned num_pending_sgs;
880 unsigned int num_queued_sgs;
881 unsigned remaining;
882
883 unsigned int status;
884#define DWC3_REQUEST_STATUS_QUEUED 0
885#define DWC3_REQUEST_STATUS_STARTED 1
886#define DWC3_REQUEST_STATUS_CANCELLED 2
887#define DWC3_REQUEST_STATUS_COMPLETED 3
888#define DWC3_REQUEST_STATUS_UNKNOWN -1
889
890 u8 epnum;
891 struct dwc3_trb *trb;
892 dma_addr_t trb_dma;
893
894 unsigned num_trbs;
895
896 unsigned needs_extra_trb:1;
897 unsigned direction:1;
898 unsigned mapped:1;
899};
900
901/*
902 * struct dwc3_scratchpad_array - hibernation scratchpad array
903 * (format defined by hw)
904 */
905struct dwc3_scratchpad_array {
906 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
907};
908
909/**
910 * struct dwc3 - representation of our controller
911 * @drd_work: workqueue used for role swapping
912 * @ep0_trb: trb which is used for the ctrl_req
913 * @bounce: address of bounce buffer
914 * @scratchbuf: address of scratch buffer
915 * @setup_buf: used while precessing STD USB requests
916 * @ep0_trb_addr: dma address of @ep0_trb
917 * @bounce_addr: dma address of @bounce
918 * @ep0_usb_req: dummy req used while handling STD USB requests
919 * @scratch_addr: dma address of scratchbuf
920 * @ep0_in_setup: one control transfer is completed and enter setup phase
921 * @lock: for synchronizing
922 * @dev: pointer to our struct device
923 * @sysdev: pointer to the DMA-capable device
924 * @xhci: pointer to our xHCI child
925 * @xhci_resources: struct resources for our @xhci child
926 * @ev_buf: struct dwc3_event_buffer pointer
927 * @eps: endpoint array
928 * @gadget: device side representation of the peripheral controller
929 * @gadget_driver: pointer to the gadget driver
930 * @clks: array of clocks
931 * @num_clks: number of clocks
932 * @reset: reset control
933 * @regs: base address for our registers
934 * @regs_size: address space size
935 * @fladj: frame length adjustment
936 * @irq_gadget: peripheral controller's IRQ number
937 * @otg_irq: IRQ number for OTG IRQs
938 * @current_otg_role: current role of operation while using the OTG block
939 * @desired_otg_role: desired role of operation while using the OTG block
940 * @otg_restart_host: flag that OTG controller needs to restart host
941 * @nr_scratch: number of scratch buffers
942 * @u1u2: only used on revisions <1.83a for workaround
943 * @maximum_speed: maximum speed requested (mainly for testing purposes)
944 * @revision: revision register contents
945 * @version_type: VERSIONTYPE register contents, a sub release of a revision
946 * @dr_mode: requested mode of operation
947 * @current_dr_role: current role of operation when in dual-role mode
948 * @desired_dr_role: desired role of operation when in dual-role mode
949 * @edev: extcon handle
950 * @edev_nb: extcon notifier
951 * @hsphy_mode: UTMI phy mode, one of following:
952 * - USBPHY_INTERFACE_MODE_UTMI
953 * - USBPHY_INTERFACE_MODE_UTMIW
954 * @usb2_phy: pointer to USB2 PHY
955 * @usb3_phy: pointer to USB3 PHY
956 * @usb2_generic_phy: pointer to USB2 PHY
957 * @usb3_generic_phy: pointer to USB3 PHY
958 * @phys_ready: flag to indicate that PHYs are ready
959 * @ulpi: pointer to ulpi interface
960 * @ulpi_ready: flag to indicate that ULPI is initialized
961 * @u2sel: parameter from Set SEL request.
962 * @u2pel: parameter from Set SEL request.
963 * @u1sel: parameter from Set SEL request.
964 * @u1pel: parameter from Set SEL request.
965 * @num_eps: number of endpoints
966 * @ep0_next_event: hold the next expected event
967 * @ep0state: state of endpoint zero
968 * @link_state: link state
969 * @speed: device speed (super, high, full, low)
970 * @hwparams: copy of hwparams registers
971 * @root: debugfs root folder pointer
972 * @regset: debugfs pointer to regdump file
973 * @dbg_lsp_select: current debug lsp mux register selection
974 * @test_mode: true when we're entering a USB test mode
975 * @test_mode_nr: test feature selector
976 * @lpm_nyet_threshold: LPM NYET response threshold
977 * @hird_threshold: HIRD threshold
978 * @rx_thr_num_pkt_prd: periodic ESS receive packet count
979 * @rx_max_burst_prd: max periodic ESS receive burst size
980 * @tx_thr_num_pkt_prd: periodic ESS transmit packet count
981 * @tx_max_burst_prd: max periodic ESS transmit burst size
982 * @hsphy_interface: "utmi" or "ulpi"
983 * @connected: true when we're connected to a host, false otherwise
984 * @delayed_status: true when gadget driver asks for delayed status
985 * @ep0_bounced: true when we used bounce buffer
986 * @ep0_expect_in: true when we expect a DATA IN transfer
987 * @has_hibernation: true when dwc3 was configured with Hibernation
988 * @sysdev_is_parent: true when dwc3 device has a parent driver
989 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
990 * there's now way for software to detect this in runtime.
991 * @is_utmi_l1_suspend: the core asserts output signal
992 * 0 - utmi_sleep_n
993 * 1 - utmi_l1_suspend_n
994 * @is_fpga: true when we are using the FPGA board
995 * @pending_events: true when we have pending IRQs to be handled
996 * @pullups_connected: true when Run/Stop bit is set
997 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
998 * @three_stage_setup: set if we perform a three phase setup
999 * @dis_start_transfer_quirk: set if start_transfer failure SW workaround is
1000 * not needed for DWC_usb31 version 1.70a-ea06 and below
1001 * @usb3_lpm_capable: set if hadrware supports Link Power Management
1002 * @usb2_lpm_disable: set to disable usb2 lpm
1003 * @disable_scramble_quirk: set if we enable the disable scramble quirk
1004 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
1005 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
1006 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
1007 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
1008 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
1009 * @lfps_filter_quirk: set if we enable LFPS filter quirk
1010 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
1011 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
1012 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
1013 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
1014 * disabling the suspend signal to the PHY.
1015 * @dis_u1_entry_quirk: set if link entering into U1 state needs to be disabled.
1016 * @dis_u2_entry_quirk: set if link entering into U2 state needs to be disabled.
1017 * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3
1018 * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
1019 * in GUSB2PHYCFG, specify that USB2 PHY doesn't
1020 * provide a free-running PHY clock.
1021 * @dis_del_phy_power_chg_quirk: set if we disable delay phy power
1022 * change quirk.
1023 * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
1024 * check during HS transmit.
1025 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
1026 * @tx_de_emphasis: Tx de-emphasis value
1027 * 0 - -6dB de-emphasis
1028 * 1 - -3.5dB de-emphasis
1029 * 2 - No de-emphasis
1030 * 3 - Reserved
1031 * @dis_metastability_quirk: set to disable metastability quirk.
1032 * @imod_interval: set the interrupt moderation interval in 250ns
1033 * increments or 0 to disable.
1034 */
1035struct dwc3 {
1036 struct work_struct drd_work;
1037 struct dwc3_trb *ep0_trb;
1038 void *bounce;
1039 void *scratchbuf;
1040 u8 *setup_buf;
1041 dma_addr_t ep0_trb_addr;
1042 dma_addr_t bounce_addr;
1043 dma_addr_t scratch_addr;
1044 struct dwc3_request ep0_usb_req;
1045 struct completion ep0_in_setup;
1046
1047 /* device lock */
1048 spinlock_t lock;
1049
1050 struct device *dev;
1051 struct device *sysdev;
1052
1053 struct platform_device *xhci;
1054 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
1055
1056 struct dwc3_event_buffer *ev_buf;
1057 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
1058
1059 struct usb_gadget gadget;
1060 struct usb_gadget_driver *gadget_driver;
1061
1062 struct clk_bulk_data *clks;
1063 int num_clks;
1064
1065 struct reset_control *reset;
1066
1067 struct usb_phy *usb2_phy;
1068 struct usb_phy *usb3_phy;
1069
1070 struct phy *usb2_generic_phy;
1071 struct phy *usb3_generic_phy;
1072
1073 bool phys_ready;
1074
1075 struct ulpi *ulpi;
1076 bool ulpi_ready;
1077
1078 void __iomem *regs;
1079 size_t regs_size;
1080
1081 enum usb_dr_mode dr_mode;
1082 u32 current_dr_role;
1083 u32 desired_dr_role;
1084 struct extcon_dev *edev;
1085 struct notifier_block edev_nb;
1086 enum usb_phy_interface hsphy_mode;
1087
1088 u32 fladj;
1089 u32 irq_gadget;
1090 u32 otg_irq;
1091 u32 current_otg_role;
1092 u32 desired_otg_role;
1093 bool otg_restart_host;
1094 u32 nr_scratch;
1095 u32 u1u2;
1096 u32 maximum_speed;
1097
1098 /*
1099 * All 3.1 IP version constants are greater than the 3.0 IP
1100 * version constants. This works for most version checks in
1101 * dwc3. However, in the future, this may not apply as
1102 * features may be developed on newer versions of the 3.0 IP
1103 * that are not in the 3.1 IP.
1104 */
1105 u32 revision;
1106
1107#define DWC3_REVISION_173A 0x5533173a
1108#define DWC3_REVISION_175A 0x5533175a
1109#define DWC3_REVISION_180A 0x5533180a
1110#define DWC3_REVISION_183A 0x5533183a
1111#define DWC3_REVISION_185A 0x5533185a
1112#define DWC3_REVISION_187A 0x5533187a
1113#define DWC3_REVISION_188A 0x5533188a
1114#define DWC3_REVISION_190A 0x5533190a
1115#define DWC3_REVISION_194A 0x5533194a
1116#define DWC3_REVISION_200A 0x5533200a
1117#define DWC3_REVISION_202A 0x5533202a
1118#define DWC3_REVISION_210A 0x5533210a
1119#define DWC3_REVISION_220A 0x5533220a
1120#define DWC3_REVISION_230A 0x5533230a
1121#define DWC3_REVISION_240A 0x5533240a
1122#define DWC3_REVISION_250A 0x5533250a
1123#define DWC3_REVISION_260A 0x5533260a
1124#define DWC3_REVISION_270A 0x5533270a
1125#define DWC3_REVISION_280A 0x5533280a
1126#define DWC3_REVISION_290A 0x5533290a
1127#define DWC3_REVISION_300A 0x5533300a
1128#define DWC3_REVISION_310A 0x5533310a
1129#define DWC3_REVISION_330A 0x5533330a
1130
1131/*
1132 * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really
1133 * just so dwc31 revisions are always larger than dwc3.
1134 */
1135#define DWC3_REVISION_IS_DWC31 0x80000000
1136#define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_DWC31)
1137#define DWC3_USB31_REVISION_120A (0x3132302a | DWC3_REVISION_IS_DWC31)
1138#define DWC3_USB31_REVISION_160A (0x3136302a | DWC3_REVISION_IS_DWC31)
1139#define DWC3_USB31_REVISION_170A (0x3137302a | DWC3_REVISION_IS_DWC31)
1140#define DWC3_USB31_REVISION_180A (0x3138302a | DWC3_REVISION_IS_DWC31)
1141#define DWC3_USB31_REVISION_190A (0x3139302a | DWC3_REVISION_IS_DWC31)
1142
1143 u32 version_type;
1144
1145#define DWC31_VERSIONTYPE_EA01 0x65613031
1146#define DWC31_VERSIONTYPE_EA02 0x65613032
1147#define DWC31_VERSIONTYPE_EA03 0x65613033
1148#define DWC31_VERSIONTYPE_EA04 0x65613034
1149#define DWC31_VERSIONTYPE_EA05 0x65613035
1150#define DWC31_VERSIONTYPE_EA06 0x65613036
1151
1152 enum dwc3_ep0_next ep0_next_event;
1153 enum dwc3_ep0_state ep0state;
1154 enum dwc3_link_state link_state;
1155
1156 u16 u2sel;
1157 u16 u2pel;
1158 u8 u1sel;
1159 u8 u1pel;
1160
1161 u8 speed;
1162
1163 u8 num_eps;
1164
1165 struct dwc3_hwparams hwparams;
1166 struct dentry *root;
1167 struct debugfs_regset32 *regset;
1168
1169 u32 dbg_lsp_select;
1170
1171 u8 test_mode;
1172 u8 test_mode_nr;
1173 u8 lpm_nyet_threshold;
1174 u8 hird_threshold;
1175 u8 rx_thr_num_pkt_prd;
1176 u8 rx_max_burst_prd;
1177 u8 tx_thr_num_pkt_prd;
1178 u8 tx_max_burst_prd;
1179
1180 const char *hsphy_interface;
1181
1182 unsigned connected:1;
1183 unsigned delayed_status:1;
1184 unsigned ep0_bounced:1;
1185 unsigned ep0_expect_in:1;
1186 unsigned has_hibernation:1;
1187 unsigned sysdev_is_parent:1;
1188 unsigned has_lpm_erratum:1;
1189 unsigned is_utmi_l1_suspend:1;
1190 unsigned is_fpga:1;
1191 unsigned pending_events:1;
1192 unsigned pullups_connected:1;
1193 unsigned setup_packet_pending:1;
1194 unsigned three_stage_setup:1;
1195 unsigned dis_start_transfer_quirk:1;
1196 unsigned usb3_lpm_capable:1;
1197 unsigned usb2_lpm_disable:1;
1198
1199 unsigned disable_scramble_quirk:1;
1200 unsigned u2exit_lfps_quirk:1;
1201 unsigned u2ss_inp3_quirk:1;
1202 unsigned req_p1p2p3_quirk:1;
1203 unsigned del_p1p2p3_quirk:1;
1204 unsigned del_phy_power_chg_quirk:1;
1205 unsigned lfps_filter_quirk:1;
1206 unsigned rx_detect_poll_quirk:1;
1207 unsigned dis_u3_susphy_quirk:1;
1208 unsigned dis_u2_susphy_quirk:1;
1209 unsigned dis_enblslpm_quirk:1;
1210 unsigned dis_u1_entry_quirk:1;
1211 unsigned dis_u2_entry_quirk:1;
1212 unsigned dis_rxdet_inp3_quirk:1;
1213 unsigned dis_u2_freeclk_exists_quirk:1;
1214 unsigned dis_del_phy_power_chg_quirk:1;
1215 unsigned dis_tx_ipgap_linecheck_quirk:1;
1216
1217 unsigned tx_de_emphasis_quirk:1;
1218 unsigned tx_de_emphasis:2;
1219
1220 unsigned dis_metastability_quirk:1;
1221
1222 u16 imod_interval;
1223};
1224
1225#define INCRX_BURST_MODE 0
1226#define INCRX_UNDEF_LENGTH_BURST_MODE 1
1227
1228#define work_to_dwc(w) (container_of((w), struct dwc3, drd_work))
1229
1230/* -------------------------------------------------------------------------- */
1231
1232struct dwc3_event_type {
1233 u32 is_devspec:1;
1234 u32 type:7;
1235 u32 reserved8_31:24;
1236} __packed;
1237
1238#define DWC3_DEPEVT_XFERCOMPLETE 0x01
1239#define DWC3_DEPEVT_XFERINPROGRESS 0x02
1240#define DWC3_DEPEVT_XFERNOTREADY 0x03
1241#define DWC3_DEPEVT_RXTXFIFOEVT 0x04
1242#define DWC3_DEPEVT_STREAMEVT 0x06
1243#define DWC3_DEPEVT_EPCMDCMPLT 0x07
1244
1245/**
1246 * struct dwc3_event_depvt - Device Endpoint Events
1247 * @one_bit: indicates this is an endpoint event (not used)
1248 * @endpoint_number: number of the endpoint
1249 * @endpoint_event: The event we have:
1250 * 0x00 - Reserved
1251 * 0x01 - XferComplete
1252 * 0x02 - XferInProgress
1253 * 0x03 - XferNotReady
1254 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
1255 * 0x05 - Reserved
1256 * 0x06 - StreamEvt
1257 * 0x07 - EPCmdCmplt
1258 * @reserved11_10: Reserved, don't use.
1259 * @status: Indicates the status of the event. Refer to databook for
1260 * more information.
1261 * @parameters: Parameters of the current event. Refer to databook for
1262 * more information.
1263 */
1264struct dwc3_event_depevt {
1265 u32 one_bit:1;
1266 u32 endpoint_number:5;
1267 u32 endpoint_event:4;
1268 u32 reserved11_10:2;
1269 u32 status:4;
1270
1271/* Within XferNotReady */
1272#define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3)
1273
1274/* Within XferComplete or XferInProgress */
1275#define DEPEVT_STATUS_BUSERR BIT(0)
1276#define DEPEVT_STATUS_SHORT BIT(1)
1277#define DEPEVT_STATUS_IOC BIT(2)
1278#define DEPEVT_STATUS_LST BIT(3) /* XferComplete */
1279#define DEPEVT_STATUS_MISSED_ISOC BIT(3) /* XferInProgress */
1280
1281/* Stream event only */
1282#define DEPEVT_STREAMEVT_FOUND 1
1283#define DEPEVT_STREAMEVT_NOTFOUND 2
1284
1285/* Control-only Status */
1286#define DEPEVT_STATUS_CONTROL_DATA 1
1287#define DEPEVT_STATUS_CONTROL_STATUS 2
1288#define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3)
1289
1290/* In response to Start Transfer */
1291#define DEPEVT_TRANSFER_NO_RESOURCE 1
1292#define DEPEVT_TRANSFER_BUS_EXPIRY 2
1293
1294 u32 parameters:16;
1295
1296/* For Command Complete Events */
1297#define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8)
1298} __packed;
1299
1300/**
1301 * struct dwc3_event_devt - Device Events
1302 * @one_bit: indicates this is a non-endpoint event (not used)
1303 * @device_event: indicates it's a device event. Should read as 0x00
1304 * @type: indicates the type of device event.
1305 * 0 - DisconnEvt
1306 * 1 - USBRst
1307 * 2 - ConnectDone
1308 * 3 - ULStChng
1309 * 4 - WkUpEvt
1310 * 5 - Reserved
1311 * 6 - EOPF
1312 * 7 - SOF
1313 * 8 - Reserved
1314 * 9 - ErrticErr
1315 * 10 - CmdCmplt
1316 * 11 - EvntOverflow
1317 * 12 - VndrDevTstRcved
1318 * @reserved15_12: Reserved, not used
1319 * @event_info: Information about this event
1320 * @reserved31_25: Reserved, not used
1321 */
1322struct dwc3_event_devt {
1323 u32 one_bit:1;
1324 u32 device_event:7;
1325 u32 type:4;
1326 u32 reserved15_12:4;
1327 u32 event_info:9;
1328 u32 reserved31_25:7;
1329} __packed;
1330
1331/**
1332 * struct dwc3_event_gevt - Other Core Events
1333 * @one_bit: indicates this is a non-endpoint event (not used)
1334 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1335 * @phy_port_number: self-explanatory
1336 * @reserved31_12: Reserved, not used.
1337 */
1338struct dwc3_event_gevt {
1339 u32 one_bit:1;
1340 u32 device_event:7;
1341 u32 phy_port_number:4;
1342 u32 reserved31_12:20;
1343} __packed;
1344
1345/**
1346 * union dwc3_event - representation of Event Buffer contents
1347 * @raw: raw 32-bit event
1348 * @type: the type of the event
1349 * @depevt: Device Endpoint Event
1350 * @devt: Device Event
1351 * @gevt: Global Event
1352 */
1353union dwc3_event {
1354 u32 raw;
1355 struct dwc3_event_type type;
1356 struct dwc3_event_depevt depevt;
1357 struct dwc3_event_devt devt;
1358 struct dwc3_event_gevt gevt;
1359};
1360
1361/**
1362 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1363 * parameters
1364 * @param2: third parameter
1365 * @param1: second parameter
1366 * @param0: first parameter
1367 */
1368struct dwc3_gadget_ep_cmd_params {
1369 u32 param2;
1370 u32 param1;
1371 u32 param0;
1372};
1373
1374/*
1375 * DWC3 Features to be used as Driver Data
1376 */
1377
1378#define DWC3_HAS_PERIPHERAL BIT(0)
1379#define DWC3_HAS_XHCI BIT(1)
1380#define DWC3_HAS_OTG BIT(3)
1381
1382/* prototypes */
1383void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode);
1384void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1385u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
1386
1387/* check whether we are on the DWC_usb3 core */
1388static inline bool dwc3_is_usb3(struct dwc3 *dwc)
1389{
1390 return !(dwc->revision & DWC3_REVISION_IS_DWC31);
1391}
1392
1393/* check whether we are on the DWC_usb31 core */
1394static inline bool dwc3_is_usb31(struct dwc3 *dwc)
1395{
1396 return !!(dwc->revision & DWC3_REVISION_IS_DWC31);
1397}
1398
1399bool dwc3_has_imod(struct dwc3 *dwc);
1400
1401int dwc3_event_buffers_setup(struct dwc3 *dwc);
1402void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
1403
1404#if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1405int dwc3_host_init(struct dwc3 *dwc);
1406void dwc3_host_exit(struct dwc3 *dwc);
1407#else
1408static inline int dwc3_host_init(struct dwc3 *dwc)
1409{ return 0; }
1410static inline void dwc3_host_exit(struct dwc3 *dwc)
1411{ }
1412#endif
1413
1414#if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1415int dwc3_gadget_init(struct dwc3 *dwc);
1416void dwc3_gadget_exit(struct dwc3 *dwc);
1417int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1418int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1419int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1420int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1421 struct dwc3_gadget_ep_cmd_params *params);
1422int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1423#else
1424static inline int dwc3_gadget_init(struct dwc3 *dwc)
1425{ return 0; }
1426static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1427{ }
1428static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1429{ return 0; }
1430static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1431{ return 0; }
1432static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1433 enum dwc3_link_state state)
1434{ return 0; }
1435
1436static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1437 struct dwc3_gadget_ep_cmd_params *params)
1438{ return 0; }
1439static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1440 int cmd, u32 param)
1441{ return 0; }
1442#endif
1443
1444#if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1445int dwc3_drd_init(struct dwc3 *dwc);
1446void dwc3_drd_exit(struct dwc3 *dwc);
1447void dwc3_otg_init(struct dwc3 *dwc);
1448void dwc3_otg_exit(struct dwc3 *dwc);
1449void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus);
1450void dwc3_otg_host_init(struct dwc3 *dwc);
1451#else
1452static inline int dwc3_drd_init(struct dwc3 *dwc)
1453{ return 0; }
1454static inline void dwc3_drd_exit(struct dwc3 *dwc)
1455{ }
1456static inline void dwc3_otg_init(struct dwc3 *dwc)
1457{ }
1458static inline void dwc3_otg_exit(struct dwc3 *dwc)
1459{ }
1460static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
1461{ }
1462static inline void dwc3_otg_host_init(struct dwc3 *dwc)
1463{ }
1464#endif
1465
1466/* power management interface */
1467#if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1468int dwc3_gadget_suspend(struct dwc3 *dwc);
1469int dwc3_gadget_resume(struct dwc3 *dwc);
1470void dwc3_gadget_process_pending_events(struct dwc3 *dwc);
1471#else
1472static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1473{
1474 return 0;
1475}
1476
1477static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1478{
1479 return 0;
1480}
1481
1482static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
1483{
1484}
1485#endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1486
1487#if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1488int dwc3_ulpi_init(struct dwc3 *dwc);
1489void dwc3_ulpi_exit(struct dwc3 *dwc);
1490#else
1491static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1492{ return 0; }
1493static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1494{ }
1495#endif
1496
1497#endif /* __DRIVERS_USB_DWC3_CORE_H */