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1/**
2 * core.h - DesignWare USB3 DRD Core Header
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#ifndef __DRIVERS_USB_DWC3_CORE_H
40#define __DRIVERS_USB_DWC3_CORE_H
41
42#include <linux/device.h>
43#include <linux/spinlock.h>
44#include <linux/ioport.h>
45#include <linux/list.h>
46#include <linux/dma-mapping.h>
47#include <linux/mm.h>
48#include <linux/debugfs.h>
49
50#include <linux/usb/ch9.h>
51#include <linux/usb/gadget.h>
52
53/* Global constants */
54#define DWC3_EP0_BOUNCE_SIZE 512
55#define DWC3_ENDPOINTS_NUM 32
56#define DWC3_XHCI_RESOURCES_NUM 2
57
58#define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE
59#define DWC3_EVENT_TYPE_MASK 0xfe
60
61#define DWC3_EVENT_TYPE_DEV 0
62#define DWC3_EVENT_TYPE_CARKIT 3
63#define DWC3_EVENT_TYPE_I2C 4
64
65#define DWC3_DEVICE_EVENT_DISCONNECT 0
66#define DWC3_DEVICE_EVENT_RESET 1
67#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
68#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
69#define DWC3_DEVICE_EVENT_WAKEUP 4
70#define DWC3_DEVICE_EVENT_EOPF 6
71#define DWC3_DEVICE_EVENT_SOF 7
72#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
73#define DWC3_DEVICE_EVENT_CMD_CMPL 10
74#define DWC3_DEVICE_EVENT_OVERFLOW 11
75
76#define DWC3_GEVNTCOUNT_MASK 0xfffc
77#define DWC3_GSNPSID_MASK 0xffff0000
78#define DWC3_GSNPSREV_MASK 0xffff
79
80/* DWC3 registers memory space boundries */
81#define DWC3_XHCI_REGS_START 0x0
82#define DWC3_XHCI_REGS_END 0x7fff
83#define DWC3_GLOBALS_REGS_START 0xc100
84#define DWC3_GLOBALS_REGS_END 0xc6ff
85#define DWC3_DEVICE_REGS_START 0xc700
86#define DWC3_DEVICE_REGS_END 0xcbff
87#define DWC3_OTG_REGS_START 0xcc00
88#define DWC3_OTG_REGS_END 0xccff
89
90/* Global Registers */
91#define DWC3_GSBUSCFG0 0xc100
92#define DWC3_GSBUSCFG1 0xc104
93#define DWC3_GTXTHRCFG 0xc108
94#define DWC3_GRXTHRCFG 0xc10c
95#define DWC3_GCTL 0xc110
96#define DWC3_GEVTEN 0xc114
97#define DWC3_GSTS 0xc118
98#define DWC3_GSNPSID 0xc120
99#define DWC3_GGPIO 0xc124
100#define DWC3_GUID 0xc128
101#define DWC3_GUCTL 0xc12c
102#define DWC3_GBUSERRADDR0 0xc130
103#define DWC3_GBUSERRADDR1 0xc134
104#define DWC3_GPRTBIMAP0 0xc138
105#define DWC3_GPRTBIMAP1 0xc13c
106#define DWC3_GHWPARAMS0 0xc140
107#define DWC3_GHWPARAMS1 0xc144
108#define DWC3_GHWPARAMS2 0xc148
109#define DWC3_GHWPARAMS3 0xc14c
110#define DWC3_GHWPARAMS4 0xc150
111#define DWC3_GHWPARAMS5 0xc154
112#define DWC3_GHWPARAMS6 0xc158
113#define DWC3_GHWPARAMS7 0xc15c
114#define DWC3_GDBGFIFOSPACE 0xc160
115#define DWC3_GDBGLTSSM 0xc164
116#define DWC3_GPRTBIMAP_HS0 0xc180
117#define DWC3_GPRTBIMAP_HS1 0xc184
118#define DWC3_GPRTBIMAP_FS0 0xc188
119#define DWC3_GPRTBIMAP_FS1 0xc18c
120
121#define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
122#define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
123
124#define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
125
126#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
127
128#define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
129#define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
130
131#define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
132#define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
133#define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
134#define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
135
136#define DWC3_GHWPARAMS8 0xc600
137
138/* Device Registers */
139#define DWC3_DCFG 0xc700
140#define DWC3_DCTL 0xc704
141#define DWC3_DEVTEN 0xc708
142#define DWC3_DSTS 0xc70c
143#define DWC3_DGCMDPAR 0xc710
144#define DWC3_DGCMD 0xc714
145#define DWC3_DALEPENA 0xc720
146#define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
147#define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
148#define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
149#define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
150
151/* OTG Registers */
152#define DWC3_OCFG 0xcc00
153#define DWC3_OCTL 0xcc04
154#define DWC3_OEVTEN 0xcc08
155#define DWC3_OSTS 0xcc0C
156
157/* Bit fields */
158
159/* Global Configuration Register */
160#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
161#define DWC3_GCTL_U2RSTECN (1 << 16)
162#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
163#define DWC3_GCTL_CLK_BUS (0)
164#define DWC3_GCTL_CLK_PIPE (1)
165#define DWC3_GCTL_CLK_PIPEHALF (2)
166#define DWC3_GCTL_CLK_MASK (3)
167
168#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
169#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
170#define DWC3_GCTL_PRTCAP_HOST 1
171#define DWC3_GCTL_PRTCAP_DEVICE 2
172#define DWC3_GCTL_PRTCAP_OTG 3
173
174#define DWC3_GCTL_CORESOFTRESET (1 << 11)
175#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
176#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
177#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
178#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
179
180/* Global USB2 PHY Configuration Register */
181#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
182#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
183
184/* Global USB3 PIPE Control Register */
185#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
186#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
187
188/* Global TX Fifo Size Register */
189#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
190#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
191
192/* Global HWPARAMS1 Register */
193#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
194#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
195#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
196
197/* Device Configuration Register */
198#define DWC3_DCFG_LPM_CAP (1 << 22)
199#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
200#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
201
202#define DWC3_DCFG_SPEED_MASK (7 << 0)
203#define DWC3_DCFG_SUPERSPEED (4 << 0)
204#define DWC3_DCFG_HIGHSPEED (0 << 0)
205#define DWC3_DCFG_FULLSPEED2 (1 << 0)
206#define DWC3_DCFG_LOWSPEED (2 << 0)
207#define DWC3_DCFG_FULLSPEED1 (3 << 0)
208
209/* Device Control Register */
210#define DWC3_DCTL_RUN_STOP (1 << 31)
211#define DWC3_DCTL_CSFTRST (1 << 30)
212#define DWC3_DCTL_LSFTRST (1 << 29)
213
214#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
215#define DWC3_DCTL_HIRD_THRES(n) (((n) & DWC3_DCTL_HIRD_THRES_MASK) >> 24)
216
217#define DWC3_DCTL_APPL1RES (1 << 23)
218
219#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
220#define DWC3_DCTL_TRGTULST(n) ((n) << 17)
221
222#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
223#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
224#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
225#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
226#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
227
228#define DWC3_DCTL_INITU2ENA (1 << 12)
229#define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
230#define DWC3_DCTL_INITU1ENA (1 << 10)
231#define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
232#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
233
234#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
235#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
236
237#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
238#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
239#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
240#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
241#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
242#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
243#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
244
245/* Device Event Enable Register */
246#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
247#define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
248#define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
249#define DWC3_DEVTEN_ERRTICERREN (1 << 9)
250#define DWC3_DEVTEN_SOFEN (1 << 7)
251#define DWC3_DEVTEN_EOPFEN (1 << 6)
252#define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
253#define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
254#define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
255#define DWC3_DEVTEN_USBRSTEN (1 << 1)
256#define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
257
258/* Device Status Register */
259#define DWC3_DSTS_PWRUPREQ (1 << 24)
260#define DWC3_DSTS_COREIDLE (1 << 23)
261#define DWC3_DSTS_DEVCTRLHLT (1 << 22)
262
263#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
264#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
265
266#define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
267
268#define DWC3_DSTS_SOFFN_MASK (0x3ff << 3)
269#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
270
271#define DWC3_DSTS_CONNECTSPD (7 << 0)
272
273#define DWC3_DSTS_SUPERSPEED (4 << 0)
274#define DWC3_DSTS_HIGHSPEED (0 << 0)
275#define DWC3_DSTS_FULLSPEED2 (1 << 0)
276#define DWC3_DSTS_LOWSPEED (2 << 0)
277#define DWC3_DSTS_FULLSPEED1 (3 << 0)
278
279/* Device Generic Command Register */
280#define DWC3_DGCMD_SET_LMP 0x01
281#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
282#define DWC3_DGCMD_XMIT_FUNCTION 0x03
283#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
284#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
285#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
286#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
287
288#define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1)
289#define DWC3_DGCMD_CMDACT (1 << 10)
290
291/* Device Endpoint Command Register */
292#define DWC3_DEPCMD_PARAM_SHIFT 16
293#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
294#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
295#define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1)
296#define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
297#define DWC3_DEPCMD_CMDACT (1 << 10)
298#define DWC3_DEPCMD_CMDIOC (1 << 8)
299
300#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
301#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
302#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
303#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
304#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
305#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
306#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
307#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
308#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
309
310/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
311#define DWC3_DALEPENA_EP(n) (1 << n)
312
313#define DWC3_DEPCMD_TYPE_CONTROL 0
314#define DWC3_DEPCMD_TYPE_ISOC 1
315#define DWC3_DEPCMD_TYPE_BULK 2
316#define DWC3_DEPCMD_TYPE_INTR 3
317
318/* Structures */
319
320struct dwc3_trb;
321
322/**
323 * struct dwc3_event_buffer - Software event buffer representation
324 * @list: a list of event buffers
325 * @buf: _THE_ buffer
326 * @length: size of this buffer
327 * @dma: dma_addr_t
328 * @dwc: pointer to DWC controller
329 */
330struct dwc3_event_buffer {
331 void *buf;
332 unsigned length;
333 unsigned int lpos;
334
335 dma_addr_t dma;
336
337 struct dwc3 *dwc;
338};
339
340#define DWC3_EP_FLAG_STALLED (1 << 0)
341#define DWC3_EP_FLAG_WEDGED (1 << 1)
342
343#define DWC3_EP_DIRECTION_TX true
344#define DWC3_EP_DIRECTION_RX false
345
346#define DWC3_TRB_NUM 32
347#define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
348
349/**
350 * struct dwc3_ep - device side endpoint representation
351 * @endpoint: usb endpoint
352 * @request_list: list of requests for this endpoint
353 * @req_queued: list of requests on this ep which have TRBs setup
354 * @trb_pool: array of transaction buffers
355 * @trb_pool_dma: dma address of @trb_pool
356 * @free_slot: next slot which is going to be used
357 * @busy_slot: first slot which is owned by HW
358 * @desc: usb_endpoint_descriptor pointer
359 * @dwc: pointer to DWC controller
360 * @flags: endpoint flags (wedged, stalled, ...)
361 * @current_trb: index of current used trb
362 * @number: endpoint number (1 - 15)
363 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
364 * @res_trans_idx: Resource transfer index
365 * @interval: the intervall on which the ISOC transfer is started
366 * @name: a human readable name e.g. ep1out-bulk
367 * @direction: true for TX, false for RX
368 * @stream_capable: true when streams are enabled
369 */
370struct dwc3_ep {
371 struct usb_ep endpoint;
372 struct list_head request_list;
373 struct list_head req_queued;
374
375 struct dwc3_trb *trb_pool;
376 dma_addr_t trb_pool_dma;
377 u32 free_slot;
378 u32 busy_slot;
379 const struct usb_ss_ep_comp_descriptor *comp_desc;
380 struct dwc3 *dwc;
381
382 unsigned flags;
383#define DWC3_EP_ENABLED (1 << 0)
384#define DWC3_EP_STALL (1 << 1)
385#define DWC3_EP_WEDGE (1 << 2)
386#define DWC3_EP_BUSY (1 << 4)
387#define DWC3_EP_PENDING_REQUEST (1 << 5)
388
389 /* This last one is specific to EP0 */
390#define DWC3_EP0_DIR_IN (1 << 31)
391
392 unsigned current_trb;
393
394 u8 number;
395 u8 type;
396 u8 res_trans_idx;
397 u32 interval;
398
399 char name[20];
400
401 unsigned direction:1;
402 unsigned stream_capable:1;
403};
404
405enum dwc3_phy {
406 DWC3_PHY_UNKNOWN = 0,
407 DWC3_PHY_USB3,
408 DWC3_PHY_USB2,
409};
410
411enum dwc3_ep0_next {
412 DWC3_EP0_UNKNOWN = 0,
413 DWC3_EP0_COMPLETE,
414 DWC3_EP0_NRDY_SETUP,
415 DWC3_EP0_NRDY_DATA,
416 DWC3_EP0_NRDY_STATUS,
417};
418
419enum dwc3_ep0_state {
420 EP0_UNCONNECTED = 0,
421 EP0_SETUP_PHASE,
422 EP0_DATA_PHASE,
423 EP0_STATUS_PHASE,
424};
425
426enum dwc3_link_state {
427 /* In SuperSpeed */
428 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
429 DWC3_LINK_STATE_U1 = 0x01,
430 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
431 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
432 DWC3_LINK_STATE_SS_DIS = 0x04,
433 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
434 DWC3_LINK_STATE_SS_INACT = 0x06,
435 DWC3_LINK_STATE_POLL = 0x07,
436 DWC3_LINK_STATE_RECOV = 0x08,
437 DWC3_LINK_STATE_HRESET = 0x09,
438 DWC3_LINK_STATE_CMPLY = 0x0a,
439 DWC3_LINK_STATE_LPBK = 0x0b,
440 DWC3_LINK_STATE_MASK = 0x0f,
441};
442
443enum dwc3_device_state {
444 DWC3_DEFAULT_STATE,
445 DWC3_ADDRESS_STATE,
446 DWC3_CONFIGURED_STATE,
447};
448
449/* TRB Length, PCM and Status */
450#define DWC3_TRB_SIZE_MASK (0x00ffffff)
451#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
452#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
453#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28) >> 28))
454
455#define DWC3_TRBSTS_OK 0
456#define DWC3_TRBSTS_MISSED_ISOC 1
457#define DWC3_TRBSTS_SETUP_PENDING 2
458
459/* TRB Control */
460#define DWC3_TRB_CTRL_HWO (1 << 0)
461#define DWC3_TRB_CTRL_LST (1 << 1)
462#define DWC3_TRB_CTRL_CHN (1 << 2)
463#define DWC3_TRB_CTRL_CSP (1 << 3)
464#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
465#define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
466#define DWC3_TRB_CTRL_IOC (1 << 11)
467#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
468
469#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
470#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
471#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
472#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
473#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
474#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
475#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
476#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
477
478/**
479 * struct dwc3_trb - transfer request block (hw format)
480 * @bpl: DW0-3
481 * @bph: DW4-7
482 * @size: DW8-B
483 * @trl: DWC-F
484 */
485struct dwc3_trb {
486 u32 bpl;
487 u32 bph;
488 u32 size;
489 u32 ctrl;
490} __packed;
491
492/**
493 * dwc3_hwparams - copy of HWPARAMS registers
494 * @hwparams0 - GHWPARAMS0
495 * @hwparams1 - GHWPARAMS1
496 * @hwparams2 - GHWPARAMS2
497 * @hwparams3 - GHWPARAMS3
498 * @hwparams4 - GHWPARAMS4
499 * @hwparams5 - GHWPARAMS5
500 * @hwparams6 - GHWPARAMS6
501 * @hwparams7 - GHWPARAMS7
502 * @hwparams8 - GHWPARAMS8
503 */
504struct dwc3_hwparams {
505 u32 hwparams0;
506 u32 hwparams1;
507 u32 hwparams2;
508 u32 hwparams3;
509 u32 hwparams4;
510 u32 hwparams5;
511 u32 hwparams6;
512 u32 hwparams7;
513 u32 hwparams8;
514};
515
516/* HWPARAMS0 */
517#define DWC3_MODE(n) ((n) & 0x7)
518
519#define DWC3_MODE_DEVICE 0
520#define DWC3_MODE_HOST 1
521#define DWC3_MODE_DRD 2
522#define DWC3_MODE_HUB 3
523
524#define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
525
526/* HWPARAMS1 */
527#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
528
529/* HWPARAMS7 */
530#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
531
532struct dwc3_request {
533 struct usb_request request;
534 struct list_head list;
535 struct dwc3_ep *dep;
536
537 u8 epnum;
538 struct dwc3_trb *trb;
539 dma_addr_t trb_dma;
540
541 unsigned direction:1;
542 unsigned mapped:1;
543 unsigned queued:1;
544};
545
546/**
547 * struct dwc3 - representation of our controller
548 * @ctrl_req: usb control request which is used for ep0
549 * @ep0_trb: trb which is used for the ctrl_req
550 * @ep0_bounce: bounce buffer for ep0
551 * @setup_buf: used while precessing STD USB requests
552 * @ctrl_req_addr: dma address of ctrl_req
553 * @ep0_trb: dma address of ep0_trb
554 * @ep0_usb_req: dummy req used while handling STD USB requests
555 * @ep0_bounce_addr: dma address of ep0_bounce
556 * @lock: for synchronizing
557 * @dev: pointer to our struct device
558 * @xhci: pointer to our xHCI child
559 * @event_buffer_list: a list of event buffers
560 * @gadget: device side representation of the peripheral controller
561 * @gadget_driver: pointer to the gadget driver
562 * @regs: base address for our registers
563 * @regs_size: address space size
564 * @irq: IRQ number
565 * @num_event_buffers: calculated number of event buffers
566 * @u1u2: only used on revisions <1.83a for workaround
567 * @maximum_speed: maximum speed requested (mainly for testing purposes)
568 * @revision: revision register contents
569 * @mode: mode of operation
570 * @is_selfpowered: true when we are selfpowered
571 * @three_stage_setup: set if we perform a three phase setup
572 * @ep0_bounced: true when we used bounce buffer
573 * @ep0_expect_in: true when we expect a DATA IN transfer
574 * @start_config_issued: true when StartConfig command has been issued
575 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
576 * @needs_fifo_resize: not all users might want fifo resizing, flag it
577 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes.
578 * @isoch_delay: wValue from Set Isochronous Delay request;
579 * @u2sel: parameter from Set SEL request.
580 * @u2pel: parameter from Set SEL request.
581 * @u1sel: parameter from Set SEL request.
582 * @u1pel: parameter from Set SEL request.
583 * @ep0_next_event: hold the next expected event
584 * @ep0state: state of endpoint zero
585 * @link_state: link state
586 * @speed: device speed (super, high, full, low)
587 * @mem: points to start of memory which is used for this struct.
588 * @hwparams: copy of hwparams registers
589 * @root: debugfs root folder pointer
590 */
591struct dwc3 {
592 struct usb_ctrlrequest *ctrl_req;
593 struct dwc3_trb *ep0_trb;
594 void *ep0_bounce;
595 u8 *setup_buf;
596 dma_addr_t ctrl_req_addr;
597 dma_addr_t ep0_trb_addr;
598 dma_addr_t ep0_bounce_addr;
599 struct dwc3_request ep0_usb_req;
600 /* device lock */
601 spinlock_t lock;
602 struct device *dev;
603
604 struct platform_device *xhci;
605 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
606
607 struct dwc3_event_buffer **ev_buffs;
608 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
609
610 struct usb_gadget gadget;
611 struct usb_gadget_driver *gadget_driver;
612
613 void __iomem *regs;
614 size_t regs_size;
615
616 u32 num_event_buffers;
617 u32 u1u2;
618 u32 maximum_speed;
619 u32 revision;
620 u32 mode;
621
622#define DWC3_REVISION_173A 0x5533173a
623#define DWC3_REVISION_175A 0x5533175a
624#define DWC3_REVISION_180A 0x5533180a
625#define DWC3_REVISION_183A 0x5533183a
626#define DWC3_REVISION_185A 0x5533185a
627#define DWC3_REVISION_188A 0x5533188a
628#define DWC3_REVISION_190A 0x5533190a
629#define DWC3_REVISION_200A 0x5533200a
630#define DWC3_REVISION_202A 0x5533202a
631#define DWC3_REVISION_210A 0x5533210a
632#define DWC3_REVISION_220A 0x5533220a
633
634 unsigned is_selfpowered:1;
635 unsigned three_stage_setup:1;
636 unsigned ep0_bounced:1;
637 unsigned ep0_expect_in:1;
638 unsigned start_config_issued:1;
639 unsigned setup_packet_pending:1;
640 unsigned delayed_status:1;
641 unsigned needs_fifo_resize:1;
642 unsigned resize_fifos:1;
643
644 enum dwc3_ep0_next ep0_next_event;
645 enum dwc3_ep0_state ep0state;
646 enum dwc3_link_state link_state;
647 enum dwc3_device_state dev_state;
648
649 u16 isoch_delay;
650 u16 u2sel;
651 u16 u2pel;
652 u8 u1sel;
653 u8 u1pel;
654
655 u8 speed;
656
657 void *mem;
658
659 struct dwc3_hwparams hwparams;
660 struct dentry *root;
661
662 u8 test_mode;
663 u8 test_mode_nr;
664};
665
666/* -------------------------------------------------------------------------- */
667
668/* -------------------------------------------------------------------------- */
669
670struct dwc3_event_type {
671 u32 is_devspec:1;
672 u32 type:6;
673 u32 reserved8_31:25;
674} __packed;
675
676#define DWC3_DEPEVT_XFERCOMPLETE 0x01
677#define DWC3_DEPEVT_XFERINPROGRESS 0x02
678#define DWC3_DEPEVT_XFERNOTREADY 0x03
679#define DWC3_DEPEVT_RXTXFIFOEVT 0x04
680#define DWC3_DEPEVT_STREAMEVT 0x06
681#define DWC3_DEPEVT_EPCMDCMPLT 0x07
682
683/**
684 * struct dwc3_event_depvt - Device Endpoint Events
685 * @one_bit: indicates this is an endpoint event (not used)
686 * @endpoint_number: number of the endpoint
687 * @endpoint_event: The event we have:
688 * 0x00 - Reserved
689 * 0x01 - XferComplete
690 * 0x02 - XferInProgress
691 * 0x03 - XferNotReady
692 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
693 * 0x05 - Reserved
694 * 0x06 - StreamEvt
695 * 0x07 - EPCmdCmplt
696 * @reserved11_10: Reserved, don't use.
697 * @status: Indicates the status of the event. Refer to databook for
698 * more information.
699 * @parameters: Parameters of the current event. Refer to databook for
700 * more information.
701 */
702struct dwc3_event_depevt {
703 u32 one_bit:1;
704 u32 endpoint_number:5;
705 u32 endpoint_event:4;
706 u32 reserved11_10:2;
707 u32 status:4;
708
709/* Within XferNotReady */
710#define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
711
712/* Within XferComplete */
713#define DEPEVT_STATUS_BUSERR (1 << 0)
714#define DEPEVT_STATUS_SHORT (1 << 1)
715#define DEPEVT_STATUS_IOC (1 << 2)
716#define DEPEVT_STATUS_LST (1 << 3)
717
718/* Stream event only */
719#define DEPEVT_STREAMEVT_FOUND 1
720#define DEPEVT_STREAMEVT_NOTFOUND 2
721
722/* Control-only Status */
723#define DEPEVT_STATUS_CONTROL_SETUP 0
724#define DEPEVT_STATUS_CONTROL_DATA 1
725#define DEPEVT_STATUS_CONTROL_STATUS 2
726
727 u32 parameters:16;
728} __packed;
729
730/**
731 * struct dwc3_event_devt - Device Events
732 * @one_bit: indicates this is a non-endpoint event (not used)
733 * @device_event: indicates it's a device event. Should read as 0x00
734 * @type: indicates the type of device event.
735 * 0 - DisconnEvt
736 * 1 - USBRst
737 * 2 - ConnectDone
738 * 3 - ULStChng
739 * 4 - WkUpEvt
740 * 5 - Reserved
741 * 6 - EOPF
742 * 7 - SOF
743 * 8 - Reserved
744 * 9 - ErrticErr
745 * 10 - CmdCmplt
746 * 11 - EvntOverflow
747 * 12 - VndrDevTstRcved
748 * @reserved15_12: Reserved, not used
749 * @event_info: Information about this event
750 * @reserved31_24: Reserved, not used
751 */
752struct dwc3_event_devt {
753 u32 one_bit:1;
754 u32 device_event:7;
755 u32 type:4;
756 u32 reserved15_12:4;
757 u32 event_info:8;
758 u32 reserved31_24:8;
759} __packed;
760
761/**
762 * struct dwc3_event_gevt - Other Core Events
763 * @one_bit: indicates this is a non-endpoint event (not used)
764 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
765 * @phy_port_number: self-explanatory
766 * @reserved31_12: Reserved, not used.
767 */
768struct dwc3_event_gevt {
769 u32 one_bit:1;
770 u32 device_event:7;
771 u32 phy_port_number:4;
772 u32 reserved31_12:20;
773} __packed;
774
775/**
776 * union dwc3_event - representation of Event Buffer contents
777 * @raw: raw 32-bit event
778 * @type: the type of the event
779 * @depevt: Device Endpoint Event
780 * @devt: Device Event
781 * @gevt: Global Event
782 */
783union dwc3_event {
784 u32 raw;
785 struct dwc3_event_type type;
786 struct dwc3_event_depevt depevt;
787 struct dwc3_event_devt devt;
788 struct dwc3_event_gevt gevt;
789};
790
791/*
792 * DWC3 Features to be used as Driver Data
793 */
794
795#define DWC3_HAS_PERIPHERAL BIT(0)
796#define DWC3_HAS_XHCI BIT(1)
797#define DWC3_HAS_OTG BIT(3)
798
799/* prototypes */
800void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
801int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
802
803int dwc3_host_init(struct dwc3 *dwc);
804void dwc3_host_exit(struct dwc3 *dwc);
805
806int dwc3_gadget_init(struct dwc3 *dwc);
807void dwc3_gadget_exit(struct dwc3 *dwc);
808
809extern int dwc3_get_device_id(void);
810extern void dwc3_put_device_id(int id);
811
812#endif /* __DRIVERS_USB_DWC3_CORE_H */