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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/console.h>
29#include <linux/slab.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
33#include <linux/vgaarb.h>
34#include <linux/vga_switcheroo.h>
35#include <linux/efi.h>
36#include "radeon_reg.h"
37#include "radeon.h"
38#include "atom.h"
39
40static const char radeon_family_name[][16] = {
41 "R100",
42 "RV100",
43 "RS100",
44 "RV200",
45 "RS200",
46 "R200",
47 "RV250",
48 "RS300",
49 "RV280",
50 "R300",
51 "R350",
52 "RV350",
53 "RV380",
54 "R420",
55 "R423",
56 "RV410",
57 "RS400",
58 "RS480",
59 "RS600",
60 "RS690",
61 "RS740",
62 "RV515",
63 "R520",
64 "RV530",
65 "RV560",
66 "RV570",
67 "R580",
68 "R600",
69 "RV610",
70 "RV630",
71 "RV670",
72 "RV620",
73 "RV635",
74 "RS780",
75 "RS880",
76 "RV770",
77 "RV730",
78 "RV710",
79 "RV740",
80 "CEDAR",
81 "REDWOOD",
82 "JUNIPER",
83 "CYPRESS",
84 "HEMLOCK",
85 "PALM",
86 "SUMO",
87 "SUMO2",
88 "BARTS",
89 "TURKS",
90 "CAICOS",
91 "CAYMAN",
92 "LAST",
93};
94
95/*
96 * Clear GPU surface registers.
97 */
98void radeon_surface_init(struct radeon_device *rdev)
99{
100 /* FIXME: check this out */
101 if (rdev->family < CHIP_R600) {
102 int i;
103
104 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
105 if (rdev->surface_regs[i].bo)
106 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
107 else
108 radeon_clear_surface_reg(rdev, i);
109 }
110 /* enable surfaces */
111 WREG32(RADEON_SURFACE_CNTL, 0);
112 }
113}
114
115/*
116 * GPU scratch registers helpers function.
117 */
118void radeon_scratch_init(struct radeon_device *rdev)
119{
120 int i;
121
122 /* FIXME: check this out */
123 if (rdev->family < CHIP_R300) {
124 rdev->scratch.num_reg = 5;
125 } else {
126 rdev->scratch.num_reg = 7;
127 }
128 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
129 for (i = 0; i < rdev->scratch.num_reg; i++) {
130 rdev->scratch.free[i] = true;
131 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
132 }
133}
134
135int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
136{
137 int i;
138
139 for (i = 0; i < rdev->scratch.num_reg; i++) {
140 if (rdev->scratch.free[i]) {
141 rdev->scratch.free[i] = false;
142 *reg = rdev->scratch.reg[i];
143 return 0;
144 }
145 }
146 return -EINVAL;
147}
148
149void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
150{
151 int i;
152
153 for (i = 0; i < rdev->scratch.num_reg; i++) {
154 if (rdev->scratch.reg[i] == reg) {
155 rdev->scratch.free[i] = true;
156 return;
157 }
158 }
159}
160
161void radeon_wb_disable(struct radeon_device *rdev)
162{
163 int r;
164
165 if (rdev->wb.wb_obj) {
166 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
167 if (unlikely(r != 0))
168 return;
169 radeon_bo_kunmap(rdev->wb.wb_obj);
170 radeon_bo_unpin(rdev->wb.wb_obj);
171 radeon_bo_unreserve(rdev->wb.wb_obj);
172 }
173 rdev->wb.enabled = false;
174}
175
176void radeon_wb_fini(struct radeon_device *rdev)
177{
178 radeon_wb_disable(rdev);
179 if (rdev->wb.wb_obj) {
180 radeon_bo_unref(&rdev->wb.wb_obj);
181 rdev->wb.wb = NULL;
182 rdev->wb.wb_obj = NULL;
183 }
184}
185
186int radeon_wb_init(struct radeon_device *rdev)
187{
188 int r;
189
190 if (rdev->wb.wb_obj == NULL) {
191 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
192 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
193 if (r) {
194 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
195 return r;
196 }
197 }
198 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
199 if (unlikely(r != 0)) {
200 radeon_wb_fini(rdev);
201 return r;
202 }
203 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
204 &rdev->wb.gpu_addr);
205 if (r) {
206 radeon_bo_unreserve(rdev->wb.wb_obj);
207 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
208 radeon_wb_fini(rdev);
209 return r;
210 }
211 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
212 radeon_bo_unreserve(rdev->wb.wb_obj);
213 if (r) {
214 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
215 radeon_wb_fini(rdev);
216 return r;
217 }
218
219 /* clear wb memory */
220 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
221 /* disable event_write fences */
222 rdev->wb.use_event = false;
223 /* disabled via module param */
224 if (radeon_no_wb == 1)
225 rdev->wb.enabled = false;
226 else {
227 /* often unreliable on AGP */
228 if (rdev->flags & RADEON_IS_AGP) {
229 rdev->wb.enabled = false;
230 } else {
231 rdev->wb.enabled = true;
232 /* event_write fences are only available on r600+ */
233 if (rdev->family >= CHIP_R600)
234 rdev->wb.use_event = true;
235 }
236 }
237 /* always use writeback/events on NI */
238 if (ASIC_IS_DCE5(rdev)) {
239 rdev->wb.enabled = true;
240 rdev->wb.use_event = true;
241 }
242
243 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
244
245 return 0;
246}
247
248/**
249 * radeon_vram_location - try to find VRAM location
250 * @rdev: radeon device structure holding all necessary informations
251 * @mc: memory controller structure holding memory informations
252 * @base: base address at which to put VRAM
253 *
254 * Function will place try to place VRAM at base address provided
255 * as parameter (which is so far either PCI aperture address or
256 * for IGP TOM base address).
257 *
258 * If there is not enough space to fit the unvisible VRAM in the 32bits
259 * address space then we limit the VRAM size to the aperture.
260 *
261 * If we are using AGP and if the AGP aperture doesn't allow us to have
262 * room for all the VRAM than we restrict the VRAM to the PCI aperture
263 * size and print a warning.
264 *
265 * This function will never fails, worst case are limiting VRAM.
266 *
267 * Note: GTT start, end, size should be initialized before calling this
268 * function on AGP platform.
269 *
270 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
271 * this shouldn't be a problem as we are using the PCI aperture as a reference.
272 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
273 * not IGP.
274 *
275 * Note: we use mc_vram_size as on some board we need to program the mc to
276 * cover the whole aperture even if VRAM size is inferior to aperture size
277 * Novell bug 204882 + along with lots of ubuntu ones
278 *
279 * Note: when limiting vram it's safe to overwritte real_vram_size because
280 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
281 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
282 * ones)
283 *
284 * Note: IGP TOM addr should be the same as the aperture addr, we don't
285 * explicitly check for that thought.
286 *
287 * FIXME: when reducing VRAM size align new size on power of 2.
288 */
289void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
290{
291 mc->vram_start = base;
292 if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
293 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
294 mc->real_vram_size = mc->aper_size;
295 mc->mc_vram_size = mc->aper_size;
296 }
297 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
298 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
299 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
300 mc->real_vram_size = mc->aper_size;
301 mc->mc_vram_size = mc->aper_size;
302 }
303 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
304 if (radeon_vram_limit && radeon_vram_limit < mc->real_vram_size)
305 mc->real_vram_size = radeon_vram_limit;
306 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
307 mc->mc_vram_size >> 20, mc->vram_start,
308 mc->vram_end, mc->real_vram_size >> 20);
309}
310
311/**
312 * radeon_gtt_location - try to find GTT location
313 * @rdev: radeon device structure holding all necessary informations
314 * @mc: memory controller structure holding memory informations
315 *
316 * Function will place try to place GTT before or after VRAM.
317 *
318 * If GTT size is bigger than space left then we ajust GTT size.
319 * Thus function will never fails.
320 *
321 * FIXME: when reducing GTT size align new size on power of 2.
322 */
323void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
324{
325 u64 size_af, size_bf;
326
327 size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
328 size_bf = mc->vram_start & ~mc->gtt_base_align;
329 if (size_bf > size_af) {
330 if (mc->gtt_size > size_bf) {
331 dev_warn(rdev->dev, "limiting GTT\n");
332 mc->gtt_size = size_bf;
333 }
334 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
335 } else {
336 if (mc->gtt_size > size_af) {
337 dev_warn(rdev->dev, "limiting GTT\n");
338 mc->gtt_size = size_af;
339 }
340 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
341 }
342 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
343 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
344 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
345}
346
347/*
348 * GPU helpers function.
349 */
350bool radeon_card_posted(struct radeon_device *rdev)
351{
352 uint32_t reg;
353
354 if (efi_enabled && rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE)
355 return false;
356
357 /* first check CRTCs */
358 if (ASIC_IS_DCE41(rdev)) {
359 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
360 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
361 if (reg & EVERGREEN_CRTC_MASTER_EN)
362 return true;
363 } else if (ASIC_IS_DCE4(rdev)) {
364 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
365 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
366 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
367 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
368 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
369 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
370 if (reg & EVERGREEN_CRTC_MASTER_EN)
371 return true;
372 } else if (ASIC_IS_AVIVO(rdev)) {
373 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
374 RREG32(AVIVO_D2CRTC_CONTROL);
375 if (reg & AVIVO_CRTC_EN) {
376 return true;
377 }
378 } else {
379 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
380 RREG32(RADEON_CRTC2_GEN_CNTL);
381 if (reg & RADEON_CRTC_EN) {
382 return true;
383 }
384 }
385
386 /* then check MEM_SIZE, in case the crtcs are off */
387 if (rdev->family >= CHIP_R600)
388 reg = RREG32(R600_CONFIG_MEMSIZE);
389 else
390 reg = RREG32(RADEON_CONFIG_MEMSIZE);
391
392 if (reg)
393 return true;
394
395 return false;
396
397}
398
399void radeon_update_bandwidth_info(struct radeon_device *rdev)
400{
401 fixed20_12 a;
402 u32 sclk = rdev->pm.current_sclk;
403 u32 mclk = rdev->pm.current_mclk;
404
405 /* sclk/mclk in Mhz */
406 a.full = dfixed_const(100);
407 rdev->pm.sclk.full = dfixed_const(sclk);
408 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
409 rdev->pm.mclk.full = dfixed_const(mclk);
410 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
411
412 if (rdev->flags & RADEON_IS_IGP) {
413 a.full = dfixed_const(16);
414 /* core_bandwidth = sclk(Mhz) * 16 */
415 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
416 }
417}
418
419bool radeon_boot_test_post_card(struct radeon_device *rdev)
420{
421 if (radeon_card_posted(rdev))
422 return true;
423
424 if (rdev->bios) {
425 DRM_INFO("GPU not posted. posting now...\n");
426 if (rdev->is_atom_bios)
427 atom_asic_init(rdev->mode_info.atom_context);
428 else
429 radeon_combios_asic_init(rdev->ddev);
430 return true;
431 } else {
432 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
433 return false;
434 }
435}
436
437int radeon_dummy_page_init(struct radeon_device *rdev)
438{
439 if (rdev->dummy_page.page)
440 return 0;
441 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
442 if (rdev->dummy_page.page == NULL)
443 return -ENOMEM;
444 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
445 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
446 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
447 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
448 __free_page(rdev->dummy_page.page);
449 rdev->dummy_page.page = NULL;
450 return -ENOMEM;
451 }
452 return 0;
453}
454
455void radeon_dummy_page_fini(struct radeon_device *rdev)
456{
457 if (rdev->dummy_page.page == NULL)
458 return;
459 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
460 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
461 __free_page(rdev->dummy_page.page);
462 rdev->dummy_page.page = NULL;
463}
464
465
466/* ATOM accessor methods */
467static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
468{
469 struct radeon_device *rdev = info->dev->dev_private;
470 uint32_t r;
471
472 r = rdev->pll_rreg(rdev, reg);
473 return r;
474}
475
476static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
477{
478 struct radeon_device *rdev = info->dev->dev_private;
479
480 rdev->pll_wreg(rdev, reg, val);
481}
482
483static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
484{
485 struct radeon_device *rdev = info->dev->dev_private;
486 uint32_t r;
487
488 r = rdev->mc_rreg(rdev, reg);
489 return r;
490}
491
492static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
493{
494 struct radeon_device *rdev = info->dev->dev_private;
495
496 rdev->mc_wreg(rdev, reg, val);
497}
498
499static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
500{
501 struct radeon_device *rdev = info->dev->dev_private;
502
503 WREG32(reg*4, val);
504}
505
506static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
507{
508 struct radeon_device *rdev = info->dev->dev_private;
509 uint32_t r;
510
511 r = RREG32(reg*4);
512 return r;
513}
514
515static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
516{
517 struct radeon_device *rdev = info->dev->dev_private;
518
519 WREG32_IO(reg*4, val);
520}
521
522static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
523{
524 struct radeon_device *rdev = info->dev->dev_private;
525 uint32_t r;
526
527 r = RREG32_IO(reg*4);
528 return r;
529}
530
531int radeon_atombios_init(struct radeon_device *rdev)
532{
533 struct card_info *atom_card_info =
534 kzalloc(sizeof(struct card_info), GFP_KERNEL);
535
536 if (!atom_card_info)
537 return -ENOMEM;
538
539 rdev->mode_info.atom_card_info = atom_card_info;
540 atom_card_info->dev = rdev->ddev;
541 atom_card_info->reg_read = cail_reg_read;
542 atom_card_info->reg_write = cail_reg_write;
543 /* needed for iio ops */
544 if (rdev->rio_mem) {
545 atom_card_info->ioreg_read = cail_ioreg_read;
546 atom_card_info->ioreg_write = cail_ioreg_write;
547 } else {
548 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
549 atom_card_info->ioreg_read = cail_reg_read;
550 atom_card_info->ioreg_write = cail_reg_write;
551 }
552 atom_card_info->mc_read = cail_mc_read;
553 atom_card_info->mc_write = cail_mc_write;
554 atom_card_info->pll_read = cail_pll_read;
555 atom_card_info->pll_write = cail_pll_write;
556
557 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
558 mutex_init(&rdev->mode_info.atom_context->mutex);
559 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
560 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
561 return 0;
562}
563
564void radeon_atombios_fini(struct radeon_device *rdev)
565{
566 if (rdev->mode_info.atom_context) {
567 kfree(rdev->mode_info.atom_context->scratch);
568 kfree(rdev->mode_info.atom_context);
569 }
570 kfree(rdev->mode_info.atom_card_info);
571}
572
573int radeon_combios_init(struct radeon_device *rdev)
574{
575 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
576 return 0;
577}
578
579void radeon_combios_fini(struct radeon_device *rdev)
580{
581}
582
583/* if we get transitioned to only one device, tak VGA back */
584static unsigned int radeon_vga_set_decode(void *cookie, bool state)
585{
586 struct radeon_device *rdev = cookie;
587 radeon_vga_set_state(rdev, state);
588 if (state)
589 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
590 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
591 else
592 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
593}
594
595void radeon_check_arguments(struct radeon_device *rdev)
596{
597 /* vramlimit must be a power of two */
598 switch (radeon_vram_limit) {
599 case 0:
600 case 4:
601 case 8:
602 case 16:
603 case 32:
604 case 64:
605 case 128:
606 case 256:
607 case 512:
608 case 1024:
609 case 2048:
610 case 4096:
611 break;
612 default:
613 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
614 radeon_vram_limit);
615 radeon_vram_limit = 0;
616 break;
617 }
618 radeon_vram_limit = radeon_vram_limit << 20;
619 /* gtt size must be power of two and greater or equal to 32M */
620 switch (radeon_gart_size) {
621 case 4:
622 case 8:
623 case 16:
624 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
625 radeon_gart_size);
626 radeon_gart_size = 512;
627 break;
628 case 32:
629 case 64:
630 case 128:
631 case 256:
632 case 512:
633 case 1024:
634 case 2048:
635 case 4096:
636 break;
637 default:
638 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
639 radeon_gart_size);
640 radeon_gart_size = 512;
641 break;
642 }
643 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
644 /* AGP mode can only be -1, 1, 2, 4, 8 */
645 switch (radeon_agpmode) {
646 case -1:
647 case 0:
648 case 1:
649 case 2:
650 case 4:
651 case 8:
652 break;
653 default:
654 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
655 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
656 radeon_agpmode = 0;
657 break;
658 }
659}
660
661static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
662{
663 struct drm_device *dev = pci_get_drvdata(pdev);
664 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
665 if (state == VGA_SWITCHEROO_ON) {
666 printk(KERN_INFO "radeon: switched on\n");
667 /* don't suspend or resume card normally */
668 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
669 radeon_resume_kms(dev);
670 dev->switch_power_state = DRM_SWITCH_POWER_ON;
671 drm_kms_helper_poll_enable(dev);
672 } else {
673 printk(KERN_INFO "radeon: switched off\n");
674 drm_kms_helper_poll_disable(dev);
675 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
676 radeon_suspend_kms(dev, pmm);
677 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
678 }
679}
680
681static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
682{
683 struct drm_device *dev = pci_get_drvdata(pdev);
684 bool can_switch;
685
686 spin_lock(&dev->count_lock);
687 can_switch = (dev->open_count == 0);
688 spin_unlock(&dev->count_lock);
689 return can_switch;
690}
691
692
693int radeon_device_init(struct radeon_device *rdev,
694 struct drm_device *ddev,
695 struct pci_dev *pdev,
696 uint32_t flags)
697{
698 int r, i;
699 int dma_bits;
700
701 rdev->shutdown = false;
702 rdev->dev = &pdev->dev;
703 rdev->ddev = ddev;
704 rdev->pdev = pdev;
705 rdev->flags = flags;
706 rdev->family = flags & RADEON_FAMILY_MASK;
707 rdev->is_atom_bios = false;
708 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
709 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
710 rdev->gpu_lockup = false;
711 rdev->accel_working = false;
712
713 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
714 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
715 pdev->subsystem_vendor, pdev->subsystem_device);
716
717 /* mutex initialization are all done here so we
718 * can recall function without having locking issues */
719 mutex_init(&rdev->cs_mutex);
720 mutex_init(&rdev->ib_pool.mutex);
721 mutex_init(&rdev->cp.mutex);
722 mutex_init(&rdev->dc_hw_i2c_mutex);
723 if (rdev->family >= CHIP_R600)
724 spin_lock_init(&rdev->ih.lock);
725 mutex_init(&rdev->gem.mutex);
726 mutex_init(&rdev->pm.mutex);
727 mutex_init(&rdev->vram_mutex);
728 rwlock_init(&rdev->fence_drv.lock);
729 INIT_LIST_HEAD(&rdev->gem.objects);
730 init_waitqueue_head(&rdev->irq.vblank_queue);
731 init_waitqueue_head(&rdev->irq.idle_queue);
732
733 /* Set asic functions */
734 r = radeon_asic_init(rdev);
735 if (r)
736 return r;
737 radeon_check_arguments(rdev);
738
739 /* all of the newer IGP chips have an internal gart
740 * However some rs4xx report as AGP, so remove that here.
741 */
742 if ((rdev->family >= CHIP_RS400) &&
743 (rdev->flags & RADEON_IS_IGP)) {
744 rdev->flags &= ~RADEON_IS_AGP;
745 }
746
747 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
748 radeon_agp_disable(rdev);
749 }
750
751 /* set DMA mask + need_dma32 flags.
752 * PCIE - can handle 40-bits.
753 * IGP - can handle 40-bits (in theory)
754 * AGP - generally dma32 is safest
755 * PCI - only dma32
756 */
757 rdev->need_dma32 = false;
758 if (rdev->flags & RADEON_IS_AGP)
759 rdev->need_dma32 = true;
760 if (rdev->flags & RADEON_IS_PCI)
761 rdev->need_dma32 = true;
762
763 dma_bits = rdev->need_dma32 ? 32 : 40;
764 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
765 if (r) {
766 rdev->need_dma32 = true;
767 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
768 }
769
770 /* Registers mapping */
771 /* TODO: block userspace mapping of io register */
772 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
773 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
774 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
775 if (rdev->rmmio == NULL) {
776 return -ENOMEM;
777 }
778 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
779 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
780
781 /* io port mapping */
782 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
783 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
784 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
785 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
786 break;
787 }
788 }
789 if (rdev->rio_mem == NULL)
790 DRM_ERROR("Unable to find PCI I/O BAR\n");
791
792 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
793 /* this will fail for cards that aren't VGA class devices, just
794 * ignore it */
795 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
796 vga_switcheroo_register_client(rdev->pdev,
797 radeon_switcheroo_set_state,
798 NULL,
799 radeon_switcheroo_can_switch);
800
801 r = radeon_init(rdev);
802 if (r)
803 return r;
804
805 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
806 /* Acceleration not working on AGP card try again
807 * with fallback to PCI or PCIE GART
808 */
809 radeon_asic_reset(rdev);
810 radeon_fini(rdev);
811 radeon_agp_disable(rdev);
812 r = radeon_init(rdev);
813 if (r)
814 return r;
815 }
816 if (radeon_testing) {
817 radeon_test_moves(rdev);
818 }
819 if (radeon_benchmarking) {
820 radeon_benchmark(rdev);
821 }
822 return 0;
823}
824
825void radeon_device_fini(struct radeon_device *rdev)
826{
827 DRM_INFO("radeon: finishing device.\n");
828 rdev->shutdown = true;
829 /* evict vram memory */
830 radeon_bo_evict_vram(rdev);
831 radeon_fini(rdev);
832 vga_switcheroo_unregister_client(rdev->pdev);
833 vga_client_register(rdev->pdev, NULL, NULL, NULL);
834 if (rdev->rio_mem)
835 pci_iounmap(rdev->pdev, rdev->rio_mem);
836 rdev->rio_mem = NULL;
837 iounmap(rdev->rmmio);
838 rdev->rmmio = NULL;
839}
840
841
842/*
843 * Suspend & resume.
844 */
845int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
846{
847 struct radeon_device *rdev;
848 struct drm_crtc *crtc;
849 struct drm_connector *connector;
850 int r;
851
852 if (dev == NULL || dev->dev_private == NULL) {
853 return -ENODEV;
854 }
855 if (state.event == PM_EVENT_PRETHAW) {
856 return 0;
857 }
858 rdev = dev->dev_private;
859
860 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
861 return 0;
862
863 /* turn off display hw */
864 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
865 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
866 }
867
868 /* unpin the front buffers */
869 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
870 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
871 struct radeon_bo *robj;
872
873 if (rfb == NULL || rfb->obj == NULL) {
874 continue;
875 }
876 robj = gem_to_radeon_bo(rfb->obj);
877 /* don't unpin kernel fb objects */
878 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
879 r = radeon_bo_reserve(robj, false);
880 if (r == 0) {
881 radeon_bo_unpin(robj);
882 radeon_bo_unreserve(robj);
883 }
884 }
885 }
886 /* evict vram memory */
887 radeon_bo_evict_vram(rdev);
888 /* wait for gpu to finish processing current batch */
889 radeon_fence_wait_last(rdev);
890
891 radeon_save_bios_scratch_regs(rdev);
892
893 radeon_pm_suspend(rdev);
894 radeon_suspend(rdev);
895 radeon_hpd_fini(rdev);
896 /* evict remaining vram memory */
897 radeon_bo_evict_vram(rdev);
898
899 radeon_agp_suspend(rdev);
900
901 pci_save_state(dev->pdev);
902 if (state.event == PM_EVENT_SUSPEND) {
903 /* Shut down the device */
904 pci_disable_device(dev->pdev);
905 pci_set_power_state(dev->pdev, PCI_D3hot);
906 }
907 console_lock();
908 radeon_fbdev_set_suspend(rdev, 1);
909 console_unlock();
910 return 0;
911}
912
913int radeon_resume_kms(struct drm_device *dev)
914{
915 struct drm_connector *connector;
916 struct radeon_device *rdev = dev->dev_private;
917
918 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
919 return 0;
920
921 console_lock();
922 pci_set_power_state(dev->pdev, PCI_D0);
923 pci_restore_state(dev->pdev);
924 if (pci_enable_device(dev->pdev)) {
925 console_unlock();
926 return -1;
927 }
928 pci_set_master(dev->pdev);
929 /* resume AGP if in use */
930 radeon_agp_resume(rdev);
931 radeon_resume(rdev);
932 radeon_pm_resume(rdev);
933 radeon_restore_bios_scratch_regs(rdev);
934
935 radeon_fbdev_set_suspend(rdev, 0);
936 console_unlock();
937
938 /* init dig PHYs */
939 if (rdev->is_atom_bios)
940 radeon_atom_encoder_init(rdev);
941 /* reset hpd state */
942 radeon_hpd_init(rdev);
943 /* blat the mode back in */
944 drm_helper_resume_force_mode(dev);
945 /* turn on display hw */
946 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
947 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
948 }
949 return 0;
950}
951
952int radeon_gpu_reset(struct radeon_device *rdev)
953{
954 int r;
955 int resched;
956
957 radeon_save_bios_scratch_regs(rdev);
958 /* block TTM */
959 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
960 radeon_suspend(rdev);
961
962 r = radeon_asic_reset(rdev);
963 if (!r) {
964 dev_info(rdev->dev, "GPU reset succeed\n");
965 radeon_resume(rdev);
966 radeon_restore_bios_scratch_regs(rdev);
967 drm_helper_resume_force_mode(rdev->ddev);
968 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
969 return 0;
970 }
971 /* bad news, how to tell it to userspace ? */
972 dev_info(rdev->dev, "GPU reset failed\n");
973 return r;
974}
975
976
977/*
978 * Debugfs
979 */
980struct radeon_debugfs {
981 struct drm_info_list *files;
982 unsigned num_files;
983};
984static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
985static unsigned _radeon_debugfs_count = 0;
986
987int radeon_debugfs_add_files(struct radeon_device *rdev,
988 struct drm_info_list *files,
989 unsigned nfiles)
990{
991 unsigned i;
992
993 for (i = 0; i < _radeon_debugfs_count; i++) {
994 if (_radeon_debugfs[i].files == files) {
995 /* Already registered */
996 return 0;
997 }
998 }
999 if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
1000 DRM_ERROR("Reached maximum number of debugfs files.\n");
1001 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
1002 return -EINVAL;
1003 }
1004 _radeon_debugfs[_radeon_debugfs_count].files = files;
1005 _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
1006 _radeon_debugfs_count++;
1007#if defined(CONFIG_DEBUG_FS)
1008 drm_debugfs_create_files(files, nfiles,
1009 rdev->ddev->control->debugfs_root,
1010 rdev->ddev->control);
1011 drm_debugfs_create_files(files, nfiles,
1012 rdev->ddev->primary->debugfs_root,
1013 rdev->ddev->primary);
1014#endif
1015 return 0;
1016}
1017
1018#if defined(CONFIG_DEBUG_FS)
1019int radeon_debugfs_init(struct drm_minor *minor)
1020{
1021 return 0;
1022}
1023
1024void radeon_debugfs_cleanup(struct drm_minor *minor)
1025{
1026 unsigned i;
1027
1028 for (i = 0; i < _radeon_debugfs_count; i++) {
1029 drm_debugfs_remove_files(_radeon_debugfs[i].files,
1030 _radeon_debugfs[i].num_files, minor);
1031 }
1032}
1033#endif
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/console.h>
29#include <linux/slab.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/drm_cache.h>
33#include <drm/radeon_drm.h>
34#include <linux/pm_runtime.h>
35#include <linux/vgaarb.h>
36#include <linux/vga_switcheroo.h>
37#include <linux/efi.h>
38#include "radeon_reg.h"
39#include "radeon.h"
40#include "atom.h"
41
42static const char radeon_family_name[][16] = {
43 "R100",
44 "RV100",
45 "RS100",
46 "RV200",
47 "RS200",
48 "R200",
49 "RV250",
50 "RS300",
51 "RV280",
52 "R300",
53 "R350",
54 "RV350",
55 "RV380",
56 "R420",
57 "R423",
58 "RV410",
59 "RS400",
60 "RS480",
61 "RS600",
62 "RS690",
63 "RS740",
64 "RV515",
65 "R520",
66 "RV530",
67 "RV560",
68 "RV570",
69 "R580",
70 "R600",
71 "RV610",
72 "RV630",
73 "RV670",
74 "RV620",
75 "RV635",
76 "RS780",
77 "RS880",
78 "RV770",
79 "RV730",
80 "RV710",
81 "RV740",
82 "CEDAR",
83 "REDWOOD",
84 "JUNIPER",
85 "CYPRESS",
86 "HEMLOCK",
87 "PALM",
88 "SUMO",
89 "SUMO2",
90 "BARTS",
91 "TURKS",
92 "CAICOS",
93 "CAYMAN",
94 "ARUBA",
95 "TAHITI",
96 "PITCAIRN",
97 "VERDE",
98 "OLAND",
99 "HAINAN",
100 "BONAIRE",
101 "KAVERI",
102 "KABINI",
103 "HAWAII",
104 "MULLINS",
105 "LAST",
106};
107
108#if defined(CONFIG_VGA_SWITCHEROO)
109bool radeon_has_atpx_dgpu_power_cntl(void);
110bool radeon_is_atpx_hybrid(void);
111#else
112static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
113static inline bool radeon_is_atpx_hybrid(void) { return false; }
114#endif
115
116#define RADEON_PX_QUIRK_DISABLE_PX (1 << 0)
117
118struct radeon_px_quirk {
119 u32 chip_vendor;
120 u32 chip_device;
121 u32 subsys_vendor;
122 u32 subsys_device;
123 u32 px_quirk_flags;
124};
125
126static struct radeon_px_quirk radeon_px_quirk_list[] = {
127 /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m)
128 * https://bugzilla.kernel.org/show_bug.cgi?id=74551
129 */
130 { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX },
131 /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU
132 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
133 */
134 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX },
135 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
136 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
137 */
138 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX },
139 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
140 * https://bugs.freedesktop.org/show_bug.cgi?id=101491
141 */
142 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX },
143 /* Asus K73TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
144 * https://bugzilla.kernel.org/show_bug.cgi?id=51381#c52
145 */
146 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2123, RADEON_PX_QUIRK_DISABLE_PX },
147 { 0, 0, 0, 0, 0 },
148};
149
150bool radeon_is_px(struct drm_device *dev)
151{
152 struct radeon_device *rdev = dev->dev_private;
153
154 if (rdev->flags & RADEON_IS_PX)
155 return true;
156 return false;
157}
158
159static void radeon_device_handle_px_quirks(struct radeon_device *rdev)
160{
161 struct radeon_px_quirk *p = radeon_px_quirk_list;
162
163 /* Apply PX quirks */
164 while (p && p->chip_device != 0) {
165 if (rdev->pdev->vendor == p->chip_vendor &&
166 rdev->pdev->device == p->chip_device &&
167 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
168 rdev->pdev->subsystem_device == p->subsys_device) {
169 rdev->px_quirk_flags = p->px_quirk_flags;
170 break;
171 }
172 ++p;
173 }
174
175 if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX)
176 rdev->flags &= ~RADEON_IS_PX;
177
178 /* disable PX is the system doesn't support dGPU power control or hybrid gfx */
179 if (!radeon_is_atpx_hybrid() &&
180 !radeon_has_atpx_dgpu_power_cntl())
181 rdev->flags &= ~RADEON_IS_PX;
182}
183
184/**
185 * radeon_program_register_sequence - program an array of registers.
186 *
187 * @rdev: radeon_device pointer
188 * @registers: pointer to the register array
189 * @array_size: size of the register array
190 *
191 * Programs an array or registers with and and or masks.
192 * This is a helper for setting golden registers.
193 */
194void radeon_program_register_sequence(struct radeon_device *rdev,
195 const u32 *registers,
196 const u32 array_size)
197{
198 u32 tmp, reg, and_mask, or_mask;
199 int i;
200
201 if (array_size % 3)
202 return;
203
204 for (i = 0; i < array_size; i +=3) {
205 reg = registers[i + 0];
206 and_mask = registers[i + 1];
207 or_mask = registers[i + 2];
208
209 if (and_mask == 0xffffffff) {
210 tmp = or_mask;
211 } else {
212 tmp = RREG32(reg);
213 tmp &= ~and_mask;
214 tmp |= or_mask;
215 }
216 WREG32(reg, tmp);
217 }
218}
219
220void radeon_pci_config_reset(struct radeon_device *rdev)
221{
222 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
223}
224
225/**
226 * radeon_surface_init - Clear GPU surface registers.
227 *
228 * @rdev: radeon_device pointer
229 *
230 * Clear GPU surface registers (r1xx-r5xx).
231 */
232void radeon_surface_init(struct radeon_device *rdev)
233{
234 /* FIXME: check this out */
235 if (rdev->family < CHIP_R600) {
236 int i;
237
238 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
239 if (rdev->surface_regs[i].bo)
240 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
241 else
242 radeon_clear_surface_reg(rdev, i);
243 }
244 /* enable surfaces */
245 WREG32(RADEON_SURFACE_CNTL, 0);
246 }
247}
248
249/*
250 * GPU scratch registers helpers function.
251 */
252/**
253 * radeon_scratch_init - Init scratch register driver information.
254 *
255 * @rdev: radeon_device pointer
256 *
257 * Init CP scratch register driver information (r1xx-r5xx)
258 */
259void radeon_scratch_init(struct radeon_device *rdev)
260{
261 int i;
262
263 /* FIXME: check this out */
264 if (rdev->family < CHIP_R300) {
265 rdev->scratch.num_reg = 5;
266 } else {
267 rdev->scratch.num_reg = 7;
268 }
269 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
270 for (i = 0; i < rdev->scratch.num_reg; i++) {
271 rdev->scratch.free[i] = true;
272 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
273 }
274}
275
276/**
277 * radeon_scratch_get - Allocate a scratch register
278 *
279 * @rdev: radeon_device pointer
280 * @reg: scratch register mmio offset
281 *
282 * Allocate a CP scratch register for use by the driver (all asics).
283 * Returns 0 on success or -EINVAL on failure.
284 */
285int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
286{
287 int i;
288
289 for (i = 0; i < rdev->scratch.num_reg; i++) {
290 if (rdev->scratch.free[i]) {
291 rdev->scratch.free[i] = false;
292 *reg = rdev->scratch.reg[i];
293 return 0;
294 }
295 }
296 return -EINVAL;
297}
298
299/**
300 * radeon_scratch_free - Free a scratch register
301 *
302 * @rdev: radeon_device pointer
303 * @reg: scratch register mmio offset
304 *
305 * Free a CP scratch register allocated for use by the driver (all asics)
306 */
307void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
308{
309 int i;
310
311 for (i = 0; i < rdev->scratch.num_reg; i++) {
312 if (rdev->scratch.reg[i] == reg) {
313 rdev->scratch.free[i] = true;
314 return;
315 }
316 }
317}
318
319/*
320 * GPU doorbell aperture helpers function.
321 */
322/**
323 * radeon_doorbell_init - Init doorbell driver information.
324 *
325 * @rdev: radeon_device pointer
326 *
327 * Init doorbell driver information (CIK)
328 * Returns 0 on success, error on failure.
329 */
330static int radeon_doorbell_init(struct radeon_device *rdev)
331{
332 /* doorbell bar mapping */
333 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
334 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
335
336 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
337 if (rdev->doorbell.num_doorbells == 0)
338 return -EINVAL;
339
340 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
341 if (rdev->doorbell.ptr == NULL) {
342 return -ENOMEM;
343 }
344 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
345 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
346
347 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
348
349 return 0;
350}
351
352/**
353 * radeon_doorbell_fini - Tear down doorbell driver information.
354 *
355 * @rdev: radeon_device pointer
356 *
357 * Tear down doorbell driver information (CIK)
358 */
359static void radeon_doorbell_fini(struct radeon_device *rdev)
360{
361 iounmap(rdev->doorbell.ptr);
362 rdev->doorbell.ptr = NULL;
363}
364
365/**
366 * radeon_doorbell_get - Allocate a doorbell entry
367 *
368 * @rdev: radeon_device pointer
369 * @doorbell: doorbell index
370 *
371 * Allocate a doorbell for use by the driver (all asics).
372 * Returns 0 on success or -EINVAL on failure.
373 */
374int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
375{
376 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
377 if (offset < rdev->doorbell.num_doorbells) {
378 __set_bit(offset, rdev->doorbell.used);
379 *doorbell = offset;
380 return 0;
381 } else {
382 return -EINVAL;
383 }
384}
385
386/**
387 * radeon_doorbell_free - Free a doorbell entry
388 *
389 * @rdev: radeon_device pointer
390 * @doorbell: doorbell index
391 *
392 * Free a doorbell allocated for use by the driver (all asics)
393 */
394void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
395{
396 if (doorbell < rdev->doorbell.num_doorbells)
397 __clear_bit(doorbell, rdev->doorbell.used);
398}
399
400/*
401 * radeon_wb_*()
402 * Writeback is the the method by which the the GPU updates special pages
403 * in memory with the status of certain GPU events (fences, ring pointers,
404 * etc.).
405 */
406
407/**
408 * radeon_wb_disable - Disable Writeback
409 *
410 * @rdev: radeon_device pointer
411 *
412 * Disables Writeback (all asics). Used for suspend.
413 */
414void radeon_wb_disable(struct radeon_device *rdev)
415{
416 rdev->wb.enabled = false;
417}
418
419/**
420 * radeon_wb_fini - Disable Writeback and free memory
421 *
422 * @rdev: radeon_device pointer
423 *
424 * Disables Writeback and frees the Writeback memory (all asics).
425 * Used at driver shutdown.
426 */
427void radeon_wb_fini(struct radeon_device *rdev)
428{
429 radeon_wb_disable(rdev);
430 if (rdev->wb.wb_obj) {
431 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
432 radeon_bo_kunmap(rdev->wb.wb_obj);
433 radeon_bo_unpin(rdev->wb.wb_obj);
434 radeon_bo_unreserve(rdev->wb.wb_obj);
435 }
436 radeon_bo_unref(&rdev->wb.wb_obj);
437 rdev->wb.wb = NULL;
438 rdev->wb.wb_obj = NULL;
439 }
440}
441
442/**
443 * radeon_wb_init- Init Writeback driver info and allocate memory
444 *
445 * @rdev: radeon_device pointer
446 *
447 * Disables Writeback and frees the Writeback memory (all asics).
448 * Used at driver startup.
449 * Returns 0 on success or an -error on failure.
450 */
451int radeon_wb_init(struct radeon_device *rdev)
452{
453 int r;
454
455 if (rdev->wb.wb_obj == NULL) {
456 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
457 RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL,
458 &rdev->wb.wb_obj);
459 if (r) {
460 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
461 return r;
462 }
463 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
464 if (unlikely(r != 0)) {
465 radeon_wb_fini(rdev);
466 return r;
467 }
468 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
469 &rdev->wb.gpu_addr);
470 if (r) {
471 radeon_bo_unreserve(rdev->wb.wb_obj);
472 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
473 radeon_wb_fini(rdev);
474 return r;
475 }
476 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
477 radeon_bo_unreserve(rdev->wb.wb_obj);
478 if (r) {
479 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
480 radeon_wb_fini(rdev);
481 return r;
482 }
483 }
484
485 /* clear wb memory */
486 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
487 /* disable event_write fences */
488 rdev->wb.use_event = false;
489 /* disabled via module param */
490 if (radeon_no_wb == 1) {
491 rdev->wb.enabled = false;
492 } else {
493 if (rdev->flags & RADEON_IS_AGP) {
494 /* often unreliable on AGP */
495 rdev->wb.enabled = false;
496 } else if (rdev->family < CHIP_R300) {
497 /* often unreliable on pre-r300 */
498 rdev->wb.enabled = false;
499 } else {
500 rdev->wb.enabled = true;
501 /* event_write fences are only available on r600+ */
502 if (rdev->family >= CHIP_R600) {
503 rdev->wb.use_event = true;
504 }
505 }
506 }
507 /* always use writeback/events on NI, APUs */
508 if (rdev->family >= CHIP_PALM) {
509 rdev->wb.enabled = true;
510 rdev->wb.use_event = true;
511 }
512
513 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
514
515 return 0;
516}
517
518/**
519 * radeon_vram_location - try to find VRAM location
520 * @rdev: radeon device structure holding all necessary informations
521 * @mc: memory controller structure holding memory informations
522 * @base: base address at which to put VRAM
523 *
524 * Function will place try to place VRAM at base address provided
525 * as parameter (which is so far either PCI aperture address or
526 * for IGP TOM base address).
527 *
528 * If there is not enough space to fit the unvisible VRAM in the 32bits
529 * address space then we limit the VRAM size to the aperture.
530 *
531 * If we are using AGP and if the AGP aperture doesn't allow us to have
532 * room for all the VRAM than we restrict the VRAM to the PCI aperture
533 * size and print a warning.
534 *
535 * This function will never fails, worst case are limiting VRAM.
536 *
537 * Note: GTT start, end, size should be initialized before calling this
538 * function on AGP platform.
539 *
540 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
541 * this shouldn't be a problem as we are using the PCI aperture as a reference.
542 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
543 * not IGP.
544 *
545 * Note: we use mc_vram_size as on some board we need to program the mc to
546 * cover the whole aperture even if VRAM size is inferior to aperture size
547 * Novell bug 204882 + along with lots of ubuntu ones
548 *
549 * Note: when limiting vram it's safe to overwritte real_vram_size because
550 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
551 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
552 * ones)
553 *
554 * Note: IGP TOM addr should be the same as the aperture addr, we don't
555 * explicitly check for that thought.
556 *
557 * FIXME: when reducing VRAM size align new size on power of 2.
558 */
559void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
560{
561 uint64_t limit = (uint64_t)radeon_vram_limit << 20;
562
563 mc->vram_start = base;
564 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
565 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
566 mc->real_vram_size = mc->aper_size;
567 mc->mc_vram_size = mc->aper_size;
568 }
569 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
570 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
571 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
572 mc->real_vram_size = mc->aper_size;
573 mc->mc_vram_size = mc->aper_size;
574 }
575 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
576 if (limit && limit < mc->real_vram_size)
577 mc->real_vram_size = limit;
578 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
579 mc->mc_vram_size >> 20, mc->vram_start,
580 mc->vram_end, mc->real_vram_size >> 20);
581}
582
583/**
584 * radeon_gtt_location - try to find GTT location
585 * @rdev: radeon device structure holding all necessary informations
586 * @mc: memory controller structure holding memory informations
587 *
588 * Function will place try to place GTT before or after VRAM.
589 *
590 * If GTT size is bigger than space left then we ajust GTT size.
591 * Thus function will never fails.
592 *
593 * FIXME: when reducing GTT size align new size on power of 2.
594 */
595void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
596{
597 u64 size_af, size_bf;
598
599 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
600 size_bf = mc->vram_start & ~mc->gtt_base_align;
601 if (size_bf > size_af) {
602 if (mc->gtt_size > size_bf) {
603 dev_warn(rdev->dev, "limiting GTT\n");
604 mc->gtt_size = size_bf;
605 }
606 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
607 } else {
608 if (mc->gtt_size > size_af) {
609 dev_warn(rdev->dev, "limiting GTT\n");
610 mc->gtt_size = size_af;
611 }
612 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
613 }
614 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
615 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
616 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
617}
618
619/*
620 * GPU helpers function.
621 */
622
623/**
624 * radeon_device_is_virtual - check if we are running is a virtual environment
625 *
626 * Check if the asic has been passed through to a VM (all asics).
627 * Used at driver startup.
628 * Returns true if virtual or false if not.
629 */
630bool radeon_device_is_virtual(void)
631{
632#ifdef CONFIG_X86
633 return boot_cpu_has(X86_FEATURE_HYPERVISOR);
634#else
635 return false;
636#endif
637}
638
639/**
640 * radeon_card_posted - check if the hw has already been initialized
641 *
642 * @rdev: radeon_device pointer
643 *
644 * Check if the asic has been initialized (all asics).
645 * Used at driver startup.
646 * Returns true if initialized or false if not.
647 */
648bool radeon_card_posted(struct radeon_device *rdev)
649{
650 uint32_t reg;
651
652 /* for pass through, always force asic_init for CI */
653 if (rdev->family >= CHIP_BONAIRE &&
654 radeon_device_is_virtual())
655 return false;
656
657 /* required for EFI mode on macbook2,1 which uses an r5xx asic */
658 if (efi_enabled(EFI_BOOT) &&
659 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
660 (rdev->family < CHIP_R600))
661 return false;
662
663 if (ASIC_IS_NODCE(rdev))
664 goto check_memsize;
665
666 /* first check CRTCs */
667 if (ASIC_IS_DCE4(rdev)) {
668 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
669 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
670 if (rdev->num_crtc >= 4) {
671 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
672 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
673 }
674 if (rdev->num_crtc >= 6) {
675 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
676 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
677 }
678 if (reg & EVERGREEN_CRTC_MASTER_EN)
679 return true;
680 } else if (ASIC_IS_AVIVO(rdev)) {
681 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
682 RREG32(AVIVO_D2CRTC_CONTROL);
683 if (reg & AVIVO_CRTC_EN) {
684 return true;
685 }
686 } else {
687 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
688 RREG32(RADEON_CRTC2_GEN_CNTL);
689 if (reg & RADEON_CRTC_EN) {
690 return true;
691 }
692 }
693
694check_memsize:
695 /* then check MEM_SIZE, in case the crtcs are off */
696 if (rdev->family >= CHIP_R600)
697 reg = RREG32(R600_CONFIG_MEMSIZE);
698 else
699 reg = RREG32(RADEON_CONFIG_MEMSIZE);
700
701 if (reg)
702 return true;
703
704 return false;
705
706}
707
708/**
709 * radeon_update_bandwidth_info - update display bandwidth params
710 *
711 * @rdev: radeon_device pointer
712 *
713 * Used when sclk/mclk are switched or display modes are set.
714 * params are used to calculate display watermarks (all asics)
715 */
716void radeon_update_bandwidth_info(struct radeon_device *rdev)
717{
718 fixed20_12 a;
719 u32 sclk = rdev->pm.current_sclk;
720 u32 mclk = rdev->pm.current_mclk;
721
722 /* sclk/mclk in Mhz */
723 a.full = dfixed_const(100);
724 rdev->pm.sclk.full = dfixed_const(sclk);
725 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
726 rdev->pm.mclk.full = dfixed_const(mclk);
727 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
728
729 if (rdev->flags & RADEON_IS_IGP) {
730 a.full = dfixed_const(16);
731 /* core_bandwidth = sclk(Mhz) * 16 */
732 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
733 }
734}
735
736/**
737 * radeon_boot_test_post_card - check and possibly initialize the hw
738 *
739 * @rdev: radeon_device pointer
740 *
741 * Check if the asic is initialized and if not, attempt to initialize
742 * it (all asics).
743 * Returns true if initialized or false if not.
744 */
745bool radeon_boot_test_post_card(struct radeon_device *rdev)
746{
747 if (radeon_card_posted(rdev))
748 return true;
749
750 if (rdev->bios) {
751 DRM_INFO("GPU not posted. posting now...\n");
752 if (rdev->is_atom_bios)
753 atom_asic_init(rdev->mode_info.atom_context);
754 else
755 radeon_combios_asic_init(rdev->ddev);
756 return true;
757 } else {
758 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
759 return false;
760 }
761}
762
763/**
764 * radeon_dummy_page_init - init dummy page used by the driver
765 *
766 * @rdev: radeon_device pointer
767 *
768 * Allocate the dummy page used by the driver (all asics).
769 * This dummy page is used by the driver as a filler for gart entries
770 * when pages are taken out of the GART
771 * Returns 0 on sucess, -ENOMEM on failure.
772 */
773int radeon_dummy_page_init(struct radeon_device *rdev)
774{
775 if (rdev->dummy_page.page)
776 return 0;
777 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
778 if (rdev->dummy_page.page == NULL)
779 return -ENOMEM;
780 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
781 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
782 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
783 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
784 __free_page(rdev->dummy_page.page);
785 rdev->dummy_page.page = NULL;
786 return -ENOMEM;
787 }
788 rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr,
789 RADEON_GART_PAGE_DUMMY);
790 return 0;
791}
792
793/**
794 * radeon_dummy_page_fini - free dummy page used by the driver
795 *
796 * @rdev: radeon_device pointer
797 *
798 * Frees the dummy page used by the driver (all asics).
799 */
800void radeon_dummy_page_fini(struct radeon_device *rdev)
801{
802 if (rdev->dummy_page.page == NULL)
803 return;
804 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
805 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
806 __free_page(rdev->dummy_page.page);
807 rdev->dummy_page.page = NULL;
808}
809
810
811/* ATOM accessor methods */
812/*
813 * ATOM is an interpreted byte code stored in tables in the vbios. The
814 * driver registers callbacks to access registers and the interpreter
815 * in the driver parses the tables and executes then to program specific
816 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
817 * atombios.h, and atom.c
818 */
819
820/**
821 * cail_pll_read - read PLL register
822 *
823 * @info: atom card_info pointer
824 * @reg: PLL register offset
825 *
826 * Provides a PLL register accessor for the atom interpreter (r4xx+).
827 * Returns the value of the PLL register.
828 */
829static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
830{
831 struct radeon_device *rdev = info->dev->dev_private;
832 uint32_t r;
833
834 r = rdev->pll_rreg(rdev, reg);
835 return r;
836}
837
838/**
839 * cail_pll_write - write PLL register
840 *
841 * @info: atom card_info pointer
842 * @reg: PLL register offset
843 * @val: value to write to the pll register
844 *
845 * Provides a PLL register accessor for the atom interpreter (r4xx+).
846 */
847static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
848{
849 struct radeon_device *rdev = info->dev->dev_private;
850
851 rdev->pll_wreg(rdev, reg, val);
852}
853
854/**
855 * cail_mc_read - read MC (Memory Controller) register
856 *
857 * @info: atom card_info pointer
858 * @reg: MC register offset
859 *
860 * Provides an MC register accessor for the atom interpreter (r4xx+).
861 * Returns the value of the MC register.
862 */
863static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
864{
865 struct radeon_device *rdev = info->dev->dev_private;
866 uint32_t r;
867
868 r = rdev->mc_rreg(rdev, reg);
869 return r;
870}
871
872/**
873 * cail_mc_write - write MC (Memory Controller) register
874 *
875 * @info: atom card_info pointer
876 * @reg: MC register offset
877 * @val: value to write to the pll register
878 *
879 * Provides a MC register accessor for the atom interpreter (r4xx+).
880 */
881static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
882{
883 struct radeon_device *rdev = info->dev->dev_private;
884
885 rdev->mc_wreg(rdev, reg, val);
886}
887
888/**
889 * cail_reg_write - write MMIO register
890 *
891 * @info: atom card_info pointer
892 * @reg: MMIO register offset
893 * @val: value to write to the pll register
894 *
895 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
896 */
897static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
898{
899 struct radeon_device *rdev = info->dev->dev_private;
900
901 WREG32(reg*4, val);
902}
903
904/**
905 * cail_reg_read - read MMIO register
906 *
907 * @info: atom card_info pointer
908 * @reg: MMIO register offset
909 *
910 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
911 * Returns the value of the MMIO register.
912 */
913static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
914{
915 struct radeon_device *rdev = info->dev->dev_private;
916 uint32_t r;
917
918 r = RREG32(reg*4);
919 return r;
920}
921
922/**
923 * cail_ioreg_write - write IO register
924 *
925 * @info: atom card_info pointer
926 * @reg: IO register offset
927 * @val: value to write to the pll register
928 *
929 * Provides a IO register accessor for the atom interpreter (r4xx+).
930 */
931static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
932{
933 struct radeon_device *rdev = info->dev->dev_private;
934
935 WREG32_IO(reg*4, val);
936}
937
938/**
939 * cail_ioreg_read - read IO register
940 *
941 * @info: atom card_info pointer
942 * @reg: IO register offset
943 *
944 * Provides an IO register accessor for the atom interpreter (r4xx+).
945 * Returns the value of the IO register.
946 */
947static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
948{
949 struct radeon_device *rdev = info->dev->dev_private;
950 uint32_t r;
951
952 r = RREG32_IO(reg*4);
953 return r;
954}
955
956/**
957 * radeon_atombios_init - init the driver info and callbacks for atombios
958 *
959 * @rdev: radeon_device pointer
960 *
961 * Initializes the driver info and register access callbacks for the
962 * ATOM interpreter (r4xx+).
963 * Returns 0 on sucess, -ENOMEM on failure.
964 * Called at driver startup.
965 */
966int radeon_atombios_init(struct radeon_device *rdev)
967{
968 struct card_info *atom_card_info =
969 kzalloc(sizeof(struct card_info), GFP_KERNEL);
970
971 if (!atom_card_info)
972 return -ENOMEM;
973
974 rdev->mode_info.atom_card_info = atom_card_info;
975 atom_card_info->dev = rdev->ddev;
976 atom_card_info->reg_read = cail_reg_read;
977 atom_card_info->reg_write = cail_reg_write;
978 /* needed for iio ops */
979 if (rdev->rio_mem) {
980 atom_card_info->ioreg_read = cail_ioreg_read;
981 atom_card_info->ioreg_write = cail_ioreg_write;
982 } else {
983 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
984 atom_card_info->ioreg_read = cail_reg_read;
985 atom_card_info->ioreg_write = cail_reg_write;
986 }
987 atom_card_info->mc_read = cail_mc_read;
988 atom_card_info->mc_write = cail_mc_write;
989 atom_card_info->pll_read = cail_pll_read;
990 atom_card_info->pll_write = cail_pll_write;
991
992 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
993 if (!rdev->mode_info.atom_context) {
994 radeon_atombios_fini(rdev);
995 return -ENOMEM;
996 }
997
998 mutex_init(&rdev->mode_info.atom_context->mutex);
999 mutex_init(&rdev->mode_info.atom_context->scratch_mutex);
1000 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
1001 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
1002 return 0;
1003}
1004
1005/**
1006 * radeon_atombios_fini - free the driver info and callbacks for atombios
1007 *
1008 * @rdev: radeon_device pointer
1009 *
1010 * Frees the driver info and register access callbacks for the ATOM
1011 * interpreter (r4xx+).
1012 * Called at driver shutdown.
1013 */
1014void radeon_atombios_fini(struct radeon_device *rdev)
1015{
1016 if (rdev->mode_info.atom_context) {
1017 kfree(rdev->mode_info.atom_context->scratch);
1018 }
1019 kfree(rdev->mode_info.atom_context);
1020 rdev->mode_info.atom_context = NULL;
1021 kfree(rdev->mode_info.atom_card_info);
1022 rdev->mode_info.atom_card_info = NULL;
1023}
1024
1025/* COMBIOS */
1026/*
1027 * COMBIOS is the bios format prior to ATOM. It provides
1028 * command tables similar to ATOM, but doesn't have a unified
1029 * parser. See radeon_combios.c
1030 */
1031
1032/**
1033 * radeon_combios_init - init the driver info for combios
1034 *
1035 * @rdev: radeon_device pointer
1036 *
1037 * Initializes the driver info for combios (r1xx-r3xx).
1038 * Returns 0 on sucess.
1039 * Called at driver startup.
1040 */
1041int radeon_combios_init(struct radeon_device *rdev)
1042{
1043 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
1044 return 0;
1045}
1046
1047/**
1048 * radeon_combios_fini - free the driver info for combios
1049 *
1050 * @rdev: radeon_device pointer
1051 *
1052 * Frees the driver info for combios (r1xx-r3xx).
1053 * Called at driver shutdown.
1054 */
1055void radeon_combios_fini(struct radeon_device *rdev)
1056{
1057}
1058
1059/* if we get transitioned to only one device, take VGA back */
1060/**
1061 * radeon_vga_set_decode - enable/disable vga decode
1062 *
1063 * @cookie: radeon_device pointer
1064 * @state: enable/disable vga decode
1065 *
1066 * Enable/disable vga decode (all asics).
1067 * Returns VGA resource flags.
1068 */
1069static unsigned int radeon_vga_set_decode(void *cookie, bool state)
1070{
1071 struct radeon_device *rdev = cookie;
1072 radeon_vga_set_state(rdev, state);
1073 if (state)
1074 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1075 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1076 else
1077 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1078}
1079
1080/**
1081 * radeon_check_pot_argument - check that argument is a power of two
1082 *
1083 * @arg: value to check
1084 *
1085 * Validates that a certain argument is a power of two (all asics).
1086 * Returns true if argument is valid.
1087 */
1088static bool radeon_check_pot_argument(int arg)
1089{
1090 return (arg & (arg - 1)) == 0;
1091}
1092
1093/**
1094 * Determine a sensible default GART size according to ASIC family.
1095 *
1096 * @family ASIC family name
1097 */
1098static int radeon_gart_size_auto(enum radeon_family family)
1099{
1100 /* default to a larger gart size on newer asics */
1101 if (family >= CHIP_TAHITI)
1102 return 2048;
1103 else if (family >= CHIP_RV770)
1104 return 1024;
1105 else
1106 return 512;
1107}
1108
1109/**
1110 * radeon_check_arguments - validate module params
1111 *
1112 * @rdev: radeon_device pointer
1113 *
1114 * Validates certain module parameters and updates
1115 * the associated values used by the driver (all asics).
1116 */
1117static void radeon_check_arguments(struct radeon_device *rdev)
1118{
1119 /* vramlimit must be a power of two */
1120 if (!radeon_check_pot_argument(radeon_vram_limit)) {
1121 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
1122 radeon_vram_limit);
1123 radeon_vram_limit = 0;
1124 }
1125
1126 if (radeon_gart_size == -1) {
1127 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1128 }
1129 /* gtt size must be power of two and greater or equal to 32M */
1130 if (radeon_gart_size < 32) {
1131 dev_warn(rdev->dev, "gart size (%d) too small\n",
1132 radeon_gart_size);
1133 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1134 } else if (!radeon_check_pot_argument(radeon_gart_size)) {
1135 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
1136 radeon_gart_size);
1137 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1138 }
1139 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
1140
1141 /* AGP mode can only be -1, 1, 2, 4, 8 */
1142 switch (radeon_agpmode) {
1143 case -1:
1144 case 0:
1145 case 1:
1146 case 2:
1147 case 4:
1148 case 8:
1149 break;
1150 default:
1151 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
1152 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
1153 radeon_agpmode = 0;
1154 break;
1155 }
1156
1157 if (!radeon_check_pot_argument(radeon_vm_size)) {
1158 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n",
1159 radeon_vm_size);
1160 radeon_vm_size = 4;
1161 }
1162
1163 if (radeon_vm_size < 1) {
1164 dev_warn(rdev->dev, "VM size (%d) too small, min is 1GB\n",
1165 radeon_vm_size);
1166 radeon_vm_size = 4;
1167 }
1168
1169 /*
1170 * Max GPUVM size for Cayman, SI and CI are 40 bits.
1171 */
1172 if (radeon_vm_size > 1024) {
1173 dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n",
1174 radeon_vm_size);
1175 radeon_vm_size = 4;
1176 }
1177
1178 /* defines number of bits in page table versus page directory,
1179 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1180 * page table and the remaining bits are in the page directory */
1181 if (radeon_vm_block_size == -1) {
1182
1183 /* Total bits covered by PD + PTs */
1184 unsigned bits = ilog2(radeon_vm_size) + 18;
1185
1186 /* Make sure the PD is 4K in size up to 8GB address space.
1187 Above that split equal between PD and PTs */
1188 if (radeon_vm_size <= 8)
1189 radeon_vm_block_size = bits - 9;
1190 else
1191 radeon_vm_block_size = (bits + 3) / 2;
1192
1193 } else if (radeon_vm_block_size < 9) {
1194 dev_warn(rdev->dev, "VM page table size (%d) too small\n",
1195 radeon_vm_block_size);
1196 radeon_vm_block_size = 9;
1197 }
1198
1199 if (radeon_vm_block_size > 24 ||
1200 (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) {
1201 dev_warn(rdev->dev, "VM page table size (%d) too large\n",
1202 radeon_vm_block_size);
1203 radeon_vm_block_size = 9;
1204 }
1205}
1206
1207/**
1208 * radeon_switcheroo_set_state - set switcheroo state
1209 *
1210 * @pdev: pci dev pointer
1211 * @state: vga_switcheroo state
1212 *
1213 * Callback for the switcheroo driver. Suspends or resumes the
1214 * the asics before or after it is powered up using ACPI methods.
1215 */
1216static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1217{
1218 struct drm_device *dev = pci_get_drvdata(pdev);
1219
1220 if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1221 return;
1222
1223 if (state == VGA_SWITCHEROO_ON) {
1224 pr_info("radeon: switched on\n");
1225 /* don't suspend or resume card normally */
1226 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1227
1228 radeon_resume_kms(dev, true, true);
1229
1230 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1231 drm_kms_helper_poll_enable(dev);
1232 } else {
1233 pr_info("radeon: switched off\n");
1234 drm_kms_helper_poll_disable(dev);
1235 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1236 radeon_suspend_kms(dev, true, true, false);
1237 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1238 }
1239}
1240
1241/**
1242 * radeon_switcheroo_can_switch - see if switcheroo state can change
1243 *
1244 * @pdev: pci dev pointer
1245 *
1246 * Callback for the switcheroo driver. Check of the switcheroo
1247 * state can be changed.
1248 * Returns true if the state can be changed, false if not.
1249 */
1250static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
1251{
1252 struct drm_device *dev = pci_get_drvdata(pdev);
1253
1254 /*
1255 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1256 * locking inversion with the driver load path. And the access here is
1257 * completely racy anyway. So don't bother with locking for now.
1258 */
1259 return dev->open_count == 0;
1260}
1261
1262static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
1263 .set_gpu_state = radeon_switcheroo_set_state,
1264 .reprobe = NULL,
1265 .can_switch = radeon_switcheroo_can_switch,
1266};
1267
1268/**
1269 * radeon_device_init - initialize the driver
1270 *
1271 * @rdev: radeon_device pointer
1272 * @pdev: drm dev pointer
1273 * @pdev: pci dev pointer
1274 * @flags: driver flags
1275 *
1276 * Initializes the driver info and hw (all asics).
1277 * Returns 0 for success or an error on failure.
1278 * Called at driver startup.
1279 */
1280int radeon_device_init(struct radeon_device *rdev,
1281 struct drm_device *ddev,
1282 struct pci_dev *pdev,
1283 uint32_t flags)
1284{
1285 int r, i;
1286 int dma_bits;
1287 bool runtime = false;
1288
1289 rdev->shutdown = false;
1290 rdev->dev = &pdev->dev;
1291 rdev->ddev = ddev;
1292 rdev->pdev = pdev;
1293 rdev->flags = flags;
1294 rdev->family = flags & RADEON_FAMILY_MASK;
1295 rdev->is_atom_bios = false;
1296 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1297 rdev->mc.gtt_size = 512 * 1024 * 1024;
1298 rdev->accel_working = false;
1299 /* set up ring ids */
1300 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1301 rdev->ring[i].idx = i;
1302 }
1303 rdev->fence_context = dma_fence_context_alloc(RADEON_NUM_RINGS);
1304
1305 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1306 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1307 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1308
1309 /* mutex initialization are all done here so we
1310 * can recall function without having locking issues */
1311 mutex_init(&rdev->ring_lock);
1312 mutex_init(&rdev->dc_hw_i2c_mutex);
1313 atomic_set(&rdev->ih.lock, 0);
1314 mutex_init(&rdev->gem.mutex);
1315 mutex_init(&rdev->pm.mutex);
1316 mutex_init(&rdev->gpu_clock_mutex);
1317 mutex_init(&rdev->srbm_mutex);
1318 init_rwsem(&rdev->pm.mclk_lock);
1319 init_rwsem(&rdev->exclusive_lock);
1320 init_waitqueue_head(&rdev->irq.vblank_queue);
1321 mutex_init(&rdev->mn_lock);
1322 hash_init(rdev->mn_hash);
1323 r = radeon_gem_init(rdev);
1324 if (r)
1325 return r;
1326
1327 radeon_check_arguments(rdev);
1328 /* Adjust VM size here.
1329 * Max GPUVM size for cayman+ is 40 bits.
1330 */
1331 rdev->vm_manager.max_pfn = radeon_vm_size << 18;
1332
1333 /* Set asic functions */
1334 r = radeon_asic_init(rdev);
1335 if (r)
1336 return r;
1337
1338 /* all of the newer IGP chips have an internal gart
1339 * However some rs4xx report as AGP, so remove that here.
1340 */
1341 if ((rdev->family >= CHIP_RS400) &&
1342 (rdev->flags & RADEON_IS_IGP)) {
1343 rdev->flags &= ~RADEON_IS_AGP;
1344 }
1345
1346 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1347 radeon_agp_disable(rdev);
1348 }
1349
1350 /* Set the internal MC address mask
1351 * This is the max address of the GPU's
1352 * internal address space.
1353 */
1354 if (rdev->family >= CHIP_CAYMAN)
1355 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1356 else if (rdev->family >= CHIP_CEDAR)
1357 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
1358 else
1359 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
1360
1361 /* set DMA mask + need_dma32 flags.
1362 * PCIE - can handle 40-bits.
1363 * IGP - can handle 40-bits
1364 * AGP - generally dma32 is safest
1365 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1366 */
1367 rdev->need_dma32 = false;
1368 if (rdev->flags & RADEON_IS_AGP)
1369 rdev->need_dma32 = true;
1370 if ((rdev->flags & RADEON_IS_PCI) &&
1371 (rdev->family <= CHIP_RS740))
1372 rdev->need_dma32 = true;
1373#ifdef CONFIG_PPC64
1374 if (rdev->family == CHIP_CEDAR)
1375 rdev->need_dma32 = true;
1376#endif
1377
1378 dma_bits = rdev->need_dma32 ? 32 : 40;
1379 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1380 if (r) {
1381 rdev->need_dma32 = true;
1382 dma_bits = 32;
1383 pr_warn("radeon: No suitable DMA available\n");
1384 }
1385 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1386 if (r) {
1387 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
1388 pr_warn("radeon: No coherent DMA available\n");
1389 }
1390 rdev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
1391
1392 /* Registers mapping */
1393 /* TODO: block userspace mapping of io register */
1394 spin_lock_init(&rdev->mmio_idx_lock);
1395 spin_lock_init(&rdev->smc_idx_lock);
1396 spin_lock_init(&rdev->pll_idx_lock);
1397 spin_lock_init(&rdev->mc_idx_lock);
1398 spin_lock_init(&rdev->pcie_idx_lock);
1399 spin_lock_init(&rdev->pciep_idx_lock);
1400 spin_lock_init(&rdev->pif_idx_lock);
1401 spin_lock_init(&rdev->cg_idx_lock);
1402 spin_lock_init(&rdev->uvd_idx_lock);
1403 spin_lock_init(&rdev->rcu_idx_lock);
1404 spin_lock_init(&rdev->didt_idx_lock);
1405 spin_lock_init(&rdev->end_idx_lock);
1406 if (rdev->family >= CHIP_BONAIRE) {
1407 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
1408 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
1409 } else {
1410 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
1411 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1412 }
1413 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1414 if (rdev->rmmio == NULL)
1415 return -ENOMEM;
1416
1417 /* doorbell bar mapping */
1418 if (rdev->family >= CHIP_BONAIRE)
1419 radeon_doorbell_init(rdev);
1420
1421 /* io port mapping */
1422 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1423 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
1424 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
1425 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
1426 break;
1427 }
1428 }
1429 if (rdev->rio_mem == NULL)
1430 DRM_ERROR("Unable to find PCI I/O BAR\n");
1431
1432 if (rdev->flags & RADEON_IS_PX)
1433 radeon_device_handle_px_quirks(rdev);
1434
1435 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1436 /* this will fail for cards that aren't VGA class devices, just
1437 * ignore it */
1438 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1439
1440 if (rdev->flags & RADEON_IS_PX)
1441 runtime = true;
1442 if (!pci_is_thunderbolt_attached(rdev->pdev))
1443 vga_switcheroo_register_client(rdev->pdev,
1444 &radeon_switcheroo_ops, runtime);
1445 if (runtime)
1446 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain);
1447
1448 r = radeon_init(rdev);
1449 if (r)
1450 goto failed;
1451
1452 r = radeon_gem_debugfs_init(rdev);
1453 if (r) {
1454 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1455 }
1456
1457 r = radeon_mst_debugfs_init(rdev);
1458 if (r) {
1459 DRM_ERROR("registering mst debugfs failed (%d).\n", r);
1460 }
1461
1462 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1463 /* Acceleration not working on AGP card try again
1464 * with fallback to PCI or PCIE GART
1465 */
1466 radeon_asic_reset(rdev);
1467 radeon_fini(rdev);
1468 radeon_agp_disable(rdev);
1469 r = radeon_init(rdev);
1470 if (r)
1471 goto failed;
1472 }
1473
1474 r = radeon_ib_ring_tests(rdev);
1475 if (r)
1476 DRM_ERROR("ib ring test failed (%d).\n", r);
1477
1478 /*
1479 * Turks/Thames GPU will freeze whole laptop if DPM is not restarted
1480 * after the CP ring have chew one packet at least. Hence here we stop
1481 * and restart DPM after the radeon_ib_ring_tests().
1482 */
1483 if (rdev->pm.dpm_enabled &&
1484 (rdev->pm.pm_method == PM_METHOD_DPM) &&
1485 (rdev->family == CHIP_TURKS) &&
1486 (rdev->flags & RADEON_IS_MOBILITY)) {
1487 mutex_lock(&rdev->pm.mutex);
1488 radeon_dpm_disable(rdev);
1489 radeon_dpm_enable(rdev);
1490 mutex_unlock(&rdev->pm.mutex);
1491 }
1492
1493 if ((radeon_testing & 1)) {
1494 if (rdev->accel_working)
1495 radeon_test_moves(rdev);
1496 else
1497 DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1498 }
1499 if ((radeon_testing & 2)) {
1500 if (rdev->accel_working)
1501 radeon_test_syncing(rdev);
1502 else
1503 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1504 }
1505 if (radeon_benchmarking) {
1506 if (rdev->accel_working)
1507 radeon_benchmark(rdev, radeon_benchmarking);
1508 else
1509 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1510 }
1511 return 0;
1512
1513failed:
1514 /* balance pm_runtime_get_sync() in radeon_driver_unload_kms() */
1515 if (radeon_is_px(ddev))
1516 pm_runtime_put_noidle(ddev->dev);
1517 if (runtime)
1518 vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1519 return r;
1520}
1521
1522/**
1523 * radeon_device_fini - tear down the driver
1524 *
1525 * @rdev: radeon_device pointer
1526 *
1527 * Tear down the driver info (all asics).
1528 * Called at driver shutdown.
1529 */
1530void radeon_device_fini(struct radeon_device *rdev)
1531{
1532 DRM_INFO("radeon: finishing device.\n");
1533 rdev->shutdown = true;
1534 /* evict vram memory */
1535 radeon_bo_evict_vram(rdev);
1536 radeon_fini(rdev);
1537 if (!pci_is_thunderbolt_attached(rdev->pdev))
1538 vga_switcheroo_unregister_client(rdev->pdev);
1539 if (rdev->flags & RADEON_IS_PX)
1540 vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1541 vga_client_register(rdev->pdev, NULL, NULL, NULL);
1542 if (rdev->rio_mem)
1543 pci_iounmap(rdev->pdev, rdev->rio_mem);
1544 rdev->rio_mem = NULL;
1545 iounmap(rdev->rmmio);
1546 rdev->rmmio = NULL;
1547 if (rdev->family >= CHIP_BONAIRE)
1548 radeon_doorbell_fini(rdev);
1549}
1550
1551
1552/*
1553 * Suspend & resume.
1554 */
1555/**
1556 * radeon_suspend_kms - initiate device suspend
1557 *
1558 * @pdev: drm dev pointer
1559 * @state: suspend state
1560 *
1561 * Puts the hw in the suspend state (all asics).
1562 * Returns 0 for success or an error on failure.
1563 * Called at driver suspend.
1564 */
1565int radeon_suspend_kms(struct drm_device *dev, bool suspend,
1566 bool fbcon, bool freeze)
1567{
1568 struct radeon_device *rdev;
1569 struct drm_crtc *crtc;
1570 struct drm_connector *connector;
1571 int i, r;
1572
1573 if (dev == NULL || dev->dev_private == NULL) {
1574 return -ENODEV;
1575 }
1576
1577 rdev = dev->dev_private;
1578
1579 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1580 return 0;
1581
1582 drm_kms_helper_poll_disable(dev);
1583
1584 drm_modeset_lock_all(dev);
1585 /* turn off display hw */
1586 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1587 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1588 }
1589 drm_modeset_unlock_all(dev);
1590
1591 /* unpin the front buffers and cursors */
1592 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1593 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1594 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb);
1595 struct radeon_bo *robj;
1596
1597 if (radeon_crtc->cursor_bo) {
1598 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
1599 r = radeon_bo_reserve(robj, false);
1600 if (r == 0) {
1601 radeon_bo_unpin(robj);
1602 radeon_bo_unreserve(robj);
1603 }
1604 }
1605
1606 if (rfb == NULL || rfb->obj == NULL) {
1607 continue;
1608 }
1609 robj = gem_to_radeon_bo(rfb->obj);
1610 /* don't unpin kernel fb objects */
1611 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1612 r = radeon_bo_reserve(robj, false);
1613 if (r == 0) {
1614 radeon_bo_unpin(robj);
1615 radeon_bo_unreserve(robj);
1616 }
1617 }
1618 }
1619 /* evict vram memory */
1620 radeon_bo_evict_vram(rdev);
1621
1622 /* wait for gpu to finish processing current batch */
1623 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1624 r = radeon_fence_wait_empty(rdev, i);
1625 if (r) {
1626 /* delay GPU reset to resume */
1627 radeon_fence_driver_force_completion(rdev, i);
1628 }
1629 }
1630
1631 radeon_save_bios_scratch_regs(rdev);
1632
1633 radeon_suspend(rdev);
1634 radeon_hpd_fini(rdev);
1635 /* evict remaining vram memory
1636 * This second call to evict vram is to evict the gart page table
1637 * using the CPU.
1638 */
1639 radeon_bo_evict_vram(rdev);
1640
1641 radeon_agp_suspend(rdev);
1642
1643 pci_save_state(dev->pdev);
1644 if (freeze && rdev->family >= CHIP_CEDAR && !(rdev->flags & RADEON_IS_IGP)) {
1645 rdev->asic->asic_reset(rdev, true);
1646 pci_restore_state(dev->pdev);
1647 } else if (suspend) {
1648 /* Shut down the device */
1649 pci_disable_device(dev->pdev);
1650 pci_set_power_state(dev->pdev, PCI_D3hot);
1651 }
1652
1653 if (fbcon) {
1654 console_lock();
1655 radeon_fbdev_set_suspend(rdev, 1);
1656 console_unlock();
1657 }
1658 return 0;
1659}
1660
1661/**
1662 * radeon_resume_kms - initiate device resume
1663 *
1664 * @pdev: drm dev pointer
1665 *
1666 * Bring the hw back to operating state (all asics).
1667 * Returns 0 for success or an error on failure.
1668 * Called at driver resume.
1669 */
1670int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1671{
1672 struct drm_connector *connector;
1673 struct radeon_device *rdev = dev->dev_private;
1674 struct drm_crtc *crtc;
1675 int r;
1676
1677 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1678 return 0;
1679
1680 if (fbcon) {
1681 console_lock();
1682 }
1683 if (resume) {
1684 pci_set_power_state(dev->pdev, PCI_D0);
1685 pci_restore_state(dev->pdev);
1686 if (pci_enable_device(dev->pdev)) {
1687 if (fbcon)
1688 console_unlock();
1689 return -1;
1690 }
1691 }
1692 /* resume AGP if in use */
1693 radeon_agp_resume(rdev);
1694 radeon_resume(rdev);
1695
1696 r = radeon_ib_ring_tests(rdev);
1697 if (r)
1698 DRM_ERROR("ib ring test failed (%d).\n", r);
1699
1700 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1701 /* do dpm late init */
1702 r = radeon_pm_late_init(rdev);
1703 if (r) {
1704 rdev->pm.dpm_enabled = false;
1705 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1706 }
1707 } else {
1708 /* resume old pm late */
1709 radeon_pm_resume(rdev);
1710 }
1711
1712 radeon_restore_bios_scratch_regs(rdev);
1713
1714 /* pin cursors */
1715 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1716 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1717
1718 if (radeon_crtc->cursor_bo) {
1719 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
1720 r = radeon_bo_reserve(robj, false);
1721 if (r == 0) {
1722 /* Only 27 bit offset for legacy cursor */
1723 r = radeon_bo_pin_restricted(robj,
1724 RADEON_GEM_DOMAIN_VRAM,
1725 ASIC_IS_AVIVO(rdev) ?
1726 0 : 1 << 27,
1727 &radeon_crtc->cursor_addr);
1728 if (r != 0)
1729 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
1730 radeon_bo_unreserve(robj);
1731 }
1732 }
1733 }
1734
1735 /* init dig PHYs, disp eng pll */
1736 if (rdev->is_atom_bios) {
1737 radeon_atom_encoder_init(rdev);
1738 radeon_atom_disp_eng_pll_init(rdev);
1739 /* turn on the BL */
1740 if (rdev->mode_info.bl_encoder) {
1741 u8 bl_level = radeon_get_backlight_level(rdev,
1742 rdev->mode_info.bl_encoder);
1743 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1744 bl_level);
1745 }
1746 }
1747 /* reset hpd state */
1748 radeon_hpd_init(rdev);
1749 /* blat the mode back in */
1750 if (fbcon) {
1751 drm_helper_resume_force_mode(dev);
1752 /* turn on display hw */
1753 drm_modeset_lock_all(dev);
1754 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1755 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1756 }
1757 drm_modeset_unlock_all(dev);
1758 }
1759
1760 drm_kms_helper_poll_enable(dev);
1761
1762 /* set the power state here in case we are a PX system or headless */
1763 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1764 radeon_pm_compute_clocks(rdev);
1765
1766 if (fbcon) {
1767 radeon_fbdev_set_suspend(rdev, 0);
1768 console_unlock();
1769 }
1770
1771 return 0;
1772}
1773
1774/**
1775 * radeon_gpu_reset - reset the asic
1776 *
1777 * @rdev: radeon device pointer
1778 *
1779 * Attempt the reset the GPU if it has hung (all asics).
1780 * Returns 0 for success or an error on failure.
1781 */
1782int radeon_gpu_reset(struct radeon_device *rdev)
1783{
1784 unsigned ring_sizes[RADEON_NUM_RINGS];
1785 uint32_t *ring_data[RADEON_NUM_RINGS];
1786
1787 bool saved = false;
1788
1789 int i, r;
1790 int resched;
1791
1792 down_write(&rdev->exclusive_lock);
1793
1794 if (!rdev->needs_reset) {
1795 up_write(&rdev->exclusive_lock);
1796 return 0;
1797 }
1798
1799 atomic_inc(&rdev->gpu_reset_counter);
1800
1801 radeon_save_bios_scratch_regs(rdev);
1802 /* block TTM */
1803 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1804 radeon_suspend(rdev);
1805 radeon_hpd_fini(rdev);
1806
1807 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1808 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1809 &ring_data[i]);
1810 if (ring_sizes[i]) {
1811 saved = true;
1812 dev_info(rdev->dev, "Saved %d dwords of commands "
1813 "on ring %d.\n", ring_sizes[i], i);
1814 }
1815 }
1816
1817 r = radeon_asic_reset(rdev);
1818 if (!r) {
1819 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1820 radeon_resume(rdev);
1821 }
1822
1823 radeon_restore_bios_scratch_regs(rdev);
1824
1825 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1826 if (!r && ring_data[i]) {
1827 radeon_ring_restore(rdev, &rdev->ring[i],
1828 ring_sizes[i], ring_data[i]);
1829 } else {
1830 radeon_fence_driver_force_completion(rdev, i);
1831 kfree(ring_data[i]);
1832 }
1833 }
1834
1835 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1836 /* do dpm late init */
1837 r = radeon_pm_late_init(rdev);
1838 if (r) {
1839 rdev->pm.dpm_enabled = false;
1840 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1841 }
1842 } else {
1843 /* resume old pm late */
1844 radeon_pm_resume(rdev);
1845 }
1846
1847 /* init dig PHYs, disp eng pll */
1848 if (rdev->is_atom_bios) {
1849 radeon_atom_encoder_init(rdev);
1850 radeon_atom_disp_eng_pll_init(rdev);
1851 /* turn on the BL */
1852 if (rdev->mode_info.bl_encoder) {
1853 u8 bl_level = radeon_get_backlight_level(rdev,
1854 rdev->mode_info.bl_encoder);
1855 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1856 bl_level);
1857 }
1858 }
1859 /* reset hpd state */
1860 radeon_hpd_init(rdev);
1861
1862 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1863
1864 rdev->in_reset = true;
1865 rdev->needs_reset = false;
1866
1867 downgrade_write(&rdev->exclusive_lock);
1868
1869 drm_helper_resume_force_mode(rdev->ddev);
1870
1871 /* set the power state here in case we are a PX system or headless */
1872 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1873 radeon_pm_compute_clocks(rdev);
1874
1875 if (!r) {
1876 r = radeon_ib_ring_tests(rdev);
1877 if (r && saved)
1878 r = -EAGAIN;
1879 } else {
1880 /* bad news, how to tell it to userspace ? */
1881 dev_info(rdev->dev, "GPU reset failed\n");
1882 }
1883
1884 rdev->needs_reset = r == -EAGAIN;
1885 rdev->in_reset = false;
1886
1887 up_read(&rdev->exclusive_lock);
1888 return r;
1889}
1890
1891
1892/*
1893 * Debugfs
1894 */
1895int radeon_debugfs_add_files(struct radeon_device *rdev,
1896 struct drm_info_list *files,
1897 unsigned nfiles)
1898{
1899 unsigned i;
1900
1901 for (i = 0; i < rdev->debugfs_count; i++) {
1902 if (rdev->debugfs[i].files == files) {
1903 /* Already registered */
1904 return 0;
1905 }
1906 }
1907
1908 i = rdev->debugfs_count + 1;
1909 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1910 DRM_ERROR("Reached maximum number of debugfs components.\n");
1911 DRM_ERROR("Report so we increase "
1912 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1913 return -EINVAL;
1914 }
1915 rdev->debugfs[rdev->debugfs_count].files = files;
1916 rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1917 rdev->debugfs_count = i;
1918#if defined(CONFIG_DEBUG_FS)
1919 drm_debugfs_create_files(files, nfiles,
1920 rdev->ddev->primary->debugfs_root,
1921 rdev->ddev->primary);
1922#endif
1923 return 0;
1924}