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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/console.h>
29#include <linux/slab.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
33#include <linux/vgaarb.h>
34#include <linux/vga_switcheroo.h>
35#include <linux/efi.h>
36#include "radeon_reg.h"
37#include "radeon.h"
38#include "atom.h"
39
40static const char radeon_family_name[][16] = {
41 "R100",
42 "RV100",
43 "RS100",
44 "RV200",
45 "RS200",
46 "R200",
47 "RV250",
48 "RS300",
49 "RV280",
50 "R300",
51 "R350",
52 "RV350",
53 "RV380",
54 "R420",
55 "R423",
56 "RV410",
57 "RS400",
58 "RS480",
59 "RS600",
60 "RS690",
61 "RS740",
62 "RV515",
63 "R520",
64 "RV530",
65 "RV560",
66 "RV570",
67 "R580",
68 "R600",
69 "RV610",
70 "RV630",
71 "RV670",
72 "RV620",
73 "RV635",
74 "RS780",
75 "RS880",
76 "RV770",
77 "RV730",
78 "RV710",
79 "RV740",
80 "CEDAR",
81 "REDWOOD",
82 "JUNIPER",
83 "CYPRESS",
84 "HEMLOCK",
85 "PALM",
86 "SUMO",
87 "SUMO2",
88 "BARTS",
89 "TURKS",
90 "CAICOS",
91 "CAYMAN",
92 "LAST",
93};
94
95/*
96 * Clear GPU surface registers.
97 */
98void radeon_surface_init(struct radeon_device *rdev)
99{
100 /* FIXME: check this out */
101 if (rdev->family < CHIP_R600) {
102 int i;
103
104 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
105 if (rdev->surface_regs[i].bo)
106 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
107 else
108 radeon_clear_surface_reg(rdev, i);
109 }
110 /* enable surfaces */
111 WREG32(RADEON_SURFACE_CNTL, 0);
112 }
113}
114
115/*
116 * GPU scratch registers helpers function.
117 */
118void radeon_scratch_init(struct radeon_device *rdev)
119{
120 int i;
121
122 /* FIXME: check this out */
123 if (rdev->family < CHIP_R300) {
124 rdev->scratch.num_reg = 5;
125 } else {
126 rdev->scratch.num_reg = 7;
127 }
128 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
129 for (i = 0; i < rdev->scratch.num_reg; i++) {
130 rdev->scratch.free[i] = true;
131 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
132 }
133}
134
135int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
136{
137 int i;
138
139 for (i = 0; i < rdev->scratch.num_reg; i++) {
140 if (rdev->scratch.free[i]) {
141 rdev->scratch.free[i] = false;
142 *reg = rdev->scratch.reg[i];
143 return 0;
144 }
145 }
146 return -EINVAL;
147}
148
149void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
150{
151 int i;
152
153 for (i = 0; i < rdev->scratch.num_reg; i++) {
154 if (rdev->scratch.reg[i] == reg) {
155 rdev->scratch.free[i] = true;
156 return;
157 }
158 }
159}
160
161void radeon_wb_disable(struct radeon_device *rdev)
162{
163 int r;
164
165 if (rdev->wb.wb_obj) {
166 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
167 if (unlikely(r != 0))
168 return;
169 radeon_bo_kunmap(rdev->wb.wb_obj);
170 radeon_bo_unpin(rdev->wb.wb_obj);
171 radeon_bo_unreserve(rdev->wb.wb_obj);
172 }
173 rdev->wb.enabled = false;
174}
175
176void radeon_wb_fini(struct radeon_device *rdev)
177{
178 radeon_wb_disable(rdev);
179 if (rdev->wb.wb_obj) {
180 radeon_bo_unref(&rdev->wb.wb_obj);
181 rdev->wb.wb = NULL;
182 rdev->wb.wb_obj = NULL;
183 }
184}
185
186int radeon_wb_init(struct radeon_device *rdev)
187{
188 int r;
189
190 if (rdev->wb.wb_obj == NULL) {
191 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
192 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
193 if (r) {
194 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
195 return r;
196 }
197 }
198 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
199 if (unlikely(r != 0)) {
200 radeon_wb_fini(rdev);
201 return r;
202 }
203 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
204 &rdev->wb.gpu_addr);
205 if (r) {
206 radeon_bo_unreserve(rdev->wb.wb_obj);
207 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
208 radeon_wb_fini(rdev);
209 return r;
210 }
211 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
212 radeon_bo_unreserve(rdev->wb.wb_obj);
213 if (r) {
214 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
215 radeon_wb_fini(rdev);
216 return r;
217 }
218
219 /* clear wb memory */
220 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
221 /* disable event_write fences */
222 rdev->wb.use_event = false;
223 /* disabled via module param */
224 if (radeon_no_wb == 1)
225 rdev->wb.enabled = false;
226 else {
227 /* often unreliable on AGP */
228 if (rdev->flags & RADEON_IS_AGP) {
229 rdev->wb.enabled = false;
230 } else {
231 rdev->wb.enabled = true;
232 /* event_write fences are only available on r600+ */
233 if (rdev->family >= CHIP_R600)
234 rdev->wb.use_event = true;
235 }
236 }
237 /* always use writeback/events on NI */
238 if (ASIC_IS_DCE5(rdev)) {
239 rdev->wb.enabled = true;
240 rdev->wb.use_event = true;
241 }
242
243 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
244
245 return 0;
246}
247
248/**
249 * radeon_vram_location - try to find VRAM location
250 * @rdev: radeon device structure holding all necessary informations
251 * @mc: memory controller structure holding memory informations
252 * @base: base address at which to put VRAM
253 *
254 * Function will place try to place VRAM at base address provided
255 * as parameter (which is so far either PCI aperture address or
256 * for IGP TOM base address).
257 *
258 * If there is not enough space to fit the unvisible VRAM in the 32bits
259 * address space then we limit the VRAM size to the aperture.
260 *
261 * If we are using AGP and if the AGP aperture doesn't allow us to have
262 * room for all the VRAM than we restrict the VRAM to the PCI aperture
263 * size and print a warning.
264 *
265 * This function will never fails, worst case are limiting VRAM.
266 *
267 * Note: GTT start, end, size should be initialized before calling this
268 * function on AGP platform.
269 *
270 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
271 * this shouldn't be a problem as we are using the PCI aperture as a reference.
272 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
273 * not IGP.
274 *
275 * Note: we use mc_vram_size as on some board we need to program the mc to
276 * cover the whole aperture even if VRAM size is inferior to aperture size
277 * Novell bug 204882 + along with lots of ubuntu ones
278 *
279 * Note: when limiting vram it's safe to overwritte real_vram_size because
280 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
281 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
282 * ones)
283 *
284 * Note: IGP TOM addr should be the same as the aperture addr, we don't
285 * explicitly check for that thought.
286 *
287 * FIXME: when reducing VRAM size align new size on power of 2.
288 */
289void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
290{
291 mc->vram_start = base;
292 if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
293 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
294 mc->real_vram_size = mc->aper_size;
295 mc->mc_vram_size = mc->aper_size;
296 }
297 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
298 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
299 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
300 mc->real_vram_size = mc->aper_size;
301 mc->mc_vram_size = mc->aper_size;
302 }
303 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
304 if (radeon_vram_limit && radeon_vram_limit < mc->real_vram_size)
305 mc->real_vram_size = radeon_vram_limit;
306 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
307 mc->mc_vram_size >> 20, mc->vram_start,
308 mc->vram_end, mc->real_vram_size >> 20);
309}
310
311/**
312 * radeon_gtt_location - try to find GTT location
313 * @rdev: radeon device structure holding all necessary informations
314 * @mc: memory controller structure holding memory informations
315 *
316 * Function will place try to place GTT before or after VRAM.
317 *
318 * If GTT size is bigger than space left then we ajust GTT size.
319 * Thus function will never fails.
320 *
321 * FIXME: when reducing GTT size align new size on power of 2.
322 */
323void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
324{
325 u64 size_af, size_bf;
326
327 size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
328 size_bf = mc->vram_start & ~mc->gtt_base_align;
329 if (size_bf > size_af) {
330 if (mc->gtt_size > size_bf) {
331 dev_warn(rdev->dev, "limiting GTT\n");
332 mc->gtt_size = size_bf;
333 }
334 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
335 } else {
336 if (mc->gtt_size > size_af) {
337 dev_warn(rdev->dev, "limiting GTT\n");
338 mc->gtt_size = size_af;
339 }
340 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
341 }
342 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
343 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
344 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
345}
346
347/*
348 * GPU helpers function.
349 */
350bool radeon_card_posted(struct radeon_device *rdev)
351{
352 uint32_t reg;
353
354 if (efi_enabled && rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE)
355 return false;
356
357 /* first check CRTCs */
358 if (ASIC_IS_DCE41(rdev)) {
359 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
360 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
361 if (reg & EVERGREEN_CRTC_MASTER_EN)
362 return true;
363 } else if (ASIC_IS_DCE4(rdev)) {
364 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
365 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
366 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
367 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
368 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
369 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
370 if (reg & EVERGREEN_CRTC_MASTER_EN)
371 return true;
372 } else if (ASIC_IS_AVIVO(rdev)) {
373 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
374 RREG32(AVIVO_D2CRTC_CONTROL);
375 if (reg & AVIVO_CRTC_EN) {
376 return true;
377 }
378 } else {
379 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
380 RREG32(RADEON_CRTC2_GEN_CNTL);
381 if (reg & RADEON_CRTC_EN) {
382 return true;
383 }
384 }
385
386 /* then check MEM_SIZE, in case the crtcs are off */
387 if (rdev->family >= CHIP_R600)
388 reg = RREG32(R600_CONFIG_MEMSIZE);
389 else
390 reg = RREG32(RADEON_CONFIG_MEMSIZE);
391
392 if (reg)
393 return true;
394
395 return false;
396
397}
398
399void radeon_update_bandwidth_info(struct radeon_device *rdev)
400{
401 fixed20_12 a;
402 u32 sclk = rdev->pm.current_sclk;
403 u32 mclk = rdev->pm.current_mclk;
404
405 /* sclk/mclk in Mhz */
406 a.full = dfixed_const(100);
407 rdev->pm.sclk.full = dfixed_const(sclk);
408 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
409 rdev->pm.mclk.full = dfixed_const(mclk);
410 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
411
412 if (rdev->flags & RADEON_IS_IGP) {
413 a.full = dfixed_const(16);
414 /* core_bandwidth = sclk(Mhz) * 16 */
415 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
416 }
417}
418
419bool radeon_boot_test_post_card(struct radeon_device *rdev)
420{
421 if (radeon_card_posted(rdev))
422 return true;
423
424 if (rdev->bios) {
425 DRM_INFO("GPU not posted. posting now...\n");
426 if (rdev->is_atom_bios)
427 atom_asic_init(rdev->mode_info.atom_context);
428 else
429 radeon_combios_asic_init(rdev->ddev);
430 return true;
431 } else {
432 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
433 return false;
434 }
435}
436
437int radeon_dummy_page_init(struct radeon_device *rdev)
438{
439 if (rdev->dummy_page.page)
440 return 0;
441 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
442 if (rdev->dummy_page.page == NULL)
443 return -ENOMEM;
444 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
445 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
446 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
447 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
448 __free_page(rdev->dummy_page.page);
449 rdev->dummy_page.page = NULL;
450 return -ENOMEM;
451 }
452 return 0;
453}
454
455void radeon_dummy_page_fini(struct radeon_device *rdev)
456{
457 if (rdev->dummy_page.page == NULL)
458 return;
459 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
460 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
461 __free_page(rdev->dummy_page.page);
462 rdev->dummy_page.page = NULL;
463}
464
465
466/* ATOM accessor methods */
467static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
468{
469 struct radeon_device *rdev = info->dev->dev_private;
470 uint32_t r;
471
472 r = rdev->pll_rreg(rdev, reg);
473 return r;
474}
475
476static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
477{
478 struct radeon_device *rdev = info->dev->dev_private;
479
480 rdev->pll_wreg(rdev, reg, val);
481}
482
483static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
484{
485 struct radeon_device *rdev = info->dev->dev_private;
486 uint32_t r;
487
488 r = rdev->mc_rreg(rdev, reg);
489 return r;
490}
491
492static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
493{
494 struct radeon_device *rdev = info->dev->dev_private;
495
496 rdev->mc_wreg(rdev, reg, val);
497}
498
499static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
500{
501 struct radeon_device *rdev = info->dev->dev_private;
502
503 WREG32(reg*4, val);
504}
505
506static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
507{
508 struct radeon_device *rdev = info->dev->dev_private;
509 uint32_t r;
510
511 r = RREG32(reg*4);
512 return r;
513}
514
515static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
516{
517 struct radeon_device *rdev = info->dev->dev_private;
518
519 WREG32_IO(reg*4, val);
520}
521
522static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
523{
524 struct radeon_device *rdev = info->dev->dev_private;
525 uint32_t r;
526
527 r = RREG32_IO(reg*4);
528 return r;
529}
530
531int radeon_atombios_init(struct radeon_device *rdev)
532{
533 struct card_info *atom_card_info =
534 kzalloc(sizeof(struct card_info), GFP_KERNEL);
535
536 if (!atom_card_info)
537 return -ENOMEM;
538
539 rdev->mode_info.atom_card_info = atom_card_info;
540 atom_card_info->dev = rdev->ddev;
541 atom_card_info->reg_read = cail_reg_read;
542 atom_card_info->reg_write = cail_reg_write;
543 /* needed for iio ops */
544 if (rdev->rio_mem) {
545 atom_card_info->ioreg_read = cail_ioreg_read;
546 atom_card_info->ioreg_write = cail_ioreg_write;
547 } else {
548 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
549 atom_card_info->ioreg_read = cail_reg_read;
550 atom_card_info->ioreg_write = cail_reg_write;
551 }
552 atom_card_info->mc_read = cail_mc_read;
553 atom_card_info->mc_write = cail_mc_write;
554 atom_card_info->pll_read = cail_pll_read;
555 atom_card_info->pll_write = cail_pll_write;
556
557 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
558 mutex_init(&rdev->mode_info.atom_context->mutex);
559 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
560 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
561 return 0;
562}
563
564void radeon_atombios_fini(struct radeon_device *rdev)
565{
566 if (rdev->mode_info.atom_context) {
567 kfree(rdev->mode_info.atom_context->scratch);
568 kfree(rdev->mode_info.atom_context);
569 }
570 kfree(rdev->mode_info.atom_card_info);
571}
572
573int radeon_combios_init(struct radeon_device *rdev)
574{
575 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
576 return 0;
577}
578
579void radeon_combios_fini(struct radeon_device *rdev)
580{
581}
582
583/* if we get transitioned to only one device, tak VGA back */
584static unsigned int radeon_vga_set_decode(void *cookie, bool state)
585{
586 struct radeon_device *rdev = cookie;
587 radeon_vga_set_state(rdev, state);
588 if (state)
589 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
590 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
591 else
592 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
593}
594
595void radeon_check_arguments(struct radeon_device *rdev)
596{
597 /* vramlimit must be a power of two */
598 switch (radeon_vram_limit) {
599 case 0:
600 case 4:
601 case 8:
602 case 16:
603 case 32:
604 case 64:
605 case 128:
606 case 256:
607 case 512:
608 case 1024:
609 case 2048:
610 case 4096:
611 break;
612 default:
613 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
614 radeon_vram_limit);
615 radeon_vram_limit = 0;
616 break;
617 }
618 radeon_vram_limit = radeon_vram_limit << 20;
619 /* gtt size must be power of two and greater or equal to 32M */
620 switch (radeon_gart_size) {
621 case 4:
622 case 8:
623 case 16:
624 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
625 radeon_gart_size);
626 radeon_gart_size = 512;
627 break;
628 case 32:
629 case 64:
630 case 128:
631 case 256:
632 case 512:
633 case 1024:
634 case 2048:
635 case 4096:
636 break;
637 default:
638 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
639 radeon_gart_size);
640 radeon_gart_size = 512;
641 break;
642 }
643 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
644 /* AGP mode can only be -1, 1, 2, 4, 8 */
645 switch (radeon_agpmode) {
646 case -1:
647 case 0:
648 case 1:
649 case 2:
650 case 4:
651 case 8:
652 break;
653 default:
654 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
655 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
656 radeon_agpmode = 0;
657 break;
658 }
659}
660
661static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
662{
663 struct drm_device *dev = pci_get_drvdata(pdev);
664 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
665 if (state == VGA_SWITCHEROO_ON) {
666 printk(KERN_INFO "radeon: switched on\n");
667 /* don't suspend or resume card normally */
668 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
669 radeon_resume_kms(dev);
670 dev->switch_power_state = DRM_SWITCH_POWER_ON;
671 drm_kms_helper_poll_enable(dev);
672 } else {
673 printk(KERN_INFO "radeon: switched off\n");
674 drm_kms_helper_poll_disable(dev);
675 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
676 radeon_suspend_kms(dev, pmm);
677 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
678 }
679}
680
681static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
682{
683 struct drm_device *dev = pci_get_drvdata(pdev);
684 bool can_switch;
685
686 spin_lock(&dev->count_lock);
687 can_switch = (dev->open_count == 0);
688 spin_unlock(&dev->count_lock);
689 return can_switch;
690}
691
692
693int radeon_device_init(struct radeon_device *rdev,
694 struct drm_device *ddev,
695 struct pci_dev *pdev,
696 uint32_t flags)
697{
698 int r, i;
699 int dma_bits;
700
701 rdev->shutdown = false;
702 rdev->dev = &pdev->dev;
703 rdev->ddev = ddev;
704 rdev->pdev = pdev;
705 rdev->flags = flags;
706 rdev->family = flags & RADEON_FAMILY_MASK;
707 rdev->is_atom_bios = false;
708 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
709 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
710 rdev->gpu_lockup = false;
711 rdev->accel_working = false;
712
713 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
714 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
715 pdev->subsystem_vendor, pdev->subsystem_device);
716
717 /* mutex initialization are all done here so we
718 * can recall function without having locking issues */
719 mutex_init(&rdev->cs_mutex);
720 mutex_init(&rdev->ib_pool.mutex);
721 mutex_init(&rdev->cp.mutex);
722 mutex_init(&rdev->dc_hw_i2c_mutex);
723 if (rdev->family >= CHIP_R600)
724 spin_lock_init(&rdev->ih.lock);
725 mutex_init(&rdev->gem.mutex);
726 mutex_init(&rdev->pm.mutex);
727 mutex_init(&rdev->vram_mutex);
728 rwlock_init(&rdev->fence_drv.lock);
729 INIT_LIST_HEAD(&rdev->gem.objects);
730 init_waitqueue_head(&rdev->irq.vblank_queue);
731 init_waitqueue_head(&rdev->irq.idle_queue);
732
733 /* Set asic functions */
734 r = radeon_asic_init(rdev);
735 if (r)
736 return r;
737 radeon_check_arguments(rdev);
738
739 /* all of the newer IGP chips have an internal gart
740 * However some rs4xx report as AGP, so remove that here.
741 */
742 if ((rdev->family >= CHIP_RS400) &&
743 (rdev->flags & RADEON_IS_IGP)) {
744 rdev->flags &= ~RADEON_IS_AGP;
745 }
746
747 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
748 radeon_agp_disable(rdev);
749 }
750
751 /* set DMA mask + need_dma32 flags.
752 * PCIE - can handle 40-bits.
753 * IGP - can handle 40-bits (in theory)
754 * AGP - generally dma32 is safest
755 * PCI - only dma32
756 */
757 rdev->need_dma32 = false;
758 if (rdev->flags & RADEON_IS_AGP)
759 rdev->need_dma32 = true;
760 if (rdev->flags & RADEON_IS_PCI)
761 rdev->need_dma32 = true;
762
763 dma_bits = rdev->need_dma32 ? 32 : 40;
764 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
765 if (r) {
766 rdev->need_dma32 = true;
767 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
768 }
769
770 /* Registers mapping */
771 /* TODO: block userspace mapping of io register */
772 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
773 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
774 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
775 if (rdev->rmmio == NULL) {
776 return -ENOMEM;
777 }
778 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
779 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
780
781 /* io port mapping */
782 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
783 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
784 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
785 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
786 break;
787 }
788 }
789 if (rdev->rio_mem == NULL)
790 DRM_ERROR("Unable to find PCI I/O BAR\n");
791
792 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
793 /* this will fail for cards that aren't VGA class devices, just
794 * ignore it */
795 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
796 vga_switcheroo_register_client(rdev->pdev,
797 radeon_switcheroo_set_state,
798 NULL,
799 radeon_switcheroo_can_switch);
800
801 r = radeon_init(rdev);
802 if (r)
803 return r;
804
805 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
806 /* Acceleration not working on AGP card try again
807 * with fallback to PCI or PCIE GART
808 */
809 radeon_asic_reset(rdev);
810 radeon_fini(rdev);
811 radeon_agp_disable(rdev);
812 r = radeon_init(rdev);
813 if (r)
814 return r;
815 }
816 if (radeon_testing) {
817 radeon_test_moves(rdev);
818 }
819 if (radeon_benchmarking) {
820 radeon_benchmark(rdev);
821 }
822 return 0;
823}
824
825void radeon_device_fini(struct radeon_device *rdev)
826{
827 DRM_INFO("radeon: finishing device.\n");
828 rdev->shutdown = true;
829 /* evict vram memory */
830 radeon_bo_evict_vram(rdev);
831 radeon_fini(rdev);
832 vga_switcheroo_unregister_client(rdev->pdev);
833 vga_client_register(rdev->pdev, NULL, NULL, NULL);
834 if (rdev->rio_mem)
835 pci_iounmap(rdev->pdev, rdev->rio_mem);
836 rdev->rio_mem = NULL;
837 iounmap(rdev->rmmio);
838 rdev->rmmio = NULL;
839}
840
841
842/*
843 * Suspend & resume.
844 */
845int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
846{
847 struct radeon_device *rdev;
848 struct drm_crtc *crtc;
849 struct drm_connector *connector;
850 int r;
851
852 if (dev == NULL || dev->dev_private == NULL) {
853 return -ENODEV;
854 }
855 if (state.event == PM_EVENT_PRETHAW) {
856 return 0;
857 }
858 rdev = dev->dev_private;
859
860 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
861 return 0;
862
863 /* turn off display hw */
864 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
865 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
866 }
867
868 /* unpin the front buffers */
869 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
870 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
871 struct radeon_bo *robj;
872
873 if (rfb == NULL || rfb->obj == NULL) {
874 continue;
875 }
876 robj = gem_to_radeon_bo(rfb->obj);
877 /* don't unpin kernel fb objects */
878 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
879 r = radeon_bo_reserve(robj, false);
880 if (r == 0) {
881 radeon_bo_unpin(robj);
882 radeon_bo_unreserve(robj);
883 }
884 }
885 }
886 /* evict vram memory */
887 radeon_bo_evict_vram(rdev);
888 /* wait for gpu to finish processing current batch */
889 radeon_fence_wait_last(rdev);
890
891 radeon_save_bios_scratch_regs(rdev);
892
893 radeon_pm_suspend(rdev);
894 radeon_suspend(rdev);
895 radeon_hpd_fini(rdev);
896 /* evict remaining vram memory */
897 radeon_bo_evict_vram(rdev);
898
899 radeon_agp_suspend(rdev);
900
901 pci_save_state(dev->pdev);
902 if (state.event == PM_EVENT_SUSPEND) {
903 /* Shut down the device */
904 pci_disable_device(dev->pdev);
905 pci_set_power_state(dev->pdev, PCI_D3hot);
906 }
907 console_lock();
908 radeon_fbdev_set_suspend(rdev, 1);
909 console_unlock();
910 return 0;
911}
912
913int radeon_resume_kms(struct drm_device *dev)
914{
915 struct drm_connector *connector;
916 struct radeon_device *rdev = dev->dev_private;
917
918 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
919 return 0;
920
921 console_lock();
922 pci_set_power_state(dev->pdev, PCI_D0);
923 pci_restore_state(dev->pdev);
924 if (pci_enable_device(dev->pdev)) {
925 console_unlock();
926 return -1;
927 }
928 pci_set_master(dev->pdev);
929 /* resume AGP if in use */
930 radeon_agp_resume(rdev);
931 radeon_resume(rdev);
932 radeon_pm_resume(rdev);
933 radeon_restore_bios_scratch_regs(rdev);
934
935 radeon_fbdev_set_suspend(rdev, 0);
936 console_unlock();
937
938 /* init dig PHYs */
939 if (rdev->is_atom_bios)
940 radeon_atom_encoder_init(rdev);
941 /* reset hpd state */
942 radeon_hpd_init(rdev);
943 /* blat the mode back in */
944 drm_helper_resume_force_mode(dev);
945 /* turn on display hw */
946 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
947 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
948 }
949 return 0;
950}
951
952int radeon_gpu_reset(struct radeon_device *rdev)
953{
954 int r;
955 int resched;
956
957 radeon_save_bios_scratch_regs(rdev);
958 /* block TTM */
959 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
960 radeon_suspend(rdev);
961
962 r = radeon_asic_reset(rdev);
963 if (!r) {
964 dev_info(rdev->dev, "GPU reset succeed\n");
965 radeon_resume(rdev);
966 radeon_restore_bios_scratch_regs(rdev);
967 drm_helper_resume_force_mode(rdev->ddev);
968 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
969 return 0;
970 }
971 /* bad news, how to tell it to userspace ? */
972 dev_info(rdev->dev, "GPU reset failed\n");
973 return r;
974}
975
976
977/*
978 * Debugfs
979 */
980struct radeon_debugfs {
981 struct drm_info_list *files;
982 unsigned num_files;
983};
984static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
985static unsigned _radeon_debugfs_count = 0;
986
987int radeon_debugfs_add_files(struct radeon_device *rdev,
988 struct drm_info_list *files,
989 unsigned nfiles)
990{
991 unsigned i;
992
993 for (i = 0; i < _radeon_debugfs_count; i++) {
994 if (_radeon_debugfs[i].files == files) {
995 /* Already registered */
996 return 0;
997 }
998 }
999 if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
1000 DRM_ERROR("Reached maximum number of debugfs files.\n");
1001 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
1002 return -EINVAL;
1003 }
1004 _radeon_debugfs[_radeon_debugfs_count].files = files;
1005 _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
1006 _radeon_debugfs_count++;
1007#if defined(CONFIG_DEBUG_FS)
1008 drm_debugfs_create_files(files, nfiles,
1009 rdev->ddev->control->debugfs_root,
1010 rdev->ddev->control);
1011 drm_debugfs_create_files(files, nfiles,
1012 rdev->ddev->primary->debugfs_root,
1013 rdev->ddev->primary);
1014#endif
1015 return 0;
1016}
1017
1018#if defined(CONFIG_DEBUG_FS)
1019int radeon_debugfs_init(struct drm_minor *minor)
1020{
1021 return 0;
1022}
1023
1024void radeon_debugfs_cleanup(struct drm_minor *minor)
1025{
1026 unsigned i;
1027
1028 for (i = 0; i < _radeon_debugfs_count; i++) {
1029 drm_debugfs_remove_files(_radeon_debugfs[i].files,
1030 _radeon_debugfs[i].num_files, minor);
1031 }
1032}
1033#endif
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/console.h>
29#include <linux/slab.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
33#include <linux/pm_runtime.h>
34#include <linux/vgaarb.h>
35#include <linux/vga_switcheroo.h>
36#include <linux/efi.h>
37#include "radeon_reg.h"
38#include "radeon.h"
39#include "atom.h"
40
41static const char radeon_family_name[][16] = {
42 "R100",
43 "RV100",
44 "RS100",
45 "RV200",
46 "RS200",
47 "R200",
48 "RV250",
49 "RS300",
50 "RV280",
51 "R300",
52 "R350",
53 "RV350",
54 "RV380",
55 "R420",
56 "R423",
57 "RV410",
58 "RS400",
59 "RS480",
60 "RS600",
61 "RS690",
62 "RS740",
63 "RV515",
64 "R520",
65 "RV530",
66 "RV560",
67 "RV570",
68 "R580",
69 "R600",
70 "RV610",
71 "RV630",
72 "RV670",
73 "RV620",
74 "RV635",
75 "RS780",
76 "RS880",
77 "RV770",
78 "RV730",
79 "RV710",
80 "RV740",
81 "CEDAR",
82 "REDWOOD",
83 "JUNIPER",
84 "CYPRESS",
85 "HEMLOCK",
86 "PALM",
87 "SUMO",
88 "SUMO2",
89 "BARTS",
90 "TURKS",
91 "CAICOS",
92 "CAYMAN",
93 "ARUBA",
94 "TAHITI",
95 "PITCAIRN",
96 "VERDE",
97 "OLAND",
98 "HAINAN",
99 "BONAIRE",
100 "KAVERI",
101 "KABINI",
102 "HAWAII",
103 "MULLINS",
104 "LAST",
105};
106
107#if defined(CONFIG_VGA_SWITCHEROO)
108bool radeon_has_atpx_dgpu_power_cntl(void);
109bool radeon_is_atpx_hybrid(void);
110#else
111static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
112static inline bool radeon_is_atpx_hybrid(void) { return false; }
113#endif
114
115#define RADEON_PX_QUIRK_DISABLE_PX (1 << 0)
116#define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)
117
118struct radeon_px_quirk {
119 u32 chip_vendor;
120 u32 chip_device;
121 u32 subsys_vendor;
122 u32 subsys_device;
123 u32 px_quirk_flags;
124};
125
126static struct radeon_px_quirk radeon_px_quirk_list[] = {
127 /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m)
128 * https://bugzilla.kernel.org/show_bug.cgi?id=74551
129 */
130 { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX },
131 /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU
132 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
133 */
134 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX },
135 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
136 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
137 */
138 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX },
139 /* macbook pro 8.2 */
140 { PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP },
141 { 0, 0, 0, 0, 0 },
142};
143
144bool radeon_is_px(struct drm_device *dev)
145{
146 struct radeon_device *rdev = dev->dev_private;
147
148 if (rdev->flags & RADEON_IS_PX)
149 return true;
150 return false;
151}
152
153static void radeon_device_handle_px_quirks(struct radeon_device *rdev)
154{
155 struct radeon_px_quirk *p = radeon_px_quirk_list;
156
157 /* Apply PX quirks */
158 while (p && p->chip_device != 0) {
159 if (rdev->pdev->vendor == p->chip_vendor &&
160 rdev->pdev->device == p->chip_device &&
161 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
162 rdev->pdev->subsystem_device == p->subsys_device) {
163 rdev->px_quirk_flags = p->px_quirk_flags;
164 break;
165 }
166 ++p;
167 }
168
169 if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX)
170 rdev->flags &= ~RADEON_IS_PX;
171
172 /* disable PX is the system doesn't support dGPU power control or hybrid gfx */
173 if (!radeon_is_atpx_hybrid() &&
174 !radeon_has_atpx_dgpu_power_cntl())
175 rdev->flags &= ~RADEON_IS_PX;
176}
177
178/**
179 * radeon_program_register_sequence - program an array of registers.
180 *
181 * @rdev: radeon_device pointer
182 * @registers: pointer to the register array
183 * @array_size: size of the register array
184 *
185 * Programs an array or registers with and and or masks.
186 * This is a helper for setting golden registers.
187 */
188void radeon_program_register_sequence(struct radeon_device *rdev,
189 const u32 *registers,
190 const u32 array_size)
191{
192 u32 tmp, reg, and_mask, or_mask;
193 int i;
194
195 if (array_size % 3)
196 return;
197
198 for (i = 0; i < array_size; i +=3) {
199 reg = registers[i + 0];
200 and_mask = registers[i + 1];
201 or_mask = registers[i + 2];
202
203 if (and_mask == 0xffffffff) {
204 tmp = or_mask;
205 } else {
206 tmp = RREG32(reg);
207 tmp &= ~and_mask;
208 tmp |= or_mask;
209 }
210 WREG32(reg, tmp);
211 }
212}
213
214void radeon_pci_config_reset(struct radeon_device *rdev)
215{
216 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
217}
218
219/**
220 * radeon_surface_init - Clear GPU surface registers.
221 *
222 * @rdev: radeon_device pointer
223 *
224 * Clear GPU surface registers (r1xx-r5xx).
225 */
226void radeon_surface_init(struct radeon_device *rdev)
227{
228 /* FIXME: check this out */
229 if (rdev->family < CHIP_R600) {
230 int i;
231
232 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
233 if (rdev->surface_regs[i].bo)
234 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
235 else
236 radeon_clear_surface_reg(rdev, i);
237 }
238 /* enable surfaces */
239 WREG32(RADEON_SURFACE_CNTL, 0);
240 }
241}
242
243/*
244 * GPU scratch registers helpers function.
245 */
246/**
247 * radeon_scratch_init - Init scratch register driver information.
248 *
249 * @rdev: radeon_device pointer
250 *
251 * Init CP scratch register driver information (r1xx-r5xx)
252 */
253void radeon_scratch_init(struct radeon_device *rdev)
254{
255 int i;
256
257 /* FIXME: check this out */
258 if (rdev->family < CHIP_R300) {
259 rdev->scratch.num_reg = 5;
260 } else {
261 rdev->scratch.num_reg = 7;
262 }
263 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
264 for (i = 0; i < rdev->scratch.num_reg; i++) {
265 rdev->scratch.free[i] = true;
266 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
267 }
268}
269
270/**
271 * radeon_scratch_get - Allocate a scratch register
272 *
273 * @rdev: radeon_device pointer
274 * @reg: scratch register mmio offset
275 *
276 * Allocate a CP scratch register for use by the driver (all asics).
277 * Returns 0 on success or -EINVAL on failure.
278 */
279int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
280{
281 int i;
282
283 for (i = 0; i < rdev->scratch.num_reg; i++) {
284 if (rdev->scratch.free[i]) {
285 rdev->scratch.free[i] = false;
286 *reg = rdev->scratch.reg[i];
287 return 0;
288 }
289 }
290 return -EINVAL;
291}
292
293/**
294 * radeon_scratch_free - Free a scratch register
295 *
296 * @rdev: radeon_device pointer
297 * @reg: scratch register mmio offset
298 *
299 * Free a CP scratch register allocated for use by the driver (all asics)
300 */
301void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
302{
303 int i;
304
305 for (i = 0; i < rdev->scratch.num_reg; i++) {
306 if (rdev->scratch.reg[i] == reg) {
307 rdev->scratch.free[i] = true;
308 return;
309 }
310 }
311}
312
313/*
314 * GPU doorbell aperture helpers function.
315 */
316/**
317 * radeon_doorbell_init - Init doorbell driver information.
318 *
319 * @rdev: radeon_device pointer
320 *
321 * Init doorbell driver information (CIK)
322 * Returns 0 on success, error on failure.
323 */
324static int radeon_doorbell_init(struct radeon_device *rdev)
325{
326 /* doorbell bar mapping */
327 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
328 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
329
330 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
331 if (rdev->doorbell.num_doorbells == 0)
332 return -EINVAL;
333
334 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
335 if (rdev->doorbell.ptr == NULL) {
336 return -ENOMEM;
337 }
338 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
339 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
340
341 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
342
343 return 0;
344}
345
346/**
347 * radeon_doorbell_fini - Tear down doorbell driver information.
348 *
349 * @rdev: radeon_device pointer
350 *
351 * Tear down doorbell driver information (CIK)
352 */
353static void radeon_doorbell_fini(struct radeon_device *rdev)
354{
355 iounmap(rdev->doorbell.ptr);
356 rdev->doorbell.ptr = NULL;
357}
358
359/**
360 * radeon_doorbell_get - Allocate a doorbell entry
361 *
362 * @rdev: radeon_device pointer
363 * @doorbell: doorbell index
364 *
365 * Allocate a doorbell for use by the driver (all asics).
366 * Returns 0 on success or -EINVAL on failure.
367 */
368int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
369{
370 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
371 if (offset < rdev->doorbell.num_doorbells) {
372 __set_bit(offset, rdev->doorbell.used);
373 *doorbell = offset;
374 return 0;
375 } else {
376 return -EINVAL;
377 }
378}
379
380/**
381 * radeon_doorbell_free - Free a doorbell entry
382 *
383 * @rdev: radeon_device pointer
384 * @doorbell: doorbell index
385 *
386 * Free a doorbell allocated for use by the driver (all asics)
387 */
388void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
389{
390 if (doorbell < rdev->doorbell.num_doorbells)
391 __clear_bit(doorbell, rdev->doorbell.used);
392}
393
394/**
395 * radeon_doorbell_get_kfd_info - Report doorbell configuration required to
396 * setup KFD
397 *
398 * @rdev: radeon_device pointer
399 * @aperture_base: output returning doorbell aperture base physical address
400 * @aperture_size: output returning doorbell aperture size in bytes
401 * @start_offset: output returning # of doorbell bytes reserved for radeon.
402 *
403 * Radeon and the KFD share the doorbell aperture. Radeon sets it up,
404 * takes doorbells required for its own rings and reports the setup to KFD.
405 * Radeon reserved doorbells are at the start of the doorbell aperture.
406 */
407void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
408 phys_addr_t *aperture_base,
409 size_t *aperture_size,
410 size_t *start_offset)
411{
412 /* The first num_doorbells are used by radeon.
413 * KFD takes whatever's left in the aperture. */
414 if (rdev->doorbell.size > rdev->doorbell.num_doorbells * sizeof(u32)) {
415 *aperture_base = rdev->doorbell.base;
416 *aperture_size = rdev->doorbell.size;
417 *start_offset = rdev->doorbell.num_doorbells * sizeof(u32);
418 } else {
419 *aperture_base = 0;
420 *aperture_size = 0;
421 *start_offset = 0;
422 }
423}
424
425/*
426 * radeon_wb_*()
427 * Writeback is the the method by which the the GPU updates special pages
428 * in memory with the status of certain GPU events (fences, ring pointers,
429 * etc.).
430 */
431
432/**
433 * radeon_wb_disable - Disable Writeback
434 *
435 * @rdev: radeon_device pointer
436 *
437 * Disables Writeback (all asics). Used for suspend.
438 */
439void radeon_wb_disable(struct radeon_device *rdev)
440{
441 rdev->wb.enabled = false;
442}
443
444/**
445 * radeon_wb_fini - Disable Writeback and free memory
446 *
447 * @rdev: radeon_device pointer
448 *
449 * Disables Writeback and frees the Writeback memory (all asics).
450 * Used at driver shutdown.
451 */
452void radeon_wb_fini(struct radeon_device *rdev)
453{
454 radeon_wb_disable(rdev);
455 if (rdev->wb.wb_obj) {
456 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
457 radeon_bo_kunmap(rdev->wb.wb_obj);
458 radeon_bo_unpin(rdev->wb.wb_obj);
459 radeon_bo_unreserve(rdev->wb.wb_obj);
460 }
461 radeon_bo_unref(&rdev->wb.wb_obj);
462 rdev->wb.wb = NULL;
463 rdev->wb.wb_obj = NULL;
464 }
465}
466
467/**
468 * radeon_wb_init- Init Writeback driver info and allocate memory
469 *
470 * @rdev: radeon_device pointer
471 *
472 * Disables Writeback and frees the Writeback memory (all asics).
473 * Used at driver startup.
474 * Returns 0 on success or an -error on failure.
475 */
476int radeon_wb_init(struct radeon_device *rdev)
477{
478 int r;
479
480 if (rdev->wb.wb_obj == NULL) {
481 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
482 RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL,
483 &rdev->wb.wb_obj);
484 if (r) {
485 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
486 return r;
487 }
488 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
489 if (unlikely(r != 0)) {
490 radeon_wb_fini(rdev);
491 return r;
492 }
493 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
494 &rdev->wb.gpu_addr);
495 if (r) {
496 radeon_bo_unreserve(rdev->wb.wb_obj);
497 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
498 radeon_wb_fini(rdev);
499 return r;
500 }
501 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
502 radeon_bo_unreserve(rdev->wb.wb_obj);
503 if (r) {
504 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
505 radeon_wb_fini(rdev);
506 return r;
507 }
508 }
509
510 /* clear wb memory */
511 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
512 /* disable event_write fences */
513 rdev->wb.use_event = false;
514 /* disabled via module param */
515 if (radeon_no_wb == 1) {
516 rdev->wb.enabled = false;
517 } else {
518 if (rdev->flags & RADEON_IS_AGP) {
519 /* often unreliable on AGP */
520 rdev->wb.enabled = false;
521 } else if (rdev->family < CHIP_R300) {
522 /* often unreliable on pre-r300 */
523 rdev->wb.enabled = false;
524 } else {
525 rdev->wb.enabled = true;
526 /* event_write fences are only available on r600+ */
527 if (rdev->family >= CHIP_R600) {
528 rdev->wb.use_event = true;
529 }
530 }
531 }
532 /* always use writeback/events on NI, APUs */
533 if (rdev->family >= CHIP_PALM) {
534 rdev->wb.enabled = true;
535 rdev->wb.use_event = true;
536 }
537
538 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
539
540 return 0;
541}
542
543/**
544 * radeon_vram_location - try to find VRAM location
545 * @rdev: radeon device structure holding all necessary informations
546 * @mc: memory controller structure holding memory informations
547 * @base: base address at which to put VRAM
548 *
549 * Function will place try to place VRAM at base address provided
550 * as parameter (which is so far either PCI aperture address or
551 * for IGP TOM base address).
552 *
553 * If there is not enough space to fit the unvisible VRAM in the 32bits
554 * address space then we limit the VRAM size to the aperture.
555 *
556 * If we are using AGP and if the AGP aperture doesn't allow us to have
557 * room for all the VRAM than we restrict the VRAM to the PCI aperture
558 * size and print a warning.
559 *
560 * This function will never fails, worst case are limiting VRAM.
561 *
562 * Note: GTT start, end, size should be initialized before calling this
563 * function on AGP platform.
564 *
565 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
566 * this shouldn't be a problem as we are using the PCI aperture as a reference.
567 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
568 * not IGP.
569 *
570 * Note: we use mc_vram_size as on some board we need to program the mc to
571 * cover the whole aperture even if VRAM size is inferior to aperture size
572 * Novell bug 204882 + along with lots of ubuntu ones
573 *
574 * Note: when limiting vram it's safe to overwritte real_vram_size because
575 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
576 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
577 * ones)
578 *
579 * Note: IGP TOM addr should be the same as the aperture addr, we don't
580 * explicitly check for that thought.
581 *
582 * FIXME: when reducing VRAM size align new size on power of 2.
583 */
584void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
585{
586 uint64_t limit = (uint64_t)radeon_vram_limit << 20;
587
588 mc->vram_start = base;
589 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
590 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
591 mc->real_vram_size = mc->aper_size;
592 mc->mc_vram_size = mc->aper_size;
593 }
594 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
595 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
596 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
597 mc->real_vram_size = mc->aper_size;
598 mc->mc_vram_size = mc->aper_size;
599 }
600 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
601 if (limit && limit < mc->real_vram_size)
602 mc->real_vram_size = limit;
603 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
604 mc->mc_vram_size >> 20, mc->vram_start,
605 mc->vram_end, mc->real_vram_size >> 20);
606}
607
608/**
609 * radeon_gtt_location - try to find GTT location
610 * @rdev: radeon device structure holding all necessary informations
611 * @mc: memory controller structure holding memory informations
612 *
613 * Function will place try to place GTT before or after VRAM.
614 *
615 * If GTT size is bigger than space left then we ajust GTT size.
616 * Thus function will never fails.
617 *
618 * FIXME: when reducing GTT size align new size on power of 2.
619 */
620void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
621{
622 u64 size_af, size_bf;
623
624 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
625 size_bf = mc->vram_start & ~mc->gtt_base_align;
626 if (size_bf > size_af) {
627 if (mc->gtt_size > size_bf) {
628 dev_warn(rdev->dev, "limiting GTT\n");
629 mc->gtt_size = size_bf;
630 }
631 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
632 } else {
633 if (mc->gtt_size > size_af) {
634 dev_warn(rdev->dev, "limiting GTT\n");
635 mc->gtt_size = size_af;
636 }
637 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
638 }
639 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
640 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
641 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
642}
643
644/*
645 * GPU helpers function.
646 */
647
648/**
649 * radeon_device_is_virtual - check if we are running is a virtual environment
650 *
651 * Check if the asic has been passed through to a VM (all asics).
652 * Used at driver startup.
653 * Returns true if virtual or false if not.
654 */
655bool radeon_device_is_virtual(void)
656{
657#ifdef CONFIG_X86
658 return boot_cpu_has(X86_FEATURE_HYPERVISOR);
659#else
660 return false;
661#endif
662}
663
664/**
665 * radeon_card_posted - check if the hw has already been initialized
666 *
667 * @rdev: radeon_device pointer
668 *
669 * Check if the asic has been initialized (all asics).
670 * Used at driver startup.
671 * Returns true if initialized or false if not.
672 */
673bool radeon_card_posted(struct radeon_device *rdev)
674{
675 uint32_t reg;
676
677 /* for pass through, always force asic_init for CI */
678 if (rdev->family >= CHIP_BONAIRE &&
679 radeon_device_is_virtual())
680 return false;
681
682 /* required for EFI mode on macbook2,1 which uses an r5xx asic */
683 if (efi_enabled(EFI_BOOT) &&
684 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
685 (rdev->family < CHIP_R600))
686 return false;
687
688 if (ASIC_IS_NODCE(rdev))
689 goto check_memsize;
690
691 /* first check CRTCs */
692 if (ASIC_IS_DCE4(rdev)) {
693 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
694 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
695 if (rdev->num_crtc >= 4) {
696 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
697 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
698 }
699 if (rdev->num_crtc >= 6) {
700 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
701 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
702 }
703 if (reg & EVERGREEN_CRTC_MASTER_EN)
704 return true;
705 } else if (ASIC_IS_AVIVO(rdev)) {
706 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
707 RREG32(AVIVO_D2CRTC_CONTROL);
708 if (reg & AVIVO_CRTC_EN) {
709 return true;
710 }
711 } else {
712 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
713 RREG32(RADEON_CRTC2_GEN_CNTL);
714 if (reg & RADEON_CRTC_EN) {
715 return true;
716 }
717 }
718
719check_memsize:
720 /* then check MEM_SIZE, in case the crtcs are off */
721 if (rdev->family >= CHIP_R600)
722 reg = RREG32(R600_CONFIG_MEMSIZE);
723 else
724 reg = RREG32(RADEON_CONFIG_MEMSIZE);
725
726 if (reg)
727 return true;
728
729 return false;
730
731}
732
733/**
734 * radeon_update_bandwidth_info - update display bandwidth params
735 *
736 * @rdev: radeon_device pointer
737 *
738 * Used when sclk/mclk are switched or display modes are set.
739 * params are used to calculate display watermarks (all asics)
740 */
741void radeon_update_bandwidth_info(struct radeon_device *rdev)
742{
743 fixed20_12 a;
744 u32 sclk = rdev->pm.current_sclk;
745 u32 mclk = rdev->pm.current_mclk;
746
747 /* sclk/mclk in Mhz */
748 a.full = dfixed_const(100);
749 rdev->pm.sclk.full = dfixed_const(sclk);
750 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
751 rdev->pm.mclk.full = dfixed_const(mclk);
752 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
753
754 if (rdev->flags & RADEON_IS_IGP) {
755 a.full = dfixed_const(16);
756 /* core_bandwidth = sclk(Mhz) * 16 */
757 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
758 }
759}
760
761/**
762 * radeon_boot_test_post_card - check and possibly initialize the hw
763 *
764 * @rdev: radeon_device pointer
765 *
766 * Check if the asic is initialized and if not, attempt to initialize
767 * it (all asics).
768 * Returns true if initialized or false if not.
769 */
770bool radeon_boot_test_post_card(struct radeon_device *rdev)
771{
772 if (radeon_card_posted(rdev))
773 return true;
774
775 if (rdev->bios) {
776 DRM_INFO("GPU not posted. posting now...\n");
777 if (rdev->is_atom_bios)
778 atom_asic_init(rdev->mode_info.atom_context);
779 else
780 radeon_combios_asic_init(rdev->ddev);
781 return true;
782 } else {
783 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
784 return false;
785 }
786}
787
788/**
789 * radeon_dummy_page_init - init dummy page used by the driver
790 *
791 * @rdev: radeon_device pointer
792 *
793 * Allocate the dummy page used by the driver (all asics).
794 * This dummy page is used by the driver as a filler for gart entries
795 * when pages are taken out of the GART
796 * Returns 0 on sucess, -ENOMEM on failure.
797 */
798int radeon_dummy_page_init(struct radeon_device *rdev)
799{
800 if (rdev->dummy_page.page)
801 return 0;
802 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
803 if (rdev->dummy_page.page == NULL)
804 return -ENOMEM;
805 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
806 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
807 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
808 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
809 __free_page(rdev->dummy_page.page);
810 rdev->dummy_page.page = NULL;
811 return -ENOMEM;
812 }
813 rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr,
814 RADEON_GART_PAGE_DUMMY);
815 return 0;
816}
817
818/**
819 * radeon_dummy_page_fini - free dummy page used by the driver
820 *
821 * @rdev: radeon_device pointer
822 *
823 * Frees the dummy page used by the driver (all asics).
824 */
825void radeon_dummy_page_fini(struct radeon_device *rdev)
826{
827 if (rdev->dummy_page.page == NULL)
828 return;
829 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
830 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
831 __free_page(rdev->dummy_page.page);
832 rdev->dummy_page.page = NULL;
833}
834
835
836/* ATOM accessor methods */
837/*
838 * ATOM is an interpreted byte code stored in tables in the vbios. The
839 * driver registers callbacks to access registers and the interpreter
840 * in the driver parses the tables and executes then to program specific
841 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
842 * atombios.h, and atom.c
843 */
844
845/**
846 * cail_pll_read - read PLL register
847 *
848 * @info: atom card_info pointer
849 * @reg: PLL register offset
850 *
851 * Provides a PLL register accessor for the atom interpreter (r4xx+).
852 * Returns the value of the PLL register.
853 */
854static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
855{
856 struct radeon_device *rdev = info->dev->dev_private;
857 uint32_t r;
858
859 r = rdev->pll_rreg(rdev, reg);
860 return r;
861}
862
863/**
864 * cail_pll_write - write PLL register
865 *
866 * @info: atom card_info pointer
867 * @reg: PLL register offset
868 * @val: value to write to the pll register
869 *
870 * Provides a PLL register accessor for the atom interpreter (r4xx+).
871 */
872static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
873{
874 struct radeon_device *rdev = info->dev->dev_private;
875
876 rdev->pll_wreg(rdev, reg, val);
877}
878
879/**
880 * cail_mc_read - read MC (Memory Controller) register
881 *
882 * @info: atom card_info pointer
883 * @reg: MC register offset
884 *
885 * Provides an MC register accessor for the atom interpreter (r4xx+).
886 * Returns the value of the MC register.
887 */
888static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
889{
890 struct radeon_device *rdev = info->dev->dev_private;
891 uint32_t r;
892
893 r = rdev->mc_rreg(rdev, reg);
894 return r;
895}
896
897/**
898 * cail_mc_write - write MC (Memory Controller) register
899 *
900 * @info: atom card_info pointer
901 * @reg: MC register offset
902 * @val: value to write to the pll register
903 *
904 * Provides a MC register accessor for the atom interpreter (r4xx+).
905 */
906static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
907{
908 struct radeon_device *rdev = info->dev->dev_private;
909
910 rdev->mc_wreg(rdev, reg, val);
911}
912
913/**
914 * cail_reg_write - write MMIO register
915 *
916 * @info: atom card_info pointer
917 * @reg: MMIO register offset
918 * @val: value to write to the pll register
919 *
920 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
921 */
922static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
923{
924 struct radeon_device *rdev = info->dev->dev_private;
925
926 WREG32(reg*4, val);
927}
928
929/**
930 * cail_reg_read - read MMIO register
931 *
932 * @info: atom card_info pointer
933 * @reg: MMIO register offset
934 *
935 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
936 * Returns the value of the MMIO register.
937 */
938static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
939{
940 struct radeon_device *rdev = info->dev->dev_private;
941 uint32_t r;
942
943 r = RREG32(reg*4);
944 return r;
945}
946
947/**
948 * cail_ioreg_write - write IO register
949 *
950 * @info: atom card_info pointer
951 * @reg: IO register offset
952 * @val: value to write to the pll register
953 *
954 * Provides a IO register accessor for the atom interpreter (r4xx+).
955 */
956static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
957{
958 struct radeon_device *rdev = info->dev->dev_private;
959
960 WREG32_IO(reg*4, val);
961}
962
963/**
964 * cail_ioreg_read - read IO register
965 *
966 * @info: atom card_info pointer
967 * @reg: IO register offset
968 *
969 * Provides an IO register accessor for the atom interpreter (r4xx+).
970 * Returns the value of the IO register.
971 */
972static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
973{
974 struct radeon_device *rdev = info->dev->dev_private;
975 uint32_t r;
976
977 r = RREG32_IO(reg*4);
978 return r;
979}
980
981/**
982 * radeon_atombios_init - init the driver info and callbacks for atombios
983 *
984 * @rdev: radeon_device pointer
985 *
986 * Initializes the driver info and register access callbacks for the
987 * ATOM interpreter (r4xx+).
988 * Returns 0 on sucess, -ENOMEM on failure.
989 * Called at driver startup.
990 */
991int radeon_atombios_init(struct radeon_device *rdev)
992{
993 struct card_info *atom_card_info =
994 kzalloc(sizeof(struct card_info), GFP_KERNEL);
995
996 if (!atom_card_info)
997 return -ENOMEM;
998
999 rdev->mode_info.atom_card_info = atom_card_info;
1000 atom_card_info->dev = rdev->ddev;
1001 atom_card_info->reg_read = cail_reg_read;
1002 atom_card_info->reg_write = cail_reg_write;
1003 /* needed for iio ops */
1004 if (rdev->rio_mem) {
1005 atom_card_info->ioreg_read = cail_ioreg_read;
1006 atom_card_info->ioreg_write = cail_ioreg_write;
1007 } else {
1008 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
1009 atom_card_info->ioreg_read = cail_reg_read;
1010 atom_card_info->ioreg_write = cail_reg_write;
1011 }
1012 atom_card_info->mc_read = cail_mc_read;
1013 atom_card_info->mc_write = cail_mc_write;
1014 atom_card_info->pll_read = cail_pll_read;
1015 atom_card_info->pll_write = cail_pll_write;
1016
1017 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
1018 if (!rdev->mode_info.atom_context) {
1019 radeon_atombios_fini(rdev);
1020 return -ENOMEM;
1021 }
1022
1023 mutex_init(&rdev->mode_info.atom_context->mutex);
1024 mutex_init(&rdev->mode_info.atom_context->scratch_mutex);
1025 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
1026 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
1027 return 0;
1028}
1029
1030/**
1031 * radeon_atombios_fini - free the driver info and callbacks for atombios
1032 *
1033 * @rdev: radeon_device pointer
1034 *
1035 * Frees the driver info and register access callbacks for the ATOM
1036 * interpreter (r4xx+).
1037 * Called at driver shutdown.
1038 */
1039void radeon_atombios_fini(struct radeon_device *rdev)
1040{
1041 if (rdev->mode_info.atom_context) {
1042 kfree(rdev->mode_info.atom_context->scratch);
1043 }
1044 kfree(rdev->mode_info.atom_context);
1045 rdev->mode_info.atom_context = NULL;
1046 kfree(rdev->mode_info.atom_card_info);
1047 rdev->mode_info.atom_card_info = NULL;
1048}
1049
1050/* COMBIOS */
1051/*
1052 * COMBIOS is the bios format prior to ATOM. It provides
1053 * command tables similar to ATOM, but doesn't have a unified
1054 * parser. See radeon_combios.c
1055 */
1056
1057/**
1058 * radeon_combios_init - init the driver info for combios
1059 *
1060 * @rdev: radeon_device pointer
1061 *
1062 * Initializes the driver info for combios (r1xx-r3xx).
1063 * Returns 0 on sucess.
1064 * Called at driver startup.
1065 */
1066int radeon_combios_init(struct radeon_device *rdev)
1067{
1068 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
1069 return 0;
1070}
1071
1072/**
1073 * radeon_combios_fini - free the driver info for combios
1074 *
1075 * @rdev: radeon_device pointer
1076 *
1077 * Frees the driver info for combios (r1xx-r3xx).
1078 * Called at driver shutdown.
1079 */
1080void radeon_combios_fini(struct radeon_device *rdev)
1081{
1082}
1083
1084/* if we get transitioned to only one device, take VGA back */
1085/**
1086 * radeon_vga_set_decode - enable/disable vga decode
1087 *
1088 * @cookie: radeon_device pointer
1089 * @state: enable/disable vga decode
1090 *
1091 * Enable/disable vga decode (all asics).
1092 * Returns VGA resource flags.
1093 */
1094static unsigned int radeon_vga_set_decode(void *cookie, bool state)
1095{
1096 struct radeon_device *rdev = cookie;
1097 radeon_vga_set_state(rdev, state);
1098 if (state)
1099 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1100 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1101 else
1102 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1103}
1104
1105/**
1106 * radeon_check_pot_argument - check that argument is a power of two
1107 *
1108 * @arg: value to check
1109 *
1110 * Validates that a certain argument is a power of two (all asics).
1111 * Returns true if argument is valid.
1112 */
1113static bool radeon_check_pot_argument(int arg)
1114{
1115 return (arg & (arg - 1)) == 0;
1116}
1117
1118/**
1119 * Determine a sensible default GART size according to ASIC family.
1120 *
1121 * @family ASIC family name
1122 */
1123static int radeon_gart_size_auto(enum radeon_family family)
1124{
1125 /* default to a larger gart size on newer asics */
1126 if (family >= CHIP_TAHITI)
1127 return 2048;
1128 else if (family >= CHIP_RV770)
1129 return 1024;
1130 else
1131 return 512;
1132}
1133
1134/**
1135 * radeon_check_arguments - validate module params
1136 *
1137 * @rdev: radeon_device pointer
1138 *
1139 * Validates certain module parameters and updates
1140 * the associated values used by the driver (all asics).
1141 */
1142static void radeon_check_arguments(struct radeon_device *rdev)
1143{
1144 /* vramlimit must be a power of two */
1145 if (!radeon_check_pot_argument(radeon_vram_limit)) {
1146 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
1147 radeon_vram_limit);
1148 radeon_vram_limit = 0;
1149 }
1150
1151 if (radeon_gart_size == -1) {
1152 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1153 }
1154 /* gtt size must be power of two and greater or equal to 32M */
1155 if (radeon_gart_size < 32) {
1156 dev_warn(rdev->dev, "gart size (%d) too small\n",
1157 radeon_gart_size);
1158 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1159 } else if (!radeon_check_pot_argument(radeon_gart_size)) {
1160 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
1161 radeon_gart_size);
1162 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1163 }
1164 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
1165
1166 /* AGP mode can only be -1, 1, 2, 4, 8 */
1167 switch (radeon_agpmode) {
1168 case -1:
1169 case 0:
1170 case 1:
1171 case 2:
1172 case 4:
1173 case 8:
1174 break;
1175 default:
1176 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
1177 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
1178 radeon_agpmode = 0;
1179 break;
1180 }
1181
1182 if (!radeon_check_pot_argument(radeon_vm_size)) {
1183 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n",
1184 radeon_vm_size);
1185 radeon_vm_size = 4;
1186 }
1187
1188 if (radeon_vm_size < 1) {
1189 dev_warn(rdev->dev, "VM size (%d) too small, min is 1GB\n",
1190 radeon_vm_size);
1191 radeon_vm_size = 4;
1192 }
1193
1194 /*
1195 * Max GPUVM size for Cayman, SI and CI are 40 bits.
1196 */
1197 if (radeon_vm_size > 1024) {
1198 dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n",
1199 radeon_vm_size);
1200 radeon_vm_size = 4;
1201 }
1202
1203 /* defines number of bits in page table versus page directory,
1204 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1205 * page table and the remaining bits are in the page directory */
1206 if (radeon_vm_block_size == -1) {
1207
1208 /* Total bits covered by PD + PTs */
1209 unsigned bits = ilog2(radeon_vm_size) + 18;
1210
1211 /* Make sure the PD is 4K in size up to 8GB address space.
1212 Above that split equal between PD and PTs */
1213 if (radeon_vm_size <= 8)
1214 radeon_vm_block_size = bits - 9;
1215 else
1216 radeon_vm_block_size = (bits + 3) / 2;
1217
1218 } else if (radeon_vm_block_size < 9) {
1219 dev_warn(rdev->dev, "VM page table size (%d) too small\n",
1220 radeon_vm_block_size);
1221 radeon_vm_block_size = 9;
1222 }
1223
1224 if (radeon_vm_block_size > 24 ||
1225 (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) {
1226 dev_warn(rdev->dev, "VM page table size (%d) too large\n",
1227 radeon_vm_block_size);
1228 radeon_vm_block_size = 9;
1229 }
1230}
1231
1232/**
1233 * radeon_switcheroo_set_state - set switcheroo state
1234 *
1235 * @pdev: pci dev pointer
1236 * @state: vga_switcheroo state
1237 *
1238 * Callback for the switcheroo driver. Suspends or resumes the
1239 * the asics before or after it is powered up using ACPI methods.
1240 */
1241static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1242{
1243 struct drm_device *dev = pci_get_drvdata(pdev);
1244 struct radeon_device *rdev = dev->dev_private;
1245
1246 if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1247 return;
1248
1249 if (state == VGA_SWITCHEROO_ON) {
1250 unsigned d3_delay = dev->pdev->d3_delay;
1251
1252 printk(KERN_INFO "radeon: switched on\n");
1253 /* don't suspend or resume card normally */
1254 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1255
1256 if (d3_delay < 20 && (rdev->px_quirk_flags & RADEON_PX_QUIRK_LONG_WAKEUP))
1257 dev->pdev->d3_delay = 20;
1258
1259 radeon_resume_kms(dev, true, true);
1260
1261 dev->pdev->d3_delay = d3_delay;
1262
1263 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1264 drm_kms_helper_poll_enable(dev);
1265 } else {
1266 printk(KERN_INFO "radeon: switched off\n");
1267 drm_kms_helper_poll_disable(dev);
1268 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1269 radeon_suspend_kms(dev, true, true, false);
1270 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1271 }
1272}
1273
1274/**
1275 * radeon_switcheroo_can_switch - see if switcheroo state can change
1276 *
1277 * @pdev: pci dev pointer
1278 *
1279 * Callback for the switcheroo driver. Check of the switcheroo
1280 * state can be changed.
1281 * Returns true if the state can be changed, false if not.
1282 */
1283static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
1284{
1285 struct drm_device *dev = pci_get_drvdata(pdev);
1286
1287 /*
1288 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1289 * locking inversion with the driver load path. And the access here is
1290 * completely racy anyway. So don't bother with locking for now.
1291 */
1292 return dev->open_count == 0;
1293}
1294
1295static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
1296 .set_gpu_state = radeon_switcheroo_set_state,
1297 .reprobe = NULL,
1298 .can_switch = radeon_switcheroo_can_switch,
1299};
1300
1301/**
1302 * radeon_device_init - initialize the driver
1303 *
1304 * @rdev: radeon_device pointer
1305 * @pdev: drm dev pointer
1306 * @pdev: pci dev pointer
1307 * @flags: driver flags
1308 *
1309 * Initializes the driver info and hw (all asics).
1310 * Returns 0 for success or an error on failure.
1311 * Called at driver startup.
1312 */
1313int radeon_device_init(struct radeon_device *rdev,
1314 struct drm_device *ddev,
1315 struct pci_dev *pdev,
1316 uint32_t flags)
1317{
1318 int r, i;
1319 int dma_bits;
1320 bool runtime = false;
1321
1322 rdev->shutdown = false;
1323 rdev->dev = &pdev->dev;
1324 rdev->ddev = ddev;
1325 rdev->pdev = pdev;
1326 rdev->flags = flags;
1327 rdev->family = flags & RADEON_FAMILY_MASK;
1328 rdev->is_atom_bios = false;
1329 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1330 rdev->mc.gtt_size = 512 * 1024 * 1024;
1331 rdev->accel_working = false;
1332 /* set up ring ids */
1333 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1334 rdev->ring[i].idx = i;
1335 }
1336 rdev->fence_context = dma_fence_context_alloc(RADEON_NUM_RINGS);
1337
1338 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1339 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1340 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1341
1342 /* mutex initialization are all done here so we
1343 * can recall function without having locking issues */
1344 mutex_init(&rdev->ring_lock);
1345 mutex_init(&rdev->dc_hw_i2c_mutex);
1346 atomic_set(&rdev->ih.lock, 0);
1347 mutex_init(&rdev->gem.mutex);
1348 mutex_init(&rdev->pm.mutex);
1349 mutex_init(&rdev->gpu_clock_mutex);
1350 mutex_init(&rdev->srbm_mutex);
1351 mutex_init(&rdev->grbm_idx_mutex);
1352 init_rwsem(&rdev->pm.mclk_lock);
1353 init_rwsem(&rdev->exclusive_lock);
1354 init_waitqueue_head(&rdev->irq.vblank_queue);
1355 mutex_init(&rdev->mn_lock);
1356 hash_init(rdev->mn_hash);
1357 r = radeon_gem_init(rdev);
1358 if (r)
1359 return r;
1360
1361 radeon_check_arguments(rdev);
1362 /* Adjust VM size here.
1363 * Max GPUVM size for cayman+ is 40 bits.
1364 */
1365 rdev->vm_manager.max_pfn = radeon_vm_size << 18;
1366
1367 /* Set asic functions */
1368 r = radeon_asic_init(rdev);
1369 if (r)
1370 return r;
1371
1372 /* all of the newer IGP chips have an internal gart
1373 * However some rs4xx report as AGP, so remove that here.
1374 */
1375 if ((rdev->family >= CHIP_RS400) &&
1376 (rdev->flags & RADEON_IS_IGP)) {
1377 rdev->flags &= ~RADEON_IS_AGP;
1378 }
1379
1380 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1381 radeon_agp_disable(rdev);
1382 }
1383
1384 /* Set the internal MC address mask
1385 * This is the max address of the GPU's
1386 * internal address space.
1387 */
1388 if (rdev->family >= CHIP_CAYMAN)
1389 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1390 else if (rdev->family >= CHIP_CEDAR)
1391 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
1392 else
1393 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
1394
1395 /* set DMA mask + need_dma32 flags.
1396 * PCIE - can handle 40-bits.
1397 * IGP - can handle 40-bits
1398 * AGP - generally dma32 is safest
1399 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1400 */
1401 rdev->need_dma32 = false;
1402 if (rdev->flags & RADEON_IS_AGP)
1403 rdev->need_dma32 = true;
1404 if ((rdev->flags & RADEON_IS_PCI) &&
1405 (rdev->family <= CHIP_RS740))
1406 rdev->need_dma32 = true;
1407
1408 dma_bits = rdev->need_dma32 ? 32 : 40;
1409 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1410 if (r) {
1411 rdev->need_dma32 = true;
1412 dma_bits = 32;
1413 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
1414 }
1415 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1416 if (r) {
1417 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
1418 printk(KERN_WARNING "radeon: No coherent DMA available.\n");
1419 }
1420
1421 /* Registers mapping */
1422 /* TODO: block userspace mapping of io register */
1423 spin_lock_init(&rdev->mmio_idx_lock);
1424 spin_lock_init(&rdev->smc_idx_lock);
1425 spin_lock_init(&rdev->pll_idx_lock);
1426 spin_lock_init(&rdev->mc_idx_lock);
1427 spin_lock_init(&rdev->pcie_idx_lock);
1428 spin_lock_init(&rdev->pciep_idx_lock);
1429 spin_lock_init(&rdev->pif_idx_lock);
1430 spin_lock_init(&rdev->cg_idx_lock);
1431 spin_lock_init(&rdev->uvd_idx_lock);
1432 spin_lock_init(&rdev->rcu_idx_lock);
1433 spin_lock_init(&rdev->didt_idx_lock);
1434 spin_lock_init(&rdev->end_idx_lock);
1435 if (rdev->family >= CHIP_BONAIRE) {
1436 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
1437 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
1438 } else {
1439 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
1440 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1441 }
1442 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1443 if (rdev->rmmio == NULL) {
1444 return -ENOMEM;
1445 }
1446 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
1447 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
1448
1449 /* doorbell bar mapping */
1450 if (rdev->family >= CHIP_BONAIRE)
1451 radeon_doorbell_init(rdev);
1452
1453 /* io port mapping */
1454 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1455 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
1456 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
1457 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
1458 break;
1459 }
1460 }
1461 if (rdev->rio_mem == NULL)
1462 DRM_ERROR("Unable to find PCI I/O BAR\n");
1463
1464 if (rdev->flags & RADEON_IS_PX)
1465 radeon_device_handle_px_quirks(rdev);
1466
1467 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1468 /* this will fail for cards that aren't VGA class devices, just
1469 * ignore it */
1470 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1471
1472 if (rdev->flags & RADEON_IS_PX)
1473 runtime = true;
1474 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime);
1475 if (runtime)
1476 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain);
1477
1478 r = radeon_init(rdev);
1479 if (r)
1480 goto failed;
1481
1482 r = radeon_gem_debugfs_init(rdev);
1483 if (r) {
1484 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1485 }
1486
1487 r = radeon_mst_debugfs_init(rdev);
1488 if (r) {
1489 DRM_ERROR("registering mst debugfs failed (%d).\n", r);
1490 }
1491
1492 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1493 /* Acceleration not working on AGP card try again
1494 * with fallback to PCI or PCIE GART
1495 */
1496 radeon_asic_reset(rdev);
1497 radeon_fini(rdev);
1498 radeon_agp_disable(rdev);
1499 r = radeon_init(rdev);
1500 if (r)
1501 goto failed;
1502 }
1503
1504 r = radeon_ib_ring_tests(rdev);
1505 if (r)
1506 DRM_ERROR("ib ring test failed (%d).\n", r);
1507
1508 /*
1509 * Turks/Thames GPU will freeze whole laptop if DPM is not restarted
1510 * after the CP ring have chew one packet at least. Hence here we stop
1511 * and restart DPM after the radeon_ib_ring_tests().
1512 */
1513 if (rdev->pm.dpm_enabled &&
1514 (rdev->pm.pm_method == PM_METHOD_DPM) &&
1515 (rdev->family == CHIP_TURKS) &&
1516 (rdev->flags & RADEON_IS_MOBILITY)) {
1517 mutex_lock(&rdev->pm.mutex);
1518 radeon_dpm_disable(rdev);
1519 radeon_dpm_enable(rdev);
1520 mutex_unlock(&rdev->pm.mutex);
1521 }
1522
1523 if ((radeon_testing & 1)) {
1524 if (rdev->accel_working)
1525 radeon_test_moves(rdev);
1526 else
1527 DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1528 }
1529 if ((radeon_testing & 2)) {
1530 if (rdev->accel_working)
1531 radeon_test_syncing(rdev);
1532 else
1533 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1534 }
1535 if (radeon_benchmarking) {
1536 if (rdev->accel_working)
1537 radeon_benchmark(rdev, radeon_benchmarking);
1538 else
1539 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1540 }
1541 return 0;
1542
1543failed:
1544 /* balance pm_runtime_get_sync() in radeon_driver_unload_kms() */
1545 if (radeon_is_px(ddev))
1546 pm_runtime_put_noidle(ddev->dev);
1547 if (runtime)
1548 vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1549 return r;
1550}
1551
1552static void radeon_debugfs_remove_files(struct radeon_device *rdev);
1553
1554/**
1555 * radeon_device_fini - tear down the driver
1556 *
1557 * @rdev: radeon_device pointer
1558 *
1559 * Tear down the driver info (all asics).
1560 * Called at driver shutdown.
1561 */
1562void radeon_device_fini(struct radeon_device *rdev)
1563{
1564 DRM_INFO("radeon: finishing device.\n");
1565 rdev->shutdown = true;
1566 /* evict vram memory */
1567 radeon_bo_evict_vram(rdev);
1568 radeon_fini(rdev);
1569 vga_switcheroo_unregister_client(rdev->pdev);
1570 if (rdev->flags & RADEON_IS_PX)
1571 vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1572 vga_client_register(rdev->pdev, NULL, NULL, NULL);
1573 if (rdev->rio_mem)
1574 pci_iounmap(rdev->pdev, rdev->rio_mem);
1575 rdev->rio_mem = NULL;
1576 iounmap(rdev->rmmio);
1577 rdev->rmmio = NULL;
1578 if (rdev->family >= CHIP_BONAIRE)
1579 radeon_doorbell_fini(rdev);
1580 radeon_debugfs_remove_files(rdev);
1581}
1582
1583
1584/*
1585 * Suspend & resume.
1586 */
1587/**
1588 * radeon_suspend_kms - initiate device suspend
1589 *
1590 * @pdev: drm dev pointer
1591 * @state: suspend state
1592 *
1593 * Puts the hw in the suspend state (all asics).
1594 * Returns 0 for success or an error on failure.
1595 * Called at driver suspend.
1596 */
1597int radeon_suspend_kms(struct drm_device *dev, bool suspend,
1598 bool fbcon, bool freeze)
1599{
1600 struct radeon_device *rdev;
1601 struct drm_crtc *crtc;
1602 struct drm_connector *connector;
1603 int i, r;
1604
1605 if (dev == NULL || dev->dev_private == NULL) {
1606 return -ENODEV;
1607 }
1608
1609 rdev = dev->dev_private;
1610
1611 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1612 return 0;
1613
1614 drm_kms_helper_poll_disable(dev);
1615
1616 drm_modeset_lock_all(dev);
1617 /* turn off display hw */
1618 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1619 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1620 }
1621 drm_modeset_unlock_all(dev);
1622
1623 /* unpin the front buffers and cursors */
1624 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1625 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1626 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb);
1627 struct radeon_bo *robj;
1628
1629 if (radeon_crtc->cursor_bo) {
1630 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
1631 r = radeon_bo_reserve(robj, false);
1632 if (r == 0) {
1633 radeon_bo_unpin(robj);
1634 radeon_bo_unreserve(robj);
1635 }
1636 }
1637
1638 if (rfb == NULL || rfb->obj == NULL) {
1639 continue;
1640 }
1641 robj = gem_to_radeon_bo(rfb->obj);
1642 /* don't unpin kernel fb objects */
1643 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1644 r = radeon_bo_reserve(robj, false);
1645 if (r == 0) {
1646 radeon_bo_unpin(robj);
1647 radeon_bo_unreserve(robj);
1648 }
1649 }
1650 }
1651 /* evict vram memory */
1652 radeon_bo_evict_vram(rdev);
1653
1654 /* wait for gpu to finish processing current batch */
1655 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1656 r = radeon_fence_wait_empty(rdev, i);
1657 if (r) {
1658 /* delay GPU reset to resume */
1659 radeon_fence_driver_force_completion(rdev, i);
1660 }
1661 }
1662
1663 radeon_save_bios_scratch_regs(rdev);
1664
1665 radeon_suspend(rdev);
1666 radeon_hpd_fini(rdev);
1667 /* evict remaining vram memory
1668 * This second call to evict vram is to evict the gart page table
1669 * using the CPU.
1670 */
1671 radeon_bo_evict_vram(rdev);
1672
1673 radeon_agp_suspend(rdev);
1674
1675 pci_save_state(dev->pdev);
1676 if (freeze && rdev->family >= CHIP_CEDAR) {
1677 rdev->asic->asic_reset(rdev, true);
1678 pci_restore_state(dev->pdev);
1679 } else if (suspend) {
1680 /* Shut down the device */
1681 pci_disable_device(dev->pdev);
1682 pci_set_power_state(dev->pdev, PCI_D3hot);
1683 }
1684
1685 if (fbcon) {
1686 console_lock();
1687 radeon_fbdev_set_suspend(rdev, 1);
1688 console_unlock();
1689 }
1690 return 0;
1691}
1692
1693/**
1694 * radeon_resume_kms - initiate device resume
1695 *
1696 * @pdev: drm dev pointer
1697 *
1698 * Bring the hw back to operating state (all asics).
1699 * Returns 0 for success or an error on failure.
1700 * Called at driver resume.
1701 */
1702int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1703{
1704 struct drm_connector *connector;
1705 struct radeon_device *rdev = dev->dev_private;
1706 struct drm_crtc *crtc;
1707 int r;
1708
1709 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1710 return 0;
1711
1712 if (fbcon) {
1713 console_lock();
1714 }
1715 if (resume) {
1716 pci_set_power_state(dev->pdev, PCI_D0);
1717 pci_restore_state(dev->pdev);
1718 if (pci_enable_device(dev->pdev)) {
1719 if (fbcon)
1720 console_unlock();
1721 return -1;
1722 }
1723 }
1724 /* resume AGP if in use */
1725 radeon_agp_resume(rdev);
1726 radeon_resume(rdev);
1727
1728 r = radeon_ib_ring_tests(rdev);
1729 if (r)
1730 DRM_ERROR("ib ring test failed (%d).\n", r);
1731
1732 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1733 /* do dpm late init */
1734 r = radeon_pm_late_init(rdev);
1735 if (r) {
1736 rdev->pm.dpm_enabled = false;
1737 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1738 }
1739 } else {
1740 /* resume old pm late */
1741 radeon_pm_resume(rdev);
1742 }
1743
1744 radeon_restore_bios_scratch_regs(rdev);
1745
1746 /* pin cursors */
1747 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1748 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1749
1750 if (radeon_crtc->cursor_bo) {
1751 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
1752 r = radeon_bo_reserve(robj, false);
1753 if (r == 0) {
1754 /* Only 27 bit offset for legacy cursor */
1755 r = radeon_bo_pin_restricted(robj,
1756 RADEON_GEM_DOMAIN_VRAM,
1757 ASIC_IS_AVIVO(rdev) ?
1758 0 : 1 << 27,
1759 &radeon_crtc->cursor_addr);
1760 if (r != 0)
1761 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
1762 radeon_bo_unreserve(robj);
1763 }
1764 }
1765 }
1766
1767 /* init dig PHYs, disp eng pll */
1768 if (rdev->is_atom_bios) {
1769 radeon_atom_encoder_init(rdev);
1770 radeon_atom_disp_eng_pll_init(rdev);
1771 /* turn on the BL */
1772 if (rdev->mode_info.bl_encoder) {
1773 u8 bl_level = radeon_get_backlight_level(rdev,
1774 rdev->mode_info.bl_encoder);
1775 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1776 bl_level);
1777 }
1778 }
1779 /* reset hpd state */
1780 radeon_hpd_init(rdev);
1781 /* blat the mode back in */
1782 if (fbcon) {
1783 drm_helper_resume_force_mode(dev);
1784 /* turn on display hw */
1785 drm_modeset_lock_all(dev);
1786 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1787 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1788 }
1789 drm_modeset_unlock_all(dev);
1790 }
1791
1792 drm_kms_helper_poll_enable(dev);
1793
1794 /* set the power state here in case we are a PX system or headless */
1795 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1796 radeon_pm_compute_clocks(rdev);
1797
1798 if (fbcon) {
1799 radeon_fbdev_set_suspend(rdev, 0);
1800 console_unlock();
1801 }
1802
1803 return 0;
1804}
1805
1806/**
1807 * radeon_gpu_reset - reset the asic
1808 *
1809 * @rdev: radeon device pointer
1810 *
1811 * Attempt the reset the GPU if it has hung (all asics).
1812 * Returns 0 for success or an error on failure.
1813 */
1814int radeon_gpu_reset(struct radeon_device *rdev)
1815{
1816 unsigned ring_sizes[RADEON_NUM_RINGS];
1817 uint32_t *ring_data[RADEON_NUM_RINGS];
1818
1819 bool saved = false;
1820
1821 int i, r;
1822 int resched;
1823
1824 down_write(&rdev->exclusive_lock);
1825
1826 if (!rdev->needs_reset) {
1827 up_write(&rdev->exclusive_lock);
1828 return 0;
1829 }
1830
1831 atomic_inc(&rdev->gpu_reset_counter);
1832
1833 radeon_save_bios_scratch_regs(rdev);
1834 /* block TTM */
1835 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1836 radeon_suspend(rdev);
1837 radeon_hpd_fini(rdev);
1838
1839 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1840 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1841 &ring_data[i]);
1842 if (ring_sizes[i]) {
1843 saved = true;
1844 dev_info(rdev->dev, "Saved %d dwords of commands "
1845 "on ring %d.\n", ring_sizes[i], i);
1846 }
1847 }
1848
1849 r = radeon_asic_reset(rdev);
1850 if (!r) {
1851 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1852 radeon_resume(rdev);
1853 }
1854
1855 radeon_restore_bios_scratch_regs(rdev);
1856
1857 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1858 if (!r && ring_data[i]) {
1859 radeon_ring_restore(rdev, &rdev->ring[i],
1860 ring_sizes[i], ring_data[i]);
1861 } else {
1862 radeon_fence_driver_force_completion(rdev, i);
1863 kfree(ring_data[i]);
1864 }
1865 }
1866
1867 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1868 /* do dpm late init */
1869 r = radeon_pm_late_init(rdev);
1870 if (r) {
1871 rdev->pm.dpm_enabled = false;
1872 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1873 }
1874 } else {
1875 /* resume old pm late */
1876 radeon_pm_resume(rdev);
1877 }
1878
1879 /* init dig PHYs, disp eng pll */
1880 if (rdev->is_atom_bios) {
1881 radeon_atom_encoder_init(rdev);
1882 radeon_atom_disp_eng_pll_init(rdev);
1883 /* turn on the BL */
1884 if (rdev->mode_info.bl_encoder) {
1885 u8 bl_level = radeon_get_backlight_level(rdev,
1886 rdev->mode_info.bl_encoder);
1887 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1888 bl_level);
1889 }
1890 }
1891 /* reset hpd state */
1892 radeon_hpd_init(rdev);
1893
1894 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1895
1896 rdev->in_reset = true;
1897 rdev->needs_reset = false;
1898
1899 downgrade_write(&rdev->exclusive_lock);
1900
1901 drm_helper_resume_force_mode(rdev->ddev);
1902
1903 /* set the power state here in case we are a PX system or headless */
1904 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1905 radeon_pm_compute_clocks(rdev);
1906
1907 if (!r) {
1908 r = radeon_ib_ring_tests(rdev);
1909 if (r && saved)
1910 r = -EAGAIN;
1911 } else {
1912 /* bad news, how to tell it to userspace ? */
1913 dev_info(rdev->dev, "GPU reset failed\n");
1914 }
1915
1916 rdev->needs_reset = r == -EAGAIN;
1917 rdev->in_reset = false;
1918
1919 up_read(&rdev->exclusive_lock);
1920 return r;
1921}
1922
1923
1924/*
1925 * Debugfs
1926 */
1927int radeon_debugfs_add_files(struct radeon_device *rdev,
1928 struct drm_info_list *files,
1929 unsigned nfiles)
1930{
1931 unsigned i;
1932
1933 for (i = 0; i < rdev->debugfs_count; i++) {
1934 if (rdev->debugfs[i].files == files) {
1935 /* Already registered */
1936 return 0;
1937 }
1938 }
1939
1940 i = rdev->debugfs_count + 1;
1941 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1942 DRM_ERROR("Reached maximum number of debugfs components.\n");
1943 DRM_ERROR("Report so we increase "
1944 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1945 return -EINVAL;
1946 }
1947 rdev->debugfs[rdev->debugfs_count].files = files;
1948 rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1949 rdev->debugfs_count = i;
1950#if defined(CONFIG_DEBUG_FS)
1951 drm_debugfs_create_files(files, nfiles,
1952 rdev->ddev->primary->debugfs_root,
1953 rdev->ddev->primary);
1954#endif
1955 return 0;
1956}
1957
1958static void radeon_debugfs_remove_files(struct radeon_device *rdev)
1959{
1960#if defined(CONFIG_DEBUG_FS)
1961 unsigned i;
1962
1963 for (i = 0; i < rdev->debugfs_count; i++) {
1964 drm_debugfs_remove_files(rdev->debugfs[i].files,
1965 rdev->debugfs[i].num_files,
1966 rdev->ddev->primary);
1967 }
1968#endif
1969}