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v3.1
   1/*
   2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
   3 * Copyright (c) 2007-2008 Intel Corporation
   4 *   Jesse Barnes <jesse.barnes@intel.com>
   5 * Copyright 2010 Red Hat, Inc.
   6 *
   7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
   8 * FB layer.
   9 *   Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
  10 *
  11 * Permission is hereby granted, free of charge, to any person obtaining a
  12 * copy of this software and associated documentation files (the "Software"),
  13 * to deal in the Software without restriction, including without limitation
  14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
  15 * and/or sell copies of the Software, and to permit persons to whom the
  16 * Software is furnished to do so, subject to the following conditions:
  17 *
  18 * The above copyright notice and this permission notice (including the
  19 * next paragraph) shall be included in all copies or substantial portions
  20 * of the Software.
  21 *
  22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  28 * DEALINGS IN THE SOFTWARE.
  29 */
  30#include <linux/kernel.h>
  31#include <linux/slab.h>
 
  32#include <linux/i2c.h>
  33#include "drmP.h"
  34#include "drm_edid.h"
  35#include "drm_edid_modes.h"
 
 
 
 
 
 
  36
  37#define version_greater(edid, maj, min) \
  38	(((edid)->version > (maj)) || \
  39	 ((edid)->version == (maj) && (edid)->revision > (min)))
  40
  41#define EDID_EST_TIMINGS 16
  42#define EDID_STD_TIMINGS 8
  43#define EDID_DETAILED_TIMINGS 4
  44
  45/*
  46 * EDID blocks out in the wild have a variety of bugs, try to collect
  47 * them here (note that userspace may work around broken monitors first,
  48 * but fixes should make their way here so that the kernel "just works"
  49 * on as many displays as possible).
  50 */
  51
  52/* First detailed mode wrong, use largest 60Hz mode */
  53#define EDID_QUIRK_PREFER_LARGE_60		(1 << 0)
  54/* Reported 135MHz pixel clock is too high, needs adjustment */
  55#define EDID_QUIRK_135_CLOCK_TOO_HIGH		(1 << 1)
  56/* Prefer the largest mode at 75 Hz */
  57#define EDID_QUIRK_PREFER_LARGE_75		(1 << 2)
  58/* Detail timing is in cm not mm */
  59#define EDID_QUIRK_DETAILED_IN_CM		(1 << 3)
  60/* Detailed timing descriptors have bogus size values, so just take the
  61 * maximum size and use that.
  62 */
  63#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE	(1 << 4)
  64/* Monitor forgot to set the first detailed is preferred bit. */
  65#define EDID_QUIRK_FIRST_DETAILED_PREFERRED	(1 << 5)
  66/* use +hsync +vsync for detailed mode */
  67#define EDID_QUIRK_DETAILED_SYNC_PP		(1 << 6)
 
 
 
 
 
 
 
 
 
 
 
 
  68
  69struct detailed_mode_closure {
  70	struct drm_connector *connector;
  71	struct edid *edid;
  72	bool preferred;
  73	u32 quirks;
  74	int modes;
  75};
  76
  77#define LEVEL_DMT	0
  78#define LEVEL_GTF	1
  79#define LEVEL_GTF2	2
  80#define LEVEL_CVT	3
  81
  82static struct edid_quirk {
  83	char *vendor;
  84	int product_id;
  85	u32 quirks;
  86} edid_quirk_list[] = {
  87	/* Acer AL1706 */
  88	{ "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
  89	/* Acer F51 */
  90	{ "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
  91	/* Unknown Acer */
  92	{ "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
  93
 
 
 
 
 
 
  94	/* Belinea 10 15 55 */
  95	{ "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
  96	{ "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
  97
  98	/* Envision Peripherals, Inc. EN-7100e */
  99	{ "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
 100	/* Envision EN2028 */
 101	{ "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
 102
 103	/* Funai Electronics PM36B */
 104	{ "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
 105	  EDID_QUIRK_DETAILED_IN_CM },
 106
 
 
 
 107	/* LG Philips LCD LP154W01-A5 */
 108	{ "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
 109	{ "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
 110
 111	/* Philips 107p5 CRT */
 112	{ "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
 113
 114	/* Proview AY765C */
 115	{ "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
 116
 117	/* Samsung SyncMaster 205BW.  Note: irony */
 118	{ "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
 119	/* Samsung SyncMaster 22[5-6]BW */
 120	{ "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
 121	{ "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 122};
 123
 124/*** DDC fetch and block validation ***/
 125
 126static const u8 edid_header[] = {
 127	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
 128};
 129
 130 /*
 131 * Sanity check the header of the base EDID block.  Return 8 if the header
 132 * is perfect, down to 0 if it's totally wrong.
 
 
 
 
 133 */
 134int drm_edid_header_is_valid(const u8 *raw_edid)
 135{
 136	int i, score = 0;
 137
 138	for (i = 0; i < sizeof(edid_header); i++)
 139		if (raw_edid[i] == edid_header[i])
 140			score++;
 141
 142	return score;
 143}
 144EXPORT_SYMBOL(drm_edid_header_is_valid);
 145
 
 
 
 
 146
 147/*
 148 * Sanity check the EDID block (base or extension).  Return 0 if the block
 149 * doesn't check out, or 1 if it's valid.
 150 */
 151static bool
 152drm_edid_block_valid(u8 *raw_edid)
 153{
 154	int i;
 155	u8 csum = 0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 156	struct edid *edid = (struct edid *)raw_edid;
 157
 158	if (raw_edid[0] == 0x00) {
 
 
 
 
 
 
 159		int score = drm_edid_header_is_valid(raw_edid);
 160		if (score == 8) ;
 161		else if (score >= 6) {
 
 
 
 
 
 
 
 
 
 162			DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
 163			memcpy(raw_edid, edid_header, sizeof(edid_header));
 164		} else {
 
 
 165			goto bad;
 166		}
 167	}
 168
 169	for (i = 0; i < EDID_LENGTH; i++)
 170		csum += raw_edid[i];
 171	if (csum) {
 172		DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
 
 173
 174		/* allow CEA to slide through, switches mangle this */
 175		if (raw_edid[0] != 0x02)
 
 
 
 
 
 
 176			goto bad;
 
 177	}
 178
 179	/* per-block-type checks */
 180	switch (raw_edid[0]) {
 181	case 0: /* base */
 182		if (edid->version != 1) {
 183			DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
 184			goto bad;
 185		}
 186
 187		if (edid->revision > 4)
 188			DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
 189		break;
 190
 191	default:
 192		break;
 193	}
 194
 195	return 1;
 196
 197bad:
 198	if (raw_edid) {
 199		printk(KERN_ERR "Raw EDID:\n");
 200		print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1,
 201			       raw_edid, EDID_LENGTH, false);
 
 
 
 
 
 202	}
 203	return 0;
 204}
 
 205
 206/**
 207 * drm_edid_is_valid - sanity check EDID data
 208 * @edid: EDID data
 209 *
 210 * Sanity-check an entire EDID record (including extensions)
 
 
 211 */
 212bool drm_edid_is_valid(struct edid *edid)
 213{
 214	int i;
 215	u8 *raw = (u8 *)edid;
 216
 217	if (!edid)
 218		return false;
 219
 220	for (i = 0; i <= edid->extensions; i++)
 221		if (!drm_edid_block_valid(raw + i * EDID_LENGTH))
 222			return false;
 223
 224	return true;
 225}
 226EXPORT_SYMBOL(drm_edid_is_valid);
 227
 228#define DDC_ADDR 0x50
 229#define DDC_SEGMENT_ADDR 0x30
 230/**
 231 * Get EDID information via I2C.
 
 
 
 
 232 *
 233 * \param adapter : i2c device adaptor
 234 * \param buf     : EDID data buffer to be filled
 235 * \param len     : EDID data buffer length
 236 * \return 0 on success or -1 on failure.
 237 *
 238 * Try to fetch EDID information by calling i2c driver function.
 239 */
 240static int
 241drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf,
 242		      int block, int len)
 243{
 
 244	unsigned char start = block * EDID_LENGTH;
 
 
 245	int ret, retries = 5;
 246
 247	/* The core i2c driver will automatically retry the transfer if the
 
 248	 * adapter reports EAGAIN. However, we find that bit-banging transfers
 249	 * are susceptible to errors under a heavily loaded machine and
 250	 * generate spurious NAKs and timeouts. Retrying the transfer
 251	 * of the individual block a few times seems to overcome this.
 252	 */
 253	do {
 254		struct i2c_msg msgs[] = {
 255			{
 
 
 
 
 
 256				.addr	= DDC_ADDR,
 257				.flags	= 0,
 258				.len	= 1,
 259				.buf	= &start,
 260			}, {
 261				.addr	= DDC_ADDR,
 262				.flags	= I2C_M_RD,
 263				.len	= len,
 264				.buf	= buf,
 265			}
 266		};
 267		ret = i2c_transfer(adapter, msgs, 2);
 268	} while (ret != 2 && --retries);
 269
 270	return ret == 2 ? 0 : -1;
 
 
 
 
 
 
 
 
 
 
 
 
 
 271}
 272
 273static bool drm_edid_is_zero(u8 *in_edid, int length)
 
 274{
 275	int i;
 276	u32 *raw_edid = (u32 *)in_edid;
 277
 278	for (i = 0; i < length / 4; i++)
 279		if (*(raw_edid + i) != 0)
 280			return false;
 281	return true;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 282}
 283
 284static u8 *
 285drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 286{
 287	int i, j = 0, valid_extensions = 0;
 288	u8 *block, *new;
 
 
 
 
 
 
 
 
 
 
 289
 290	if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
 291		return NULL;
 292
 293	/* base block fetch */
 294	for (i = 0; i < 4; i++) {
 295		if (drm_do_probe_ddc_edid(adapter, block, 0, EDID_LENGTH))
 296			goto out;
 297		if (drm_edid_block_valid(block))
 
 298			break;
 299		if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) {
 300			connector->null_edid_counter++;
 301			goto carp;
 302		}
 303	}
 304	if (i == 4)
 305		goto carp;
 306
 307	/* if there's no extensions, we're done */
 308	if (block[0x7e] == 0)
 309		return block;
 
 310
 311	new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
 312	if (!new)
 313		goto out;
 314	block = new;
 
 
 
 315
 316	for (j = 1; j <= block[0x7e]; j++) {
 317		for (i = 0; i < 4; i++) {
 318			if (drm_do_probe_ddc_edid(adapter,
 319				  block + (valid_extensions + 1) * EDID_LENGTH,
 320				  j, EDID_LENGTH))
 321				goto out;
 322			if (drm_edid_block_valid(block + (valid_extensions + 1) * EDID_LENGTH)) {
 323				valid_extensions++;
 324				break;
 325			}
 326		}
 
 327		if (i == 4)
 328			dev_warn(connector->dev->dev,
 329			 "%s: Ignoring invalid EDID block %d.\n",
 330			 drm_get_connector_name(connector), j);
 331	}
 332
 333	if (valid_extensions != block[0x7e]) {
 334		block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
 335		block[0x7e] = valid_extensions;
 336		new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
 
 
 
 
 
 337		if (!new)
 338			goto out;
 339		block = new;
 
 
 
 
 
 
 
 
 
 
 
 
 
 340	}
 341
 342	return block;
 343
 344carp:
 345	dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n",
 346		 drm_get_connector_name(connector), j);
 347
 348out:
 349	kfree(block);
 350	return NULL;
 351}
 
 352
 353/**
 354 * Probe DDC presence.
 
 355 *
 356 * \param adapter : i2c device adaptor
 357 * \return 1 on success
 358 */
 359static bool
 360drm_probe_ddc(struct i2c_adapter *adapter)
 361{
 362	unsigned char out;
 363
 364	return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
 365}
 
 366
 367/**
 368 * drm_get_edid - get EDID data, if available
 369 * @connector: connector we're probing
 370 * @adapter: i2c adapter to use for DDC
 371 *
 372 * Poke the given i2c channel to grab EDID data if possible.  If found,
 373 * attach it to the connector.
 374 *
 375 * Return edid data or NULL if we couldn't find any.
 376 */
 377struct edid *drm_get_edid(struct drm_connector *connector,
 378			  struct i2c_adapter *adapter)
 379{
 380	struct edid *edid = NULL;
 381
 382	if (drm_probe_ddc(adapter))
 383		edid = (struct edid *)drm_do_get_edid(connector, adapter);
 384
 385	connector->display_info.raw_edid = (char *)edid;
 
 386
 
 
 
 387	return edid;
 388
 389}
 390EXPORT_SYMBOL(drm_get_edid);
 391
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 392/*** EDID parsing ***/
 393
 394/**
 395 * edid_vendor - match a string against EDID's obfuscated vendor field
 396 * @edid: EDID to match
 397 * @vendor: vendor string
 398 *
 399 * Returns true if @vendor is in @edid, false otherwise
 400 */
 401static bool edid_vendor(struct edid *edid, char *vendor)
 402{
 403	char edid_vendor[3];
 404
 405	edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
 406	edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
 407			  ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
 408	edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
 409
 410	return !strncmp(edid_vendor, vendor, 3);
 411}
 412
 413/**
 414 * edid_get_quirks - return quirk flags for a given EDID
 415 * @edid: EDID to process
 416 *
 417 * This tells subsequent routines what fixes they need to apply.
 418 */
 419static u32 edid_get_quirks(struct edid *edid)
 420{
 421	struct edid_quirk *quirk;
 422	int i;
 423
 424	for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
 425		quirk = &edid_quirk_list[i];
 426
 427		if (edid_vendor(edid, quirk->vendor) &&
 428		    (EDID_PRODUCT_ID(edid) == quirk->product_id))
 429			return quirk->quirks;
 430	}
 431
 432	return 0;
 433}
 434
 435#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
 436#define MODE_REFRESH_DIFF(m,r) (abs((m)->vrefresh - target_refresh))
 437
 438/**
 439 * edid_fixup_preferred - set preferred modes based on quirk list
 440 * @connector: has mode list to fix up
 441 * @quirks: quirks list
 442 *
 443 * Walk the mode list for @connector, clearing the preferred status
 444 * on existing modes and setting it anew for the right mode ala @quirks.
 445 */
 446static void edid_fixup_preferred(struct drm_connector *connector,
 447				 u32 quirks)
 448{
 449	struct drm_display_mode *t, *cur_mode, *preferred_mode;
 450	int target_refresh = 0;
 
 451
 452	if (list_empty(&connector->probed_modes))
 453		return;
 454
 455	if (quirks & EDID_QUIRK_PREFER_LARGE_60)
 456		target_refresh = 60;
 457	if (quirks & EDID_QUIRK_PREFER_LARGE_75)
 458		target_refresh = 75;
 459
 460	preferred_mode = list_first_entry(&connector->probed_modes,
 461					  struct drm_display_mode, head);
 462
 463	list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
 464		cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
 465
 466		if (cur_mode == preferred_mode)
 467			continue;
 468
 469		/* Largest mode is preferred */
 470		if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
 471			preferred_mode = cur_mode;
 472
 
 
 
 
 473		/* At a given size, try to get closest to target refresh */
 474		if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
 475		    MODE_REFRESH_DIFF(cur_mode, target_refresh) <
 476		    MODE_REFRESH_DIFF(preferred_mode, target_refresh)) {
 477			preferred_mode = cur_mode;
 478		}
 479	}
 480
 481	preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
 482}
 483
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 484struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
 485					   int hsize, int vsize, int fresh)
 
 486{
 487	struct drm_display_mode *mode = NULL;
 488	int i;
 489
 490	for (i = 0; i < drm_num_dmt_modes; i++) {
 491		const struct drm_display_mode *ptr = &drm_dmt_modes[i];
 492		if (hsize == ptr->hdisplay &&
 493			vsize == ptr->vdisplay &&
 494			fresh == drm_mode_vrefresh(ptr)) {
 495			/* get the expected default mode */
 496			mode = drm_mode_duplicate(dev, ptr);
 497			break;
 498		}
 
 
 
 499	}
 500	return mode;
 
 501}
 502EXPORT_SYMBOL(drm_mode_find_dmt);
 503
 504typedef void detailed_cb(struct detailed_timing *timing, void *closure);
 505
 506static void
 507cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
 508{
 509	int i, n = 0;
 510	u8 rev = ext[0x01], d = ext[0x02];
 511	u8 *det_base = ext + d;
 512
 513	switch (rev) {
 514	case 0:
 515		/* can't happen */
 516		return;
 517	case 1:
 518		/* have to infer how many blocks we have, check pixel clock */
 519		for (i = 0; i < 6; i++)
 520			if (det_base[18*i] || det_base[18*i+1])
 521				n++;
 522		break;
 523	default:
 524		/* explicit count */
 525		n = min(ext[0x03] & 0x0f, 6);
 526		break;
 527	}
 528
 529	for (i = 0; i < n; i++)
 530		cb((struct detailed_timing *)(det_base + 18 * i), closure);
 531}
 532
 533static void
 534vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
 535{
 536	unsigned int i, n = min((int)ext[0x02], 6);
 537	u8 *det_base = ext + 5;
 538
 539	if (ext[0x01] != 1)
 540		return; /* unknown version */
 541
 542	for (i = 0; i < n; i++)
 543		cb((struct detailed_timing *)(det_base + 18 * i), closure);
 544}
 545
 546static void
 547drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
 548{
 549	int i;
 550	struct edid *edid = (struct edid *)raw_edid;
 551
 552	if (edid == NULL)
 553		return;
 554
 555	for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
 556		cb(&(edid->detailed_timings[i]), closure);
 557
 558	for (i = 1; i <= raw_edid[0x7e]; i++) {
 559		u8 *ext = raw_edid + (i * EDID_LENGTH);
 560		switch (*ext) {
 561		case CEA_EXT:
 562			cea_for_each_detailed_block(ext, cb, closure);
 563			break;
 564		case VTB_EXT:
 565			vtb_for_each_detailed_block(ext, cb, closure);
 566			break;
 567		default:
 568			break;
 569		}
 570	}
 571}
 572
 573static void
 574is_rb(struct detailed_timing *t, void *data)
 575{
 576	u8 *r = (u8 *)t;
 577	if (r[3] == EDID_DETAIL_MONITOR_RANGE)
 578		if (r[15] & 0x10)
 579			*(bool *)data = true;
 580}
 581
 582/* EDID 1.4 defines this explicitly.  For EDID 1.3, we guess, badly. */
 583static bool
 584drm_monitor_supports_rb(struct edid *edid)
 585{
 586	if (edid->revision >= 4) {
 587		bool ret;
 588		drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
 589		return ret;
 590	}
 591
 592	return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
 593}
 594
 595static void
 596find_gtf2(struct detailed_timing *t, void *data)
 597{
 598	u8 *r = (u8 *)t;
 599	if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
 600		*(u8 **)data = r;
 601}
 602
 603/* Secondary GTF curve kicks in above some break frequency */
 604static int
 605drm_gtf2_hbreak(struct edid *edid)
 606{
 607	u8 *r = NULL;
 608	drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
 609	return r ? (r[12] * 2) : 0;
 610}
 611
 612static int
 613drm_gtf2_2c(struct edid *edid)
 614{
 615	u8 *r = NULL;
 616	drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
 617	return r ? r[13] : 0;
 618}
 619
 620static int
 621drm_gtf2_m(struct edid *edid)
 622{
 623	u8 *r = NULL;
 624	drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
 625	return r ? (r[15] << 8) + r[14] : 0;
 626}
 627
 628static int
 629drm_gtf2_k(struct edid *edid)
 630{
 631	u8 *r = NULL;
 632	drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
 633	return r ? r[16] : 0;
 634}
 635
 636static int
 637drm_gtf2_2j(struct edid *edid)
 638{
 639	u8 *r = NULL;
 640	drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
 641	return r ? r[17] : 0;
 642}
 643
 644/**
 645 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
 646 * @edid: EDID block to scan
 647 */
 648static int standard_timing_level(struct edid *edid)
 649{
 650	if (edid->revision >= 2) {
 651		if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
 652			return LEVEL_CVT;
 653		if (drm_gtf2_hbreak(edid))
 654			return LEVEL_GTF2;
 655		return LEVEL_GTF;
 656	}
 657	return LEVEL_DMT;
 658}
 659
 660/*
 661 * 0 is reserved.  The spec says 0x01 fill for unused timings.  Some old
 662 * monitors fill with ascii space (0x20) instead.
 663 */
 664static int
 665bad_std_timing(u8 a, u8 b)
 666{
 667	return (a == 0x00 && b == 0x00) ||
 668	       (a == 0x01 && b == 0x01) ||
 669	       (a == 0x20 && b == 0x20);
 670}
 671
 672/**
 673 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
 
 
 674 * @t: standard timing params
 675 * @timing_level: standard timing level
 676 *
 677 * Take the standard timing params (in this case width, aspect, and refresh)
 678 * and convert them into a real mode using CVT/GTF/DMT.
 679 */
 680static struct drm_display_mode *
 681drm_mode_std(struct drm_connector *connector, struct edid *edid,
 682	     struct std_timing *t, int revision)
 683{
 684	struct drm_device *dev = connector->dev;
 685	struct drm_display_mode *m, *mode = NULL;
 686	int hsize, vsize;
 687	int vrefresh_rate;
 688	unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
 689		>> EDID_TIMING_ASPECT_SHIFT;
 690	unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
 691		>> EDID_TIMING_VFREQ_SHIFT;
 692	int timing_level = standard_timing_level(edid);
 693
 694	if (bad_std_timing(t->hsize, t->vfreq_aspect))
 695		return NULL;
 696
 697	/* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
 698	hsize = t->hsize * 8 + 248;
 699	/* vrefresh_rate = vfreq + 60 */
 700	vrefresh_rate = vfreq + 60;
 701	/* the vdisplay is calculated based on the aspect ratio */
 702	if (aspect_ratio == 0) {
 703		if (revision < 3)
 704			vsize = hsize;
 705		else
 706			vsize = (hsize * 10) / 16;
 707	} else if (aspect_ratio == 1)
 708		vsize = (hsize * 3) / 4;
 709	else if (aspect_ratio == 2)
 710		vsize = (hsize * 4) / 5;
 711	else
 712		vsize = (hsize * 9) / 16;
 713
 714	/* HDTV hack, part 1 */
 715	if (vrefresh_rate == 60 &&
 716	    ((hsize == 1360 && vsize == 765) ||
 717	     (hsize == 1368 && vsize == 769))) {
 718		hsize = 1366;
 719		vsize = 768;
 720	}
 721
 722	/*
 723	 * If this connector already has a mode for this size and refresh
 724	 * rate (because it came from detailed or CVT info), use that
 725	 * instead.  This way we don't have to guess at interlace or
 726	 * reduced blanking.
 727	 */
 728	list_for_each_entry(m, &connector->probed_modes, head)
 729		if (m->hdisplay == hsize && m->vdisplay == vsize &&
 730		    drm_mode_vrefresh(m) == vrefresh_rate)
 731			return NULL;
 732
 733	/* HDTV hack, part 2 */
 734	if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
 735		mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
 736				    false);
 
 
 737		mode->hdisplay = 1366;
 738		mode->hsync_start = mode->hsync_start - 1;
 739		mode->hsync_end = mode->hsync_end - 1;
 740		return mode;
 741	}
 742
 743	/* check whether it can be found in default mode table */
 744	mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate);
 
 
 
 
 
 
 745	if (mode)
 746		return mode;
 747
 
 748	switch (timing_level) {
 749	case LEVEL_DMT:
 750		break;
 751	case LEVEL_GTF:
 752		mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
 753		break;
 754	case LEVEL_GTF2:
 755		/*
 756		 * This is potentially wrong if there's ever a monitor with
 757		 * more than one ranges section, each claiming a different
 758		 * secondary GTF curve.  Please don't do that.
 759		 */
 760		mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
 
 
 761		if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
 762			kfree(mode);
 763			mode = drm_gtf_mode_complex(dev, hsize, vsize,
 764						    vrefresh_rate, 0, 0,
 765						    drm_gtf2_m(edid),
 766						    drm_gtf2_2c(edid),
 767						    drm_gtf2_k(edid),
 768						    drm_gtf2_2j(edid));
 769		}
 770		break;
 771	case LEVEL_CVT:
 772		mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
 773				    false);
 774		break;
 775	}
 776	return mode;
 777}
 778
 779/*
 780 * EDID is delightfully ambiguous about how interlaced modes are to be
 781 * encoded.  Our internal representation is of frame height, but some
 782 * HDTV detailed timings are encoded as field height.
 783 *
 784 * The format list here is from CEA, in frame size.  Technically we
 785 * should be checking refresh rate too.  Whatever.
 786 */
 787static void
 788drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
 789			    struct detailed_pixel_timing *pt)
 790{
 791	int i;
 792	static const struct {
 793		int w, h;
 794	} cea_interlaced[] = {
 795		{ 1920, 1080 },
 796		{  720,  480 },
 797		{ 1440,  480 },
 798		{ 2880,  480 },
 799		{  720,  576 },
 800		{ 1440,  576 },
 801		{ 2880,  576 },
 802	};
 803
 804	if (!(pt->misc & DRM_EDID_PT_INTERLACED))
 805		return;
 806
 807	for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
 808		if ((mode->hdisplay == cea_interlaced[i].w) &&
 809		    (mode->vdisplay == cea_interlaced[i].h / 2)) {
 810			mode->vdisplay *= 2;
 811			mode->vsync_start *= 2;
 812			mode->vsync_end *= 2;
 813			mode->vtotal *= 2;
 814			mode->vtotal |= 1;
 815		}
 816	}
 817
 818	mode->flags |= DRM_MODE_FLAG_INTERLACE;
 819}
 820
 821/**
 822 * drm_mode_detailed - create a new mode from an EDID detailed timing section
 823 * @dev: DRM device (needed to create new mode)
 824 * @edid: EDID block
 825 * @timing: EDID detailed timing info
 826 * @quirks: quirks to apply
 827 *
 828 * An EDID detailed timing block contains enough info for us to create and
 829 * return a new struct drm_display_mode.
 830 */
 831static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
 832						  struct edid *edid,
 833						  struct detailed_timing *timing,
 834						  u32 quirks)
 835{
 836	struct drm_display_mode *mode;
 837	struct detailed_pixel_timing *pt = &timing->data.pixel_data;
 838	unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
 839	unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
 840	unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
 841	unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
 842	unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
 843	unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
 844	unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) >> 2 | pt->vsync_offset_pulse_width_lo >> 4;
 845	unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
 846
 847	/* ignore tiny modes */
 848	if (hactive < 64 || vactive < 64)
 849		return NULL;
 850
 851	if (pt->misc & DRM_EDID_PT_STEREO) {
 852		printk(KERN_WARNING "stereo mode not supported\n");
 853		return NULL;
 854	}
 855	if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
 856		printk(KERN_WARNING "composite sync not supported\n");
 857	}
 858
 859	/* it is incorrect if hsync/vsync width is zero */
 860	if (!hsync_pulse_width || !vsync_pulse_width) {
 861		DRM_DEBUG_KMS("Incorrect Detailed timing. "
 862				"Wrong Hsync/Vsync pulse width\n");
 863		return NULL;
 864	}
 
 
 
 
 
 
 
 
 
 865	mode = drm_mode_create(dev);
 866	if (!mode)
 867		return NULL;
 868
 869	mode->type = DRM_MODE_TYPE_DRIVER;
 870
 871	if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
 872		timing->pixel_clock = cpu_to_le16(1088);
 873
 874	mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
 875
 876	mode->hdisplay = hactive;
 877	mode->hsync_start = mode->hdisplay + hsync_offset;
 878	mode->hsync_end = mode->hsync_start + hsync_pulse_width;
 879	mode->htotal = mode->hdisplay + hblank;
 880
 881	mode->vdisplay = vactive;
 882	mode->vsync_start = mode->vdisplay + vsync_offset;
 883	mode->vsync_end = mode->vsync_start + vsync_pulse_width;
 884	mode->vtotal = mode->vdisplay + vblank;
 885
 886	/* Some EDIDs have bogus h/vtotal values */
 887	if (mode->hsync_end > mode->htotal)
 888		mode->htotal = mode->hsync_end + 1;
 889	if (mode->vsync_end > mode->vtotal)
 890		mode->vtotal = mode->vsync_end + 1;
 891
 892	drm_mode_do_interlace_quirk(mode, pt);
 893
 894	drm_mode_set_name(mode);
 895
 896	if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
 897		pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
 898	}
 899
 900	mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
 901		DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
 902	mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
 903		DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
 904
 
 905	mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
 906	mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
 907
 908	if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
 909		mode->width_mm *= 10;
 910		mode->height_mm *= 10;
 911	}
 912
 913	if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
 914		mode->width_mm = edid->width_cm * 10;
 915		mode->height_mm = edid->height_cm * 10;
 916	}
 917
 918	return mode;
 919}
 
 920
 921static bool
 922mode_is_rb(const struct drm_display_mode *mode)
 923{
 924	return (mode->htotal - mode->hdisplay == 160) &&
 925	       (mode->hsync_end - mode->hdisplay == 80) &&
 926	       (mode->hsync_end - mode->hsync_start == 32) &&
 927	       (mode->vsync_start - mode->vdisplay == 3);
 928}
 929
 930static bool
 931mode_in_hsync_range(const struct drm_display_mode *mode,
 932		    struct edid *edid, u8 *t)
 933{
 934	int hsync, hmin, hmax;
 935
 936	hmin = t[7];
 937	if (edid->revision >= 4)
 938	    hmin += ((t[4] & 0x04) ? 255 : 0);
 939	hmax = t[8];
 940	if (edid->revision >= 4)
 941	    hmax += ((t[4] & 0x08) ? 255 : 0);
 942	hsync = drm_mode_hsync(mode);
 943
 944	return (hsync <= hmax && hsync >= hmin);
 945}
 946
 947static bool
 948mode_in_vsync_range(const struct drm_display_mode *mode,
 949		    struct edid *edid, u8 *t)
 950{
 951	int vsync, vmin, vmax;
 952
 953	vmin = t[5];
 954	if (edid->revision >= 4)
 955	    vmin += ((t[4] & 0x01) ? 255 : 0);
 956	vmax = t[6];
 957	if (edid->revision >= 4)
 958	    vmax += ((t[4] & 0x02) ? 255 : 0);
 959	vsync = drm_mode_vrefresh(mode);
 960
 961	return (vsync <= vmax && vsync >= vmin);
 962}
 963
 964static u32
 965range_pixel_clock(struct edid *edid, u8 *t)
 966{
 967	/* unspecified */
 968	if (t[9] == 0 || t[9] == 255)
 969		return 0;
 970
 971	/* 1.4 with CVT support gives us real precision, yay */
 972	if (edid->revision >= 4 && t[10] == 0x04)
 973		return (t[9] * 10000) - ((t[12] >> 2) * 250);
 974
 975	/* 1.3 is pathetic, so fuzz up a bit */
 976	return t[9] * 10000 + 5001;
 977}
 978
 979static bool
 980mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
 981	      struct detailed_timing *timing)
 982{
 983	u32 max_clock;
 984	u8 *t = (u8 *)timing;
 985
 986	if (!mode_in_hsync_range(mode, edid, t))
 987		return false;
 988
 989	if (!mode_in_vsync_range(mode, edid, t))
 990		return false;
 991
 992	if ((max_clock = range_pixel_clock(edid, t)))
 993		if (mode->clock > max_clock)
 994			return false;
 995
 996	/* 1.4 max horizontal check */
 997	if (edid->revision >= 4 && t[10] == 0x04)
 998		if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
 999			return false;
1000
1001	if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
1002		return false;
1003
1004	return true;
1005}
1006
1007/*
1008 * XXX If drm_dmt_modes ever regrows the CVT-R modes (and it will) this will
1009 * need to account for them.
1010 */
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1011static int
1012drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
1013			struct detailed_timing *timing)
1014{
1015	int i, modes = 0;
1016	struct drm_display_mode *newmode;
1017	struct drm_device *dev = connector->dev;
1018
1019	for (i = 0; i < drm_num_dmt_modes; i++) {
1020		if (mode_in_range(drm_dmt_modes + i, edid, timing)) {
 
1021			newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
1022			if (newmode) {
1023				drm_mode_probed_add(connector, newmode);
1024				modes++;
1025			}
1026		}
1027	}
1028
1029	return modes;
1030}
1031
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1032static void
1033do_inferred_modes(struct detailed_timing *timing, void *c)
1034{
1035	struct detailed_mode_closure *closure = c;
1036	struct detailed_non_pixel *data = &timing->data.other_data;
1037	int gtf = (closure->edid->features & DRM_EDID_FEATURE_DEFAULT_GTF);
1038
1039	if (gtf && data->type == EDID_DETAIL_MONITOR_RANGE)
 
 
 
 
 
 
 
 
 
 
 
 
1040		closure->modes += drm_gtf_modes_for_range(closure->connector,
1041							  closure->edid,
1042							  timing);
 
 
 
 
 
 
 
 
 
 
 
 
 
1043}
1044
1045static int
1046add_inferred_modes(struct drm_connector *connector, struct edid *edid)
1047{
1048	struct detailed_mode_closure closure = {
1049		connector, edid, 0, 0, 0
 
1050	};
1051
1052	if (version_greater(edid, 1, 0))
1053		drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
1054					    &closure);
1055
1056	return closure.modes;
1057}
1058
1059static int
1060drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
1061{
1062	int i, j, m, modes = 0;
1063	struct drm_display_mode *mode;
1064	u8 *est = ((u8 *)timing) + 5;
1065
1066	for (i = 0; i < 6; i++) {
1067		for (j = 7; j > 0; j--) {
1068			m = (i * 8) + (7 - j);
1069			if (m >= ARRAY_SIZE(est3_modes))
1070				break;
1071			if (est[i] & (1 << j)) {
1072				mode = drm_mode_find_dmt(connector->dev,
1073							 est3_modes[m].w,
1074							 est3_modes[m].h,
1075							 est3_modes[m].r
1076							 /*, est3_modes[m].rb */);
1077				if (mode) {
1078					drm_mode_probed_add(connector, mode);
1079					modes++;
1080				}
1081			}
1082		}
1083	}
1084
1085	return modes;
1086}
1087
1088static void
1089do_established_modes(struct detailed_timing *timing, void *c)
1090{
1091	struct detailed_mode_closure *closure = c;
1092	struct detailed_non_pixel *data = &timing->data.other_data;
1093
1094	if (data->type == EDID_DETAIL_EST_TIMINGS)
1095		closure->modes += drm_est3_modes(closure->connector, timing);
1096}
1097
1098/**
1099 * add_established_modes - get est. modes from EDID and add them
 
1100 * @edid: EDID block to scan
1101 *
1102 * Each EDID block contains a bitmap of the supported "established modes" list
1103 * (defined above).  Tease them out and add them to the global modes list.
1104 */
1105static int
1106add_established_modes(struct drm_connector *connector, struct edid *edid)
1107{
1108	struct drm_device *dev = connector->dev;
1109	unsigned long est_bits = edid->established_timings.t1 |
1110		(edid->established_timings.t2 << 8) |
1111		((edid->established_timings.mfg_rsvd & 0x80) << 9);
1112	int i, modes = 0;
1113	struct detailed_mode_closure closure = {
1114		connector, edid, 0, 0, 0
 
1115	};
1116
1117	for (i = 0; i <= EDID_EST_TIMINGS; i++) {
1118		if (est_bits & (1<<i)) {
1119			struct drm_display_mode *newmode;
1120			newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
1121			if (newmode) {
1122				drm_mode_probed_add(connector, newmode);
1123				modes++;
1124			}
1125		}
1126	}
1127
1128	if (version_greater(edid, 1, 0))
1129		    drm_for_each_detailed_block((u8 *)edid,
1130						do_established_modes, &closure);
1131
1132	return modes + closure.modes;
1133}
1134
1135static void
1136do_standard_modes(struct detailed_timing *timing, void *c)
1137{
1138	struct detailed_mode_closure *closure = c;
1139	struct detailed_non_pixel *data = &timing->data.other_data;
1140	struct drm_connector *connector = closure->connector;
1141	struct edid *edid = closure->edid;
1142
1143	if (data->type == EDID_DETAIL_STD_MODES) {
1144		int i;
1145		for (i = 0; i < 6; i++) {
1146			struct std_timing *std;
1147			struct drm_display_mode *newmode;
1148
1149			std = &data->data.timings[i];
1150			newmode = drm_mode_std(connector, edid, std,
1151					       edid->revision);
1152			if (newmode) {
1153				drm_mode_probed_add(connector, newmode);
1154				closure->modes++;
1155			}
1156		}
1157	}
1158}
1159
1160/**
1161 * add_standard_modes - get std. modes from EDID and add them
 
1162 * @edid: EDID block to scan
1163 *
1164 * Standard modes can be calculated using the appropriate standard (DMT,
1165 * GTF or CVT. Grab them from @edid and add them to the list.
1166 */
1167static int
1168add_standard_modes(struct drm_connector *connector, struct edid *edid)
1169{
1170	int i, modes = 0;
1171	struct detailed_mode_closure closure = {
1172		connector, edid, 0, 0, 0
 
1173	};
1174
1175	for (i = 0; i < EDID_STD_TIMINGS; i++) {
1176		struct drm_display_mode *newmode;
1177
1178		newmode = drm_mode_std(connector, edid,
1179				       &edid->standard_timings[i],
1180				       edid->revision);
1181		if (newmode) {
1182			drm_mode_probed_add(connector, newmode);
1183			modes++;
1184		}
1185	}
1186
1187	if (version_greater(edid, 1, 0))
1188		drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
1189					    &closure);
1190
1191	/* XXX should also look for standard codes in VTB blocks */
1192
1193	return modes + closure.modes;
1194}
1195
1196static int drm_cvt_modes(struct drm_connector *connector,
1197			 struct detailed_timing *timing)
1198{
1199	int i, j, modes = 0;
1200	struct drm_display_mode *newmode;
1201	struct drm_device *dev = connector->dev;
1202	struct cvt_timing *cvt;
1203	const int rates[] = { 60, 85, 75, 60, 50 };
1204	const u8 empty[3] = { 0, 0, 0 };
1205
1206	for (i = 0; i < 4; i++) {
1207		int uninitialized_var(width), height;
1208		cvt = &(timing->data.other_data.data.cvt[i]);
1209
1210		if (!memcmp(cvt->code, empty, 3))
1211			continue;
1212
1213		height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
1214		switch (cvt->code[1] & 0x0c) {
1215		case 0x00:
1216			width = height * 4 / 3;
1217			break;
1218		case 0x04:
1219			width = height * 16 / 9;
1220			break;
1221		case 0x08:
1222			width = height * 16 / 10;
1223			break;
1224		case 0x0c:
1225			width = height * 15 / 9;
1226			break;
1227		}
1228
1229		for (j = 1; j < 5; j++) {
1230			if (cvt->code[2] & (1 << j)) {
1231				newmode = drm_cvt_mode(dev, width, height,
1232						       rates[j], j == 0,
1233						       false, false);
1234				if (newmode) {
1235					drm_mode_probed_add(connector, newmode);
1236					modes++;
1237				}
1238			}
1239		}
1240	}
1241
1242	return modes;
1243}
1244
1245static void
1246do_cvt_mode(struct detailed_timing *timing, void *c)
1247{
1248	struct detailed_mode_closure *closure = c;
1249	struct detailed_non_pixel *data = &timing->data.other_data;
1250
1251	if (data->type == EDID_DETAIL_CVT_3BYTE)
1252		closure->modes += drm_cvt_modes(closure->connector, timing);
1253}
1254
1255static int
1256add_cvt_modes(struct drm_connector *connector, struct edid *edid)
1257{	
1258	struct detailed_mode_closure closure = {
1259		connector, edid, 0, 0, 0
 
1260	};
1261
1262	if (version_greater(edid, 1, 2))
1263		drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
1264
1265	/* XXX should also look for CVT codes in VTB blocks */
1266
1267	return closure.modes;
1268}
1269
 
 
1270static void
1271do_detailed_mode(struct detailed_timing *timing, void *c)
1272{
1273	struct detailed_mode_closure *closure = c;
1274	struct drm_display_mode *newmode;
1275
1276	if (timing->pixel_clock) {
1277		newmode = drm_mode_detailed(closure->connector->dev,
1278					    closure->edid, timing,
1279					    closure->quirks);
1280		if (!newmode)
1281			return;
1282
1283		if (closure->preferred)
1284			newmode->type |= DRM_MODE_TYPE_PREFERRED;
1285
 
 
 
 
 
 
 
1286		drm_mode_probed_add(closure->connector, newmode);
1287		closure->modes++;
1288		closure->preferred = 0;
1289	}
1290}
1291
1292/*
1293 * add_detailed_modes - Add modes from detailed timings
1294 * @connector: attached connector
1295 * @edid: EDID block to scan
1296 * @quirks: quirks to apply
1297 */
1298static int
1299add_detailed_modes(struct drm_connector *connector, struct edid *edid,
1300		   u32 quirks)
1301{
1302	struct detailed_mode_closure closure = {
1303		connector,
1304		edid,
1305		1,
1306		quirks,
1307		0
1308	};
1309
1310	if (closure.preferred && !version_greater(edid, 1, 3))
1311		closure.preferred =
1312		    (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
1313
1314	drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
1315
1316	return closure.modes;
1317}
1318
1319#define HDMI_IDENTIFIER 0x000C03
1320#define AUDIO_BLOCK	0x01
 
1321#define VENDOR_BLOCK    0x03
 
 
 
 
 
1322#define EDID_BASIC_AUDIO	(1 << 6)
 
 
 
1323
1324/**
1325 * Search EDID for CEA extension block.
1326 */
1327u8 *drm_find_cea_extension(struct edid *edid)
1328{
1329	u8 *edid_ext = NULL;
1330	int i;
1331
1332	/* No EDID or EDID extensions */
1333	if (edid == NULL || edid->extensions == 0)
1334		return NULL;
1335
1336	/* Find CEA extension */
1337	for (i = 0; i < edid->extensions; i++) {
1338		edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
1339		if (edid_ext[0] == CEA_EXT)
1340			break;
1341	}
1342
1343	if (i == edid->extensions)
1344		return NULL;
1345
1346	return edid_ext;
1347}
1348EXPORT_SYMBOL(drm_find_cea_extension);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1349
1350/**
1351 * drm_detect_hdmi_monitor - detect whether monitor is hdmi.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1352 * @edid: monitor EDID information
1353 *
1354 * Parse the CEA extension according to CEA-861-B.
1355 * Return true if HDMI, false if not or unknown.
 
1356 */
1357bool drm_detect_hdmi_monitor(struct edid *edid)
1358{
1359	u8 *edid_ext;
1360	int i, hdmi_id;
1361	int start_offset, end_offset;
1362	bool is_hdmi = false;
1363
1364	edid_ext = drm_find_cea_extension(edid);
1365	if (!edid_ext)
1366		goto end;
1367
1368	/* Data block offset in CEA extension block */
1369	start_offset = 4;
1370	end_offset = edid_ext[2];
1371
1372	/*
1373	 * Because HDMI identifier is in Vendor Specific Block,
1374	 * search it from all data blocks of CEA extension.
1375	 */
1376	for (i = start_offset; i < end_offset;
1377		/* Increased by data block len */
1378		i += ((edid_ext[i] & 0x1f) + 1)) {
1379		/* Find vendor specific block */
1380		if ((edid_ext[i] >> 5) == VENDOR_BLOCK) {
1381			hdmi_id = edid_ext[i + 1] | (edid_ext[i + 2] << 8) |
1382				  edid_ext[i + 3] << 16;
1383			/* Find HDMI identifier */
1384			if (hdmi_id == HDMI_IDENTIFIER)
1385				is_hdmi = true;
1386			break;
1387		}
1388	}
1389
1390end:
1391	return is_hdmi;
1392}
1393EXPORT_SYMBOL(drm_detect_hdmi_monitor);
1394
1395/**
1396 * drm_detect_monitor_audio - check monitor audio capability
 
1397 *
1398 * Monitor should have CEA extension block.
1399 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
1400 * audio' only. If there is any audio extension block and supported
1401 * audio format, assume at least 'basic audio' support, even if 'basic
1402 * audio' is not defined in EDID.
1403 *
 
1404 */
1405bool drm_detect_monitor_audio(struct edid *edid)
1406{
1407	u8 *edid_ext;
1408	int i, j;
1409	bool has_audio = false;
1410	int start_offset, end_offset;
1411
1412	edid_ext = drm_find_cea_extension(edid);
1413	if (!edid_ext)
1414		goto end;
1415
1416	has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
1417
1418	if (has_audio) {
1419		DRM_DEBUG_KMS("Monitor has basic audio support\n");
1420		goto end;
1421	}
1422
1423	/* Data block offset in CEA extension block */
1424	start_offset = 4;
1425	end_offset = edid_ext[2];
1426
1427	for (i = start_offset; i < end_offset;
1428			i += ((edid_ext[i] & 0x1f) + 1)) {
1429		if ((edid_ext[i] >> 5) == AUDIO_BLOCK) {
1430			has_audio = true;
1431			for (j = 1; j < (edid_ext[i] & 0x1f); j += 3)
1432				DRM_DEBUG_KMS("CEA audio format %d\n",
1433					      (edid_ext[i + j] >> 3) & 0xf);
1434			goto end;
1435		}
1436	}
1437end:
1438	return has_audio;
1439}
1440EXPORT_SYMBOL(drm_detect_monitor_audio);
1441
1442/**
1443 * drm_add_display_info - pull display info out if present
1444 * @edid: EDID data
1445 * @info: display info (attached to connector)
 
 
 
1446 *
1447 * Grab any available display info and stuff it into the drm_display_info
1448 * structure that's part of the connector.  Useful for tracking bpp and
1449 * color spaces.
1450 */
1451static void drm_add_display_info(struct edid *edid,
1452				 struct drm_display_info *info)
1453{
1454	u8 *edid_ext;
 
1455
1456	info->width_mm = edid->width_cm * 10;
1457	info->height_mm = edid->height_cm * 10;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1458
1459	/* driver figures it out in this case */
1460	info->bpc = 0;
1461	info->color_formats = 0;
 
 
 
 
 
1462
1463	/* Only defined for 1.4 with digital displays */
1464	if (edid->revision < 4)
1465		return;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1466
1467	if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
1468		return;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1469
1470	switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
1471	case DRM_EDID_DIGITAL_DEPTH_6:
1472		info->bpc = 6;
1473		break;
1474	case DRM_EDID_DIGITAL_DEPTH_8:
1475		info->bpc = 8;
1476		break;
1477	case DRM_EDID_DIGITAL_DEPTH_10:
1478		info->bpc = 10;
1479		break;
1480	case DRM_EDID_DIGITAL_DEPTH_12:
1481		info->bpc = 12;
1482		break;
1483	case DRM_EDID_DIGITAL_DEPTH_14:
1484		info->bpc = 14;
1485		break;
1486	case DRM_EDID_DIGITAL_DEPTH_16:
1487		info->bpc = 16;
1488		break;
1489	case DRM_EDID_DIGITAL_DEPTH_UNDEF:
1490	default:
1491		info->bpc = 0;
1492		break;
1493	}
1494
1495	info->color_formats = DRM_COLOR_FORMAT_RGB444;
1496	if (info->color_formats & DRM_EDID_FEATURE_RGB_YCRCB444)
1497		info->color_formats = DRM_COLOR_FORMAT_YCRCB444;
1498	if (info->color_formats & DRM_EDID_FEATURE_RGB_YCRCB422)
1499		info->color_formats = DRM_COLOR_FORMAT_YCRCB422;
1500
1501	/* Get data from CEA blocks if present */
1502	edid_ext = drm_find_cea_extension(edid);
1503	if (!edid_ext)
1504		return;
 
 
 
 
1505
1506	info->cea_rev = edid_ext[1];
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1507}
1508
1509/**
1510 * drm_add_edid_modes - add modes from EDID data, if available
1511 * @connector: connector we're probing
1512 * @edid: edid data
1513 *
1514 * Add the specified modes to the connector's mode list.
 
 
1515 *
1516 * Return number of modes added or 0 if we couldn't find any.
1517 */
1518int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
1519{
1520	int num_modes = 0;
1521	u32 quirks;
1522
1523	if (edid == NULL) {
 
1524		return 0;
1525	}
1526	if (!drm_edid_is_valid(edid)) {
 
1527		dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
1528			 drm_get_connector_name(connector));
1529		return 0;
1530	}
1531
1532	quirks = edid_get_quirks(edid);
 
 
 
 
 
 
 
1533
1534	/*
1535	 * EDID spec says modes should be preferred in this order:
1536	 * - preferred detailed mode
1537	 * - other detailed modes from base block
1538	 * - detailed modes from extension blocks
1539	 * - CVT 3-byte code modes
1540	 * - standard timing codes
1541	 * - established timing codes
1542	 * - modes inferred from GTF or CVT range information
1543	 *
1544	 * We get this pretty much right.
1545	 *
1546	 * XXX order for additional mode types in extension blocks?
1547	 */
1548	num_modes += add_detailed_modes(connector, edid, quirks);
1549	num_modes += add_cvt_modes(connector, edid);
1550	num_modes += add_standard_modes(connector, edid);
1551	num_modes += add_established_modes(connector, edid);
1552	num_modes += add_inferred_modes(connector, edid);
 
 
 
 
1553
1554	if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
1555		edid_fixup_preferred(connector, quirks);
1556
1557	drm_add_display_info(edid, &connector->display_info);
 
 
 
 
 
 
 
 
 
 
1558
1559	return num_modes;
1560}
1561EXPORT_SYMBOL(drm_add_edid_modes);
1562
1563/**
1564 * drm_add_modes_noedid - add modes for the connectors without EDID
1565 * @connector: connector we're probing
1566 * @hdisplay: the horizontal display limit
1567 * @vdisplay: the vertical display limit
1568 *
1569 * Add the specified modes to the connector's mode list. Only when the
1570 * hdisplay/vdisplay is not beyond the given limit, it will be added.
1571 *
1572 * Return number of modes added or 0 if we couldn't find any.
1573 */
1574int drm_add_modes_noedid(struct drm_connector *connector,
1575			int hdisplay, int vdisplay)
1576{
1577	int i, count, num_modes = 0;
1578	struct drm_display_mode *mode;
1579	struct drm_device *dev = connector->dev;
1580
1581	count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
1582	if (hdisplay < 0)
1583		hdisplay = 0;
1584	if (vdisplay < 0)
1585		vdisplay = 0;
1586
1587	for (i = 0; i < count; i++) {
1588		const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1589		if (hdisplay && vdisplay) {
1590			/*
1591			 * Only when two are valid, they will be used to check
1592			 * whether the mode should be added to the mode list of
1593			 * the connector.
1594			 */
1595			if (ptr->hdisplay > hdisplay ||
1596					ptr->vdisplay > vdisplay)
1597				continue;
1598		}
1599		if (drm_mode_vrefresh(ptr) > 61)
1600			continue;
1601		mode = drm_mode_duplicate(dev, ptr);
1602		if (mode) {
1603			drm_mode_probed_add(connector, mode);
1604			num_modes++;
1605		}
1606	}
1607	return num_modes;
1608}
1609EXPORT_SYMBOL(drm_add_modes_noedid);
v4.17
   1/*
   2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
   3 * Copyright (c) 2007-2008 Intel Corporation
   4 *   Jesse Barnes <jesse.barnes@intel.com>
   5 * Copyright 2010 Red Hat, Inc.
   6 *
   7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
   8 * FB layer.
   9 *   Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
  10 *
  11 * Permission is hereby granted, free of charge, to any person obtaining a
  12 * copy of this software and associated documentation files (the "Software"),
  13 * to deal in the Software without restriction, including without limitation
  14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
  15 * and/or sell copies of the Software, and to permit persons to whom the
  16 * Software is furnished to do so, subject to the following conditions:
  17 *
  18 * The above copyright notice and this permission notice (including the
  19 * next paragraph) shall be included in all copies or substantial portions
  20 * of the Software.
  21 *
  22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  28 * DEALINGS IN THE SOFTWARE.
  29 */
  30#include <linux/kernel.h>
  31#include <linux/slab.h>
  32#include <linux/hdmi.h>
  33#include <linux/i2c.h>
  34#include <linux/module.h>
  35#include <linux/vga_switcheroo.h>
  36#include <drm/drmP.h>
  37#include <drm/drm_edid.h>
  38#include <drm/drm_encoder.h>
  39#include <drm/drm_displayid.h>
  40#include <drm/drm_scdc_helper.h>
  41
  42#include "drm_crtc_internal.h"
  43
  44#define version_greater(edid, maj, min) \
  45	(((edid)->version > (maj)) || \
  46	 ((edid)->version == (maj) && (edid)->revision > (min)))
  47
  48#define EDID_EST_TIMINGS 16
  49#define EDID_STD_TIMINGS 8
  50#define EDID_DETAILED_TIMINGS 4
  51
  52/*
  53 * EDID blocks out in the wild have a variety of bugs, try to collect
  54 * them here (note that userspace may work around broken monitors first,
  55 * but fixes should make their way here so that the kernel "just works"
  56 * on as many displays as possible).
  57 */
  58
  59/* First detailed mode wrong, use largest 60Hz mode */
  60#define EDID_QUIRK_PREFER_LARGE_60		(1 << 0)
  61/* Reported 135MHz pixel clock is too high, needs adjustment */
  62#define EDID_QUIRK_135_CLOCK_TOO_HIGH		(1 << 1)
  63/* Prefer the largest mode at 75 Hz */
  64#define EDID_QUIRK_PREFER_LARGE_75		(1 << 2)
  65/* Detail timing is in cm not mm */
  66#define EDID_QUIRK_DETAILED_IN_CM		(1 << 3)
  67/* Detailed timing descriptors have bogus size values, so just take the
  68 * maximum size and use that.
  69 */
  70#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE	(1 << 4)
  71/* Monitor forgot to set the first detailed is preferred bit. */
  72#define EDID_QUIRK_FIRST_DETAILED_PREFERRED	(1 << 5)
  73/* use +hsync +vsync for detailed mode */
  74#define EDID_QUIRK_DETAILED_SYNC_PP		(1 << 6)
  75/* Force reduced-blanking timings for detailed modes */
  76#define EDID_QUIRK_FORCE_REDUCED_BLANKING	(1 << 7)
  77/* Force 8bpc */
  78#define EDID_QUIRK_FORCE_8BPC			(1 << 8)
  79/* Force 12bpc */
  80#define EDID_QUIRK_FORCE_12BPC			(1 << 9)
  81/* Force 6bpc */
  82#define EDID_QUIRK_FORCE_6BPC			(1 << 10)
  83/* Force 10bpc */
  84#define EDID_QUIRK_FORCE_10BPC			(1 << 11)
  85/* Non desktop display (i.e. HMD) */
  86#define EDID_QUIRK_NON_DESKTOP			(1 << 12)
  87
  88struct detailed_mode_closure {
  89	struct drm_connector *connector;
  90	struct edid *edid;
  91	bool preferred;
  92	u32 quirks;
  93	int modes;
  94};
  95
  96#define LEVEL_DMT	0
  97#define LEVEL_GTF	1
  98#define LEVEL_GTF2	2
  99#define LEVEL_CVT	3
 100
 101static const struct edid_quirk {
 102	char vendor[4];
 103	int product_id;
 104	u32 quirks;
 105} edid_quirk_list[] = {
 106	/* Acer AL1706 */
 107	{ "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
 108	/* Acer F51 */
 109	{ "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
 110	/* Unknown Acer */
 111	{ "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
 112
 113	/* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
 114	{ "AEO", 0, EDID_QUIRK_FORCE_6BPC },
 115
 116	/* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
 117	{ "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
 118
 119	/* Belinea 10 15 55 */
 120	{ "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
 121	{ "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
 122
 123	/* Envision Peripherals, Inc. EN-7100e */
 124	{ "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
 125	/* Envision EN2028 */
 126	{ "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
 127
 128	/* Funai Electronics PM36B */
 129	{ "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
 130	  EDID_QUIRK_DETAILED_IN_CM },
 131
 132	/* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
 133	{ "LGD", 764, EDID_QUIRK_FORCE_10BPC },
 134
 135	/* LG Philips LCD LP154W01-A5 */
 136	{ "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
 137	{ "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
 138
 139	/* Philips 107p5 CRT */
 140	{ "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
 141
 142	/* Proview AY765C */
 143	{ "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
 144
 145	/* Samsung SyncMaster 205BW.  Note: irony */
 146	{ "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
 147	/* Samsung SyncMaster 22[5-6]BW */
 148	{ "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
 149	{ "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
 150
 151	/* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
 152	{ "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
 153
 154	/* ViewSonic VA2026w */
 155	{ "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
 156
 157	/* Medion MD 30217 PG */
 158	{ "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
 159
 160	/* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
 161	{ "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
 162
 163	/* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
 164	{ "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
 165
 166	/* HTC Vive VR Headset */
 167	{ "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
 168
 169	/* Oculus Rift DK1, DK2, and CV1 VR Headsets */
 170	{ "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
 171	{ "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
 172	{ "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
 173
 174	/* Windows Mixed Reality Headsets */
 175	{ "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
 176	{ "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
 177	{ "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
 178	{ "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
 179	{ "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
 180	{ "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
 181	{ "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
 182	{ "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
 183
 184	/* Sony PlayStation VR Headset */
 185	{ "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
 186};
 187
 188/*
 189 * Autogenerated from the DMT spec.
 190 * This table is copied from xfree86/modes/xf86EdidModes.c.
 191 */
 192static const struct drm_display_mode drm_dmt_modes[] = {
 193	/* 0x01 - 640x350@85Hz */
 194	{ DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
 195		   736, 832, 0, 350, 382, 385, 445, 0,
 196		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 197	/* 0x02 - 640x400@85Hz */
 198	{ DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
 199		   736, 832, 0, 400, 401, 404, 445, 0,
 200		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 201	/* 0x03 - 720x400@85Hz */
 202	{ DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
 203		   828, 936, 0, 400, 401, 404, 446, 0,
 204		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 205	/* 0x04 - 640x480@60Hz */
 206	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
 207		   752, 800, 0, 480, 490, 492, 525, 0,
 208		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 209	/* 0x05 - 640x480@72Hz */
 210	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
 211		   704, 832, 0, 480, 489, 492, 520, 0,
 212		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 213	/* 0x06 - 640x480@75Hz */
 214	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
 215		   720, 840, 0, 480, 481, 484, 500, 0,
 216		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 217	/* 0x07 - 640x480@85Hz */
 218	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
 219		   752, 832, 0, 480, 481, 484, 509, 0,
 220		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 221	/* 0x08 - 800x600@56Hz */
 222	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
 223		   896, 1024, 0, 600, 601, 603, 625, 0,
 224		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 225	/* 0x09 - 800x600@60Hz */
 226	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
 227		   968, 1056, 0, 600, 601, 605, 628, 0,
 228		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 229	/* 0x0a - 800x600@72Hz */
 230	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
 231		   976, 1040, 0, 600, 637, 643, 666, 0,
 232		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 233	/* 0x0b - 800x600@75Hz */
 234	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
 235		   896, 1056, 0, 600, 601, 604, 625, 0,
 236		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 237	/* 0x0c - 800x600@85Hz */
 238	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
 239		   896, 1048, 0, 600, 601, 604, 631, 0,
 240		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 241	/* 0x0d - 800x600@120Hz RB */
 242	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
 243		   880, 960, 0, 600, 603, 607, 636, 0,
 244		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 245	/* 0x0e - 848x480@60Hz */
 246	{ DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
 247		   976, 1088, 0, 480, 486, 494, 517, 0,
 248		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 249	/* 0x0f - 1024x768@43Hz, interlace */
 250	{ DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
 251		   1208, 1264, 0, 768, 768, 776, 817, 0,
 252		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
 253		   DRM_MODE_FLAG_INTERLACE) },
 254	/* 0x10 - 1024x768@60Hz */
 255	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
 256		   1184, 1344, 0, 768, 771, 777, 806, 0,
 257		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 258	/* 0x11 - 1024x768@70Hz */
 259	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
 260		   1184, 1328, 0, 768, 771, 777, 806, 0,
 261		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 262	/* 0x12 - 1024x768@75Hz */
 263	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
 264		   1136, 1312, 0, 768, 769, 772, 800, 0,
 265		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 266	/* 0x13 - 1024x768@85Hz */
 267	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
 268		   1168, 1376, 0, 768, 769, 772, 808, 0,
 269		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 270	/* 0x14 - 1024x768@120Hz RB */
 271	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
 272		   1104, 1184, 0, 768, 771, 775, 813, 0,
 273		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 274	/* 0x15 - 1152x864@75Hz */
 275	{ DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
 276		   1344, 1600, 0, 864, 865, 868, 900, 0,
 277		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 278	/* 0x55 - 1280x720@60Hz */
 279	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
 280		   1430, 1650, 0, 720, 725, 730, 750, 0,
 281		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 282	/* 0x16 - 1280x768@60Hz RB */
 283	{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
 284		   1360, 1440, 0, 768, 771, 778, 790, 0,
 285		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 286	/* 0x17 - 1280x768@60Hz */
 287	{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
 288		   1472, 1664, 0, 768, 771, 778, 798, 0,
 289		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 290	/* 0x18 - 1280x768@75Hz */
 291	{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
 292		   1488, 1696, 0, 768, 771, 778, 805, 0,
 293		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 294	/* 0x19 - 1280x768@85Hz */
 295	{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
 296		   1496, 1712, 0, 768, 771, 778, 809, 0,
 297		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 298	/* 0x1a - 1280x768@120Hz RB */
 299	{ DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
 300		   1360, 1440, 0, 768, 771, 778, 813, 0,
 301		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 302	/* 0x1b - 1280x800@60Hz RB */
 303	{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
 304		   1360, 1440, 0, 800, 803, 809, 823, 0,
 305		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 306	/* 0x1c - 1280x800@60Hz */
 307	{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
 308		   1480, 1680, 0, 800, 803, 809, 831, 0,
 309		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 310	/* 0x1d - 1280x800@75Hz */
 311	{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
 312		   1488, 1696, 0, 800, 803, 809, 838, 0,
 313		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 314	/* 0x1e - 1280x800@85Hz */
 315	{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
 316		   1496, 1712, 0, 800, 803, 809, 843, 0,
 317		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 318	/* 0x1f - 1280x800@120Hz RB */
 319	{ DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
 320		   1360, 1440, 0, 800, 803, 809, 847, 0,
 321		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 322	/* 0x20 - 1280x960@60Hz */
 323	{ DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
 324		   1488, 1800, 0, 960, 961, 964, 1000, 0,
 325		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 326	/* 0x21 - 1280x960@85Hz */
 327	{ DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
 328		   1504, 1728, 0, 960, 961, 964, 1011, 0,
 329		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 330	/* 0x22 - 1280x960@120Hz RB */
 331	{ DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
 332		   1360, 1440, 0, 960, 963, 967, 1017, 0,
 333		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 334	/* 0x23 - 1280x1024@60Hz */
 335	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
 336		   1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
 337		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 338	/* 0x24 - 1280x1024@75Hz */
 339	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
 340		   1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
 341		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 342	/* 0x25 - 1280x1024@85Hz */
 343	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
 344		   1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
 345		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 346	/* 0x26 - 1280x1024@120Hz RB */
 347	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
 348		   1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
 349		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 350	/* 0x27 - 1360x768@60Hz */
 351	{ DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
 352		   1536, 1792, 0, 768, 771, 777, 795, 0,
 353		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 354	/* 0x28 - 1360x768@120Hz RB */
 355	{ DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
 356		   1440, 1520, 0, 768, 771, 776, 813, 0,
 357		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 358	/* 0x51 - 1366x768@60Hz */
 359	{ DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
 360		   1579, 1792, 0, 768, 771, 774, 798, 0,
 361		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 362	/* 0x56 - 1366x768@60Hz */
 363	{ DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
 364		   1436, 1500, 0, 768, 769, 772, 800, 0,
 365		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 366	/* 0x29 - 1400x1050@60Hz RB */
 367	{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
 368		   1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
 369		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 370	/* 0x2a - 1400x1050@60Hz */
 371	{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
 372		   1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
 373		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 374	/* 0x2b - 1400x1050@75Hz */
 375	{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
 376		   1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
 377		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 378	/* 0x2c - 1400x1050@85Hz */
 379	{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
 380		   1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
 381		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 382	/* 0x2d - 1400x1050@120Hz RB */
 383	{ DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
 384		   1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
 385		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 386	/* 0x2e - 1440x900@60Hz RB */
 387	{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
 388		   1520, 1600, 0, 900, 903, 909, 926, 0,
 389		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 390	/* 0x2f - 1440x900@60Hz */
 391	{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
 392		   1672, 1904, 0, 900, 903, 909, 934, 0,
 393		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 394	/* 0x30 - 1440x900@75Hz */
 395	{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
 396		   1688, 1936, 0, 900, 903, 909, 942, 0,
 397		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 398	/* 0x31 - 1440x900@85Hz */
 399	{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
 400		   1696, 1952, 0, 900, 903, 909, 948, 0,
 401		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 402	/* 0x32 - 1440x900@120Hz RB */
 403	{ DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
 404		   1520, 1600, 0, 900, 903, 909, 953, 0,
 405		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 406	/* 0x53 - 1600x900@60Hz */
 407	{ DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
 408		   1704, 1800, 0, 900, 901, 904, 1000, 0,
 409		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 410	/* 0x33 - 1600x1200@60Hz */
 411	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
 412		   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
 413		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 414	/* 0x34 - 1600x1200@65Hz */
 415	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
 416		   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
 417		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 418	/* 0x35 - 1600x1200@70Hz */
 419	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
 420		   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
 421		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 422	/* 0x36 - 1600x1200@75Hz */
 423	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
 424		   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
 425		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 426	/* 0x37 - 1600x1200@85Hz */
 427	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
 428		   1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
 429		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 430	/* 0x38 - 1600x1200@120Hz RB */
 431	{ DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
 432		   1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
 433		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 434	/* 0x39 - 1680x1050@60Hz RB */
 435	{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
 436		   1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
 437		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 438	/* 0x3a - 1680x1050@60Hz */
 439	{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
 440		   1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
 441		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 442	/* 0x3b - 1680x1050@75Hz */
 443	{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
 444		   1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
 445		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 446	/* 0x3c - 1680x1050@85Hz */
 447	{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
 448		   1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
 449		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 450	/* 0x3d - 1680x1050@120Hz RB */
 451	{ DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
 452		   1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
 453		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 454	/* 0x3e - 1792x1344@60Hz */
 455	{ DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
 456		   2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
 457		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 458	/* 0x3f - 1792x1344@75Hz */
 459	{ DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
 460		   2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
 461		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 462	/* 0x40 - 1792x1344@120Hz RB */
 463	{ DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
 464		   1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
 465		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 466	/* 0x41 - 1856x1392@60Hz */
 467	{ DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
 468		   2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
 469		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 470	/* 0x42 - 1856x1392@75Hz */
 471	{ DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
 472		   2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
 473		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 474	/* 0x43 - 1856x1392@120Hz RB */
 475	{ DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
 476		   1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
 477		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 478	/* 0x52 - 1920x1080@60Hz */
 479	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
 480		   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
 481		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
 482	/* 0x44 - 1920x1200@60Hz RB */
 483	{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
 484		   2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
 485		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 486	/* 0x45 - 1920x1200@60Hz */
 487	{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
 488		   2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
 489		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 490	/* 0x46 - 1920x1200@75Hz */
 491	{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
 492		   2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
 493		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 494	/* 0x47 - 1920x1200@85Hz */
 495	{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
 496		   2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
 497		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 498	/* 0x48 - 1920x1200@120Hz RB */
 499	{ DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
 500		   2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
 501		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 502	/* 0x49 - 1920x1440@60Hz */
 503	{ DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
 504		   2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
 505		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 506	/* 0x4a - 1920x1440@75Hz */
 507	{ DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
 508		   2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
 509		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 510	/* 0x4b - 1920x1440@120Hz RB */
 511	{ DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
 512		   2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
 513		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 514	/* 0x54 - 2048x1152@60Hz */
 515	{ DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
 516		   2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
 517		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
 518	/* 0x4c - 2560x1600@60Hz RB */
 519	{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
 520		   2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
 521		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 522	/* 0x4d - 2560x1600@60Hz */
 523	{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
 524		   3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
 525		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 526	/* 0x4e - 2560x1600@75Hz */
 527	{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
 528		   3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
 529		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 530	/* 0x4f - 2560x1600@85Hz */
 531	{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
 532		   3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
 533		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
 534	/* 0x50 - 2560x1600@120Hz RB */
 535	{ DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
 536		   2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
 537		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 538	/* 0x57 - 4096x2160@60Hz RB */
 539	{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
 540		   4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
 541		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 542	/* 0x58 - 4096x2160@59.94Hz RB */
 543	{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
 544		   4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
 545		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
 546};
 547
 548/*
 549 * These more or less come from the DMT spec.  The 720x400 modes are
 550 * inferred from historical 80x25 practice.  The 640x480@67 and 832x624@75
 551 * modes are old-school Mac modes.  The EDID spec says the 1152x864@75 mode
 552 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
 553 * mode.
 554 *
 555 * The DMT modes have been fact-checked; the rest are mild guesses.
 556 */
 557static const struct drm_display_mode edid_est_modes[] = {
 558	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
 559		   968, 1056, 0, 600, 601, 605, 628, 0,
 560		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
 561	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
 562		   896, 1024, 0, 600, 601, 603,  625, 0,
 563		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
 564	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
 565		   720, 840, 0, 480, 481, 484, 500, 0,
 566		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
 567	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
 568		   704,  832, 0, 480, 489, 492, 520, 0,
 569		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
 570	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
 571		   768,  864, 0, 480, 483, 486, 525, 0,
 572		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
 573	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
 574		   752, 800, 0, 480, 490, 492, 525, 0,
 575		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
 576	{ DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
 577		   846, 900, 0, 400, 421, 423,  449, 0,
 578		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
 579	{ DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
 580		   846,  900, 0, 400, 412, 414, 449, 0,
 581		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
 582	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
 583		   1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
 584		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
 585	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
 586		   1136, 1312, 0,  768, 769, 772, 800, 0,
 587		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
 588	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
 589		   1184, 1328, 0,  768, 771, 777, 806, 0,
 590		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
 591	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
 592		   1184, 1344, 0,  768, 771, 777, 806, 0,
 593		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
 594	{ DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
 595		   1208, 1264, 0, 768, 768, 776, 817, 0,
 596		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
 597	{ DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
 598		   928, 1152, 0, 624, 625, 628, 667, 0,
 599		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
 600	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
 601		   896, 1056, 0, 600, 601, 604,  625, 0,
 602		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
 603	{ DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
 604		   976, 1040, 0, 600, 637, 643, 666, 0,
 605		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
 606	{ DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
 607		   1344, 1600, 0,  864, 865, 868, 900, 0,
 608		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
 609};
 610
 611struct minimode {
 612	short w;
 613	short h;
 614	short r;
 615	short rb;
 616};
 617
 618static const struct minimode est3_modes[] = {
 619	/* byte 6 */
 620	{ 640, 350, 85, 0 },
 621	{ 640, 400, 85, 0 },
 622	{ 720, 400, 85, 0 },
 623	{ 640, 480, 85, 0 },
 624	{ 848, 480, 60, 0 },
 625	{ 800, 600, 85, 0 },
 626	{ 1024, 768, 85, 0 },
 627	{ 1152, 864, 75, 0 },
 628	/* byte 7 */
 629	{ 1280, 768, 60, 1 },
 630	{ 1280, 768, 60, 0 },
 631	{ 1280, 768, 75, 0 },
 632	{ 1280, 768, 85, 0 },
 633	{ 1280, 960, 60, 0 },
 634	{ 1280, 960, 85, 0 },
 635	{ 1280, 1024, 60, 0 },
 636	{ 1280, 1024, 85, 0 },
 637	/* byte 8 */
 638	{ 1360, 768, 60, 0 },
 639	{ 1440, 900, 60, 1 },
 640	{ 1440, 900, 60, 0 },
 641	{ 1440, 900, 75, 0 },
 642	{ 1440, 900, 85, 0 },
 643	{ 1400, 1050, 60, 1 },
 644	{ 1400, 1050, 60, 0 },
 645	{ 1400, 1050, 75, 0 },
 646	/* byte 9 */
 647	{ 1400, 1050, 85, 0 },
 648	{ 1680, 1050, 60, 1 },
 649	{ 1680, 1050, 60, 0 },
 650	{ 1680, 1050, 75, 0 },
 651	{ 1680, 1050, 85, 0 },
 652	{ 1600, 1200, 60, 0 },
 653	{ 1600, 1200, 65, 0 },
 654	{ 1600, 1200, 70, 0 },
 655	/* byte 10 */
 656	{ 1600, 1200, 75, 0 },
 657	{ 1600, 1200, 85, 0 },
 658	{ 1792, 1344, 60, 0 },
 659	{ 1792, 1344, 75, 0 },
 660	{ 1856, 1392, 60, 0 },
 661	{ 1856, 1392, 75, 0 },
 662	{ 1920, 1200, 60, 1 },
 663	{ 1920, 1200, 60, 0 },
 664	/* byte 11 */
 665	{ 1920, 1200, 75, 0 },
 666	{ 1920, 1200, 85, 0 },
 667	{ 1920, 1440, 60, 0 },
 668	{ 1920, 1440, 75, 0 },
 669};
 670
 671static const struct minimode extra_modes[] = {
 672	{ 1024, 576,  60, 0 },
 673	{ 1366, 768,  60, 0 },
 674	{ 1600, 900,  60, 0 },
 675	{ 1680, 945,  60, 0 },
 676	{ 1920, 1080, 60, 0 },
 677	{ 2048, 1152, 60, 0 },
 678	{ 2048, 1536, 60, 0 },
 679};
 680
 681/*
 682 * Probably taken from CEA-861 spec.
 683 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
 684 *
 685 * Index using the VIC.
 686 */
 687static const struct drm_display_mode edid_cea_modes[] = {
 688	/* 0 - dummy, VICs start at 1 */
 689	{ },
 690	/* 1 - 640x480@60Hz */
 691	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
 692		   752, 800, 0, 480, 490, 492, 525, 0,
 693		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 694	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 695	/* 2 - 720x480@60Hz */
 696	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
 697		   798, 858, 0, 480, 489, 495, 525, 0,
 698		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 699	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 700	/* 3 - 720x480@60Hz */
 701	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
 702		   798, 858, 0, 480, 489, 495, 525, 0,
 703		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 704	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 705	/* 4 - 1280x720@60Hz */
 706	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
 707		   1430, 1650, 0, 720, 725, 730, 750, 0,
 708		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 709	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 710	/* 5 - 1920x1080i@60Hz */
 711	{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
 712		   2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
 713		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
 714			DRM_MODE_FLAG_INTERLACE),
 715	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 716	/* 6 - 720(1440)x480i@60Hz */
 717	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
 718		   801, 858, 0, 480, 488, 494, 525, 0,
 719		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 720			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 721	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 722	/* 7 - 720(1440)x480i@60Hz */
 723	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
 724		   801, 858, 0, 480, 488, 494, 525, 0,
 725		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 726			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 727	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 728	/* 8 - 720(1440)x240@60Hz */
 729	{ DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
 730		   801, 858, 0, 240, 244, 247, 262, 0,
 731		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 732			DRM_MODE_FLAG_DBLCLK),
 733	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 734	/* 9 - 720(1440)x240@60Hz */
 735	{ DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
 736		   801, 858, 0, 240, 244, 247, 262, 0,
 737		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 738			DRM_MODE_FLAG_DBLCLK),
 739	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 740	/* 10 - 2880x480i@60Hz */
 741	{ DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
 742		   3204, 3432, 0, 480, 488, 494, 525, 0,
 743		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 744			DRM_MODE_FLAG_INTERLACE),
 745	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 746	/* 11 - 2880x480i@60Hz */
 747	{ DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
 748		   3204, 3432, 0, 480, 488, 494, 525, 0,
 749		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 750			DRM_MODE_FLAG_INTERLACE),
 751	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 752	/* 12 - 2880x240@60Hz */
 753	{ DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
 754		   3204, 3432, 0, 240, 244, 247, 262, 0,
 755		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 756	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 757	/* 13 - 2880x240@60Hz */
 758	{ DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
 759		   3204, 3432, 0, 240, 244, 247, 262, 0,
 760		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 761	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 762	/* 14 - 1440x480@60Hz */
 763	{ DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
 764		   1596, 1716, 0, 480, 489, 495, 525, 0,
 765		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 766	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 767	/* 15 - 1440x480@60Hz */
 768	{ DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
 769		   1596, 1716, 0, 480, 489, 495, 525, 0,
 770		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 771	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 772	/* 16 - 1920x1080@60Hz */
 773	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
 774		   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
 775		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 776	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 777	/* 17 - 720x576@50Hz */
 778	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
 779		   796, 864, 0, 576, 581, 586, 625, 0,
 780		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 781	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 782	/* 18 - 720x576@50Hz */
 783	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
 784		   796, 864, 0, 576, 581, 586, 625, 0,
 785		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 786	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 787	/* 19 - 1280x720@50Hz */
 788	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
 789		   1760, 1980, 0, 720, 725, 730, 750, 0,
 790		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 791	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 792	/* 20 - 1920x1080i@50Hz */
 793	{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
 794		   2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
 795		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
 796			DRM_MODE_FLAG_INTERLACE),
 797	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 798	/* 21 - 720(1440)x576i@50Hz */
 799	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
 800		   795, 864, 0, 576, 580, 586, 625, 0,
 801		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 802			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 803	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 804	/* 22 - 720(1440)x576i@50Hz */
 805	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
 806		   795, 864, 0, 576, 580, 586, 625, 0,
 807		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 808			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 809	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 810	/* 23 - 720(1440)x288@50Hz */
 811	{ DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
 812		   795, 864, 0, 288, 290, 293, 312, 0,
 813		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 814			DRM_MODE_FLAG_DBLCLK),
 815	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 816	/* 24 - 720(1440)x288@50Hz */
 817	{ DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
 818		   795, 864, 0, 288, 290, 293, 312, 0,
 819		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 820			DRM_MODE_FLAG_DBLCLK),
 821	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 822	/* 25 - 2880x576i@50Hz */
 823	{ DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
 824		   3180, 3456, 0, 576, 580, 586, 625, 0,
 825		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 826			DRM_MODE_FLAG_INTERLACE),
 827	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 828	/* 26 - 2880x576i@50Hz */
 829	{ DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
 830		   3180, 3456, 0, 576, 580, 586, 625, 0,
 831		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 832			DRM_MODE_FLAG_INTERLACE),
 833	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 834	/* 27 - 2880x288@50Hz */
 835	{ DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
 836		   3180, 3456, 0, 288, 290, 293, 312, 0,
 837		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 838	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 839	/* 28 - 2880x288@50Hz */
 840	{ DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
 841		   3180, 3456, 0, 288, 290, 293, 312, 0,
 842		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 843	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 844	/* 29 - 1440x576@50Hz */
 845	{ DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
 846		   1592, 1728, 0, 576, 581, 586, 625, 0,
 847		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 848	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 849	/* 30 - 1440x576@50Hz */
 850	{ DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
 851		   1592, 1728, 0, 576, 581, 586, 625, 0,
 852		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 853	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 854	/* 31 - 1920x1080@50Hz */
 855	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
 856		   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
 857		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 858	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 859	/* 32 - 1920x1080@24Hz */
 860	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
 861		   2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
 862		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 863	  .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 864	/* 33 - 1920x1080@25Hz */
 865	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
 866		   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
 867		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 868	  .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 869	/* 34 - 1920x1080@30Hz */
 870	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
 871		   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
 872		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 873	  .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 874	/* 35 - 2880x480@60Hz */
 875	{ DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
 876		   3192, 3432, 0, 480, 489, 495, 525, 0,
 877		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 878	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 879	/* 36 - 2880x480@60Hz */
 880	{ DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
 881		   3192, 3432, 0, 480, 489, 495, 525, 0,
 882		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 883	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 884	/* 37 - 2880x576@50Hz */
 885	{ DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
 886		   3184, 3456, 0, 576, 581, 586, 625, 0,
 887		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 888	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 889	/* 38 - 2880x576@50Hz */
 890	{ DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
 891		   3184, 3456, 0, 576, 581, 586, 625, 0,
 892		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 893	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 894	/* 39 - 1920x1080i@50Hz */
 895	{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
 896		   2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
 897		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
 898			DRM_MODE_FLAG_INTERLACE),
 899	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 900	/* 40 - 1920x1080i@100Hz */
 901	{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
 902		   2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
 903		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
 904			DRM_MODE_FLAG_INTERLACE),
 905	  .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 906	/* 41 - 1280x720@100Hz */
 907	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
 908		   1760, 1980, 0, 720, 725, 730, 750, 0,
 909		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 910	  .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 911	/* 42 - 720x576@100Hz */
 912	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
 913		   796, 864, 0, 576, 581, 586, 625, 0,
 914		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 915	  .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 916	/* 43 - 720x576@100Hz */
 917	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
 918		   796, 864, 0, 576, 581, 586, 625, 0,
 919		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 920	  .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 921	/* 44 - 720(1440)x576i@100Hz */
 922	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
 923		   795, 864, 0, 576, 580, 586, 625, 0,
 924		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 925			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 926	  .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 927	/* 45 - 720(1440)x576i@100Hz */
 928	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
 929		   795, 864, 0, 576, 580, 586, 625, 0,
 930		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 931			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 932	  .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 933	/* 46 - 1920x1080i@120Hz */
 934	{ DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
 935		   2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
 936		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
 937			DRM_MODE_FLAG_INTERLACE),
 938	  .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 939	/* 47 - 1280x720@120Hz */
 940	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
 941		   1430, 1650, 0, 720, 725, 730, 750, 0,
 942		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
 943	  .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 944	/* 48 - 720x480@120Hz */
 945	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
 946		   798, 858, 0, 480, 489, 495, 525, 0,
 947		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 948	  .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 949	/* 49 - 720x480@120Hz */
 950	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
 951		   798, 858, 0, 480, 489, 495, 525, 0,
 952		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 953	  .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 954	/* 50 - 720(1440)x480i@120Hz */
 955	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
 956		   801, 858, 0, 480, 488, 494, 525, 0,
 957		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 958			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 959	  .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 960	/* 51 - 720(1440)x480i@120Hz */
 961	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
 962		   801, 858, 0, 480, 488, 494, 525, 0,
 963		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 964			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 965	  .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 966	/* 52 - 720x576@200Hz */
 967	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
 968		   796, 864, 0, 576, 581, 586, 625, 0,
 969		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 970	  .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 971	/* 53 - 720x576@200Hz */
 972	{ DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
 973		   796, 864, 0, 576, 581, 586, 625, 0,
 974		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 975	  .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 976	/* 54 - 720(1440)x576i@200Hz */
 977	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
 978		   795, 864, 0, 576, 580, 586, 625, 0,
 979		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 980			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 981	  .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 982	/* 55 - 720(1440)x576i@200Hz */
 983	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
 984		   795, 864, 0, 576, 580, 586, 625, 0,
 985		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
 986			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
 987	  .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 988	/* 56 - 720x480@240Hz */
 989	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
 990		   798, 858, 0, 480, 489, 495, 525, 0,
 991		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 992	  .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
 993	/* 57 - 720x480@240Hz */
 994	{ DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
 995		   798, 858, 0, 480, 489, 495, 525, 0,
 996		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
 997	  .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
 998	/* 58 - 720(1440)x480i@240Hz */
 999	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1000		   801, 858, 0, 480, 488, 494, 525, 0,
1001		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1002			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1003	  .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1004	/* 59 - 720(1440)x480i@240Hz */
1005	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1006		   801, 858, 0, 480, 488, 494, 525, 0,
1007		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1008			DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1009	  .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1010	/* 60 - 1280x720@24Hz */
1011	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1012		   3080, 3300, 0, 720, 725, 730, 750, 0,
1013		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1014	  .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1015	/* 61 - 1280x720@25Hz */
1016	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1017		   3740, 3960, 0, 720, 725, 730, 750, 0,
1018		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1019	  .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1020	/* 62 - 1280x720@30Hz */
1021	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1022		   3080, 3300, 0, 720, 725, 730, 750, 0,
1023		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1024	  .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1025	/* 63 - 1920x1080@120Hz */
1026	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1027		   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1028		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1029	 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1030	/* 64 - 1920x1080@100Hz */
1031	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1032		   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1033		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1034	 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1035	/* 65 - 1280x720@24Hz */
1036	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1037		   3080, 3300, 0, 720, 725, 730, 750, 0,
1038		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1039	  .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1040	/* 66 - 1280x720@25Hz */
1041	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1042		   3740, 3960, 0, 720, 725, 730, 750, 0,
1043		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1044	  .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1045	/* 67 - 1280x720@30Hz */
1046	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1047		   3080, 3300, 0, 720, 725, 730, 750, 0,
1048		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1049	  .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1050	/* 68 - 1280x720@50Hz */
1051	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1052		   1760, 1980, 0, 720, 725, 730, 750, 0,
1053		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1054	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1055	/* 69 - 1280x720@60Hz */
1056	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1057		   1430, 1650, 0, 720, 725, 730, 750, 0,
1058		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1059	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1060	/* 70 - 1280x720@100Hz */
1061	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1062		   1760, 1980, 0, 720, 725, 730, 750, 0,
1063		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1064	  .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1065	/* 71 - 1280x720@120Hz */
1066	{ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1067		   1430, 1650, 0, 720, 725, 730, 750, 0,
1068		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1069	  .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1070	/* 72 - 1920x1080@24Hz */
1071	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1072		   2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1073		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1074	  .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1075	/* 73 - 1920x1080@25Hz */
1076	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1077		   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1078		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1079	  .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1080	/* 74 - 1920x1080@30Hz */
1081	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1082		   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1083		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1084	  .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1085	/* 75 - 1920x1080@50Hz */
1086	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1087		   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1088		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1089	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1090	/* 76 - 1920x1080@60Hz */
1091	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1092		   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1093		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1094	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1095	/* 77 - 1920x1080@100Hz */
1096	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1097		   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1098		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1099	  .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1100	/* 78 - 1920x1080@120Hz */
1101	{ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1102		   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1103		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1104	  .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1105	/* 79 - 1680x720@24Hz */
1106	{ DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1107		   3080, 3300, 0, 720, 725, 730, 750, 0,
1108		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1109	  .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1110	/* 80 - 1680x720@25Hz */
1111	{ DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1112		   2948, 3168, 0, 720, 725, 730, 750, 0,
1113		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1114	  .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1115	/* 81 - 1680x720@30Hz */
1116	{ DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1117		   2420, 2640, 0, 720, 725, 730, 750, 0,
1118		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1119	  .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1120	/* 82 - 1680x720@50Hz */
1121	{ DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1122		   1980, 2200, 0, 720, 725, 730, 750, 0,
1123		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1124	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1125	/* 83 - 1680x720@60Hz */
1126	{ DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1127		   1980, 2200, 0, 720, 725, 730, 750, 0,
1128		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1129	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1130	/* 84 - 1680x720@100Hz */
1131	{ DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1132		   1780, 2000, 0, 720, 725, 730, 825, 0,
1133		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1134	  .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1135	/* 85 - 1680x720@120Hz */
1136	{ DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1137		   1780, 2000, 0, 720, 725, 730, 825, 0,
1138		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1139	  .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1140	/* 86 - 2560x1080@24Hz */
1141	{ DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1142		   3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1143		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1144	  .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1145	/* 87 - 2560x1080@25Hz */
1146	{ DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1147		   3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1148		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1149	  .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1150	/* 88 - 2560x1080@30Hz */
1151	{ DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1152		   3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1153		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1154	  .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1155	/* 89 - 2560x1080@50Hz */
1156	{ DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1157		   3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1158		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1159	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1160	/* 90 - 2560x1080@60Hz */
1161	{ DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1162		   2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1163		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1164	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1165	/* 91 - 2560x1080@100Hz */
1166	{ DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1167		   2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1168		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1169	  .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1170	/* 92 - 2560x1080@120Hz */
1171	{ DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1172		   3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1173		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1174	  .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1175	/* 93 - 3840x2160p@24Hz 16:9 */
1176	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1177		   5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1178		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1179	  .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1180	/* 94 - 3840x2160p@25Hz 16:9 */
1181	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1182		   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1183		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1184	  .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1185	/* 95 - 3840x2160p@30Hz 16:9 */
1186	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1187		   4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1188		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1189	  .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1190	/* 96 - 3840x2160p@50Hz 16:9 */
1191	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1192		   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1193		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1194	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1195	/* 97 - 3840x2160p@60Hz 16:9 */
1196	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1197		   4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1198		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1199	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1200	/* 98 - 4096x2160p@24Hz 256:135 */
1201	{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1202		   5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1203		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1204	  .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1205	/* 99 - 4096x2160p@25Hz 256:135 */
1206	{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1207		   5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1208		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1209	  .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1210	/* 100 - 4096x2160p@30Hz 256:135 */
1211	{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1212		   4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1213		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1214	  .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1215	/* 101 - 4096x2160p@50Hz 256:135 */
1216	{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1217		   5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1218		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1219	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1220	/* 102 - 4096x2160p@60Hz 256:135 */
1221	{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1222		   4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1223		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1224	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1225	/* 103 - 3840x2160p@24Hz 64:27 */
1226	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1227		   5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1228		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1229	  .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1230	/* 104 - 3840x2160p@25Hz 64:27 */
1231	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1232		   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1233		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1234	  .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1235	/* 105 - 3840x2160p@30Hz 64:27 */
1236	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1237		   4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1238		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1239	  .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1240	/* 106 - 3840x2160p@50Hz 64:27 */
1241	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1242		   4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1243		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1244	  .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1245	/* 107 - 3840x2160p@60Hz 64:27 */
1246	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1247		   4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1248		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1249	  .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1250};
1251
1252/*
1253 * HDMI 1.4 4k modes. Index using the VIC.
1254 */
1255static const struct drm_display_mode edid_4k_modes[] = {
1256	/* 0 - dummy, VICs start at 1 */
1257	{ },
1258	/* 1 - 3840x2160@30Hz */
1259	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1260		   3840, 4016, 4104, 4400, 0,
1261		   2160, 2168, 2178, 2250, 0,
1262		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1263	  .vrefresh = 30, },
1264	/* 2 - 3840x2160@25Hz */
1265	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1266		   3840, 4896, 4984, 5280, 0,
1267		   2160, 2168, 2178, 2250, 0,
1268		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1269	  .vrefresh = 25, },
1270	/* 3 - 3840x2160@24Hz */
1271	{ DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1272		   3840, 5116, 5204, 5500, 0,
1273		   2160, 2168, 2178, 2250, 0,
1274		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1275	  .vrefresh = 24, },
1276	/* 4 - 4096x2160@24Hz (SMPTE) */
1277	{ DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1278		   4096, 5116, 5204, 5500, 0,
1279		   2160, 2168, 2178, 2250, 0,
1280		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1281	  .vrefresh = 24, },
1282};
1283
1284/*** DDC fetch and block validation ***/
1285
1286static const u8 edid_header[] = {
1287	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1288};
1289
1290/**
1291 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1292 * @raw_edid: pointer to raw base EDID block
1293 *
1294 * Sanity check the header of the base EDID block.
1295 *
1296 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1297 */
1298int drm_edid_header_is_valid(const u8 *raw_edid)
1299{
1300	int i, score = 0;
1301
1302	for (i = 0; i < sizeof(edid_header); i++)
1303		if (raw_edid[i] == edid_header[i])
1304			score++;
1305
1306	return score;
1307}
1308EXPORT_SYMBOL(drm_edid_header_is_valid);
1309
1310static int edid_fixup __read_mostly = 6;
1311module_param_named(edid_fixup, edid_fixup, int, 0400);
1312MODULE_PARM_DESC(edid_fixup,
1313		 "Minimum number of valid EDID header bytes (0-8, default 6)");
1314
1315static void drm_get_displayid(struct drm_connector *connector,
1316			      struct edid *edid);
1317
1318static int drm_edid_block_checksum(const u8 *raw_edid)
 
 
1319{
1320	int i;
1321	u8 csum = 0;
1322	for (i = 0; i < EDID_LENGTH; i++)
1323		csum += raw_edid[i];
1324
1325	return csum;
1326}
1327
1328static bool drm_edid_is_zero(const u8 *in_edid, int length)
1329{
1330	if (memchr_inv(in_edid, 0, length))
1331		return false;
1332
1333	return true;
1334}
1335
1336/**
1337 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1338 * @raw_edid: pointer to raw EDID block
1339 * @block: type of block to validate (0 for base, extension otherwise)
1340 * @print_bad_edid: if true, dump bad EDID blocks to the console
1341 * @edid_corrupt: if true, the header or checksum is invalid
1342 *
1343 * Validate a base or extension EDID block and optionally dump bad blocks to
1344 * the console.
1345 *
1346 * Return: True if the block is valid, false otherwise.
1347 */
1348bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1349			  bool *edid_corrupt)
1350{
1351	u8 csum;
1352	struct edid *edid = (struct edid *)raw_edid;
1353
1354	if (WARN_ON(!raw_edid))
1355		return false;
1356
1357	if (edid_fixup > 8 || edid_fixup < 0)
1358		edid_fixup = 6;
1359
1360	if (block == 0) {
1361		int score = drm_edid_header_is_valid(raw_edid);
1362		if (score == 8) {
1363			if (edid_corrupt)
1364				*edid_corrupt = false;
1365		} else if (score >= edid_fixup) {
1366			/* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1367			 * The corrupt flag needs to be set here otherwise, the
1368			 * fix-up code here will correct the problem, the
1369			 * checksum is correct and the test fails
1370			 */
1371			if (edid_corrupt)
1372				*edid_corrupt = true;
1373			DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1374			memcpy(raw_edid, edid_header, sizeof(edid_header));
1375		} else {
1376			if (edid_corrupt)
1377				*edid_corrupt = true;
1378			goto bad;
1379		}
1380	}
1381
1382	csum = drm_edid_block_checksum(raw_edid);
 
1383	if (csum) {
1384		if (edid_corrupt)
1385			*edid_corrupt = true;
1386
1387		/* allow CEA to slide through, switches mangle this */
1388		if (raw_edid[0] == CEA_EXT) {
1389			DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1390			DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1391		} else {
1392			if (print_bad_edid)
1393				DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1394
1395			goto bad;
1396		}
1397	}
1398
1399	/* per-block-type checks */
1400	switch (raw_edid[0]) {
1401	case 0: /* base */
1402		if (edid->version != 1) {
1403			DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1404			goto bad;
1405		}
1406
1407		if (edid->revision > 4)
1408			DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1409		break;
1410
1411	default:
1412		break;
1413	}
1414
1415	return true;
1416
1417bad:
1418	if (print_bad_edid) {
1419		if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1420			pr_notice("EDID block is all zeroes\n");
1421		} else {
1422			pr_notice("Raw EDID:\n");
1423			print_hex_dump(KERN_NOTICE,
1424				       " \t", DUMP_PREFIX_NONE, 16, 1,
1425				       raw_edid, EDID_LENGTH, false);
1426		}
1427	}
1428	return false;
1429}
1430EXPORT_SYMBOL(drm_edid_block_valid);
1431
1432/**
1433 * drm_edid_is_valid - sanity check EDID data
1434 * @edid: EDID data
1435 *
1436 * Sanity-check an entire EDID record (including extensions)
1437 *
1438 * Return: True if the EDID data is valid, false otherwise.
1439 */
1440bool drm_edid_is_valid(struct edid *edid)
1441{
1442	int i;
1443	u8 *raw = (u8 *)edid;
1444
1445	if (!edid)
1446		return false;
1447
1448	for (i = 0; i <= edid->extensions; i++)
1449		if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1450			return false;
1451
1452	return true;
1453}
1454EXPORT_SYMBOL(drm_edid_is_valid);
1455
 
1456#define DDC_SEGMENT_ADDR 0x30
1457/**
1458 * drm_do_probe_ddc_edid() - get EDID information via I2C
1459 * @data: I2C device adapter
1460 * @buf: EDID data buffer to be filled
1461 * @block: 128 byte EDID block to start fetching from
1462 * @len: EDID data buffer length to fetch
1463 *
1464 * Try to fetch EDID information by calling I2C driver functions.
 
 
 
1465 *
1466 * Return: 0 on success or -1 on failure.
1467 */
1468static int
1469drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
 
1470{
1471	struct i2c_adapter *adapter = data;
1472	unsigned char start = block * EDID_LENGTH;
1473	unsigned char segment = block >> 1;
1474	unsigned char xfers = segment ? 3 : 2;
1475	int ret, retries = 5;
1476
1477	/*
1478	 * The core I2C driver will automatically retry the transfer if the
1479	 * adapter reports EAGAIN. However, we find that bit-banging transfers
1480	 * are susceptible to errors under a heavily loaded machine and
1481	 * generate spurious NAKs and timeouts. Retrying the transfer
1482	 * of the individual block a few times seems to overcome this.
1483	 */
1484	do {
1485		struct i2c_msg msgs[] = {
1486			{
1487				.addr	= DDC_SEGMENT_ADDR,
1488				.flags	= 0,
1489				.len	= 1,
1490				.buf	= &segment,
1491			}, {
1492				.addr	= DDC_ADDR,
1493				.flags	= 0,
1494				.len	= 1,
1495				.buf	= &start,
1496			}, {
1497				.addr	= DDC_ADDR,
1498				.flags	= I2C_M_RD,
1499				.len	= len,
1500				.buf	= buf,
1501			}
1502		};
 
 
1503
1504		/*
1505		 * Avoid sending the segment addr to not upset non-compliant
1506		 * DDC monitors.
1507		 */
1508		ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1509
1510		if (ret == -ENXIO) {
1511			DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1512					adapter->name);
1513			break;
1514		}
1515	} while (ret != xfers && --retries);
1516
1517	return ret == xfers ? 0 : -1;
1518}
1519
1520static void connector_bad_edid(struct drm_connector *connector,
1521			       u8 *edid, int num_blocks)
1522{
1523	int i;
 
1524
1525	if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1526		return;
1527
1528	dev_warn(connector->dev->dev,
1529		 "%s: EDID is invalid:\n",
1530		 connector->name);
1531	for (i = 0; i < num_blocks; i++) {
1532		u8 *block = edid + i * EDID_LENGTH;
1533		char prefix[20];
1534
1535		if (drm_edid_is_zero(block, EDID_LENGTH))
1536			sprintf(prefix, "\t[%02x] ZERO ", i);
1537		else if (!drm_edid_block_valid(block, i, false, NULL))
1538			sprintf(prefix, "\t[%02x] BAD  ", i);
1539		else
1540			sprintf(prefix, "\t[%02x] GOOD ", i);
1541
1542		print_hex_dump(KERN_WARNING,
1543			       prefix, DUMP_PREFIX_NONE, 16, 1,
1544			       block, EDID_LENGTH, false);
1545	}
1546}
1547
1548/**
1549 * drm_do_get_edid - get EDID data using a custom EDID block read function
1550 * @connector: connector we're probing
1551 * @get_edid_block: EDID block read function
1552 * @data: private data passed to the block read function
1553 *
1554 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1555 * exposes a different interface to read EDID blocks this function can be used
1556 * to get EDID data using a custom block read function.
1557 *
1558 * As in the general case the DDC bus is accessible by the kernel at the I2C
1559 * level, drivers must make all reasonable efforts to expose it as an I2C
1560 * adapter and use drm_get_edid() instead of abusing this function.
1561 *
1562 * The EDID may be overridden using debugfs override_edid or firmare EDID
1563 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1564 * order. Having either of them bypasses actual EDID reads.
1565 *
1566 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1567 */
1568struct edid *drm_do_get_edid(struct drm_connector *connector,
1569	int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1570			      size_t len),
1571	void *data)
1572{
1573	int i, j = 0, valid_extensions = 0;
1574	u8 *edid, *new;
1575	struct edid *override = NULL;
1576
1577	if (connector->override_edid)
1578		override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1579
1580	if (!override)
1581		override = drm_load_edid_firmware(connector);
1582
1583	if (!IS_ERR_OR_NULL(override))
1584		return override;
1585
1586	if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1587		return NULL;
1588
1589	/* base block fetch */
1590	for (i = 0; i < 4; i++) {
1591		if (get_edid_block(data, edid, 0, EDID_LENGTH))
1592			goto out;
1593		if (drm_edid_block_valid(edid, 0, false,
1594					 &connector->edid_corrupt))
1595			break;
1596		if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1597			connector->null_edid_counter++;
1598			goto carp;
1599		}
1600	}
1601	if (i == 4)
1602		goto carp;
1603
1604	/* if there's no extensions, we're done */
1605	valid_extensions = edid[0x7e];
1606	if (valid_extensions == 0)
1607		return (struct edid *)edid;
1608
1609	new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1610	if (!new)
1611		goto out;
1612	edid = new;
1613
1614	for (j = 1; j <= edid[0x7e]; j++) {
1615		u8 *block = edid + j * EDID_LENGTH;
1616
 
1617		for (i = 0; i < 4; i++) {
1618			if (get_edid_block(data, block, j, EDID_LENGTH))
 
 
1619				goto out;
1620			if (drm_edid_block_valid(block, j, false, NULL))
 
1621				break;
 
1622		}
1623
1624		if (i == 4)
1625			valid_extensions--;
 
 
1626	}
1627
1628	if (valid_extensions != edid[0x7e]) {
1629		u8 *base;
1630
1631		connector_bad_edid(connector, edid, edid[0x7e] + 1);
1632
1633		edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1634		edid[0x7e] = valid_extensions;
1635
1636		new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1637		if (!new)
1638			goto out;
1639
1640		base = new;
1641		for (i = 0; i <= edid[0x7e]; i++) {
1642			u8 *block = edid + i * EDID_LENGTH;
1643
1644			if (!drm_edid_block_valid(block, i, false, NULL))
1645				continue;
1646
1647			memcpy(base, block, EDID_LENGTH);
1648			base += EDID_LENGTH;
1649		}
1650
1651		kfree(edid);
1652		edid = new;
1653	}
1654
1655	return (struct edid *)edid;
1656
1657carp:
1658	connector_bad_edid(connector, edid, 1);
 
 
1659out:
1660	kfree(edid);
1661	return NULL;
1662}
1663EXPORT_SYMBOL_GPL(drm_do_get_edid);
1664
1665/**
1666 * drm_probe_ddc() - probe DDC presence
1667 * @adapter: I2C adapter to probe
1668 *
1669 * Return: True on success, false on failure.
 
1670 */
1671bool
1672drm_probe_ddc(struct i2c_adapter *adapter)
1673{
1674	unsigned char out;
1675
1676	return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1677}
1678EXPORT_SYMBOL(drm_probe_ddc);
1679
1680/**
1681 * drm_get_edid - get EDID data, if available
1682 * @connector: connector we're probing
1683 * @adapter: I2C adapter to use for DDC
1684 *
1685 * Poke the given I2C channel to grab EDID data if possible.  If found,
1686 * attach it to the connector.
1687 *
1688 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1689 */
1690struct edid *drm_get_edid(struct drm_connector *connector,
1691			  struct i2c_adapter *adapter)
1692{
1693	struct edid *edid;
1694
1695	if (connector->force == DRM_FORCE_OFF)
1696		return NULL;
1697
1698	if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1699		return NULL;
1700
1701	edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1702	if (edid)
1703		drm_get_displayid(connector, edid);
1704	return edid;
 
1705}
1706EXPORT_SYMBOL(drm_get_edid);
1707
1708/**
1709 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1710 * @connector: connector we're probing
1711 * @adapter: I2C adapter to use for DDC
1712 *
1713 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1714 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1715 * switch DDC to the GPU which is retrieving EDID.
1716 *
1717 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1718 */
1719struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1720				     struct i2c_adapter *adapter)
1721{
1722	struct pci_dev *pdev = connector->dev->pdev;
1723	struct edid *edid;
1724
1725	vga_switcheroo_lock_ddc(pdev);
1726	edid = drm_get_edid(connector, adapter);
1727	vga_switcheroo_unlock_ddc(pdev);
1728
1729	return edid;
1730}
1731EXPORT_SYMBOL(drm_get_edid_switcheroo);
1732
1733/**
1734 * drm_edid_duplicate - duplicate an EDID and the extensions
1735 * @edid: EDID to duplicate
1736 *
1737 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1738 */
1739struct edid *drm_edid_duplicate(const struct edid *edid)
1740{
1741	return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1742}
1743EXPORT_SYMBOL(drm_edid_duplicate);
1744
1745/*** EDID parsing ***/
1746
1747/**
1748 * edid_vendor - match a string against EDID's obfuscated vendor field
1749 * @edid: EDID to match
1750 * @vendor: vendor string
1751 *
1752 * Returns true if @vendor is in @edid, false otherwise
1753 */
1754static bool edid_vendor(const struct edid *edid, const char *vendor)
1755{
1756	char edid_vendor[3];
1757
1758	edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1759	edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1760			  ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1761	edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1762
1763	return !strncmp(edid_vendor, vendor, 3);
1764}
1765
1766/**
1767 * edid_get_quirks - return quirk flags for a given EDID
1768 * @edid: EDID to process
1769 *
1770 * This tells subsequent routines what fixes they need to apply.
1771 */
1772static u32 edid_get_quirks(const struct edid *edid)
1773{
1774	const struct edid_quirk *quirk;
1775	int i;
1776
1777	for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1778		quirk = &edid_quirk_list[i];
1779
1780		if (edid_vendor(edid, quirk->vendor) &&
1781		    (EDID_PRODUCT_ID(edid) == quirk->product_id))
1782			return quirk->quirks;
1783	}
1784
1785	return 0;
1786}
1787
1788#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1789#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1790
1791/**
1792 * edid_fixup_preferred - set preferred modes based on quirk list
1793 * @connector: has mode list to fix up
1794 * @quirks: quirks list
1795 *
1796 * Walk the mode list for @connector, clearing the preferred status
1797 * on existing modes and setting it anew for the right mode ala @quirks.
1798 */
1799static void edid_fixup_preferred(struct drm_connector *connector,
1800				 u32 quirks)
1801{
1802	struct drm_display_mode *t, *cur_mode, *preferred_mode;
1803	int target_refresh = 0;
1804	int cur_vrefresh, preferred_vrefresh;
1805
1806	if (list_empty(&connector->probed_modes))
1807		return;
1808
1809	if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1810		target_refresh = 60;
1811	if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1812		target_refresh = 75;
1813
1814	preferred_mode = list_first_entry(&connector->probed_modes,
1815					  struct drm_display_mode, head);
1816
1817	list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1818		cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1819
1820		if (cur_mode == preferred_mode)
1821			continue;
1822
1823		/* Largest mode is preferred */
1824		if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1825			preferred_mode = cur_mode;
1826
1827		cur_vrefresh = cur_mode->vrefresh ?
1828			cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1829		preferred_vrefresh = preferred_mode->vrefresh ?
1830			preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1831		/* At a given size, try to get closest to target refresh */
1832		if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1833		    MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1834		    MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1835			preferred_mode = cur_mode;
1836		}
1837	}
1838
1839	preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1840}
1841
1842static bool
1843mode_is_rb(const struct drm_display_mode *mode)
1844{
1845	return (mode->htotal - mode->hdisplay == 160) &&
1846	       (mode->hsync_end - mode->hdisplay == 80) &&
1847	       (mode->hsync_end - mode->hsync_start == 32) &&
1848	       (mode->vsync_start - mode->vdisplay == 3);
1849}
1850
1851/*
1852 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1853 * @dev: Device to duplicate against
1854 * @hsize: Mode width
1855 * @vsize: Mode height
1856 * @fresh: Mode refresh rate
1857 * @rb: Mode reduced-blanking-ness
1858 *
1859 * Walk the DMT mode list looking for a match for the given parameters.
1860 *
1861 * Return: A newly allocated copy of the mode, or NULL if not found.
1862 */
1863struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1864					   int hsize, int vsize, int fresh,
1865					   bool rb)
1866{
 
1867	int i;
1868
1869	for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1870		const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1871		if (hsize != ptr->hdisplay)
1872			continue;
1873		if (vsize != ptr->vdisplay)
1874			continue;
1875		if (fresh != drm_mode_vrefresh(ptr))
1876			continue;
1877		if (rb != mode_is_rb(ptr))
1878			continue;
1879
1880		return drm_mode_duplicate(dev, ptr);
1881	}
1882
1883	return NULL;
1884}
1885EXPORT_SYMBOL(drm_mode_find_dmt);
1886
1887typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1888
1889static void
1890cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1891{
1892	int i, n = 0;
1893	u8 d = ext[0x02];
1894	u8 *det_base = ext + d;
1895
1896	n = (127 - d) / 18;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1897	for (i = 0; i < n; i++)
1898		cb((struct detailed_timing *)(det_base + 18 * i), closure);
1899}
1900
1901static void
1902vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1903{
1904	unsigned int i, n = min((int)ext[0x02], 6);
1905	u8 *det_base = ext + 5;
1906
1907	if (ext[0x01] != 1)
1908		return; /* unknown version */
1909
1910	for (i = 0; i < n; i++)
1911		cb((struct detailed_timing *)(det_base + 18 * i), closure);
1912}
1913
1914static void
1915drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1916{
1917	int i;
1918	struct edid *edid = (struct edid *)raw_edid;
1919
1920	if (edid == NULL)
1921		return;
1922
1923	for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1924		cb(&(edid->detailed_timings[i]), closure);
1925
1926	for (i = 1; i <= raw_edid[0x7e]; i++) {
1927		u8 *ext = raw_edid + (i * EDID_LENGTH);
1928		switch (*ext) {
1929		case CEA_EXT:
1930			cea_for_each_detailed_block(ext, cb, closure);
1931			break;
1932		case VTB_EXT:
1933			vtb_for_each_detailed_block(ext, cb, closure);
1934			break;
1935		default:
1936			break;
1937		}
1938	}
1939}
1940
1941static void
1942is_rb(struct detailed_timing *t, void *data)
1943{
1944	u8 *r = (u8 *)t;
1945	if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1946		if (r[15] & 0x10)
1947			*(bool *)data = true;
1948}
1949
1950/* EDID 1.4 defines this explicitly.  For EDID 1.3, we guess, badly. */
1951static bool
1952drm_monitor_supports_rb(struct edid *edid)
1953{
1954	if (edid->revision >= 4) {
1955		bool ret = false;
1956		drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1957		return ret;
1958	}
1959
1960	return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1961}
1962
1963static void
1964find_gtf2(struct detailed_timing *t, void *data)
1965{
1966	u8 *r = (u8 *)t;
1967	if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1968		*(u8 **)data = r;
1969}
1970
1971/* Secondary GTF curve kicks in above some break frequency */
1972static int
1973drm_gtf2_hbreak(struct edid *edid)
1974{
1975	u8 *r = NULL;
1976	drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1977	return r ? (r[12] * 2) : 0;
1978}
1979
1980static int
1981drm_gtf2_2c(struct edid *edid)
1982{
1983	u8 *r = NULL;
1984	drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1985	return r ? r[13] : 0;
1986}
1987
1988static int
1989drm_gtf2_m(struct edid *edid)
1990{
1991	u8 *r = NULL;
1992	drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1993	return r ? (r[15] << 8) + r[14] : 0;
1994}
1995
1996static int
1997drm_gtf2_k(struct edid *edid)
1998{
1999	u8 *r = NULL;
2000	drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2001	return r ? r[16] : 0;
2002}
2003
2004static int
2005drm_gtf2_2j(struct edid *edid)
2006{
2007	u8 *r = NULL;
2008	drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2009	return r ? r[17] : 0;
2010}
2011
2012/**
2013 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2014 * @edid: EDID block to scan
2015 */
2016static int standard_timing_level(struct edid *edid)
2017{
2018	if (edid->revision >= 2) {
2019		if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2020			return LEVEL_CVT;
2021		if (drm_gtf2_hbreak(edid))
2022			return LEVEL_GTF2;
2023		return LEVEL_GTF;
2024	}
2025	return LEVEL_DMT;
2026}
2027
2028/*
2029 * 0 is reserved.  The spec says 0x01 fill for unused timings.  Some old
2030 * monitors fill with ascii space (0x20) instead.
2031 */
2032static int
2033bad_std_timing(u8 a, u8 b)
2034{
2035	return (a == 0x00 && b == 0x00) ||
2036	       (a == 0x01 && b == 0x01) ||
2037	       (a == 0x20 && b == 0x20);
2038}
2039
2040/**
2041 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2042 * @connector: connector of for the EDID block
2043 * @edid: EDID block to scan
2044 * @t: standard timing params
 
2045 *
2046 * Take the standard timing params (in this case width, aspect, and refresh)
2047 * and convert them into a real mode using CVT/GTF/DMT.
2048 */
2049static struct drm_display_mode *
2050drm_mode_std(struct drm_connector *connector, struct edid *edid,
2051	     struct std_timing *t)
2052{
2053	struct drm_device *dev = connector->dev;
2054	struct drm_display_mode *m, *mode = NULL;
2055	int hsize, vsize;
2056	int vrefresh_rate;
2057	unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2058		>> EDID_TIMING_ASPECT_SHIFT;
2059	unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2060		>> EDID_TIMING_VFREQ_SHIFT;
2061	int timing_level = standard_timing_level(edid);
2062
2063	if (bad_std_timing(t->hsize, t->vfreq_aspect))
2064		return NULL;
2065
2066	/* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2067	hsize = t->hsize * 8 + 248;
2068	/* vrefresh_rate = vfreq + 60 */
2069	vrefresh_rate = vfreq + 60;
2070	/* the vdisplay is calculated based on the aspect ratio */
2071	if (aspect_ratio == 0) {
2072		if (edid->revision < 3)
2073			vsize = hsize;
2074		else
2075			vsize = (hsize * 10) / 16;
2076	} else if (aspect_ratio == 1)
2077		vsize = (hsize * 3) / 4;
2078	else if (aspect_ratio == 2)
2079		vsize = (hsize * 4) / 5;
2080	else
2081		vsize = (hsize * 9) / 16;
2082
2083	/* HDTV hack, part 1 */
2084	if (vrefresh_rate == 60 &&
2085	    ((hsize == 1360 && vsize == 765) ||
2086	     (hsize == 1368 && vsize == 769))) {
2087		hsize = 1366;
2088		vsize = 768;
2089	}
2090
2091	/*
2092	 * If this connector already has a mode for this size and refresh
2093	 * rate (because it came from detailed or CVT info), use that
2094	 * instead.  This way we don't have to guess at interlace or
2095	 * reduced blanking.
2096	 */
2097	list_for_each_entry(m, &connector->probed_modes, head)
2098		if (m->hdisplay == hsize && m->vdisplay == vsize &&
2099		    drm_mode_vrefresh(m) == vrefresh_rate)
2100			return NULL;
2101
2102	/* HDTV hack, part 2 */
2103	if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2104		mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2105				    false);
2106		if (!mode)
2107			return NULL;
2108		mode->hdisplay = 1366;
2109		mode->hsync_start = mode->hsync_start - 1;
2110		mode->hsync_end = mode->hsync_end - 1;
2111		return mode;
2112	}
2113
2114	/* check whether it can be found in default mode table */
2115	if (drm_monitor_supports_rb(edid)) {
2116		mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2117					 true);
2118		if (mode)
2119			return mode;
2120	}
2121	mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2122	if (mode)
2123		return mode;
2124
2125	/* okay, generate it */
2126	switch (timing_level) {
2127	case LEVEL_DMT:
2128		break;
2129	case LEVEL_GTF:
2130		mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2131		break;
2132	case LEVEL_GTF2:
2133		/*
2134		 * This is potentially wrong if there's ever a monitor with
2135		 * more than one ranges section, each claiming a different
2136		 * secondary GTF curve.  Please don't do that.
2137		 */
2138		mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2139		if (!mode)
2140			return NULL;
2141		if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2142			drm_mode_destroy(dev, mode);
2143			mode = drm_gtf_mode_complex(dev, hsize, vsize,
2144						    vrefresh_rate, 0, 0,
2145						    drm_gtf2_m(edid),
2146						    drm_gtf2_2c(edid),
2147						    drm_gtf2_k(edid),
2148						    drm_gtf2_2j(edid));
2149		}
2150		break;
2151	case LEVEL_CVT:
2152		mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2153				    false);
2154		break;
2155	}
2156	return mode;
2157}
2158
2159/*
2160 * EDID is delightfully ambiguous about how interlaced modes are to be
2161 * encoded.  Our internal representation is of frame height, but some
2162 * HDTV detailed timings are encoded as field height.
2163 *
2164 * The format list here is from CEA, in frame size.  Technically we
2165 * should be checking refresh rate too.  Whatever.
2166 */
2167static void
2168drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2169			    struct detailed_pixel_timing *pt)
2170{
2171	int i;
2172	static const struct {
2173		int w, h;
2174	} cea_interlaced[] = {
2175		{ 1920, 1080 },
2176		{  720,  480 },
2177		{ 1440,  480 },
2178		{ 2880,  480 },
2179		{  720,  576 },
2180		{ 1440,  576 },
2181		{ 2880,  576 },
2182	};
2183
2184	if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2185		return;
2186
2187	for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2188		if ((mode->hdisplay == cea_interlaced[i].w) &&
2189		    (mode->vdisplay == cea_interlaced[i].h / 2)) {
2190			mode->vdisplay *= 2;
2191			mode->vsync_start *= 2;
2192			mode->vsync_end *= 2;
2193			mode->vtotal *= 2;
2194			mode->vtotal |= 1;
2195		}
2196	}
2197
2198	mode->flags |= DRM_MODE_FLAG_INTERLACE;
2199}
2200
2201/**
2202 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2203 * @dev: DRM device (needed to create new mode)
2204 * @edid: EDID block
2205 * @timing: EDID detailed timing info
2206 * @quirks: quirks to apply
2207 *
2208 * An EDID detailed timing block contains enough info for us to create and
2209 * return a new struct drm_display_mode.
2210 */
2211static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2212						  struct edid *edid,
2213						  struct detailed_timing *timing,
2214						  u32 quirks)
2215{
2216	struct drm_display_mode *mode;
2217	struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2218	unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2219	unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2220	unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2221	unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2222	unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2223	unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2224	unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2225	unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2226
2227	/* ignore tiny modes */
2228	if (hactive < 64 || vactive < 64)
2229		return NULL;
2230
2231	if (pt->misc & DRM_EDID_PT_STEREO) {
2232		DRM_DEBUG_KMS("stereo mode not supported\n");
2233		return NULL;
2234	}
2235	if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2236		DRM_DEBUG_KMS("composite sync not supported\n");
2237	}
2238
2239	/* it is incorrect if hsync/vsync width is zero */
2240	if (!hsync_pulse_width || !vsync_pulse_width) {
2241		DRM_DEBUG_KMS("Incorrect Detailed timing. "
2242				"Wrong Hsync/Vsync pulse width\n");
2243		return NULL;
2244	}
2245
2246	if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2247		mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2248		if (!mode)
2249			return NULL;
2250
2251		goto set_size;
2252	}
2253
2254	mode = drm_mode_create(dev);
2255	if (!mode)
2256		return NULL;
2257
 
 
2258	if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2259		timing->pixel_clock = cpu_to_le16(1088);
2260
2261	mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2262
2263	mode->hdisplay = hactive;
2264	mode->hsync_start = mode->hdisplay + hsync_offset;
2265	mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2266	mode->htotal = mode->hdisplay + hblank;
2267
2268	mode->vdisplay = vactive;
2269	mode->vsync_start = mode->vdisplay + vsync_offset;
2270	mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2271	mode->vtotal = mode->vdisplay + vblank;
2272
2273	/* Some EDIDs have bogus h/vtotal values */
2274	if (mode->hsync_end > mode->htotal)
2275		mode->htotal = mode->hsync_end + 1;
2276	if (mode->vsync_end > mode->vtotal)
2277		mode->vtotal = mode->vsync_end + 1;
2278
2279	drm_mode_do_interlace_quirk(mode, pt);
2280
 
 
2281	if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2282		pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2283	}
2284
2285	mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2286		DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2287	mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2288		DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2289
2290set_size:
2291	mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2292	mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2293
2294	if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2295		mode->width_mm *= 10;
2296		mode->height_mm *= 10;
2297	}
2298
2299	if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2300		mode->width_mm = edid->width_cm * 10;
2301		mode->height_mm = edid->height_cm * 10;
2302	}
2303
2304	mode->type = DRM_MODE_TYPE_DRIVER;
2305	mode->vrefresh = drm_mode_vrefresh(mode);
2306	drm_mode_set_name(mode);
2307
2308	return mode;
 
 
 
 
 
 
2309}
2310
2311static bool
2312mode_in_hsync_range(const struct drm_display_mode *mode,
2313		    struct edid *edid, u8 *t)
2314{
2315	int hsync, hmin, hmax;
2316
2317	hmin = t[7];
2318	if (edid->revision >= 4)
2319	    hmin += ((t[4] & 0x04) ? 255 : 0);
2320	hmax = t[8];
2321	if (edid->revision >= 4)
2322	    hmax += ((t[4] & 0x08) ? 255 : 0);
2323	hsync = drm_mode_hsync(mode);
2324
2325	return (hsync <= hmax && hsync >= hmin);
2326}
2327
2328static bool
2329mode_in_vsync_range(const struct drm_display_mode *mode,
2330		    struct edid *edid, u8 *t)
2331{
2332	int vsync, vmin, vmax;
2333
2334	vmin = t[5];
2335	if (edid->revision >= 4)
2336	    vmin += ((t[4] & 0x01) ? 255 : 0);
2337	vmax = t[6];
2338	if (edid->revision >= 4)
2339	    vmax += ((t[4] & 0x02) ? 255 : 0);
2340	vsync = drm_mode_vrefresh(mode);
2341
2342	return (vsync <= vmax && vsync >= vmin);
2343}
2344
2345static u32
2346range_pixel_clock(struct edid *edid, u8 *t)
2347{
2348	/* unspecified */
2349	if (t[9] == 0 || t[9] == 255)
2350		return 0;
2351
2352	/* 1.4 with CVT support gives us real precision, yay */
2353	if (edid->revision >= 4 && t[10] == 0x04)
2354		return (t[9] * 10000) - ((t[12] >> 2) * 250);
2355
2356	/* 1.3 is pathetic, so fuzz up a bit */
2357	return t[9] * 10000 + 5001;
2358}
2359
2360static bool
2361mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2362	      struct detailed_timing *timing)
2363{
2364	u32 max_clock;
2365	u8 *t = (u8 *)timing;
2366
2367	if (!mode_in_hsync_range(mode, edid, t))
2368		return false;
2369
2370	if (!mode_in_vsync_range(mode, edid, t))
2371		return false;
2372
2373	if ((max_clock = range_pixel_clock(edid, t)))
2374		if (mode->clock > max_clock)
2375			return false;
2376
2377	/* 1.4 max horizontal check */
2378	if (edid->revision >= 4 && t[10] == 0x04)
2379		if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2380			return false;
2381
2382	if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2383		return false;
2384
2385	return true;
2386}
2387
2388static bool valid_inferred_mode(const struct drm_connector *connector,
2389				const struct drm_display_mode *mode)
2390{
2391	const struct drm_display_mode *m;
2392	bool ok = false;
2393
2394	list_for_each_entry(m, &connector->probed_modes, head) {
2395		if (mode->hdisplay == m->hdisplay &&
2396		    mode->vdisplay == m->vdisplay &&
2397		    drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2398			return false; /* duplicated */
2399		if (mode->hdisplay <= m->hdisplay &&
2400		    mode->vdisplay <= m->vdisplay)
2401			ok = true;
2402	}
2403	return ok;
2404}
2405
2406static int
2407drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2408			struct detailed_timing *timing)
2409{
2410	int i, modes = 0;
2411	struct drm_display_mode *newmode;
2412	struct drm_device *dev = connector->dev;
2413
2414	for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2415		if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2416		    valid_inferred_mode(connector, drm_dmt_modes + i)) {
2417			newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2418			if (newmode) {
2419				drm_mode_probed_add(connector, newmode);
2420				modes++;
2421			}
2422		}
2423	}
2424
2425	return modes;
2426}
2427
2428/* fix up 1366x768 mode from 1368x768;
2429 * GFT/CVT can't express 1366 width which isn't dividable by 8
2430 */
2431void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2432{
2433	if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2434		mode->hdisplay = 1366;
2435		mode->hsync_start--;
2436		mode->hsync_end--;
2437		drm_mode_set_name(mode);
2438	}
2439}
2440
2441static int
2442drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2443			struct detailed_timing *timing)
2444{
2445	int i, modes = 0;
2446	struct drm_display_mode *newmode;
2447	struct drm_device *dev = connector->dev;
2448
2449	for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2450		const struct minimode *m = &extra_modes[i];
2451		newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2452		if (!newmode)
2453			return modes;
2454
2455		drm_mode_fixup_1366x768(newmode);
2456		if (!mode_in_range(newmode, edid, timing) ||
2457		    !valid_inferred_mode(connector, newmode)) {
2458			drm_mode_destroy(dev, newmode);
2459			continue;
2460		}
2461
2462		drm_mode_probed_add(connector, newmode);
2463		modes++;
2464	}
2465
2466	return modes;
2467}
2468
2469static int
2470drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2471			struct detailed_timing *timing)
2472{
2473	int i, modes = 0;
2474	struct drm_display_mode *newmode;
2475	struct drm_device *dev = connector->dev;
2476	bool rb = drm_monitor_supports_rb(edid);
2477
2478	for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2479		const struct minimode *m = &extra_modes[i];
2480		newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2481		if (!newmode)
2482			return modes;
2483
2484		drm_mode_fixup_1366x768(newmode);
2485		if (!mode_in_range(newmode, edid, timing) ||
2486		    !valid_inferred_mode(connector, newmode)) {
2487			drm_mode_destroy(dev, newmode);
2488			continue;
2489		}
2490
2491		drm_mode_probed_add(connector, newmode);
2492		modes++;
2493	}
2494
2495	return modes;
2496}
2497
2498static void
2499do_inferred_modes(struct detailed_timing *timing, void *c)
2500{
2501	struct detailed_mode_closure *closure = c;
2502	struct detailed_non_pixel *data = &timing->data.other_data;
2503	struct detailed_data_monitor_range *range = &data->data.range;
2504
2505	if (data->type != EDID_DETAIL_MONITOR_RANGE)
2506		return;
2507
2508	closure->modes += drm_dmt_modes_for_range(closure->connector,
2509						  closure->edid,
2510						  timing);
2511	
2512	if (!version_greater(closure->edid, 1, 1))
2513		return; /* GTF not defined yet */
2514
2515	switch (range->flags) {
2516	case 0x02: /* secondary gtf, XXX could do more */
2517	case 0x00: /* default gtf */
2518		closure->modes += drm_gtf_modes_for_range(closure->connector,
2519							  closure->edid,
2520							  timing);
2521		break;
2522	case 0x04: /* cvt, only in 1.4+ */
2523		if (!version_greater(closure->edid, 1, 3))
2524			break;
2525
2526		closure->modes += drm_cvt_modes_for_range(closure->connector,
2527							  closure->edid,
2528							  timing);
2529		break;
2530	case 0x01: /* just the ranges, no formula */
2531	default:
2532		break;
2533	}
2534}
2535
2536static int
2537add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2538{
2539	struct detailed_mode_closure closure = {
2540		.connector = connector,
2541		.edid = edid,
2542	};
2543
2544	if (version_greater(edid, 1, 0))
2545		drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2546					    &closure);
2547
2548	return closure.modes;
2549}
2550
2551static int
2552drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2553{
2554	int i, j, m, modes = 0;
2555	struct drm_display_mode *mode;
2556	u8 *est = ((u8 *)timing) + 6;
2557
2558	for (i = 0; i < 6; i++) {
2559		for (j = 7; j >= 0; j--) {
2560			m = (i * 8) + (7 - j);
2561			if (m >= ARRAY_SIZE(est3_modes))
2562				break;
2563			if (est[i] & (1 << j)) {
2564				mode = drm_mode_find_dmt(connector->dev,
2565							 est3_modes[m].w,
2566							 est3_modes[m].h,
2567							 est3_modes[m].r,
2568							 est3_modes[m].rb);
2569				if (mode) {
2570					drm_mode_probed_add(connector, mode);
2571					modes++;
2572				}
2573			}
2574		}
2575	}
2576
2577	return modes;
2578}
2579
2580static void
2581do_established_modes(struct detailed_timing *timing, void *c)
2582{
2583	struct detailed_mode_closure *closure = c;
2584	struct detailed_non_pixel *data = &timing->data.other_data;
2585
2586	if (data->type == EDID_DETAIL_EST_TIMINGS)
2587		closure->modes += drm_est3_modes(closure->connector, timing);
2588}
2589
2590/**
2591 * add_established_modes - get est. modes from EDID and add them
2592 * @connector: connector to add mode(s) to
2593 * @edid: EDID block to scan
2594 *
2595 * Each EDID block contains a bitmap of the supported "established modes" list
2596 * (defined above).  Tease them out and add them to the global modes list.
2597 */
2598static int
2599add_established_modes(struct drm_connector *connector, struct edid *edid)
2600{
2601	struct drm_device *dev = connector->dev;
2602	unsigned long est_bits = edid->established_timings.t1 |
2603		(edid->established_timings.t2 << 8) |
2604		((edid->established_timings.mfg_rsvd & 0x80) << 9);
2605	int i, modes = 0;
2606	struct detailed_mode_closure closure = {
2607		.connector = connector,
2608		.edid = edid,
2609	};
2610
2611	for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2612		if (est_bits & (1<<i)) {
2613			struct drm_display_mode *newmode;
2614			newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2615			if (newmode) {
2616				drm_mode_probed_add(connector, newmode);
2617				modes++;
2618			}
2619		}
2620	}
2621
2622	if (version_greater(edid, 1, 0))
2623		    drm_for_each_detailed_block((u8 *)edid,
2624						do_established_modes, &closure);
2625
2626	return modes + closure.modes;
2627}
2628
2629static void
2630do_standard_modes(struct detailed_timing *timing, void *c)
2631{
2632	struct detailed_mode_closure *closure = c;
2633	struct detailed_non_pixel *data = &timing->data.other_data;
2634	struct drm_connector *connector = closure->connector;
2635	struct edid *edid = closure->edid;
2636
2637	if (data->type == EDID_DETAIL_STD_MODES) {
2638		int i;
2639		for (i = 0; i < 6; i++) {
2640			struct std_timing *std;
2641			struct drm_display_mode *newmode;
2642
2643			std = &data->data.timings[i];
2644			newmode = drm_mode_std(connector, edid, std);
 
2645			if (newmode) {
2646				drm_mode_probed_add(connector, newmode);
2647				closure->modes++;
2648			}
2649		}
2650	}
2651}
2652
2653/**
2654 * add_standard_modes - get std. modes from EDID and add them
2655 * @connector: connector to add mode(s) to
2656 * @edid: EDID block to scan
2657 *
2658 * Standard modes can be calculated using the appropriate standard (DMT,
2659 * GTF or CVT. Grab them from @edid and add them to the list.
2660 */
2661static int
2662add_standard_modes(struct drm_connector *connector, struct edid *edid)
2663{
2664	int i, modes = 0;
2665	struct detailed_mode_closure closure = {
2666		.connector = connector,
2667		.edid = edid,
2668	};
2669
2670	for (i = 0; i < EDID_STD_TIMINGS; i++) {
2671		struct drm_display_mode *newmode;
2672
2673		newmode = drm_mode_std(connector, edid,
2674				       &edid->standard_timings[i]);
 
2675		if (newmode) {
2676			drm_mode_probed_add(connector, newmode);
2677			modes++;
2678		}
2679	}
2680
2681	if (version_greater(edid, 1, 0))
2682		drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2683					    &closure);
2684
2685	/* XXX should also look for standard codes in VTB blocks */
2686
2687	return modes + closure.modes;
2688}
2689
2690static int drm_cvt_modes(struct drm_connector *connector,
2691			 struct detailed_timing *timing)
2692{
2693	int i, j, modes = 0;
2694	struct drm_display_mode *newmode;
2695	struct drm_device *dev = connector->dev;
2696	struct cvt_timing *cvt;
2697	const int rates[] = { 60, 85, 75, 60, 50 };
2698	const u8 empty[3] = { 0, 0, 0 };
2699
2700	for (i = 0; i < 4; i++) {
2701		int uninitialized_var(width), height;
2702		cvt = &(timing->data.other_data.data.cvt[i]);
2703
2704		if (!memcmp(cvt->code, empty, 3))
2705			continue;
2706
2707		height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2708		switch (cvt->code[1] & 0x0c) {
2709		case 0x00:
2710			width = height * 4 / 3;
2711			break;
2712		case 0x04:
2713			width = height * 16 / 9;
2714			break;
2715		case 0x08:
2716			width = height * 16 / 10;
2717			break;
2718		case 0x0c:
2719			width = height * 15 / 9;
2720			break;
2721		}
2722
2723		for (j = 1; j < 5; j++) {
2724			if (cvt->code[2] & (1 << j)) {
2725				newmode = drm_cvt_mode(dev, width, height,
2726						       rates[j], j == 0,
2727						       false, false);
2728				if (newmode) {
2729					drm_mode_probed_add(connector, newmode);
2730					modes++;
2731				}
2732			}
2733		}
2734	}
2735
2736	return modes;
2737}
2738
2739static void
2740do_cvt_mode(struct detailed_timing *timing, void *c)
2741{
2742	struct detailed_mode_closure *closure = c;
2743	struct detailed_non_pixel *data = &timing->data.other_data;
2744
2745	if (data->type == EDID_DETAIL_CVT_3BYTE)
2746		closure->modes += drm_cvt_modes(closure->connector, timing);
2747}
2748
2749static int
2750add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2751{	
2752	struct detailed_mode_closure closure = {
2753		.connector = connector,
2754		.edid = edid,
2755	};
2756
2757	if (version_greater(edid, 1, 2))
2758		drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2759
2760	/* XXX should also look for CVT codes in VTB blocks */
2761
2762	return closure.modes;
2763}
2764
2765static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2766
2767static void
2768do_detailed_mode(struct detailed_timing *timing, void *c)
2769{
2770	struct detailed_mode_closure *closure = c;
2771	struct drm_display_mode *newmode;
2772
2773	if (timing->pixel_clock) {
2774		newmode = drm_mode_detailed(closure->connector->dev,
2775					    closure->edid, timing,
2776					    closure->quirks);
2777		if (!newmode)
2778			return;
2779
2780		if (closure->preferred)
2781			newmode->type |= DRM_MODE_TYPE_PREFERRED;
2782
2783		/*
2784		 * Detailed modes are limited to 10kHz pixel clock resolution,
2785		 * so fix up anything that looks like CEA/HDMI mode, but the clock
2786		 * is just slightly off.
2787		 */
2788		fixup_detailed_cea_mode_clock(newmode);
2789
2790		drm_mode_probed_add(closure->connector, newmode);
2791		closure->modes++;
2792		closure->preferred = false;
2793	}
2794}
2795
2796/*
2797 * add_detailed_modes - Add modes from detailed timings
2798 * @connector: attached connector
2799 * @edid: EDID block to scan
2800 * @quirks: quirks to apply
2801 */
2802static int
2803add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2804		   u32 quirks)
2805{
2806	struct detailed_mode_closure closure = {
2807		.connector = connector,
2808		.edid = edid,
2809		.preferred = true,
2810		.quirks = quirks,
 
2811	};
2812
2813	if (closure.preferred && !version_greater(edid, 1, 3))
2814		closure.preferred =
2815		    (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2816
2817	drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2818
2819	return closure.modes;
2820}
2821
 
2822#define AUDIO_BLOCK	0x01
2823#define VIDEO_BLOCK     0x02
2824#define VENDOR_BLOCK    0x03
2825#define SPEAKER_BLOCK	0x04
2826#define USE_EXTENDED_TAG 0x07
2827#define EXT_VIDEO_CAPABILITY_BLOCK 0x00
2828#define EXT_VIDEO_DATA_BLOCK_420	0x0E
2829#define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
2830#define EDID_BASIC_AUDIO	(1 << 6)
2831#define EDID_CEA_YCRCB444	(1 << 5)
2832#define EDID_CEA_YCRCB422	(1 << 4)
2833#define EDID_CEA_VCDB_QS	(1 << 6)
2834
2835/*
2836 * Search EDID for CEA extension block.
2837 */
2838static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
2839{
2840	u8 *edid_ext = NULL;
2841	int i;
2842
2843	/* No EDID or EDID extensions */
2844	if (edid == NULL || edid->extensions == 0)
2845		return NULL;
2846
2847	/* Find CEA extension */
2848	for (i = 0; i < edid->extensions; i++) {
2849		edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2850		if (edid_ext[0] == ext_id)
2851			break;
2852	}
2853
2854	if (i == edid->extensions)
2855		return NULL;
2856
2857	return edid_ext;
2858}
2859
2860static u8 *drm_find_cea_extension(const struct edid *edid)
2861{
2862	return drm_find_edid_extension(edid, CEA_EXT);
2863}
2864
2865static u8 *drm_find_displayid_extension(const struct edid *edid)
2866{
2867	return drm_find_edid_extension(edid, DISPLAYID_EXT);
2868}
2869
2870/*
2871 * Calculate the alternate clock for the CEA mode
2872 * (60Hz vs. 59.94Hz etc.)
2873 */
2874static unsigned int
2875cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2876{
2877	unsigned int clock = cea_mode->clock;
2878
2879	if (cea_mode->vrefresh % 6 != 0)
2880		return clock;
2881
2882	/*
2883	 * edid_cea_modes contains the 59.94Hz
2884	 * variant for 240 and 480 line modes,
2885	 * and the 60Hz variant otherwise.
2886	 */
2887	if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2888		clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2889	else
2890		clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2891
2892	return clock;
2893}
2894
2895static bool
2896cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2897{
2898	/*
2899	 * For certain VICs the spec allows the vertical
2900	 * front porch to vary by one or two lines.
2901	 *
2902	 * cea_modes[] stores the variant with the shortest
2903	 * vertical front porch. We can adjust the mode to
2904	 * get the other variants by simply increasing the
2905	 * vertical front porch length.
2906	 */
2907	BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2908		     edid_cea_modes[9].vtotal != 262 ||
2909		     edid_cea_modes[12].vtotal != 262 ||
2910		     edid_cea_modes[13].vtotal != 262 ||
2911		     edid_cea_modes[23].vtotal != 312 ||
2912		     edid_cea_modes[24].vtotal != 312 ||
2913		     edid_cea_modes[27].vtotal != 312 ||
2914		     edid_cea_modes[28].vtotal != 312);
2915
2916	if (((vic == 8 || vic == 9 ||
2917	      vic == 12 || vic == 13) && mode->vtotal < 263) ||
2918	    ((vic == 23 || vic == 24 ||
2919	      vic == 27 || vic == 28) && mode->vtotal < 314)) {
2920		mode->vsync_start++;
2921		mode->vsync_end++;
2922		mode->vtotal++;
2923
2924		return true;
2925	}
2926
2927	return false;
2928}
2929
2930static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2931					     unsigned int clock_tolerance)
2932{
2933	u8 vic;
2934
2935	if (!to_match->clock)
2936		return 0;
2937
2938	for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2939		struct drm_display_mode cea_mode = edid_cea_modes[vic];
2940		unsigned int clock1, clock2;
2941
2942		/* Check both 60Hz and 59.94Hz */
2943		clock1 = cea_mode.clock;
2944		clock2 = cea_mode_alternate_clock(&cea_mode);
2945
2946		if (abs(to_match->clock - clock1) > clock_tolerance &&
2947		    abs(to_match->clock - clock2) > clock_tolerance)
2948			continue;
2949
2950		do {
2951			if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2952				return vic;
2953		} while (cea_mode_alternate_timings(vic, &cea_mode));
2954	}
2955
2956	return 0;
2957}
2958
2959/**
2960 * drm_match_cea_mode - look for a CEA mode matching given mode
2961 * @to_match: display mode
2962 *
2963 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2964 * mode.
2965 */
2966u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2967{
2968	u8 vic;
2969
2970	if (!to_match->clock)
2971		return 0;
2972
2973	for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2974		struct drm_display_mode cea_mode = edid_cea_modes[vic];
2975		unsigned int clock1, clock2;
2976
2977		/* Check both 60Hz and 59.94Hz */
2978		clock1 = cea_mode.clock;
2979		clock2 = cea_mode_alternate_clock(&cea_mode);
2980
2981		if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
2982		    KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
2983			continue;
2984
2985		do {
2986			if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2987				return vic;
2988		} while (cea_mode_alternate_timings(vic, &cea_mode));
2989	}
2990
2991	return 0;
2992}
2993EXPORT_SYMBOL(drm_match_cea_mode);
2994
2995static bool drm_valid_cea_vic(u8 vic)
2996{
2997	return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2998}
2999
3000/**
3001 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
3002 * the input VIC from the CEA mode list
3003 * @video_code: ID given to each of the CEA modes
3004 *
3005 * Returns picture aspect ratio
3006 */
3007enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3008{
3009	return edid_cea_modes[video_code].picture_aspect_ratio;
3010}
3011EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
3012
3013/*
3014 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3015 * specific block).
3016 *
3017 * It's almost like cea_mode_alternate_clock(), we just need to add an
3018 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
3019 * one.
3020 */
3021static unsigned int
3022hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3023{
3024	if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
3025		return hdmi_mode->clock;
3026
3027	return cea_mode_alternate_clock(hdmi_mode);
3028}
3029
3030static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3031					      unsigned int clock_tolerance)
3032{
3033	u8 vic;
3034
3035	if (!to_match->clock)
3036		return 0;
3037
3038	for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3039		const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3040		unsigned int clock1, clock2;
3041
3042		/* Make sure to also match alternate clocks */
3043		clock1 = hdmi_mode->clock;
3044		clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3045
3046		if (abs(to_match->clock - clock1) > clock_tolerance &&
3047		    abs(to_match->clock - clock2) > clock_tolerance)
3048			continue;
3049
3050		if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
3051			return vic;
3052	}
3053
3054	return 0;
3055}
3056
3057/*
3058 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3059 * @to_match: display mode
3060 *
3061 * An HDMI mode is one defined in the HDMI vendor specific block.
3062 *
3063 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3064 */
3065static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3066{
3067	u8 vic;
3068
3069	if (!to_match->clock)
3070		return 0;
3071
3072	for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3073		const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3074		unsigned int clock1, clock2;
3075
3076		/* Make sure to also match alternate clocks */
3077		clock1 = hdmi_mode->clock;
3078		clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3079
3080		if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3081		     KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3082		    drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
3083			return vic;
3084	}
3085	return 0;
3086}
3087
3088static bool drm_valid_hdmi_vic(u8 vic)
3089{
3090	return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3091}
3092
3093static int
3094add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3095{
3096	struct drm_device *dev = connector->dev;
3097	struct drm_display_mode *mode, *tmp;
3098	LIST_HEAD(list);
3099	int modes = 0;
3100
3101	/* Don't add CEA modes if the CEA extension block is missing */
3102	if (!drm_find_cea_extension(edid))
3103		return 0;
3104
3105	/*
3106	 * Go through all probed modes and create a new mode
3107	 * with the alternate clock for certain CEA modes.
3108	 */
3109	list_for_each_entry(mode, &connector->probed_modes, head) {
3110		const struct drm_display_mode *cea_mode = NULL;
3111		struct drm_display_mode *newmode;
3112		u8 vic = drm_match_cea_mode(mode);
3113		unsigned int clock1, clock2;
3114
3115		if (drm_valid_cea_vic(vic)) {
3116			cea_mode = &edid_cea_modes[vic];
3117			clock2 = cea_mode_alternate_clock(cea_mode);
3118		} else {
3119			vic = drm_match_hdmi_mode(mode);
3120			if (drm_valid_hdmi_vic(vic)) {
3121				cea_mode = &edid_4k_modes[vic];
3122				clock2 = hdmi_mode_alternate_clock(cea_mode);
3123			}
3124		}
3125
3126		if (!cea_mode)
3127			continue;
3128
3129		clock1 = cea_mode->clock;
3130
3131		if (clock1 == clock2)
3132			continue;
3133
3134		if (mode->clock != clock1 && mode->clock != clock2)
3135			continue;
3136
3137		newmode = drm_mode_duplicate(dev, cea_mode);
3138		if (!newmode)
3139			continue;
3140
3141		/* Carry over the stereo flags */
3142		newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3143
3144		/*
3145		 * The current mode could be either variant. Make
3146		 * sure to pick the "other" clock for the new mode.
3147		 */
3148		if (mode->clock != clock1)
3149			newmode->clock = clock1;
3150		else
3151			newmode->clock = clock2;
3152
3153		list_add_tail(&newmode->head, &list);
3154	}
3155
3156	list_for_each_entry_safe(mode, tmp, &list, head) {
3157		list_del(&mode->head);
3158		drm_mode_probed_add(connector, mode);
3159		modes++;
3160	}
3161
3162	return modes;
3163}
3164
3165static u8 svd_to_vic(u8 svd)
3166{
3167	/* 0-6 bit vic, 7th bit native mode indicator */
3168	if ((svd >= 1 &&  svd <= 64) || (svd >= 129 && svd <= 192))
3169		return svd & 127;
3170
3171	return svd;
3172}
3173
3174static struct drm_display_mode *
3175drm_display_mode_from_vic_index(struct drm_connector *connector,
3176				const u8 *video_db, u8 video_len,
3177				u8 video_index)
3178{
3179	struct drm_device *dev = connector->dev;
3180	struct drm_display_mode *newmode;
3181	u8 vic;
3182
3183	if (video_db == NULL || video_index >= video_len)
3184		return NULL;
3185
3186	/* CEA modes are numbered 1..127 */
3187	vic = svd_to_vic(video_db[video_index]);
3188	if (!drm_valid_cea_vic(vic))
3189		return NULL;
3190
3191	newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3192	if (!newmode)
3193		return NULL;
3194
3195	newmode->vrefresh = 0;
3196
3197	return newmode;
3198}
3199
3200/*
3201 * do_y420vdb_modes - Parse YCBCR 420 only modes
3202 * @connector: connector corresponding to the HDMI sink
3203 * @svds: start of the data block of CEA YCBCR 420 VDB
3204 * @len: length of the CEA YCBCR 420 VDB
3205 *
3206 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3207 * which contains modes which can be supported in YCBCR 420
3208 * output format only.
3209 */
3210static int do_y420vdb_modes(struct drm_connector *connector,
3211			    const u8 *svds, u8 svds_len)
3212{
3213	int modes = 0, i;
3214	struct drm_device *dev = connector->dev;
3215	struct drm_display_info *info = &connector->display_info;
3216	struct drm_hdmi_info *hdmi = &info->hdmi;
3217
3218	for (i = 0; i < svds_len; i++) {
3219		u8 vic = svd_to_vic(svds[i]);
3220		struct drm_display_mode *newmode;
3221
3222		if (!drm_valid_cea_vic(vic))
3223			continue;
3224
3225		newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3226		if (!newmode)
3227			break;
3228		bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3229		drm_mode_probed_add(connector, newmode);
3230		modes++;
3231	}
3232
3233	if (modes > 0)
3234		info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3235	return modes;
3236}
3237
3238/*
3239 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3240 * @connector: connector corresponding to the HDMI sink
3241 * @vic: CEA vic for the video mode to be added in the map
3242 *
3243 * Makes an entry for a videomode in the YCBCR 420 bitmap
3244 */
3245static void
3246drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3247{
3248	u8 vic = svd_to_vic(svd);
3249	struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3250
3251	if (!drm_valid_cea_vic(vic))
3252		return;
3253
3254	bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3255}
3256
3257static int
3258do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3259{
3260	int i, modes = 0;
3261	struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3262
3263	for (i = 0; i < len; i++) {
3264		struct drm_display_mode *mode;
3265		mode = drm_display_mode_from_vic_index(connector, db, len, i);
3266		if (mode) {
3267			/*
3268			 * YCBCR420 capability block contains a bitmap which
3269			 * gives the index of CEA modes from CEA VDB, which
3270			 * can support YCBCR 420 sampling output also (apart
3271			 * from RGB/YCBCR444 etc).
3272			 * For example, if the bit 0 in bitmap is set,
3273			 * first mode in VDB can support YCBCR420 output too.
3274			 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3275			 */
3276			if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3277				drm_add_cmdb_modes(connector, db[i]);
3278
3279			drm_mode_probed_add(connector, mode);
3280			modes++;
3281		}
3282	}
3283
3284	return modes;
3285}
3286
3287struct stereo_mandatory_mode {
3288	int width, height, vrefresh;
3289	unsigned int flags;
3290};
3291
3292static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3293	{ 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3294	{ 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3295	{ 1920, 1080, 50,
3296	  DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3297	{ 1920, 1080, 60,
3298	  DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3299	{ 1280, 720,  50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3300	{ 1280, 720,  50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3301	{ 1280, 720,  60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3302	{ 1280, 720,  60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3303};
3304
3305static bool
3306stereo_match_mandatory(const struct drm_display_mode *mode,
3307		       const struct stereo_mandatory_mode *stereo_mode)
3308{
3309	unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3310
3311	return mode->hdisplay == stereo_mode->width &&
3312	       mode->vdisplay == stereo_mode->height &&
3313	       interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3314	       drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3315}
3316
3317static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3318{
3319	struct drm_device *dev = connector->dev;
3320	const struct drm_display_mode *mode;
3321	struct list_head stereo_modes;
3322	int modes = 0, i;
3323
3324	INIT_LIST_HEAD(&stereo_modes);
3325
3326	list_for_each_entry(mode, &connector->probed_modes, head) {
3327		for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3328			const struct stereo_mandatory_mode *mandatory;
3329			struct drm_display_mode *new_mode;
3330
3331			if (!stereo_match_mandatory(mode,
3332						    &stereo_mandatory_modes[i]))
3333				continue;
3334
3335			mandatory = &stereo_mandatory_modes[i];
3336			new_mode = drm_mode_duplicate(dev, mode);
3337			if (!new_mode)
3338				continue;
3339
3340			new_mode->flags |= mandatory->flags;
3341			list_add_tail(&new_mode->head, &stereo_modes);
3342			modes++;
3343		}
3344	}
3345
3346	list_splice_tail(&stereo_modes, &connector->probed_modes);
3347
3348	return modes;
3349}
3350
3351static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3352{
3353	struct drm_device *dev = connector->dev;
3354	struct drm_display_mode *newmode;
3355
3356	if (!drm_valid_hdmi_vic(vic)) {
3357		DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3358		return 0;
3359	}
3360
3361	newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3362	if (!newmode)
3363		return 0;
3364
3365	drm_mode_probed_add(connector, newmode);
3366
3367	return 1;
3368}
3369
3370static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3371			       const u8 *video_db, u8 video_len, u8 video_index)
3372{
3373	struct drm_display_mode *newmode;
3374	int modes = 0;
3375
3376	if (structure & (1 << 0)) {
3377		newmode = drm_display_mode_from_vic_index(connector, video_db,
3378							  video_len,
3379							  video_index);
3380		if (newmode) {
3381			newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3382			drm_mode_probed_add(connector, newmode);
3383			modes++;
3384		}
3385	}
3386	if (structure & (1 << 6)) {
3387		newmode = drm_display_mode_from_vic_index(connector, video_db,
3388							  video_len,
3389							  video_index);
3390		if (newmode) {
3391			newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3392			drm_mode_probed_add(connector, newmode);
3393			modes++;
3394		}
3395	}
3396	if (structure & (1 << 8)) {
3397		newmode = drm_display_mode_from_vic_index(connector, video_db,
3398							  video_len,
3399							  video_index);
3400		if (newmode) {
3401			newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3402			drm_mode_probed_add(connector, newmode);
3403			modes++;
3404		}
3405	}
3406
3407	return modes;
3408}
3409
3410/*
3411 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3412 * @connector: connector corresponding to the HDMI sink
3413 * @db: start of the CEA vendor specific block
3414 * @len: length of the CEA block payload, ie. one can access up to db[len]
3415 *
3416 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3417 * also adds the stereo 3d modes when applicable.
3418 */
3419static int
3420do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3421		   const u8 *video_db, u8 video_len)
3422{
3423	struct drm_display_info *info = &connector->display_info;
3424	int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3425	u8 vic_len, hdmi_3d_len = 0;
3426	u16 mask;
3427	u16 structure_all;
3428
3429	if (len < 8)
3430		goto out;
3431
3432	/* no HDMI_Video_Present */
3433	if (!(db[8] & (1 << 5)))
3434		goto out;
3435
3436	/* Latency_Fields_Present */
3437	if (db[8] & (1 << 7))
3438		offset += 2;
3439
3440	/* I_Latency_Fields_Present */
3441	if (db[8] & (1 << 6))
3442		offset += 2;
3443
3444	/* the declared length is not long enough for the 2 first bytes
3445	 * of additional video format capabilities */
3446	if (len < (8 + offset + 2))
3447		goto out;
3448
3449	/* 3D_Present */
3450	offset++;
3451	if (db[8 + offset] & (1 << 7)) {
3452		modes += add_hdmi_mandatory_stereo_modes(connector);
3453
3454		/* 3D_Multi_present */
3455		multi_present = (db[8 + offset] & 0x60) >> 5;
3456	}
3457
3458	offset++;
3459	vic_len = db[8 + offset] >> 5;
3460	hdmi_3d_len = db[8 + offset] & 0x1f;
3461
3462	for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3463		u8 vic;
3464
3465		vic = db[9 + offset + i];
3466		modes += add_hdmi_mode(connector, vic);
3467	}
3468	offset += 1 + vic_len;
3469
3470	if (multi_present == 1)
3471		multi_len = 2;
3472	else if (multi_present == 2)
3473		multi_len = 4;
3474	else
3475		multi_len = 0;
3476
3477	if (len < (8 + offset + hdmi_3d_len - 1))
3478		goto out;
3479
3480	if (hdmi_3d_len < multi_len)
3481		goto out;
3482
3483	if (multi_present == 1 || multi_present == 2) {
3484		/* 3D_Structure_ALL */
3485		structure_all = (db[8 + offset] << 8) | db[9 + offset];
3486
3487		/* check if 3D_MASK is present */
3488		if (multi_present == 2)
3489			mask = (db[10 + offset] << 8) | db[11 + offset];
3490		else
3491			mask = 0xffff;
3492
3493		for (i = 0; i < 16; i++) {
3494			if (mask & (1 << i))
3495				modes += add_3d_struct_modes(connector,
3496						structure_all,
3497						video_db,
3498						video_len, i);
3499		}
3500	}
3501
3502	offset += multi_len;
3503
3504	for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3505		int vic_index;
3506		struct drm_display_mode *newmode = NULL;
3507		unsigned int newflag = 0;
3508		bool detail_present;
3509
3510		detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3511
3512		if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3513			break;
3514
3515		/* 2D_VIC_order_X */
3516		vic_index = db[8 + offset + i] >> 4;
3517
3518		/* 3D_Structure_X */
3519		switch (db[8 + offset + i] & 0x0f) {
3520		case 0:
3521			newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3522			break;
3523		case 6:
3524			newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3525			break;
3526		case 8:
3527			/* 3D_Detail_X */
3528			if ((db[9 + offset + i] >> 4) == 1)
3529				newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3530			break;
3531		}
3532
3533		if (newflag != 0) {
3534			newmode = drm_display_mode_from_vic_index(connector,
3535								  video_db,
3536								  video_len,
3537								  vic_index);
3538
3539			if (newmode) {
3540				newmode->flags |= newflag;
3541				drm_mode_probed_add(connector, newmode);
3542				modes++;
3543			}
3544		}
3545
3546		if (detail_present)
3547			i++;
3548	}
3549
3550out:
3551	if (modes > 0)
3552		info->has_hdmi_infoframe = true;
3553	return modes;
3554}
3555
3556static int
3557cea_db_payload_len(const u8 *db)
3558{
3559	return db[0] & 0x1f;
3560}
3561
3562static int
3563cea_db_extended_tag(const u8 *db)
3564{
3565	return db[1];
3566}
3567
3568static int
3569cea_db_tag(const u8 *db)
3570{
3571	return db[0] >> 5;
3572}
3573
3574static int
3575cea_revision(const u8 *cea)
3576{
3577	return cea[1];
3578}
3579
3580static int
3581cea_db_offsets(const u8 *cea, int *start, int *end)
3582{
3583	/* Data block offset in CEA extension block */
3584	*start = 4;
3585	*end = cea[2];
3586	if (*end == 0)
3587		*end = 127;
3588	if (*end < 4 || *end > 127)
3589		return -ERANGE;
3590	return 0;
3591}
3592
3593static bool cea_db_is_hdmi_vsdb(const u8 *db)
3594{
3595	int hdmi_id;
3596
3597	if (cea_db_tag(db) != VENDOR_BLOCK)
3598		return false;
3599
3600	if (cea_db_payload_len(db) < 5)
3601		return false;
3602
3603	hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3604
3605	return hdmi_id == HDMI_IEEE_OUI;
3606}
3607
3608static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3609{
3610	unsigned int oui;
3611
3612	if (cea_db_tag(db) != VENDOR_BLOCK)
3613		return false;
3614
3615	if (cea_db_payload_len(db) < 7)
3616		return false;
3617
3618	oui = db[3] << 16 | db[2] << 8 | db[1];
3619
3620	return oui == HDMI_FORUM_IEEE_OUI;
3621}
3622
3623static bool cea_db_is_y420cmdb(const u8 *db)
3624{
3625	if (cea_db_tag(db) != USE_EXTENDED_TAG)
3626		return false;
3627
3628	if (!cea_db_payload_len(db))
3629		return false;
3630
3631	if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3632		return false;
3633
3634	return true;
3635}
3636
3637static bool cea_db_is_y420vdb(const u8 *db)
3638{
3639	if (cea_db_tag(db) != USE_EXTENDED_TAG)
3640		return false;
3641
3642	if (!cea_db_payload_len(db))
3643		return false;
3644
3645	if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3646		return false;
3647
3648	return true;
3649}
3650
3651#define for_each_cea_db(cea, i, start, end) \
3652	for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3653
3654static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3655				      const u8 *db)
3656{
3657	struct drm_display_info *info = &connector->display_info;
3658	struct drm_hdmi_info *hdmi = &info->hdmi;
3659	u8 map_len = cea_db_payload_len(db) - 1;
3660	u8 count;
3661	u64 map = 0;
3662
3663	if (map_len == 0) {
3664		/* All CEA modes support ycbcr420 sampling also.*/
3665		hdmi->y420_cmdb_map = U64_MAX;
3666		info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3667		return;
3668	}
3669
3670	/*
3671	 * This map indicates which of the existing CEA block modes
3672	 * from VDB can support YCBCR420 output too. So if bit=0 is
3673	 * set, first mode from VDB can support YCBCR420 output too.
3674	 * We will parse and keep this map, before parsing VDB itself
3675	 * to avoid going through the same block again and again.
3676	 *
3677	 * Spec is not clear about max possible size of this block.
3678	 * Clamping max bitmap block size at 8 bytes. Every byte can
3679	 * address 8 CEA modes, in this way this map can address
3680	 * 8*8 = first 64 SVDs.
3681	 */
3682	if (WARN_ON_ONCE(map_len > 8))
3683		map_len = 8;
3684
3685	for (count = 0; count < map_len; count++)
3686		map |= (u64)db[2 + count] << (8 * count);
3687
3688	if (map)
3689		info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3690
3691	hdmi->y420_cmdb_map = map;
3692}
3693
3694static int
3695add_cea_modes(struct drm_connector *connector, struct edid *edid)
3696{
3697	const u8 *cea = drm_find_cea_extension(edid);
3698	const u8 *db, *hdmi = NULL, *video = NULL;
3699	u8 dbl, hdmi_len, video_len = 0;
3700	int modes = 0;
3701
3702	if (cea && cea_revision(cea) >= 3) {
3703		int i, start, end;
3704
3705		if (cea_db_offsets(cea, &start, &end))
3706			return 0;
3707
3708		for_each_cea_db(cea, i, start, end) {
3709			db = &cea[i];
3710			dbl = cea_db_payload_len(db);
3711
3712			if (cea_db_tag(db) == VIDEO_BLOCK) {
3713				video = db + 1;
3714				video_len = dbl;
3715				modes += do_cea_modes(connector, video, dbl);
3716			} else if (cea_db_is_hdmi_vsdb(db)) {
3717				hdmi = db;
3718				hdmi_len = dbl;
3719			} else if (cea_db_is_y420vdb(db)) {
3720				const u8 *vdb420 = &db[2];
3721
3722				/* Add 4:2:0(only) modes present in EDID */
3723				modes += do_y420vdb_modes(connector,
3724							  vdb420,
3725							  dbl - 1);
3726			}
3727		}
3728	}
3729
3730	/*
3731	 * We parse the HDMI VSDB after having added the cea modes as we will
3732	 * be patching their flags when the sink supports stereo 3D.
3733	 */
3734	if (hdmi)
3735		modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3736					    video_len);
3737
3738	return modes;
3739}
3740
3741static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3742{
3743	const struct drm_display_mode *cea_mode;
3744	int clock1, clock2, clock;
3745	u8 vic;
3746	const char *type;
3747
3748	/*
3749	 * allow 5kHz clock difference either way to account for
3750	 * the 10kHz clock resolution limit of detailed timings.
3751	 */
3752	vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3753	if (drm_valid_cea_vic(vic)) {
3754		type = "CEA";
3755		cea_mode = &edid_cea_modes[vic];
3756		clock1 = cea_mode->clock;
3757		clock2 = cea_mode_alternate_clock(cea_mode);
3758	} else {
3759		vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3760		if (drm_valid_hdmi_vic(vic)) {
3761			type = "HDMI";
3762			cea_mode = &edid_4k_modes[vic];
3763			clock1 = cea_mode->clock;
3764			clock2 = hdmi_mode_alternate_clock(cea_mode);
3765		} else {
3766			return;
3767		}
3768	}
3769
3770	/* pick whichever is closest */
3771	if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3772		clock = clock1;
3773	else
3774		clock = clock2;
3775
3776	if (mode->clock == clock)
3777		return;
3778
3779	DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3780		  type, vic, mode->clock, clock);
3781	mode->clock = clock;
3782}
3783
3784static void
3785drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3786{
3787	u8 len = cea_db_payload_len(db);
3788
3789	if (len >= 6 && (db[6] & (1 << 7)))
3790		connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
3791	if (len >= 8) {
3792		connector->latency_present[0] = db[8] >> 7;
3793		connector->latency_present[1] = (db[8] >> 6) & 1;
3794	}
3795	if (len >= 9)
3796		connector->video_latency[0] = db[9];
3797	if (len >= 10)
3798		connector->audio_latency[0] = db[10];
3799	if (len >= 11)
3800		connector->video_latency[1] = db[11];
3801	if (len >= 12)
3802		connector->audio_latency[1] = db[12];
3803
3804	DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3805		      "video latency %d %d, "
3806		      "audio latency %d %d\n",
3807		      connector->latency_present[0],
3808		      connector->latency_present[1],
3809		      connector->video_latency[0],
3810		      connector->video_latency[1],
3811		      connector->audio_latency[0],
3812		      connector->audio_latency[1]);
3813}
3814
3815static void
3816monitor_name(struct detailed_timing *t, void *data)
3817{
3818	if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3819		*(u8 **)data = t->data.other_data.data.str.str;
3820}
3821
3822static int get_monitor_name(struct edid *edid, char name[13])
3823{
3824	char *edid_name = NULL;
3825	int mnl;
3826
3827	if (!edid || !name)
3828		return 0;
3829
3830	drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3831	for (mnl = 0; edid_name && mnl < 13; mnl++) {
3832		if (edid_name[mnl] == 0x0a)
3833			break;
3834
3835		name[mnl] = edid_name[mnl];
3836	}
3837
3838	return mnl;
3839}
3840
3841/**
3842 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3843 * @edid: monitor EDID information
3844 * @name: pointer to a character array to hold the name of the monitor
3845 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3846 *
3847 */
3848void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3849{
3850	int name_length;
3851	char buf[13];
3852	
3853	if (bufsize <= 0)
3854		return;
3855
3856	name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3857	memcpy(name, buf, name_length);
3858	name[name_length] = '\0';
3859}
3860EXPORT_SYMBOL(drm_edid_get_monitor_name);
3861
3862static void clear_eld(struct drm_connector *connector)
3863{
3864	memset(connector->eld, 0, sizeof(connector->eld));
3865
3866	connector->latency_present[0] = false;
3867	connector->latency_present[1] = false;
3868	connector->video_latency[0] = 0;
3869	connector->audio_latency[0] = 0;
3870	connector->video_latency[1] = 0;
3871	connector->audio_latency[1] = 0;
3872}
3873
3874/*
3875 * drm_edid_to_eld - build ELD from EDID
3876 * @connector: connector corresponding to the HDMI/DP sink
3877 * @edid: EDID to parse
3878 *
3879 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3880 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
3881 */
3882static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3883{
3884	uint8_t *eld = connector->eld;
3885	u8 *cea;
3886	u8 *db;
3887	int total_sad_count = 0;
3888	int mnl;
3889	int dbl;
3890
3891	clear_eld(connector);
3892
3893	if (!edid)
3894		return;
3895
3896	cea = drm_find_cea_extension(edid);
3897	if (!cea) {
3898		DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3899		return;
3900	}
3901
3902	mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
3903	DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
3904
3905	eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
3906	eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
3907
3908	eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
3909
3910	eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
3911	eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
3912	eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
3913	eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
3914
3915	if (cea_revision(cea) >= 3) {
3916		int i, start, end;
3917
3918		if (cea_db_offsets(cea, &start, &end)) {
3919			start = 0;
3920			end = 0;
3921		}
3922
3923		for_each_cea_db(cea, i, start, end) {
3924			db = &cea[i];
3925			dbl = cea_db_payload_len(db);
3926
3927			switch (cea_db_tag(db)) {
3928				int sad_count;
3929
3930			case AUDIO_BLOCK:
3931				/* Audio Data Block, contains SADs */
3932				sad_count = min(dbl / 3, 15 - total_sad_count);
3933				if (sad_count >= 1)
3934					memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
3935					       &db[1], sad_count * 3);
3936				total_sad_count += sad_count;
3937				break;
3938			case SPEAKER_BLOCK:
3939				/* Speaker Allocation Data Block */
3940				if (dbl >= 1)
3941					eld[DRM_ELD_SPEAKER] = db[1];
3942				break;
3943			case VENDOR_BLOCK:
3944				/* HDMI Vendor-Specific Data Block */
3945				if (cea_db_is_hdmi_vsdb(db))
3946					drm_parse_hdmi_vsdb_audio(connector, db);
3947				break;
3948			default:
3949				break;
3950			}
3951		}
3952	}
3953	eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
3954
3955	if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
3956	    connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3957		eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
3958	else
3959		eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
3960
3961	eld[DRM_ELD_BASELINE_ELD_LEN] =
3962		DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3963
3964	DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3965		      drm_eld_size(eld), total_sad_count);
3966}
3967
3968/**
3969 * drm_edid_to_sad - extracts SADs from EDID
3970 * @edid: EDID to parse
3971 * @sads: pointer that will be set to the extracted SADs
3972 *
3973 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3974 *
3975 * Note: The returned pointer needs to be freed using kfree().
3976 *
3977 * Return: The number of found SADs or negative number on error.
3978 */
3979int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3980{
3981	int count = 0;
3982	int i, start, end, dbl;
3983	u8 *cea;
3984
3985	cea = drm_find_cea_extension(edid);
3986	if (!cea) {
3987		DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3988		return -ENOENT;
3989	}
3990
3991	if (cea_revision(cea) < 3) {
3992		DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3993		return -ENOTSUPP;
3994	}
3995
3996	if (cea_db_offsets(cea, &start, &end)) {
3997		DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3998		return -EPROTO;
3999	}
4000
4001	for_each_cea_db(cea, i, start, end) {
4002		u8 *db = &cea[i];
4003
4004		if (cea_db_tag(db) == AUDIO_BLOCK) {
4005			int j;
4006			dbl = cea_db_payload_len(db);
4007
4008			count = dbl / 3; /* SAD is 3B */
4009			*sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4010			if (!*sads)
4011				return -ENOMEM;
4012			for (j = 0; j < count; j++) {
4013				u8 *sad = &db[1 + j * 3];
4014
4015				(*sads)[j].format = (sad[0] & 0x78) >> 3;
4016				(*sads)[j].channels = sad[0] & 0x7;
4017				(*sads)[j].freq = sad[1] & 0x7F;
4018				(*sads)[j].byte2 = sad[2];
4019			}
4020			break;
4021		}
4022	}
4023
4024	return count;
4025}
4026EXPORT_SYMBOL(drm_edid_to_sad);
4027
4028/**
4029 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4030 * @edid: EDID to parse
4031 * @sadb: pointer to the speaker block
4032 *
4033 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4034 *
4035 * Note: The returned pointer needs to be freed using kfree().
4036 *
4037 * Return: The number of found Speaker Allocation Blocks or negative number on
4038 * error.
4039 */
4040int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4041{
4042	int count = 0;
4043	int i, start, end, dbl;
4044	const u8 *cea;
4045
4046	cea = drm_find_cea_extension(edid);
4047	if (!cea) {
4048		DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4049		return -ENOENT;
4050	}
4051
4052	if (cea_revision(cea) < 3) {
4053		DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4054		return -ENOTSUPP;
4055	}
4056
4057	if (cea_db_offsets(cea, &start, &end)) {
4058		DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4059		return -EPROTO;
4060	}
4061
4062	for_each_cea_db(cea, i, start, end) {
4063		const u8 *db = &cea[i];
4064
4065		if (cea_db_tag(db) == SPEAKER_BLOCK) {
4066			dbl = cea_db_payload_len(db);
4067
4068			/* Speaker Allocation Data Block */
4069			if (dbl == 3) {
4070				*sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4071				if (!*sadb)
4072					return -ENOMEM;
4073				count = dbl;
4074				break;
4075			}
4076		}
4077	}
4078
4079	return count;
4080}
4081EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4082
4083/**
4084 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4085 * @connector: connector associated with the HDMI/DP sink
4086 * @mode: the display mode
4087 *
4088 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4089 * the sink doesn't support audio or video.
4090 */
4091int drm_av_sync_delay(struct drm_connector *connector,
4092		      const struct drm_display_mode *mode)
4093{
4094	int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4095	int a, v;
4096
4097	if (!connector->latency_present[0])
4098		return 0;
4099	if (!connector->latency_present[1])
4100		i = 0;
4101
4102	a = connector->audio_latency[i];
4103	v = connector->video_latency[i];
4104
4105	/*
4106	 * HDMI/DP sink doesn't support audio or video?
4107	 */
4108	if (a == 255 || v == 255)
4109		return 0;
4110
4111	/*
4112	 * Convert raw EDID values to millisecond.
4113	 * Treat unknown latency as 0ms.
4114	 */
4115	if (a)
4116		a = min(2 * (a - 1), 500);
4117	if (v)
4118		v = min(2 * (v - 1), 500);
4119
4120	return max(v - a, 0);
4121}
4122EXPORT_SYMBOL(drm_av_sync_delay);
4123
4124/**
4125 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4126 * @edid: monitor EDID information
4127 *
4128 * Parse the CEA extension according to CEA-861-B.
4129 *
4130 * Return: True if the monitor is HDMI, false if not or unknown.
4131 */
4132bool drm_detect_hdmi_monitor(struct edid *edid)
4133{
4134	u8 *edid_ext;
4135	int i;
4136	int start_offset, end_offset;
 
4137
4138	edid_ext = drm_find_cea_extension(edid);
4139	if (!edid_ext)
4140		return false;
4141
4142	if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4143		return false;
 
4144
4145	/*
4146	 * Because HDMI identifier is in Vendor Specific Block,
4147	 * search it from all data blocks of CEA extension.
4148	 */
4149	for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4150		if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4151			return true;
 
 
 
 
 
 
 
 
 
4152	}
4153
4154	return false;
 
4155}
4156EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4157
4158/**
4159 * drm_detect_monitor_audio - check monitor audio capability
4160 * @edid: EDID block to scan
4161 *
4162 * Monitor should have CEA extension block.
4163 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4164 * audio' only. If there is any audio extension block and supported
4165 * audio format, assume at least 'basic audio' support, even if 'basic
4166 * audio' is not defined in EDID.
4167 *
4168 * Return: True if the monitor supports audio, false otherwise.
4169 */
4170bool drm_detect_monitor_audio(struct edid *edid)
4171{
4172	u8 *edid_ext;
4173	int i, j;
4174	bool has_audio = false;
4175	int start_offset, end_offset;
4176
4177	edid_ext = drm_find_cea_extension(edid);
4178	if (!edid_ext)
4179		goto end;
4180
4181	has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4182
4183	if (has_audio) {
4184		DRM_DEBUG_KMS("Monitor has basic audio support\n");
4185		goto end;
4186	}
4187
4188	if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4189		goto end;
 
4190
4191	for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4192		if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
 
4193			has_audio = true;
4194			for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4195				DRM_DEBUG_KMS("CEA audio format %d\n",
4196					      (edid_ext[i + j] >> 3) & 0xf);
4197			goto end;
4198		}
4199	}
4200end:
4201	return has_audio;
4202}
4203EXPORT_SYMBOL(drm_detect_monitor_audio);
4204
4205/**
4206 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
4207 * @edid: EDID block to scan
4208 *
4209 * Check whether the monitor reports the RGB quantization range selection
4210 * as supported. The AVI infoframe can then be used to inform the monitor
4211 * which quantization range (full or limited) is used.
4212 *
4213 * Return: True if the RGB quantization range is selectable, false otherwise.
 
 
4214 */
4215bool drm_rgb_quant_range_selectable(struct edid *edid)
 
4216{
4217	u8 *edid_ext;
4218	int i, start, end;
4219
4220	edid_ext = drm_find_cea_extension(edid);
4221	if (!edid_ext)
4222		return false;
4223
4224	if (cea_db_offsets(edid_ext, &start, &end))
4225		return false;
4226
4227	for_each_cea_db(edid_ext, i, start, end) {
4228		if (cea_db_tag(&edid_ext[i]) == USE_EXTENDED_TAG &&
4229		    cea_db_payload_len(&edid_ext[i]) == 2 &&
4230		    cea_db_extended_tag(&edid_ext[i]) ==
4231			EXT_VIDEO_CAPABILITY_BLOCK) {
4232			DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
4233			return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
4234		}
4235	}
4236
4237	return false;
4238}
4239EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
4240
4241/**
4242 * drm_default_rgb_quant_range - default RGB quantization range
4243 * @mode: display mode
4244 *
4245 * Determine the default RGB quantization range for the mode,
4246 * as specified in CEA-861.
4247 *
4248 * Return: The default RGB quantization range for the mode
4249 */
4250enum hdmi_quantization_range
4251drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4252{
4253	/* All CEA modes other than VIC 1 use limited quantization range. */
4254	return drm_match_cea_mode(mode) > 1 ?
4255		HDMI_QUANTIZATION_RANGE_LIMITED :
4256		HDMI_QUANTIZATION_RANGE_FULL;
4257}
4258EXPORT_SYMBOL(drm_default_rgb_quant_range);
4259
4260static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4261					       const u8 *db)
4262{
4263	u8 dc_mask;
4264	struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4265
4266	dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4267	hdmi->y420_dc_modes |= dc_mask;
4268}
4269
4270static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4271				 const u8 *hf_vsdb)
4272{
4273	struct drm_display_info *display = &connector->display_info;
4274	struct drm_hdmi_info *hdmi = &display->hdmi;
4275
4276	display->has_hdmi_infoframe = true;
4277
4278	if (hf_vsdb[6] & 0x80) {
4279		hdmi->scdc.supported = true;
4280		if (hf_vsdb[6] & 0x40)
4281			hdmi->scdc.read_request = true;
4282	}
4283
4284	/*
4285	 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4286	 * And as per the spec, three factors confirm this:
4287	 * * Availability of a HF-VSDB block in EDID (check)
4288	 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4289	 * * SCDC support available (let's check)
4290	 * Lets check it out.
4291	 */
4292
4293	if (hf_vsdb[5]) {
4294		/* max clock is 5000 KHz times block value */
4295		u32 max_tmds_clock = hf_vsdb[5] * 5000;
4296		struct drm_scdc *scdc = &hdmi->scdc;
4297
4298		if (max_tmds_clock > 340000) {
4299			display->max_tmds_clock = max_tmds_clock;
4300			DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4301				display->max_tmds_clock);
4302		}
4303
4304		if (scdc->supported) {
4305			scdc->scrambling.supported = true;
4306
4307			/* Few sinks support scrambling for cloks < 340M */
4308			if ((hf_vsdb[6] & 0x8))
4309				scdc->scrambling.low_rates = true;
4310		}
4311	}
4312
4313	drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4314}
4315
4316static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4317					   const u8 *hdmi)
4318{
4319	struct drm_display_info *info = &connector->display_info;
4320	unsigned int dc_bpc = 0;
4321
4322	/* HDMI supports at least 8 bpc */
4323	info->bpc = 8;
4324
4325	if (cea_db_payload_len(hdmi) < 6)
4326		return;
4327
4328	if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4329		dc_bpc = 10;
4330		info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4331		DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4332			  connector->name);
4333	}
4334
4335	if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4336		dc_bpc = 12;
4337		info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4338		DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4339			  connector->name);
4340	}
4341
4342	if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4343		dc_bpc = 16;
4344		info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4345		DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4346			  connector->name);
4347	}
4348
4349	if (dc_bpc == 0) {
4350		DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4351			  connector->name);
4352		return;
4353	}
4354
4355	DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4356		  connector->name, dc_bpc);
4357	info->bpc = dc_bpc;
4358
4359	/*
4360	 * Deep color support mandates RGB444 support for all video
4361	 * modes and forbids YCRCB422 support for all video modes per
4362	 * HDMI 1.3 spec.
4363	 */
4364	info->color_formats = DRM_COLOR_FORMAT_RGB444;
4365
4366	/* YCRCB444 is optional according to spec. */
4367	if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4368		info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4369		DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4370			  connector->name);
4371	}
4372
4373	/*
4374	 * Spec says that if any deep color mode is supported at all,
4375	 * then deep color 36 bit must be supported.
4376	 */
4377	if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4378		DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4379			  connector->name);
4380	}
4381}
4382
4383static void
4384drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4385{
4386	struct drm_display_info *info = &connector->display_info;
4387	u8 len = cea_db_payload_len(db);
4388
4389	if (len >= 6)
4390		info->dvi_dual = db[6] & 1;
4391	if (len >= 7)
4392		info->max_tmds_clock = db[7] * 5000;
4393
4394	DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4395		      "max TMDS clock %d kHz\n",
4396		      info->dvi_dual,
4397		      info->max_tmds_clock);
4398
4399	drm_parse_hdmi_deep_color_info(connector, db);
4400}
4401
4402static void drm_parse_cea_ext(struct drm_connector *connector,
4403			      const struct edid *edid)
4404{
4405	struct drm_display_info *info = &connector->display_info;
4406	const u8 *edid_ext;
4407	int i, start, end;
4408
4409	edid_ext = drm_find_cea_extension(edid);
4410	if (!edid_ext)
4411		return;
4412
4413	info->cea_rev = edid_ext[1];
4414
4415	/* The existence of a CEA block should imply RGB support */
4416	info->color_formats = DRM_COLOR_FORMAT_RGB444;
4417	if (edid_ext[3] & EDID_CEA_YCRCB444)
4418		info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4419	if (edid_ext[3] & EDID_CEA_YCRCB422)
4420		info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4421
4422	if (cea_db_offsets(edid_ext, &start, &end))
4423		return;
4424
4425	for_each_cea_db(edid_ext, i, start, end) {
4426		const u8 *db = &edid_ext[i];
4427
4428		if (cea_db_is_hdmi_vsdb(db))
4429			drm_parse_hdmi_vsdb_video(connector, db);
4430		if (cea_db_is_hdmi_forum_vsdb(db))
4431			drm_parse_hdmi_forum_vsdb(connector, db);
4432		if (cea_db_is_y420cmdb(db))
4433			drm_parse_y420cmdb_bitmap(connector, db);
4434	}
4435}
4436
4437/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4438 * all of the values which would have been set from EDID
4439 */
4440void
4441drm_reset_display_info(struct drm_connector *connector)
4442{
4443	struct drm_display_info *info = &connector->display_info;
4444
4445	info->width_mm = 0;
4446	info->height_mm = 0;
4447
 
4448	info->bpc = 0;
4449	info->color_formats = 0;
4450	info->cea_rev = 0;
4451	info->max_tmds_clock = 0;
4452	info->dvi_dual = false;
4453	info->has_hdmi_infoframe = false;
4454	memset(&info->hdmi, 0, sizeof(info->hdmi));
4455
4456	info->non_desktop = 0;
4457}
4458EXPORT_SYMBOL_GPL(drm_reset_display_info);
4459
4460u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
4461{
4462	struct drm_display_info *info = &connector->display_info;
4463
4464	u32 quirks = edid_get_quirks(edid);
4465
4466	drm_reset_display_info(connector);
4467
4468	info->width_mm = edid->width_cm * 10;
4469	info->height_mm = edid->height_cm * 10;
4470
4471	info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4472
4473	DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4474
4475	if (edid->revision < 3)
4476		return quirks;
4477
4478	if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4479		return quirks;
4480
4481	drm_parse_cea_ext(connector, edid);
4482
4483	/*
4484	 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4485	 *
4486	 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4487	 * tells us to assume 8 bpc color depth if the EDID doesn't have
4488	 * extensions which tell otherwise.
4489	 */
4490	if ((info->bpc == 0) && (edid->revision < 4) &&
4491	    (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
4492		info->bpc = 8;
4493		DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4494			  connector->name, info->bpc);
4495	}
4496
4497	/* Only defined for 1.4 with digital displays */
4498	if (edid->revision < 4)
4499		return quirks;
4500
4501	switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4502	case DRM_EDID_DIGITAL_DEPTH_6:
4503		info->bpc = 6;
4504		break;
4505	case DRM_EDID_DIGITAL_DEPTH_8:
4506		info->bpc = 8;
4507		break;
4508	case DRM_EDID_DIGITAL_DEPTH_10:
4509		info->bpc = 10;
4510		break;
4511	case DRM_EDID_DIGITAL_DEPTH_12:
4512		info->bpc = 12;
4513		break;
4514	case DRM_EDID_DIGITAL_DEPTH_14:
4515		info->bpc = 14;
4516		break;
4517	case DRM_EDID_DIGITAL_DEPTH_16:
4518		info->bpc = 16;
4519		break;
4520	case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4521	default:
4522		info->bpc = 0;
4523		break;
4524	}
4525
4526	DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4527			  connector->name, info->bpc);
 
 
 
4528
4529	info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4530	if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4531		info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4532	if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4533		info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4534	return quirks;
4535}
4536EXPORT_SYMBOL_GPL(drm_add_display_info);
4537
4538static int validate_displayid(u8 *displayid, int length, int idx)
4539{
4540	int i;
4541	u8 csum = 0;
4542	struct displayid_hdr *base;
4543
4544	base = (struct displayid_hdr *)&displayid[idx];
4545
4546	DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4547		      base->rev, base->bytes, base->prod_id, base->ext_count);
4548
4549	if (base->bytes + 5 > length - idx)
4550		return -EINVAL;
4551	for (i = idx; i <= base->bytes + 5; i++) {
4552		csum += displayid[i];
4553	}
4554	if (csum) {
4555		DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
4556		return -EINVAL;
4557	}
4558	return 0;
4559}
4560
4561static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4562							    struct displayid_detailed_timings_1 *timings)
4563{
4564	struct drm_display_mode *mode;
4565	unsigned pixel_clock = (timings->pixel_clock[0] |
4566				(timings->pixel_clock[1] << 8) |
4567				(timings->pixel_clock[2] << 16));
4568	unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4569	unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4570	unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4571	unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4572	unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4573	unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4574	unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4575	unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4576	bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4577	bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4578	mode = drm_mode_create(dev);
4579	if (!mode)
4580		return NULL;
4581
4582	mode->clock = pixel_clock * 10;
4583	mode->hdisplay = hactive;
4584	mode->hsync_start = mode->hdisplay + hsync;
4585	mode->hsync_end = mode->hsync_start + hsync_width;
4586	mode->htotal = mode->hdisplay + hblank;
4587
4588	mode->vdisplay = vactive;
4589	mode->vsync_start = mode->vdisplay + vsync;
4590	mode->vsync_end = mode->vsync_start + vsync_width;
4591	mode->vtotal = mode->vdisplay + vblank;
4592
4593	mode->flags = 0;
4594	mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4595	mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4596	mode->type = DRM_MODE_TYPE_DRIVER;
4597
4598	if (timings->flags & 0x80)
4599		mode->type |= DRM_MODE_TYPE_PREFERRED;
4600	mode->vrefresh = drm_mode_vrefresh(mode);
4601	drm_mode_set_name(mode);
4602
4603	return mode;
4604}
4605
4606static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4607					  struct displayid_block *block)
4608{
4609	struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4610	int i;
4611	int num_timings;
4612	struct drm_display_mode *newmode;
4613	int num_modes = 0;
4614	/* blocks must be multiple of 20 bytes length */
4615	if (block->num_bytes % 20)
4616		return 0;
4617
4618	num_timings = block->num_bytes / 20;
4619	for (i = 0; i < num_timings; i++) {
4620		struct displayid_detailed_timings_1 *timings = &det->timings[i];
4621
4622		newmode = drm_mode_displayid_detailed(connector->dev, timings);
4623		if (!newmode)
4624			continue;
4625
4626		drm_mode_probed_add(connector, newmode);
4627		num_modes++;
4628	}
4629	return num_modes;
4630}
4631
4632static int add_displayid_detailed_modes(struct drm_connector *connector,
4633					struct edid *edid)
4634{
4635	u8 *displayid;
4636	int ret;
4637	int idx = 1;
4638	int length = EDID_LENGTH;
4639	struct displayid_block *block;
4640	int num_modes = 0;
4641
4642	displayid = drm_find_displayid_extension(edid);
4643	if (!displayid)
4644		return 0;
4645
4646	ret = validate_displayid(displayid, length, idx);
4647	if (ret)
4648		return 0;
4649
4650	idx += sizeof(struct displayid_hdr);
4651	while (block = (struct displayid_block *)&displayid[idx],
4652	       idx + sizeof(struct displayid_block) <= length &&
4653	       idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4654	       block->num_bytes > 0) {
4655		idx += block->num_bytes + sizeof(struct displayid_block);
4656		switch (block->tag) {
4657		case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4658			num_modes += add_displayid_detailed_1_modes(connector, block);
4659			break;
4660		}
4661	}
4662	return num_modes;
4663}
4664
4665/**
4666 * drm_add_edid_modes - add modes from EDID data, if available
4667 * @connector: connector we're probing
4668 * @edid: EDID data
4669 *
4670 * Add the specified modes to the connector's mode list. Also fills out the
4671 * &drm_display_info structure and ELD in @connector with any information which
4672 * can be derived from the edid.
4673 *
4674 * Return: The number of modes added or 0 if we couldn't find any.
4675 */
4676int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4677{
4678	int num_modes = 0;
4679	u32 quirks;
4680
4681	if (edid == NULL) {
4682		clear_eld(connector);
4683		return 0;
4684	}
4685	if (!drm_edid_is_valid(edid)) {
4686		clear_eld(connector);
4687		dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4688			 connector->name);
4689		return 0;
4690	}
4691
4692	drm_edid_to_eld(connector, edid);
4693
4694	/*
4695	 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4696	 * To avoid multiple parsing of same block, lets parse that map
4697	 * from sink info, before parsing CEA modes.
4698	 */
4699	quirks = drm_add_display_info(connector, edid);
4700
4701	/*
4702	 * EDID spec says modes should be preferred in this order:
4703	 * - preferred detailed mode
4704	 * - other detailed modes from base block
4705	 * - detailed modes from extension blocks
4706	 * - CVT 3-byte code modes
4707	 * - standard timing codes
4708	 * - established timing codes
4709	 * - modes inferred from GTF or CVT range information
4710	 *
4711	 * We get this pretty much right.
4712	 *
4713	 * XXX order for additional mode types in extension blocks?
4714	 */
4715	num_modes += add_detailed_modes(connector, edid, quirks);
4716	num_modes += add_cvt_modes(connector, edid);
4717	num_modes += add_standard_modes(connector, edid);
4718	num_modes += add_established_modes(connector, edid);
4719	num_modes += add_cea_modes(connector, edid);
4720	num_modes += add_alternate_cea_modes(connector, edid);
4721	num_modes += add_displayid_detailed_modes(connector, edid);
4722	if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4723		num_modes += add_inferred_modes(connector, edid);
4724
4725	if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4726		edid_fixup_preferred(connector, quirks);
4727
4728	if (quirks & EDID_QUIRK_FORCE_6BPC)
4729		connector->display_info.bpc = 6;
4730
4731	if (quirks & EDID_QUIRK_FORCE_8BPC)
4732		connector->display_info.bpc = 8;
4733
4734	if (quirks & EDID_QUIRK_FORCE_10BPC)
4735		connector->display_info.bpc = 10;
4736
4737	if (quirks & EDID_QUIRK_FORCE_12BPC)
4738		connector->display_info.bpc = 12;
4739
4740	return num_modes;
4741}
4742EXPORT_SYMBOL(drm_add_edid_modes);
4743
4744/**
4745 * drm_add_modes_noedid - add modes for the connectors without EDID
4746 * @connector: connector we're probing
4747 * @hdisplay: the horizontal display limit
4748 * @vdisplay: the vertical display limit
4749 *
4750 * Add the specified modes to the connector's mode list. Only when the
4751 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4752 *
4753 * Return: The number of modes added or 0 if we couldn't find any.
4754 */
4755int drm_add_modes_noedid(struct drm_connector *connector,
4756			int hdisplay, int vdisplay)
4757{
4758	int i, count, num_modes = 0;
4759	struct drm_display_mode *mode;
4760	struct drm_device *dev = connector->dev;
4761
4762	count = ARRAY_SIZE(drm_dmt_modes);
4763	if (hdisplay < 0)
4764		hdisplay = 0;
4765	if (vdisplay < 0)
4766		vdisplay = 0;
4767
4768	for (i = 0; i < count; i++) {
4769		const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4770		if (hdisplay && vdisplay) {
4771			/*
4772			 * Only when two are valid, they will be used to check
4773			 * whether the mode should be added to the mode list of
4774			 * the connector.
4775			 */
4776			if (ptr->hdisplay > hdisplay ||
4777					ptr->vdisplay > vdisplay)
4778				continue;
4779		}
4780		if (drm_mode_vrefresh(ptr) > 61)
4781			continue;
4782		mode = drm_mode_duplicate(dev, ptr);
4783		if (mode) {
4784			drm_mode_probed_add(connector, mode);
4785			num_modes++;
4786		}
4787	}
4788	return num_modes;
4789}
4790EXPORT_SYMBOL(drm_add_modes_noedid);
4791
4792/**
4793 * drm_set_preferred_mode - Sets the preferred mode of a connector
4794 * @connector: connector whose mode list should be processed
4795 * @hpref: horizontal resolution of preferred mode
4796 * @vpref: vertical resolution of preferred mode
4797 *
4798 * Marks a mode as preferred if it matches the resolution specified by @hpref
4799 * and @vpref.
4800 */
4801void drm_set_preferred_mode(struct drm_connector *connector,
4802			   int hpref, int vpref)
4803{
4804	struct drm_display_mode *mode;
4805
4806	list_for_each_entry(mode, &connector->probed_modes, head) {
4807		if (mode->hdisplay == hpref &&
4808		    mode->vdisplay == vpref)
4809			mode->type |= DRM_MODE_TYPE_PREFERRED;
4810	}
4811}
4812EXPORT_SYMBOL(drm_set_preferred_mode);
4813
4814/**
4815 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4816 *                                              data from a DRM display mode
4817 * @frame: HDMI AVI infoframe
4818 * @mode: DRM display mode
4819 * @is_hdmi2_sink: Sink is HDMI 2.0 compliant
4820 *
4821 * Return: 0 on success or a negative error code on failure.
4822 */
4823int
4824drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4825					 const struct drm_display_mode *mode,
4826					 bool is_hdmi2_sink)
4827{
4828	int err;
4829
4830	if (!frame || !mode)
4831		return -EINVAL;
4832
4833	err = hdmi_avi_infoframe_init(frame);
4834	if (err < 0)
4835		return err;
4836
4837	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4838		frame->pixel_repeat = 1;
4839
4840	frame->video_code = drm_match_cea_mode(mode);
4841
4842	/*
4843	 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
4844	 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
4845	 * have to make sure we dont break HDMI 1.4 sinks.
4846	 */
4847	if (!is_hdmi2_sink && frame->video_code > 64)
4848		frame->video_code = 0;
4849
4850	/*
4851	 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
4852	 * we should send its VIC in vendor infoframes, else send the
4853	 * VIC in AVI infoframes. Lets check if this mode is present in
4854	 * HDMI 1.4b 4K modes
4855	 */
4856	if (frame->video_code) {
4857		u8 vendor_if_vic = drm_match_hdmi_mode(mode);
4858		bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
4859
4860		if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
4861			frame->video_code = 0;
4862	}
4863
4864	frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4865
4866	/*
4867	 * Populate picture aspect ratio from either
4868	 * user input (if specified) or from the CEA mode list.
4869	 */
4870	if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4871		mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4872		frame->picture_aspect = mode->picture_aspect_ratio;
4873	else if (frame->video_code > 0)
4874		frame->picture_aspect = drm_get_cea_aspect_ratio(
4875						frame->video_code);
4876
4877	frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4878	frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4879
4880	return 0;
4881}
4882EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4883
4884/**
4885 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
4886 *                                        quantization range information
4887 * @frame: HDMI AVI infoframe
4888 * @mode: DRM display mode
4889 * @rgb_quant_range: RGB quantization range (Q)
4890 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS)
4891 * @is_hdmi2_sink: HDMI 2.0 sink, which has different default recommendations
4892 *
4893 * Note that @is_hdmi2_sink can be derived by looking at the
4894 * &drm_scdc.supported flag stored in &drm_hdmi_info.scdc,
4895 * &drm_display_info.hdmi, which can be found in &drm_connector.display_info.
4896 */
4897void
4898drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
4899				   const struct drm_display_mode *mode,
4900				   enum hdmi_quantization_range rgb_quant_range,
4901				   bool rgb_quant_range_selectable,
4902				   bool is_hdmi2_sink)
4903{
4904	/*
4905	 * CEA-861:
4906	 * "A Source shall not send a non-zero Q value that does not correspond
4907	 *  to the default RGB Quantization Range for the transmitted Picture
4908	 *  unless the Sink indicates support for the Q bit in a Video
4909	 *  Capabilities Data Block."
4910	 *
4911	 * HDMI 2.0 recommends sending non-zero Q when it does match the
4912	 * default RGB quantization range for the mode, even when QS=0.
4913	 */
4914	if (rgb_quant_range_selectable ||
4915	    rgb_quant_range == drm_default_rgb_quant_range(mode))
4916		frame->quantization_range = rgb_quant_range;
4917	else
4918		frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
4919
4920	/*
4921	 * CEA-861-F:
4922	 * "When transmitting any RGB colorimetry, the Source should set the
4923	 *  YQ-field to match the RGB Quantization Range being transmitted
4924	 *  (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
4925	 *  set YQ=1) and the Sink shall ignore the YQ-field."
4926	 *
4927	 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
4928	 * by non-zero YQ when receiving RGB. There doesn't seem to be any
4929	 * good way to tell which version of CEA-861 the sink supports, so
4930	 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
4931	 * on on CEA-861-F.
4932	 */
4933	if (!is_hdmi2_sink ||
4934	    rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
4935		frame->ycc_quantization_range =
4936			HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
4937	else
4938		frame->ycc_quantization_range =
4939			HDMI_YCC_QUANTIZATION_RANGE_FULL;
4940}
4941EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
4942
4943static enum hdmi_3d_structure
4944s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4945{
4946	u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4947
4948	switch (layout) {
4949	case DRM_MODE_FLAG_3D_FRAME_PACKING:
4950		return HDMI_3D_STRUCTURE_FRAME_PACKING;
4951	case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4952		return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4953	case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4954		return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4955	case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4956		return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4957	case DRM_MODE_FLAG_3D_L_DEPTH:
4958		return HDMI_3D_STRUCTURE_L_DEPTH;
4959	case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4960		return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4961	case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4962		return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4963	case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4964		return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4965	default:
4966		return HDMI_3D_STRUCTURE_INVALID;
4967	}
4968}
4969
4970/**
4971 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4972 * data from a DRM display mode
4973 * @frame: HDMI vendor infoframe
4974 * @connector: the connector
4975 * @mode: DRM display mode
4976 *
4977 * Note that there's is a need to send HDMI vendor infoframes only when using a
4978 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4979 * function will return -EINVAL, error that can be safely ignored.
4980 *
4981 * Return: 0 on success or a negative error code on failure.
4982 */
4983int
4984drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
4985					    struct drm_connector *connector,
4986					    const struct drm_display_mode *mode)
4987{
4988	/*
4989	 * FIXME: sil-sii8620 doesn't have a connector around when
4990	 * we need one, so we have to be prepared for a NULL connector.
4991	 */
4992	bool has_hdmi_infoframe = connector ?
4993		connector->display_info.has_hdmi_infoframe : false;
4994	int err;
4995	u32 s3d_flags;
4996	u8 vic;
4997
4998	if (!frame || !mode)
4999		return -EINVAL;
5000
5001	if (!has_hdmi_infoframe)
5002		return -EINVAL;
5003
5004	vic = drm_match_hdmi_mode(mode);
5005	s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
5006
5007	/*
5008	 * Even if it's not absolutely necessary to send the infoframe
5009	 * (ie.vic==0 and s3d_struct==0) we will still send it if we
5010	 * know that the sink can handle it. This is based on a
5011	 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5012	 * have trouble realizing that they shuld switch from 3D to 2D
5013	 * mode if the source simply stops sending the infoframe when
5014	 * it wants to switch from 3D to 2D.
5015	 */
5016
5017	if (vic && s3d_flags)
5018		return -EINVAL;
5019
5020	err = hdmi_vendor_infoframe_init(frame);
5021	if (err < 0)
5022		return err;
5023
5024	frame->vic = vic;
5025	frame->s3d_struct = s3d_structure_from_display_mode(mode);
5026
5027	return 0;
5028}
5029EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
5030
5031static int drm_parse_tiled_block(struct drm_connector *connector,
5032				 struct displayid_block *block)
5033{
5034	struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5035	u16 w, h;
5036	u8 tile_v_loc, tile_h_loc;
5037	u8 num_v_tile, num_h_tile;
5038	struct drm_tile_group *tg;
5039
5040	w = tile->tile_size[0] | tile->tile_size[1] << 8;
5041	h = tile->tile_size[2] | tile->tile_size[3] << 8;
5042
5043	num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5044	num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5045	tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5046	tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5047
5048	connector->has_tile = true;
5049	if (tile->tile_cap & 0x80)
5050		connector->tile_is_single_monitor = true;
5051
5052	connector->num_h_tile = num_h_tile + 1;
5053	connector->num_v_tile = num_v_tile + 1;
5054	connector->tile_h_loc = tile_h_loc;
5055	connector->tile_v_loc = tile_v_loc;
5056	connector->tile_h_size = w + 1;
5057	connector->tile_v_size = h + 1;
5058
5059	DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5060	DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5061	DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5062		      num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5063	DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5064
5065	tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5066	if (!tg) {
5067		tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5068	}
5069	if (!tg)
5070		return -ENOMEM;
5071
5072	if (connector->tile_group != tg) {
5073		/* if we haven't got a pointer,
5074		   take the reference, drop ref to old tile group */
5075		if (connector->tile_group) {
5076			drm_mode_put_tile_group(connector->dev, connector->tile_group);
5077		}
5078		connector->tile_group = tg;
5079	} else
5080		/* if same tile group, then release the ref we just took. */
5081		drm_mode_put_tile_group(connector->dev, tg);
5082	return 0;
5083}
5084
5085static int drm_parse_display_id(struct drm_connector *connector,
5086				u8 *displayid, int length,
5087				bool is_edid_extension)
5088{
5089	/* if this is an EDID extension the first byte will be 0x70 */
5090	int idx = 0;
5091	struct displayid_block *block;
5092	int ret;
5093
5094	if (is_edid_extension)
5095		idx = 1;
5096
5097	ret = validate_displayid(displayid, length, idx);
5098	if (ret)
5099		return ret;
5100
5101	idx += sizeof(struct displayid_hdr);
5102	while (block = (struct displayid_block *)&displayid[idx],
5103	       idx + sizeof(struct displayid_block) <= length &&
5104	       idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
5105	       block->num_bytes > 0) {
5106		idx += block->num_bytes + sizeof(struct displayid_block);
5107		DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5108			      block->tag, block->rev, block->num_bytes);
5109
5110		switch (block->tag) {
5111		case DATA_BLOCK_TILED_DISPLAY:
5112			ret = drm_parse_tiled_block(connector, block);
5113			if (ret)
5114				return ret;
5115			break;
5116		case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5117			/* handled in mode gathering code. */
5118			break;
5119		default:
5120			DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5121			break;
5122		}
5123	}
5124	return 0;
5125}
5126
5127static void drm_get_displayid(struct drm_connector *connector,
5128			      struct edid *edid)
5129{
5130	void *displayid = NULL;
5131	int ret;
5132	connector->has_tile = false;
5133	displayid = drm_find_displayid_extension(edid);
5134	if (!displayid) {
5135		/* drop reference to any tile group we had */
5136		goto out_drop_ref;
5137	}
5138
5139	ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5140	if (ret < 0)
5141		goto out_drop_ref;
5142	if (!connector->has_tile)
5143		goto out_drop_ref;
5144	return;
5145out_drop_ref:
5146	if (connector->tile_group) {
5147		drm_mode_put_tile_group(connector->dev, connector->tile_group);
5148		connector->tile_group = NULL;
5149	}
5150	return;
5151}