Loading...
1/*
2 * Copyright (C) 2002 Motorola GSG-China
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
17 * USA.
18 *
19 * Author:
20 * Darius Augulis, Teltonika Inc.
21 *
22 * Desc.:
23 * Implementation of I2C Adapter/Algorithm Driver
24 * for I2C Bus integrated in Freescale i.MX/MXC processors
25 *
26 * Derived from Motorola GSG China I2C example driver
27 *
28 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
29 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
30 * Copyright (C) 2007 RightHand Technologies, Inc.
31 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
32 *
33 */
34
35/** Includes *******************************************************************
36*******************************************************************************/
37
38#include <linux/init.h>
39#include <linux/kernel.h>
40#include <linux/module.h>
41#include <linux/errno.h>
42#include <linux/err.h>
43#include <linux/interrupt.h>
44#include <linux/delay.h>
45#include <linux/i2c.h>
46#include <linux/io.h>
47#include <linux/sched.h>
48#include <linux/platform_device.h>
49#include <linux/clk.h>
50#include <linux/slab.h>
51
52#include <mach/irqs.h>
53#include <mach/hardware.h>
54#include <mach/i2c.h>
55
56/** Defines ********************************************************************
57*******************************************************************************/
58
59/* This will be the driver name the kernel reports */
60#define DRIVER_NAME "imx-i2c"
61
62/* Default value */
63#define IMX_I2C_BIT_RATE 100000 /* 100kHz */
64
65/* IMX I2C registers */
66#define IMX_I2C_IADR 0x00 /* i2c slave address */
67#define IMX_I2C_IFDR 0x04 /* i2c frequency divider */
68#define IMX_I2C_I2CR 0x08 /* i2c control */
69#define IMX_I2C_I2SR 0x0C /* i2c status */
70#define IMX_I2C_I2DR 0x10 /* i2c transfer data */
71
72/* Bits of IMX I2C registers */
73#define I2SR_RXAK 0x01
74#define I2SR_IIF 0x02
75#define I2SR_SRW 0x04
76#define I2SR_IAL 0x10
77#define I2SR_IBB 0x20
78#define I2SR_IAAS 0x40
79#define I2SR_ICF 0x80
80#define I2CR_RSTA 0x04
81#define I2CR_TXAK 0x08
82#define I2CR_MTX 0x10
83#define I2CR_MSTA 0x20
84#define I2CR_IIEN 0x40
85#define I2CR_IEN 0x80
86
87/** Variables ******************************************************************
88*******************************************************************************/
89
90/*
91 * sorted list of clock divider, register value pairs
92 * taken from table 26-5, p.26-9, Freescale i.MX
93 * Integrated Portable System Processor Reference Manual
94 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
95 *
96 * Duplicated divider values removed from list
97 */
98
99static u16 __initdata i2c_clk_div[50][2] = {
100 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
101 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
102 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
103 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
104 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
105 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
106 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
107 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
108 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
109 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
110 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
111 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
112 { 3072, 0x1E }, { 3840, 0x1F }
113};
114
115struct imx_i2c_struct {
116 struct i2c_adapter adapter;
117 struct resource *res;
118 struct clk *clk;
119 void __iomem *base;
120 int irq;
121 wait_queue_head_t queue;
122 unsigned long i2csr;
123 unsigned int disable_delay;
124 int stopped;
125 unsigned int ifdr; /* IMX_I2C_IFDR */
126};
127
128/** Functions for IMX I2C adapter driver ***************************************
129*******************************************************************************/
130
131static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
132{
133 unsigned long orig_jiffies = jiffies;
134 unsigned int temp;
135
136 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
137
138 while (1) {
139 temp = readb(i2c_imx->base + IMX_I2C_I2SR);
140 if (for_busy && (temp & I2SR_IBB))
141 break;
142 if (!for_busy && !(temp & I2SR_IBB))
143 break;
144 if (signal_pending(current)) {
145 dev_dbg(&i2c_imx->adapter.dev,
146 "<%s> I2C Interrupted\n", __func__);
147 return -EINTR;
148 }
149 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
150 dev_dbg(&i2c_imx->adapter.dev,
151 "<%s> I2C bus is busy\n", __func__);
152 return -ETIMEDOUT;
153 }
154 schedule();
155 }
156
157 return 0;
158}
159
160static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
161{
162 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
163
164 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
165 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
166 return -ETIMEDOUT;
167 }
168 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
169 i2c_imx->i2csr = 0;
170 return 0;
171}
172
173static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
174{
175 if (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_RXAK) {
176 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
177 return -EIO; /* No ACK */
178 }
179
180 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
181 return 0;
182}
183
184static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
185{
186 unsigned int temp = 0;
187 int result;
188
189 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
190
191 clk_enable(i2c_imx->clk);
192 writeb(i2c_imx->ifdr, i2c_imx->base + IMX_I2C_IFDR);
193 /* Enable I2C controller */
194 writeb(0, i2c_imx->base + IMX_I2C_I2SR);
195 writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR);
196
197 /* Wait controller to be stable */
198 udelay(50);
199
200 /* Start I2C transaction */
201 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
202 temp |= I2CR_MSTA;
203 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
204 result = i2c_imx_bus_busy(i2c_imx, 1);
205 if (result)
206 return result;
207 i2c_imx->stopped = 0;
208
209 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
210 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
211 return result;
212}
213
214static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
215{
216 unsigned int temp = 0;
217
218 if (!i2c_imx->stopped) {
219 /* Stop I2C transaction */
220 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
221 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
222 temp &= ~(I2CR_MSTA | I2CR_MTX);
223 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
224 }
225 if (cpu_is_mx1()) {
226 /*
227 * This delay caused by an i.MXL hardware bug.
228 * If no (or too short) delay, no "STOP" bit will be generated.
229 */
230 udelay(i2c_imx->disable_delay);
231 }
232
233 if (!i2c_imx->stopped) {
234 i2c_imx_bus_busy(i2c_imx, 0);
235 i2c_imx->stopped = 1;
236 }
237
238 /* Disable I2C controller */
239 writeb(0, i2c_imx->base + IMX_I2C_I2CR);
240 clk_disable(i2c_imx->clk);
241}
242
243static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
244 unsigned int rate)
245{
246 unsigned int i2c_clk_rate;
247 unsigned int div;
248 int i;
249
250 /* Divider value calculation */
251 i2c_clk_rate = clk_get_rate(i2c_imx->clk);
252 div = (i2c_clk_rate + rate - 1) / rate;
253 if (div < i2c_clk_div[0][0])
254 i = 0;
255 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
256 i = ARRAY_SIZE(i2c_clk_div) - 1;
257 else
258 for (i = 0; i2c_clk_div[i][0] < div; i++);
259
260 /* Store divider value */
261 i2c_imx->ifdr = i2c_clk_div[i][1];
262
263 /*
264 * There dummy delay is calculated.
265 * It should be about one I2C clock period long.
266 * This delay is used in I2C bus disable function
267 * to fix chip hardware bug.
268 */
269 i2c_imx->disable_delay = (500000U * i2c_clk_div[i][0]
270 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
271
272 /* dev_dbg() can't be used, because adapter is not yet registered */
273#ifdef CONFIG_I2C_DEBUG_BUS
274 printk(KERN_DEBUG "I2C: <%s> I2C_CLK=%d, REQ DIV=%d\n",
275 __func__, i2c_clk_rate, div);
276 printk(KERN_DEBUG "I2C: <%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
277 __func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
278#endif
279}
280
281static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
282{
283 struct imx_i2c_struct *i2c_imx = dev_id;
284 unsigned int temp;
285
286 temp = readb(i2c_imx->base + IMX_I2C_I2SR);
287 if (temp & I2SR_IIF) {
288 /* save status register */
289 i2c_imx->i2csr = temp;
290 temp &= ~I2SR_IIF;
291 writeb(temp, i2c_imx->base + IMX_I2C_I2SR);
292 wake_up(&i2c_imx->queue);
293 return IRQ_HANDLED;
294 }
295
296 return IRQ_NONE;
297}
298
299static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
300{
301 int i, result;
302
303 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
304 __func__, msgs->addr << 1);
305
306 /* write slave address */
307 writeb(msgs->addr << 1, i2c_imx->base + IMX_I2C_I2DR);
308 result = i2c_imx_trx_complete(i2c_imx);
309 if (result)
310 return result;
311 result = i2c_imx_acked(i2c_imx);
312 if (result)
313 return result;
314 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
315
316 /* write data */
317 for (i = 0; i < msgs->len; i++) {
318 dev_dbg(&i2c_imx->adapter.dev,
319 "<%s> write byte: B%d=0x%X\n",
320 __func__, i, msgs->buf[i]);
321 writeb(msgs->buf[i], i2c_imx->base + IMX_I2C_I2DR);
322 result = i2c_imx_trx_complete(i2c_imx);
323 if (result)
324 return result;
325 result = i2c_imx_acked(i2c_imx);
326 if (result)
327 return result;
328 }
329 return 0;
330}
331
332static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
333{
334 int i, result;
335 unsigned int temp;
336
337 dev_dbg(&i2c_imx->adapter.dev,
338 "<%s> write slave address: addr=0x%x\n",
339 __func__, (msgs->addr << 1) | 0x01);
340
341 /* write slave address */
342 writeb((msgs->addr << 1) | 0x01, i2c_imx->base + IMX_I2C_I2DR);
343 result = i2c_imx_trx_complete(i2c_imx);
344 if (result)
345 return result;
346 result = i2c_imx_acked(i2c_imx);
347 if (result)
348 return result;
349
350 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
351
352 /* setup bus to read data */
353 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
354 temp &= ~I2CR_MTX;
355 if (msgs->len - 1)
356 temp &= ~I2CR_TXAK;
357 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
358 readb(i2c_imx->base + IMX_I2C_I2DR); /* dummy read */
359
360 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
361
362 /* read data */
363 for (i = 0; i < msgs->len; i++) {
364 result = i2c_imx_trx_complete(i2c_imx);
365 if (result)
366 return result;
367 if (i == (msgs->len - 1)) {
368 /* It must generate STOP before read I2DR to prevent
369 controller from generating another clock cycle */
370 dev_dbg(&i2c_imx->adapter.dev,
371 "<%s> clear MSTA\n", __func__);
372 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
373 temp &= ~(I2CR_MSTA | I2CR_MTX);
374 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
375 i2c_imx_bus_busy(i2c_imx, 0);
376 i2c_imx->stopped = 1;
377 } else if (i == (msgs->len - 2)) {
378 dev_dbg(&i2c_imx->adapter.dev,
379 "<%s> set TXAK\n", __func__);
380 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
381 temp |= I2CR_TXAK;
382 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
383 }
384 msgs->buf[i] = readb(i2c_imx->base + IMX_I2C_I2DR);
385 dev_dbg(&i2c_imx->adapter.dev,
386 "<%s> read byte: B%d=0x%X\n",
387 __func__, i, msgs->buf[i]);
388 }
389 return 0;
390}
391
392static int i2c_imx_xfer(struct i2c_adapter *adapter,
393 struct i2c_msg *msgs, int num)
394{
395 unsigned int i, temp;
396 int result;
397 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
398
399 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
400
401 /* Start I2C transfer */
402 result = i2c_imx_start(i2c_imx);
403 if (result)
404 goto fail0;
405
406 /* read/write data */
407 for (i = 0; i < num; i++) {
408 if (i) {
409 dev_dbg(&i2c_imx->adapter.dev,
410 "<%s> repeated start\n", __func__);
411 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
412 temp |= I2CR_RSTA;
413 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
414 result = i2c_imx_bus_busy(i2c_imx, 1);
415 if (result)
416 goto fail0;
417 }
418 dev_dbg(&i2c_imx->adapter.dev,
419 "<%s> transfer message: %d\n", __func__, i);
420 /* write/read data */
421#ifdef CONFIG_I2C_DEBUG_BUS
422 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
423 dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, "
424 "MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__,
425 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
426 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
427 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
428 temp = readb(i2c_imx->base + IMX_I2C_I2SR);
429 dev_dbg(&i2c_imx->adapter.dev,
430 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, "
431 "IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__,
432 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
433 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
434 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
435 (temp & I2SR_RXAK ? 1 : 0));
436#endif
437 if (msgs[i].flags & I2C_M_RD)
438 result = i2c_imx_read(i2c_imx, &msgs[i]);
439 else
440 result = i2c_imx_write(i2c_imx, &msgs[i]);
441 if (result)
442 goto fail0;
443 }
444
445fail0:
446 /* Stop I2C transfer */
447 i2c_imx_stop(i2c_imx);
448
449 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
450 (result < 0) ? "error" : "success msg",
451 (result < 0) ? result : num);
452 return (result < 0) ? result : num;
453}
454
455static u32 i2c_imx_func(struct i2c_adapter *adapter)
456{
457 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
458}
459
460static struct i2c_algorithm i2c_imx_algo = {
461 .master_xfer = i2c_imx_xfer,
462 .functionality = i2c_imx_func,
463};
464
465static int __init i2c_imx_probe(struct platform_device *pdev)
466{
467 struct imx_i2c_struct *i2c_imx;
468 struct resource *res;
469 struct imxi2c_platform_data *pdata;
470 void __iomem *base;
471 resource_size_t res_size;
472 int irq;
473 int ret;
474
475 dev_dbg(&pdev->dev, "<%s>\n", __func__);
476
477 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
478 if (!res) {
479 dev_err(&pdev->dev, "can't get device resources\n");
480 return -ENOENT;
481 }
482 irq = platform_get_irq(pdev, 0);
483 if (irq < 0) {
484 dev_err(&pdev->dev, "can't get irq number\n");
485 return -ENOENT;
486 }
487
488 pdata = pdev->dev.platform_data;
489
490 if (pdata && pdata->init) {
491 ret = pdata->init(&pdev->dev);
492 if (ret)
493 return ret;
494 }
495
496 res_size = resource_size(res);
497
498 if (!request_mem_region(res->start, res_size, DRIVER_NAME)) {
499 ret = -EBUSY;
500 goto fail0;
501 }
502
503 base = ioremap(res->start, res_size);
504 if (!base) {
505 dev_err(&pdev->dev, "ioremap failed\n");
506 ret = -EIO;
507 goto fail1;
508 }
509
510 i2c_imx = kzalloc(sizeof(struct imx_i2c_struct), GFP_KERNEL);
511 if (!i2c_imx) {
512 dev_err(&pdev->dev, "can't allocate interface\n");
513 ret = -ENOMEM;
514 goto fail2;
515 }
516
517 /* Setup i2c_imx driver structure */
518 strcpy(i2c_imx->adapter.name, pdev->name);
519 i2c_imx->adapter.owner = THIS_MODULE;
520 i2c_imx->adapter.algo = &i2c_imx_algo;
521 i2c_imx->adapter.dev.parent = &pdev->dev;
522 i2c_imx->adapter.nr = pdev->id;
523 i2c_imx->irq = irq;
524 i2c_imx->base = base;
525 i2c_imx->res = res;
526
527 /* Get I2C clock */
528 i2c_imx->clk = clk_get(&pdev->dev, "i2c_clk");
529 if (IS_ERR(i2c_imx->clk)) {
530 ret = PTR_ERR(i2c_imx->clk);
531 dev_err(&pdev->dev, "can't get I2C clock\n");
532 goto fail3;
533 }
534
535 /* Request IRQ */
536 ret = request_irq(i2c_imx->irq, i2c_imx_isr, 0, pdev->name, i2c_imx);
537 if (ret) {
538 dev_err(&pdev->dev, "can't claim irq %d\n", i2c_imx->irq);
539 goto fail4;
540 }
541
542 /* Init queue */
543 init_waitqueue_head(&i2c_imx->queue);
544
545 /* Set up adapter data */
546 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
547
548 /* Set up clock divider */
549 if (pdata && pdata->bitrate)
550 i2c_imx_set_clk(i2c_imx, pdata->bitrate);
551 else
552 i2c_imx_set_clk(i2c_imx, IMX_I2C_BIT_RATE);
553
554 /* Set up chip registers to defaults */
555 writeb(0, i2c_imx->base + IMX_I2C_I2CR);
556 writeb(0, i2c_imx->base + IMX_I2C_I2SR);
557
558 /* Add I2C adapter */
559 ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
560 if (ret < 0) {
561 dev_err(&pdev->dev, "registration failed\n");
562 goto fail5;
563 }
564
565 /* Set up platform driver data */
566 platform_set_drvdata(pdev, i2c_imx);
567
568 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", i2c_imx->irq);
569 dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n",
570 i2c_imx->res->start, i2c_imx->res->end);
571 dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x \n",
572 res_size, i2c_imx->res->start);
573 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
574 i2c_imx->adapter.name);
575 dev_dbg(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
576
577 return 0; /* Return OK */
578
579fail5:
580 free_irq(i2c_imx->irq, i2c_imx);
581fail4:
582 clk_put(i2c_imx->clk);
583fail3:
584 kfree(i2c_imx);
585fail2:
586 iounmap(base);
587fail1:
588 release_mem_region(res->start, resource_size(res));
589fail0:
590 if (pdata && pdata->exit)
591 pdata->exit(&pdev->dev);
592 return ret; /* Return error number */
593}
594
595static int __exit i2c_imx_remove(struct platform_device *pdev)
596{
597 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
598 struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
599
600 /* remove adapter */
601 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
602 i2c_del_adapter(&i2c_imx->adapter);
603 platform_set_drvdata(pdev, NULL);
604
605 /* free interrupt */
606 free_irq(i2c_imx->irq, i2c_imx);
607
608 /* setup chip registers to defaults */
609 writeb(0, i2c_imx->base + IMX_I2C_IADR);
610 writeb(0, i2c_imx->base + IMX_I2C_IFDR);
611 writeb(0, i2c_imx->base + IMX_I2C_I2CR);
612 writeb(0, i2c_imx->base + IMX_I2C_I2SR);
613
614 /* Shut down hardware */
615 if (pdata && pdata->exit)
616 pdata->exit(&pdev->dev);
617
618 clk_put(i2c_imx->clk);
619
620 iounmap(i2c_imx->base);
621 release_mem_region(i2c_imx->res->start, resource_size(i2c_imx->res));
622 kfree(i2c_imx);
623 return 0;
624}
625
626static struct platform_driver i2c_imx_driver = {
627 .remove = __exit_p(i2c_imx_remove),
628 .driver = {
629 .name = DRIVER_NAME,
630 .owner = THIS_MODULE,
631 }
632};
633
634static int __init i2c_adap_imx_init(void)
635{
636 return platform_driver_probe(&i2c_imx_driver, i2c_imx_probe);
637}
638subsys_initcall(i2c_adap_imx_init);
639
640static void __exit i2c_adap_imx_exit(void)
641{
642 platform_driver_unregister(&i2c_imx_driver);
643}
644module_exit(i2c_adap_imx_exit);
645
646MODULE_LICENSE("GPL");
647MODULE_AUTHOR("Darius Augulis");
648MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
649MODULE_ALIAS("platform:" DRIVER_NAME);
1/*
2 * Copyright (C) 2002 Motorola GSG-China
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * Author:
15 * Darius Augulis, Teltonika Inc.
16 *
17 * Desc.:
18 * Implementation of I2C Adapter/Algorithm Driver
19 * for I2C Bus integrated in Freescale i.MX/MXC processors
20 *
21 * Derived from Motorola GSG China I2C example driver
22 *
23 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
24 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
25 * Copyright (C) 2007 RightHand Technologies, Inc.
26 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
27 *
28 * Copyright 2013 Freescale Semiconductor, Inc.
29 *
30 */
31
32#include <linux/clk.h>
33#include <linux/completion.h>
34#include <linux/delay.h>
35#include <linux/dma-mapping.h>
36#include <linux/dmaengine.h>
37#include <linux/dmapool.h>
38#include <linux/err.h>
39#include <linux/errno.h>
40#include <linux/i2c.h>
41#include <linux/init.h>
42#include <linux/interrupt.h>
43#include <linux/io.h>
44#include <linux/kernel.h>
45#include <linux/module.h>
46#include <linux/of.h>
47#include <linux/of_device.h>
48#include <linux/of_dma.h>
49#include <linux/of_gpio.h>
50#include <linux/pinctrl/consumer.h>
51#include <linux/platform_data/i2c-imx.h>
52#include <linux/platform_device.h>
53#include <linux/pm_runtime.h>
54#include <linux/sched.h>
55#include <linux/slab.h>
56
57/* This will be the driver name the kernel reports */
58#define DRIVER_NAME "imx-i2c"
59
60/* Default value */
61#define IMX_I2C_BIT_RATE 100000 /* 100kHz */
62
63/*
64 * Enable DMA if transfer byte size is bigger than this threshold.
65 * As the hardware request, it must bigger than 4 bytes.\
66 * I have set '16' here, maybe it's not the best but I think it's
67 * the appropriate.
68 */
69#define DMA_THRESHOLD 16
70#define DMA_TIMEOUT 1000
71
72/* IMX I2C registers:
73 * the I2C register offset is different between SoCs,
74 * to provid support for all these chips, split the
75 * register offset into a fixed base address and a
76 * variable shift value, then the full register offset
77 * will be calculated by
78 * reg_off = ( reg_base_addr << reg_shift)
79 */
80#define IMX_I2C_IADR 0x00 /* i2c slave address */
81#define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
82#define IMX_I2C_I2CR 0x02 /* i2c control */
83#define IMX_I2C_I2SR 0x03 /* i2c status */
84#define IMX_I2C_I2DR 0x04 /* i2c transfer data */
85
86#define IMX_I2C_REGSHIFT 2
87#define VF610_I2C_REGSHIFT 0
88
89/* Bits of IMX I2C registers */
90#define I2SR_RXAK 0x01
91#define I2SR_IIF 0x02
92#define I2SR_SRW 0x04
93#define I2SR_IAL 0x10
94#define I2SR_IBB 0x20
95#define I2SR_IAAS 0x40
96#define I2SR_ICF 0x80
97#define I2CR_DMAEN 0x02
98#define I2CR_RSTA 0x04
99#define I2CR_TXAK 0x08
100#define I2CR_MTX 0x10
101#define I2CR_MSTA 0x20
102#define I2CR_IIEN 0x40
103#define I2CR_IEN 0x80
104
105/* register bits different operating codes definition:
106 * 1) I2SR: Interrupt flags clear operation differ between SoCs:
107 * - write zero to clear(w0c) INT flag on i.MX,
108 * - but write one to clear(w1c) INT flag on Vybrid.
109 * 2) I2CR: I2C module enable operation also differ between SoCs:
110 * - set I2CR_IEN bit enable the module on i.MX,
111 * - but clear I2CR_IEN bit enable the module on Vybrid.
112 */
113#define I2SR_CLR_OPCODE_W0C 0x0
114#define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)
115#define I2CR_IEN_OPCODE_0 0x0
116#define I2CR_IEN_OPCODE_1 I2CR_IEN
117
118#define I2C_PM_TIMEOUT 10 /* ms */
119
120/*
121 * sorted list of clock divider, register value pairs
122 * taken from table 26-5, p.26-9, Freescale i.MX
123 * Integrated Portable System Processor Reference Manual
124 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
125 *
126 * Duplicated divider values removed from list
127 */
128struct imx_i2c_clk_pair {
129 u16 div;
130 u16 val;
131};
132
133static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
134 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
135 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
136 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
137 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
138 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
139 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
140 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
141 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
142 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
143 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
144 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
145 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
146 { 3072, 0x1E }, { 3840, 0x1F }
147};
148
149/* Vybrid VF610 clock divider, register value pairs */
150static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
151 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
152 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
153 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
154 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
155 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
156 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
157 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
158 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
159 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
160 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
161 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
162 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
163 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
164 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
165 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
166};
167
168enum imx_i2c_type {
169 IMX1_I2C,
170 IMX21_I2C,
171 VF610_I2C,
172};
173
174struct imx_i2c_hwdata {
175 enum imx_i2c_type devtype;
176 unsigned regshift;
177 struct imx_i2c_clk_pair *clk_div;
178 unsigned ndivs;
179 unsigned i2sr_clr_opcode;
180 unsigned i2cr_ien_opcode;
181};
182
183struct imx_i2c_dma {
184 struct dma_chan *chan_tx;
185 struct dma_chan *chan_rx;
186 struct dma_chan *chan_using;
187 struct completion cmd_complete;
188 dma_addr_t dma_buf;
189 unsigned int dma_len;
190 enum dma_transfer_direction dma_transfer_dir;
191 enum dma_data_direction dma_data_dir;
192};
193
194struct imx_i2c_struct {
195 struct i2c_adapter adapter;
196 struct clk *clk;
197 void __iomem *base;
198 wait_queue_head_t queue;
199 unsigned long i2csr;
200 unsigned int disable_delay;
201 int stopped;
202 unsigned int ifdr; /* IMX_I2C_IFDR */
203 unsigned int cur_clk;
204 unsigned int bitrate;
205 const struct imx_i2c_hwdata *hwdata;
206 struct i2c_bus_recovery_info rinfo;
207
208 struct pinctrl *pinctrl;
209 struct pinctrl_state *pinctrl_pins_default;
210 struct pinctrl_state *pinctrl_pins_gpio;
211
212 struct imx_i2c_dma *dma;
213};
214
215static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
216 .devtype = IMX1_I2C,
217 .regshift = IMX_I2C_REGSHIFT,
218 .clk_div = imx_i2c_clk_div,
219 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
220 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
221 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
222
223};
224
225static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
226 .devtype = IMX21_I2C,
227 .regshift = IMX_I2C_REGSHIFT,
228 .clk_div = imx_i2c_clk_div,
229 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
230 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
231 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
232
233};
234
235static struct imx_i2c_hwdata vf610_i2c_hwdata = {
236 .devtype = VF610_I2C,
237 .regshift = VF610_I2C_REGSHIFT,
238 .clk_div = vf610_i2c_clk_div,
239 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div),
240 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,
241 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0,
242
243};
244
245static const struct platform_device_id imx_i2c_devtype[] = {
246 {
247 .name = "imx1-i2c",
248 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
249 }, {
250 .name = "imx21-i2c",
251 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
252 }, {
253 /* sentinel */
254 }
255};
256MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
257
258static const struct of_device_id i2c_imx_dt_ids[] = {
259 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
260 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
261 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
262 { /* sentinel */ }
263};
264MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
265
266static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
267{
268 return i2c_imx->hwdata->devtype == IMX1_I2C;
269}
270
271static inline void imx_i2c_write_reg(unsigned int val,
272 struct imx_i2c_struct *i2c_imx, unsigned int reg)
273{
274 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
275}
276
277static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
278 unsigned int reg)
279{
280 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
281}
282
283/* Functions for DMA support */
284static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
285 dma_addr_t phy_addr)
286{
287 struct imx_i2c_dma *dma;
288 struct dma_slave_config dma_sconfig;
289 struct device *dev = &i2c_imx->adapter.dev;
290 int ret;
291
292 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
293 if (!dma)
294 return;
295
296 dma->chan_tx = dma_request_slave_channel(dev, "tx");
297 if (!dma->chan_tx) {
298 dev_dbg(dev, "can't request DMA tx channel\n");
299 goto fail_al;
300 }
301
302 dma_sconfig.dst_addr = phy_addr +
303 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
304 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
305 dma_sconfig.dst_maxburst = 1;
306 dma_sconfig.direction = DMA_MEM_TO_DEV;
307 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
308 if (ret < 0) {
309 dev_dbg(dev, "can't configure tx channel\n");
310 goto fail_tx;
311 }
312
313 dma->chan_rx = dma_request_slave_channel(dev, "rx");
314 if (!dma->chan_rx) {
315 dev_dbg(dev, "can't request DMA rx channel\n");
316 goto fail_tx;
317 }
318
319 dma_sconfig.src_addr = phy_addr +
320 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
321 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
322 dma_sconfig.src_maxburst = 1;
323 dma_sconfig.direction = DMA_DEV_TO_MEM;
324 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
325 if (ret < 0) {
326 dev_dbg(dev, "can't configure rx channel\n");
327 goto fail_rx;
328 }
329
330 i2c_imx->dma = dma;
331 init_completion(&dma->cmd_complete);
332 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
333 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
334
335 return;
336
337fail_rx:
338 dma_release_channel(dma->chan_rx);
339fail_tx:
340 dma_release_channel(dma->chan_tx);
341fail_al:
342 devm_kfree(dev, dma);
343 dev_info(dev, "can't use DMA, using PIO instead.\n");
344}
345
346static void i2c_imx_dma_callback(void *arg)
347{
348 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
349 struct imx_i2c_dma *dma = i2c_imx->dma;
350
351 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
352 dma->dma_len, dma->dma_data_dir);
353 complete(&dma->cmd_complete);
354}
355
356static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
357 struct i2c_msg *msgs)
358{
359 struct imx_i2c_dma *dma = i2c_imx->dma;
360 struct dma_async_tx_descriptor *txdesc;
361 struct device *dev = &i2c_imx->adapter.dev;
362 struct device *chan_dev = dma->chan_using->device->dev;
363
364 dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
365 dma->dma_len, dma->dma_data_dir);
366 if (dma_mapping_error(chan_dev, dma->dma_buf)) {
367 dev_err(dev, "DMA mapping failed\n");
368 goto err_map;
369 }
370
371 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
372 dma->dma_len, dma->dma_transfer_dir,
373 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
374 if (!txdesc) {
375 dev_err(dev, "Not able to get desc for DMA xfer\n");
376 goto err_desc;
377 }
378
379 txdesc->callback = i2c_imx_dma_callback;
380 txdesc->callback_param = i2c_imx;
381 if (dma_submit_error(dmaengine_submit(txdesc))) {
382 dev_err(dev, "DMA submit failed\n");
383 goto err_submit;
384 }
385
386 dma_async_issue_pending(dma->chan_using);
387 return 0;
388
389err_submit:
390 dmaengine_terminate_all(dma->chan_using);
391err_desc:
392 dma_unmap_single(chan_dev, dma->dma_buf,
393 dma->dma_len, dma->dma_data_dir);
394err_map:
395 return -EINVAL;
396}
397
398static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
399{
400 struct imx_i2c_dma *dma = i2c_imx->dma;
401
402 dma->dma_buf = 0;
403 dma->dma_len = 0;
404
405 dma_release_channel(dma->chan_tx);
406 dma->chan_tx = NULL;
407
408 dma_release_channel(dma->chan_rx);
409 dma->chan_rx = NULL;
410
411 dma->chan_using = NULL;
412}
413
414static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
415{
416 unsigned long orig_jiffies = jiffies;
417 unsigned int temp;
418
419 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
420
421 while (1) {
422 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
423
424 /* check for arbitration lost */
425 if (temp & I2SR_IAL) {
426 temp &= ~I2SR_IAL;
427 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
428 return -EAGAIN;
429 }
430
431 if (for_busy && (temp & I2SR_IBB))
432 break;
433 if (!for_busy && !(temp & I2SR_IBB))
434 break;
435 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
436 dev_dbg(&i2c_imx->adapter.dev,
437 "<%s> I2C bus is busy\n", __func__);
438 return -ETIMEDOUT;
439 }
440 schedule();
441 }
442
443 return 0;
444}
445
446static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
447{
448 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
449
450 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
451 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
452 return -ETIMEDOUT;
453 }
454 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
455 i2c_imx->i2csr = 0;
456 return 0;
457}
458
459static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
460{
461 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
462 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
463 return -ENXIO; /* No ACK */
464 }
465
466 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
467 return 0;
468}
469
470static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx)
471{
472 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
473 unsigned int i2c_clk_rate;
474 unsigned int div;
475 int i;
476
477 /* Divider value calculation */
478 i2c_clk_rate = clk_get_rate(i2c_imx->clk);
479 if (i2c_imx->cur_clk == i2c_clk_rate)
480 return;
481
482 i2c_imx->cur_clk = i2c_clk_rate;
483
484 div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate;
485 if (div < i2c_clk_div[0].div)
486 i = 0;
487 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
488 i = i2c_imx->hwdata->ndivs - 1;
489 else
490 for (i = 0; i2c_clk_div[i].div < div; i++)
491 ;
492
493 /* Store divider value */
494 i2c_imx->ifdr = i2c_clk_div[i].val;
495
496 /*
497 * There dummy delay is calculated.
498 * It should be about one I2C clock period long.
499 * This delay is used in I2C bus disable function
500 * to fix chip hardware bug.
501 */
502 i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
503 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
504
505#ifdef CONFIG_I2C_DEBUG_BUS
506 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
507 i2c_clk_rate, div);
508 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
509 i2c_clk_div[i].val, i2c_clk_div[i].div);
510#endif
511}
512
513static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
514{
515 unsigned int temp = 0;
516 int result;
517
518 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
519
520 i2c_imx_set_clk(i2c_imx);
521
522 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
523 /* Enable I2C controller */
524 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
525 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
526
527 /* Wait controller to be stable */
528 usleep_range(50, 150);
529
530 /* Start I2C transaction */
531 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
532 temp |= I2CR_MSTA;
533 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
534 result = i2c_imx_bus_busy(i2c_imx, 1);
535 if (result)
536 return result;
537 i2c_imx->stopped = 0;
538
539 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
540 temp &= ~I2CR_DMAEN;
541 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
542 return result;
543}
544
545static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
546{
547 unsigned int temp = 0;
548
549 if (!i2c_imx->stopped) {
550 /* Stop I2C transaction */
551 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
552 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
553 temp &= ~(I2CR_MSTA | I2CR_MTX);
554 if (i2c_imx->dma)
555 temp &= ~I2CR_DMAEN;
556 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
557 }
558 if (is_imx1_i2c(i2c_imx)) {
559 /*
560 * This delay caused by an i.MXL hardware bug.
561 * If no (or too short) delay, no "STOP" bit will be generated.
562 */
563 udelay(i2c_imx->disable_delay);
564 }
565
566 if (!i2c_imx->stopped) {
567 i2c_imx_bus_busy(i2c_imx, 0);
568 i2c_imx->stopped = 1;
569 }
570
571 /* Disable I2C controller */
572 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
573 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
574}
575
576static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
577{
578 struct imx_i2c_struct *i2c_imx = dev_id;
579 unsigned int temp;
580
581 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
582 if (temp & I2SR_IIF) {
583 /* save status register */
584 i2c_imx->i2csr = temp;
585 temp &= ~I2SR_IIF;
586 temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
587 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
588 wake_up(&i2c_imx->queue);
589 return IRQ_HANDLED;
590 }
591
592 return IRQ_NONE;
593}
594
595static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
596 struct i2c_msg *msgs)
597{
598 int result;
599 unsigned long time_left;
600 unsigned int temp = 0;
601 unsigned long orig_jiffies = jiffies;
602 struct imx_i2c_dma *dma = i2c_imx->dma;
603 struct device *dev = &i2c_imx->adapter.dev;
604
605 dma->chan_using = dma->chan_tx;
606 dma->dma_transfer_dir = DMA_MEM_TO_DEV;
607 dma->dma_data_dir = DMA_TO_DEVICE;
608 dma->dma_len = msgs->len - 1;
609 result = i2c_imx_dma_xfer(i2c_imx, msgs);
610 if (result)
611 return result;
612
613 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
614 temp |= I2CR_DMAEN;
615 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
616
617 /*
618 * Write slave address.
619 * The first byte must be transmitted by the CPU.
620 */
621 imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
622 reinit_completion(&i2c_imx->dma->cmd_complete);
623 time_left = wait_for_completion_timeout(
624 &i2c_imx->dma->cmd_complete,
625 msecs_to_jiffies(DMA_TIMEOUT));
626 if (time_left == 0) {
627 dmaengine_terminate_all(dma->chan_using);
628 return -ETIMEDOUT;
629 }
630
631 /* Waiting for transfer complete. */
632 while (1) {
633 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
634 if (temp & I2SR_ICF)
635 break;
636 if (time_after(jiffies, orig_jiffies +
637 msecs_to_jiffies(DMA_TIMEOUT))) {
638 dev_dbg(dev, "<%s> Timeout\n", __func__);
639 return -ETIMEDOUT;
640 }
641 schedule();
642 }
643
644 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
645 temp &= ~I2CR_DMAEN;
646 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
647
648 /* The last data byte must be transferred by the CPU. */
649 imx_i2c_write_reg(msgs->buf[msgs->len-1],
650 i2c_imx, IMX_I2C_I2DR);
651 result = i2c_imx_trx_complete(i2c_imx);
652 if (result)
653 return result;
654
655 return i2c_imx_acked(i2c_imx);
656}
657
658static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
659 struct i2c_msg *msgs, bool is_lastmsg)
660{
661 int result;
662 unsigned long time_left;
663 unsigned int temp;
664 unsigned long orig_jiffies = jiffies;
665 struct imx_i2c_dma *dma = i2c_imx->dma;
666 struct device *dev = &i2c_imx->adapter.dev;
667
668 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
669 temp |= I2CR_DMAEN;
670 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
671
672 dma->chan_using = dma->chan_rx;
673 dma->dma_transfer_dir = DMA_DEV_TO_MEM;
674 dma->dma_data_dir = DMA_FROM_DEVICE;
675 /* The last two data bytes must be transferred by the CPU. */
676 dma->dma_len = msgs->len - 2;
677 result = i2c_imx_dma_xfer(i2c_imx, msgs);
678 if (result)
679 return result;
680
681 reinit_completion(&i2c_imx->dma->cmd_complete);
682 time_left = wait_for_completion_timeout(
683 &i2c_imx->dma->cmd_complete,
684 msecs_to_jiffies(DMA_TIMEOUT));
685 if (time_left == 0) {
686 dmaengine_terminate_all(dma->chan_using);
687 return -ETIMEDOUT;
688 }
689
690 /* waiting for transfer complete. */
691 while (1) {
692 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
693 if (temp & I2SR_ICF)
694 break;
695 if (time_after(jiffies, orig_jiffies +
696 msecs_to_jiffies(DMA_TIMEOUT))) {
697 dev_dbg(dev, "<%s> Timeout\n", __func__);
698 return -ETIMEDOUT;
699 }
700 schedule();
701 }
702
703 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
704 temp &= ~I2CR_DMAEN;
705 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
706
707 /* read n-1 byte data */
708 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
709 temp |= I2CR_TXAK;
710 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
711
712 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
713 /* read n byte data */
714 result = i2c_imx_trx_complete(i2c_imx);
715 if (result)
716 return result;
717
718 if (is_lastmsg) {
719 /*
720 * It must generate STOP before read I2DR to prevent
721 * controller from generating another clock cycle
722 */
723 dev_dbg(dev, "<%s> clear MSTA\n", __func__);
724 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
725 temp &= ~(I2CR_MSTA | I2CR_MTX);
726 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
727 i2c_imx_bus_busy(i2c_imx, 0);
728 i2c_imx->stopped = 1;
729 } else {
730 /*
731 * For i2c master receiver repeat restart operation like:
732 * read -> repeat MSTA -> read/write
733 * The controller must set MTX before read the last byte in
734 * the first read operation, otherwise the first read cost
735 * one extra clock cycle.
736 */
737 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
738 temp |= I2CR_MTX;
739 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
740 }
741 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
742
743 return 0;
744}
745
746static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
747{
748 int i, result;
749
750 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
751 __func__, msgs->addr << 1);
752
753 /* write slave address */
754 imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
755 result = i2c_imx_trx_complete(i2c_imx);
756 if (result)
757 return result;
758 result = i2c_imx_acked(i2c_imx);
759 if (result)
760 return result;
761 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
762
763 /* write data */
764 for (i = 0; i < msgs->len; i++) {
765 dev_dbg(&i2c_imx->adapter.dev,
766 "<%s> write byte: B%d=0x%X\n",
767 __func__, i, msgs->buf[i]);
768 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
769 result = i2c_imx_trx_complete(i2c_imx);
770 if (result)
771 return result;
772 result = i2c_imx_acked(i2c_imx);
773 if (result)
774 return result;
775 }
776 return 0;
777}
778
779static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bool is_lastmsg)
780{
781 int i, result;
782 unsigned int temp;
783 int block_data = msgs->flags & I2C_M_RECV_LEN;
784
785 dev_dbg(&i2c_imx->adapter.dev,
786 "<%s> write slave address: addr=0x%x\n",
787 __func__, (msgs->addr << 1) | 0x01);
788
789 /* write slave address */
790 imx_i2c_write_reg((msgs->addr << 1) | 0x01, i2c_imx, IMX_I2C_I2DR);
791 result = i2c_imx_trx_complete(i2c_imx);
792 if (result)
793 return result;
794 result = i2c_imx_acked(i2c_imx);
795 if (result)
796 return result;
797
798 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
799
800 /* setup bus to read data */
801 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
802 temp &= ~I2CR_MTX;
803
804 /*
805 * Reset the I2CR_TXAK flag initially for SMBus block read since the
806 * length is unknown
807 */
808 if ((msgs->len - 1) || block_data)
809 temp &= ~I2CR_TXAK;
810 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
811 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
812
813 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
814
815 if (i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data)
816 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
817
818 /* read data */
819 for (i = 0; i < msgs->len; i++) {
820 u8 len = 0;
821
822 result = i2c_imx_trx_complete(i2c_imx);
823 if (result)
824 return result;
825 /*
826 * First byte is the length of remaining packet
827 * in the SMBus block data read. Add it to
828 * msgs->len.
829 */
830 if ((!i) && block_data) {
831 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
832 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
833 return -EPROTO;
834 dev_dbg(&i2c_imx->adapter.dev,
835 "<%s> read length: 0x%X\n",
836 __func__, len);
837 msgs->len += len;
838 }
839 if (i == (msgs->len - 1)) {
840 if (is_lastmsg) {
841 /*
842 * It must generate STOP before read I2DR to prevent
843 * controller from generating another clock cycle
844 */
845 dev_dbg(&i2c_imx->adapter.dev,
846 "<%s> clear MSTA\n", __func__);
847 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
848 temp &= ~(I2CR_MSTA | I2CR_MTX);
849 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
850 i2c_imx_bus_busy(i2c_imx, 0);
851 i2c_imx->stopped = 1;
852 } else {
853 /*
854 * For i2c master receiver repeat restart operation like:
855 * read -> repeat MSTA -> read/write
856 * The controller must set MTX before read the last byte in
857 * the first read operation, otherwise the first read cost
858 * one extra clock cycle.
859 */
860 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
861 temp |= I2CR_MTX;
862 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
863 }
864 } else if (i == (msgs->len - 2)) {
865 dev_dbg(&i2c_imx->adapter.dev,
866 "<%s> set TXAK\n", __func__);
867 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
868 temp |= I2CR_TXAK;
869 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
870 }
871 if ((!i) && block_data)
872 msgs->buf[0] = len;
873 else
874 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
875 dev_dbg(&i2c_imx->adapter.dev,
876 "<%s> read byte: B%d=0x%X\n",
877 __func__, i, msgs->buf[i]);
878 }
879 return 0;
880}
881
882static int i2c_imx_xfer(struct i2c_adapter *adapter,
883 struct i2c_msg *msgs, int num)
884{
885 unsigned int i, temp;
886 int result;
887 bool is_lastmsg = false;
888 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
889
890 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
891
892 result = pm_runtime_get_sync(i2c_imx->adapter.dev.parent);
893 if (result < 0)
894 goto out;
895
896 /* Start I2C transfer */
897 result = i2c_imx_start(i2c_imx);
898 if (result) {
899 if (i2c_imx->adapter.bus_recovery_info) {
900 i2c_recover_bus(&i2c_imx->adapter);
901 result = i2c_imx_start(i2c_imx);
902 }
903 }
904
905 if (result)
906 goto fail0;
907
908 /* read/write data */
909 for (i = 0; i < num; i++) {
910 if (i == num - 1)
911 is_lastmsg = true;
912
913 if (i) {
914 dev_dbg(&i2c_imx->adapter.dev,
915 "<%s> repeated start\n", __func__);
916 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
917 temp |= I2CR_RSTA;
918 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
919 result = i2c_imx_bus_busy(i2c_imx, 1);
920 if (result)
921 goto fail0;
922 }
923 dev_dbg(&i2c_imx->adapter.dev,
924 "<%s> transfer message: %d\n", __func__, i);
925 /* write/read data */
926#ifdef CONFIG_I2C_DEBUG_BUS
927 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
928 dev_dbg(&i2c_imx->adapter.dev,
929 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
930 __func__,
931 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
932 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
933 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
934 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
935 dev_dbg(&i2c_imx->adapter.dev,
936 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
937 __func__,
938 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
939 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
940 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
941 (temp & I2SR_RXAK ? 1 : 0));
942#endif
943 if (msgs[i].flags & I2C_M_RD)
944 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg);
945 else {
946 if (i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD)
947 result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
948 else
949 result = i2c_imx_write(i2c_imx, &msgs[i]);
950 }
951 if (result)
952 goto fail0;
953 }
954
955fail0:
956 /* Stop I2C transfer */
957 i2c_imx_stop(i2c_imx);
958
959 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent);
960 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent);
961
962out:
963 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
964 (result < 0) ? "error" : "success msg",
965 (result < 0) ? result : num);
966 return (result < 0) ? result : num;
967}
968
969static void i2c_imx_prepare_recovery(struct i2c_adapter *adap)
970{
971 struct imx_i2c_struct *i2c_imx;
972
973 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
974
975 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio);
976}
977
978static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap)
979{
980 struct imx_i2c_struct *i2c_imx;
981
982 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
983
984 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default);
985}
986
987/*
988 * We switch SCL and SDA to their GPIO function and do some bitbanging
989 * for bus recovery. These alternative pinmux settings can be
990 * described in the device tree by a separate pinctrl state "gpio". If
991 * this is missing this is not a big problem, the only implication is
992 * that we can't do bus recovery.
993 */
994static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,
995 struct platform_device *pdev)
996{
997 struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo;
998
999 i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
1000 if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) {
1001 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n");
1002 return PTR_ERR(i2c_imx->pinctrl);
1003 }
1004
1005 i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl,
1006 PINCTRL_STATE_DEFAULT);
1007 i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl,
1008 "gpio");
1009 rinfo->sda_gpio = of_get_named_gpio(pdev->dev.of_node, "sda-gpios", 0);
1010 rinfo->scl_gpio = of_get_named_gpio(pdev->dev.of_node, "scl-gpios", 0);
1011
1012 if (rinfo->sda_gpio == -EPROBE_DEFER ||
1013 rinfo->scl_gpio == -EPROBE_DEFER) {
1014 return -EPROBE_DEFER;
1015 } else if (!gpio_is_valid(rinfo->sda_gpio) ||
1016 !gpio_is_valid(rinfo->scl_gpio) ||
1017 IS_ERR(i2c_imx->pinctrl_pins_default) ||
1018 IS_ERR(i2c_imx->pinctrl_pins_gpio)) {
1019 dev_dbg(&pdev->dev, "recovery information incomplete\n");
1020 return 0;
1021 }
1022
1023 dev_dbg(&pdev->dev, "using scl-gpio %d and sda-gpio %d for recovery\n",
1024 rinfo->sda_gpio, rinfo->scl_gpio);
1025
1026 rinfo->prepare_recovery = i2c_imx_prepare_recovery;
1027 rinfo->unprepare_recovery = i2c_imx_unprepare_recovery;
1028 rinfo->recover_bus = i2c_generic_gpio_recovery;
1029 i2c_imx->adapter.bus_recovery_info = rinfo;
1030
1031 return 0;
1032}
1033
1034static u32 i2c_imx_func(struct i2c_adapter *adapter)
1035{
1036 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
1037 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1038}
1039
1040static struct i2c_algorithm i2c_imx_algo = {
1041 .master_xfer = i2c_imx_xfer,
1042 .functionality = i2c_imx_func,
1043};
1044
1045static int i2c_imx_probe(struct platform_device *pdev)
1046{
1047 const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids,
1048 &pdev->dev);
1049 struct imx_i2c_struct *i2c_imx;
1050 struct resource *res;
1051 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
1052 void __iomem *base;
1053 int irq, ret;
1054 dma_addr_t phy_addr;
1055
1056 dev_dbg(&pdev->dev, "<%s>\n", __func__);
1057
1058 irq = platform_get_irq(pdev, 0);
1059 if (irq < 0) {
1060 dev_err(&pdev->dev, "can't get irq number\n");
1061 return irq;
1062 }
1063
1064 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1065 base = devm_ioremap_resource(&pdev->dev, res);
1066 if (IS_ERR(base))
1067 return PTR_ERR(base);
1068
1069 phy_addr = (dma_addr_t)res->start;
1070 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
1071 if (!i2c_imx)
1072 return -ENOMEM;
1073
1074 if (of_id)
1075 i2c_imx->hwdata = of_id->data;
1076 else
1077 i2c_imx->hwdata = (struct imx_i2c_hwdata *)
1078 platform_get_device_id(pdev)->driver_data;
1079
1080 /* Setup i2c_imx driver structure */
1081 strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
1082 i2c_imx->adapter.owner = THIS_MODULE;
1083 i2c_imx->adapter.algo = &i2c_imx_algo;
1084 i2c_imx->adapter.dev.parent = &pdev->dev;
1085 i2c_imx->adapter.nr = pdev->id;
1086 i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
1087 i2c_imx->base = base;
1088
1089 /* Get I2C clock */
1090 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
1091 if (IS_ERR(i2c_imx->clk)) {
1092 dev_err(&pdev->dev, "can't get I2C clock\n");
1093 return PTR_ERR(i2c_imx->clk);
1094 }
1095
1096 ret = clk_prepare_enable(i2c_imx->clk);
1097 if (ret) {
1098 dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret);
1099 return ret;
1100 }
1101
1102 /* Request IRQ */
1103 ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
1104 pdev->name, i2c_imx);
1105 if (ret) {
1106 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
1107 goto clk_disable;
1108 }
1109
1110 /* Init queue */
1111 init_waitqueue_head(&i2c_imx->queue);
1112
1113 /* Set up adapter data */
1114 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
1115
1116 /* Set up platform driver data */
1117 platform_set_drvdata(pdev, i2c_imx);
1118
1119 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
1120 pm_runtime_use_autosuspend(&pdev->dev);
1121 pm_runtime_set_active(&pdev->dev);
1122 pm_runtime_enable(&pdev->dev);
1123
1124 ret = pm_runtime_get_sync(&pdev->dev);
1125 if (ret < 0)
1126 goto rpm_disable;
1127
1128 /* Set up clock divider */
1129 i2c_imx->bitrate = IMX_I2C_BIT_RATE;
1130 ret = of_property_read_u32(pdev->dev.of_node,
1131 "clock-frequency", &i2c_imx->bitrate);
1132 if (ret < 0 && pdata && pdata->bitrate)
1133 i2c_imx->bitrate = pdata->bitrate;
1134
1135 /* Set up chip registers to defaults */
1136 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
1137 i2c_imx, IMX_I2C_I2CR);
1138 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
1139
1140 /* Init optional bus recovery function */
1141 ret = i2c_imx_init_recovery_info(i2c_imx, pdev);
1142 /* Give it another chance if pinctrl used is not ready yet */
1143 if (ret == -EPROBE_DEFER)
1144 goto rpm_disable;
1145
1146 /* Add I2C adapter */
1147 ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
1148 if (ret < 0)
1149 goto rpm_disable;
1150
1151 pm_runtime_mark_last_busy(&pdev->dev);
1152 pm_runtime_put_autosuspend(&pdev->dev);
1153
1154 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
1155 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
1156 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
1157 i2c_imx->adapter.name);
1158 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1159
1160 /* Init DMA config if supported */
1161 i2c_imx_dma_request(i2c_imx, phy_addr);
1162
1163 return 0; /* Return OK */
1164
1165rpm_disable:
1166 pm_runtime_put_noidle(&pdev->dev);
1167 pm_runtime_disable(&pdev->dev);
1168 pm_runtime_set_suspended(&pdev->dev);
1169 pm_runtime_dont_use_autosuspend(&pdev->dev);
1170
1171clk_disable:
1172 clk_disable_unprepare(i2c_imx->clk);
1173 return ret;
1174}
1175
1176static int i2c_imx_remove(struct platform_device *pdev)
1177{
1178 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
1179 int ret;
1180
1181 ret = pm_runtime_get_sync(&pdev->dev);
1182 if (ret < 0)
1183 return ret;
1184
1185 /* remove adapter */
1186 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
1187 i2c_del_adapter(&i2c_imx->adapter);
1188
1189 if (i2c_imx->dma)
1190 i2c_imx_dma_free(i2c_imx);
1191
1192 /* setup chip registers to defaults */
1193 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
1194 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
1195 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
1196 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
1197
1198 clk_disable_unprepare(i2c_imx->clk);
1199
1200 pm_runtime_put_noidle(&pdev->dev);
1201 pm_runtime_disable(&pdev->dev);
1202
1203 return 0;
1204}
1205
1206#ifdef CONFIG_PM
1207static int i2c_imx_runtime_suspend(struct device *dev)
1208{
1209 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1210
1211 clk_disable_unprepare(i2c_imx->clk);
1212
1213 return 0;
1214}
1215
1216static int i2c_imx_runtime_resume(struct device *dev)
1217{
1218 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1219 int ret;
1220
1221 ret = clk_prepare_enable(i2c_imx->clk);
1222 if (ret)
1223 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret);
1224
1225 return ret;
1226}
1227
1228static const struct dev_pm_ops i2c_imx_pm_ops = {
1229 SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend,
1230 i2c_imx_runtime_resume, NULL)
1231};
1232#define I2C_IMX_PM_OPS (&i2c_imx_pm_ops)
1233#else
1234#define I2C_IMX_PM_OPS NULL
1235#endif /* CONFIG_PM */
1236
1237static struct platform_driver i2c_imx_driver = {
1238 .probe = i2c_imx_probe,
1239 .remove = i2c_imx_remove,
1240 .driver = {
1241 .name = DRIVER_NAME,
1242 .pm = I2C_IMX_PM_OPS,
1243 .of_match_table = i2c_imx_dt_ids,
1244 },
1245 .id_table = imx_i2c_devtype,
1246};
1247
1248static int __init i2c_adap_imx_init(void)
1249{
1250 return platform_driver_register(&i2c_imx_driver);
1251}
1252subsys_initcall(i2c_adap_imx_init);
1253
1254static void __exit i2c_adap_imx_exit(void)
1255{
1256 platform_driver_unregister(&i2c_imx_driver);
1257}
1258module_exit(i2c_adap_imx_exit);
1259
1260MODULE_LICENSE("GPL");
1261MODULE_AUTHOR("Darius Augulis");
1262MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
1263MODULE_ALIAS("platform:" DRIVER_NAME);