1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2 */
   3/*
   4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5 * All Rights Reserved.
   6 *
   7 * Permission is hereby granted, free of charge, to any person obtaining a
   8 * copy of this software and associated documentation files (the
   9 * "Software"), to deal in the Software without restriction, including
  10 * without limitation the rights to use, copy, modify, merge, publish,
  11 * distribute, sub license, and/or sell copies of the Software, and to
  12 * permit persons to whom the Software is furnished to do so, subject to
  13 * the following conditions:
  14 *
  15 * The above copyright notice and this permission notice (including the
  16 * next paragraph) shall be included in all copies or substantial portions
  17 * of the Software.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26 *
  27 */
  28
 
 
  29#include <linux/sysrq.h>
  30#include <linux/slab.h>
  31#include "drmP.h"
  32#include "drm.h"
  33#include "i915_drm.h"
  34#include "i915_drv.h"
  35#include "i915_trace.h"
  36#include "intel_drv.h"
  37
  38#define MAX_NOPID ((u32)~0)
  39
  40/**
  41 * Interrupts that are always left unmasked.
  42 *
  43 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44 * we leave them always unmasked in IMR and then control enabling them through
  45 * PIPESTAT alone.
  46 */
  47#define I915_INTERRUPT_ENABLE_FIX			\
  48	(I915_ASLE_INTERRUPT |				\
  49	 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |		\
  50	 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |		\
  51	 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |	\
  52	 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |	\
  53	 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55/** Interrupts that we mask and unmask at runtime. */
  56#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58#define I915_PIPE_VBLANK_STATUS	(PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59				 PIPE_VBLANK_INTERRUPT_STATUS)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  60
  61#define I915_PIPE_VBLANK_ENABLE	(PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62				 PIPE_VBLANK_INTERRUPT_ENABLE)
 
 
 
 
 
  63
  64#define DRM_I915_VBLANK_PIPE_ALL	(DRM_I915_VBLANK_PIPE_A | \
  65					 DRM_I915_VBLANK_PIPE_B)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  66
  67/* For display hotplug interrupt */
  68static void
  69ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  70{
  71	if ((dev_priv->irq_mask & mask) != 0) {
  72		dev_priv->irq_mask &= ~mask;
 
 
 
 
 
 
 
 
 
 
 
 
 
  73		I915_WRITE(DEIMR, dev_priv->irq_mask);
  74		POSTING_READ(DEIMR);
  75	}
  76}
  77
  78static inline void
  79ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 
 
 
 
 
 
 
  80{
  81	if ((dev_priv->irq_mask & mask) != mask) {
  82		dev_priv->irq_mask |= mask;
  83		I915_WRITE(DEIMR, dev_priv->irq_mask);
  84		POSTING_READ(DEIMR);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  85	}
  86}
  87
  88void
  89i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  90{
  91	if ((dev_priv->pipestat[pipe] & mask) != mask) {
  92		u32 reg = PIPESTAT(pipe);
  93
  94		dev_priv->pipestat[pipe] |= mask;
  95		/* Enable the interrupt, clear any pending status */
  96		I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  97		POSTING_READ(reg);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  98	}
 
  99}
 100
 101void
 102i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 103{
 104	if ((dev_priv->pipestat[pipe] & mask) != 0) {
 105		u32 reg = PIPESTAT(pipe);
 106
 107		dev_priv->pipestat[pipe] &= ~mask;
 108		I915_WRITE(reg, dev_priv->pipestat[pipe]);
 109		POSTING_READ(reg);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 110	}
 111}
 112
 113/**
 114 * intel_enable_asle - enable ASLE interrupt for OpRegion
 
 
 
 
 115 */
 116void intel_enable_asle(struct drm_device *dev)
 
 
 
 117{
 118	drm_i915_private_t *dev_priv = dev->dev_private;
 119	unsigned long irqflags;
 120
 121	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 
 
 
 
 
 122
 123	if (HAS_PCH_SPLIT(dev))
 124		ironlake_enable_display_irq(dev_priv, DE_GSE);
 125	else {
 126		i915_enable_pipestat(dev_priv, 1,
 127				     PIPE_LEGACY_BLC_EVENT_ENABLE);
 128		if (INTEL_INFO(dev)->gen >= 4)
 129			i915_enable_pipestat(dev_priv, 0,
 130					     PIPE_LEGACY_BLC_EVENT_ENABLE);
 131	}
 
 132
 133	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 134}
 135
 136/**
 137 * i915_pipe_enabled - check if a pipe is enabled
 138 * @dev: DRM device
 139 * @pipe: pipe to check
 140 *
 141 * Reading certain registers when the pipe is disabled can hang the chip.
 142 * Use this routine to make sure the PLL is running and the pipe is active
 143 * before reading such registers if unsure.
 144 */
 145static int
 146i915_pipe_enabled(struct drm_device *dev, int pipe)
 147{
 148	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 149	return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 
 
 
 
 
 
 
 
 
 150}
 151
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 152/* Called from drm generic code, passed a 'crtc', which
 153 * we use as a pipe index
 154 */
 155static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 156{
 157	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 158	unsigned long high_frame;
 159	unsigned long low_frame;
 160	u32 high1, high2, low;
 161
 162	if (!i915_pipe_enabled(dev, pipe)) {
 163		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 164				"pipe %c\n", pipe_name(pipe));
 165		return 0;
 166	}
 
 
 
 
 
 
 
 
 167
 168	high_frame = PIPEFRAME(pipe);
 169	low_frame = PIPEFRAMEPIXEL(pipe);
 170
 171	/*
 172	 * High & low register fields aren't synchronized, so make sure
 173	 * we get a low value that's stable across two reads of the high
 174	 * register.
 175	 */
 176	do {
 177		high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 178		low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 179		high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 180	} while (high1 != high2);
 181
 182	high1 >>= PIPE_FRAME_HIGH_SHIFT;
 
 183	low >>= PIPE_FRAME_LOW_SHIFT;
 184	return (high1 << 8) | low;
 
 
 
 
 
 
 185}
 186
 187static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 188{
 189	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 190	int reg = PIPE_FRMCOUNT_GM45(pipe);
 191
 192	if (!i915_pipe_enabled(dev, pipe)) {
 193		DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 194				 "pipe %c\n", pipe_name(pipe));
 195		return 0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 196	}
 197
 198	return I915_READ(reg);
 
 
 
 
 199}
 200
 201static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 202			     int *vpos, int *hpos)
 203{
 204	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 205	u32 vbl = 0, position = 0;
 206	int vbl_start, vbl_end, htotal, vtotal;
 
 
 
 
 207	bool in_vbl = true;
 208	int ret = 0;
 
 209
 210	if (!i915_pipe_enabled(dev, pipe)) {
 211		DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 212				 "pipe %c\n", pipe_name(pipe));
 213		return 0;
 214	}
 215
 216	/* Get vtotal. */
 217	vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 218
 219	if (INTEL_INFO(dev)->gen >= 4) {
 220		/* No obvious pixelcount register. Only query vertical
 221		 * scanout position from Display scan line register.
 222		 */
 223		position = I915_READ(PIPEDSL(pipe));
 224
 225		/* Decode into vertical scanout position. Don't have
 226		 * horizontal scanout position.
 227		 */
 228		*vpos = position & 0x1fff;
 229		*hpos = 0;
 230	} else {
 231		/* Have access to pixelcount since start of frame.
 232		 * We can split this into vertical and horizontal
 233		 * scanout position.
 234		 */
 235		position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 236
 237		htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
 238		*vpos = position / htotal;
 239		*hpos = position - (*vpos * htotal);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 240	}
 241
 242	/* Query vblank area. */
 243	vbl = I915_READ(VBLANK(pipe));
 
 244
 245	/* Test position against vblank region. */
 246	vbl_start = vbl & 0x1fff;
 247	vbl_end = (vbl >> 16) & 0x1fff;
 248
 249	if ((*vpos < vbl_start) || (*vpos > vbl_end))
 250		in_vbl = false;
 251
 252	/* Inside "upper part" of vblank area? Apply corrective offset: */
 253	if (in_vbl && (*vpos >= vbl_start))
 254		*vpos = *vpos - vtotal;
 255
 256	/* Readouts valid? */
 257	if (vbl > 0)
 258		ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 
 
 
 
 
 
 
 
 
 
 259
 260	/* In vblank? */
 261	if (in_vbl)
 262		ret |= DRM_SCANOUTPOS_INVBL;
 263
 264	return ret;
 265}
 266
 267static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 
 
 
 
 
 
 
 
 
 
 
 
 
 268			      int *max_error,
 269			      struct timeval *vblank_time,
 270			      unsigned flags)
 271{
 272	struct drm_i915_private *dev_priv = dev->dev_private;
 273	struct drm_crtc *crtc;
 274
 275	if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 276		DRM_ERROR("Invalid crtc %d\n", pipe);
 277		return -EINVAL;
 278	}
 279
 280	/* Get drm_crtc to timestamp: */
 281	crtc = intel_get_crtc_for_pipe(dev, pipe);
 282	if (crtc == NULL) {
 283		DRM_ERROR("Invalid crtc %d\n", pipe);
 284		return -EINVAL;
 285	}
 286
 287	if (!crtc->enabled) {
 288		DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 289		return -EBUSY;
 290	}
 291
 292	/* Helper routine in DRM core does all the work: */
 293	return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 294						     vblank_time, flags,
 295						     crtc);
 296}
 297
 298/*
 299 * Handle hotplug events outside the interrupt handler proper.
 300 */
 301static void i915_hotplug_work_func(struct work_struct *work)
 302{
 303	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 304						    hotplug_work);
 305	struct drm_device *dev = dev_priv->dev;
 306	struct drm_mode_config *mode_config = &dev->mode_config;
 307	struct intel_encoder *encoder;
 308
 309	mutex_lock(&mode_config->mutex);
 310	DRM_DEBUG_KMS("running encoder hotplug functions\n");
 311
 312	list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 313		if (encoder->hot_plug)
 314			encoder->hot_plug(encoder);
 315
 316	mutex_unlock(&mode_config->mutex);
 317
 318	/* Just fire off a uevent and let userspace tell us what to do */
 319	drm_helper_hpd_irq_event(dev);
 320}
 321
 322static void i915_handle_rps_change(struct drm_device *dev)
 323{
 324	drm_i915_private_t *dev_priv = dev->dev_private;
 325	u32 busy_up, busy_down, max_avg, min_avg;
 326	u8 new_delay = dev_priv->cur_delay;
 327
 328	I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 329	busy_up = I915_READ(RCPREVBSYTUPAVG);
 330	busy_down = I915_READ(RCPREVBSYTDNAVG);
 331	max_avg = I915_READ(RCBMAXAVG);
 332	min_avg = I915_READ(RCBMINAVG);
 333
 334	/* Handle RCS change request from hw */
 335	if (busy_up > max_avg) {
 336		if (dev_priv->cur_delay != dev_priv->max_delay)
 337			new_delay = dev_priv->cur_delay - 1;
 338		if (new_delay < dev_priv->max_delay)
 339			new_delay = dev_priv->max_delay;
 340	} else if (busy_down < min_avg) {
 341		if (dev_priv->cur_delay != dev_priv->min_delay)
 342			new_delay = dev_priv->cur_delay + 1;
 343		if (new_delay > dev_priv->min_delay)
 344			new_delay = dev_priv->min_delay;
 345	}
 346
 347	if (ironlake_set_drps(dev, new_delay))
 348		dev_priv->cur_delay = new_delay;
 
 
 349
 350	return;
 351}
 352
 353static void notify_ring(struct drm_device *dev,
 354			struct intel_ring_buffer *ring)
 
 
 
 
 
 
 
 355{
 356	struct drm_i915_private *dev_priv = dev->dev_private;
 357	u32 seqno;
 
 
 358
 359	if (ring->obj == NULL)
 360		return;
 
 
 361
 362	seqno = ring->get_seqno(ring);
 363	trace_i915_gem_request_complete(ring, seqno);
 
 
 
 
 
 
 
 
 
 
 364
 365	ring->irq_seqno = seqno;
 366	wake_up_all(&ring->irq_queue);
 367	if (i915_enable_hangcheck) {
 368		dev_priv->hangcheck_count = 0;
 369		mod_timer(&dev_priv->hangcheck_timer,
 370			  jiffies +
 371			  msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 372	}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 373}
 374
 375static void gen6_pm_rps_work(struct work_struct *work)
 376{
 377	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 378						    rps_work);
 379	u8 new_delay = dev_priv->cur_delay;
 380	u32 pm_iir, pm_imr;
 381
 382	spin_lock_irq(&dev_priv->rps_lock);
 383	pm_iir = dev_priv->pm_iir;
 384	dev_priv->pm_iir = 0;
 385	pm_imr = I915_READ(GEN6_PMIMR);
 386	spin_unlock_irq(&dev_priv->rps_lock);
 387
 388	if (!pm_iir)
 389		return;
 390
 391	mutex_lock(&dev_priv->dev->struct_mutex);
 392	if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
 393		if (dev_priv->cur_delay != dev_priv->max_delay)
 394			new_delay = dev_priv->cur_delay + 1;
 395		if (new_delay > dev_priv->max_delay)
 396			new_delay = dev_priv->max_delay;
 397	} else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
 398		gen6_gt_force_wake_get(dev_priv);
 399		if (dev_priv->cur_delay != dev_priv->min_delay)
 400			new_delay = dev_priv->cur_delay - 1;
 401		if (new_delay < dev_priv->min_delay) {
 402			new_delay = dev_priv->min_delay;
 403			I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 404				   I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
 405				   ((new_delay << 16) & 0x3f0000));
 406		} else {
 407			/* Make sure we continue to get down interrupts
 408			 * until we hit the minimum frequency */
 409			I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
 410				   I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 411		}
 412		gen6_gt_force_wake_put(dev_priv);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 413	}
 414
 415	gen6_set_rps(dev_priv->dev, new_delay);
 416	dev_priv->cur_delay = new_delay;
 417
 418	/*
 419	 * rps_lock not held here because clearing is non-destructive. There is
 420	 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
 421	 * by holding struct_mutex for the duration of the write.
 422	 */
 423	I915_WRITE(GEN6_PMIMR, pm_imr & ~pm_iir);
 424	mutex_unlock(&dev_priv->dev->struct_mutex);
 
 
 
 
 425}
 426
 427static void pch_irq_handler(struct drm_device *dev)
 
 
 
 
 
 
 
 
 
 
 428{
 429	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 430	u32 pch_iir;
 431	int pipe;
 
 
 
 
 
 
 
 
 
 432
 433	pch_iir = I915_READ(SDEIIR);
 
 
 434
 435	if (pch_iir & SDE_AUDIO_POWER_MASK)
 436		DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 437				 (pch_iir & SDE_AUDIO_POWER_MASK) >>
 438				 SDE_AUDIO_POWER_SHIFT);
 439
 440	if (pch_iir & SDE_GMBUS)
 441		DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 442
 443	if (pch_iir & SDE_AUDIO_HDCP_MASK)
 444		DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 
 445
 446	if (pch_iir & SDE_AUDIO_TRANS_MASK)
 447		DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 448
 449	if (pch_iir & SDE_POISON)
 450		DRM_ERROR("PCH poison interrupt\n");
 451
 452	if (pch_iir & SDE_FDI_MASK)
 453		for_each_pipe(pipe)
 454			DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 455					 pipe_name(pipe),
 456					 I915_READ(FDI_RX_IIR(pipe)));
 457
 458	if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 459		DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 460
 461	if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 462		DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 
 
 
 
 463
 464	if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 465		DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 466	if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 467		DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 468}
 469
 470static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
 
 471{
 472	struct drm_device *dev = (struct drm_device *) arg;
 473	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 474	int ret = IRQ_NONE;
 475	u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 476	struct drm_i915_master_private *master_priv;
 477
 478	atomic_inc(&dev_priv->irq_received);
 479
 480	/* disable master interrupt before clearing iir  */
 481	de_ier = I915_READ(DEIER);
 482	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 483	POSTING_READ(DEIER);
 484
 485	de_iir = I915_READ(DEIIR);
 486	gt_iir = I915_READ(GTIIR);
 487	pch_iir = I915_READ(SDEIIR);
 488	pm_iir = I915_READ(GEN6_PMIIR);
 489
 490	if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
 491		goto done;
 492
 493	ret = IRQ_HANDLED;
 
 494
 495	if (dev->primary->master) {
 496		master_priv = dev->primary->master->driver_priv;
 497		if (master_priv->sarea_priv)
 498			master_priv->sarea_priv->last_dispatch =
 499				READ_BREADCRUMB(dev_priv);
 500	}
 
 
 501
 502	if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 503		notify_ring(dev, &dev_priv->ring[RCS]);
 504	if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT)
 505		notify_ring(dev, &dev_priv->ring[VCS]);
 
 
 
 506	if (gt_iir & GT_BLT_USER_INTERRUPT)
 507		notify_ring(dev, &dev_priv->ring[BCS]);
 508
 509	if (de_iir & DE_GSE_IVB)
 510		intel_opregion_gse_intr(dev);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 511
 512	if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
 513		intel_prepare_page_flip(dev, 0);
 514		intel_finish_page_flip_plane(dev, 0);
 
 
 
 
 
 515	}
 516
 517	if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
 518		intel_prepare_page_flip(dev, 1);
 519		intel_finish_page_flip_plane(dev, 1);
 
 
 520	}
 521
 522	if (de_iir & DE_PIPEA_VBLANK_IVB)
 523		drm_handle_vblank(dev, 0);
 
 524
 525	if (de_iir & DE_PIPEB_VBLANK_IVB)
 526		drm_handle_vblank(dev, 1);
 527
 528	/* check event from PCH */
 529	if (de_iir & DE_PCH_EVENT_IVB) {
 530		if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 531			queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 532		pch_irq_handler(dev);
 533	}
 534
 535	if (pm_iir & GEN6_PM_DEFERRED_EVENTS) {
 536		unsigned long flags;
 537		spin_lock_irqsave(&dev_priv->rps_lock, flags);
 538		WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
 539		I915_WRITE(GEN6_PMIMR, pm_iir);
 540		dev_priv->pm_iir |= pm_iir;
 541		spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
 542		queue_work(dev_priv->wq, &dev_priv->rps_work);
 543	}
 544
 545	/* should clear PCH hotplug event before clear CPU irq */
 546	I915_WRITE(SDEIIR, pch_iir);
 547	I915_WRITE(GTIIR, gt_iir);
 548	I915_WRITE(DEIIR, de_iir);
 549	I915_WRITE(GEN6_PMIIR, pm_iir);
 550
 551done:
 552	I915_WRITE(DEIER, de_ier);
 553	POSTING_READ(DEIER);
 
 
 
 
 
 
 
 
 
 
 554
 555	return ret;
 
 
 
 
 
 
 
 556}
 557
 558static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
 559{
 560	struct drm_device *dev = (struct drm_device *) arg;
 561	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 562	int ret = IRQ_NONE;
 563	u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 564	u32 hotplug_mask;
 565	struct drm_i915_master_private *master_priv;
 566	u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
 
 
 
 
 
 
 567
 568	atomic_inc(&dev_priv->irq_received);
 
 
 
 
 
 
 
 
 569
 570	if (IS_GEN6(dev))
 571		bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
 
 
 
 
 
 
 
 
 
 
 
 572
 573	/* disable master interrupt before clearing iir  */
 574	de_ier = I915_READ(DEIER);
 575	I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 576	POSTING_READ(DEIER);
 
 
 
 
 
 
 
 
 
 577
 578	de_iir = I915_READ(DEIIR);
 579	gt_iir = I915_READ(GTIIR);
 580	pch_iir = I915_READ(SDEIIR);
 581	pm_iir = I915_READ(GEN6_PMIIR);
 
 
 
 
 
 
 
 
 
 
 582
 583	if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
 584	    (!IS_GEN6(dev) || pm_iir == 0))
 585		goto done;
 586
 587	if (HAS_PCH_CPT(dev))
 588		hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 589	else
 590		hotplug_mask = SDE_HOTPLUG_MASK;
 591
 592	ret = IRQ_HANDLED;
 
 593
 594	if (dev->primary->master) {
 595		master_priv = dev->primary->master->driver_priv;
 596		if (master_priv->sarea_priv)
 597			master_priv->sarea_priv->last_dispatch =
 598				READ_BREADCRUMB(dev_priv);
 599	}
 600
 601	if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 602		notify_ring(dev, &dev_priv->ring[RCS]);
 603	if (gt_iir & bsd_usr_interrupt)
 604		notify_ring(dev, &dev_priv->ring[VCS]);
 605	if (gt_iir & GT_BLT_USER_INTERRUPT)
 606		notify_ring(dev, &dev_priv->ring[BCS]);
 607
 608	if (de_iir & DE_GSE)
 609		intel_opregion_gse_intr(dev);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 610
 611	if (de_iir & DE_PLANEA_FLIP_DONE) {
 612		intel_prepare_page_flip(dev, 0);
 613		intel_finish_page_flip_plane(dev, 0);
 
 614	}
 615
 616	if (de_iir & DE_PLANEB_FLIP_DONE) {
 617		intel_prepare_page_flip(dev, 1);
 618		intel_finish_page_flip_plane(dev, 1);
 
 
 
 
 619	}
 620
 621	if (de_iir & DE_PIPEA_VBLANK)
 622		drm_handle_vblank(dev, 0);
 623
 624	if (de_iir & DE_PIPEB_VBLANK)
 625		drm_handle_vblank(dev, 1);
 
 
 
 
 
 626
 627	/* check event from PCH */
 628	if (de_iir & DE_PCH_EVENT) {
 629		if (pch_iir & hotplug_mask)
 630			queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 631		pch_irq_handler(dev);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 632	}
 633
 634	if (de_iir & DE_PCU_EVENT) {
 635		I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 636		i915_handle_rps_change(dev);
 
 
 
 
 
 
 637	}
 
 638
 639	if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) {
 640		/*
 641		 * IIR bits should never already be set because IMR should
 642		 * prevent an interrupt from being shown in IIR. The warning
 643		 * displays a case where we've unsafely cleared
 644		 * dev_priv->pm_iir. Although missing an interrupt of the same
 645		 * type is not a problem, it displays a problem in the logic.
 646		 *
 647		 * The mask bit in IMR is cleared by rps_work.
 
 
 
 648		 */
 649		unsigned long flags;
 650		spin_lock_irqsave(&dev_priv->rps_lock, flags);
 651		WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
 652		I915_WRITE(GEN6_PMIMR, pm_iir);
 653		dev_priv->pm_iir |= pm_iir;
 654		spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
 655		queue_work(dev_priv->wq, &dev_priv->rps_work);
 656	}
 657
 658	/* should clear PCH hotplug event before clear CPU irq */
 659	I915_WRITE(SDEIIR, pch_iir);
 660	I915_WRITE(GTIIR, gt_iir);
 661	I915_WRITE(DEIIR, de_iir);
 662	I915_WRITE(GEN6_PMIIR, pm_iir);
 663
 664done:
 665	I915_WRITE(DEIER, de_ier);
 666	POSTING_READ(DEIER);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 667
 668	return ret;
 669}
 670
 671/**
 672 * i915_error_work_func - do process context error handling work
 673 * @work: work struct
 674 *
 675 * Fire an error uevent so userspace can see that a hang or error
 676 * was detected.
 677 */
 678static void i915_error_work_func(struct work_struct *work)
 679{
 680	drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 681						    error_work);
 682	struct drm_device *dev = dev_priv->dev;
 683	char *error_event[] = { "ERROR=1", NULL };
 684	char *reset_event[] = { "RESET=1", NULL };
 685	char *reset_done_event[] = { "ERROR=0", NULL };
 686
 687	kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 688
 689	if (atomic_read(&dev_priv->mm.wedged)) {
 690		DRM_DEBUG_DRIVER("resetting chip\n");
 691		kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 692		if (!i915_reset(dev, GRDOM_RENDER)) {
 693			atomic_set(&dev_priv->mm.wedged, 0);
 694			kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 695		}
 696		complete_all(&dev_priv->error_completion);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 697	}
 
 698}
 699
 700#ifdef CONFIG_DEBUG_FS
 701static struct drm_i915_error_object *
 702i915_error_object_create(struct drm_i915_private *dev_priv,
 703			 struct drm_i915_gem_object *src)
 704{
 705	struct drm_i915_error_object *dst;
 706	int page, page_count;
 707	u32 reloc_offset;
 708
 709	if (src == NULL || src->pages == NULL)
 710		return NULL;
 
 
 711
 712	page_count = src->base.size / PAGE_SIZE;
 
 713
 714	dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 715	if (dst == NULL)
 716		return NULL;
 717
 718	reloc_offset = src->gtt_offset;
 719	for (page = 0; page < page_count; page++) {
 720		unsigned long flags;
 721		void __iomem *s;
 722		void *d;
 723
 724		d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 725		if (d == NULL)
 726			goto unwind;
 727
 728		local_irq_save(flags);
 729		s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 730					     reloc_offset);
 731		memcpy_fromio(d, s, PAGE_SIZE);
 732		io_mapping_unmap_atomic(s);
 733		local_irq_restore(flags);
 734
 735		dst->pages[page] = d;
 
 736
 737		reloc_offset += PAGE_SIZE;
 738	}
 739	dst->page_count = page_count;
 740	dst->gtt_offset = src->gtt_offset;
 741
 742	return dst;
 
 
 
 
 
 
 
 
 
 
 
 
 743
 744unwind:
 745	while (page--)
 746		kfree(dst->pages[page]);
 747	kfree(dst);
 748	return NULL;
 
 
 
 
 
 
 
 
 
 
 749}
 750
 751static void
 752i915_error_object_free(struct drm_i915_error_object *obj)
 753{
 754	int page;
 
 
 755
 756	if (obj == NULL)
 757		return;
 758
 759	for (page = 0; page < obj->page_count; page++)
 760		kfree(obj->pages[page]);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 761
 762	kfree(obj);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 763}
 764
 765static void
 766i915_error_state_free(struct drm_device *dev,
 767		      struct drm_i915_error_state *error)
 768{
 769	int i;
 
 
 770
 771	for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++)
 772		i915_error_object_free(error->batchbuffer[i]);
 773
 774	for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++)
 775		i915_error_object_free(error->ringbuffer[i]);
 776
 777	kfree(error->active_bo);
 778	kfree(error->overlay);
 779	kfree(error);
 780}
 781
 782static u32 capture_bo_list(struct drm_i915_error_buffer *err,
 783			   int count,
 784			   struct list_head *head)
 785{
 786	struct drm_i915_gem_object *obj;
 787	int i = 0;
 788
 789	list_for_each_entry(obj, head, mm_list) {
 790		err->size = obj->base.size;
 791		err->name = obj->base.name;
 792		err->seqno = obj->last_rendering_seqno;
 793		err->gtt_offset = obj->gtt_offset;
 794		err->read_domains = obj->base.read_domains;
 795		err->write_domain = obj->base.write_domain;
 796		err->fence_reg = obj->fence_reg;
 797		err->pinned = 0;
 798		if (obj->pin_count > 0)
 799			err->pinned = 1;
 800		if (obj->user_pin_count > 0)
 801			err->pinned = -1;
 802		err->tiling = obj->tiling_mode;
 803		err->dirty = obj->dirty;
 804		err->purgeable = obj->madv != I915_MADV_WILLNEED;
 805		err->ring = obj->ring ? obj->ring->id : 0;
 806		err->cache_level = obj->cache_level;
 807
 808		if (++i == count)
 809			break;
 810
 811		err++;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 812	}
 813
 814	return i;
 
 
 
 
 
 
 
 
 815}
 816
 817static void i915_gem_record_fences(struct drm_device *dev,
 818				   struct drm_i915_error_state *error)
 819{
 820	struct drm_i915_private *dev_priv = dev->dev_private;
 821	int i;
 822
 823	/* Fences */
 824	switch (INTEL_INFO(dev)->gen) {
 825	case 6:
 826		for (i = 0; i < 16; i++)
 827			error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
 828		break;
 829	case 5:
 830	case 4:
 831		for (i = 0; i < 16; i++)
 832			error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 833		break;
 834	case 3:
 835		if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 836			for (i = 0; i < 8; i++)
 837				error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
 838	case 2:
 839		for (i = 0; i < 8; i++)
 840			error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
 841		break;
 842
 
 
 
 
 
 843	}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 844}
 845
 846static struct drm_i915_error_object *
 847i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
 848			     struct intel_ring_buffer *ring)
 849{
 850	struct drm_i915_gem_object *obj;
 851	u32 seqno;
 852
 853	if (!ring->get_seqno)
 854		return NULL;
 855
 856	seqno = ring->get_seqno(ring);
 857	list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
 858		if (obj->ring != ring)
 859			continue;
 860
 861		if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
 862			continue;
 863
 864		if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
 865			continue;
 
 866
 867		/* We need to copy these to an anonymous buffer as the simplest
 868		 * method to avoid being overwritten by userspace.
 869		 */
 870		return i915_error_object_create(dev_priv, obj);
 
 
 871	}
 872
 873	return NULL;
 874}
 875
 876/**
 877 * i915_capture_error_state - capture an error record for later analysis
 878 * @dev: drm device
 879 *
 880 * Should be called when an error is detected (either a hang or an error
 881 * interrupt) to capture error state from the time of the error.  Fills
 882 * out a structure which becomes available in debugfs for user level tools
 883 * to pick up.
 884 */
 885static void i915_capture_error_state(struct drm_device *dev)
 886{
 887	struct drm_i915_private *dev_priv = dev->dev_private;
 888	struct drm_i915_gem_object *obj;
 889	struct drm_i915_error_state *error;
 890	unsigned long flags;
 891	int i, pipe;
 892
 893	spin_lock_irqsave(&dev_priv->error_lock, flags);
 894	error = dev_priv->first_error;
 895	spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 896	if (error)
 897		return;
 898
 899	/* Account for pipe specific data like PIPE*STAT */
 900	error = kmalloc(sizeof(*error), GFP_ATOMIC);
 901	if (!error) {
 902		DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 903		return;
 904	}
 905
 906	DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
 907		 dev->primary->index);
 908
 909	error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]);
 910	error->eir = I915_READ(EIR);
 911	error->pgtbl_er = I915_READ(PGTBL_ER);
 912	for_each_pipe(pipe)
 913		error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
 914	error->instpm = I915_READ(INSTPM);
 915	error->error = 0;
 916	if (INTEL_INFO(dev)->gen >= 6) {
 917		error->error = I915_READ(ERROR_GEN6);
 918
 919		error->bcs_acthd = I915_READ(BCS_ACTHD);
 920		error->bcs_ipehr = I915_READ(BCS_IPEHR);
 921		error->bcs_ipeir = I915_READ(BCS_IPEIR);
 922		error->bcs_instdone = I915_READ(BCS_INSTDONE);
 923		error->bcs_seqno = 0;
 924		if (dev_priv->ring[BCS].get_seqno)
 925			error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]);
 926
 927		error->vcs_acthd = I915_READ(VCS_ACTHD);
 928		error->vcs_ipehr = I915_READ(VCS_IPEHR);
 929		error->vcs_ipeir = I915_READ(VCS_IPEIR);
 930		error->vcs_instdone = I915_READ(VCS_INSTDONE);
 931		error->vcs_seqno = 0;
 932		if (dev_priv->ring[VCS].get_seqno)
 933			error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]);
 934	}
 935	if (INTEL_INFO(dev)->gen >= 4) {
 936		error->ipeir = I915_READ(IPEIR_I965);
 937		error->ipehr = I915_READ(IPEHR_I965);
 938		error->instdone = I915_READ(INSTDONE_I965);
 939		error->instps = I915_READ(INSTPS);
 940		error->instdone1 = I915_READ(INSTDONE1);
 941		error->acthd = I915_READ(ACTHD_I965);
 942		error->bbaddr = I915_READ64(BB_ADDR);
 943	} else {
 944		error->ipeir = I915_READ(IPEIR);
 945		error->ipehr = I915_READ(IPEHR);
 946		error->instdone = I915_READ(INSTDONE);
 947		error->acthd = I915_READ(ACTHD);
 948		error->bbaddr = 0;
 949	}
 950	i915_gem_record_fences(dev, error);
 951
 952	/* Record the active batch and ring buffers */
 953	for (i = 0; i < I915_NUM_RINGS; i++) {
 954		error->batchbuffer[i] =
 955			i915_error_first_batchbuffer(dev_priv,
 956						     &dev_priv->ring[i]);
 957
 958		error->ringbuffer[i] =
 959			i915_error_object_create(dev_priv,
 960						 dev_priv->ring[i].obj);
 961	}
 962
 963	/* Record buffers on the active and pinned lists. */
 964	error->active_bo = NULL;
 965	error->pinned_bo = NULL;
 966
 967	i = 0;
 968	list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
 969		i++;
 970	error->active_bo_count = i;
 971	list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 972		i++;
 973	error->pinned_bo_count = i - error->active_bo_count;
 974
 975	error->active_bo = NULL;
 976	error->pinned_bo = NULL;
 977	if (i) {
 978		error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
 979					   GFP_ATOMIC);
 980		if (error->active_bo)
 981			error->pinned_bo =
 982				error->active_bo + error->active_bo_count;
 983	}
 984
 985	if (error->active_bo)
 986		error->active_bo_count =
 987			capture_bo_list(error->active_bo,
 988					error->active_bo_count,
 989					&dev_priv->mm.active_list);
 990
 991	if (error->pinned_bo)
 992		error->pinned_bo_count =
 993			capture_bo_list(error->pinned_bo,
 994					error->pinned_bo_count,
 995					&dev_priv->mm.pinned_list);
 996
 997	do_gettimeofday(&error->time);
 998
 999	error->overlay = intel_overlay_capture_error_state(dev);
1000	error->display = intel_display_capture_error_state(dev);
1001
1002	spin_lock_irqsave(&dev_priv->error_lock, flags);
1003	if (dev_priv->first_error == NULL) {
1004		dev_priv->first_error = error;
1005		error = NULL;
1006	}
1007	spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1008
1009	if (error)
1010		i915_error_state_free(dev, error);
1011}
1012
1013void i915_destroy_error_state(struct drm_device *dev)
1014{
1015	struct drm_i915_private *dev_priv = dev->dev_private;
1016	struct drm_i915_error_state *error;
1017
1018	spin_lock(&dev_priv->error_lock);
1019	error = dev_priv->first_error;
1020	dev_priv->first_error = NULL;
1021	spin_unlock(&dev_priv->error_lock);
1022
1023	if (error)
1024		i915_error_state_free(dev, error);
 
 
 
 
 
1025}
1026#else
1027#define i915_capture_error_state(x)
1028#endif
1029
1030static void i915_report_and_clear_eir(struct drm_device *dev)
1031{
1032	struct drm_i915_private *dev_priv = dev->dev_private;
1033	u32 eir = I915_READ(EIR);
1034	int pipe;
 
1035
1036	if (!eir)
1037		return;
1038
1039	printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
1040	       eir);
 
 
 
 
1041
1042	if (IS_G4X(dev)) {
1043		if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1044			u32 ipeir = I915_READ(IPEIR_I965);
1045
1046			printk(KERN_ERR "  IPEIR: 0x%08x\n",
1047			       I915_READ(IPEIR_I965));
1048			printk(KERN_ERR "  IPEHR: 0x%08x\n",
1049			       I915_READ(IPEHR_I965));
1050			printk(KERN_ERR "  INSTDONE: 0x%08x\n",
1051			       I915_READ(INSTDONE_I965));
1052			printk(KERN_ERR "  INSTPS: 0x%08x\n",
1053			       I915_READ(INSTPS));
1054			printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
1055			       I915_READ(INSTDONE1));
1056			printk(KERN_ERR "  ACTHD: 0x%08x\n",
1057			       I915_READ(ACTHD_I965));
1058			I915_WRITE(IPEIR_I965, ipeir);
1059			POSTING_READ(IPEIR_I965);
1060		}
1061		if (eir & GM45_ERROR_PAGE_TABLE) {
1062			u32 pgtbl_err = I915_READ(PGTBL_ER);
1063			printk(KERN_ERR "page table error\n");
1064			printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
1065			       pgtbl_err);
1066			I915_WRITE(PGTBL_ER, pgtbl_err);
1067			POSTING_READ(PGTBL_ER);
1068		}
1069	}
1070
1071	if (!IS_GEN2(dev)) {
1072		if (eir & I915_ERROR_PAGE_TABLE) {
1073			u32 pgtbl_err = I915_READ(PGTBL_ER);
1074			printk(KERN_ERR "page table error\n");
1075			printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
1076			       pgtbl_err);
1077			I915_WRITE(PGTBL_ER, pgtbl_err);
1078			POSTING_READ(PGTBL_ER);
1079		}
1080	}
1081
1082	if (eir & I915_ERROR_MEMORY_REFRESH) {
1083		printk(KERN_ERR "memory refresh error:\n");
1084		for_each_pipe(pipe)
1085			printk(KERN_ERR "pipe %c stat: 0x%08x\n",
1086			       pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1087		/* pipestat has already been acked */
1088	}
1089	if (eir & I915_ERROR_INSTRUCTION) {
1090		printk(KERN_ERR "instruction error\n");
1091		printk(KERN_ERR "  INSTPM: 0x%08x\n",
1092		       I915_READ(INSTPM));
1093		if (INTEL_INFO(dev)->gen < 4) {
1094			u32 ipeir = I915_READ(IPEIR);
1095
1096			printk(KERN_ERR "  IPEIR: 0x%08x\n",
1097			       I915_READ(IPEIR));
1098			printk(KERN_ERR "  IPEHR: 0x%08x\n",
1099			       I915_READ(IPEHR));
1100			printk(KERN_ERR "  INSTDONE: 0x%08x\n",
1101			       I915_READ(INSTDONE));
1102			printk(KERN_ERR "  ACTHD: 0x%08x\n",
1103			       I915_READ(ACTHD));
1104			I915_WRITE(IPEIR, ipeir);
1105			POSTING_READ(IPEIR);
1106		} else {
1107			u32 ipeir = I915_READ(IPEIR_I965);
1108
1109			printk(KERN_ERR "  IPEIR: 0x%08x\n",
1110			       I915_READ(IPEIR_I965));
1111			printk(KERN_ERR "  IPEHR: 0x%08x\n",
1112			       I915_READ(IPEHR_I965));
1113			printk(KERN_ERR "  INSTDONE: 0x%08x\n",
1114			       I915_READ(INSTDONE_I965));
1115			printk(KERN_ERR "  INSTPS: 0x%08x\n",
1116			       I915_READ(INSTPS));
1117			printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
1118			       I915_READ(INSTDONE1));
1119			printk(KERN_ERR "  ACTHD: 0x%08x\n",
1120			       I915_READ(ACTHD_I965));
1121			I915_WRITE(IPEIR_I965, ipeir);
1122			POSTING_READ(IPEIR_I965);
1123		}
1124	}
1125
1126	I915_WRITE(EIR, eir);
1127	POSTING_READ(EIR);
1128	eir = I915_READ(EIR);
1129	if (eir) {
1130		/*
1131		 * some errors might have become stuck,
1132		 * mask them.
1133		 */
1134		DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1135		I915_WRITE(EMR, I915_READ(EMR) | eir);
1136		I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1137	}
 
 
1138}
1139
1140/**
1141 * i915_handle_error - handle an error interrupt
1142 * @dev: drm device
1143 *
1144 * Do some basic checking of regsiter state at error interrupt time and
1145 * dump it to the syslog.  Also call i915_capture_error_state() to make
1146 * sure we get a record and make it available in debugfs.  Fire a uevent
1147 * so userspace knows something bad happened (should trigger collection
1148 * of a ring dump etc.).
1149 */
1150void i915_handle_error(struct drm_device *dev, bool wedged)
1151{
1152	struct drm_i915_private *dev_priv = dev->dev_private;
 
 
 
1153
1154	i915_capture_error_state(dev);
1155	i915_report_and_clear_eir(dev);
1156
1157	if (wedged) {
1158		INIT_COMPLETION(dev_priv->error_completion);
1159		atomic_set(&dev_priv->mm.wedged, 1);
1160
1161		/*
1162		 * Wakeup waiting processes so they don't hang
1163		 */
1164		wake_up_all(&dev_priv->ring[RCS].irq_queue);
1165		if (HAS_BSD(dev))
1166			wake_up_all(&dev_priv->ring[VCS].irq_queue);
1167		if (HAS_BLT(dev))
1168			wake_up_all(&dev_priv->ring[BCS].irq_queue);
 
 
 
 
 
 
1169	}
1170
1171	queue_work(dev_priv->wq, &dev_priv->error_work);
 
 
 
 
1172}
1173
1174static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
 
 
1175{
1176	drm_i915_private_t *dev_priv = dev->dev_private;
1177	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1178	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1179	struct drm_i915_gem_object *obj;
1180	struct intel_unpin_work *work;
1181	unsigned long flags;
1182	bool stall_detected;
1183
1184	/* Ignore early vblank irqs */
1185	if (intel_crtc == NULL)
1186		return;
1187
1188	spin_lock_irqsave(&dev->event_lock, flags);
1189	work = intel_crtc->unpin_work;
 
1190
1191	if (work == NULL || work->pending || !work->enable_stall_check) {
1192		/* Either the pending flip IRQ arrived, or we're too early. Don't check */
1193		spin_unlock_irqrestore(&dev->event_lock, flags);
1194		return;
1195	}
1196
1197	/* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1198	obj = work->pending_flip_obj;
1199	if (INTEL_INFO(dev)->gen >= 4) {
1200		int dspsurf = DSPSURF(intel_crtc->plane);
1201		stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
1202	} else {
1203		int dspaddr = DSPADDR(intel_crtc->plane);
1204		stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1205							crtc->y * crtc->fb->pitch +
1206							crtc->x * crtc->fb->bits_per_pixel/8);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1207	}
1208
1209	spin_unlock_irqrestore(&dev->event_lock, flags);
 
 
 
 
 
 
 
1210
1211	if (stall_detected) {
1212		DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1213		intel_prepare_page_flip(dev, intel_crtc->plane);
1214	}
 
 
 
1215}
1216
1217static irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 
1218{
1219	struct drm_device *dev = (struct drm_device *) arg;
1220	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1221	struct drm_i915_master_private *master_priv;
1222	u32 iir, new_iir;
1223	u32 pipe_stats[I915_MAX_PIPES];
1224	u32 vblank_status;
1225	int vblank = 0;
1226	unsigned long irqflags;
1227	int irq_received;
1228	int ret = IRQ_NONE, pipe;
1229	bool blc_event = false;
1230
1231	atomic_inc(&dev_priv->irq_received);
 
1232
1233	iir = I915_READ(IIR);
 
1234
1235	if (INTEL_INFO(dev)->gen >= 4)
1236		vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
1237	else
1238		vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
1239
1240	for (;;) {
1241		irq_received = iir != 0;
1242
1243		/* Can't rely on pipestat interrupt bit in iir as it might
1244		 * have been cleared after the pipestat interrupt was received.
1245		 * It doesn't set the bit in iir again, but it still produces
1246		 * interrupts (for non-MSI).
1247		 */
1248		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1249		if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1250			i915_handle_error(dev, false);
 
1251
1252		for_each_pipe(pipe) {
1253			int reg = PIPESTAT(pipe);
1254			pipe_stats[pipe] = I915_READ(reg);
1255
1256			/*
1257			 * Clear the PIPE*STAT regs before the IIR
1258			 */
1259			if (pipe_stats[pipe] & 0x8000ffff) {
1260				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1261					DRM_DEBUG_DRIVER("pipe %c underrun\n",
1262							 pipe_name(pipe));
1263				I915_WRITE(reg, pipe_stats[pipe]);
1264				irq_received = 1;
1265			}
1266		}
1267		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1268
1269		if (!irq_received)
1270			break;
 
 
1271
1272		ret = IRQ_HANDLED;
 
 
 
 
 
 
 
 
 
 
 
 
 
1273
1274		/* Consume port.  Then clear IIR or we'll miss events */
1275		if ((I915_HAS_HOTPLUG(dev)) &&
1276		    (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1277			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1278
1279			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1280				  hotplug_status);
1281			if (hotplug_status & dev_priv->hotplug_supported_mask)
1282				queue_work(dev_priv->wq,
1283					   &dev_priv->hotplug_work);
1284
1285			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1286			I915_READ(PORT_HOTPLUG_STAT);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1287		}
 
1288
1289		I915_WRITE(IIR, iir);
1290		new_iir = I915_READ(IIR); /* Flush posted writes */
 
 
 
 
 
 
 
1291
1292		if (dev->primary->master) {
1293			master_priv = dev->primary->master->driver_priv;
1294			if (master_priv->sarea_priv)
1295				master_priv->sarea_priv->last_dispatch =
1296					READ_BREADCRUMB(dev_priv);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1297		}
 
 
 
1298
1299		if (iir & I915_USER_INTERRUPT)
1300			notify_ring(dev, &dev_priv->ring[RCS]);
1301		if (iir & I915_BSD_USER_INTERRUPT)
1302			notify_ring(dev, &dev_priv->ring[VCS]);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1303
1304		if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1305			intel_prepare_page_flip(dev, 0);
1306			if (dev_priv->flip_pending_is_done)
1307				intel_finish_page_flip_plane(dev, 0);
1308		}
1309
1310		if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1311			intel_prepare_page_flip(dev, 1);
1312			if (dev_priv->flip_pending_is_done)
1313				intel_finish_page_flip_plane(dev, 1);
1314		}
1315
1316		for_each_pipe(pipe) {
1317			if (pipe_stats[pipe] & vblank_status &&
1318			    drm_handle_vblank(dev, pipe)) {
1319				vblank++;
1320				if (!dev_priv->flip_pending_is_done) {
1321					i915_pageflip_stall_check(dev, pipe);
1322					intel_finish_page_flip(dev, pipe);
1323				}
1324			}
1325
1326			if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1327				blc_event = true;
 
 
 
 
 
1328		}
 
 
 
1329
 
 
1330
1331		if (blc_event || (iir & I915_ASLE_INTERRUPT))
1332			intel_opregion_asle_intr(dev);
1333
1334		/* With MSI, interrupts are only generated when iir
1335		 * transitions from zero to nonzero.  If another bit got
1336		 * set while we were handling the existing iir bits, then
1337		 * we would never get another interrupt.
1338		 *
1339		 * This is fine on non-MSI as well, as if we hit this path
1340		 * we avoid exiting the interrupt handler only to generate
1341		 * another one.
1342		 *
1343		 * Note that for MSI this could cause a stray interrupt report
1344		 * if an interrupt landed in the time between writing IIR and
1345		 * the posting read.  This should be rare enough to never
1346		 * trigger the 99% of 100,000 interrupts test for disabling
1347		 * stray interrupts.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1348		 */
1349		iir = new_iir;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1350	}
1351
1352	return ret;
1353}
1354
1355static int i915_emit_irq(struct drm_device * dev)
1356{
1357	drm_i915_private_t *dev_priv = dev->dev_private;
1358	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 
 
 
1359
1360	i915_kernel_lost_context(dev);
 
1361
1362	DRM_DEBUG_DRIVER("\n");
 
 
 
1363
1364	dev_priv->counter++;
1365	if (dev_priv->counter > 0x7FFFFFFFUL)
1366		dev_priv->counter = 1;
1367	if (master_priv->sarea_priv)
1368		master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1369
1370	if (BEGIN_LP_RING(4) == 0) {
1371		OUT_RING(MI_STORE_DWORD_INDEX);
1372		OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1373		OUT_RING(dev_priv->counter);
1374		OUT_RING(MI_USER_INTERRUPT);
1375		ADVANCE_LP_RING();
1376	}
1377
1378	return dev_priv->counter;
 
 
 
 
 
1379}
1380
1381static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1382{
1383	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1384	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1385	int ret = 0;
1386	struct intel_ring_buffer *ring = LP_RING(dev_priv);
 
 
1387
1388	DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1389		  READ_BREADCRUMB(dev_priv));
1390
1391	if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1392		if (master_priv->sarea_priv)
1393			master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1394		return 0;
1395	}
1396
1397	if (master_priv->sarea_priv)
1398		master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 
 
 
 
 
 
 
 
 
 
 
1399
1400	if (ring->irq_get(ring)) {
1401		DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1402			    READ_BREADCRUMB(dev_priv) >= irq_nr);
1403		ring->irq_put(ring);
1404	} else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
1405		ret = -EBUSY;
1406
1407	if (ret == -EBUSY) {
1408		DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1409			  READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1410	}
1411
1412	return ret;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1413}
1414
1415/* Needs the lock as it touches the ring.
1416 */
1417int i915_irq_emit(struct drm_device *dev, void *data,
1418			 struct drm_file *file_priv)
1419{
1420	drm_i915_private_t *dev_priv = dev->dev_private;
1421	drm_i915_irq_emit_t *emit = data;
1422	int result;
1423
1424	if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
1425		DRM_ERROR("called with no initialization\n");
1426		return -EINVAL;
1427	}
1428
1429	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 
1430
1431	mutex_lock(&dev->struct_mutex);
1432	result = i915_emit_irq(dev);
1433	mutex_unlock(&dev->struct_mutex);
1434
1435	if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1436		DRM_ERROR("copy_to_user\n");
1437		return -EFAULT;
1438	}
1439
1440	return 0;
 
 
 
 
 
 
 
 
 
1441}
1442
1443/* Doesn't need the hardware lock.
1444 */
1445int i915_irq_wait(struct drm_device *dev, void *data,
1446			 struct drm_file *file_priv)
1447{
1448	drm_i915_private_t *dev_priv = dev->dev_private;
1449	drm_i915_irq_wait_t *irqwait = data;
1450
1451	if (!dev_priv) {
1452		DRM_ERROR("called with no initialization\n");
1453		return -EINVAL;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1454	}
 
1455
1456	return i915_wait_irq(dev, irqwait->irq_seq);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1457}
1458
1459/* Called from drm generic code, passed 'crtc' which
1460 * we use as a pipe index
1461 */
1462static int i915_enable_vblank(struct drm_device *dev, int pipe)
1463{
1464	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1465	unsigned long irqflags;
1466
1467	if (!i915_pipe_enabled(dev, pipe))
1468		return -EINVAL;
1469
1470	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1471	if (INTEL_INFO(dev)->gen >= 4)
1472		i915_enable_pipestat(dev_priv, pipe,
1473				     PIPE_START_VBLANK_INTERRUPT_ENABLE);
1474	else
1475		i915_enable_pipestat(dev_priv, pipe,
1476				     PIPE_VBLANK_INTERRUPT_ENABLE);
1477
1478	/* maintain vblank delivery even in deep C-states */
1479	if (dev_priv->info->gen == 3)
1480		I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16);
1481	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1482
1483	return 0;
1484}
1485
1486static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1487{
1488	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1489	unsigned long irqflags;
1490
1491	if (!i915_pipe_enabled(dev, pipe))
1492		return -EINVAL;
1493
1494	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1495	ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1496				    DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1497	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1498
1499	return 0;
1500}
1501
1502static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1503{
1504	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1505	unsigned long irqflags;
 
 
1506
1507	if (!i915_pipe_enabled(dev, pipe))
1508		return -EINVAL;
 
 
 
 
 
 
 
 
 
1509
1510	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1511	ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1512				    DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1513	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1514
1515	return 0;
1516}
1517
1518/* Called from drm generic code, passed 'crtc' which
1519 * we use as a pipe index
1520 */
1521static void i915_disable_vblank(struct drm_device *dev, int pipe)
1522{
1523	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1524	unsigned long irqflags;
1525
1526	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1527	if (dev_priv->info->gen == 3)
1528		I915_WRITE(INSTPM,
1529			   INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS);
 
 
 
 
 
1530
 
1531	i915_disable_pipestat(dev_priv, pipe,
1532			      PIPE_VBLANK_INTERRUPT_ENABLE |
1533			      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1534	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1535}
1536
1537static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1538{
1539	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1540	unsigned long irqflags;
 
 
1541
1542	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1543	ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1544				     DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1545	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1546}
1547
1548static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1549{
1550	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1551	unsigned long irqflags;
1552
1553	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1554	ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1555				     DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1556	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1557}
1558
1559/* Set the vblank monitor pipe
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1560 */
1561int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1562			 struct drm_file *file_priv)
1563{
1564	drm_i915_private_t *dev_priv = dev->dev_private;
1565
1566	if (!dev_priv) {
1567		DRM_ERROR("called with no initialization\n");
1568		return -EINVAL;
1569	}
1570
1571	return 0;
 
 
1572}
1573
1574int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1575			 struct drm_file *file_priv)
1576{
1577	drm_i915_private_t *dev_priv = dev->dev_private;
1578	drm_i915_vblank_pipe_t *pipe = data;
 
 
1579
1580	if (!dev_priv) {
1581		DRM_ERROR("called with no initialization\n");
1582		return -EINVAL;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1583	}
1584
1585	pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 
 
1586
1587	return 0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1588}
1589
1590/**
1591 * Schedule buffer swap at given vertical blank.
1592 */
1593int i915_vblank_swap(struct drm_device *dev, void *data,
1594		     struct drm_file *file_priv)
1595{
1596	/* The delayed swap mechanism was fundamentally racy, and has been
1597	 * removed.  The model was that the client requested a delayed flip/swap
1598	 * from the kernel, then waited for vblank before continuing to perform
1599	 * rendering.  The problem was that the kernel might wake the client
1600	 * up before it dispatched the vblank swap (since the lock has to be
1601	 * held while touching the ringbuffer), in which case the client would
1602	 * clear and start the next frame before the swap occurred, and
1603	 * flicker would occur in addition to likely missing the vblank.
1604	 *
1605	 * In the absence of this ioctl, userland falls back to a correct path
1606	 * of waiting for a vblank, then dispatching the swap on its own.
1607	 * Context switching to userland and back is plenty fast enough for
1608	 * meeting the requirements of vblank swapping.
1609	 */
1610	return -EINVAL;
 
 
 
 
 
 
 
 
 
 
 
1611}
1612
1613static u32
1614ring_last_seqno(struct intel_ring_buffer *ring)
1615{
1616	return list_entry(ring->request_list.prev,
1617			  struct drm_i915_gem_request, list)->seqno;
 
 
1618}
1619
1620static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1621{
1622	if (list_empty(&ring->request_list) ||
1623	    i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1624		/* Issue a wake-up to catch stuck h/w. */
1625		if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1626			DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1627				  ring->name,
1628				  ring->waiting_seqno,
1629				  ring->get_seqno(ring));
1630			wake_up_all(&ring->irq_queue);
1631			*err = true;
1632		}
1633		return true;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1634	}
1635	return false;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1636}
1637
1638static bool kick_ring(struct intel_ring_buffer *ring)
1639{
1640	struct drm_device *dev = ring->dev;
1641	struct drm_i915_private *dev_priv = dev->dev_private;
1642	u32 tmp = I915_READ_CTL(ring);
1643	if (tmp & RING_WAIT) {
1644		DRM_ERROR("Kicking stuck wait on %s\n",
1645			  ring->name);
1646		I915_WRITE_CTL(ring, tmp);
1647		return true;
1648	}
1649	if (IS_GEN6(dev) &&
1650	    (tmp & RING_WAIT_SEMAPHORE)) {
1651		DRM_ERROR("Kicking stuck semaphore on %s\n",
1652			  ring->name);
1653		I915_WRITE_CTL(ring, tmp);
1654		return true;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1655	}
1656	return false;
 
 
 
 
 
 
 
 
 
 
 
1657}
1658
1659/**
1660 * This is called when the chip hasn't reported back with completed
1661 * batchbuffers in a long time. The first time this is called we simply record
1662 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1663 * again, we assume the chip is wedged and try to fix it.
1664 */
1665void i915_hangcheck_elapsed(unsigned long data)
1666{
1667	struct drm_device *dev = (struct drm_device *)data;
1668	drm_i915_private_t *dev_priv = dev->dev_private;
1669	uint32_t acthd, instdone, instdone1;
1670	bool err = false;
1671
1672	if (!i915_enable_hangcheck)
1673		return;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1674
1675	/* If all work is done then ACTHD clearly hasn't advanced. */
1676	if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1677	    i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1678	    i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
1679		dev_priv->hangcheck_count = 0;
1680		if (err)
1681			goto repeat;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1682		return;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1683	}
1684
1685	if (INTEL_INFO(dev)->gen < 4) {
1686		acthd = I915_READ(ACTHD);
1687		instdone = I915_READ(INSTDONE);
1688		instdone1 = 0;
1689	} else {
1690		acthd = I915_READ(ACTHD_I965);
1691		instdone = I915_READ(INSTDONE_I965);
1692		instdone1 = I915_READ(INSTDONE1);
1693	}
1694
1695	if (dev_priv->last_acthd == acthd &&
1696	    dev_priv->last_instdone == instdone &&
1697	    dev_priv->last_instdone1 == instdone1) {
1698		if (dev_priv->hangcheck_count++ > 1) {
1699			DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1700
1701			if (!IS_GEN2(dev)) {
1702				/* Is the chip hanging on a WAIT_FOR_EVENT?
1703				 * If so we can simply poke the RB_WAIT bit
1704				 * and break the hang. This should work on
1705				 * all but the second generation chipsets.
1706				 */
1707
1708				if (kick_ring(&dev_priv->ring[RCS]))
1709					goto repeat;
1710
1711				if (HAS_BSD(dev) &&
1712				    kick_ring(&dev_priv->ring[VCS]))
1713					goto repeat;
1714
1715				if (HAS_BLT(dev) &&
1716				    kick_ring(&dev_priv->ring[BCS]))
1717					goto repeat;
1718			}
1719
1720			i915_handle_error(dev, true);
1721			return;
 
 
 
 
 
 
1722		}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1723	} else {
1724		dev_priv->hangcheck_count = 0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1725
1726		dev_priv->last_acthd = acthd;
1727		dev_priv->last_instdone = instdone;
1728		dev_priv->last_instdone1 = instdone1;
 
 
 
 
 
 
1729	}
1730
1731repeat:
1732	/* Reset timer case chip hangs without another request being added */
1733	mod_timer(&dev_priv->hangcheck_timer,
1734		  jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1735}
1736
1737/* drm_dma.h hooks
1738*/
1739static void ironlake_irq_preinstall(struct drm_device *dev)
1740{
1741	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1742
1743	atomic_set(&dev_priv->irq_received, 0);
 
1744
1745	INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1746	INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1747	if (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
1748		INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
1749
1750	I915_WRITE(HWSTAM, 0xeffe);
1751	if (IS_GEN6(dev) || IS_GEN7(dev)) {
1752		/* Workaround stalls observed on Sandy Bridge GPUs by
1753		 * making the blitter command streamer generate a
1754		 * write to the Hardware Status Page for
1755		 * MI_USER_INTERRUPT.  This appears to serialize the
1756		 * previous seqno write out before the interrupt
1757		 * happens.
1758		 */
1759		I915_WRITE(GEN6_BLITTER_HWSTAM, ~GEN6_BLITTER_USER_INTERRUPT);
1760		I915_WRITE(GEN6_BSD_HWSTAM, ~GEN6_BSD_USER_INTERRUPT);
1761	}
 
1762
1763	/* XXX hotplug from PCH */
 
 
1764
1765	I915_WRITE(DEIMR, 0xffffffff);
1766	I915_WRITE(DEIER, 0x0);
1767	POSTING_READ(DEIER);
1768
1769	/* and GT */
1770	I915_WRITE(GTIMR, 0xffffffff);
1771	I915_WRITE(GTIER, 0x0);
1772	POSTING_READ(GTIER);
1773
1774	/* south display irq */
1775	I915_WRITE(SDEIMR, 0xffffffff);
1776	I915_WRITE(SDEIER, 0x0);
1777	POSTING_READ(SDEIER);
1778}
1779
1780static int ironlake_irq_postinstall(struct drm_device *dev)
 
1781{
1782	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1783	/* enable kind of interrupts always enabled */
1784	u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1785			   DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1786	u32 render_irqs;
1787	u32 hotplug_mask;
1788
1789	DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1790	if (HAS_BSD(dev))
1791		DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1792	if (HAS_BLT(dev))
1793		DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1794
1795	dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1796	dev_priv->irq_mask = ~display_mask;
1797
1798	/* should always can generate irq */
1799	I915_WRITE(DEIIR, I915_READ(DEIIR));
1800	I915_WRITE(DEIMR, dev_priv->irq_mask);
1801	I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1802	POSTING_READ(DEIER);
1803
1804	dev_priv->gt_irq_mask = ~0;
 
1805
1806	I915_WRITE(GTIIR, I915_READ(GTIIR));
1807	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1808
1809	if (IS_GEN6(dev))
1810		render_irqs =
1811			GT_USER_INTERRUPT |
1812			GT_GEN6_BSD_USER_INTERRUPT |
1813			GT_BLT_USER_INTERRUPT;
1814	else
1815		render_irqs =
1816			GT_USER_INTERRUPT |
1817			GT_PIPE_NOTIFY |
1818			GT_BSD_USER_INTERRUPT;
1819	I915_WRITE(GTIER, render_irqs);
1820	POSTING_READ(GTIER);
1821
1822	if (HAS_PCH_CPT(dev)) {
1823		hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1824				SDE_PORTB_HOTPLUG_CPT |
1825				SDE_PORTC_HOTPLUG_CPT |
1826				SDE_PORTD_HOTPLUG_CPT);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1827	} else {
1828		hotplug_mask = (SDE_CRT_HOTPLUG |
1829				SDE_PORTB_HOTPLUG |
1830				SDE_PORTC_HOTPLUG |
1831				SDE_PORTD_HOTPLUG |
1832				SDE_AUX_MASK);
1833	}
1834
1835	dev_priv->pch_irq_mask = ~hotplug_mask;
1836
1837	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1838	I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1839	I915_WRITE(SDEIER, hotplug_mask);
1840	POSTING_READ(SDEIER);
1841
1842	if (IS_IRONLAKE_M(dev)) {
1843		/* Clear & enable PCU event interrupts */
1844		I915_WRITE(DEIIR, DE_PCU_EVENT);
1845		I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1846		ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1847	}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1848
1849	return 0;
1850}
1851
1852static int ivybridge_irq_postinstall(struct drm_device *dev)
1853{
1854	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1855	/* enable kind of interrupts always enabled */
1856	u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
1857		DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
1858		DE_PLANEB_FLIP_DONE_IVB;
1859	u32 render_irqs;
1860	u32 hotplug_mask;
1861
1862	DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1863	if (HAS_BSD(dev))
1864		DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1865	if (HAS_BLT(dev))
1866		DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1867
1868	dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1869	dev_priv->irq_mask = ~display_mask;
1870
1871	/* should always can generate irq */
1872	I915_WRITE(DEIIR, I915_READ(DEIIR));
1873	I915_WRITE(DEIMR, dev_priv->irq_mask);
1874	I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
1875		   DE_PIPEB_VBLANK_IVB);
1876	POSTING_READ(DEIER);
1877
1878	dev_priv->gt_irq_mask = ~0;
 
1879
1880	I915_WRITE(GTIIR, I915_READ(GTIIR));
1881	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1882
1883	render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT |
1884		GT_BLT_USER_INTERRUPT;
1885	I915_WRITE(GTIER, render_irqs);
1886	POSTING_READ(GTIER);
1887
1888	hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1889			SDE_PORTB_HOTPLUG_CPT |
1890			SDE_PORTC_HOTPLUG_CPT |
1891			SDE_PORTD_HOTPLUG_CPT);
1892	dev_priv->pch_irq_mask = ~hotplug_mask;
1893
1894	I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1895	I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1896	I915_WRITE(SDEIER, hotplug_mask);
1897	POSTING_READ(SDEIER);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1898
1899	return 0;
1900}
1901
1902static void i915_driver_irq_preinstall(struct drm_device * dev)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1903{
1904	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 
 
 
1905	int pipe;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1906
1907	atomic_set(&dev_priv->irq_received, 0);
 
 
 
 
 
 
 
 
1908
1909	INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1910	INIT_WORK(&dev_priv->error_work, i915_error_work_func);
 
1911
1912	if (I915_HAS_HOTPLUG(dev)) {
1913		I915_WRITE(PORT_HOTPLUG_EN, 0);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1914		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1915	}
1916
1917	I915_WRITE(HWSTAM, 0xeffe);
1918	for_each_pipe(pipe)
1919		I915_WRITE(PIPESTAT(pipe), 0);
1920	I915_WRITE(IMR, 0xffffffff);
1921	I915_WRITE(IER, 0x0);
1922	POSTING_READ(IER);
1923}
1924
1925/*
1926 * Must be called after intel_modeset_init or hotplug interrupts won't be
1927 * enabled correctly.
1928 */
1929static int i915_driver_irq_postinstall(struct drm_device *dev)
1930{
1931	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1932	u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1933	u32 error_mask;
1934
1935	dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1936
1937	/* Unmask the interrupts that we always want on. */
1938	dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
1939
1940	dev_priv->pipestat[0] = 0;
1941	dev_priv->pipestat[1] = 0;
 
 
 
 
 
 
 
 
 
 
 
 
1942
1943	if (I915_HAS_HOTPLUG(dev)) {
1944		/* Enable in IER... */
1945		enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1946		/* and unmask in IMR */
1947		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
1948	}
1949
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1950	/*
1951	 * Enable some error detection, note the instruction error mask
1952	 * bit is reserved, so we leave it masked.
1953	 */
1954	if (IS_G4X(dev)) {
1955		error_mask = ~(GM45_ERROR_PAGE_TABLE |
1956			       GM45_ERROR_MEM_PRIV |
1957			       GM45_ERROR_CP_PRIV |
1958			       I915_ERROR_MEMORY_REFRESH);
1959	} else {
1960		error_mask = ~(I915_ERROR_PAGE_TABLE |
1961			       I915_ERROR_MEMORY_REFRESH);
1962	}
1963	I915_WRITE(EMR, error_mask);
1964
1965	I915_WRITE(IMR, dev_priv->irq_mask);
1966	I915_WRITE(IER, enable_mask);
1967	POSTING_READ(IER);
1968
1969	if (I915_HAS_HOTPLUG(dev)) {
1970		u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1971
1972		/* Note HDMI and DP share bits */
1973		if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1974			hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1975		if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1976			hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1977		if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1978			hotplug_en |= HDMID_HOTPLUG_INT_EN;
1979		if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1980			hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1981		if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1982			hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1983		if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1984			hotplug_en |= CRT_HOTPLUG_INT_EN;
1985
1986			/* Programming the CRT detection parameters tends
1987			   to generate a spurious hotplug event about three
1988			   seconds later.  So just do it once.
1989			*/
1990			if (IS_G4X(dev))
1991				hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1992			hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1993		}
1994
1995		/* Ignore TV since it's buggy */
 
1996
1997		I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1998	}
 
1999
2000	intel_opregion_enable_asle(dev);
2001
2002	return 0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2003}
2004
2005static void ironlake_irq_uninstall(struct drm_device *dev)
2006{
2007	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 
 
 
 
 
 
 
2008
2009	if (!dev_priv)
2010		return;
2011
2012	dev_priv->vblank_pipe = 0;
 
2013
2014	I915_WRITE(HWSTAM, 0xffffffff);
 
 
 
 
2015
2016	I915_WRITE(DEIMR, 0xffffffff);
2017	I915_WRITE(DEIER, 0x0);
2018	I915_WRITE(DEIIR, I915_READ(DEIIR));
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2019
2020	I915_WRITE(GTIMR, 0xffffffff);
2021	I915_WRITE(GTIER, 0x0);
2022	I915_WRITE(GTIIR, I915_READ(GTIIR));
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2023}
2024
2025static void i915_driver_irq_uninstall(struct drm_device * dev)
2026{
2027	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2028	int pipe;
2029
2030	if (!dev_priv)
2031		return;
2032
2033	dev_priv->vblank_pipe = 0;
2034
2035	if (I915_HAS_HOTPLUG(dev)) {
2036		I915_WRITE(PORT_HOTPLUG_EN, 0);
2037		I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2038	}
2039
2040	I915_WRITE(HWSTAM, 0xffffffff);
2041	for_each_pipe(pipe)
2042		I915_WRITE(PIPESTAT(pipe), 0);
2043	I915_WRITE(IMR, 0xffffffff);
2044	I915_WRITE(IER, 0x0);
2045
2046	for_each_pipe(pipe)
2047		I915_WRITE(PIPESTAT(pipe),
2048			   I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2049	I915_WRITE(IIR, I915_READ(IIR));
2050}
2051
2052void intel_irq_init(struct drm_device *dev)
 
 
 
 
 
 
 
2053{
2054	dev->driver->get_vblank_counter = i915_get_vblank_counter;
2055	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2056	if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2057		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2058		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
 
 
 
2059	}
2060
2061	if (drm_core_check_feature(dev, DRIVER_MODESET))
2062		dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2063	else
2064		dev->driver->get_vblank_timestamp = NULL;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2065	dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2066
2067	if (IS_IVYBRIDGE(dev)) {
2068		/* Share pre & uninstall handlers with ILK/SNB */
2069		dev->driver->irq_handler = ivybridge_irq_handler;
2070		dev->driver->irq_preinstall = ironlake_irq_preinstall;
2071		dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2072		dev->driver->irq_uninstall = ironlake_irq_uninstall;
2073		dev->driver->enable_vblank = ivybridge_enable_vblank;
2074		dev->driver->disable_vblank = ivybridge_disable_vblank;
2075	} else if (HAS_PCH_SPLIT(dev)) {
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2076		dev->driver->irq_handler = ironlake_irq_handler;
2077		dev->driver->irq_preinstall = ironlake_irq_preinstall;
2078		dev->driver->irq_postinstall = ironlake_irq_postinstall;
2079		dev->driver->irq_uninstall = ironlake_irq_uninstall;
2080		dev->driver->enable_vblank = ironlake_enable_vblank;
2081		dev->driver->disable_vblank = ironlake_disable_vblank;
 
2082	} else {
2083		dev->driver->irq_preinstall = i915_driver_irq_preinstall;
2084		dev->driver->irq_postinstall = i915_driver_irq_postinstall;
2085		dev->driver->irq_uninstall = i915_driver_irq_uninstall;
2086		dev->driver->irq_handler = i915_driver_irq_handler;
2087		dev->driver->enable_vblank = i915_enable_vblank;
2088		dev->driver->disable_vblank = i915_disable_vblank;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2089	}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2090}