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1/*
2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
23
24#undef DEBUG
25
26#include <linux/module.h>
27#include <linux/errno.h>
28#include <linux/timer.h>
29#include <linux/interrupt.h>
30#include <linux/tty.h>
31#include <linux/tty_flip.h>
32#include <linux/serial.h>
33#include <linux/major.h>
34#include <linux/string.h>
35#include <linux/sysrq.h>
36#include <linux/ioport.h>
37#include <linux/mm.h>
38#include <linux/init.h>
39#include <linux/delay.h>
40#include <linux/console.h>
41#include <linux/platform_device.h>
42#include <linux/serial_sci.h>
43#include <linux/notifier.h>
44#include <linux/pm_runtime.h>
45#include <linux/cpufreq.h>
46#include <linux/clk.h>
47#include <linux/ctype.h>
48#include <linux/err.h>
49#include <linux/dmaengine.h>
50#include <linux/dma-mapping.h>
51#include <linux/scatterlist.h>
52#include <linux/slab.h>
53
54#ifdef CONFIG_SUPERH
55#include <asm/sh_bios.h>
56#endif
57
58#include "sh-sci.h"
59
60struct sci_port {
61 struct uart_port port;
62
63 /* Platform configuration */
64 struct plat_sci_port *cfg;
65
66 /* Break timer */
67 struct timer_list break_timer;
68 int break_flag;
69
70 /* Interface clock */
71 struct clk *iclk;
72 /* Function clock */
73 struct clk *fclk;
74
75 char *irqstr[SCIx_NR_IRQS];
76
77 struct dma_chan *chan_tx;
78 struct dma_chan *chan_rx;
79
80#ifdef CONFIG_SERIAL_SH_SCI_DMA
81 struct dma_async_tx_descriptor *desc_tx;
82 struct dma_async_tx_descriptor *desc_rx[2];
83 dma_cookie_t cookie_tx;
84 dma_cookie_t cookie_rx[2];
85 dma_cookie_t active_rx;
86 struct scatterlist sg_tx;
87 unsigned int sg_len_tx;
88 struct scatterlist sg_rx[2];
89 size_t buf_len_rx;
90 struct sh_dmae_slave param_tx;
91 struct sh_dmae_slave param_rx;
92 struct work_struct work_tx;
93 struct work_struct work_rx;
94 struct timer_list rx_timer;
95 unsigned int rx_timeout;
96#endif
97
98 struct notifier_block freq_transition;
99
100#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
101 unsigned short saved_smr;
102 unsigned short saved_fcr;
103 unsigned char saved_brr;
104#endif
105};
106
107/* Function prototypes */
108static void sci_start_tx(struct uart_port *port);
109static void sci_stop_tx(struct uart_port *port);
110static void sci_start_rx(struct uart_port *port);
111
112#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
113
114static struct sci_port sci_ports[SCI_NPORTS];
115static struct uart_driver sci_uart_driver;
116
117static inline struct sci_port *
118to_sci_port(struct uart_port *uart)
119{
120 return container_of(uart, struct sci_port, port);
121}
122
123struct plat_sci_reg {
124 u8 offset, size;
125};
126
127/* Helper for invalidating specific entries of an inherited map. */
128#define sci_reg_invalid { .offset = 0, .size = 0 }
129
130static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
131 [SCIx_PROBE_REGTYPE] = {
132 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
133 },
134
135 /*
136 * Common SCI definitions, dependent on the port's regshift
137 * value.
138 */
139 [SCIx_SCI_REGTYPE] = {
140 [SCSMR] = { 0x00, 8 },
141 [SCBRR] = { 0x01, 8 },
142 [SCSCR] = { 0x02, 8 },
143 [SCxTDR] = { 0x03, 8 },
144 [SCxSR] = { 0x04, 8 },
145 [SCxRDR] = { 0x05, 8 },
146 [SCFCR] = sci_reg_invalid,
147 [SCFDR] = sci_reg_invalid,
148 [SCTFDR] = sci_reg_invalid,
149 [SCRFDR] = sci_reg_invalid,
150 [SCSPTR] = sci_reg_invalid,
151 [SCLSR] = sci_reg_invalid,
152 },
153
154 /*
155 * Common definitions for legacy IrDA ports, dependent on
156 * regshift value.
157 */
158 [SCIx_IRDA_REGTYPE] = {
159 [SCSMR] = { 0x00, 8 },
160 [SCBRR] = { 0x01, 8 },
161 [SCSCR] = { 0x02, 8 },
162 [SCxTDR] = { 0x03, 8 },
163 [SCxSR] = { 0x04, 8 },
164 [SCxRDR] = { 0x05, 8 },
165 [SCFCR] = { 0x06, 8 },
166 [SCFDR] = { 0x07, 16 },
167 [SCTFDR] = sci_reg_invalid,
168 [SCRFDR] = sci_reg_invalid,
169 [SCSPTR] = sci_reg_invalid,
170 [SCLSR] = sci_reg_invalid,
171 },
172
173 /*
174 * Common SCIFA definitions.
175 */
176 [SCIx_SCIFA_REGTYPE] = {
177 [SCSMR] = { 0x00, 16 },
178 [SCBRR] = { 0x04, 8 },
179 [SCSCR] = { 0x08, 16 },
180 [SCxTDR] = { 0x20, 8 },
181 [SCxSR] = { 0x14, 16 },
182 [SCxRDR] = { 0x24, 8 },
183 [SCFCR] = { 0x18, 16 },
184 [SCFDR] = { 0x1c, 16 },
185 [SCTFDR] = sci_reg_invalid,
186 [SCRFDR] = sci_reg_invalid,
187 [SCSPTR] = sci_reg_invalid,
188 [SCLSR] = sci_reg_invalid,
189 },
190
191 /*
192 * Common SCIFB definitions.
193 */
194 [SCIx_SCIFB_REGTYPE] = {
195 [SCSMR] = { 0x00, 16 },
196 [SCBRR] = { 0x04, 8 },
197 [SCSCR] = { 0x08, 16 },
198 [SCxTDR] = { 0x40, 8 },
199 [SCxSR] = { 0x14, 16 },
200 [SCxRDR] = { 0x60, 8 },
201 [SCFCR] = { 0x18, 16 },
202 [SCFDR] = { 0x1c, 16 },
203 [SCTFDR] = sci_reg_invalid,
204 [SCRFDR] = sci_reg_invalid,
205 [SCSPTR] = sci_reg_invalid,
206 [SCLSR] = sci_reg_invalid,
207 },
208
209 /*
210 * Common SH-3 SCIF definitions.
211 */
212 [SCIx_SH3_SCIF_REGTYPE] = {
213 [SCSMR] = { 0x00, 8 },
214 [SCBRR] = { 0x02, 8 },
215 [SCSCR] = { 0x04, 8 },
216 [SCxTDR] = { 0x06, 8 },
217 [SCxSR] = { 0x08, 16 },
218 [SCxRDR] = { 0x0a, 8 },
219 [SCFCR] = { 0x0c, 8 },
220 [SCFDR] = { 0x0e, 16 },
221 [SCTFDR] = sci_reg_invalid,
222 [SCRFDR] = sci_reg_invalid,
223 [SCSPTR] = sci_reg_invalid,
224 [SCLSR] = sci_reg_invalid,
225 },
226
227 /*
228 * Common SH-4(A) SCIF(B) definitions.
229 */
230 [SCIx_SH4_SCIF_REGTYPE] = {
231 [SCSMR] = { 0x00, 16 },
232 [SCBRR] = { 0x04, 8 },
233 [SCSCR] = { 0x08, 16 },
234 [SCxTDR] = { 0x0c, 8 },
235 [SCxSR] = { 0x10, 16 },
236 [SCxRDR] = { 0x14, 8 },
237 [SCFCR] = { 0x18, 16 },
238 [SCFDR] = { 0x1c, 16 },
239 [SCTFDR] = sci_reg_invalid,
240 [SCRFDR] = sci_reg_invalid,
241 [SCSPTR] = { 0x20, 16 },
242 [SCLSR] = { 0x24, 16 },
243 },
244
245 /*
246 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
247 * register.
248 */
249 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
250 [SCSMR] = { 0x00, 16 },
251 [SCBRR] = { 0x04, 8 },
252 [SCSCR] = { 0x08, 16 },
253 [SCxTDR] = { 0x0c, 8 },
254 [SCxSR] = { 0x10, 16 },
255 [SCxRDR] = { 0x14, 8 },
256 [SCFCR] = { 0x18, 16 },
257 [SCFDR] = { 0x1c, 16 },
258 [SCTFDR] = sci_reg_invalid,
259 [SCRFDR] = sci_reg_invalid,
260 [SCSPTR] = sci_reg_invalid,
261 [SCLSR] = { 0x24, 16 },
262 },
263
264 /*
265 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
266 * count registers.
267 */
268 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
269 [SCSMR] = { 0x00, 16 },
270 [SCBRR] = { 0x04, 8 },
271 [SCSCR] = { 0x08, 16 },
272 [SCxTDR] = { 0x0c, 8 },
273 [SCxSR] = { 0x10, 16 },
274 [SCxRDR] = { 0x14, 8 },
275 [SCFCR] = { 0x18, 16 },
276 [SCFDR] = { 0x1c, 16 },
277 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
278 [SCRFDR] = { 0x20, 16 },
279 [SCSPTR] = { 0x24, 16 },
280 [SCLSR] = { 0x28, 16 },
281 },
282
283 /*
284 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
285 * registers.
286 */
287 [SCIx_SH7705_SCIF_REGTYPE] = {
288 [SCSMR] = { 0x00, 16 },
289 [SCBRR] = { 0x04, 8 },
290 [SCSCR] = { 0x08, 16 },
291 [SCxTDR] = { 0x20, 8 },
292 [SCxSR] = { 0x14, 16 },
293 [SCxRDR] = { 0x24, 8 },
294 [SCFCR] = { 0x18, 16 },
295 [SCFDR] = { 0x1c, 16 },
296 [SCTFDR] = sci_reg_invalid,
297 [SCRFDR] = sci_reg_invalid,
298 [SCSPTR] = sci_reg_invalid,
299 [SCLSR] = sci_reg_invalid,
300 },
301};
302
303#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
304
305/*
306 * The "offset" here is rather misleading, in that it refers to an enum
307 * value relative to the port mapping rather than the fixed offset
308 * itself, which needs to be manually retrieved from the platform's
309 * register map for the given port.
310 */
311static unsigned int sci_serial_in(struct uart_port *p, int offset)
312{
313 struct plat_sci_reg *reg = sci_getreg(p, offset);
314
315 if (reg->size == 8)
316 return ioread8(p->membase + (reg->offset << p->regshift));
317 else if (reg->size == 16)
318 return ioread16(p->membase + (reg->offset << p->regshift));
319 else
320 WARN(1, "Invalid register access\n");
321
322 return 0;
323}
324
325static void sci_serial_out(struct uart_port *p, int offset, int value)
326{
327 struct plat_sci_reg *reg = sci_getreg(p, offset);
328
329 if (reg->size == 8)
330 iowrite8(value, p->membase + (reg->offset << p->regshift));
331 else if (reg->size == 16)
332 iowrite16(value, p->membase + (reg->offset << p->regshift));
333 else
334 WARN(1, "Invalid register access\n");
335}
336
337#define sci_in(up, offset) (up->serial_in(up, offset))
338#define sci_out(up, offset, value) (up->serial_out(up, offset, value))
339
340static int sci_probe_regmap(struct plat_sci_port *cfg)
341{
342 switch (cfg->type) {
343 case PORT_SCI:
344 cfg->regtype = SCIx_SCI_REGTYPE;
345 break;
346 case PORT_IRDA:
347 cfg->regtype = SCIx_IRDA_REGTYPE;
348 break;
349 case PORT_SCIFA:
350 cfg->regtype = SCIx_SCIFA_REGTYPE;
351 break;
352 case PORT_SCIFB:
353 cfg->regtype = SCIx_SCIFB_REGTYPE;
354 break;
355 case PORT_SCIF:
356 /*
357 * The SH-4 is a bit of a misnomer here, although that's
358 * where this particular port layout originated. This
359 * configuration (or some slight variation thereof)
360 * remains the dominant model for all SCIFs.
361 */
362 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
363 break;
364 default:
365 printk(KERN_ERR "Can't probe register map for given port\n");
366 return -EINVAL;
367 }
368
369 return 0;
370}
371
372static void sci_port_enable(struct sci_port *sci_port)
373{
374 if (!sci_port->port.dev)
375 return;
376
377 pm_runtime_get_sync(sci_port->port.dev);
378
379 clk_enable(sci_port->iclk);
380 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
381 clk_enable(sci_port->fclk);
382}
383
384static void sci_port_disable(struct sci_port *sci_port)
385{
386 if (!sci_port->port.dev)
387 return;
388
389 clk_disable(sci_port->fclk);
390 clk_disable(sci_port->iclk);
391
392 pm_runtime_put_sync(sci_port->port.dev);
393}
394
395#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
396
397#ifdef CONFIG_CONSOLE_POLL
398static int sci_poll_get_char(struct uart_port *port)
399{
400 unsigned short status;
401 int c;
402
403 do {
404 status = sci_in(port, SCxSR);
405 if (status & SCxSR_ERRORS(port)) {
406 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
407 continue;
408 }
409 break;
410 } while (1);
411
412 if (!(status & SCxSR_RDxF(port)))
413 return NO_POLL_CHAR;
414
415 c = sci_in(port, SCxRDR);
416
417 /* Dummy read */
418 sci_in(port, SCxSR);
419 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
420
421 return c;
422}
423#endif
424
425static void sci_poll_put_char(struct uart_port *port, unsigned char c)
426{
427 unsigned short status;
428
429 do {
430 status = sci_in(port, SCxSR);
431 } while (!(status & SCxSR_TDxE(port)));
432
433 sci_out(port, SCxTDR, c);
434 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
435}
436#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
437
438static void sci_init_pins(struct uart_port *port, unsigned int cflag)
439{
440 struct sci_port *s = to_sci_port(port);
441 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
442
443 /*
444 * Use port-specific handler if provided.
445 */
446 if (s->cfg->ops && s->cfg->ops->init_pins) {
447 s->cfg->ops->init_pins(port, cflag);
448 return;
449 }
450
451 /*
452 * For the generic path SCSPTR is necessary. Bail out if that's
453 * unavailable, too.
454 */
455 if (!reg->size)
456 return;
457
458 if (!(cflag & CRTSCTS))
459 sci_out(port, SCSPTR, 0x0080); /* Set RTS = 1 */
460}
461
462static int sci_txfill(struct uart_port *port)
463{
464 struct plat_sci_reg *reg;
465
466 reg = sci_getreg(port, SCTFDR);
467 if (reg->size)
468 return sci_in(port, SCTFDR) & 0xff;
469
470 reg = sci_getreg(port, SCFDR);
471 if (reg->size)
472 return sci_in(port, SCFDR) >> 8;
473
474 return !(sci_in(port, SCxSR) & SCI_TDRE);
475}
476
477static int sci_txroom(struct uart_port *port)
478{
479 return port->fifosize - sci_txfill(port);
480}
481
482static int sci_rxfill(struct uart_port *port)
483{
484 struct plat_sci_reg *reg;
485
486 reg = sci_getreg(port, SCRFDR);
487 if (reg->size)
488 return sci_in(port, SCRFDR) & 0xff;
489
490 reg = sci_getreg(port, SCFDR);
491 if (reg->size)
492 return sci_in(port, SCFDR) & ((port->fifosize << 1) - 1);
493
494 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
495}
496
497/*
498 * SCI helper for checking the state of the muxed port/RXD pins.
499 */
500static inline int sci_rxd_in(struct uart_port *port)
501{
502 struct sci_port *s = to_sci_port(port);
503
504 if (s->cfg->port_reg <= 0)
505 return 1;
506
507 return !!__raw_readb(s->cfg->port_reg);
508}
509
510/* ********************************************************************** *
511 * the interrupt related routines *
512 * ********************************************************************** */
513
514static void sci_transmit_chars(struct uart_port *port)
515{
516 struct circ_buf *xmit = &port->state->xmit;
517 unsigned int stopped = uart_tx_stopped(port);
518 unsigned short status;
519 unsigned short ctrl;
520 int count;
521
522 status = sci_in(port, SCxSR);
523 if (!(status & SCxSR_TDxE(port))) {
524 ctrl = sci_in(port, SCSCR);
525 if (uart_circ_empty(xmit))
526 ctrl &= ~SCSCR_TIE;
527 else
528 ctrl |= SCSCR_TIE;
529 sci_out(port, SCSCR, ctrl);
530 return;
531 }
532
533 count = sci_txroom(port);
534
535 do {
536 unsigned char c;
537
538 if (port->x_char) {
539 c = port->x_char;
540 port->x_char = 0;
541 } else if (!uart_circ_empty(xmit) && !stopped) {
542 c = xmit->buf[xmit->tail];
543 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
544 } else {
545 break;
546 }
547
548 sci_out(port, SCxTDR, c);
549
550 port->icount.tx++;
551 } while (--count > 0);
552
553 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
554
555 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
556 uart_write_wakeup(port);
557 if (uart_circ_empty(xmit)) {
558 sci_stop_tx(port);
559 } else {
560 ctrl = sci_in(port, SCSCR);
561
562 if (port->type != PORT_SCI) {
563 sci_in(port, SCxSR); /* Dummy read */
564 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
565 }
566
567 ctrl |= SCSCR_TIE;
568 sci_out(port, SCSCR, ctrl);
569 }
570}
571
572/* On SH3, SCIF may read end-of-break as a space->mark char */
573#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
574
575static void sci_receive_chars(struct uart_port *port)
576{
577 struct sci_port *sci_port = to_sci_port(port);
578 struct tty_struct *tty = port->state->port.tty;
579 int i, count, copied = 0;
580 unsigned short status;
581 unsigned char flag;
582
583 status = sci_in(port, SCxSR);
584 if (!(status & SCxSR_RDxF(port)))
585 return;
586
587 while (1) {
588 /* Don't copy more bytes than there is room for in the buffer */
589 count = tty_buffer_request_room(tty, sci_rxfill(port));
590
591 /* If for any reason we can't copy more data, we're done! */
592 if (count == 0)
593 break;
594
595 if (port->type == PORT_SCI) {
596 char c = sci_in(port, SCxRDR);
597 if (uart_handle_sysrq_char(port, c) ||
598 sci_port->break_flag)
599 count = 0;
600 else
601 tty_insert_flip_char(tty, c, TTY_NORMAL);
602 } else {
603 for (i = 0; i < count; i++) {
604 char c = sci_in(port, SCxRDR);
605 status = sci_in(port, SCxSR);
606#if defined(CONFIG_CPU_SH3)
607 /* Skip "chars" during break */
608 if (sci_port->break_flag) {
609 if ((c == 0) &&
610 (status & SCxSR_FER(port))) {
611 count--; i--;
612 continue;
613 }
614
615 /* Nonzero => end-of-break */
616 dev_dbg(port->dev, "debounce<%02x>\n", c);
617 sci_port->break_flag = 0;
618
619 if (STEPFN(c)) {
620 count--; i--;
621 continue;
622 }
623 }
624#endif /* CONFIG_CPU_SH3 */
625 if (uart_handle_sysrq_char(port, c)) {
626 count--; i--;
627 continue;
628 }
629
630 /* Store data and status */
631 if (status & SCxSR_FER(port)) {
632 flag = TTY_FRAME;
633 dev_notice(port->dev, "frame error\n");
634 } else if (status & SCxSR_PER(port)) {
635 flag = TTY_PARITY;
636 dev_notice(port->dev, "parity error\n");
637 } else
638 flag = TTY_NORMAL;
639
640 tty_insert_flip_char(tty, c, flag);
641 }
642 }
643
644 sci_in(port, SCxSR); /* dummy read */
645 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
646
647 copied += count;
648 port->icount.rx += count;
649 }
650
651 if (copied) {
652 /* Tell the rest of the system the news. New characters! */
653 tty_flip_buffer_push(tty);
654 } else {
655 sci_in(port, SCxSR); /* dummy read */
656 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
657 }
658}
659
660#define SCI_BREAK_JIFFIES (HZ/20)
661
662/*
663 * The sci generates interrupts during the break,
664 * 1 per millisecond or so during the break period, for 9600 baud.
665 * So dont bother disabling interrupts.
666 * But dont want more than 1 break event.
667 * Use a kernel timer to periodically poll the rx line until
668 * the break is finished.
669 */
670static inline void sci_schedule_break_timer(struct sci_port *port)
671{
672 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
673}
674
675/* Ensure that two consecutive samples find the break over. */
676static void sci_break_timer(unsigned long data)
677{
678 struct sci_port *port = (struct sci_port *)data;
679
680 sci_port_enable(port);
681
682 if (sci_rxd_in(&port->port) == 0) {
683 port->break_flag = 1;
684 sci_schedule_break_timer(port);
685 } else if (port->break_flag == 1) {
686 /* break is over. */
687 port->break_flag = 2;
688 sci_schedule_break_timer(port);
689 } else
690 port->break_flag = 0;
691
692 sci_port_disable(port);
693}
694
695static int sci_handle_errors(struct uart_port *port)
696{
697 int copied = 0;
698 unsigned short status = sci_in(port, SCxSR);
699 struct tty_struct *tty = port->state->port.tty;
700 struct sci_port *s = to_sci_port(port);
701
702 /*
703 * Handle overruns, if supported.
704 */
705 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
706 if (status & (1 << s->cfg->overrun_bit)) {
707 /* overrun error */
708 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
709 copied++;
710
711 dev_notice(port->dev, "overrun error");
712 }
713 }
714
715 if (status & SCxSR_FER(port)) {
716 if (sci_rxd_in(port) == 0) {
717 /* Notify of BREAK */
718 struct sci_port *sci_port = to_sci_port(port);
719
720 if (!sci_port->break_flag) {
721 sci_port->break_flag = 1;
722 sci_schedule_break_timer(sci_port);
723
724 /* Do sysrq handling. */
725 if (uart_handle_break(port))
726 return 0;
727
728 dev_dbg(port->dev, "BREAK detected\n");
729
730 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
731 copied++;
732 }
733
734 } else {
735 /* frame error */
736 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
737 copied++;
738
739 dev_notice(port->dev, "frame error\n");
740 }
741 }
742
743 if (status & SCxSR_PER(port)) {
744 /* parity error */
745 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
746 copied++;
747
748 dev_notice(port->dev, "parity error");
749 }
750
751 if (copied)
752 tty_flip_buffer_push(tty);
753
754 return copied;
755}
756
757static int sci_handle_fifo_overrun(struct uart_port *port)
758{
759 struct tty_struct *tty = port->state->port.tty;
760 struct sci_port *s = to_sci_port(port);
761 struct plat_sci_reg *reg;
762 int copied = 0;
763
764 reg = sci_getreg(port, SCLSR);
765 if (!reg->size)
766 return 0;
767
768 if ((sci_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
769 sci_out(port, SCLSR, 0);
770
771 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
772 tty_flip_buffer_push(tty);
773
774 dev_notice(port->dev, "overrun error\n");
775 copied++;
776 }
777
778 return copied;
779}
780
781static int sci_handle_breaks(struct uart_port *port)
782{
783 int copied = 0;
784 unsigned short status = sci_in(port, SCxSR);
785 struct tty_struct *tty = port->state->port.tty;
786 struct sci_port *s = to_sci_port(port);
787
788 if (uart_handle_break(port))
789 return 0;
790
791 if (!s->break_flag && status & SCxSR_BRK(port)) {
792#if defined(CONFIG_CPU_SH3)
793 /* Debounce break */
794 s->break_flag = 1;
795#endif
796 /* Notify of BREAK */
797 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
798 copied++;
799
800 dev_dbg(port->dev, "BREAK detected\n");
801 }
802
803 if (copied)
804 tty_flip_buffer_push(tty);
805
806 copied += sci_handle_fifo_overrun(port);
807
808 return copied;
809}
810
811static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
812{
813#ifdef CONFIG_SERIAL_SH_SCI_DMA
814 struct uart_port *port = ptr;
815 struct sci_port *s = to_sci_port(port);
816
817 if (s->chan_rx) {
818 u16 scr = sci_in(port, SCSCR);
819 u16 ssr = sci_in(port, SCxSR);
820
821 /* Disable future Rx interrupts */
822 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
823 disable_irq_nosync(irq);
824 scr |= 0x4000;
825 } else {
826 scr &= ~SCSCR_RIE;
827 }
828 sci_out(port, SCSCR, scr);
829 /* Clear current interrupt */
830 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
831 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
832 jiffies, s->rx_timeout);
833 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
834
835 return IRQ_HANDLED;
836 }
837#endif
838
839 /* I think sci_receive_chars has to be called irrespective
840 * of whether the I_IXOFF is set, otherwise, how is the interrupt
841 * to be disabled?
842 */
843 sci_receive_chars(ptr);
844
845 return IRQ_HANDLED;
846}
847
848static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
849{
850 struct uart_port *port = ptr;
851 unsigned long flags;
852
853 spin_lock_irqsave(&port->lock, flags);
854 sci_transmit_chars(port);
855 spin_unlock_irqrestore(&port->lock, flags);
856
857 return IRQ_HANDLED;
858}
859
860static irqreturn_t sci_er_interrupt(int irq, void *ptr)
861{
862 struct uart_port *port = ptr;
863
864 /* Handle errors */
865 if (port->type == PORT_SCI) {
866 if (sci_handle_errors(port)) {
867 /* discard character in rx buffer */
868 sci_in(port, SCxSR);
869 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
870 }
871 } else {
872 sci_handle_fifo_overrun(port);
873 sci_rx_interrupt(irq, ptr);
874 }
875
876 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
877
878 /* Kick the transmission */
879 sci_tx_interrupt(irq, ptr);
880
881 return IRQ_HANDLED;
882}
883
884static irqreturn_t sci_br_interrupt(int irq, void *ptr)
885{
886 struct uart_port *port = ptr;
887
888 /* Handle BREAKs */
889 sci_handle_breaks(port);
890 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
891
892 return IRQ_HANDLED;
893}
894
895static inline unsigned long port_rx_irq_mask(struct uart_port *port)
896{
897 /*
898 * Not all ports (such as SCIFA) will support REIE. Rather than
899 * special-casing the port type, we check the port initialization
900 * IRQ enable mask to see whether the IRQ is desired at all. If
901 * it's unset, it's logically inferred that there's no point in
902 * testing for it.
903 */
904 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
905}
906
907static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
908{
909 unsigned short ssr_status, scr_status, err_enabled;
910 struct uart_port *port = ptr;
911 struct sci_port *s = to_sci_port(port);
912 irqreturn_t ret = IRQ_NONE;
913
914 ssr_status = sci_in(port, SCxSR);
915 scr_status = sci_in(port, SCSCR);
916 err_enabled = scr_status & port_rx_irq_mask(port);
917
918 /* Tx Interrupt */
919 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
920 !s->chan_tx)
921 ret = sci_tx_interrupt(irq, ptr);
922
923 /*
924 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
925 * DR flags
926 */
927 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
928 (scr_status & SCSCR_RIE))
929 ret = sci_rx_interrupt(irq, ptr);
930
931 /* Error Interrupt */
932 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
933 ret = sci_er_interrupt(irq, ptr);
934
935 /* Break Interrupt */
936 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
937 ret = sci_br_interrupt(irq, ptr);
938
939 return ret;
940}
941
942/*
943 * Here we define a transition notifier so that we can update all of our
944 * ports' baud rate when the peripheral clock changes.
945 */
946static int sci_notifier(struct notifier_block *self,
947 unsigned long phase, void *p)
948{
949 struct sci_port *sci_port;
950 unsigned long flags;
951
952 sci_port = container_of(self, struct sci_port, freq_transition);
953
954 if ((phase == CPUFREQ_POSTCHANGE) ||
955 (phase == CPUFREQ_RESUMECHANGE)) {
956 struct uart_port *port = &sci_port->port;
957
958 spin_lock_irqsave(&port->lock, flags);
959 port->uartclk = clk_get_rate(sci_port->iclk);
960 spin_unlock_irqrestore(&port->lock, flags);
961 }
962
963 return NOTIFY_OK;
964}
965
966static struct sci_irq_desc {
967 const char *desc;
968 irq_handler_t handler;
969} sci_irq_desc[] = {
970 /*
971 * Split out handlers, the default case.
972 */
973 [SCIx_ERI_IRQ] = {
974 .desc = "rx err",
975 .handler = sci_er_interrupt,
976 },
977
978 [SCIx_RXI_IRQ] = {
979 .desc = "rx full",
980 .handler = sci_rx_interrupt,
981 },
982
983 [SCIx_TXI_IRQ] = {
984 .desc = "tx empty",
985 .handler = sci_tx_interrupt,
986 },
987
988 [SCIx_BRI_IRQ] = {
989 .desc = "break",
990 .handler = sci_br_interrupt,
991 },
992
993 /*
994 * Special muxed handler.
995 */
996 [SCIx_MUX_IRQ] = {
997 .desc = "mux",
998 .handler = sci_mpxed_interrupt,
999 },
1000};
1001
1002static int sci_request_irq(struct sci_port *port)
1003{
1004 struct uart_port *up = &port->port;
1005 int i, j, ret = 0;
1006
1007 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1008 struct sci_irq_desc *desc;
1009 unsigned int irq;
1010
1011 if (SCIx_IRQ_IS_MUXED(port)) {
1012 i = SCIx_MUX_IRQ;
1013 irq = up->irq;
1014 } else
1015 irq = port->cfg->irqs[i];
1016
1017 desc = sci_irq_desc + i;
1018 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1019 dev_name(up->dev), desc->desc);
1020 if (!port->irqstr[j]) {
1021 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1022 desc->desc);
1023 goto out_nomem;
1024 }
1025
1026 ret = request_irq(irq, desc->handler, up->irqflags,
1027 port->irqstr[j], port);
1028 if (unlikely(ret)) {
1029 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1030 goto out_noirq;
1031 }
1032 }
1033
1034 return 0;
1035
1036out_noirq:
1037 while (--i >= 0)
1038 free_irq(port->cfg->irqs[i], port);
1039
1040out_nomem:
1041 while (--j >= 0)
1042 kfree(port->irqstr[j]);
1043
1044 return ret;
1045}
1046
1047static void sci_free_irq(struct sci_port *port)
1048{
1049 int i;
1050
1051 /*
1052 * Intentionally in reverse order so we iterate over the muxed
1053 * IRQ first.
1054 */
1055 for (i = 0; i < SCIx_NR_IRQS; i++) {
1056 free_irq(port->cfg->irqs[i], port);
1057 kfree(port->irqstr[i]);
1058
1059 if (SCIx_IRQ_IS_MUXED(port)) {
1060 /* If there's only one IRQ, we're done. */
1061 return;
1062 }
1063 }
1064}
1065
1066static unsigned int sci_tx_empty(struct uart_port *port)
1067{
1068 unsigned short status = sci_in(port, SCxSR);
1069 unsigned short in_tx_fifo = sci_txfill(port);
1070
1071 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1072}
1073
1074static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1075{
1076 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
1077 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
1078 /* If you have signals for DTR and DCD, please implement here. */
1079}
1080
1081static unsigned int sci_get_mctrl(struct uart_port *port)
1082{
1083 /* This routine is used for getting signals of: DTR, DCD, DSR, RI,
1084 and CTS/RTS */
1085
1086 return TIOCM_DTR | TIOCM_RTS | TIOCM_CTS | TIOCM_DSR;
1087}
1088
1089#ifdef CONFIG_SERIAL_SH_SCI_DMA
1090static void sci_dma_tx_complete(void *arg)
1091{
1092 struct sci_port *s = arg;
1093 struct uart_port *port = &s->port;
1094 struct circ_buf *xmit = &port->state->xmit;
1095 unsigned long flags;
1096
1097 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1098
1099 spin_lock_irqsave(&port->lock, flags);
1100
1101 xmit->tail += sg_dma_len(&s->sg_tx);
1102 xmit->tail &= UART_XMIT_SIZE - 1;
1103
1104 port->icount.tx += sg_dma_len(&s->sg_tx);
1105
1106 async_tx_ack(s->desc_tx);
1107 s->cookie_tx = -EINVAL;
1108 s->desc_tx = NULL;
1109
1110 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1111 uart_write_wakeup(port);
1112
1113 if (!uart_circ_empty(xmit)) {
1114 schedule_work(&s->work_tx);
1115 } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1116 u16 ctrl = sci_in(port, SCSCR);
1117 sci_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1118 }
1119
1120 spin_unlock_irqrestore(&port->lock, flags);
1121}
1122
1123/* Locking: called with port lock held */
1124static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
1125 size_t count)
1126{
1127 struct uart_port *port = &s->port;
1128 int i, active, room;
1129
1130 room = tty_buffer_request_room(tty, count);
1131
1132 if (s->active_rx == s->cookie_rx[0]) {
1133 active = 0;
1134 } else if (s->active_rx == s->cookie_rx[1]) {
1135 active = 1;
1136 } else {
1137 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1138 return 0;
1139 }
1140
1141 if (room < count)
1142 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
1143 count - room);
1144 if (!room)
1145 return room;
1146
1147 for (i = 0; i < room; i++)
1148 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1149 TTY_NORMAL);
1150
1151 port->icount.rx += room;
1152
1153 return room;
1154}
1155
1156static void sci_dma_rx_complete(void *arg)
1157{
1158 struct sci_port *s = arg;
1159 struct uart_port *port = &s->port;
1160 struct tty_struct *tty = port->state->port.tty;
1161 unsigned long flags;
1162 int count;
1163
1164 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
1165
1166 spin_lock_irqsave(&port->lock, flags);
1167
1168 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
1169
1170 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1171
1172 spin_unlock_irqrestore(&port->lock, flags);
1173
1174 if (count)
1175 tty_flip_buffer_push(tty);
1176
1177 schedule_work(&s->work_rx);
1178}
1179
1180static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1181{
1182 struct dma_chan *chan = s->chan_rx;
1183 struct uart_port *port = &s->port;
1184
1185 s->chan_rx = NULL;
1186 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1187 dma_release_channel(chan);
1188 if (sg_dma_address(&s->sg_rx[0]))
1189 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1190 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1191 if (enable_pio)
1192 sci_start_rx(port);
1193}
1194
1195static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1196{
1197 struct dma_chan *chan = s->chan_tx;
1198 struct uart_port *port = &s->port;
1199
1200 s->chan_tx = NULL;
1201 s->cookie_tx = -EINVAL;
1202 dma_release_channel(chan);
1203 if (enable_pio)
1204 sci_start_tx(port);
1205}
1206
1207static void sci_submit_rx(struct sci_port *s)
1208{
1209 struct dma_chan *chan = s->chan_rx;
1210 int i;
1211
1212 for (i = 0; i < 2; i++) {
1213 struct scatterlist *sg = &s->sg_rx[i];
1214 struct dma_async_tx_descriptor *desc;
1215
1216 desc = chan->device->device_prep_slave_sg(chan,
1217 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT);
1218
1219 if (desc) {
1220 s->desc_rx[i] = desc;
1221 desc->callback = sci_dma_rx_complete;
1222 desc->callback_param = s;
1223 s->cookie_rx[i] = desc->tx_submit(desc);
1224 }
1225
1226 if (!desc || s->cookie_rx[i] < 0) {
1227 if (i) {
1228 async_tx_ack(s->desc_rx[0]);
1229 s->cookie_rx[0] = -EINVAL;
1230 }
1231 if (desc) {
1232 async_tx_ack(desc);
1233 s->cookie_rx[i] = -EINVAL;
1234 }
1235 dev_warn(s->port.dev,
1236 "failed to re-start DMA, using PIO\n");
1237 sci_rx_dma_release(s, true);
1238 return;
1239 }
1240 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1241 s->cookie_rx[i], i);
1242 }
1243
1244 s->active_rx = s->cookie_rx[0];
1245
1246 dma_async_issue_pending(chan);
1247}
1248
1249static void work_fn_rx(struct work_struct *work)
1250{
1251 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1252 struct uart_port *port = &s->port;
1253 struct dma_async_tx_descriptor *desc;
1254 int new;
1255
1256 if (s->active_rx == s->cookie_rx[0]) {
1257 new = 0;
1258 } else if (s->active_rx == s->cookie_rx[1]) {
1259 new = 1;
1260 } else {
1261 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1262 return;
1263 }
1264 desc = s->desc_rx[new];
1265
1266 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1267 DMA_SUCCESS) {
1268 /* Handle incomplete DMA receive */
1269 struct tty_struct *tty = port->state->port.tty;
1270 struct dma_chan *chan = s->chan_rx;
1271 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1272 async_tx);
1273 unsigned long flags;
1274 int count;
1275
1276 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
1277 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1278 sh_desc->partial, sh_desc->cookie);
1279
1280 spin_lock_irqsave(&port->lock, flags);
1281 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1282 spin_unlock_irqrestore(&port->lock, flags);
1283
1284 if (count)
1285 tty_flip_buffer_push(tty);
1286
1287 sci_submit_rx(s);
1288
1289 return;
1290 }
1291
1292 s->cookie_rx[new] = desc->tx_submit(desc);
1293 if (s->cookie_rx[new] < 0) {
1294 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1295 sci_rx_dma_release(s, true);
1296 return;
1297 }
1298
1299 s->active_rx = s->cookie_rx[!new];
1300
1301 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1302 s->cookie_rx[new], new, s->active_rx);
1303}
1304
1305static void work_fn_tx(struct work_struct *work)
1306{
1307 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1308 struct dma_async_tx_descriptor *desc;
1309 struct dma_chan *chan = s->chan_tx;
1310 struct uart_port *port = &s->port;
1311 struct circ_buf *xmit = &port->state->xmit;
1312 struct scatterlist *sg = &s->sg_tx;
1313
1314 /*
1315 * DMA is idle now.
1316 * Port xmit buffer is already mapped, and it is one page... Just adjust
1317 * offsets and lengths. Since it is a circular buffer, we have to
1318 * transmit till the end, and then the rest. Take the port lock to get a
1319 * consistent xmit buffer state.
1320 */
1321 spin_lock_irq(&port->lock);
1322 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1323 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1324 sg->offset;
1325 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1326 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1327 spin_unlock_irq(&port->lock);
1328
1329 BUG_ON(!sg_dma_len(sg));
1330
1331 desc = chan->device->device_prep_slave_sg(chan,
1332 sg, s->sg_len_tx, DMA_TO_DEVICE,
1333 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1334 if (!desc) {
1335 /* switch to PIO */
1336 sci_tx_dma_release(s, true);
1337 return;
1338 }
1339
1340 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1341
1342 spin_lock_irq(&port->lock);
1343 s->desc_tx = desc;
1344 desc->callback = sci_dma_tx_complete;
1345 desc->callback_param = s;
1346 spin_unlock_irq(&port->lock);
1347 s->cookie_tx = desc->tx_submit(desc);
1348 if (s->cookie_tx < 0) {
1349 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1350 /* switch to PIO */
1351 sci_tx_dma_release(s, true);
1352 return;
1353 }
1354
1355 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1356 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1357
1358 dma_async_issue_pending(chan);
1359}
1360#endif
1361
1362static void sci_start_tx(struct uart_port *port)
1363{
1364 struct sci_port *s = to_sci_port(port);
1365 unsigned short ctrl;
1366
1367#ifdef CONFIG_SERIAL_SH_SCI_DMA
1368 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1369 u16 new, scr = sci_in(port, SCSCR);
1370 if (s->chan_tx)
1371 new = scr | 0x8000;
1372 else
1373 new = scr & ~0x8000;
1374 if (new != scr)
1375 sci_out(port, SCSCR, new);
1376 }
1377
1378 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1379 s->cookie_tx < 0)
1380 schedule_work(&s->work_tx);
1381#endif
1382
1383 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1384 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1385 ctrl = sci_in(port, SCSCR);
1386 sci_out(port, SCSCR, ctrl | SCSCR_TIE);
1387 }
1388}
1389
1390static void sci_stop_tx(struct uart_port *port)
1391{
1392 unsigned short ctrl;
1393
1394 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1395 ctrl = sci_in(port, SCSCR);
1396
1397 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1398 ctrl &= ~0x8000;
1399
1400 ctrl &= ~SCSCR_TIE;
1401
1402 sci_out(port, SCSCR, ctrl);
1403}
1404
1405static void sci_start_rx(struct uart_port *port)
1406{
1407 unsigned short ctrl;
1408
1409 ctrl = sci_in(port, SCSCR) | port_rx_irq_mask(port);
1410
1411 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1412 ctrl &= ~0x4000;
1413
1414 sci_out(port, SCSCR, ctrl);
1415}
1416
1417static void sci_stop_rx(struct uart_port *port)
1418{
1419 unsigned short ctrl;
1420
1421 ctrl = sci_in(port, SCSCR);
1422
1423 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1424 ctrl &= ~0x4000;
1425
1426 ctrl &= ~port_rx_irq_mask(port);
1427
1428 sci_out(port, SCSCR, ctrl);
1429}
1430
1431static void sci_enable_ms(struct uart_port *port)
1432{
1433 /* Nothing here yet .. */
1434}
1435
1436static void sci_break_ctl(struct uart_port *port, int break_state)
1437{
1438 /* Nothing here yet .. */
1439}
1440
1441#ifdef CONFIG_SERIAL_SH_SCI_DMA
1442static bool filter(struct dma_chan *chan, void *slave)
1443{
1444 struct sh_dmae_slave *param = slave;
1445
1446 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1447 param->slave_id);
1448
1449 if (param->dma_dev == chan->device->dev) {
1450 chan->private = param;
1451 return true;
1452 } else {
1453 return false;
1454 }
1455}
1456
1457static void rx_timer_fn(unsigned long arg)
1458{
1459 struct sci_port *s = (struct sci_port *)arg;
1460 struct uart_port *port = &s->port;
1461 u16 scr = sci_in(port, SCSCR);
1462
1463 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1464 scr &= ~0x4000;
1465 enable_irq(s->cfg->irqs[1]);
1466 }
1467 sci_out(port, SCSCR, scr | SCSCR_RIE);
1468 dev_dbg(port->dev, "DMA Rx timed out\n");
1469 schedule_work(&s->work_rx);
1470}
1471
1472static void sci_request_dma(struct uart_port *port)
1473{
1474 struct sci_port *s = to_sci_port(port);
1475 struct sh_dmae_slave *param;
1476 struct dma_chan *chan;
1477 dma_cap_mask_t mask;
1478 int nent;
1479
1480 dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__,
1481 port->line, s->cfg->dma_dev);
1482
1483 if (!s->cfg->dma_dev)
1484 return;
1485
1486 dma_cap_zero(mask);
1487 dma_cap_set(DMA_SLAVE, mask);
1488
1489 param = &s->param_tx;
1490
1491 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1492 param->slave_id = s->cfg->dma_slave_tx;
1493 param->dma_dev = s->cfg->dma_dev;
1494
1495 s->cookie_tx = -EINVAL;
1496 chan = dma_request_channel(mask, filter, param);
1497 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1498 if (chan) {
1499 s->chan_tx = chan;
1500 sg_init_table(&s->sg_tx, 1);
1501 /* UART circular tx buffer is an aligned page. */
1502 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1503 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1504 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1505 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1506 if (!nent)
1507 sci_tx_dma_release(s, false);
1508 else
1509 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1510 sg_dma_len(&s->sg_tx),
1511 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1512
1513 s->sg_len_tx = nent;
1514
1515 INIT_WORK(&s->work_tx, work_fn_tx);
1516 }
1517
1518 param = &s->param_rx;
1519
1520 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1521 param->slave_id = s->cfg->dma_slave_rx;
1522 param->dma_dev = s->cfg->dma_dev;
1523
1524 chan = dma_request_channel(mask, filter, param);
1525 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1526 if (chan) {
1527 dma_addr_t dma[2];
1528 void *buf[2];
1529 int i;
1530
1531 s->chan_rx = chan;
1532
1533 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1534 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1535 &dma[0], GFP_KERNEL);
1536
1537 if (!buf[0]) {
1538 dev_warn(port->dev,
1539 "failed to allocate dma buffer, using PIO\n");
1540 sci_rx_dma_release(s, true);
1541 return;
1542 }
1543
1544 buf[1] = buf[0] + s->buf_len_rx;
1545 dma[1] = dma[0] + s->buf_len_rx;
1546
1547 for (i = 0; i < 2; i++) {
1548 struct scatterlist *sg = &s->sg_rx[i];
1549
1550 sg_init_table(sg, 1);
1551 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1552 (int)buf[i] & ~PAGE_MASK);
1553 sg_dma_address(sg) = dma[i];
1554 }
1555
1556 INIT_WORK(&s->work_rx, work_fn_rx);
1557 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1558
1559 sci_submit_rx(s);
1560 }
1561}
1562
1563static void sci_free_dma(struct uart_port *port)
1564{
1565 struct sci_port *s = to_sci_port(port);
1566
1567 if (!s->cfg->dma_dev)
1568 return;
1569
1570 if (s->chan_tx)
1571 sci_tx_dma_release(s, false);
1572 if (s->chan_rx)
1573 sci_rx_dma_release(s, false);
1574}
1575#else
1576static inline void sci_request_dma(struct uart_port *port)
1577{
1578}
1579
1580static inline void sci_free_dma(struct uart_port *port)
1581{
1582}
1583#endif
1584
1585static int sci_startup(struct uart_port *port)
1586{
1587 struct sci_port *s = to_sci_port(port);
1588 int ret;
1589
1590 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1591
1592 sci_port_enable(s);
1593
1594 ret = sci_request_irq(s);
1595 if (unlikely(ret < 0))
1596 return ret;
1597
1598 sci_request_dma(port);
1599
1600 sci_start_tx(port);
1601 sci_start_rx(port);
1602
1603 return 0;
1604}
1605
1606static void sci_shutdown(struct uart_port *port)
1607{
1608 struct sci_port *s = to_sci_port(port);
1609
1610 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1611
1612 sci_stop_rx(port);
1613 sci_stop_tx(port);
1614
1615 sci_free_dma(port);
1616 sci_free_irq(s);
1617
1618 sci_port_disable(s);
1619}
1620
1621static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1622 unsigned long freq)
1623{
1624 switch (algo_id) {
1625 case SCBRR_ALGO_1:
1626 return ((freq + 16 * bps) / (16 * bps) - 1);
1627 case SCBRR_ALGO_2:
1628 return ((freq + 16 * bps) / (32 * bps) - 1);
1629 case SCBRR_ALGO_3:
1630 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1631 case SCBRR_ALGO_4:
1632 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1633 case SCBRR_ALGO_5:
1634 return (((freq * 1000 / 32) / bps) - 1);
1635 }
1636
1637 /* Warn, but use a safe default */
1638 WARN_ON(1);
1639
1640 return ((freq + 16 * bps) / (32 * bps) - 1);
1641}
1642
1643static void sci_reset(struct uart_port *port)
1644{
1645 unsigned int status;
1646
1647 do {
1648 status = sci_in(port, SCxSR);
1649 } while (!(status & SCxSR_TEND(port)));
1650
1651 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1652
1653 if (port->type != PORT_SCI)
1654 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1655}
1656
1657static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1658 struct ktermios *old)
1659{
1660 struct sci_port *s = to_sci_port(port);
1661 unsigned int baud, smr_val, max_baud;
1662 int t = -1;
1663 u16 scfcr = 0;
1664
1665 /*
1666 * earlyprintk comes here early on with port->uartclk set to zero.
1667 * the clock framework is not up and running at this point so here
1668 * we assume that 115200 is the maximum baud rate. please note that
1669 * the baud rate is not programmed during earlyprintk - it is assumed
1670 * that the previous boot loader has enabled required clocks and
1671 * setup the baud rate generator hardware for us already.
1672 */
1673 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1674
1675 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1676 if (likely(baud && port->uartclk))
1677 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
1678
1679 sci_port_enable(s);
1680
1681 sci_reset(port);
1682
1683 smr_val = sci_in(port, SCSMR) & 3;
1684
1685 if ((termios->c_cflag & CSIZE) == CS7)
1686 smr_val |= 0x40;
1687 if (termios->c_cflag & PARENB)
1688 smr_val |= 0x20;
1689 if (termios->c_cflag & PARODD)
1690 smr_val |= 0x30;
1691 if (termios->c_cflag & CSTOPB)
1692 smr_val |= 0x08;
1693
1694 uart_update_timeout(port, termios->c_cflag, baud);
1695
1696 sci_out(port, SCSMR, smr_val);
1697
1698 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
1699 s->cfg->scscr);
1700
1701 if (t > 0) {
1702 if (t >= 256) {
1703 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1704 t >>= 2;
1705 } else
1706 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1707
1708 sci_out(port, SCBRR, t);
1709 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1710 }
1711
1712 sci_init_pins(port, termios->c_cflag);
1713 sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0));
1714
1715 sci_out(port, SCSCR, s->cfg->scscr);
1716
1717#ifdef CONFIG_SERIAL_SH_SCI_DMA
1718 /*
1719 * Calculate delay for 1.5 DMA buffers: see
1720 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1721 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1722 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1723 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1724 * sizes), but it has been found out experimentally, that this is not
1725 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1726 * as a minimum seem to work perfectly.
1727 */
1728 if (s->chan_rx) {
1729 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1730 port->fifosize / 2;
1731 dev_dbg(port->dev,
1732 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1733 s->rx_timeout * 1000 / HZ, port->timeout);
1734 if (s->rx_timeout < msecs_to_jiffies(20))
1735 s->rx_timeout = msecs_to_jiffies(20);
1736 }
1737#endif
1738
1739 if ((termios->c_cflag & CREAD) != 0)
1740 sci_start_rx(port);
1741
1742 sci_port_disable(s);
1743}
1744
1745static const char *sci_type(struct uart_port *port)
1746{
1747 switch (port->type) {
1748 case PORT_IRDA:
1749 return "irda";
1750 case PORT_SCI:
1751 return "sci";
1752 case PORT_SCIF:
1753 return "scif";
1754 case PORT_SCIFA:
1755 return "scifa";
1756 case PORT_SCIFB:
1757 return "scifb";
1758 }
1759
1760 return NULL;
1761}
1762
1763static inline unsigned long sci_port_size(struct uart_port *port)
1764{
1765 /*
1766 * Pick an arbitrary size that encapsulates all of the base
1767 * registers by default. This can be optimized later, or derived
1768 * from platform resource data at such a time that ports begin to
1769 * behave more erratically.
1770 */
1771 return 64;
1772}
1773
1774static int sci_remap_port(struct uart_port *port)
1775{
1776 unsigned long size = sci_port_size(port);
1777
1778 /*
1779 * Nothing to do if there's already an established membase.
1780 */
1781 if (port->membase)
1782 return 0;
1783
1784 if (port->flags & UPF_IOREMAP) {
1785 port->membase = ioremap_nocache(port->mapbase, size);
1786 if (unlikely(!port->membase)) {
1787 dev_err(port->dev, "can't remap port#%d\n", port->line);
1788 return -ENXIO;
1789 }
1790 } else {
1791 /*
1792 * For the simple (and majority of) cases where we don't
1793 * need to do any remapping, just cast the cookie
1794 * directly.
1795 */
1796 port->membase = (void __iomem *)port->mapbase;
1797 }
1798
1799 return 0;
1800}
1801
1802static void sci_release_port(struct uart_port *port)
1803{
1804 if (port->flags & UPF_IOREMAP) {
1805 iounmap(port->membase);
1806 port->membase = NULL;
1807 }
1808
1809 release_mem_region(port->mapbase, sci_port_size(port));
1810}
1811
1812static int sci_request_port(struct uart_port *port)
1813{
1814 unsigned long size = sci_port_size(port);
1815 struct resource *res;
1816 int ret;
1817
1818 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
1819 if (unlikely(res == NULL))
1820 return -EBUSY;
1821
1822 ret = sci_remap_port(port);
1823 if (unlikely(ret != 0)) {
1824 release_resource(res);
1825 return ret;
1826 }
1827
1828 return 0;
1829}
1830
1831static void sci_config_port(struct uart_port *port, int flags)
1832{
1833 if (flags & UART_CONFIG_TYPE) {
1834 struct sci_port *sport = to_sci_port(port);
1835
1836 port->type = sport->cfg->type;
1837 sci_request_port(port);
1838 }
1839}
1840
1841static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1842{
1843 struct sci_port *s = to_sci_port(port);
1844
1845 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1846 return -EINVAL;
1847 if (ser->baud_base < 2400)
1848 /* No paper tape reader for Mitch.. */
1849 return -EINVAL;
1850
1851 return 0;
1852}
1853
1854static struct uart_ops sci_uart_ops = {
1855 .tx_empty = sci_tx_empty,
1856 .set_mctrl = sci_set_mctrl,
1857 .get_mctrl = sci_get_mctrl,
1858 .start_tx = sci_start_tx,
1859 .stop_tx = sci_stop_tx,
1860 .stop_rx = sci_stop_rx,
1861 .enable_ms = sci_enable_ms,
1862 .break_ctl = sci_break_ctl,
1863 .startup = sci_startup,
1864 .shutdown = sci_shutdown,
1865 .set_termios = sci_set_termios,
1866 .type = sci_type,
1867 .release_port = sci_release_port,
1868 .request_port = sci_request_port,
1869 .config_port = sci_config_port,
1870 .verify_port = sci_verify_port,
1871#ifdef CONFIG_CONSOLE_POLL
1872 .poll_get_char = sci_poll_get_char,
1873 .poll_put_char = sci_poll_put_char,
1874#endif
1875};
1876
1877static int __devinit sci_init_single(struct platform_device *dev,
1878 struct sci_port *sci_port,
1879 unsigned int index,
1880 struct plat_sci_port *p)
1881{
1882 struct uart_port *port = &sci_port->port;
1883 int ret;
1884
1885 port->ops = &sci_uart_ops;
1886 port->iotype = UPIO_MEM;
1887 port->line = index;
1888
1889 switch (p->type) {
1890 case PORT_SCIFB:
1891 port->fifosize = 256;
1892 break;
1893 case PORT_SCIFA:
1894 port->fifosize = 64;
1895 break;
1896 case PORT_SCIF:
1897 port->fifosize = 16;
1898 break;
1899 default:
1900 port->fifosize = 1;
1901 break;
1902 }
1903
1904 if (p->regtype == SCIx_PROBE_REGTYPE) {
1905 ret = sci_probe_regmap(p);
1906 if (unlikely(ret))
1907 return ret;
1908 }
1909
1910 if (dev) {
1911 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
1912 if (IS_ERR(sci_port->iclk)) {
1913 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
1914 if (IS_ERR(sci_port->iclk)) {
1915 dev_err(&dev->dev, "can't get iclk\n");
1916 return PTR_ERR(sci_port->iclk);
1917 }
1918 }
1919
1920 /*
1921 * The function clock is optional, ignore it if we can't
1922 * find it.
1923 */
1924 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
1925 if (IS_ERR(sci_port->fclk))
1926 sci_port->fclk = NULL;
1927
1928 port->dev = &dev->dev;
1929
1930 pm_runtime_irq_safe(&dev->dev);
1931 pm_runtime_enable(&dev->dev);
1932 }
1933
1934 sci_port->break_timer.data = (unsigned long)sci_port;
1935 sci_port->break_timer.function = sci_break_timer;
1936 init_timer(&sci_port->break_timer);
1937
1938 /*
1939 * Establish some sensible defaults for the error detection.
1940 */
1941 if (!p->error_mask)
1942 p->error_mask = (p->type == PORT_SCI) ?
1943 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
1944
1945 /*
1946 * Establish sensible defaults for the overrun detection, unless
1947 * the part has explicitly disabled support for it.
1948 */
1949 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
1950 if (p->type == PORT_SCI)
1951 p->overrun_bit = 5;
1952 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
1953 p->overrun_bit = 9;
1954 else
1955 p->overrun_bit = 0;
1956
1957 /*
1958 * Make the error mask inclusive of overrun detection, if
1959 * supported.
1960 */
1961 p->error_mask |= (1 << p->overrun_bit);
1962 }
1963
1964 sci_port->cfg = p;
1965
1966 port->mapbase = p->mapbase;
1967 port->type = p->type;
1968 port->flags = p->flags;
1969 port->regshift = p->regshift;
1970
1971 /*
1972 * The UART port needs an IRQ value, so we peg this to the RX IRQ
1973 * for the multi-IRQ ports, which is where we are primarily
1974 * concerned with the shutdown path synchronization.
1975 *
1976 * For the muxed case there's nothing more to do.
1977 */
1978 port->irq = p->irqs[SCIx_RXI_IRQ];
1979 port->irqflags = IRQF_DISABLED;
1980
1981 port->serial_in = sci_serial_in;
1982 port->serial_out = sci_serial_out;
1983
1984 if (p->dma_dev)
1985 dev_dbg(port->dev, "DMA device %p, tx %d, rx %d\n",
1986 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx);
1987
1988 return 0;
1989}
1990
1991#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1992static void serial_console_putchar(struct uart_port *port, int ch)
1993{
1994 sci_poll_put_char(port, ch);
1995}
1996
1997/*
1998 * Print a string to the serial port trying not to disturb
1999 * any possible real use of the port...
2000 */
2001static void serial_console_write(struct console *co, const char *s,
2002 unsigned count)
2003{
2004 struct sci_port *sci_port = &sci_ports[co->index];
2005 struct uart_port *port = &sci_port->port;
2006 unsigned short bits;
2007
2008 sci_port_enable(sci_port);
2009
2010 uart_console_write(port, s, count, serial_console_putchar);
2011
2012 /* wait until fifo is empty and last bit has been transmitted */
2013 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2014 while ((sci_in(port, SCxSR) & bits) != bits)
2015 cpu_relax();
2016
2017 sci_port_disable(sci_port);
2018}
2019
2020static int __devinit serial_console_setup(struct console *co, char *options)
2021{
2022 struct sci_port *sci_port;
2023 struct uart_port *port;
2024 int baud = 115200;
2025 int bits = 8;
2026 int parity = 'n';
2027 int flow = 'n';
2028 int ret;
2029
2030 /*
2031 * Refuse to handle any bogus ports.
2032 */
2033 if (co->index < 0 || co->index >= SCI_NPORTS)
2034 return -ENODEV;
2035
2036 sci_port = &sci_ports[co->index];
2037 port = &sci_port->port;
2038
2039 /*
2040 * Refuse to handle uninitialized ports.
2041 */
2042 if (!port->ops)
2043 return -ENODEV;
2044
2045 ret = sci_remap_port(port);
2046 if (unlikely(ret != 0))
2047 return ret;
2048
2049 sci_port_enable(sci_port);
2050
2051 if (options)
2052 uart_parse_options(options, &baud, &parity, &bits, &flow);
2053
2054 sci_port_disable(sci_port);
2055
2056 return uart_set_options(port, co, baud, parity, bits, flow);
2057}
2058
2059static struct console serial_console = {
2060 .name = "ttySC",
2061 .device = uart_console_device,
2062 .write = serial_console_write,
2063 .setup = serial_console_setup,
2064 .flags = CON_PRINTBUFFER,
2065 .index = -1,
2066 .data = &sci_uart_driver,
2067};
2068
2069static struct console early_serial_console = {
2070 .name = "early_ttySC",
2071 .write = serial_console_write,
2072 .flags = CON_PRINTBUFFER,
2073 .index = -1,
2074};
2075
2076static char early_serial_buf[32];
2077
2078static int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2079{
2080 struct plat_sci_port *cfg = pdev->dev.platform_data;
2081
2082 if (early_serial_console.data)
2083 return -EEXIST;
2084
2085 early_serial_console.index = pdev->id;
2086
2087 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
2088
2089 serial_console_setup(&early_serial_console, early_serial_buf);
2090
2091 if (!strstr(early_serial_buf, "keep"))
2092 early_serial_console.flags |= CON_BOOT;
2093
2094 register_console(&early_serial_console);
2095 return 0;
2096}
2097
2098#define uart_console(port) ((port)->cons->index == (port)->line)
2099
2100static int sci_runtime_suspend(struct device *dev)
2101{
2102 struct sci_port *sci_port = dev_get_drvdata(dev);
2103 struct uart_port *port = &sci_port->port;
2104
2105 if (uart_console(port)) {
2106 sci_port->saved_smr = sci_in(port, SCSMR);
2107 sci_port->saved_brr = sci_in(port, SCBRR);
2108 sci_port->saved_fcr = sci_in(port, SCFCR);
2109 }
2110 return 0;
2111}
2112
2113static int sci_runtime_resume(struct device *dev)
2114{
2115 struct sci_port *sci_port = dev_get_drvdata(dev);
2116 struct uart_port *port = &sci_port->port;
2117
2118 if (uart_console(port)) {
2119 sci_reset(port);
2120 sci_out(port, SCSMR, sci_port->saved_smr);
2121 sci_out(port, SCBRR, sci_port->saved_brr);
2122 sci_out(port, SCFCR, sci_port->saved_fcr);
2123 sci_out(port, SCSCR, sci_port->cfg->scscr);
2124 }
2125 return 0;
2126}
2127
2128#define SCI_CONSOLE (&serial_console)
2129
2130#else
2131static inline int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2132{
2133 return -EINVAL;
2134}
2135
2136#define SCI_CONSOLE NULL
2137#define sci_runtime_suspend NULL
2138#define sci_runtime_resume NULL
2139
2140#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2141
2142static char banner[] __initdata =
2143 KERN_INFO "SuperH SCI(F) driver initialized\n";
2144
2145static struct uart_driver sci_uart_driver = {
2146 .owner = THIS_MODULE,
2147 .driver_name = "sci",
2148 .dev_name = "ttySC",
2149 .major = SCI_MAJOR,
2150 .minor = SCI_MINOR_START,
2151 .nr = SCI_NPORTS,
2152 .cons = SCI_CONSOLE,
2153};
2154
2155static int sci_remove(struct platform_device *dev)
2156{
2157 struct sci_port *port = platform_get_drvdata(dev);
2158
2159 cpufreq_unregister_notifier(&port->freq_transition,
2160 CPUFREQ_TRANSITION_NOTIFIER);
2161
2162 uart_remove_one_port(&sci_uart_driver, &port->port);
2163
2164 clk_put(port->iclk);
2165 clk_put(port->fclk);
2166
2167 pm_runtime_disable(&dev->dev);
2168 return 0;
2169}
2170
2171static int __devinit sci_probe_single(struct platform_device *dev,
2172 unsigned int index,
2173 struct plat_sci_port *p,
2174 struct sci_port *sciport)
2175{
2176 int ret;
2177
2178 /* Sanity check */
2179 if (unlikely(index >= SCI_NPORTS)) {
2180 dev_notice(&dev->dev, "Attempting to register port "
2181 "%d when only %d are available.\n",
2182 index+1, SCI_NPORTS);
2183 dev_notice(&dev->dev, "Consider bumping "
2184 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2185 return 0;
2186 }
2187
2188 ret = sci_init_single(dev, sciport, index, p);
2189 if (ret)
2190 return ret;
2191
2192 return uart_add_one_port(&sci_uart_driver, &sciport->port);
2193}
2194
2195static int __devinit sci_probe(struct platform_device *dev)
2196{
2197 struct plat_sci_port *p = dev->dev.platform_data;
2198 struct sci_port *sp = &sci_ports[dev->id];
2199 int ret;
2200
2201 /*
2202 * If we've come here via earlyprintk initialization, head off to
2203 * the special early probe. We don't have sufficient device state
2204 * to make it beyond this yet.
2205 */
2206 if (is_early_platform_device(dev))
2207 return sci_probe_earlyprintk(dev);
2208
2209 platform_set_drvdata(dev, sp);
2210
2211 ret = sci_probe_single(dev, dev->id, p, sp);
2212 if (ret)
2213 goto err_unreg;
2214
2215 sp->freq_transition.notifier_call = sci_notifier;
2216
2217 ret = cpufreq_register_notifier(&sp->freq_transition,
2218 CPUFREQ_TRANSITION_NOTIFIER);
2219 if (unlikely(ret < 0))
2220 goto err_unreg;
2221
2222#ifdef CONFIG_SH_STANDARD_BIOS
2223 sh_bios_gdb_detach();
2224#endif
2225
2226 return 0;
2227
2228err_unreg:
2229 sci_remove(dev);
2230 return ret;
2231}
2232
2233static int sci_suspend(struct device *dev)
2234{
2235 struct sci_port *sport = dev_get_drvdata(dev);
2236
2237 if (sport)
2238 uart_suspend_port(&sci_uart_driver, &sport->port);
2239
2240 return 0;
2241}
2242
2243static int sci_resume(struct device *dev)
2244{
2245 struct sci_port *sport = dev_get_drvdata(dev);
2246
2247 if (sport)
2248 uart_resume_port(&sci_uart_driver, &sport->port);
2249
2250 return 0;
2251}
2252
2253static const struct dev_pm_ops sci_dev_pm_ops = {
2254 .runtime_suspend = sci_runtime_suspend,
2255 .runtime_resume = sci_runtime_resume,
2256 .suspend = sci_suspend,
2257 .resume = sci_resume,
2258};
2259
2260static struct platform_driver sci_driver = {
2261 .probe = sci_probe,
2262 .remove = sci_remove,
2263 .driver = {
2264 .name = "sh-sci",
2265 .owner = THIS_MODULE,
2266 .pm = &sci_dev_pm_ops,
2267 },
2268};
2269
2270static int __init sci_init(void)
2271{
2272 int ret;
2273
2274 printk(banner);
2275
2276 ret = uart_register_driver(&sci_uart_driver);
2277 if (likely(ret == 0)) {
2278 ret = platform_driver_register(&sci_driver);
2279 if (unlikely(ret))
2280 uart_unregister_driver(&sci_uart_driver);
2281 }
2282
2283 return ret;
2284}
2285
2286static void __exit sci_exit(void)
2287{
2288 platform_driver_unregister(&sci_driver);
2289 uart_unregister_driver(&sci_uart_driver);
2290}
2291
2292#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2293early_platform_init_buffer("earlyprintk", &sci_driver,
2294 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2295#endif
2296module_init(sci_init);
2297module_exit(sci_exit);
2298
2299MODULE_LICENSE("GPL");
2300MODULE_ALIAS("platform:sh-sci");
2301MODULE_AUTHOR("Paul Mundt");
2302MODULE_DESCRIPTION("SuperH SCI(F) serial driver");
1/*
2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Copyright (C) 2015 Glider bvba
6 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 *
8 * based off of the old drivers/char/sh-sci.c by:
9 *
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15 * Removed SH7300 support (Jul 2007).
16 *
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details.
20 */
21#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22#define SUPPORT_SYSRQ
23#endif
24
25#undef DEBUG
26
27#include <linux/clk.h>
28#include <linux/console.h>
29#include <linux/ctype.h>
30#include <linux/cpufreq.h>
31#include <linux/delay.h>
32#include <linux/dmaengine.h>
33#include <linux/dma-mapping.h>
34#include <linux/err.h>
35#include <linux/errno.h>
36#include <linux/init.h>
37#include <linux/interrupt.h>
38#include <linux/ioport.h>
39#include <linux/major.h>
40#include <linux/module.h>
41#include <linux/mm.h>
42#include <linux/of.h>
43#include <linux/platform_device.h>
44#include <linux/pm_runtime.h>
45#include <linux/scatterlist.h>
46#include <linux/serial.h>
47#include <linux/serial_sci.h>
48#include <linux/sh_dma.h>
49#include <linux/slab.h>
50#include <linux/string.h>
51#include <linux/sysrq.h>
52#include <linux/timer.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
55
56#ifdef CONFIG_SUPERH
57#include <asm/sh_bios.h>
58#endif
59
60#include "serial_mctrl_gpio.h"
61#include "sh-sci.h"
62
63/* Offsets into the sci_port->irqs array */
64enum {
65 SCIx_ERI_IRQ,
66 SCIx_RXI_IRQ,
67 SCIx_TXI_IRQ,
68 SCIx_BRI_IRQ,
69 SCIx_NR_IRQS,
70
71 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
72};
73
74#define SCIx_IRQ_IS_MUXED(port) \
75 ((port)->irqs[SCIx_ERI_IRQ] == \
76 (port)->irqs[SCIx_RXI_IRQ]) || \
77 ((port)->irqs[SCIx_ERI_IRQ] && \
78 ((port)->irqs[SCIx_RXI_IRQ] < 0))
79
80enum SCI_CLKS {
81 SCI_FCK, /* Functional Clock */
82 SCI_SCK, /* Optional External Clock */
83 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
84 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
85 SCI_NUM_CLKS
86};
87
88/* Bit x set means sampling rate x + 1 is supported */
89#define SCI_SR(x) BIT((x) - 1)
90#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
91
92#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
93 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
94 SCI_SR(19) | SCI_SR(27)
95
96#define min_sr(_port) ffs((_port)->sampling_rate_mask)
97#define max_sr(_port) fls((_port)->sampling_rate_mask)
98
99/* Iterate over all supported sampling rates, from high to low */
100#define for_each_sr(_sr, _port) \
101 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
102 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
103
104struct sci_port {
105 struct uart_port port;
106
107 /* Platform configuration */
108 struct plat_sci_port *cfg;
109 unsigned int overrun_reg;
110 unsigned int overrun_mask;
111 unsigned int error_mask;
112 unsigned int error_clear;
113 unsigned int sampling_rate_mask;
114 resource_size_t reg_size;
115 struct mctrl_gpios *gpios;
116
117 /* Break timer */
118 struct timer_list break_timer;
119 int break_flag;
120
121 /* Clocks */
122 struct clk *clks[SCI_NUM_CLKS];
123 unsigned long clk_rates[SCI_NUM_CLKS];
124
125 int irqs[SCIx_NR_IRQS];
126 char *irqstr[SCIx_NR_IRQS];
127
128 struct dma_chan *chan_tx;
129 struct dma_chan *chan_rx;
130
131#ifdef CONFIG_SERIAL_SH_SCI_DMA
132 dma_cookie_t cookie_tx;
133 dma_cookie_t cookie_rx[2];
134 dma_cookie_t active_rx;
135 dma_addr_t tx_dma_addr;
136 unsigned int tx_dma_len;
137 struct scatterlist sg_rx[2];
138 void *rx_buf[2];
139 size_t buf_len_rx;
140 struct work_struct work_tx;
141 struct timer_list rx_timer;
142 unsigned int rx_timeout;
143#endif
144
145 bool autorts;
146};
147
148#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
149
150static struct sci_port sci_ports[SCI_NPORTS];
151static struct uart_driver sci_uart_driver;
152
153static inline struct sci_port *
154to_sci_port(struct uart_port *uart)
155{
156 return container_of(uart, struct sci_port, port);
157}
158
159struct plat_sci_reg {
160 u8 offset, size;
161};
162
163/* Helper for invalidating specific entries of an inherited map. */
164#define sci_reg_invalid { .offset = 0, .size = 0 }
165
166static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
167 [SCIx_PROBE_REGTYPE] = {
168 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
169 },
170
171 /*
172 * Common SCI definitions, dependent on the port's regshift
173 * value.
174 */
175 [SCIx_SCI_REGTYPE] = {
176 [SCSMR] = { 0x00, 8 },
177 [SCBRR] = { 0x01, 8 },
178 [SCSCR] = { 0x02, 8 },
179 [SCxTDR] = { 0x03, 8 },
180 [SCxSR] = { 0x04, 8 },
181 [SCxRDR] = { 0x05, 8 },
182 [SCFCR] = sci_reg_invalid,
183 [SCFDR] = sci_reg_invalid,
184 [SCTFDR] = sci_reg_invalid,
185 [SCRFDR] = sci_reg_invalid,
186 [SCSPTR] = sci_reg_invalid,
187 [SCLSR] = sci_reg_invalid,
188 [HSSRR] = sci_reg_invalid,
189 [SCPCR] = sci_reg_invalid,
190 [SCPDR] = sci_reg_invalid,
191 [SCDL] = sci_reg_invalid,
192 [SCCKS] = sci_reg_invalid,
193 },
194
195 /*
196 * Common definitions for legacy IrDA ports, dependent on
197 * regshift value.
198 */
199 [SCIx_IRDA_REGTYPE] = {
200 [SCSMR] = { 0x00, 8 },
201 [SCBRR] = { 0x01, 8 },
202 [SCSCR] = { 0x02, 8 },
203 [SCxTDR] = { 0x03, 8 },
204 [SCxSR] = { 0x04, 8 },
205 [SCxRDR] = { 0x05, 8 },
206 [SCFCR] = { 0x06, 8 },
207 [SCFDR] = { 0x07, 16 },
208 [SCTFDR] = sci_reg_invalid,
209 [SCRFDR] = sci_reg_invalid,
210 [SCSPTR] = sci_reg_invalid,
211 [SCLSR] = sci_reg_invalid,
212 [HSSRR] = sci_reg_invalid,
213 [SCPCR] = sci_reg_invalid,
214 [SCPDR] = sci_reg_invalid,
215 [SCDL] = sci_reg_invalid,
216 [SCCKS] = sci_reg_invalid,
217 },
218
219 /*
220 * Common SCIFA definitions.
221 */
222 [SCIx_SCIFA_REGTYPE] = {
223 [SCSMR] = { 0x00, 16 },
224 [SCBRR] = { 0x04, 8 },
225 [SCSCR] = { 0x08, 16 },
226 [SCxTDR] = { 0x20, 8 },
227 [SCxSR] = { 0x14, 16 },
228 [SCxRDR] = { 0x24, 8 },
229 [SCFCR] = { 0x18, 16 },
230 [SCFDR] = { 0x1c, 16 },
231 [SCTFDR] = sci_reg_invalid,
232 [SCRFDR] = sci_reg_invalid,
233 [SCSPTR] = sci_reg_invalid,
234 [SCLSR] = sci_reg_invalid,
235 [HSSRR] = sci_reg_invalid,
236 [SCPCR] = { 0x30, 16 },
237 [SCPDR] = { 0x34, 16 },
238 [SCDL] = sci_reg_invalid,
239 [SCCKS] = sci_reg_invalid,
240 },
241
242 /*
243 * Common SCIFB definitions.
244 */
245 [SCIx_SCIFB_REGTYPE] = {
246 [SCSMR] = { 0x00, 16 },
247 [SCBRR] = { 0x04, 8 },
248 [SCSCR] = { 0x08, 16 },
249 [SCxTDR] = { 0x40, 8 },
250 [SCxSR] = { 0x14, 16 },
251 [SCxRDR] = { 0x60, 8 },
252 [SCFCR] = { 0x18, 16 },
253 [SCFDR] = sci_reg_invalid,
254 [SCTFDR] = { 0x38, 16 },
255 [SCRFDR] = { 0x3c, 16 },
256 [SCSPTR] = sci_reg_invalid,
257 [SCLSR] = sci_reg_invalid,
258 [HSSRR] = sci_reg_invalid,
259 [SCPCR] = { 0x30, 16 },
260 [SCPDR] = { 0x34, 16 },
261 [SCDL] = sci_reg_invalid,
262 [SCCKS] = sci_reg_invalid,
263 },
264
265 /*
266 * Common SH-2(A) SCIF definitions for ports with FIFO data
267 * count registers.
268 */
269 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
270 [SCSMR] = { 0x00, 16 },
271 [SCBRR] = { 0x04, 8 },
272 [SCSCR] = { 0x08, 16 },
273 [SCxTDR] = { 0x0c, 8 },
274 [SCxSR] = { 0x10, 16 },
275 [SCxRDR] = { 0x14, 8 },
276 [SCFCR] = { 0x18, 16 },
277 [SCFDR] = { 0x1c, 16 },
278 [SCTFDR] = sci_reg_invalid,
279 [SCRFDR] = sci_reg_invalid,
280 [SCSPTR] = { 0x20, 16 },
281 [SCLSR] = { 0x24, 16 },
282 [HSSRR] = sci_reg_invalid,
283 [SCPCR] = sci_reg_invalid,
284 [SCPDR] = sci_reg_invalid,
285 [SCDL] = sci_reg_invalid,
286 [SCCKS] = sci_reg_invalid,
287 },
288
289 /*
290 * Common SH-3 SCIF definitions.
291 */
292 [SCIx_SH3_SCIF_REGTYPE] = {
293 [SCSMR] = { 0x00, 8 },
294 [SCBRR] = { 0x02, 8 },
295 [SCSCR] = { 0x04, 8 },
296 [SCxTDR] = { 0x06, 8 },
297 [SCxSR] = { 0x08, 16 },
298 [SCxRDR] = { 0x0a, 8 },
299 [SCFCR] = { 0x0c, 8 },
300 [SCFDR] = { 0x0e, 16 },
301 [SCTFDR] = sci_reg_invalid,
302 [SCRFDR] = sci_reg_invalid,
303 [SCSPTR] = sci_reg_invalid,
304 [SCLSR] = sci_reg_invalid,
305 [HSSRR] = sci_reg_invalid,
306 [SCPCR] = sci_reg_invalid,
307 [SCPDR] = sci_reg_invalid,
308 [SCDL] = sci_reg_invalid,
309 [SCCKS] = sci_reg_invalid,
310 },
311
312 /*
313 * Common SH-4(A) SCIF(B) definitions.
314 */
315 [SCIx_SH4_SCIF_REGTYPE] = {
316 [SCSMR] = { 0x00, 16 },
317 [SCBRR] = { 0x04, 8 },
318 [SCSCR] = { 0x08, 16 },
319 [SCxTDR] = { 0x0c, 8 },
320 [SCxSR] = { 0x10, 16 },
321 [SCxRDR] = { 0x14, 8 },
322 [SCFCR] = { 0x18, 16 },
323 [SCFDR] = { 0x1c, 16 },
324 [SCTFDR] = sci_reg_invalid,
325 [SCRFDR] = sci_reg_invalid,
326 [SCSPTR] = { 0x20, 16 },
327 [SCLSR] = { 0x24, 16 },
328 [HSSRR] = sci_reg_invalid,
329 [SCPCR] = sci_reg_invalid,
330 [SCPDR] = sci_reg_invalid,
331 [SCDL] = sci_reg_invalid,
332 [SCCKS] = sci_reg_invalid,
333 },
334
335 /*
336 * Common SCIF definitions for ports with a Baud Rate Generator for
337 * External Clock (BRG).
338 */
339 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
340 [SCSMR] = { 0x00, 16 },
341 [SCBRR] = { 0x04, 8 },
342 [SCSCR] = { 0x08, 16 },
343 [SCxTDR] = { 0x0c, 8 },
344 [SCxSR] = { 0x10, 16 },
345 [SCxRDR] = { 0x14, 8 },
346 [SCFCR] = { 0x18, 16 },
347 [SCFDR] = { 0x1c, 16 },
348 [SCTFDR] = sci_reg_invalid,
349 [SCRFDR] = sci_reg_invalid,
350 [SCSPTR] = { 0x20, 16 },
351 [SCLSR] = { 0x24, 16 },
352 [HSSRR] = sci_reg_invalid,
353 [SCPCR] = sci_reg_invalid,
354 [SCPDR] = sci_reg_invalid,
355 [SCDL] = { 0x30, 16 },
356 [SCCKS] = { 0x34, 16 },
357 },
358
359 /*
360 * Common HSCIF definitions.
361 */
362 [SCIx_HSCIF_REGTYPE] = {
363 [SCSMR] = { 0x00, 16 },
364 [SCBRR] = { 0x04, 8 },
365 [SCSCR] = { 0x08, 16 },
366 [SCxTDR] = { 0x0c, 8 },
367 [SCxSR] = { 0x10, 16 },
368 [SCxRDR] = { 0x14, 8 },
369 [SCFCR] = { 0x18, 16 },
370 [SCFDR] = { 0x1c, 16 },
371 [SCTFDR] = sci_reg_invalid,
372 [SCRFDR] = sci_reg_invalid,
373 [SCSPTR] = { 0x20, 16 },
374 [SCLSR] = { 0x24, 16 },
375 [HSSRR] = { 0x40, 16 },
376 [SCPCR] = sci_reg_invalid,
377 [SCPDR] = sci_reg_invalid,
378 [SCDL] = { 0x30, 16 },
379 [SCCKS] = { 0x34, 16 },
380 },
381
382 /*
383 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
384 * register.
385 */
386 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
387 [SCSMR] = { 0x00, 16 },
388 [SCBRR] = { 0x04, 8 },
389 [SCSCR] = { 0x08, 16 },
390 [SCxTDR] = { 0x0c, 8 },
391 [SCxSR] = { 0x10, 16 },
392 [SCxRDR] = { 0x14, 8 },
393 [SCFCR] = { 0x18, 16 },
394 [SCFDR] = { 0x1c, 16 },
395 [SCTFDR] = sci_reg_invalid,
396 [SCRFDR] = sci_reg_invalid,
397 [SCSPTR] = sci_reg_invalid,
398 [SCLSR] = { 0x24, 16 },
399 [HSSRR] = sci_reg_invalid,
400 [SCPCR] = sci_reg_invalid,
401 [SCPDR] = sci_reg_invalid,
402 [SCDL] = sci_reg_invalid,
403 [SCCKS] = sci_reg_invalid,
404 },
405
406 /*
407 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
408 * count registers.
409 */
410 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
411 [SCSMR] = { 0x00, 16 },
412 [SCBRR] = { 0x04, 8 },
413 [SCSCR] = { 0x08, 16 },
414 [SCxTDR] = { 0x0c, 8 },
415 [SCxSR] = { 0x10, 16 },
416 [SCxRDR] = { 0x14, 8 },
417 [SCFCR] = { 0x18, 16 },
418 [SCFDR] = { 0x1c, 16 },
419 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
420 [SCRFDR] = { 0x20, 16 },
421 [SCSPTR] = { 0x24, 16 },
422 [SCLSR] = { 0x28, 16 },
423 [HSSRR] = sci_reg_invalid,
424 [SCPCR] = sci_reg_invalid,
425 [SCPDR] = sci_reg_invalid,
426 [SCDL] = sci_reg_invalid,
427 [SCCKS] = sci_reg_invalid,
428 },
429
430 /*
431 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
432 * registers.
433 */
434 [SCIx_SH7705_SCIF_REGTYPE] = {
435 [SCSMR] = { 0x00, 16 },
436 [SCBRR] = { 0x04, 8 },
437 [SCSCR] = { 0x08, 16 },
438 [SCxTDR] = { 0x20, 8 },
439 [SCxSR] = { 0x14, 16 },
440 [SCxRDR] = { 0x24, 8 },
441 [SCFCR] = { 0x18, 16 },
442 [SCFDR] = { 0x1c, 16 },
443 [SCTFDR] = sci_reg_invalid,
444 [SCRFDR] = sci_reg_invalid,
445 [SCSPTR] = sci_reg_invalid,
446 [SCLSR] = sci_reg_invalid,
447 [HSSRR] = sci_reg_invalid,
448 [SCPCR] = sci_reg_invalid,
449 [SCPDR] = sci_reg_invalid,
450 [SCDL] = sci_reg_invalid,
451 [SCCKS] = sci_reg_invalid,
452 },
453};
454
455#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
456
457/*
458 * The "offset" here is rather misleading, in that it refers to an enum
459 * value relative to the port mapping rather than the fixed offset
460 * itself, which needs to be manually retrieved from the platform's
461 * register map for the given port.
462 */
463static unsigned int sci_serial_in(struct uart_port *p, int offset)
464{
465 const struct plat_sci_reg *reg = sci_getreg(p, offset);
466
467 if (reg->size == 8)
468 return ioread8(p->membase + (reg->offset << p->regshift));
469 else if (reg->size == 16)
470 return ioread16(p->membase + (reg->offset << p->regshift));
471 else
472 WARN(1, "Invalid register access\n");
473
474 return 0;
475}
476
477static void sci_serial_out(struct uart_port *p, int offset, int value)
478{
479 const struct plat_sci_reg *reg = sci_getreg(p, offset);
480
481 if (reg->size == 8)
482 iowrite8(value, p->membase + (reg->offset << p->regshift));
483 else if (reg->size == 16)
484 iowrite16(value, p->membase + (reg->offset << p->regshift));
485 else
486 WARN(1, "Invalid register access\n");
487}
488
489static int sci_probe_regmap(struct plat_sci_port *cfg)
490{
491 switch (cfg->type) {
492 case PORT_SCI:
493 cfg->regtype = SCIx_SCI_REGTYPE;
494 break;
495 case PORT_IRDA:
496 cfg->regtype = SCIx_IRDA_REGTYPE;
497 break;
498 case PORT_SCIFA:
499 cfg->regtype = SCIx_SCIFA_REGTYPE;
500 break;
501 case PORT_SCIFB:
502 cfg->regtype = SCIx_SCIFB_REGTYPE;
503 break;
504 case PORT_SCIF:
505 /*
506 * The SH-4 is a bit of a misnomer here, although that's
507 * where this particular port layout originated. This
508 * configuration (or some slight variation thereof)
509 * remains the dominant model for all SCIFs.
510 */
511 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
512 break;
513 case PORT_HSCIF:
514 cfg->regtype = SCIx_HSCIF_REGTYPE;
515 break;
516 default:
517 pr_err("Can't probe register map for given port\n");
518 return -EINVAL;
519 }
520
521 return 0;
522}
523
524static void sci_port_enable(struct sci_port *sci_port)
525{
526 unsigned int i;
527
528 if (!sci_port->port.dev)
529 return;
530
531 pm_runtime_get_sync(sci_port->port.dev);
532
533 for (i = 0; i < SCI_NUM_CLKS; i++) {
534 clk_prepare_enable(sci_port->clks[i]);
535 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
536 }
537 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
538}
539
540static void sci_port_disable(struct sci_port *sci_port)
541{
542 unsigned int i;
543
544 if (!sci_port->port.dev)
545 return;
546
547 /* Cancel the break timer to ensure that the timer handler will not try
548 * to access the hardware with clocks and power disabled. Reset the
549 * break flag to make the break debouncing state machine ready for the
550 * next break.
551 */
552 del_timer_sync(&sci_port->break_timer);
553 sci_port->break_flag = 0;
554
555 for (i = SCI_NUM_CLKS; i-- > 0; )
556 clk_disable_unprepare(sci_port->clks[i]);
557
558 pm_runtime_put_sync(sci_port->port.dev);
559}
560
561static inline unsigned long port_rx_irq_mask(struct uart_port *port)
562{
563 /*
564 * Not all ports (such as SCIFA) will support REIE. Rather than
565 * special-casing the port type, we check the port initialization
566 * IRQ enable mask to see whether the IRQ is desired at all. If
567 * it's unset, it's logically inferred that there's no point in
568 * testing for it.
569 */
570 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
571}
572
573static void sci_start_tx(struct uart_port *port)
574{
575 struct sci_port *s = to_sci_port(port);
576 unsigned short ctrl;
577
578#ifdef CONFIG_SERIAL_SH_SCI_DMA
579 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
580 u16 new, scr = serial_port_in(port, SCSCR);
581 if (s->chan_tx)
582 new = scr | SCSCR_TDRQE;
583 else
584 new = scr & ~SCSCR_TDRQE;
585 if (new != scr)
586 serial_port_out(port, SCSCR, new);
587 }
588
589 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
590 dma_submit_error(s->cookie_tx)) {
591 s->cookie_tx = 0;
592 schedule_work(&s->work_tx);
593 }
594#endif
595
596 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
597 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
598 ctrl = serial_port_in(port, SCSCR);
599 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
600 }
601}
602
603static void sci_stop_tx(struct uart_port *port)
604{
605 unsigned short ctrl;
606
607 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
608 ctrl = serial_port_in(port, SCSCR);
609
610 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
611 ctrl &= ~SCSCR_TDRQE;
612
613 ctrl &= ~SCSCR_TIE;
614
615 serial_port_out(port, SCSCR, ctrl);
616}
617
618static void sci_start_rx(struct uart_port *port)
619{
620 unsigned short ctrl;
621
622 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
623
624 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
625 ctrl &= ~SCSCR_RDRQE;
626
627 serial_port_out(port, SCSCR, ctrl);
628}
629
630static void sci_stop_rx(struct uart_port *port)
631{
632 unsigned short ctrl;
633
634 ctrl = serial_port_in(port, SCSCR);
635
636 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
637 ctrl &= ~SCSCR_RDRQE;
638
639 ctrl &= ~port_rx_irq_mask(port);
640
641 serial_port_out(port, SCSCR, ctrl);
642}
643
644static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
645{
646 if (port->type == PORT_SCI) {
647 /* Just store the mask */
648 serial_port_out(port, SCxSR, mask);
649 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
650 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
651 /* Only clear the status bits we want to clear */
652 serial_port_out(port, SCxSR,
653 serial_port_in(port, SCxSR) & mask);
654 } else {
655 /* Store the mask, clear parity/framing errors */
656 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
657 }
658}
659
660#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
661 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
662
663#ifdef CONFIG_CONSOLE_POLL
664static int sci_poll_get_char(struct uart_port *port)
665{
666 unsigned short status;
667 int c;
668
669 do {
670 status = serial_port_in(port, SCxSR);
671 if (status & SCxSR_ERRORS(port)) {
672 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
673 continue;
674 }
675 break;
676 } while (1);
677
678 if (!(status & SCxSR_RDxF(port)))
679 return NO_POLL_CHAR;
680
681 c = serial_port_in(port, SCxRDR);
682
683 /* Dummy read */
684 serial_port_in(port, SCxSR);
685 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
686
687 return c;
688}
689#endif
690
691static void sci_poll_put_char(struct uart_port *port, unsigned char c)
692{
693 unsigned short status;
694
695 do {
696 status = serial_port_in(port, SCxSR);
697 } while (!(status & SCxSR_TDxE(port)));
698
699 serial_port_out(port, SCxTDR, c);
700 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
701}
702#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
703 CONFIG_SERIAL_SH_SCI_EARLYCON */
704
705static void sci_init_pins(struct uart_port *port, unsigned int cflag)
706{
707 struct sci_port *s = to_sci_port(port);
708
709 /*
710 * Use port-specific handler if provided.
711 */
712 if (s->cfg->ops && s->cfg->ops->init_pins) {
713 s->cfg->ops->init_pins(port, cflag);
714 return;
715 }
716
717 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
718 u16 ctrl = serial_port_in(port, SCPCR);
719
720 /* Enable RXD and TXD pin functions */
721 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
722 if (to_sci_port(port)->cfg->capabilities & SCIx_HAVE_RTSCTS) {
723 /* RTS# is output, driven 1 */
724 ctrl |= SCPCR_RTSC;
725 serial_port_out(port, SCPDR,
726 serial_port_in(port, SCPDR) | SCPDR_RTSD);
727 /* Enable CTS# pin function */
728 ctrl &= ~SCPCR_CTSC;
729 }
730 serial_port_out(port, SCPCR, ctrl);
731 } else if (sci_getreg(port, SCSPTR)->size) {
732 u16 status = serial_port_in(port, SCSPTR);
733
734 /* RTS# is output, driven 1 */
735 status |= SCSPTR_RTSIO | SCSPTR_RTSDT;
736 /* CTS# and SCK are inputs */
737 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
738 serial_port_out(port, SCSPTR, status);
739 }
740}
741
742static int sci_txfill(struct uart_port *port)
743{
744 const struct plat_sci_reg *reg;
745
746 reg = sci_getreg(port, SCTFDR);
747 if (reg->size)
748 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
749
750 reg = sci_getreg(port, SCFDR);
751 if (reg->size)
752 return serial_port_in(port, SCFDR) >> 8;
753
754 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
755}
756
757static int sci_txroom(struct uart_port *port)
758{
759 return port->fifosize - sci_txfill(port);
760}
761
762static int sci_rxfill(struct uart_port *port)
763{
764 const struct plat_sci_reg *reg;
765
766 reg = sci_getreg(port, SCRFDR);
767 if (reg->size)
768 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
769
770 reg = sci_getreg(port, SCFDR);
771 if (reg->size)
772 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
773
774 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
775}
776
777/*
778 * SCI helper for checking the state of the muxed port/RXD pins.
779 */
780static inline int sci_rxd_in(struct uart_port *port)
781{
782 struct sci_port *s = to_sci_port(port);
783
784 if (s->cfg->port_reg <= 0)
785 return 1;
786
787 /* Cast for ARM damage */
788 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
789}
790
791/* ********************************************************************** *
792 * the interrupt related routines *
793 * ********************************************************************** */
794
795static void sci_transmit_chars(struct uart_port *port)
796{
797 struct circ_buf *xmit = &port->state->xmit;
798 unsigned int stopped = uart_tx_stopped(port);
799 unsigned short status;
800 unsigned short ctrl;
801 int count;
802
803 status = serial_port_in(port, SCxSR);
804 if (!(status & SCxSR_TDxE(port))) {
805 ctrl = serial_port_in(port, SCSCR);
806 if (uart_circ_empty(xmit))
807 ctrl &= ~SCSCR_TIE;
808 else
809 ctrl |= SCSCR_TIE;
810 serial_port_out(port, SCSCR, ctrl);
811 return;
812 }
813
814 count = sci_txroom(port);
815
816 do {
817 unsigned char c;
818
819 if (port->x_char) {
820 c = port->x_char;
821 port->x_char = 0;
822 } else if (!uart_circ_empty(xmit) && !stopped) {
823 c = xmit->buf[xmit->tail];
824 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
825 } else {
826 break;
827 }
828
829 serial_port_out(port, SCxTDR, c);
830
831 port->icount.tx++;
832 } while (--count > 0);
833
834 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
835
836 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
837 uart_write_wakeup(port);
838 if (uart_circ_empty(xmit)) {
839 sci_stop_tx(port);
840 } else {
841 ctrl = serial_port_in(port, SCSCR);
842
843 if (port->type != PORT_SCI) {
844 serial_port_in(port, SCxSR); /* Dummy read */
845 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
846 }
847
848 ctrl |= SCSCR_TIE;
849 serial_port_out(port, SCSCR, ctrl);
850 }
851}
852
853/* On SH3, SCIF may read end-of-break as a space->mark char */
854#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
855
856static void sci_receive_chars(struct uart_port *port)
857{
858 struct sci_port *sci_port = to_sci_port(port);
859 struct tty_port *tport = &port->state->port;
860 int i, count, copied = 0;
861 unsigned short status;
862 unsigned char flag;
863
864 status = serial_port_in(port, SCxSR);
865 if (!(status & SCxSR_RDxF(port)))
866 return;
867
868 while (1) {
869 /* Don't copy more bytes than there is room for in the buffer */
870 count = tty_buffer_request_room(tport, sci_rxfill(port));
871
872 /* If for any reason we can't copy more data, we're done! */
873 if (count == 0)
874 break;
875
876 if (port->type == PORT_SCI) {
877 char c = serial_port_in(port, SCxRDR);
878 if (uart_handle_sysrq_char(port, c) ||
879 sci_port->break_flag)
880 count = 0;
881 else
882 tty_insert_flip_char(tport, c, TTY_NORMAL);
883 } else {
884 for (i = 0; i < count; i++) {
885 char c = serial_port_in(port, SCxRDR);
886
887 status = serial_port_in(port, SCxSR);
888#if defined(CONFIG_CPU_SH3)
889 /* Skip "chars" during break */
890 if (sci_port->break_flag) {
891 if ((c == 0) &&
892 (status & SCxSR_FER(port))) {
893 count--; i--;
894 continue;
895 }
896
897 /* Nonzero => end-of-break */
898 dev_dbg(port->dev, "debounce<%02x>\n", c);
899 sci_port->break_flag = 0;
900
901 if (STEPFN(c)) {
902 count--; i--;
903 continue;
904 }
905 }
906#endif /* CONFIG_CPU_SH3 */
907 if (uart_handle_sysrq_char(port, c)) {
908 count--; i--;
909 continue;
910 }
911
912 /* Store data and status */
913 if (status & SCxSR_FER(port)) {
914 flag = TTY_FRAME;
915 port->icount.frame++;
916 dev_notice(port->dev, "frame error\n");
917 } else if (status & SCxSR_PER(port)) {
918 flag = TTY_PARITY;
919 port->icount.parity++;
920 dev_notice(port->dev, "parity error\n");
921 } else
922 flag = TTY_NORMAL;
923
924 tty_insert_flip_char(tport, c, flag);
925 }
926 }
927
928 serial_port_in(port, SCxSR); /* dummy read */
929 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
930
931 copied += count;
932 port->icount.rx += count;
933 }
934
935 if (copied) {
936 /* Tell the rest of the system the news. New characters! */
937 tty_flip_buffer_push(tport);
938 } else {
939 serial_port_in(port, SCxSR); /* dummy read */
940 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
941 }
942}
943
944#define SCI_BREAK_JIFFIES (HZ/20)
945
946/*
947 * The sci generates interrupts during the break,
948 * 1 per millisecond or so during the break period, for 9600 baud.
949 * So dont bother disabling interrupts.
950 * But dont want more than 1 break event.
951 * Use a kernel timer to periodically poll the rx line until
952 * the break is finished.
953 */
954static inline void sci_schedule_break_timer(struct sci_port *port)
955{
956 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
957}
958
959/* Ensure that two consecutive samples find the break over. */
960static void sci_break_timer(unsigned long data)
961{
962 struct sci_port *port = (struct sci_port *)data;
963
964 if (sci_rxd_in(&port->port) == 0) {
965 port->break_flag = 1;
966 sci_schedule_break_timer(port);
967 } else if (port->break_flag == 1) {
968 /* break is over. */
969 port->break_flag = 2;
970 sci_schedule_break_timer(port);
971 } else
972 port->break_flag = 0;
973}
974
975static int sci_handle_errors(struct uart_port *port)
976{
977 int copied = 0;
978 unsigned short status = serial_port_in(port, SCxSR);
979 struct tty_port *tport = &port->state->port;
980 struct sci_port *s = to_sci_port(port);
981
982 /* Handle overruns */
983 if (status & s->overrun_mask) {
984 port->icount.overrun++;
985
986 /* overrun error */
987 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
988 copied++;
989
990 dev_notice(port->dev, "overrun error\n");
991 }
992
993 if (status & SCxSR_FER(port)) {
994 if (sci_rxd_in(port) == 0) {
995 /* Notify of BREAK */
996 struct sci_port *sci_port = to_sci_port(port);
997
998 if (!sci_port->break_flag) {
999 port->icount.brk++;
1000
1001 sci_port->break_flag = 1;
1002 sci_schedule_break_timer(sci_port);
1003
1004 /* Do sysrq handling. */
1005 if (uart_handle_break(port))
1006 return 0;
1007
1008 dev_dbg(port->dev, "BREAK detected\n");
1009
1010 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1011 copied++;
1012 }
1013
1014 } else {
1015 /* frame error */
1016 port->icount.frame++;
1017
1018 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
1019 copied++;
1020
1021 dev_notice(port->dev, "frame error\n");
1022 }
1023 }
1024
1025 if (status & SCxSR_PER(port)) {
1026 /* parity error */
1027 port->icount.parity++;
1028
1029 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
1030 copied++;
1031
1032 dev_notice(port->dev, "parity error\n");
1033 }
1034
1035 if (copied)
1036 tty_flip_buffer_push(tport);
1037
1038 return copied;
1039}
1040
1041static int sci_handle_fifo_overrun(struct uart_port *port)
1042{
1043 struct tty_port *tport = &port->state->port;
1044 struct sci_port *s = to_sci_port(port);
1045 const struct plat_sci_reg *reg;
1046 int copied = 0;
1047 u16 status;
1048
1049 reg = sci_getreg(port, s->overrun_reg);
1050 if (!reg->size)
1051 return 0;
1052
1053 status = serial_port_in(port, s->overrun_reg);
1054 if (status & s->overrun_mask) {
1055 status &= ~s->overrun_mask;
1056 serial_port_out(port, s->overrun_reg, status);
1057
1058 port->icount.overrun++;
1059
1060 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1061 tty_flip_buffer_push(tport);
1062
1063 dev_dbg(port->dev, "overrun error\n");
1064 copied++;
1065 }
1066
1067 return copied;
1068}
1069
1070static int sci_handle_breaks(struct uart_port *port)
1071{
1072 int copied = 0;
1073 unsigned short status = serial_port_in(port, SCxSR);
1074 struct tty_port *tport = &port->state->port;
1075 struct sci_port *s = to_sci_port(port);
1076
1077 if (uart_handle_break(port))
1078 return 0;
1079
1080 if (!s->break_flag && status & SCxSR_BRK(port)) {
1081#if defined(CONFIG_CPU_SH3)
1082 /* Debounce break */
1083 s->break_flag = 1;
1084#endif
1085
1086 port->icount.brk++;
1087
1088 /* Notify of BREAK */
1089 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1090 copied++;
1091
1092 dev_dbg(port->dev, "BREAK detected\n");
1093 }
1094
1095 if (copied)
1096 tty_flip_buffer_push(tport);
1097
1098 copied += sci_handle_fifo_overrun(port);
1099
1100 return copied;
1101}
1102
1103#ifdef CONFIG_SERIAL_SH_SCI_DMA
1104static void sci_dma_tx_complete(void *arg)
1105{
1106 struct sci_port *s = arg;
1107 struct uart_port *port = &s->port;
1108 struct circ_buf *xmit = &port->state->xmit;
1109 unsigned long flags;
1110
1111 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1112
1113 spin_lock_irqsave(&port->lock, flags);
1114
1115 xmit->tail += s->tx_dma_len;
1116 xmit->tail &= UART_XMIT_SIZE - 1;
1117
1118 port->icount.tx += s->tx_dma_len;
1119
1120 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1121 uart_write_wakeup(port);
1122
1123 if (!uart_circ_empty(xmit)) {
1124 s->cookie_tx = 0;
1125 schedule_work(&s->work_tx);
1126 } else {
1127 s->cookie_tx = -EINVAL;
1128 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1129 u16 ctrl = serial_port_in(port, SCSCR);
1130 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1131 }
1132 }
1133
1134 spin_unlock_irqrestore(&port->lock, flags);
1135}
1136
1137/* Locking: called with port lock held */
1138static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1139{
1140 struct uart_port *port = &s->port;
1141 struct tty_port *tport = &port->state->port;
1142 int copied;
1143
1144 copied = tty_insert_flip_string(tport, buf, count);
1145 if (copied < count)
1146 port->icount.buf_overrun++;
1147
1148 port->icount.rx += copied;
1149
1150 return copied;
1151}
1152
1153static int sci_dma_rx_find_active(struct sci_port *s)
1154{
1155 unsigned int i;
1156
1157 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1158 if (s->active_rx == s->cookie_rx[i])
1159 return i;
1160
1161 return -1;
1162}
1163
1164static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1165{
1166 struct dma_chan *chan = s->chan_rx;
1167 struct uart_port *port = &s->port;
1168 unsigned long flags;
1169
1170 spin_lock_irqsave(&port->lock, flags);
1171 s->chan_rx = NULL;
1172 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1173 spin_unlock_irqrestore(&port->lock, flags);
1174 dmaengine_terminate_all(chan);
1175 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1176 sg_dma_address(&s->sg_rx[0]));
1177 dma_release_channel(chan);
1178 if (enable_pio)
1179 sci_start_rx(port);
1180}
1181
1182static void sci_dma_rx_complete(void *arg)
1183{
1184 struct sci_port *s = arg;
1185 struct dma_chan *chan = s->chan_rx;
1186 struct uart_port *port = &s->port;
1187 struct dma_async_tx_descriptor *desc;
1188 unsigned long flags;
1189 int active, count = 0;
1190
1191 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1192 s->active_rx);
1193
1194 spin_lock_irqsave(&port->lock, flags);
1195
1196 active = sci_dma_rx_find_active(s);
1197 if (active >= 0)
1198 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1199
1200 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1201
1202 if (count)
1203 tty_flip_buffer_push(&port->state->port);
1204
1205 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1206 DMA_DEV_TO_MEM,
1207 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1208 if (!desc)
1209 goto fail;
1210
1211 desc->callback = sci_dma_rx_complete;
1212 desc->callback_param = s;
1213 s->cookie_rx[active] = dmaengine_submit(desc);
1214 if (dma_submit_error(s->cookie_rx[active]))
1215 goto fail;
1216
1217 s->active_rx = s->cookie_rx[!active];
1218
1219 dma_async_issue_pending(chan);
1220
1221 spin_unlock_irqrestore(&port->lock, flags);
1222 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1223 __func__, s->cookie_rx[active], active, s->active_rx);
1224 return;
1225
1226fail:
1227 spin_unlock_irqrestore(&port->lock, flags);
1228 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1229 sci_rx_dma_release(s, true);
1230}
1231
1232static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1233{
1234 struct dma_chan *chan = s->chan_tx;
1235 struct uart_port *port = &s->port;
1236 unsigned long flags;
1237
1238 spin_lock_irqsave(&port->lock, flags);
1239 s->chan_tx = NULL;
1240 s->cookie_tx = -EINVAL;
1241 spin_unlock_irqrestore(&port->lock, flags);
1242 dmaengine_terminate_all(chan);
1243 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1244 DMA_TO_DEVICE);
1245 dma_release_channel(chan);
1246 if (enable_pio)
1247 sci_start_tx(port);
1248}
1249
1250static void sci_submit_rx(struct sci_port *s)
1251{
1252 struct dma_chan *chan = s->chan_rx;
1253 int i;
1254
1255 for (i = 0; i < 2; i++) {
1256 struct scatterlist *sg = &s->sg_rx[i];
1257 struct dma_async_tx_descriptor *desc;
1258
1259 desc = dmaengine_prep_slave_sg(chan,
1260 sg, 1, DMA_DEV_TO_MEM,
1261 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1262 if (!desc)
1263 goto fail;
1264
1265 desc->callback = sci_dma_rx_complete;
1266 desc->callback_param = s;
1267 s->cookie_rx[i] = dmaengine_submit(desc);
1268 if (dma_submit_error(s->cookie_rx[i]))
1269 goto fail;
1270
1271 }
1272
1273 s->active_rx = s->cookie_rx[0];
1274
1275 dma_async_issue_pending(chan);
1276 return;
1277
1278fail:
1279 if (i)
1280 dmaengine_terminate_all(chan);
1281 for (i = 0; i < 2; i++)
1282 s->cookie_rx[i] = -EINVAL;
1283 s->active_rx = -EINVAL;
1284 sci_rx_dma_release(s, true);
1285}
1286
1287static void work_fn_tx(struct work_struct *work)
1288{
1289 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1290 struct dma_async_tx_descriptor *desc;
1291 struct dma_chan *chan = s->chan_tx;
1292 struct uart_port *port = &s->port;
1293 struct circ_buf *xmit = &port->state->xmit;
1294 dma_addr_t buf;
1295
1296 /*
1297 * DMA is idle now.
1298 * Port xmit buffer is already mapped, and it is one page... Just adjust
1299 * offsets and lengths. Since it is a circular buffer, we have to
1300 * transmit till the end, and then the rest. Take the port lock to get a
1301 * consistent xmit buffer state.
1302 */
1303 spin_lock_irq(&port->lock);
1304 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1305 s->tx_dma_len = min_t(unsigned int,
1306 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1307 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1308 spin_unlock_irq(&port->lock);
1309
1310 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1311 DMA_MEM_TO_DEV,
1312 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1313 if (!desc) {
1314 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1315 /* switch to PIO */
1316 sci_tx_dma_release(s, true);
1317 return;
1318 }
1319
1320 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1321 DMA_TO_DEVICE);
1322
1323 spin_lock_irq(&port->lock);
1324 desc->callback = sci_dma_tx_complete;
1325 desc->callback_param = s;
1326 spin_unlock_irq(&port->lock);
1327 s->cookie_tx = dmaengine_submit(desc);
1328 if (dma_submit_error(s->cookie_tx)) {
1329 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1330 /* switch to PIO */
1331 sci_tx_dma_release(s, true);
1332 return;
1333 }
1334
1335 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1336 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1337
1338 dma_async_issue_pending(chan);
1339}
1340
1341static void rx_timer_fn(unsigned long arg)
1342{
1343 struct sci_port *s = (struct sci_port *)arg;
1344 struct dma_chan *chan = s->chan_rx;
1345 struct uart_port *port = &s->port;
1346 struct dma_tx_state state;
1347 enum dma_status status;
1348 unsigned long flags;
1349 unsigned int read;
1350 int active, count;
1351 u16 scr;
1352
1353 dev_dbg(port->dev, "DMA Rx timed out\n");
1354
1355 spin_lock_irqsave(&port->lock, flags);
1356
1357 active = sci_dma_rx_find_active(s);
1358 if (active < 0) {
1359 spin_unlock_irqrestore(&port->lock, flags);
1360 return;
1361 }
1362
1363 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1364 if (status == DMA_COMPLETE) {
1365 spin_unlock_irqrestore(&port->lock, flags);
1366 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1367 s->active_rx, active);
1368
1369 /* Let packet complete handler take care of the packet */
1370 return;
1371 }
1372
1373 dmaengine_pause(chan);
1374
1375 /*
1376 * sometimes DMA transfer doesn't stop even if it is stopped and
1377 * data keeps on coming until transaction is complete so check
1378 * for DMA_COMPLETE again
1379 * Let packet complete handler take care of the packet
1380 */
1381 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1382 if (status == DMA_COMPLETE) {
1383 spin_unlock_irqrestore(&port->lock, flags);
1384 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1385 return;
1386 }
1387
1388 /* Handle incomplete DMA receive */
1389 dmaengine_terminate_all(s->chan_rx);
1390 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1391
1392 if (read) {
1393 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1394 if (count)
1395 tty_flip_buffer_push(&port->state->port);
1396 }
1397
1398 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1399 sci_submit_rx(s);
1400
1401 /* Direct new serial port interrupts back to CPU */
1402 scr = serial_port_in(port, SCSCR);
1403 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1404 scr &= ~SCSCR_RDRQE;
1405 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1406 }
1407 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1408
1409 spin_unlock_irqrestore(&port->lock, flags);
1410}
1411
1412static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1413 enum dma_transfer_direction dir,
1414 unsigned int id)
1415{
1416 dma_cap_mask_t mask;
1417 struct dma_chan *chan;
1418 struct dma_slave_config cfg;
1419 int ret;
1420
1421 dma_cap_zero(mask);
1422 dma_cap_set(DMA_SLAVE, mask);
1423
1424 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1425 (void *)(unsigned long)id, port->dev,
1426 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1427 if (!chan) {
1428 dev_warn(port->dev,
1429 "dma_request_slave_channel_compat failed\n");
1430 return NULL;
1431 }
1432
1433 memset(&cfg, 0, sizeof(cfg));
1434 cfg.direction = dir;
1435 if (dir == DMA_MEM_TO_DEV) {
1436 cfg.dst_addr = port->mapbase +
1437 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1438 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1439 } else {
1440 cfg.src_addr = port->mapbase +
1441 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1442 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1443 }
1444
1445 ret = dmaengine_slave_config(chan, &cfg);
1446 if (ret) {
1447 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1448 dma_release_channel(chan);
1449 return NULL;
1450 }
1451
1452 return chan;
1453}
1454
1455static void sci_request_dma(struct uart_port *port)
1456{
1457 struct sci_port *s = to_sci_port(port);
1458 struct dma_chan *chan;
1459
1460 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1461
1462 if (!port->dev->of_node &&
1463 (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
1464 return;
1465
1466 s->cookie_tx = -EINVAL;
1467 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
1468 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1469 if (chan) {
1470 s->chan_tx = chan;
1471 /* UART circular tx buffer is an aligned page. */
1472 s->tx_dma_addr = dma_map_single(chan->device->dev,
1473 port->state->xmit.buf,
1474 UART_XMIT_SIZE,
1475 DMA_TO_DEVICE);
1476 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1477 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1478 dma_release_channel(chan);
1479 s->chan_tx = NULL;
1480 } else {
1481 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1482 __func__, UART_XMIT_SIZE,
1483 port->state->xmit.buf, &s->tx_dma_addr);
1484 }
1485
1486 INIT_WORK(&s->work_tx, work_fn_tx);
1487 }
1488
1489 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
1490 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1491 if (chan) {
1492 unsigned int i;
1493 dma_addr_t dma;
1494 void *buf;
1495
1496 s->chan_rx = chan;
1497
1498 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1499 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1500 &dma, GFP_KERNEL);
1501 if (!buf) {
1502 dev_warn(port->dev,
1503 "Failed to allocate Rx dma buffer, using PIO\n");
1504 dma_release_channel(chan);
1505 s->chan_rx = NULL;
1506 return;
1507 }
1508
1509 for (i = 0; i < 2; i++) {
1510 struct scatterlist *sg = &s->sg_rx[i];
1511
1512 sg_init_table(sg, 1);
1513 s->rx_buf[i] = buf;
1514 sg_dma_address(sg) = dma;
1515 sg_dma_len(sg) = s->buf_len_rx;
1516
1517 buf += s->buf_len_rx;
1518 dma += s->buf_len_rx;
1519 }
1520
1521 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1522
1523 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1524 sci_submit_rx(s);
1525 }
1526}
1527
1528static void sci_free_dma(struct uart_port *port)
1529{
1530 struct sci_port *s = to_sci_port(port);
1531
1532 if (s->chan_tx)
1533 sci_tx_dma_release(s, false);
1534 if (s->chan_rx)
1535 sci_rx_dma_release(s, false);
1536}
1537#else
1538static inline void sci_request_dma(struct uart_port *port)
1539{
1540}
1541
1542static inline void sci_free_dma(struct uart_port *port)
1543{
1544}
1545#endif
1546
1547static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1548{
1549#ifdef CONFIG_SERIAL_SH_SCI_DMA
1550 struct uart_port *port = ptr;
1551 struct sci_port *s = to_sci_port(port);
1552
1553 if (s->chan_rx) {
1554 u16 scr = serial_port_in(port, SCSCR);
1555 u16 ssr = serial_port_in(port, SCxSR);
1556
1557 /* Disable future Rx interrupts */
1558 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1559 disable_irq_nosync(irq);
1560 scr |= SCSCR_RDRQE;
1561 } else {
1562 scr &= ~SCSCR_RIE;
1563 sci_submit_rx(s);
1564 }
1565 serial_port_out(port, SCSCR, scr);
1566 /* Clear current interrupt */
1567 serial_port_out(port, SCxSR,
1568 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1569 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1570 jiffies, s->rx_timeout);
1571 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1572
1573 return IRQ_HANDLED;
1574 }
1575#endif
1576
1577 /* I think sci_receive_chars has to be called irrespective
1578 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1579 * to be disabled?
1580 */
1581 sci_receive_chars(ptr);
1582
1583 return IRQ_HANDLED;
1584}
1585
1586static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1587{
1588 struct uart_port *port = ptr;
1589 unsigned long flags;
1590
1591 spin_lock_irqsave(&port->lock, flags);
1592 sci_transmit_chars(port);
1593 spin_unlock_irqrestore(&port->lock, flags);
1594
1595 return IRQ_HANDLED;
1596}
1597
1598static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1599{
1600 struct uart_port *port = ptr;
1601 struct sci_port *s = to_sci_port(port);
1602
1603 /* Handle errors */
1604 if (port->type == PORT_SCI) {
1605 if (sci_handle_errors(port)) {
1606 /* discard character in rx buffer */
1607 serial_port_in(port, SCxSR);
1608 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1609 }
1610 } else {
1611 sci_handle_fifo_overrun(port);
1612 if (!s->chan_rx)
1613 sci_receive_chars(ptr);
1614 }
1615
1616 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1617
1618 /* Kick the transmission */
1619 if (!s->chan_tx)
1620 sci_tx_interrupt(irq, ptr);
1621
1622 return IRQ_HANDLED;
1623}
1624
1625static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1626{
1627 struct uart_port *port = ptr;
1628
1629 /* Handle BREAKs */
1630 sci_handle_breaks(port);
1631 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1632
1633 return IRQ_HANDLED;
1634}
1635
1636static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1637{
1638 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1639 struct uart_port *port = ptr;
1640 struct sci_port *s = to_sci_port(port);
1641 irqreturn_t ret = IRQ_NONE;
1642
1643 ssr_status = serial_port_in(port, SCxSR);
1644 scr_status = serial_port_in(port, SCSCR);
1645 if (s->overrun_reg == SCxSR)
1646 orer_status = ssr_status;
1647 else {
1648 if (sci_getreg(port, s->overrun_reg)->size)
1649 orer_status = serial_port_in(port, s->overrun_reg);
1650 }
1651
1652 err_enabled = scr_status & port_rx_irq_mask(port);
1653
1654 /* Tx Interrupt */
1655 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1656 !s->chan_tx)
1657 ret = sci_tx_interrupt(irq, ptr);
1658
1659 /*
1660 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1661 * DR flags
1662 */
1663 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1664 (scr_status & SCSCR_RIE))
1665 ret = sci_rx_interrupt(irq, ptr);
1666
1667 /* Error Interrupt */
1668 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1669 ret = sci_er_interrupt(irq, ptr);
1670
1671 /* Break Interrupt */
1672 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1673 ret = sci_br_interrupt(irq, ptr);
1674
1675 /* Overrun Interrupt */
1676 if (orer_status & s->overrun_mask) {
1677 sci_handle_fifo_overrun(port);
1678 ret = IRQ_HANDLED;
1679 }
1680
1681 return ret;
1682}
1683
1684static const struct sci_irq_desc {
1685 const char *desc;
1686 irq_handler_t handler;
1687} sci_irq_desc[] = {
1688 /*
1689 * Split out handlers, the default case.
1690 */
1691 [SCIx_ERI_IRQ] = {
1692 .desc = "rx err",
1693 .handler = sci_er_interrupt,
1694 },
1695
1696 [SCIx_RXI_IRQ] = {
1697 .desc = "rx full",
1698 .handler = sci_rx_interrupt,
1699 },
1700
1701 [SCIx_TXI_IRQ] = {
1702 .desc = "tx empty",
1703 .handler = sci_tx_interrupt,
1704 },
1705
1706 [SCIx_BRI_IRQ] = {
1707 .desc = "break",
1708 .handler = sci_br_interrupt,
1709 },
1710
1711 /*
1712 * Special muxed handler.
1713 */
1714 [SCIx_MUX_IRQ] = {
1715 .desc = "mux",
1716 .handler = sci_mpxed_interrupt,
1717 },
1718};
1719
1720static int sci_request_irq(struct sci_port *port)
1721{
1722 struct uart_port *up = &port->port;
1723 int i, j, ret = 0;
1724
1725 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1726 const struct sci_irq_desc *desc;
1727 int irq;
1728
1729 if (SCIx_IRQ_IS_MUXED(port)) {
1730 i = SCIx_MUX_IRQ;
1731 irq = up->irq;
1732 } else {
1733 irq = port->irqs[i];
1734
1735 /*
1736 * Certain port types won't support all of the
1737 * available interrupt sources.
1738 */
1739 if (unlikely(irq < 0))
1740 continue;
1741 }
1742
1743 desc = sci_irq_desc + i;
1744 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1745 dev_name(up->dev), desc->desc);
1746 if (!port->irqstr[j])
1747 goto out_nomem;
1748
1749 ret = request_irq(irq, desc->handler, up->irqflags,
1750 port->irqstr[j], port);
1751 if (unlikely(ret)) {
1752 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1753 goto out_noirq;
1754 }
1755 }
1756
1757 return 0;
1758
1759out_noirq:
1760 while (--i >= 0)
1761 free_irq(port->irqs[i], port);
1762
1763out_nomem:
1764 while (--j >= 0)
1765 kfree(port->irqstr[j]);
1766
1767 return ret;
1768}
1769
1770static void sci_free_irq(struct sci_port *port)
1771{
1772 int i;
1773
1774 /*
1775 * Intentionally in reverse order so we iterate over the muxed
1776 * IRQ first.
1777 */
1778 for (i = 0; i < SCIx_NR_IRQS; i++) {
1779 int irq = port->irqs[i];
1780
1781 /*
1782 * Certain port types won't support all of the available
1783 * interrupt sources.
1784 */
1785 if (unlikely(irq < 0))
1786 continue;
1787
1788 free_irq(port->irqs[i], port);
1789 kfree(port->irqstr[i]);
1790
1791 if (SCIx_IRQ_IS_MUXED(port)) {
1792 /* If there's only one IRQ, we're done. */
1793 return;
1794 }
1795 }
1796}
1797
1798static unsigned int sci_tx_empty(struct uart_port *port)
1799{
1800 unsigned short status = serial_port_in(port, SCxSR);
1801 unsigned short in_tx_fifo = sci_txfill(port);
1802
1803 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1804}
1805
1806static void sci_set_rts(struct uart_port *port, bool state)
1807{
1808 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1809 u16 data = serial_port_in(port, SCPDR);
1810
1811 /* Active low */
1812 if (state)
1813 data &= ~SCPDR_RTSD;
1814 else
1815 data |= SCPDR_RTSD;
1816 serial_port_out(port, SCPDR, data);
1817
1818 /* RTS# is output */
1819 serial_port_out(port, SCPCR,
1820 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1821 } else if (sci_getreg(port, SCSPTR)->size) {
1822 u16 ctrl = serial_port_in(port, SCSPTR);
1823
1824 /* Active low */
1825 if (state)
1826 ctrl &= ~SCSPTR_RTSDT;
1827 else
1828 ctrl |= SCSPTR_RTSDT;
1829 serial_port_out(port, SCSPTR, ctrl);
1830 }
1831}
1832
1833static bool sci_get_cts(struct uart_port *port)
1834{
1835 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1836 /* Active low */
1837 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
1838 } else if (sci_getreg(port, SCSPTR)->size) {
1839 /* Active low */
1840 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
1841 }
1842
1843 return true;
1844}
1845
1846/*
1847 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1848 * CTS/RTS is supported in hardware by at least one port and controlled
1849 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1850 * handled via the ->init_pins() op, which is a bit of a one-way street,
1851 * lacking any ability to defer pin control -- this will later be
1852 * converted over to the GPIO framework).
1853 *
1854 * Other modes (such as loopback) are supported generically on certain
1855 * port types, but not others. For these it's sufficient to test for the
1856 * existence of the support register and simply ignore the port type.
1857 */
1858static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1859{
1860 struct sci_port *s = to_sci_port(port);
1861
1862 if (mctrl & TIOCM_LOOP) {
1863 const struct plat_sci_reg *reg;
1864
1865 /*
1866 * Standard loopback mode for SCFCR ports.
1867 */
1868 reg = sci_getreg(port, SCFCR);
1869 if (reg->size)
1870 serial_port_out(port, SCFCR,
1871 serial_port_in(port, SCFCR) |
1872 SCFCR_LOOP);
1873 }
1874
1875 mctrl_gpio_set(s->gpios, mctrl);
1876
1877 if (!(s->cfg->capabilities & SCIx_HAVE_RTSCTS))
1878 return;
1879
1880 if (!(mctrl & TIOCM_RTS)) {
1881 /* Disable Auto RTS */
1882 serial_port_out(port, SCFCR,
1883 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
1884
1885 /* Clear RTS */
1886 sci_set_rts(port, 0);
1887 } else if (s->autorts) {
1888 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1889 /* Enable RTS# pin function */
1890 serial_port_out(port, SCPCR,
1891 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
1892 }
1893
1894 /* Enable Auto RTS */
1895 serial_port_out(port, SCFCR,
1896 serial_port_in(port, SCFCR) | SCFCR_MCE);
1897 } else {
1898 /* Set RTS */
1899 sci_set_rts(port, 1);
1900 }
1901}
1902
1903static unsigned int sci_get_mctrl(struct uart_port *port)
1904{
1905 struct sci_port *s = to_sci_port(port);
1906 struct mctrl_gpios *gpios = s->gpios;
1907 unsigned int mctrl = 0;
1908
1909 mctrl_gpio_get(gpios, &mctrl);
1910
1911 /*
1912 * CTS/RTS is handled in hardware when supported, while nothing
1913 * else is wired up.
1914 */
1915 if (s->autorts) {
1916 if (sci_get_cts(port))
1917 mctrl |= TIOCM_CTS;
1918 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
1919 mctrl |= TIOCM_CTS;
1920 }
1921 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
1922 mctrl |= TIOCM_DSR;
1923 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
1924 mctrl |= TIOCM_CAR;
1925
1926 return mctrl;
1927}
1928
1929static void sci_enable_ms(struct uart_port *port)
1930{
1931 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
1932}
1933
1934static void sci_break_ctl(struct uart_port *port, int break_state)
1935{
1936 unsigned short scscr, scsptr;
1937
1938 /* check wheter the port has SCSPTR */
1939 if (!sci_getreg(port, SCSPTR)->size) {
1940 /*
1941 * Not supported by hardware. Most parts couple break and rx
1942 * interrupts together, with break detection always enabled.
1943 */
1944 return;
1945 }
1946
1947 scsptr = serial_port_in(port, SCSPTR);
1948 scscr = serial_port_in(port, SCSCR);
1949
1950 if (break_state == -1) {
1951 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1952 scscr &= ~SCSCR_TE;
1953 } else {
1954 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1955 scscr |= SCSCR_TE;
1956 }
1957
1958 serial_port_out(port, SCSPTR, scsptr);
1959 serial_port_out(port, SCSCR, scscr);
1960}
1961
1962static int sci_startup(struct uart_port *port)
1963{
1964 struct sci_port *s = to_sci_port(port);
1965 int ret;
1966
1967 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1968
1969 ret = sci_request_irq(s);
1970 if (unlikely(ret < 0))
1971 return ret;
1972
1973 sci_request_dma(port);
1974
1975 return 0;
1976}
1977
1978static void sci_shutdown(struct uart_port *port)
1979{
1980 struct sci_port *s = to_sci_port(port);
1981 unsigned long flags;
1982 u16 scr;
1983
1984 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1985
1986 s->autorts = false;
1987 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
1988
1989 spin_lock_irqsave(&port->lock, flags);
1990 sci_stop_rx(port);
1991 sci_stop_tx(port);
1992 /* Stop RX and TX, disable related interrupts, keep clock source */
1993 scr = serial_port_in(port, SCSCR);
1994 serial_port_out(port, SCSCR, scr & (SCSCR_CKE1 | SCSCR_CKE0));
1995 spin_unlock_irqrestore(&port->lock, flags);
1996
1997#ifdef CONFIG_SERIAL_SH_SCI_DMA
1998 if (s->chan_rx) {
1999 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2000 port->line);
2001 del_timer_sync(&s->rx_timer);
2002 }
2003#endif
2004
2005 sci_free_dma(port);
2006 sci_free_irq(s);
2007}
2008
2009static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2010 unsigned int *srr)
2011{
2012 unsigned long freq = s->clk_rates[SCI_SCK];
2013 int err, min_err = INT_MAX;
2014 unsigned int sr;
2015
2016 if (s->port.type != PORT_HSCIF)
2017 freq *= 2;
2018
2019 for_each_sr(sr, s) {
2020 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2021 if (abs(err) >= abs(min_err))
2022 continue;
2023
2024 min_err = err;
2025 *srr = sr - 1;
2026
2027 if (!err)
2028 break;
2029 }
2030
2031 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2032 *srr + 1);
2033 return min_err;
2034}
2035
2036static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2037 unsigned long freq, unsigned int *dlr,
2038 unsigned int *srr)
2039{
2040 int err, min_err = INT_MAX;
2041 unsigned int sr, dl;
2042
2043 if (s->port.type != PORT_HSCIF)
2044 freq *= 2;
2045
2046 for_each_sr(sr, s) {
2047 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2048 dl = clamp(dl, 1U, 65535U);
2049
2050 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2051 if (abs(err) >= abs(min_err))
2052 continue;
2053
2054 min_err = err;
2055 *dlr = dl;
2056 *srr = sr - 1;
2057
2058 if (!err)
2059 break;
2060 }
2061
2062 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2063 min_err, *dlr, *srr + 1);
2064 return min_err;
2065}
2066
2067/* calculate sample rate, BRR, and clock select */
2068static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2069 unsigned int *brr, unsigned int *srr,
2070 unsigned int *cks)
2071{
2072 unsigned long freq = s->clk_rates[SCI_FCK];
2073 unsigned int sr, br, prediv, scrate, c;
2074 int err, min_err = INT_MAX;
2075
2076 if (s->port.type != PORT_HSCIF)
2077 freq *= 2;
2078
2079 /*
2080 * Find the combination of sample rate and clock select with the
2081 * smallest deviation from the desired baud rate.
2082 * Prefer high sample rates to maximise the receive margin.
2083 *
2084 * M: Receive margin (%)
2085 * N: Ratio of bit rate to clock (N = sampling rate)
2086 * D: Clock duty (D = 0 to 1.0)
2087 * L: Frame length (L = 9 to 12)
2088 * F: Absolute value of clock frequency deviation
2089 *
2090 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2091 * (|D - 0.5| / N * (1 + F))|
2092 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2093 */
2094 for_each_sr(sr, s) {
2095 for (c = 0; c <= 3; c++) {
2096 /* integerized formulas from HSCIF documentation */
2097 prediv = sr * (1 << (2 * c + 1));
2098
2099 /*
2100 * We need to calculate:
2101 *
2102 * br = freq / (prediv * bps) clamped to [1..256]
2103 * err = freq / (br * prediv) - bps
2104 *
2105 * Watch out for overflow when calculating the desired
2106 * sampling clock rate!
2107 */
2108 if (bps > UINT_MAX / prediv)
2109 break;
2110
2111 scrate = prediv * bps;
2112 br = DIV_ROUND_CLOSEST(freq, scrate);
2113 br = clamp(br, 1U, 256U);
2114
2115 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2116 if (abs(err) >= abs(min_err))
2117 continue;
2118
2119 min_err = err;
2120 *brr = br - 1;
2121 *srr = sr - 1;
2122 *cks = c;
2123
2124 if (!err)
2125 goto found;
2126 }
2127 }
2128
2129found:
2130 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2131 min_err, *brr, *srr + 1, *cks);
2132 return min_err;
2133}
2134
2135static void sci_reset(struct uart_port *port)
2136{
2137 const struct plat_sci_reg *reg;
2138 unsigned int status;
2139
2140 do {
2141 status = serial_port_in(port, SCxSR);
2142 } while (!(status & SCxSR_TEND(port)));
2143
2144 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
2145
2146 reg = sci_getreg(port, SCFCR);
2147 if (reg->size)
2148 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2149
2150 sci_clear_SCxSR(port,
2151 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2152 SCxSR_BREAK_CLEAR(port));
2153 if (sci_getreg(port, SCLSR)->size) {
2154 status = serial_port_in(port, SCLSR);
2155 status &= ~(SCLSR_TO | SCLSR_ORER);
2156 serial_port_out(port, SCLSR, status);
2157 }
2158}
2159
2160static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2161 struct ktermios *old)
2162{
2163 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i;
2164 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2165 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2166 struct sci_port *s = to_sci_port(port);
2167 const struct plat_sci_reg *reg;
2168 int min_err = INT_MAX, err;
2169 unsigned long max_freq = 0;
2170 int best_clk = -1;
2171
2172 if ((termios->c_cflag & CSIZE) == CS7)
2173 smr_val |= SCSMR_CHR;
2174 if (termios->c_cflag & PARENB)
2175 smr_val |= SCSMR_PE;
2176 if (termios->c_cflag & PARODD)
2177 smr_val |= SCSMR_PE | SCSMR_ODD;
2178 if (termios->c_cflag & CSTOPB)
2179 smr_val |= SCSMR_STOP;
2180
2181 /*
2182 * earlyprintk comes here early on with port->uartclk set to zero.
2183 * the clock framework is not up and running at this point so here
2184 * we assume that 115200 is the maximum baud rate. please note that
2185 * the baud rate is not programmed during earlyprintk - it is assumed
2186 * that the previous boot loader has enabled required clocks and
2187 * setup the baud rate generator hardware for us already.
2188 */
2189 if (!port->uartclk) {
2190 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2191 goto done;
2192 }
2193
2194 for (i = 0; i < SCI_NUM_CLKS; i++)
2195 max_freq = max(max_freq, s->clk_rates[i]);
2196
2197 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2198 if (!baud)
2199 goto done;
2200
2201 /*
2202 * There can be multiple sources for the sampling clock. Find the one
2203 * that gives us the smallest deviation from the desired baud rate.
2204 */
2205
2206 /* Optional Undivided External Clock */
2207 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2208 port->type != PORT_SCIFB) {
2209 err = sci_sck_calc(s, baud, &srr1);
2210 if (abs(err) < abs(min_err)) {
2211 best_clk = SCI_SCK;
2212 scr_val = SCSCR_CKE1;
2213 sccks = SCCKS_CKS;
2214 min_err = err;
2215 srr = srr1;
2216 if (!err)
2217 goto done;
2218 }
2219 }
2220
2221 /* Optional BRG Frequency Divided External Clock */
2222 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2223 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2224 &srr1);
2225 if (abs(err) < abs(min_err)) {
2226 best_clk = SCI_SCIF_CLK;
2227 scr_val = SCSCR_CKE1;
2228 sccks = 0;
2229 min_err = err;
2230 dl = dl1;
2231 srr = srr1;
2232 if (!err)
2233 goto done;
2234 }
2235 }
2236
2237 /* Optional BRG Frequency Divided Internal Clock */
2238 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2239 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2240 &srr1);
2241 if (abs(err) < abs(min_err)) {
2242 best_clk = SCI_BRG_INT;
2243 scr_val = SCSCR_CKE1;
2244 sccks = SCCKS_XIN;
2245 min_err = err;
2246 dl = dl1;
2247 srr = srr1;
2248 if (!min_err)
2249 goto done;
2250 }
2251 }
2252
2253 /* Divided Functional Clock using standard Bit Rate Register */
2254 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2255 if (abs(err) < abs(min_err)) {
2256 best_clk = SCI_FCK;
2257 scr_val = 0;
2258 min_err = err;
2259 brr = brr1;
2260 srr = srr1;
2261 cks = cks1;
2262 }
2263
2264done:
2265 if (best_clk >= 0)
2266 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2267 s->clks[best_clk], baud, min_err);
2268
2269 sci_port_enable(s);
2270
2271 /*
2272 * Program the optional External Baud Rate Generator (BRG) first.
2273 * It controls the mux to select (H)SCK or frequency divided clock.
2274 */
2275 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2276 serial_port_out(port, SCDL, dl);
2277 serial_port_out(port, SCCKS, sccks);
2278 }
2279
2280 sci_reset(port);
2281
2282 uart_update_timeout(port, termios->c_cflag, baud);
2283
2284 if (best_clk >= 0) {
2285 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2286 switch (srr + 1) {
2287 case 5: smr_val |= SCSMR_SRC_5; break;
2288 case 7: smr_val |= SCSMR_SRC_7; break;
2289 case 11: smr_val |= SCSMR_SRC_11; break;
2290 case 13: smr_val |= SCSMR_SRC_13; break;
2291 case 16: smr_val |= SCSMR_SRC_16; break;
2292 case 17: smr_val |= SCSMR_SRC_17; break;
2293 case 19: smr_val |= SCSMR_SRC_19; break;
2294 case 27: smr_val |= SCSMR_SRC_27; break;
2295 }
2296 smr_val |= cks;
2297 dev_dbg(port->dev,
2298 "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
2299 scr_val, smr_val, brr, sccks, dl, srr);
2300 serial_port_out(port, SCSCR, scr_val);
2301 serial_port_out(port, SCSMR, smr_val);
2302 serial_port_out(port, SCBRR, brr);
2303 if (sci_getreg(port, HSSRR)->size)
2304 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2305
2306 /* Wait one bit interval */
2307 udelay((1000000 + (baud - 1)) / baud);
2308 } else {
2309 /* Don't touch the bit rate configuration */
2310 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2311 smr_val |= serial_port_in(port, SCSMR) &
2312 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2313 dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
2314 serial_port_out(port, SCSCR, scr_val);
2315 serial_port_out(port, SCSMR, smr_val);
2316 }
2317
2318 sci_init_pins(port, termios->c_cflag);
2319
2320 port->status &= ~UPSTAT_AUTOCTS;
2321 s->autorts = false;
2322 reg = sci_getreg(port, SCFCR);
2323 if (reg->size) {
2324 unsigned short ctrl = serial_port_in(port, SCFCR);
2325
2326 if ((port->flags & UPF_HARD_FLOW) &&
2327 (termios->c_cflag & CRTSCTS)) {
2328 /* There is no CTS interrupt to restart the hardware */
2329 port->status |= UPSTAT_AUTOCTS;
2330 /* MCE is enabled when RTS is raised */
2331 s->autorts = true;
2332 }
2333
2334 /*
2335 * As we've done a sci_reset() above, ensure we don't
2336 * interfere with the FIFOs while toggling MCE. As the
2337 * reset values could still be set, simply mask them out.
2338 */
2339 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2340
2341 serial_port_out(port, SCFCR, ctrl);
2342 }
2343
2344 scr_val |= s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0);
2345 dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
2346 serial_port_out(port, SCSCR, scr_val);
2347 if ((srr + 1 == 5) &&
2348 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2349 /*
2350 * In asynchronous mode, when the sampling rate is 1/5, first
2351 * received data may become invalid on some SCIFA and SCIFB.
2352 * To avoid this problem wait more than 1 serial data time (1
2353 * bit time x serial data number) after setting SCSCR.RE = 1.
2354 */
2355 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2356 }
2357
2358#ifdef CONFIG_SERIAL_SH_SCI_DMA
2359 /*
2360 * Calculate delay for 2 DMA buffers (4 FIFO).
2361 * See serial_core.c::uart_update_timeout().
2362 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2363 * function calculates 1 jiffie for the data plus 5 jiffies for the
2364 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2365 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2366 * value obtained by this formula is too small. Therefore, if the value
2367 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2368 */
2369 if (s->chan_rx) {
2370 unsigned int bits;
2371
2372 /* byte size and parity */
2373 switch (termios->c_cflag & CSIZE) {
2374 case CS5:
2375 bits = 7;
2376 break;
2377 case CS6:
2378 bits = 8;
2379 break;
2380 case CS7:
2381 bits = 9;
2382 break;
2383 default:
2384 bits = 10;
2385 break;
2386 }
2387
2388 if (termios->c_cflag & CSTOPB)
2389 bits++;
2390 if (termios->c_cflag & PARENB)
2391 bits++;
2392 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2393 (baud / 10), 10);
2394 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2395 s->rx_timeout * 1000 / HZ, port->timeout);
2396 if (s->rx_timeout < msecs_to_jiffies(20))
2397 s->rx_timeout = msecs_to_jiffies(20);
2398 }
2399#endif
2400
2401 if ((termios->c_cflag & CREAD) != 0)
2402 sci_start_rx(port);
2403
2404 sci_port_disable(s);
2405
2406 if (UART_ENABLE_MS(port, termios->c_cflag))
2407 sci_enable_ms(port);
2408}
2409
2410static void sci_pm(struct uart_port *port, unsigned int state,
2411 unsigned int oldstate)
2412{
2413 struct sci_port *sci_port = to_sci_port(port);
2414
2415 switch (state) {
2416 case UART_PM_STATE_OFF:
2417 sci_port_disable(sci_port);
2418 break;
2419 default:
2420 sci_port_enable(sci_port);
2421 break;
2422 }
2423}
2424
2425static const char *sci_type(struct uart_port *port)
2426{
2427 switch (port->type) {
2428 case PORT_IRDA:
2429 return "irda";
2430 case PORT_SCI:
2431 return "sci";
2432 case PORT_SCIF:
2433 return "scif";
2434 case PORT_SCIFA:
2435 return "scifa";
2436 case PORT_SCIFB:
2437 return "scifb";
2438 case PORT_HSCIF:
2439 return "hscif";
2440 }
2441
2442 return NULL;
2443}
2444
2445static int sci_remap_port(struct uart_port *port)
2446{
2447 struct sci_port *sport = to_sci_port(port);
2448
2449 /*
2450 * Nothing to do if there's already an established membase.
2451 */
2452 if (port->membase)
2453 return 0;
2454
2455 if (port->flags & UPF_IOREMAP) {
2456 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2457 if (unlikely(!port->membase)) {
2458 dev_err(port->dev, "can't remap port#%d\n", port->line);
2459 return -ENXIO;
2460 }
2461 } else {
2462 /*
2463 * For the simple (and majority of) cases where we don't
2464 * need to do any remapping, just cast the cookie
2465 * directly.
2466 */
2467 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2468 }
2469
2470 return 0;
2471}
2472
2473static void sci_release_port(struct uart_port *port)
2474{
2475 struct sci_port *sport = to_sci_port(port);
2476
2477 if (port->flags & UPF_IOREMAP) {
2478 iounmap(port->membase);
2479 port->membase = NULL;
2480 }
2481
2482 release_mem_region(port->mapbase, sport->reg_size);
2483}
2484
2485static int sci_request_port(struct uart_port *port)
2486{
2487 struct resource *res;
2488 struct sci_port *sport = to_sci_port(port);
2489 int ret;
2490
2491 res = request_mem_region(port->mapbase, sport->reg_size,
2492 dev_name(port->dev));
2493 if (unlikely(res == NULL)) {
2494 dev_err(port->dev, "request_mem_region failed.");
2495 return -EBUSY;
2496 }
2497
2498 ret = sci_remap_port(port);
2499 if (unlikely(ret != 0)) {
2500 release_resource(res);
2501 return ret;
2502 }
2503
2504 return 0;
2505}
2506
2507static void sci_config_port(struct uart_port *port, int flags)
2508{
2509 if (flags & UART_CONFIG_TYPE) {
2510 struct sci_port *sport = to_sci_port(port);
2511
2512 port->type = sport->cfg->type;
2513 sci_request_port(port);
2514 }
2515}
2516
2517static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2518{
2519 if (ser->baud_base < 2400)
2520 /* No paper tape reader for Mitch.. */
2521 return -EINVAL;
2522
2523 return 0;
2524}
2525
2526static const struct uart_ops sci_uart_ops = {
2527 .tx_empty = sci_tx_empty,
2528 .set_mctrl = sci_set_mctrl,
2529 .get_mctrl = sci_get_mctrl,
2530 .start_tx = sci_start_tx,
2531 .stop_tx = sci_stop_tx,
2532 .stop_rx = sci_stop_rx,
2533 .enable_ms = sci_enable_ms,
2534 .break_ctl = sci_break_ctl,
2535 .startup = sci_startup,
2536 .shutdown = sci_shutdown,
2537 .set_termios = sci_set_termios,
2538 .pm = sci_pm,
2539 .type = sci_type,
2540 .release_port = sci_release_port,
2541 .request_port = sci_request_port,
2542 .config_port = sci_config_port,
2543 .verify_port = sci_verify_port,
2544#ifdef CONFIG_CONSOLE_POLL
2545 .poll_get_char = sci_poll_get_char,
2546 .poll_put_char = sci_poll_put_char,
2547#endif
2548};
2549
2550static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2551{
2552 const char *clk_names[] = {
2553 [SCI_FCK] = "fck",
2554 [SCI_SCK] = "sck",
2555 [SCI_BRG_INT] = "brg_int",
2556 [SCI_SCIF_CLK] = "scif_clk",
2557 };
2558 struct clk *clk;
2559 unsigned int i;
2560
2561 if (sci_port->cfg->type == PORT_HSCIF)
2562 clk_names[SCI_SCK] = "hsck";
2563
2564 for (i = 0; i < SCI_NUM_CLKS; i++) {
2565 clk = devm_clk_get(dev, clk_names[i]);
2566 if (PTR_ERR(clk) == -EPROBE_DEFER)
2567 return -EPROBE_DEFER;
2568
2569 if (IS_ERR(clk) && i == SCI_FCK) {
2570 /*
2571 * "fck" used to be called "sci_ick", and we need to
2572 * maintain DT backward compatibility.
2573 */
2574 clk = devm_clk_get(dev, "sci_ick");
2575 if (PTR_ERR(clk) == -EPROBE_DEFER)
2576 return -EPROBE_DEFER;
2577
2578 if (!IS_ERR(clk))
2579 goto found;
2580
2581 /*
2582 * Not all SH platforms declare a clock lookup entry
2583 * for SCI devices, in which case we need to get the
2584 * global "peripheral_clk" clock.
2585 */
2586 clk = devm_clk_get(dev, "peripheral_clk");
2587 if (!IS_ERR(clk))
2588 goto found;
2589
2590 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2591 PTR_ERR(clk));
2592 return PTR_ERR(clk);
2593 }
2594
2595found:
2596 if (IS_ERR(clk))
2597 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2598 PTR_ERR(clk));
2599 else
2600 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2601 clk, clk);
2602 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2603 }
2604 return 0;
2605}
2606
2607static int sci_init_single(struct platform_device *dev,
2608 struct sci_port *sci_port, unsigned int index,
2609 struct plat_sci_port *p, bool early)
2610{
2611 struct uart_port *port = &sci_port->port;
2612 const struct resource *res;
2613 unsigned int i;
2614 int ret;
2615
2616 sci_port->cfg = p;
2617
2618 port->ops = &sci_uart_ops;
2619 port->iotype = UPIO_MEM;
2620 port->line = index;
2621
2622 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2623 if (res == NULL)
2624 return -ENOMEM;
2625
2626 port->mapbase = res->start;
2627 sci_port->reg_size = resource_size(res);
2628
2629 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2630 sci_port->irqs[i] = platform_get_irq(dev, i);
2631
2632 /* The SCI generates several interrupts. They can be muxed together or
2633 * connected to different interrupt lines. In the muxed case only one
2634 * interrupt resource is specified. In the non-muxed case three or four
2635 * interrupt resources are specified, as the BRI interrupt is optional.
2636 */
2637 if (sci_port->irqs[0] < 0)
2638 return -ENXIO;
2639
2640 if (sci_port->irqs[1] < 0) {
2641 sci_port->irqs[1] = sci_port->irqs[0];
2642 sci_port->irqs[2] = sci_port->irqs[0];
2643 sci_port->irqs[3] = sci_port->irqs[0];
2644 }
2645
2646 if (p->regtype == SCIx_PROBE_REGTYPE) {
2647 ret = sci_probe_regmap(p);
2648 if (unlikely(ret))
2649 return ret;
2650 }
2651
2652 switch (p->type) {
2653 case PORT_SCIFB:
2654 port->fifosize = 256;
2655 sci_port->overrun_reg = SCxSR;
2656 sci_port->overrun_mask = SCIFA_ORER;
2657 sci_port->sampling_rate_mask = SCI_SR_SCIFAB;
2658 break;
2659 case PORT_HSCIF:
2660 port->fifosize = 128;
2661 sci_port->overrun_reg = SCLSR;
2662 sci_port->overrun_mask = SCLSR_ORER;
2663 sci_port->sampling_rate_mask = SCI_SR_RANGE(8, 32);
2664 break;
2665 case PORT_SCIFA:
2666 port->fifosize = 64;
2667 sci_port->overrun_reg = SCxSR;
2668 sci_port->overrun_mask = SCIFA_ORER;
2669 sci_port->sampling_rate_mask = SCI_SR_SCIFAB;
2670 break;
2671 case PORT_SCIF:
2672 port->fifosize = 16;
2673 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2674 sci_port->overrun_reg = SCxSR;
2675 sci_port->overrun_mask = SCIFA_ORER;
2676 sci_port->sampling_rate_mask = SCI_SR(16);
2677 } else {
2678 sci_port->overrun_reg = SCLSR;
2679 sci_port->overrun_mask = SCLSR_ORER;
2680 sci_port->sampling_rate_mask = SCI_SR(32);
2681 }
2682 break;
2683 default:
2684 port->fifosize = 1;
2685 sci_port->overrun_reg = SCxSR;
2686 sci_port->overrun_mask = SCI_ORER;
2687 sci_port->sampling_rate_mask = SCI_SR(32);
2688 break;
2689 }
2690
2691 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2692 * match the SoC datasheet, this should be investigated. Let platform
2693 * data override the sampling rate for now.
2694 */
2695 if (p->sampling_rate)
2696 sci_port->sampling_rate_mask = SCI_SR(p->sampling_rate);
2697
2698 if (!early) {
2699 ret = sci_init_clocks(sci_port, &dev->dev);
2700 if (ret < 0)
2701 return ret;
2702
2703 port->dev = &dev->dev;
2704
2705 pm_runtime_enable(&dev->dev);
2706 }
2707
2708 sci_port->break_timer.data = (unsigned long)sci_port;
2709 sci_port->break_timer.function = sci_break_timer;
2710 init_timer(&sci_port->break_timer);
2711
2712 /*
2713 * Establish some sensible defaults for the error detection.
2714 */
2715 if (p->type == PORT_SCI) {
2716 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2717 sci_port->error_clear = SCI_ERROR_CLEAR;
2718 } else {
2719 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2720 sci_port->error_clear = SCIF_ERROR_CLEAR;
2721 }
2722
2723 /*
2724 * Make the error mask inclusive of overrun detection, if
2725 * supported.
2726 */
2727 if (sci_port->overrun_reg == SCxSR) {
2728 sci_port->error_mask |= sci_port->overrun_mask;
2729 sci_port->error_clear &= ~sci_port->overrun_mask;
2730 }
2731
2732 port->type = p->type;
2733 port->flags = UPF_FIXED_PORT | p->flags;
2734 port->regshift = p->regshift;
2735
2736 /*
2737 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2738 * for the multi-IRQ ports, which is where we are primarily
2739 * concerned with the shutdown path synchronization.
2740 *
2741 * For the muxed case there's nothing more to do.
2742 */
2743 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2744 port->irqflags = 0;
2745
2746 port->serial_in = sci_serial_in;
2747 port->serial_out = sci_serial_out;
2748
2749 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2750 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2751 p->dma_slave_tx, p->dma_slave_rx);
2752
2753 return 0;
2754}
2755
2756static void sci_cleanup_single(struct sci_port *port)
2757{
2758 pm_runtime_disable(port->port.dev);
2759}
2760
2761#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2762 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2763static void serial_console_putchar(struct uart_port *port, int ch)
2764{
2765 sci_poll_put_char(port, ch);
2766}
2767
2768/*
2769 * Print a string to the serial port trying not to disturb
2770 * any possible real use of the port...
2771 */
2772static void serial_console_write(struct console *co, const char *s,
2773 unsigned count)
2774{
2775 struct sci_port *sci_port = &sci_ports[co->index];
2776 struct uart_port *port = &sci_port->port;
2777 unsigned short bits, ctrl, ctrl_temp;
2778 unsigned long flags;
2779 int locked = 1;
2780
2781 local_irq_save(flags);
2782#if defined(SUPPORT_SYSRQ)
2783 if (port->sysrq)
2784 locked = 0;
2785 else
2786#endif
2787 if (oops_in_progress)
2788 locked = spin_trylock(&port->lock);
2789 else
2790 spin_lock(&port->lock);
2791
2792 /* first save SCSCR then disable interrupts, keep clock source */
2793 ctrl = serial_port_in(port, SCSCR);
2794 ctrl_temp = (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2795 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2796 serial_port_out(port, SCSCR, ctrl_temp);
2797
2798 uart_console_write(port, s, count, serial_console_putchar);
2799
2800 /* wait until fifo is empty and last bit has been transmitted */
2801 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2802 while ((serial_port_in(port, SCxSR) & bits) != bits)
2803 cpu_relax();
2804
2805 /* restore the SCSCR */
2806 serial_port_out(port, SCSCR, ctrl);
2807
2808 if (locked)
2809 spin_unlock(&port->lock);
2810 local_irq_restore(flags);
2811}
2812
2813static int serial_console_setup(struct console *co, char *options)
2814{
2815 struct sci_port *sci_port;
2816 struct uart_port *port;
2817 int baud = 115200;
2818 int bits = 8;
2819 int parity = 'n';
2820 int flow = 'n';
2821 int ret;
2822
2823 /*
2824 * Refuse to handle any bogus ports.
2825 */
2826 if (co->index < 0 || co->index >= SCI_NPORTS)
2827 return -ENODEV;
2828
2829 sci_port = &sci_ports[co->index];
2830 port = &sci_port->port;
2831
2832 /*
2833 * Refuse to handle uninitialized ports.
2834 */
2835 if (!port->ops)
2836 return -ENODEV;
2837
2838 ret = sci_remap_port(port);
2839 if (unlikely(ret != 0))
2840 return ret;
2841
2842 if (options)
2843 uart_parse_options(options, &baud, &parity, &bits, &flow);
2844
2845 return uart_set_options(port, co, baud, parity, bits, flow);
2846}
2847
2848static struct console serial_console = {
2849 .name = "ttySC",
2850 .device = uart_console_device,
2851 .write = serial_console_write,
2852 .setup = serial_console_setup,
2853 .flags = CON_PRINTBUFFER,
2854 .index = -1,
2855 .data = &sci_uart_driver,
2856};
2857
2858static struct console early_serial_console = {
2859 .name = "early_ttySC",
2860 .write = serial_console_write,
2861 .flags = CON_PRINTBUFFER,
2862 .index = -1,
2863};
2864
2865static char early_serial_buf[32];
2866
2867static int sci_probe_earlyprintk(struct platform_device *pdev)
2868{
2869 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2870
2871 if (early_serial_console.data)
2872 return -EEXIST;
2873
2874 early_serial_console.index = pdev->id;
2875
2876 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2877
2878 serial_console_setup(&early_serial_console, early_serial_buf);
2879
2880 if (!strstr(early_serial_buf, "keep"))
2881 early_serial_console.flags |= CON_BOOT;
2882
2883 register_console(&early_serial_console);
2884 return 0;
2885}
2886
2887#define SCI_CONSOLE (&serial_console)
2888
2889#else
2890static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2891{
2892 return -EINVAL;
2893}
2894
2895#define SCI_CONSOLE NULL
2896
2897#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
2898
2899static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2900
2901static struct uart_driver sci_uart_driver = {
2902 .owner = THIS_MODULE,
2903 .driver_name = "sci",
2904 .dev_name = "ttySC",
2905 .major = SCI_MAJOR,
2906 .minor = SCI_MINOR_START,
2907 .nr = SCI_NPORTS,
2908 .cons = SCI_CONSOLE,
2909};
2910
2911static int sci_remove(struct platform_device *dev)
2912{
2913 struct sci_port *port = platform_get_drvdata(dev);
2914
2915 uart_remove_one_port(&sci_uart_driver, &port->port);
2916
2917 sci_cleanup_single(port);
2918
2919 return 0;
2920}
2921
2922
2923#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
2924#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
2925#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
2926
2927static const struct of_device_id of_sci_match[] = {
2928 /* SoC-specific types */
2929 {
2930 .compatible = "renesas,scif-r7s72100",
2931 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
2932 },
2933 /* Family-specific types */
2934 {
2935 .compatible = "renesas,rcar-gen1-scif",
2936 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2937 }, {
2938 .compatible = "renesas,rcar-gen2-scif",
2939 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2940 }, {
2941 .compatible = "renesas,rcar-gen3-scif",
2942 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2943 },
2944 /* Generic types */
2945 {
2946 .compatible = "renesas,scif",
2947 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
2948 }, {
2949 .compatible = "renesas,scifa",
2950 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
2951 }, {
2952 .compatible = "renesas,scifb",
2953 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
2954 }, {
2955 .compatible = "renesas,hscif",
2956 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
2957 }, {
2958 .compatible = "renesas,sci",
2959 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
2960 }, {
2961 /* Terminator */
2962 },
2963};
2964MODULE_DEVICE_TABLE(of, of_sci_match);
2965
2966static struct plat_sci_port *
2967sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2968{
2969 struct device_node *np = pdev->dev.of_node;
2970 const struct of_device_id *match;
2971 struct plat_sci_port *p;
2972 int id;
2973
2974 if (!IS_ENABLED(CONFIG_OF) || !np)
2975 return NULL;
2976
2977 match = of_match_node(of_sci_match, np);
2978 if (!match)
2979 return NULL;
2980
2981 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2982 if (!p)
2983 return NULL;
2984
2985 /* Get the line number from the aliases node. */
2986 id = of_alias_get_id(np, "serial");
2987 if (id < 0) {
2988 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2989 return NULL;
2990 }
2991
2992 *dev_id = id;
2993
2994 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2995 p->type = SCI_OF_TYPE(match->data);
2996 p->regtype = SCI_OF_REGTYPE(match->data);
2997 p->scscr = SCSCR_RE | SCSCR_TE;
2998
2999 if (of_find_property(np, "uart-has-rtscts", NULL))
3000 p->capabilities |= SCIx_HAVE_RTSCTS;
3001
3002 return p;
3003}
3004
3005static int sci_probe_single(struct platform_device *dev,
3006 unsigned int index,
3007 struct plat_sci_port *p,
3008 struct sci_port *sciport)
3009{
3010 int ret;
3011
3012 /* Sanity check */
3013 if (unlikely(index >= SCI_NPORTS)) {
3014 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3015 index+1, SCI_NPORTS);
3016 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3017 return -EINVAL;
3018 }
3019
3020 ret = sci_init_single(dev, sciport, index, p, false);
3021 if (ret)
3022 return ret;
3023
3024 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3025 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3026 return PTR_ERR(sciport->gpios);
3027
3028 if (p->capabilities & SCIx_HAVE_RTSCTS) {
3029 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3030 UART_GPIO_CTS)) ||
3031 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3032 UART_GPIO_RTS))) {
3033 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3034 return -EINVAL;
3035 }
3036 sciport->port.flags |= UPF_HARD_FLOW;
3037 }
3038
3039 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3040 if (ret) {
3041 sci_cleanup_single(sciport);
3042 return ret;
3043 }
3044
3045 return 0;
3046}
3047
3048static int sci_probe(struct platform_device *dev)
3049{
3050 struct plat_sci_port *p;
3051 struct sci_port *sp;
3052 unsigned int dev_id;
3053 int ret;
3054
3055 /*
3056 * If we've come here via earlyprintk initialization, head off to
3057 * the special early probe. We don't have sufficient device state
3058 * to make it beyond this yet.
3059 */
3060 if (is_early_platform_device(dev))
3061 return sci_probe_earlyprintk(dev);
3062
3063 if (dev->dev.of_node) {
3064 p = sci_parse_dt(dev, &dev_id);
3065 if (p == NULL)
3066 return -EINVAL;
3067 } else {
3068 p = dev->dev.platform_data;
3069 if (p == NULL) {
3070 dev_err(&dev->dev, "no platform data supplied\n");
3071 return -EINVAL;
3072 }
3073
3074 dev_id = dev->id;
3075 }
3076
3077 sp = &sci_ports[dev_id];
3078 platform_set_drvdata(dev, sp);
3079
3080 ret = sci_probe_single(dev, dev_id, p, sp);
3081 if (ret)
3082 return ret;
3083
3084#ifdef CONFIG_SH_STANDARD_BIOS
3085 sh_bios_gdb_detach();
3086#endif
3087
3088 return 0;
3089}
3090
3091static __maybe_unused int sci_suspend(struct device *dev)
3092{
3093 struct sci_port *sport = dev_get_drvdata(dev);
3094
3095 if (sport)
3096 uart_suspend_port(&sci_uart_driver, &sport->port);
3097
3098 return 0;
3099}
3100
3101static __maybe_unused int sci_resume(struct device *dev)
3102{
3103 struct sci_port *sport = dev_get_drvdata(dev);
3104
3105 if (sport)
3106 uart_resume_port(&sci_uart_driver, &sport->port);
3107
3108 return 0;
3109}
3110
3111static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3112
3113static struct platform_driver sci_driver = {
3114 .probe = sci_probe,
3115 .remove = sci_remove,
3116 .driver = {
3117 .name = "sh-sci",
3118 .pm = &sci_dev_pm_ops,
3119 .of_match_table = of_match_ptr(of_sci_match),
3120 },
3121};
3122
3123static int __init sci_init(void)
3124{
3125 int ret;
3126
3127 pr_info("%s\n", banner);
3128
3129 ret = uart_register_driver(&sci_uart_driver);
3130 if (likely(ret == 0)) {
3131 ret = platform_driver_register(&sci_driver);
3132 if (unlikely(ret))
3133 uart_unregister_driver(&sci_uart_driver);
3134 }
3135
3136 return ret;
3137}
3138
3139static void __exit sci_exit(void)
3140{
3141 platform_driver_unregister(&sci_driver);
3142 uart_unregister_driver(&sci_uart_driver);
3143}
3144
3145#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3146early_platform_init_buffer("earlyprintk", &sci_driver,
3147 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3148#endif
3149#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3150static struct __init plat_sci_port port_cfg;
3151
3152static int __init early_console_setup(struct earlycon_device *device,
3153 int type)
3154{
3155 if (!device->port.membase)
3156 return -ENODEV;
3157
3158 device->port.serial_in = sci_serial_in;
3159 device->port.serial_out = sci_serial_out;
3160 device->port.type = type;
3161 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3162 sci_ports[0].cfg = &port_cfg;
3163 sci_ports[0].cfg->type = type;
3164 sci_probe_regmap(sci_ports[0].cfg);
3165 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR) |
3166 SCSCR_RE | SCSCR_TE;
3167 sci_serial_out(&sci_ports[0].port, SCSCR, port_cfg.scscr);
3168
3169 device->con->write = serial_console_write;
3170 return 0;
3171}
3172static int __init sci_early_console_setup(struct earlycon_device *device,
3173 const char *opt)
3174{
3175 return early_console_setup(device, PORT_SCI);
3176}
3177static int __init scif_early_console_setup(struct earlycon_device *device,
3178 const char *opt)
3179{
3180 return early_console_setup(device, PORT_SCIF);
3181}
3182static int __init scifa_early_console_setup(struct earlycon_device *device,
3183 const char *opt)
3184{
3185 return early_console_setup(device, PORT_SCIFA);
3186}
3187static int __init scifb_early_console_setup(struct earlycon_device *device,
3188 const char *opt)
3189{
3190 return early_console_setup(device, PORT_SCIFB);
3191}
3192static int __init hscif_early_console_setup(struct earlycon_device *device,
3193 const char *opt)
3194{
3195 return early_console_setup(device, PORT_HSCIF);
3196}
3197
3198OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3199OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3200OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3201OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3202OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3203#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3204
3205module_init(sci_init);
3206module_exit(sci_exit);
3207
3208MODULE_LICENSE("GPL");
3209MODULE_ALIAS("platform:sh-sci");
3210MODULE_AUTHOR("Paul Mundt");
3211MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");