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1/*
2 * drivers/pci/setup-res.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
13
14/*
15 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Resource sorting
17 */
18
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/pci.h>
22#include <linux/errno.h>
23#include <linux/ioport.h>
24#include <linux/cache.h>
25#include <linux/slab.h>
26#include "pci.h"
27
28
29void pci_update_resource(struct pci_dev *dev, int resno)
30{
31 struct pci_bus_region region;
32 u32 new, check, mask;
33 int reg;
34 enum pci_bar_type type;
35 struct resource *res = dev->resource + resno;
36
37 /*
38 * Ignore resources for unimplemented BARs and unused resource slots
39 * for 64 bit BARs.
40 */
41 if (!res->flags)
42 return;
43
44 /*
45 * Ignore non-moveable resources. This might be legacy resources for
46 * which no functional BAR register exists or another important
47 * system resource we shouldn't move around.
48 */
49 if (res->flags & IORESOURCE_PCI_FIXED)
50 return;
51
52 pcibios_resource_to_bus(dev, ®ion, res);
53
54 new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
55 if (res->flags & IORESOURCE_IO)
56 mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
57 else
58 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
59
60 reg = pci_resource_bar(dev, resno, &type);
61 if (!reg)
62 return;
63 if (type != pci_bar_unknown) {
64 if (!(res->flags & IORESOURCE_ROM_ENABLE))
65 return;
66 new |= PCI_ROM_ADDRESS_ENABLE;
67 }
68
69 pci_write_config_dword(dev, reg, new);
70 pci_read_config_dword(dev, reg, &check);
71
72 if ((new ^ check) & mask) {
73 dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
74 resno, new, check);
75 }
76
77 if (res->flags & IORESOURCE_MEM_64) {
78 new = region.start >> 16 >> 16;
79 pci_write_config_dword(dev, reg + 4, new);
80 pci_read_config_dword(dev, reg + 4, &check);
81 if (check != new) {
82 dev_err(&dev->dev, "BAR %d: error updating "
83 "(high %#08x != %#08x)\n", resno, new, check);
84 }
85 }
86 res->flags &= ~IORESOURCE_UNSET;
87 dev_info(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx])\n",
88 resno, res, (unsigned long long)region.start,
89 (unsigned long long)region.end);
90}
91
92int pci_claim_resource(struct pci_dev *dev, int resource)
93{
94 struct resource *res = &dev->resource[resource];
95 struct resource *root, *conflict;
96
97 root = pci_find_parent_resource(dev, res);
98 if (!root) {
99 dev_info(&dev->dev, "no compatible bridge window for %pR\n",
100 res);
101 return -EINVAL;
102 }
103
104 conflict = request_resource_conflict(root, res);
105 if (conflict) {
106 dev_info(&dev->dev,
107 "address space collision: %pR conflicts with %s %pR\n",
108 res, conflict->name, conflict);
109 return -EBUSY;
110 }
111
112 return 0;
113}
114EXPORT_SYMBOL(pci_claim_resource);
115
116#ifdef CONFIG_PCI_QUIRKS
117void pci_disable_bridge_window(struct pci_dev *dev)
118{
119 dev_info(&dev->dev, "disabling bridge mem windows\n");
120
121 /* MMIO Base/Limit */
122 pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
123
124 /* Prefetchable MMIO Base/Limit */
125 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
126 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
127 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
128}
129#endif /* CONFIG_PCI_QUIRKS */
130
131
132
133static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
134 int resno, resource_size_t size, resource_size_t align)
135{
136 struct resource *res = dev->resource + resno;
137 resource_size_t min;
138 int ret;
139
140 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
141
142 /* First, try exact prefetching match.. */
143 ret = pci_bus_alloc_resource(bus, res, size, align, min,
144 IORESOURCE_PREFETCH,
145 pcibios_align_resource, dev);
146
147 if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
148 /*
149 * That failed.
150 *
151 * But a prefetching area can handle a non-prefetching
152 * window (it will just not perform as well).
153 */
154 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
155 pcibios_align_resource, dev);
156 }
157 return ret;
158}
159
160static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
161 int resno, resource_size_t size)
162{
163 struct resource *root, *conflict;
164 resource_size_t start, end;
165 int ret = 0;
166
167 if (res->flags & IORESOURCE_IO)
168 root = &ioport_resource;
169 else
170 root = &iomem_resource;
171
172 start = res->start;
173 end = res->end;
174 res->start = dev->fw_addr[resno];
175 res->end = res->start + size - 1;
176 dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
177 resno, res);
178 conflict = request_resource_conflict(root, res);
179 if (conflict) {
180 dev_info(&dev->dev,
181 "BAR %d: %pR conflicts with %s %pR\n", resno,
182 res, conflict->name, conflict);
183 res->start = start;
184 res->end = end;
185 ret = 1;
186 }
187 return ret;
188}
189
190static int _pci_assign_resource(struct pci_dev *dev, int resno, int size, resource_size_t min_align)
191{
192 struct resource *res = dev->resource + resno;
193 struct pci_bus *bus;
194 int ret;
195 char *type;
196
197 bus = dev->bus;
198 while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
199 if (!bus->parent || !bus->self->transparent)
200 break;
201 bus = bus->parent;
202 }
203
204 if (ret) {
205 if (res->flags & IORESOURCE_MEM)
206 if (res->flags & IORESOURCE_PREFETCH)
207 type = "mem pref";
208 else
209 type = "mem";
210 else if (res->flags & IORESOURCE_IO)
211 type = "io";
212 else
213 type = "unknown";
214 dev_info(&dev->dev,
215 "BAR %d: can't assign %s (size %#llx)\n",
216 resno, type, (unsigned long long) resource_size(res));
217 }
218
219 return ret;
220}
221
222int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
223 resource_size_t min_align)
224{
225 struct resource *res = dev->resource + resno;
226 resource_size_t new_size;
227 int ret;
228
229 if (!res->parent) {
230 dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resouce %pR "
231 "\n", resno, res);
232 return -EINVAL;
233 }
234
235 new_size = resource_size(res) + addsize + min_align;
236 ret = _pci_assign_resource(dev, resno, new_size, min_align);
237 if (!ret) {
238 res->flags &= ~IORESOURCE_STARTALIGN;
239 dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
240 if (resno < PCI_BRIDGE_RESOURCES)
241 pci_update_resource(dev, resno);
242 }
243 return ret;
244}
245
246int pci_assign_resource(struct pci_dev *dev, int resno)
247{
248 struct resource *res = dev->resource + resno;
249 resource_size_t align, size;
250 struct pci_bus *bus;
251 int ret;
252
253 align = pci_resource_alignment(dev, res);
254 if (!align) {
255 dev_info(&dev->dev, "BAR %d: can't assign %pR "
256 "(bogus alignment)\n", resno, res);
257 return -EINVAL;
258 }
259
260 bus = dev->bus;
261 size = resource_size(res);
262 ret = _pci_assign_resource(dev, resno, size, align);
263
264 /*
265 * If we failed to assign anything, let's try the address
266 * where firmware left it. That at least has a chance of
267 * working, which is better than just leaving it disabled.
268 */
269 if (ret < 0 && dev->fw_addr[resno])
270 ret = pci_revert_fw_address(res, dev, resno, size);
271
272 if (!ret) {
273 res->flags &= ~IORESOURCE_STARTALIGN;
274 dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
275 if (resno < PCI_BRIDGE_RESOURCES)
276 pci_update_resource(dev, resno);
277 }
278 return ret;
279}
280
281
282/* Sort resources by alignment */
283void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)
284{
285 int i;
286
287 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
288 struct resource *r;
289 struct resource_list *list, *tmp;
290 resource_size_t r_align;
291
292 r = &dev->resource[i];
293
294 if (r->flags & IORESOURCE_PCI_FIXED)
295 continue;
296
297 if (!(r->flags) || r->parent)
298 continue;
299
300 r_align = pci_resource_alignment(dev, r);
301 if (!r_align) {
302 dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
303 i, r);
304 continue;
305 }
306 for (list = head; ; list = list->next) {
307 resource_size_t align = 0;
308 struct resource_list *ln = list->next;
309
310 if (ln)
311 align = pci_resource_alignment(ln->dev, ln->res);
312
313 if (r_align > align) {
314 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
315 if (!tmp)
316 panic("pdev_sort_resources(): "
317 "kmalloc() failed!\n");
318 tmp->next = ln;
319 tmp->res = r;
320 tmp->dev = dev;
321 list->next = tmp;
322 break;
323 }
324 }
325 }
326}
327
328int pci_enable_resources(struct pci_dev *dev, int mask)
329{
330 u16 cmd, old_cmd;
331 int i;
332 struct resource *r;
333
334 pci_read_config_word(dev, PCI_COMMAND, &cmd);
335 old_cmd = cmd;
336
337 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
338 if (!(mask & (1 << i)))
339 continue;
340
341 r = &dev->resource[i];
342
343 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
344 continue;
345 if ((i == PCI_ROM_RESOURCE) &&
346 (!(r->flags & IORESOURCE_ROM_ENABLE)))
347 continue;
348
349 if (!r->parent) {
350 dev_err(&dev->dev, "device not available "
351 "(can't reserve %pR)\n", r);
352 return -EINVAL;
353 }
354
355 if (r->flags & IORESOURCE_IO)
356 cmd |= PCI_COMMAND_IO;
357 if (r->flags & IORESOURCE_MEM)
358 cmd |= PCI_COMMAND_MEMORY;
359 }
360
361 if (cmd != old_cmd) {
362 dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
363 old_cmd, cmd);
364 pci_write_config_word(dev, PCI_COMMAND, cmd);
365 }
366 return 0;
367}
1/*
2 * drivers/pci/setup-res.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
13
14/*
15 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Resource sorting
17 */
18
19#include <linux/kernel.h>
20#include <linux/export.h>
21#include <linux/pci.h>
22#include <linux/errno.h>
23#include <linux/ioport.h>
24#include <linux/cache.h>
25#include <linux/slab.h>
26#include "pci.h"
27
28static void pci_std_update_resource(struct pci_dev *dev, int resno)
29{
30 struct pci_bus_region region;
31 bool disable;
32 u16 cmd;
33 u32 new, check, mask;
34 int reg;
35 struct resource *res = dev->resource + resno;
36
37 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
38 if (dev->is_virtfn)
39 return;
40
41 /*
42 * Ignore resources for unimplemented BARs and unused resource slots
43 * for 64 bit BARs.
44 */
45 if (!res->flags)
46 return;
47
48 if (res->flags & IORESOURCE_UNSET)
49 return;
50
51 /*
52 * Ignore non-moveable resources. This might be legacy resources for
53 * which no functional BAR register exists or another important
54 * system resource we shouldn't move around.
55 */
56 if (res->flags & IORESOURCE_PCI_FIXED)
57 return;
58
59 pcibios_resource_to_bus(dev->bus, ®ion, res);
60 new = region.start;
61
62 if (res->flags & IORESOURCE_IO) {
63 mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
64 new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK;
65 } else if (resno == PCI_ROM_RESOURCE) {
66 mask = (u32)PCI_ROM_ADDRESS_MASK;
67 } else {
68 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
69 new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
70 }
71
72 if (resno < PCI_ROM_RESOURCE) {
73 reg = PCI_BASE_ADDRESS_0 + 4 * resno;
74 } else if (resno == PCI_ROM_RESOURCE) {
75
76 /*
77 * Apparently some Matrox devices have ROM BARs that read
78 * as zero when disabled, so don't update ROM BARs unless
79 * they're enabled. See https://lkml.org/lkml/2005/8/30/138.
80 */
81 if (!(res->flags & IORESOURCE_ROM_ENABLE))
82 return;
83
84 reg = dev->rom_base_reg;
85 new |= PCI_ROM_ADDRESS_ENABLE;
86 } else
87 return;
88
89 /*
90 * We can't update a 64-bit BAR atomically, so when possible,
91 * disable decoding so that a half-updated BAR won't conflict
92 * with another device.
93 */
94 disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
95 if (disable) {
96 pci_read_config_word(dev, PCI_COMMAND, &cmd);
97 pci_write_config_word(dev, PCI_COMMAND,
98 cmd & ~PCI_COMMAND_MEMORY);
99 }
100
101 pci_write_config_dword(dev, reg, new);
102 pci_read_config_dword(dev, reg, &check);
103
104 if ((new ^ check) & mask) {
105 dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
106 resno, new, check);
107 }
108
109 if (res->flags & IORESOURCE_MEM_64) {
110 new = region.start >> 16 >> 16;
111 pci_write_config_dword(dev, reg + 4, new);
112 pci_read_config_dword(dev, reg + 4, &check);
113 if (check != new) {
114 dev_err(&dev->dev, "BAR %d: error updating (high %#08x != %#08x)\n",
115 resno, new, check);
116 }
117 }
118
119 if (disable)
120 pci_write_config_word(dev, PCI_COMMAND, cmd);
121}
122
123void pci_update_resource(struct pci_dev *dev, int resno)
124{
125 if (resno <= PCI_ROM_RESOURCE)
126 pci_std_update_resource(dev, resno);
127#ifdef CONFIG_PCI_IOV
128 else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
129 pci_iov_update_resource(dev, resno);
130#endif
131}
132
133int pci_claim_resource(struct pci_dev *dev, int resource)
134{
135 struct resource *res = &dev->resource[resource];
136 struct resource *root, *conflict;
137
138 if (res->flags & IORESOURCE_UNSET) {
139 dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n",
140 resource, res);
141 return -EINVAL;
142 }
143
144 /*
145 * If we have a shadow copy in RAM, the PCI device doesn't respond
146 * to the shadow range, so we don't need to claim it, and upstream
147 * bridges don't need to route the range to the device.
148 */
149 if (res->flags & IORESOURCE_ROM_SHADOW)
150 return 0;
151
152 root = pci_find_parent_resource(dev, res);
153 if (!root) {
154 dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",
155 resource, res);
156 res->flags |= IORESOURCE_UNSET;
157 return -EINVAL;
158 }
159
160 conflict = request_resource_conflict(root, res);
161 if (conflict) {
162 dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
163 resource, res, conflict->name, conflict);
164 res->flags |= IORESOURCE_UNSET;
165 return -EBUSY;
166 }
167
168 return 0;
169}
170EXPORT_SYMBOL(pci_claim_resource);
171
172void pci_disable_bridge_window(struct pci_dev *dev)
173{
174 dev_info(&dev->dev, "disabling bridge mem windows\n");
175
176 /* MMIO Base/Limit */
177 pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
178
179 /* Prefetchable MMIO Base/Limit */
180 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
181 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
182 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
183}
184
185/*
186 * Generic function that returns a value indicating that the device's
187 * original BIOS BAR address was not saved and so is not available for
188 * reinstatement.
189 *
190 * Can be over-ridden by architecture specific code that implements
191 * reinstatement functionality rather than leaving it disabled when
192 * normal allocation attempts fail.
193 */
194resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
195{
196 return 0;
197}
198
199static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
200 int resno, resource_size_t size)
201{
202 struct resource *root, *conflict;
203 resource_size_t fw_addr, start, end;
204
205 fw_addr = pcibios_retrieve_fw_addr(dev, resno);
206 if (!fw_addr)
207 return -ENOMEM;
208
209 start = res->start;
210 end = res->end;
211 res->start = fw_addr;
212 res->end = res->start + size - 1;
213 res->flags &= ~IORESOURCE_UNSET;
214
215 root = pci_find_parent_resource(dev, res);
216 if (!root) {
217 if (res->flags & IORESOURCE_IO)
218 root = &ioport_resource;
219 else
220 root = &iomem_resource;
221 }
222
223 dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
224 resno, res);
225 conflict = request_resource_conflict(root, res);
226 if (conflict) {
227 dev_info(&dev->dev, "BAR %d: %pR conflicts with %s %pR\n",
228 resno, res, conflict->name, conflict);
229 res->start = start;
230 res->end = end;
231 res->flags |= IORESOURCE_UNSET;
232 return -EBUSY;
233 }
234 return 0;
235}
236
237static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
238 int resno, resource_size_t size, resource_size_t align)
239{
240 struct resource *res = dev->resource + resno;
241 resource_size_t min;
242 int ret;
243
244 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
245
246 /*
247 * First, try exact prefetching match. Even if a 64-bit
248 * prefetchable bridge window is below 4GB, we can't put a 32-bit
249 * prefetchable resource in it because pbus_size_mem() assumes a
250 * 64-bit window will contain no 32-bit resources. If we assign
251 * things differently than they were sized, not everything will fit.
252 */
253 ret = pci_bus_alloc_resource(bus, res, size, align, min,
254 IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
255 pcibios_align_resource, dev);
256 if (ret == 0)
257 return 0;
258
259 /*
260 * If the prefetchable window is only 32 bits wide, we can put
261 * 64-bit prefetchable resources in it.
262 */
263 if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
264 (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
265 ret = pci_bus_alloc_resource(bus, res, size, align, min,
266 IORESOURCE_PREFETCH,
267 pcibios_align_resource, dev);
268 if (ret == 0)
269 return 0;
270 }
271
272 /*
273 * If we didn't find a better match, we can put any memory resource
274 * in a non-prefetchable window. If this resource is 32 bits and
275 * non-prefetchable, the first call already tried the only possibility
276 * so we don't need to try again.
277 */
278 if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
279 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
280 pcibios_align_resource, dev);
281
282 return ret;
283}
284
285static int _pci_assign_resource(struct pci_dev *dev, int resno,
286 resource_size_t size, resource_size_t min_align)
287{
288 struct pci_bus *bus;
289 int ret;
290
291 bus = dev->bus;
292 while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
293 if (!bus->parent || !bus->self->transparent)
294 break;
295 bus = bus->parent;
296 }
297
298 return ret;
299}
300
301int pci_assign_resource(struct pci_dev *dev, int resno)
302{
303 struct resource *res = dev->resource + resno;
304 resource_size_t align, size;
305 int ret;
306
307 if (res->flags & IORESOURCE_PCI_FIXED)
308 return 0;
309
310 res->flags |= IORESOURCE_UNSET;
311 align = pci_resource_alignment(dev, res);
312 if (!align) {
313 dev_info(&dev->dev, "BAR %d: can't assign %pR (bogus alignment)\n",
314 resno, res);
315 return -EINVAL;
316 }
317
318 size = resource_size(res);
319 ret = _pci_assign_resource(dev, resno, size, align);
320
321 /*
322 * If we failed to assign anything, let's try the address
323 * where firmware left it. That at least has a chance of
324 * working, which is better than just leaving it disabled.
325 */
326 if (ret < 0) {
327 dev_info(&dev->dev, "BAR %d: no space for %pR\n", resno, res);
328 ret = pci_revert_fw_address(res, dev, resno, size);
329 }
330
331 if (ret < 0) {
332 dev_info(&dev->dev, "BAR %d: failed to assign %pR\n", resno,
333 res);
334 return ret;
335 }
336
337 res->flags &= ~IORESOURCE_UNSET;
338 res->flags &= ~IORESOURCE_STARTALIGN;
339 dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
340 if (resno < PCI_BRIDGE_RESOURCES)
341 pci_update_resource(dev, resno);
342
343 return 0;
344}
345EXPORT_SYMBOL(pci_assign_resource);
346
347int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
348 resource_size_t min_align)
349{
350 struct resource *res = dev->resource + resno;
351 unsigned long flags;
352 resource_size_t new_size;
353 int ret;
354
355 if (res->flags & IORESOURCE_PCI_FIXED)
356 return 0;
357
358 flags = res->flags;
359 res->flags |= IORESOURCE_UNSET;
360 if (!res->parent) {
361 dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR\n",
362 resno, res);
363 return -EINVAL;
364 }
365
366 /* already aligned with min_align */
367 new_size = resource_size(res) + addsize;
368 ret = _pci_assign_resource(dev, resno, new_size, min_align);
369 if (ret) {
370 res->flags = flags;
371 dev_info(&dev->dev, "BAR %d: %pR (failed to expand by %#llx)\n",
372 resno, res, (unsigned long long) addsize);
373 return ret;
374 }
375
376 res->flags &= ~IORESOURCE_UNSET;
377 res->flags &= ~IORESOURCE_STARTALIGN;
378 dev_info(&dev->dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
379 resno, res, (unsigned long long) addsize);
380 if (resno < PCI_BRIDGE_RESOURCES)
381 pci_update_resource(dev, resno);
382
383 return 0;
384}
385
386int pci_enable_resources(struct pci_dev *dev, int mask)
387{
388 u16 cmd, old_cmd;
389 int i;
390 struct resource *r;
391
392 pci_read_config_word(dev, PCI_COMMAND, &cmd);
393 old_cmd = cmd;
394
395 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
396 if (!(mask & (1 << i)))
397 continue;
398
399 r = &dev->resource[i];
400
401 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
402 continue;
403 if ((i == PCI_ROM_RESOURCE) &&
404 (!(r->flags & IORESOURCE_ROM_ENABLE)))
405 continue;
406
407 if (r->flags & IORESOURCE_UNSET) {
408 dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n",
409 i, r);
410 return -EINVAL;
411 }
412
413 if (!r->parent) {
414 dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n",
415 i, r);
416 return -EINVAL;
417 }
418
419 if (r->flags & IORESOURCE_IO)
420 cmd |= PCI_COMMAND_IO;
421 if (r->flags & IORESOURCE_MEM)
422 cmd |= PCI_COMMAND_MEMORY;
423 }
424
425 if (cmd != old_cmd) {
426 dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
427 old_cmd, cmd);
428 pci_write_config_word(dev, PCI_COMMAND, cmd);
429 }
430 return 0;
431}