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1/*
2 * drivers/pci/setup-res.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
13
14/*
15 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Resource sorting
17 */
18
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/pci.h>
22#include <linux/errno.h>
23#include <linux/ioport.h>
24#include <linux/cache.h>
25#include <linux/slab.h>
26#include "pci.h"
27
28
29void pci_update_resource(struct pci_dev *dev, int resno)
30{
31 struct pci_bus_region region;
32 u32 new, check, mask;
33 int reg;
34 enum pci_bar_type type;
35 struct resource *res = dev->resource + resno;
36
37 /*
38 * Ignore resources for unimplemented BARs and unused resource slots
39 * for 64 bit BARs.
40 */
41 if (!res->flags)
42 return;
43
44 /*
45 * Ignore non-moveable resources. This might be legacy resources for
46 * which no functional BAR register exists or another important
47 * system resource we shouldn't move around.
48 */
49 if (res->flags & IORESOURCE_PCI_FIXED)
50 return;
51
52 pcibios_resource_to_bus(dev, ®ion, res);
53
54 new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
55 if (res->flags & IORESOURCE_IO)
56 mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
57 else
58 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
59
60 reg = pci_resource_bar(dev, resno, &type);
61 if (!reg)
62 return;
63 if (type != pci_bar_unknown) {
64 if (!(res->flags & IORESOURCE_ROM_ENABLE))
65 return;
66 new |= PCI_ROM_ADDRESS_ENABLE;
67 }
68
69 pci_write_config_dword(dev, reg, new);
70 pci_read_config_dword(dev, reg, &check);
71
72 if ((new ^ check) & mask) {
73 dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
74 resno, new, check);
75 }
76
77 if (res->flags & IORESOURCE_MEM_64) {
78 new = region.start >> 16 >> 16;
79 pci_write_config_dword(dev, reg + 4, new);
80 pci_read_config_dword(dev, reg + 4, &check);
81 if (check != new) {
82 dev_err(&dev->dev, "BAR %d: error updating "
83 "(high %#08x != %#08x)\n", resno, new, check);
84 }
85 }
86 res->flags &= ~IORESOURCE_UNSET;
87 dev_info(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx])\n",
88 resno, res, (unsigned long long)region.start,
89 (unsigned long long)region.end);
90}
91
92int pci_claim_resource(struct pci_dev *dev, int resource)
93{
94 struct resource *res = &dev->resource[resource];
95 struct resource *root, *conflict;
96
97 root = pci_find_parent_resource(dev, res);
98 if (!root) {
99 dev_info(&dev->dev, "no compatible bridge window for %pR\n",
100 res);
101 return -EINVAL;
102 }
103
104 conflict = request_resource_conflict(root, res);
105 if (conflict) {
106 dev_info(&dev->dev,
107 "address space collision: %pR conflicts with %s %pR\n",
108 res, conflict->name, conflict);
109 return -EBUSY;
110 }
111
112 return 0;
113}
114EXPORT_SYMBOL(pci_claim_resource);
115
116#ifdef CONFIG_PCI_QUIRKS
117void pci_disable_bridge_window(struct pci_dev *dev)
118{
119 dev_info(&dev->dev, "disabling bridge mem windows\n");
120
121 /* MMIO Base/Limit */
122 pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
123
124 /* Prefetchable MMIO Base/Limit */
125 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
126 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
127 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
128}
129#endif /* CONFIG_PCI_QUIRKS */
130
131
132
133static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
134 int resno, resource_size_t size, resource_size_t align)
135{
136 struct resource *res = dev->resource + resno;
137 resource_size_t min;
138 int ret;
139
140 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
141
142 /* First, try exact prefetching match.. */
143 ret = pci_bus_alloc_resource(bus, res, size, align, min,
144 IORESOURCE_PREFETCH,
145 pcibios_align_resource, dev);
146
147 if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
148 /*
149 * That failed.
150 *
151 * But a prefetching area can handle a non-prefetching
152 * window (it will just not perform as well).
153 */
154 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
155 pcibios_align_resource, dev);
156 }
157 return ret;
158}
159
160static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
161 int resno, resource_size_t size)
162{
163 struct resource *root, *conflict;
164 resource_size_t start, end;
165 int ret = 0;
166
167 if (res->flags & IORESOURCE_IO)
168 root = &ioport_resource;
169 else
170 root = &iomem_resource;
171
172 start = res->start;
173 end = res->end;
174 res->start = dev->fw_addr[resno];
175 res->end = res->start + size - 1;
176 dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
177 resno, res);
178 conflict = request_resource_conflict(root, res);
179 if (conflict) {
180 dev_info(&dev->dev,
181 "BAR %d: %pR conflicts with %s %pR\n", resno,
182 res, conflict->name, conflict);
183 res->start = start;
184 res->end = end;
185 ret = 1;
186 }
187 return ret;
188}
189
190static int _pci_assign_resource(struct pci_dev *dev, int resno, int size, resource_size_t min_align)
191{
192 struct resource *res = dev->resource + resno;
193 struct pci_bus *bus;
194 int ret;
195 char *type;
196
197 bus = dev->bus;
198 while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
199 if (!bus->parent || !bus->self->transparent)
200 break;
201 bus = bus->parent;
202 }
203
204 if (ret) {
205 if (res->flags & IORESOURCE_MEM)
206 if (res->flags & IORESOURCE_PREFETCH)
207 type = "mem pref";
208 else
209 type = "mem";
210 else if (res->flags & IORESOURCE_IO)
211 type = "io";
212 else
213 type = "unknown";
214 dev_info(&dev->dev,
215 "BAR %d: can't assign %s (size %#llx)\n",
216 resno, type, (unsigned long long) resource_size(res));
217 }
218
219 return ret;
220}
221
222int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
223 resource_size_t min_align)
224{
225 struct resource *res = dev->resource + resno;
226 resource_size_t new_size;
227 int ret;
228
229 if (!res->parent) {
230 dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resouce %pR "
231 "\n", resno, res);
232 return -EINVAL;
233 }
234
235 new_size = resource_size(res) + addsize + min_align;
236 ret = _pci_assign_resource(dev, resno, new_size, min_align);
237 if (!ret) {
238 res->flags &= ~IORESOURCE_STARTALIGN;
239 dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
240 if (resno < PCI_BRIDGE_RESOURCES)
241 pci_update_resource(dev, resno);
242 }
243 return ret;
244}
245
246int pci_assign_resource(struct pci_dev *dev, int resno)
247{
248 struct resource *res = dev->resource + resno;
249 resource_size_t align, size;
250 struct pci_bus *bus;
251 int ret;
252
253 align = pci_resource_alignment(dev, res);
254 if (!align) {
255 dev_info(&dev->dev, "BAR %d: can't assign %pR "
256 "(bogus alignment)\n", resno, res);
257 return -EINVAL;
258 }
259
260 bus = dev->bus;
261 size = resource_size(res);
262 ret = _pci_assign_resource(dev, resno, size, align);
263
264 /*
265 * If we failed to assign anything, let's try the address
266 * where firmware left it. That at least has a chance of
267 * working, which is better than just leaving it disabled.
268 */
269 if (ret < 0 && dev->fw_addr[resno])
270 ret = pci_revert_fw_address(res, dev, resno, size);
271
272 if (!ret) {
273 res->flags &= ~IORESOURCE_STARTALIGN;
274 dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
275 if (resno < PCI_BRIDGE_RESOURCES)
276 pci_update_resource(dev, resno);
277 }
278 return ret;
279}
280
281
282/* Sort resources by alignment */
283void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)
284{
285 int i;
286
287 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
288 struct resource *r;
289 struct resource_list *list, *tmp;
290 resource_size_t r_align;
291
292 r = &dev->resource[i];
293
294 if (r->flags & IORESOURCE_PCI_FIXED)
295 continue;
296
297 if (!(r->flags) || r->parent)
298 continue;
299
300 r_align = pci_resource_alignment(dev, r);
301 if (!r_align) {
302 dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
303 i, r);
304 continue;
305 }
306 for (list = head; ; list = list->next) {
307 resource_size_t align = 0;
308 struct resource_list *ln = list->next;
309
310 if (ln)
311 align = pci_resource_alignment(ln->dev, ln->res);
312
313 if (r_align > align) {
314 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
315 if (!tmp)
316 panic("pdev_sort_resources(): "
317 "kmalloc() failed!\n");
318 tmp->next = ln;
319 tmp->res = r;
320 tmp->dev = dev;
321 list->next = tmp;
322 break;
323 }
324 }
325 }
326}
327
328int pci_enable_resources(struct pci_dev *dev, int mask)
329{
330 u16 cmd, old_cmd;
331 int i;
332 struct resource *r;
333
334 pci_read_config_word(dev, PCI_COMMAND, &cmd);
335 old_cmd = cmd;
336
337 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
338 if (!(mask & (1 << i)))
339 continue;
340
341 r = &dev->resource[i];
342
343 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
344 continue;
345 if ((i == PCI_ROM_RESOURCE) &&
346 (!(r->flags & IORESOURCE_ROM_ENABLE)))
347 continue;
348
349 if (!r->parent) {
350 dev_err(&dev->dev, "device not available "
351 "(can't reserve %pR)\n", r);
352 return -EINVAL;
353 }
354
355 if (r->flags & IORESOURCE_IO)
356 cmd |= PCI_COMMAND_IO;
357 if (r->flags & IORESOURCE_MEM)
358 cmd |= PCI_COMMAND_MEMORY;
359 }
360
361 if (cmd != old_cmd) {
362 dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
363 old_cmd, cmd);
364 pci_write_config_word(dev, PCI_COMMAND, cmd);
365 }
366 return 0;
367}
1/*
2 * drivers/pci/setup-res.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
13
14/*
15 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Resource sorting
17 */
18
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/export.h>
22#include <linux/pci.h>
23#include <linux/errno.h>
24#include <linux/ioport.h>
25#include <linux/cache.h>
26#include <linux/slab.h>
27#include "pci.h"
28
29
30void pci_update_resource(struct pci_dev *dev, int resno)
31{
32 struct pci_bus_region region;
33 bool disable;
34 u16 cmd;
35 u32 new, check, mask;
36 int reg;
37 enum pci_bar_type type;
38 struct resource *res = dev->resource + resno;
39
40 /*
41 * Ignore resources for unimplemented BARs and unused resource slots
42 * for 64 bit BARs.
43 */
44 if (!res->flags)
45 return;
46
47 if (res->flags & IORESOURCE_UNSET)
48 return;
49
50 /*
51 * Ignore non-moveable resources. This might be legacy resources for
52 * which no functional BAR register exists or another important
53 * system resource we shouldn't move around.
54 */
55 if (res->flags & IORESOURCE_PCI_FIXED)
56 return;
57
58 pcibios_resource_to_bus(dev->bus, ®ion, res);
59
60 new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
61 if (res->flags & IORESOURCE_IO)
62 mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
63 else
64 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
65
66 reg = pci_resource_bar(dev, resno, &type);
67 if (!reg)
68 return;
69 if (type != pci_bar_unknown) {
70 if (!(res->flags & IORESOURCE_ROM_ENABLE))
71 return;
72 new |= PCI_ROM_ADDRESS_ENABLE;
73 }
74
75 /*
76 * We can't update a 64-bit BAR atomically, so when possible,
77 * disable decoding so that a half-updated BAR won't conflict
78 * with another device.
79 */
80 disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
81 if (disable) {
82 pci_read_config_word(dev, PCI_COMMAND, &cmd);
83 pci_write_config_word(dev, PCI_COMMAND,
84 cmd & ~PCI_COMMAND_MEMORY);
85 }
86
87 pci_write_config_dword(dev, reg, new);
88 pci_read_config_dword(dev, reg, &check);
89
90 if ((new ^ check) & mask) {
91 dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
92 resno, new, check);
93 }
94
95 if (res->flags & IORESOURCE_MEM_64) {
96 new = region.start >> 16 >> 16;
97 pci_write_config_dword(dev, reg + 4, new);
98 pci_read_config_dword(dev, reg + 4, &check);
99 if (check != new) {
100 dev_err(&dev->dev, "BAR %d: error updating "
101 "(high %#08x != %#08x)\n", resno, new, check);
102 }
103 }
104
105 if (disable)
106 pci_write_config_word(dev, PCI_COMMAND, cmd);
107}
108
109int pci_claim_resource(struct pci_dev *dev, int resource)
110{
111 struct resource *res = &dev->resource[resource];
112 struct resource *root, *conflict;
113
114 if (res->flags & IORESOURCE_UNSET) {
115 dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n",
116 resource, res);
117 return -EINVAL;
118 }
119
120 root = pci_find_parent_resource(dev, res);
121 if (!root) {
122 dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",
123 resource, res);
124 return -EINVAL;
125 }
126
127 conflict = request_resource_conflict(root, res);
128 if (conflict) {
129 dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
130 resource, res, conflict->name, conflict);
131 return -EBUSY;
132 }
133
134 return 0;
135}
136EXPORT_SYMBOL(pci_claim_resource);
137
138void pci_disable_bridge_window(struct pci_dev *dev)
139{
140 dev_info(&dev->dev, "disabling bridge mem windows\n");
141
142 /* MMIO Base/Limit */
143 pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
144
145 /* Prefetchable MMIO Base/Limit */
146 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
147 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
148 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
149}
150
151/*
152 * Generic function that returns a value indicating that the device's
153 * original BIOS BAR address was not saved and so is not available for
154 * reinstatement.
155 *
156 * Can be over-ridden by architecture specific code that implements
157 * reinstatement functionality rather than leaving it disabled when
158 * normal allocation attempts fail.
159 */
160resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
161{
162 return 0;
163}
164
165static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
166 int resno, resource_size_t size)
167{
168 struct resource *root, *conflict;
169 resource_size_t fw_addr, start, end;
170 int ret = 0;
171
172 fw_addr = pcibios_retrieve_fw_addr(dev, resno);
173 if (!fw_addr)
174 return 1;
175
176 start = res->start;
177 end = res->end;
178 res->start = fw_addr;
179 res->end = res->start + size - 1;
180
181 root = pci_find_parent_resource(dev, res);
182 if (!root) {
183 if (res->flags & IORESOURCE_IO)
184 root = &ioport_resource;
185 else
186 root = &iomem_resource;
187 }
188
189 dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
190 resno, res);
191 conflict = request_resource_conflict(root, res);
192 if (conflict) {
193 dev_info(&dev->dev,
194 "BAR %d: %pR conflicts with %s %pR\n", resno,
195 res, conflict->name, conflict);
196 res->start = start;
197 res->end = end;
198 ret = 1;
199 }
200 return ret;
201}
202
203static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
204 int resno, resource_size_t size, resource_size_t align)
205{
206 struct resource *res = dev->resource + resno;
207 resource_size_t min;
208 int ret;
209
210 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
211
212 /* First, try exact prefetching match.. */
213 ret = pci_bus_alloc_resource(bus, res, size, align, min,
214 IORESOURCE_PREFETCH,
215 pcibios_align_resource, dev);
216
217 if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
218 /*
219 * That failed.
220 *
221 * But a prefetching area can handle a non-prefetching
222 * window (it will just not perform as well).
223 */
224 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
225 pcibios_align_resource, dev);
226 }
227 return ret;
228}
229
230static int _pci_assign_resource(struct pci_dev *dev, int resno,
231 resource_size_t size, resource_size_t min_align)
232{
233 struct resource *res = dev->resource + resno;
234 struct pci_bus *bus;
235 int ret;
236 char *type;
237
238 bus = dev->bus;
239 while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
240 if (!bus->parent || !bus->self->transparent)
241 break;
242 bus = bus->parent;
243 }
244
245 if (ret) {
246 if (res->flags & IORESOURCE_MEM)
247 if (res->flags & IORESOURCE_PREFETCH)
248 type = "mem pref";
249 else
250 type = "mem";
251 else if (res->flags & IORESOURCE_IO)
252 type = "io";
253 else
254 type = "unknown";
255 dev_info(&dev->dev,
256 "BAR %d: can't assign %s (size %#llx)\n",
257 resno, type, (unsigned long long) resource_size(res));
258 }
259
260 return ret;
261}
262
263int pci_assign_resource(struct pci_dev *dev, int resno)
264{
265 struct resource *res = dev->resource + resno;
266 resource_size_t align, size;
267 int ret;
268
269 res->flags |= IORESOURCE_UNSET;
270 align = pci_resource_alignment(dev, res);
271 if (!align) {
272 dev_info(&dev->dev, "BAR %d: can't assign %pR "
273 "(bogus alignment)\n", resno, res);
274 return -EINVAL;
275 }
276
277 size = resource_size(res);
278 ret = _pci_assign_resource(dev, resno, size, align);
279
280 /*
281 * If we failed to assign anything, let's try the address
282 * where firmware left it. That at least has a chance of
283 * working, which is better than just leaving it disabled.
284 */
285 if (ret < 0)
286 ret = pci_revert_fw_address(res, dev, resno, size);
287
288 if (!ret) {
289 res->flags &= ~IORESOURCE_UNSET;
290 res->flags &= ~IORESOURCE_STARTALIGN;
291 dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
292 if (resno < PCI_BRIDGE_RESOURCES)
293 pci_update_resource(dev, resno);
294 }
295 return ret;
296}
297
298int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
299 resource_size_t min_align)
300{
301 struct resource *res = dev->resource + resno;
302 resource_size_t new_size;
303 int ret;
304
305 res->flags |= IORESOURCE_UNSET;
306 if (!res->parent) {
307 dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR "
308 "\n", resno, res);
309 return -EINVAL;
310 }
311
312 /* already aligned with min_align */
313 new_size = resource_size(res) + addsize;
314 ret = _pci_assign_resource(dev, resno, new_size, min_align);
315 if (!ret) {
316 res->flags &= ~IORESOURCE_UNSET;
317 res->flags &= ~IORESOURCE_STARTALIGN;
318 dev_info(&dev->dev, "BAR %d: reassigned %pR\n", resno, res);
319 if (resno < PCI_BRIDGE_RESOURCES)
320 pci_update_resource(dev, resno);
321 }
322 return ret;
323}
324
325int pci_enable_resources(struct pci_dev *dev, int mask)
326{
327 u16 cmd, old_cmd;
328 int i;
329 struct resource *r;
330
331 pci_read_config_word(dev, PCI_COMMAND, &cmd);
332 old_cmd = cmd;
333
334 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
335 if (!(mask & (1 << i)))
336 continue;
337
338 r = &dev->resource[i];
339
340 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
341 continue;
342 if ((i == PCI_ROM_RESOURCE) &&
343 (!(r->flags & IORESOURCE_ROM_ENABLE)))
344 continue;
345
346 if (r->flags & IORESOURCE_UNSET) {
347 dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n",
348 i, r);
349 return -EINVAL;
350 }
351
352 if (!r->parent) {
353 dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n",
354 i, r);
355 return -EINVAL;
356 }
357
358 if (r->flags & IORESOURCE_IO)
359 cmd |= PCI_COMMAND_IO;
360 if (r->flags & IORESOURCE_MEM)
361 cmd |= PCI_COMMAND_MEMORY;
362 }
363
364 if (cmd != old_cmd) {
365 dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
366 old_cmd, cmd);
367 pci_write_config_word(dev, PCI_COMMAND, cmd);
368 }
369 return 0;
370}