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1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18#include "hw-ops.h"
19#include "../regd.h"
20#include "ar9002_phy.h"
21
22/* All code below is for AR5008, AR9001, AR9002 */
23
24static const int firstep_table[] =
25/* level: 0 1 2 3 4 5 6 7 8 */
26 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
27
28static const int cycpwrThr1_table[] =
29/* level: 0 1 2 3 4 5 6 7 8 */
30 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
31
32/*
33 * register values to turn OFDM weak signal detection OFF
34 */
35static const int m1ThreshLow_off = 127;
36static const int m2ThreshLow_off = 127;
37static const int m1Thresh_off = 127;
38static const int m2Thresh_off = 127;
39static const int m2CountThr_off = 31;
40static const int m2CountThrLow_off = 63;
41static const int m1ThreshLowExt_off = 127;
42static const int m2ThreshLowExt_off = 127;
43static const int m1ThreshExt_off = 127;
44static const int m2ThreshExt_off = 127;
45
46
47static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array,
48 int col)
49{
50 int i;
51
52 for (i = 0; i < array->ia_rows; i++)
53 bank[i] = INI_RA(array, i, col);
54}
55
56
57#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \
58 ar5008_write_rf_array(ah, iniarray, regData, &(regWr))
59
60static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array,
61 u32 *data, unsigned int *writecnt)
62{
63 int r;
64
65 ENABLE_REGWRITE_BUFFER(ah);
66
67 for (r = 0; r < array->ia_rows; r++) {
68 REG_WRITE(ah, INI_RA(array, r, 0), data[r]);
69 DO_DELAY(*writecnt);
70 }
71
72 REGWRITE_BUFFER_FLUSH(ah);
73}
74
75/**
76 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
77 * @rfbuf:
78 * @reg32:
79 * @numBits:
80 * @firstBit:
81 * @column:
82 *
83 * Performs analog "swizzling" of parameters into their location.
84 * Used on external AR2133/AR5133 radios.
85 */
86static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
87 u32 numBits, u32 firstBit,
88 u32 column)
89{
90 u32 tmp32, mask, arrayEntry, lastBit;
91 int32_t bitPosition, bitsLeft;
92
93 tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
94 arrayEntry = (firstBit - 1) / 8;
95 bitPosition = (firstBit - 1) % 8;
96 bitsLeft = numBits;
97 while (bitsLeft > 0) {
98 lastBit = (bitPosition + bitsLeft > 8) ?
99 8 : bitPosition + bitsLeft;
100 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
101 (column * 8);
102 rfBuf[arrayEntry] &= ~mask;
103 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
104 (column * 8)) & mask;
105 bitsLeft -= 8 - bitPosition;
106 tmp32 = tmp32 >> (8 - bitPosition);
107 bitPosition = 0;
108 arrayEntry++;
109 }
110}
111
112/*
113 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
114 * rf_pwd_icsyndiv.
115 *
116 * Theoretical Rules:
117 * if 2 GHz band
118 * if forceBiasAuto
119 * if synth_freq < 2412
120 * bias = 0
121 * else if 2412 <= synth_freq <= 2422
122 * bias = 1
123 * else // synth_freq > 2422
124 * bias = 2
125 * else if forceBias > 0
126 * bias = forceBias & 7
127 * else
128 * no change, use value from ini file
129 * else
130 * no change, invalid band
131 *
132 * 1st Mod:
133 * 2422 also uses value of 2
134 * <approved>
135 *
136 * 2nd Mod:
137 * Less than 2412 uses value of 0, 2412 and above uses value of 2
138 */
139static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
140{
141 struct ath_common *common = ath9k_hw_common(ah);
142 u32 tmp_reg;
143 int reg_writes = 0;
144 u32 new_bias = 0;
145
146 if (!AR_SREV_5416(ah) || synth_freq >= 3000)
147 return;
148
149 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
150
151 if (synth_freq < 2412)
152 new_bias = 0;
153 else if (synth_freq < 2422)
154 new_bias = 1;
155 else
156 new_bias = 2;
157
158 /* pre-reverse this field */
159 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
160
161 ath_dbg(common, ATH_DBG_CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n",
162 new_bias, synth_freq);
163
164 /* swizzle rf_pwd_icsyndiv */
165 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
166
167 /* write Bank 6 with new params */
168 REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
169}
170
171/**
172 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
173 * @ah: atheros hardware structure
174 * @chan:
175 *
176 * For the external AR2133/AR5133 radios, takes the MHz channel value and set
177 * the channel value. Assumes writes enabled to analog bus and bank6 register
178 * cache in ah->analogBank6Data.
179 */
180static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
181{
182 struct ath_common *common = ath9k_hw_common(ah);
183 u32 channelSel = 0;
184 u32 bModeSynth = 0;
185 u32 aModeRefSel = 0;
186 u32 reg32 = 0;
187 u16 freq;
188 struct chan_centers centers;
189
190 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
191 freq = centers.synth_center;
192
193 if (freq < 4800) {
194 u32 txctl;
195
196 if (((freq - 2192) % 5) == 0) {
197 channelSel = ((freq - 672) * 2 - 3040) / 10;
198 bModeSynth = 0;
199 } else if (((freq - 2224) % 5) == 0) {
200 channelSel = ((freq - 704) * 2 - 3040) / 10;
201 bModeSynth = 1;
202 } else {
203 ath_err(common, "Invalid channel %u MHz\n", freq);
204 return -EINVAL;
205 }
206
207 channelSel = (channelSel << 2) & 0xff;
208 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
209
210 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
211 if (freq == 2484) {
212
213 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
214 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
215 } else {
216 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
217 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
218 }
219
220 } else if ((freq % 20) == 0 && freq >= 5120) {
221 channelSel =
222 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
223 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
224 } else if ((freq % 10) == 0) {
225 channelSel =
226 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
227 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
228 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
229 else
230 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
231 } else if ((freq % 5) == 0) {
232 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
233 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
234 } else {
235 ath_err(common, "Invalid channel %u MHz\n", freq);
236 return -EINVAL;
237 }
238
239 ar5008_hw_force_bias(ah, freq);
240
241 reg32 =
242 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
243 (1 << 5) | 0x1;
244
245 REG_WRITE(ah, AR_PHY(0x37), reg32);
246
247 ah->curchan = chan;
248 ah->curchan_rad_index = -1;
249
250 return 0;
251}
252
253/**
254 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
255 * @ah: atheros hardware structure
256 * @chan:
257 *
258 * For non single-chip solutions. Converts to baseband spur frequency given the
259 * input channel frequency and compute register settings below.
260 */
261static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
262 struct ath9k_channel *chan)
263{
264 int bb_spur = AR_NO_SPUR;
265 int bin, cur_bin;
266 int spur_freq_sd;
267 int spur_delta_phase;
268 int denominator;
269 int upper, lower, cur_vit_mask;
270 int tmp, new;
271 int i;
272 static int pilot_mask_reg[4] = {
273 AR_PHY_TIMING7, AR_PHY_TIMING8,
274 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
275 };
276 static int chan_mask_reg[4] = {
277 AR_PHY_TIMING9, AR_PHY_TIMING10,
278 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
279 };
280 static int inc[4] = { 0, 100, 0, 0 };
281
282 int8_t mask_m[123];
283 int8_t mask_p[123];
284 int8_t mask_amt;
285 int tmp_mask;
286 int cur_bb_spur;
287 bool is2GHz = IS_CHAN_2GHZ(chan);
288
289 memset(&mask_m, 0, sizeof(int8_t) * 123);
290 memset(&mask_p, 0, sizeof(int8_t) * 123);
291
292 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
293 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
294 if (AR_NO_SPUR == cur_bb_spur)
295 break;
296 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
297 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
298 bb_spur = cur_bb_spur;
299 break;
300 }
301 }
302
303 if (AR_NO_SPUR == bb_spur)
304 return;
305
306 bin = bb_spur * 32;
307
308 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
309 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
310 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
311 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
312 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
313
314 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
315
316 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
317 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
318 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
319 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
320 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
321 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
322
323 spur_delta_phase = ((bb_spur * 524288) / 100) &
324 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
325
326 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
327 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
328
329 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
330 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
331 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
332 REG_WRITE(ah, AR_PHY_TIMING11, new);
333
334 cur_bin = -6000;
335 upper = bin + 100;
336 lower = bin - 100;
337
338 for (i = 0; i < 4; i++) {
339 int pilot_mask = 0;
340 int chan_mask = 0;
341 int bp = 0;
342 for (bp = 0; bp < 30; bp++) {
343 if ((cur_bin > lower) && (cur_bin < upper)) {
344 pilot_mask = pilot_mask | 0x1 << bp;
345 chan_mask = chan_mask | 0x1 << bp;
346 }
347 cur_bin += 100;
348 }
349 cur_bin += inc[i];
350 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
351 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
352 }
353
354 cur_vit_mask = 6100;
355 upper = bin + 120;
356 lower = bin - 120;
357
358 for (i = 0; i < 123; i++) {
359 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
360
361 /* workaround for gcc bug #37014 */
362 volatile int tmp_v = abs(cur_vit_mask - bin);
363
364 if (tmp_v < 75)
365 mask_amt = 1;
366 else
367 mask_amt = 0;
368 if (cur_vit_mask < 0)
369 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
370 else
371 mask_p[cur_vit_mask / 100] = mask_amt;
372 }
373 cur_vit_mask -= 100;
374 }
375
376 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
377 | (mask_m[48] << 26) | (mask_m[49] << 24)
378 | (mask_m[50] << 22) | (mask_m[51] << 20)
379 | (mask_m[52] << 18) | (mask_m[53] << 16)
380 | (mask_m[54] << 14) | (mask_m[55] << 12)
381 | (mask_m[56] << 10) | (mask_m[57] << 8)
382 | (mask_m[58] << 6) | (mask_m[59] << 4)
383 | (mask_m[60] << 2) | (mask_m[61] << 0);
384 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
385 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
386
387 tmp_mask = (mask_m[31] << 28)
388 | (mask_m[32] << 26) | (mask_m[33] << 24)
389 | (mask_m[34] << 22) | (mask_m[35] << 20)
390 | (mask_m[36] << 18) | (mask_m[37] << 16)
391 | (mask_m[48] << 14) | (mask_m[39] << 12)
392 | (mask_m[40] << 10) | (mask_m[41] << 8)
393 | (mask_m[42] << 6) | (mask_m[43] << 4)
394 | (mask_m[44] << 2) | (mask_m[45] << 0);
395 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
396 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
397
398 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
399 | (mask_m[18] << 26) | (mask_m[18] << 24)
400 | (mask_m[20] << 22) | (mask_m[20] << 20)
401 | (mask_m[22] << 18) | (mask_m[22] << 16)
402 | (mask_m[24] << 14) | (mask_m[24] << 12)
403 | (mask_m[25] << 10) | (mask_m[26] << 8)
404 | (mask_m[27] << 6) | (mask_m[28] << 4)
405 | (mask_m[29] << 2) | (mask_m[30] << 0);
406 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
407 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
408
409 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
410 | (mask_m[2] << 26) | (mask_m[3] << 24)
411 | (mask_m[4] << 22) | (mask_m[5] << 20)
412 | (mask_m[6] << 18) | (mask_m[7] << 16)
413 | (mask_m[8] << 14) | (mask_m[9] << 12)
414 | (mask_m[10] << 10) | (mask_m[11] << 8)
415 | (mask_m[12] << 6) | (mask_m[13] << 4)
416 | (mask_m[14] << 2) | (mask_m[15] << 0);
417 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
418 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
419
420 tmp_mask = (mask_p[15] << 28)
421 | (mask_p[14] << 26) | (mask_p[13] << 24)
422 | (mask_p[12] << 22) | (mask_p[11] << 20)
423 | (mask_p[10] << 18) | (mask_p[9] << 16)
424 | (mask_p[8] << 14) | (mask_p[7] << 12)
425 | (mask_p[6] << 10) | (mask_p[5] << 8)
426 | (mask_p[4] << 6) | (mask_p[3] << 4)
427 | (mask_p[2] << 2) | (mask_p[1] << 0);
428 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
429 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
430
431 tmp_mask = (mask_p[30] << 28)
432 | (mask_p[29] << 26) | (mask_p[28] << 24)
433 | (mask_p[27] << 22) | (mask_p[26] << 20)
434 | (mask_p[25] << 18) | (mask_p[24] << 16)
435 | (mask_p[23] << 14) | (mask_p[22] << 12)
436 | (mask_p[21] << 10) | (mask_p[20] << 8)
437 | (mask_p[19] << 6) | (mask_p[18] << 4)
438 | (mask_p[17] << 2) | (mask_p[16] << 0);
439 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
440 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
441
442 tmp_mask = (mask_p[45] << 28)
443 | (mask_p[44] << 26) | (mask_p[43] << 24)
444 | (mask_p[42] << 22) | (mask_p[41] << 20)
445 | (mask_p[40] << 18) | (mask_p[39] << 16)
446 | (mask_p[38] << 14) | (mask_p[37] << 12)
447 | (mask_p[36] << 10) | (mask_p[35] << 8)
448 | (mask_p[34] << 6) | (mask_p[33] << 4)
449 | (mask_p[32] << 2) | (mask_p[31] << 0);
450 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
451 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
452
453 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
454 | (mask_p[59] << 26) | (mask_p[58] << 24)
455 | (mask_p[57] << 22) | (mask_p[56] << 20)
456 | (mask_p[55] << 18) | (mask_p[54] << 16)
457 | (mask_p[53] << 14) | (mask_p[52] << 12)
458 | (mask_p[51] << 10) | (mask_p[50] << 8)
459 | (mask_p[49] << 6) | (mask_p[48] << 4)
460 | (mask_p[47] << 2) | (mask_p[46] << 0);
461 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
462 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
463}
464
465/**
466 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
467 * @ah: atheros hardware structure
468 *
469 * Only required for older devices with external AR2133/AR5133 radios.
470 */
471static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
472{
473#define ATH_ALLOC_BANK(bank, size) do { \
474 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
475 if (!bank) { \
476 ath_err(common, "Cannot allocate RF banks\n"); \
477 return -ENOMEM; \
478 } \
479 } while (0);
480
481 struct ath_common *common = ath9k_hw_common(ah);
482
483 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
484
485 ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
486 ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
487 ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
488 ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
489 ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
490 ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
491 ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
492 ATH_ALLOC_BANK(ah->addac5416_21,
493 ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
494 ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
495
496 return 0;
497#undef ATH_ALLOC_BANK
498}
499
500
501/**
502 * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
503 * @ah: atheros hardware struture
504 * For the external AR2133/AR5133 radios banks.
505 */
506static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
507{
508#define ATH_FREE_BANK(bank) do { \
509 kfree(bank); \
510 bank = NULL; \
511 } while (0);
512
513 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
514
515 ATH_FREE_BANK(ah->analogBank0Data);
516 ATH_FREE_BANK(ah->analogBank1Data);
517 ATH_FREE_BANK(ah->analogBank2Data);
518 ATH_FREE_BANK(ah->analogBank3Data);
519 ATH_FREE_BANK(ah->analogBank6Data);
520 ATH_FREE_BANK(ah->analogBank6TPCData);
521 ATH_FREE_BANK(ah->analogBank7Data);
522 ATH_FREE_BANK(ah->addac5416_21);
523 ATH_FREE_BANK(ah->bank6Temp);
524
525#undef ATH_FREE_BANK
526}
527
528/* *
529 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
530 * @ah: atheros hardware structure
531 * @chan:
532 * @modesIndex:
533 *
534 * Used for the external AR2133/AR5133 radios.
535 *
536 * Reads the EEPROM header info from the device structure and programs
537 * all rf registers. This routine requires access to the analog
538 * rf device. This is not required for single-chip devices.
539 */
540static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
541 struct ath9k_channel *chan,
542 u16 modesIndex)
543{
544 u32 eepMinorRev;
545 u32 ob5GHz = 0, db5GHz = 0;
546 u32 ob2GHz = 0, db2GHz = 0;
547 int regWrites = 0;
548
549 /*
550 * Software does not need to program bank data
551 * for single chip devices, that is AR9280 or anything
552 * after that.
553 */
554 if (AR_SREV_9280_20_OR_LATER(ah))
555 return true;
556
557 /* Setup rf parameters */
558 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
559
560 /* Setup Bank 0 Write */
561 ar5008_rf_bank_setup(ah->analogBank0Data, &ah->iniBank0, 1);
562
563 /* Setup Bank 1 Write */
564 ar5008_rf_bank_setup(ah->analogBank1Data, &ah->iniBank1, 1);
565
566 /* Setup Bank 2 Write */
567 ar5008_rf_bank_setup(ah->analogBank2Data, &ah->iniBank2, 1);
568
569 /* Setup Bank 6 Write */
570 ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3,
571 modesIndex);
572 {
573 int i;
574 for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
575 ah->analogBank6Data[i] =
576 INI_RA(&ah->iniBank6TPC, i, modesIndex);
577 }
578 }
579
580 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
581 if (eepMinorRev >= 2) {
582 if (IS_CHAN_2GHZ(chan)) {
583 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
584 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
585 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
586 ob2GHz, 3, 197, 0);
587 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
588 db2GHz, 3, 194, 0);
589 } else {
590 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
591 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
592 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
593 ob5GHz, 3, 203, 0);
594 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
595 db5GHz, 3, 200, 0);
596 }
597 }
598
599 /* Setup Bank 7 Setup */
600 ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1);
601
602 /* Write Analog registers */
603 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
604 regWrites);
605 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
606 regWrites);
607 REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
608 regWrites);
609 REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
610 regWrites);
611 REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
612 regWrites);
613 REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
614 regWrites);
615
616 return true;
617}
618
619static void ar5008_hw_init_bb(struct ath_hw *ah,
620 struct ath9k_channel *chan)
621{
622 u32 synthDelay;
623
624 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
625 if (IS_CHAN_B(chan))
626 synthDelay = (4 * synthDelay) / 22;
627 else
628 synthDelay /= 10;
629
630 if (IS_CHAN_HALF_RATE(chan))
631 synthDelay *= 2;
632 else if (IS_CHAN_QUARTER_RATE(chan))
633 synthDelay *= 4;
634
635 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
636
637 udelay(synthDelay + BASE_ACTIVATE_DELAY);
638}
639
640static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
641{
642 int rx_chainmask, tx_chainmask;
643
644 rx_chainmask = ah->rxchainmask;
645 tx_chainmask = ah->txchainmask;
646
647
648 switch (rx_chainmask) {
649 case 0x5:
650 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
651 AR_PHY_SWAP_ALT_CHAIN);
652 case 0x3:
653 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
654 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
655 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
656 break;
657 }
658 case 0x1:
659 case 0x2:
660 case 0x7:
661 ENABLE_REGWRITE_BUFFER(ah);
662 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
663 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
664 break;
665 default:
666 ENABLE_REGWRITE_BUFFER(ah);
667 break;
668 }
669
670 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
671
672 REGWRITE_BUFFER_FLUSH(ah);
673
674 if (tx_chainmask == 0x5) {
675 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
676 AR_PHY_SWAP_ALT_CHAIN);
677 }
678 if (AR_SREV_9100(ah))
679 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
680 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
681}
682
683static void ar5008_hw_override_ini(struct ath_hw *ah,
684 struct ath9k_channel *chan)
685{
686 u32 val;
687
688 /*
689 * Set the RX_ABORT and RX_DIS and clear if off only after
690 * RXE is set for MAC. This prevents frames with corrupted
691 * descriptor status.
692 */
693 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
694
695 if (AR_SREV_9280_20_OR_LATER(ah)) {
696 val = REG_READ(ah, AR_PCU_MISC_MODE2);
697
698 if (!AR_SREV_9271(ah))
699 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
700
701 if (AR_SREV_9287_11_OR_LATER(ah))
702 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
703
704 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
705 }
706
707 if (!AR_SREV_5416_20_OR_LATER(ah) ||
708 AR_SREV_9280_20_OR_LATER(ah))
709 return;
710 /*
711 * Disable BB clock gating
712 * Necessary to avoid issues on AR5416 2.0
713 */
714 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
715
716 /*
717 * Disable RIFS search on some chips to avoid baseband
718 * hang issues.
719 */
720 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
721 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
722 val &= ~AR_PHY_RIFS_INIT_DELAY;
723 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
724 }
725}
726
727static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
728 struct ath9k_channel *chan)
729{
730 u32 phymode;
731 u32 enableDacFifo = 0;
732
733 if (AR_SREV_9285_12_OR_LATER(ah))
734 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
735 AR_PHY_FC_ENABLE_DAC_FIFO);
736
737 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
738 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
739
740 if (IS_CHAN_HT40(chan)) {
741 phymode |= AR_PHY_FC_DYN2040_EN;
742
743 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
744 (chan->chanmode == CHANNEL_G_HT40PLUS))
745 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
746
747 }
748 REG_WRITE(ah, AR_PHY_TURBO, phymode);
749
750 ath9k_hw_set11nmac2040(ah);
751
752 ENABLE_REGWRITE_BUFFER(ah);
753
754 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
755 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
756
757 REGWRITE_BUFFER_FLUSH(ah);
758}
759
760
761static int ar5008_hw_process_ini(struct ath_hw *ah,
762 struct ath9k_channel *chan)
763{
764 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
765 struct ath_common *common = ath9k_hw_common(ah);
766 int i, regWrites = 0;
767 struct ieee80211_channel *channel = chan->chan;
768 u32 modesIndex, freqIndex;
769
770 switch (chan->chanmode) {
771 case CHANNEL_A:
772 case CHANNEL_A_HT20:
773 modesIndex = 1;
774 freqIndex = 1;
775 break;
776 case CHANNEL_A_HT40PLUS:
777 case CHANNEL_A_HT40MINUS:
778 modesIndex = 2;
779 freqIndex = 1;
780 break;
781 case CHANNEL_G:
782 case CHANNEL_G_HT20:
783 case CHANNEL_B:
784 modesIndex = 4;
785 freqIndex = 2;
786 break;
787 case CHANNEL_G_HT40PLUS:
788 case CHANNEL_G_HT40MINUS:
789 modesIndex = 3;
790 freqIndex = 2;
791 break;
792
793 default:
794 return -EINVAL;
795 }
796
797 /*
798 * Set correct baseband to analog shift setting to
799 * access analog chips.
800 */
801 REG_WRITE(ah, AR_PHY(0), 0x00000007);
802
803 /* Write ADDAC shifts */
804 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
805 ah->eep_ops->set_addac(ah, chan);
806
807 if (AR_SREV_5416_22_OR_LATER(ah)) {
808 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
809 } else {
810 struct ar5416IniArray temp;
811 u32 addacSize =
812 sizeof(u32) * ah->iniAddac.ia_rows *
813 ah->iniAddac.ia_columns;
814
815 /* For AR5416 2.0/2.1 */
816 memcpy(ah->addac5416_21,
817 ah->iniAddac.ia_array, addacSize);
818
819 /* override CLKDRV value at [row, column] = [31, 1] */
820 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
821
822 temp.ia_array = ah->addac5416_21;
823 temp.ia_columns = ah->iniAddac.ia_columns;
824 temp.ia_rows = ah->iniAddac.ia_rows;
825 REG_WRITE_ARRAY(&temp, 1, regWrites);
826 }
827
828 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
829
830 ENABLE_REGWRITE_BUFFER(ah);
831
832 for (i = 0; i < ah->iniModes.ia_rows; i++) {
833 u32 reg = INI_RA(&ah->iniModes, i, 0);
834 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
835
836 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
837 val &= ~AR_AN_TOP2_PWDCLKIND;
838
839 REG_WRITE(ah, reg, val);
840
841 if (reg >= 0x7800 && reg < 0x78a0
842 && ah->config.analog_shiftreg
843 && (common->bus_ops->ath_bus_type != ATH_USB)) {
844 udelay(100);
845 }
846
847 DO_DELAY(regWrites);
848 }
849
850 REGWRITE_BUFFER_FLUSH(ah);
851
852 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah))
853 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
854
855 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
856 AR_SREV_9287_11_OR_LATER(ah))
857 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
858
859 if (AR_SREV_9271_10(ah))
860 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
861 modesIndex, regWrites);
862
863 ENABLE_REGWRITE_BUFFER(ah);
864
865 /* Write common array parameters */
866 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
867 u32 reg = INI_RA(&ah->iniCommon, i, 0);
868 u32 val = INI_RA(&ah->iniCommon, i, 1);
869
870 REG_WRITE(ah, reg, val);
871
872 if (reg >= 0x7800 && reg < 0x78a0
873 && ah->config.analog_shiftreg
874 && (common->bus_ops->ath_bus_type != ATH_USB)) {
875 udelay(100);
876 }
877
878 DO_DELAY(regWrites);
879 }
880
881 REGWRITE_BUFFER_FLUSH(ah);
882
883 if (AR_SREV_9271(ah)) {
884 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
885 REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
886 modesIndex, regWrites);
887 else
888 REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
889 modesIndex, regWrites);
890 }
891
892 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
893
894 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) {
895 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
896 regWrites);
897 }
898
899 ar5008_hw_override_ini(ah, chan);
900 ar5008_hw_set_channel_regs(ah, chan);
901 ar5008_hw_init_chain_masks(ah);
902 ath9k_olc_init(ah);
903
904 /* Set TX power */
905 ah->eep_ops->set_txpower(ah, chan,
906 ath9k_regd_get_ctl(regulatory, chan),
907 channel->max_antenna_gain * 2,
908 channel->max_power * 2,
909 min((u32) MAX_RATE_POWER,
910 (u32) regulatory->power_limit), false);
911
912 /* Write analog registers */
913 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
914 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n");
915 return -EIO;
916 }
917
918 return 0;
919}
920
921static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
922{
923 u32 rfMode = 0;
924
925 if (chan == NULL)
926 return;
927
928 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
929 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
930
931 if (!AR_SREV_9280_20_OR_LATER(ah))
932 rfMode |= (IS_CHAN_5GHZ(chan)) ?
933 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
934
935 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
936 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
937
938 REG_WRITE(ah, AR_PHY_MODE, rfMode);
939}
940
941static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
942{
943 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
944}
945
946static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
947 struct ath9k_channel *chan)
948{
949 u32 coef_scaled, ds_coef_exp, ds_coef_man;
950 u32 clockMhzScaled = 0x64000000;
951 struct chan_centers centers;
952
953 if (IS_CHAN_HALF_RATE(chan))
954 clockMhzScaled = clockMhzScaled >> 1;
955 else if (IS_CHAN_QUARTER_RATE(chan))
956 clockMhzScaled = clockMhzScaled >> 2;
957
958 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
959 coef_scaled = clockMhzScaled / centers.synth_center;
960
961 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
962 &ds_coef_exp);
963
964 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
965 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
966 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
967 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
968
969 coef_scaled = (9 * coef_scaled) / 10;
970
971 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
972 &ds_coef_exp);
973
974 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
975 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
976 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
977 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
978}
979
980static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
981{
982 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
983 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
984 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
985}
986
987static void ar5008_hw_rfbus_done(struct ath_hw *ah)
988{
989 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
990 if (IS_CHAN_B(ah->curchan))
991 synthDelay = (4 * synthDelay) / 22;
992 else
993 synthDelay /= 10;
994
995 udelay(synthDelay + BASE_ACTIVATE_DELAY);
996
997 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
998}
999
1000static void ar5008_restore_chainmask(struct ath_hw *ah)
1001{
1002 int rx_chainmask = ah->rxchainmask;
1003
1004 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
1005 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1006 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1007 }
1008}
1009
1010static void ar5008_set_diversity(struct ath_hw *ah, bool value)
1011{
1012 u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
1013 if (value)
1014 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1015 else
1016 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1017 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
1018}
1019
1020static u32 ar9100_hw_compute_pll_control(struct ath_hw *ah,
1021 struct ath9k_channel *chan)
1022{
1023 if (chan && IS_CHAN_5GHZ(chan))
1024 return 0x1450;
1025 return 0x1458;
1026}
1027
1028static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
1029 struct ath9k_channel *chan)
1030{
1031 u32 pll;
1032
1033 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1034
1035 if (chan && IS_CHAN_HALF_RATE(chan))
1036 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1037 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1038 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1039
1040 if (chan && IS_CHAN_5GHZ(chan))
1041 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1042 else
1043 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1044
1045 return pll;
1046}
1047
1048static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
1049 struct ath9k_channel *chan)
1050{
1051 u32 pll;
1052
1053 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1054
1055 if (chan && IS_CHAN_HALF_RATE(chan))
1056 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1057 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1058 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1059
1060 if (chan && IS_CHAN_5GHZ(chan))
1061 pll |= SM(0xa, AR_RTC_PLL_DIV);
1062 else
1063 pll |= SM(0xb, AR_RTC_PLL_DIV);
1064
1065 return pll;
1066}
1067
1068static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
1069 enum ath9k_ani_cmd cmd,
1070 int param)
1071{
1072 struct ar5416AniState *aniState = &ah->curchan->ani;
1073 struct ath_common *common = ath9k_hw_common(ah);
1074
1075 switch (cmd & ah->ani_function) {
1076 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
1077 u32 level = param;
1078
1079 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
1080 ath_dbg(common, ATH_DBG_ANI,
1081 "level out of range (%u > %zu)\n",
1082 level, ARRAY_SIZE(ah->totalSizeDesired));
1083 return false;
1084 }
1085
1086 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1087 AR_PHY_DESIRED_SZ_TOT_DES,
1088 ah->totalSizeDesired[level]);
1089 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1090 AR_PHY_AGC_CTL1_COARSE_LOW,
1091 ah->coarse_low[level]);
1092 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1093 AR_PHY_AGC_CTL1_COARSE_HIGH,
1094 ah->coarse_high[level]);
1095 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1096 AR_PHY_FIND_SIG_FIRPWR,
1097 ah->firpwr[level]);
1098
1099 if (level > aniState->noiseImmunityLevel)
1100 ah->stats.ast_ani_niup++;
1101 else if (level < aniState->noiseImmunityLevel)
1102 ah->stats.ast_ani_nidown++;
1103 aniState->noiseImmunityLevel = level;
1104 break;
1105 }
1106 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1107 static const int m1ThreshLow[] = { 127, 50 };
1108 static const int m2ThreshLow[] = { 127, 40 };
1109 static const int m1Thresh[] = { 127, 0x4d };
1110 static const int m2Thresh[] = { 127, 0x40 };
1111 static const int m2CountThr[] = { 31, 16 };
1112 static const int m2CountThrLow[] = { 63, 48 };
1113 u32 on = param ? 1 : 0;
1114
1115 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1116 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1117 m1ThreshLow[on]);
1118 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1119 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1120 m2ThreshLow[on]);
1121 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1122 AR_PHY_SFCORR_M1_THRESH,
1123 m1Thresh[on]);
1124 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1125 AR_PHY_SFCORR_M2_THRESH,
1126 m2Thresh[on]);
1127 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1128 AR_PHY_SFCORR_M2COUNT_THR,
1129 m2CountThr[on]);
1130 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1131 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1132 m2CountThrLow[on]);
1133
1134 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1135 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1136 m1ThreshLow[on]);
1137 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1138 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1139 m2ThreshLow[on]);
1140 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1141 AR_PHY_SFCORR_EXT_M1_THRESH,
1142 m1Thresh[on]);
1143 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1144 AR_PHY_SFCORR_EXT_M2_THRESH,
1145 m2Thresh[on]);
1146
1147 if (on)
1148 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1149 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1150 else
1151 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1152 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1153
1154 if (!on != aniState->ofdmWeakSigDetectOff) {
1155 if (on)
1156 ah->stats.ast_ani_ofdmon++;
1157 else
1158 ah->stats.ast_ani_ofdmoff++;
1159 aniState->ofdmWeakSigDetectOff = !on;
1160 }
1161 break;
1162 }
1163 case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
1164 static const int weakSigThrCck[] = { 8, 6 };
1165 u32 high = param ? 1 : 0;
1166
1167 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
1168 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
1169 weakSigThrCck[high]);
1170 if (high != aniState->cckWeakSigThreshold) {
1171 if (high)
1172 ah->stats.ast_ani_cckhigh++;
1173 else
1174 ah->stats.ast_ani_ccklow++;
1175 aniState->cckWeakSigThreshold = high;
1176 }
1177 break;
1178 }
1179 case ATH9K_ANI_FIRSTEP_LEVEL:{
1180 static const int firstep[] = { 0, 4, 8 };
1181 u32 level = param;
1182
1183 if (level >= ARRAY_SIZE(firstep)) {
1184 ath_dbg(common, ATH_DBG_ANI,
1185 "level out of range (%u > %zu)\n",
1186 level, ARRAY_SIZE(firstep));
1187 return false;
1188 }
1189 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1190 AR_PHY_FIND_SIG_FIRSTEP,
1191 firstep[level]);
1192 if (level > aniState->firstepLevel)
1193 ah->stats.ast_ani_stepup++;
1194 else if (level < aniState->firstepLevel)
1195 ah->stats.ast_ani_stepdown++;
1196 aniState->firstepLevel = level;
1197 break;
1198 }
1199 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1200 static const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
1201 u32 level = param;
1202
1203 if (level >= ARRAY_SIZE(cycpwrThr1)) {
1204 ath_dbg(common, ATH_DBG_ANI,
1205 "level out of range (%u > %zu)\n",
1206 level, ARRAY_SIZE(cycpwrThr1));
1207 return false;
1208 }
1209 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1210 AR_PHY_TIMING5_CYCPWR_THR1,
1211 cycpwrThr1[level]);
1212 if (level > aniState->spurImmunityLevel)
1213 ah->stats.ast_ani_spurup++;
1214 else if (level < aniState->spurImmunityLevel)
1215 ah->stats.ast_ani_spurdown++;
1216 aniState->spurImmunityLevel = level;
1217 break;
1218 }
1219 case ATH9K_ANI_PRESENT:
1220 break;
1221 default:
1222 ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
1223 return false;
1224 }
1225
1226 ath_dbg(common, ATH_DBG_ANI, "ANI parameters:\n");
1227 ath_dbg(common, ATH_DBG_ANI,
1228 "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetectOff=%d\n",
1229 aniState->noiseImmunityLevel,
1230 aniState->spurImmunityLevel,
1231 !aniState->ofdmWeakSigDetectOff);
1232 ath_dbg(common, ATH_DBG_ANI,
1233 "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n",
1234 aniState->cckWeakSigThreshold,
1235 aniState->firstepLevel,
1236 aniState->listenTime);
1237 ath_dbg(common, ATH_DBG_ANI,
1238 "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
1239 aniState->ofdmPhyErrCount,
1240 aniState->cckPhyErrCount);
1241
1242 return true;
1243}
1244
1245static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1246 enum ath9k_ani_cmd cmd,
1247 int param)
1248{
1249 struct ath_common *common = ath9k_hw_common(ah);
1250 struct ath9k_channel *chan = ah->curchan;
1251 struct ar5416AniState *aniState = &chan->ani;
1252 s32 value, value2;
1253
1254 switch (cmd & ah->ani_function) {
1255 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1256 /*
1257 * on == 1 means ofdm weak signal detection is ON
1258 * on == 1 is the default, for less noise immunity
1259 *
1260 * on == 0 means ofdm weak signal detection is OFF
1261 * on == 0 means more noise imm
1262 */
1263 u32 on = param ? 1 : 0;
1264 /*
1265 * make register setting for default
1266 * (weak sig detect ON) come from INI file
1267 */
1268 int m1ThreshLow = on ?
1269 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
1270 int m2ThreshLow = on ?
1271 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
1272 int m1Thresh = on ?
1273 aniState->iniDef.m1Thresh : m1Thresh_off;
1274 int m2Thresh = on ?
1275 aniState->iniDef.m2Thresh : m2Thresh_off;
1276 int m2CountThr = on ?
1277 aniState->iniDef.m2CountThr : m2CountThr_off;
1278 int m2CountThrLow = on ?
1279 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
1280 int m1ThreshLowExt = on ?
1281 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
1282 int m2ThreshLowExt = on ?
1283 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
1284 int m1ThreshExt = on ?
1285 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
1286 int m2ThreshExt = on ?
1287 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
1288
1289 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1290 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1291 m1ThreshLow);
1292 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1293 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1294 m2ThreshLow);
1295 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1296 AR_PHY_SFCORR_M1_THRESH, m1Thresh);
1297 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1298 AR_PHY_SFCORR_M2_THRESH, m2Thresh);
1299 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1300 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
1301 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1302 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1303 m2CountThrLow);
1304
1305 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1306 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
1307 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1308 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
1309 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1310 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
1311 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1312 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
1313
1314 if (on)
1315 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1316 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1317 else
1318 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1319 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1320
1321 if (!on != aniState->ofdmWeakSigDetectOff) {
1322 ath_dbg(common, ATH_DBG_ANI,
1323 "** ch %d: ofdm weak signal: %s=>%s\n",
1324 chan->channel,
1325 !aniState->ofdmWeakSigDetectOff ?
1326 "on" : "off",
1327 on ? "on" : "off");
1328 if (on)
1329 ah->stats.ast_ani_ofdmon++;
1330 else
1331 ah->stats.ast_ani_ofdmoff++;
1332 aniState->ofdmWeakSigDetectOff = !on;
1333 }
1334 break;
1335 }
1336 case ATH9K_ANI_FIRSTEP_LEVEL:{
1337 u32 level = param;
1338
1339 if (level >= ARRAY_SIZE(firstep_table)) {
1340 ath_dbg(common, ATH_DBG_ANI,
1341 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1342 level, ARRAY_SIZE(firstep_table));
1343 return false;
1344 }
1345
1346 /*
1347 * make register setting relative to default
1348 * from INI file & cap value
1349 */
1350 value = firstep_table[level] -
1351 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
1352 aniState->iniDef.firstep;
1353 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1354 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1355 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1356 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1357 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1358 AR_PHY_FIND_SIG_FIRSTEP,
1359 value);
1360 /*
1361 * we need to set first step low register too
1362 * make register setting relative to default
1363 * from INI file & cap value
1364 */
1365 value2 = firstep_table[level] -
1366 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
1367 aniState->iniDef.firstepLow;
1368 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1369 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1370 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1371 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1372
1373 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1374 AR_PHY_FIND_SIG_FIRSTEP_LOW, value2);
1375
1376 if (level != aniState->firstepLevel) {
1377 ath_dbg(common, ATH_DBG_ANI,
1378 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1379 chan->channel,
1380 aniState->firstepLevel,
1381 level,
1382 ATH9K_ANI_FIRSTEP_LVL_NEW,
1383 value,
1384 aniState->iniDef.firstep);
1385 ath_dbg(common, ATH_DBG_ANI,
1386 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1387 chan->channel,
1388 aniState->firstepLevel,
1389 level,
1390 ATH9K_ANI_FIRSTEP_LVL_NEW,
1391 value2,
1392 aniState->iniDef.firstepLow);
1393 if (level > aniState->firstepLevel)
1394 ah->stats.ast_ani_stepup++;
1395 else if (level < aniState->firstepLevel)
1396 ah->stats.ast_ani_stepdown++;
1397 aniState->firstepLevel = level;
1398 }
1399 break;
1400 }
1401 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1402 u32 level = param;
1403
1404 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1405 ath_dbg(common, ATH_DBG_ANI,
1406 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1407 level, ARRAY_SIZE(cycpwrThr1_table));
1408 return false;
1409 }
1410 /*
1411 * make register setting relative to default
1412 * from INI file & cap value
1413 */
1414 value = cycpwrThr1_table[level] -
1415 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
1416 aniState->iniDef.cycpwrThr1;
1417 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1418 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1419 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1420 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1421 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1422 AR_PHY_TIMING5_CYCPWR_THR1,
1423 value);
1424
1425 /*
1426 * set AR_PHY_EXT_CCA for extension channel
1427 * make register setting relative to default
1428 * from INI file & cap value
1429 */
1430 value2 = cycpwrThr1_table[level] -
1431 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
1432 aniState->iniDef.cycpwrThr1Ext;
1433 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1434 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1435 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1436 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1437 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1438 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2);
1439
1440 if (level != aniState->spurImmunityLevel) {
1441 ath_dbg(common, ATH_DBG_ANI,
1442 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1443 chan->channel,
1444 aniState->spurImmunityLevel,
1445 level,
1446 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1447 value,
1448 aniState->iniDef.cycpwrThr1);
1449 ath_dbg(common, ATH_DBG_ANI,
1450 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1451 chan->channel,
1452 aniState->spurImmunityLevel,
1453 level,
1454 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1455 value2,
1456 aniState->iniDef.cycpwrThr1Ext);
1457 if (level > aniState->spurImmunityLevel)
1458 ah->stats.ast_ani_spurup++;
1459 else if (level < aniState->spurImmunityLevel)
1460 ah->stats.ast_ani_spurdown++;
1461 aniState->spurImmunityLevel = level;
1462 }
1463 break;
1464 }
1465 case ATH9K_ANI_MRC_CCK:
1466 /*
1467 * You should not see this as AR5008, AR9001, AR9002
1468 * does not have hardware support for MRC CCK.
1469 */
1470 WARN_ON(1);
1471 break;
1472 case ATH9K_ANI_PRESENT:
1473 break;
1474 default:
1475 ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
1476 return false;
1477 }
1478
1479 ath_dbg(common, ATH_DBG_ANI,
1480 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1481 aniState->spurImmunityLevel,
1482 !aniState->ofdmWeakSigDetectOff ? "on" : "off",
1483 aniState->firstepLevel,
1484 !aniState->mrcCCKOff ? "on" : "off",
1485 aniState->listenTime,
1486 aniState->ofdmPhyErrCount,
1487 aniState->cckPhyErrCount);
1488 return true;
1489}
1490
1491static void ar5008_hw_do_getnf(struct ath_hw *ah,
1492 int16_t nfarray[NUM_NF_READINGS])
1493{
1494 int16_t nf;
1495
1496 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
1497 nfarray[0] = sign_extend32(nf, 8);
1498
1499 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
1500 nfarray[1] = sign_extend32(nf, 8);
1501
1502 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
1503 nfarray[2] = sign_extend32(nf, 8);
1504
1505 if (!IS_CHAN_HT40(ah->curchan))
1506 return;
1507
1508 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
1509 nfarray[3] = sign_extend32(nf, 8);
1510
1511 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
1512 nfarray[4] = sign_extend32(nf, 8);
1513
1514 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
1515 nfarray[5] = sign_extend32(nf, 8);
1516}
1517
1518/*
1519 * Initialize the ANI register values with default (ini) values.
1520 * This routine is called during a (full) hardware reset after
1521 * all the registers are initialised from the INI.
1522 */
1523static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
1524{
1525 struct ath_common *common = ath9k_hw_common(ah);
1526 struct ath9k_channel *chan = ah->curchan;
1527 struct ar5416AniState *aniState = &chan->ani;
1528 struct ath9k_ani_default *iniDef;
1529 u32 val;
1530
1531 iniDef = &aniState->iniDef;
1532
1533 ath_dbg(common, ATH_DBG_ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1534 ah->hw_version.macVersion,
1535 ah->hw_version.macRev,
1536 ah->opmode,
1537 chan->channel,
1538 chan->channelFlags);
1539
1540 val = REG_READ(ah, AR_PHY_SFCORR);
1541 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1542 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1543 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1544
1545 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1546 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1547 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1548 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1549
1550 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1551 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1552 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1553 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1554 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1555 iniDef->firstep = REG_READ_FIELD(ah,
1556 AR_PHY_FIND_SIG,
1557 AR_PHY_FIND_SIG_FIRSTEP);
1558 iniDef->firstepLow = REG_READ_FIELD(ah,
1559 AR_PHY_FIND_SIG_LOW,
1560 AR_PHY_FIND_SIG_FIRSTEP_LOW);
1561 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1562 AR_PHY_TIMING5,
1563 AR_PHY_TIMING5_CYCPWR_THR1);
1564 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1565 AR_PHY_EXT_CCA,
1566 AR_PHY_EXT_TIMING5_CYCPWR_THR1);
1567
1568 /* these levels just got reset to defaults by the INI */
1569 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1570 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1571 aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
1572 aniState->mrcCCKOff = true; /* not available on pre AR9003 */
1573}
1574
1575static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
1576{
1577 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
1578 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
1579 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
1580 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
1581 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
1582 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
1583}
1584
1585static void ar5008_hw_set_radar_params(struct ath_hw *ah,
1586 struct ath_hw_radar_conf *conf)
1587{
1588 u32 radar_0 = 0, radar_1 = 0;
1589
1590 if (!conf) {
1591 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1592 return;
1593 }
1594
1595 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1596 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1597 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1598 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1599 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1600 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1601
1602 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1603 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1604 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1605 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1606 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1607
1608 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1609 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1610 if (conf->ext_channel)
1611 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1612 else
1613 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1614}
1615
1616static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
1617{
1618 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1619
1620 conf->fir_power = -33;
1621 conf->radar_rssi = 20;
1622 conf->pulse_height = 10;
1623 conf->pulse_rssi = 24;
1624 conf->pulse_inband = 15;
1625 conf->pulse_maxlen = 255;
1626 conf->pulse_inband_step = 12;
1627 conf->radar_inband = 8;
1628}
1629
1630void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
1631{
1632 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1633 static const u32 ar5416_cca_regs[6] = {
1634 AR_PHY_CCA,
1635 AR_PHY_CH1_CCA,
1636 AR_PHY_CH2_CCA,
1637 AR_PHY_EXT_CCA,
1638 AR_PHY_CH1_EXT_CCA,
1639 AR_PHY_CH2_EXT_CCA
1640 };
1641
1642 priv_ops->rf_set_freq = ar5008_hw_set_channel;
1643 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
1644
1645 priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks;
1646 priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks;
1647 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
1648 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
1649 priv_ops->init_bb = ar5008_hw_init_bb;
1650 priv_ops->process_ini = ar5008_hw_process_ini;
1651 priv_ops->set_rfmode = ar5008_hw_set_rfmode;
1652 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
1653 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
1654 priv_ops->rfbus_req = ar5008_hw_rfbus_req;
1655 priv_ops->rfbus_done = ar5008_hw_rfbus_done;
1656 priv_ops->restore_chainmask = ar5008_restore_chainmask;
1657 priv_ops->set_diversity = ar5008_set_diversity;
1658 priv_ops->do_getnf = ar5008_hw_do_getnf;
1659 priv_ops->set_radar_params = ar5008_hw_set_radar_params;
1660
1661 if (modparam_force_new_ani) {
1662 priv_ops->ani_control = ar5008_hw_ani_control_new;
1663 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs;
1664 } else
1665 priv_ops->ani_control = ar5008_hw_ani_control_old;
1666
1667 if (AR_SREV_9100(ah))
1668 priv_ops->compute_pll_control = ar9100_hw_compute_pll_control;
1669 else if (AR_SREV_9160_10_OR_LATER(ah))
1670 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
1671 else
1672 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
1673
1674 ar5008_hw_set_nf_limits(ah);
1675 ar5008_hw_set_radar_conf(ah);
1676 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
1677}
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18#include "hw-ops.h"
19#include "../regd.h"
20#include "ar9002_phy.h"
21
22/* All code below is for AR5008, AR9001, AR9002 */
23
24static const int firstep_table[] =
25/* level: 0 1 2 3 4 5 6 7 8 */
26 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
27
28static const int cycpwrThr1_table[] =
29/* level: 0 1 2 3 4 5 6 7 8 */
30 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
31
32/*
33 * register values to turn OFDM weak signal detection OFF
34 */
35static const int m1ThreshLow_off = 127;
36static const int m2ThreshLow_off = 127;
37static const int m1Thresh_off = 127;
38static const int m2Thresh_off = 127;
39static const int m2CountThr_off = 31;
40static const int m2CountThrLow_off = 63;
41static const int m1ThreshLowExt_off = 127;
42static const int m2ThreshLowExt_off = 127;
43static const int m1ThreshExt_off = 127;
44static const int m2ThreshExt_off = 127;
45
46
47static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array,
48 int col)
49{
50 int i;
51
52 for (i = 0; i < array->ia_rows; i++)
53 bank[i] = INI_RA(array, i, col);
54}
55
56
57#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \
58 ar5008_write_rf_array(ah, iniarray, regData, &(regWr))
59
60static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array,
61 u32 *data, unsigned int *writecnt)
62{
63 int r;
64
65 ENABLE_REGWRITE_BUFFER(ah);
66
67 for (r = 0; r < array->ia_rows; r++) {
68 REG_WRITE(ah, INI_RA(array, r, 0), data[r]);
69 DO_DELAY(*writecnt);
70 }
71
72 REGWRITE_BUFFER_FLUSH(ah);
73}
74
75/**
76 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
77 * @rfbuf:
78 * @reg32:
79 * @numBits:
80 * @firstBit:
81 * @column:
82 *
83 * Performs analog "swizzling" of parameters into their location.
84 * Used on external AR2133/AR5133 radios.
85 */
86static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
87 u32 numBits, u32 firstBit,
88 u32 column)
89{
90 u32 tmp32, mask, arrayEntry, lastBit;
91 int32_t bitPosition, bitsLeft;
92
93 tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
94 arrayEntry = (firstBit - 1) / 8;
95 bitPosition = (firstBit - 1) % 8;
96 bitsLeft = numBits;
97 while (bitsLeft > 0) {
98 lastBit = (bitPosition + bitsLeft > 8) ?
99 8 : bitPosition + bitsLeft;
100 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
101 (column * 8);
102 rfBuf[arrayEntry] &= ~mask;
103 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
104 (column * 8)) & mask;
105 bitsLeft -= 8 - bitPosition;
106 tmp32 = tmp32 >> (8 - bitPosition);
107 bitPosition = 0;
108 arrayEntry++;
109 }
110}
111
112/*
113 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
114 * rf_pwd_icsyndiv.
115 *
116 * Theoretical Rules:
117 * if 2 GHz band
118 * if forceBiasAuto
119 * if synth_freq < 2412
120 * bias = 0
121 * else if 2412 <= synth_freq <= 2422
122 * bias = 1
123 * else // synth_freq > 2422
124 * bias = 2
125 * else if forceBias > 0
126 * bias = forceBias & 7
127 * else
128 * no change, use value from ini file
129 * else
130 * no change, invalid band
131 *
132 * 1st Mod:
133 * 2422 also uses value of 2
134 * <approved>
135 *
136 * 2nd Mod:
137 * Less than 2412 uses value of 0, 2412 and above uses value of 2
138 */
139static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
140{
141 struct ath_common *common = ath9k_hw_common(ah);
142 u32 tmp_reg;
143 int reg_writes = 0;
144 u32 new_bias = 0;
145
146 if (!AR_SREV_5416(ah) || synth_freq >= 3000)
147 return;
148
149 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
150
151 if (synth_freq < 2412)
152 new_bias = 0;
153 else if (synth_freq < 2422)
154 new_bias = 1;
155 else
156 new_bias = 2;
157
158 /* pre-reverse this field */
159 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
160
161 ath_dbg(common, CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n",
162 new_bias, synth_freq);
163
164 /* swizzle rf_pwd_icsyndiv */
165 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
166
167 /* write Bank 6 with new params */
168 REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
169}
170
171/**
172 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
173 * @ah: atheros hardware structure
174 * @chan:
175 *
176 * For the external AR2133/AR5133 radios, takes the MHz channel value and set
177 * the channel value. Assumes writes enabled to analog bus and bank6 register
178 * cache in ah->analogBank6Data.
179 */
180static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
181{
182 struct ath_common *common = ath9k_hw_common(ah);
183 u32 channelSel = 0;
184 u32 bModeSynth = 0;
185 u32 aModeRefSel = 0;
186 u32 reg32 = 0;
187 u16 freq;
188 struct chan_centers centers;
189
190 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
191 freq = centers.synth_center;
192
193 if (freq < 4800) {
194 u32 txctl;
195
196 if (((freq - 2192) % 5) == 0) {
197 channelSel = ((freq - 672) * 2 - 3040) / 10;
198 bModeSynth = 0;
199 } else if (((freq - 2224) % 5) == 0) {
200 channelSel = ((freq - 704) * 2 - 3040) / 10;
201 bModeSynth = 1;
202 } else {
203 ath_err(common, "Invalid channel %u MHz\n", freq);
204 return -EINVAL;
205 }
206
207 channelSel = (channelSel << 2) & 0xff;
208 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
209
210 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
211 if (freq == 2484) {
212
213 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
214 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
215 } else {
216 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
217 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
218 }
219
220 } else if ((freq % 20) == 0 && freq >= 5120) {
221 channelSel =
222 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
223 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
224 } else if ((freq % 10) == 0) {
225 channelSel =
226 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
227 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
228 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
229 else
230 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
231 } else if ((freq % 5) == 0) {
232 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
233 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
234 } else {
235 ath_err(common, "Invalid channel %u MHz\n", freq);
236 return -EINVAL;
237 }
238
239 ar5008_hw_force_bias(ah, freq);
240
241 reg32 =
242 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
243 (1 << 5) | 0x1;
244
245 REG_WRITE(ah, AR_PHY(0x37), reg32);
246
247 ah->curchan = chan;
248
249 return 0;
250}
251
252/**
253 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
254 * @ah: atheros hardware structure
255 * @chan:
256 *
257 * For non single-chip solutions. Converts to baseband spur frequency given the
258 * input channel frequency and compute register settings below.
259 */
260static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
261 struct ath9k_channel *chan)
262{
263 int bb_spur = AR_NO_SPUR;
264 int bin, cur_bin;
265 int spur_freq_sd;
266 int spur_delta_phase;
267 int denominator;
268 int upper, lower, cur_vit_mask;
269 int tmp, new;
270 int i;
271 static int pilot_mask_reg[4] = {
272 AR_PHY_TIMING7, AR_PHY_TIMING8,
273 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
274 };
275 static int chan_mask_reg[4] = {
276 AR_PHY_TIMING9, AR_PHY_TIMING10,
277 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
278 };
279 static int inc[4] = { 0, 100, 0, 0 };
280
281 int8_t mask_m[123];
282 int8_t mask_p[123];
283 int8_t mask_amt;
284 int tmp_mask;
285 int cur_bb_spur;
286 bool is2GHz = IS_CHAN_2GHZ(chan);
287
288 memset(&mask_m, 0, sizeof(int8_t) * 123);
289 memset(&mask_p, 0, sizeof(int8_t) * 123);
290
291 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
292 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
293 if (AR_NO_SPUR == cur_bb_spur)
294 break;
295 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
296 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
297 bb_spur = cur_bb_spur;
298 break;
299 }
300 }
301
302 if (AR_NO_SPUR == bb_spur)
303 return;
304
305 bin = bb_spur * 32;
306
307 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
308 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
309 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
310 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
311 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
312
313 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
314
315 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
316 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
317 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
318 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
319 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
320 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
321
322 spur_delta_phase = ((bb_spur * 524288) / 100) &
323 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
324
325 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
326 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
327
328 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
329 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
330 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
331 REG_WRITE(ah, AR_PHY_TIMING11, new);
332
333 cur_bin = -6000;
334 upper = bin + 100;
335 lower = bin - 100;
336
337 for (i = 0; i < 4; i++) {
338 int pilot_mask = 0;
339 int chan_mask = 0;
340 int bp = 0;
341 for (bp = 0; bp < 30; bp++) {
342 if ((cur_bin > lower) && (cur_bin < upper)) {
343 pilot_mask = pilot_mask | 0x1 << bp;
344 chan_mask = chan_mask | 0x1 << bp;
345 }
346 cur_bin += 100;
347 }
348 cur_bin += inc[i];
349 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
350 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
351 }
352
353 cur_vit_mask = 6100;
354 upper = bin + 120;
355 lower = bin - 120;
356
357 for (i = 0; i < 123; i++) {
358 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
359
360 /* workaround for gcc bug #37014 */
361 volatile int tmp_v = abs(cur_vit_mask - bin);
362
363 if (tmp_v < 75)
364 mask_amt = 1;
365 else
366 mask_amt = 0;
367 if (cur_vit_mask < 0)
368 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
369 else
370 mask_p[cur_vit_mask / 100] = mask_amt;
371 }
372 cur_vit_mask -= 100;
373 }
374
375 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
376 | (mask_m[48] << 26) | (mask_m[49] << 24)
377 | (mask_m[50] << 22) | (mask_m[51] << 20)
378 | (mask_m[52] << 18) | (mask_m[53] << 16)
379 | (mask_m[54] << 14) | (mask_m[55] << 12)
380 | (mask_m[56] << 10) | (mask_m[57] << 8)
381 | (mask_m[58] << 6) | (mask_m[59] << 4)
382 | (mask_m[60] << 2) | (mask_m[61] << 0);
383 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
384 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
385
386 tmp_mask = (mask_m[31] << 28)
387 | (mask_m[32] << 26) | (mask_m[33] << 24)
388 | (mask_m[34] << 22) | (mask_m[35] << 20)
389 | (mask_m[36] << 18) | (mask_m[37] << 16)
390 | (mask_m[48] << 14) | (mask_m[39] << 12)
391 | (mask_m[40] << 10) | (mask_m[41] << 8)
392 | (mask_m[42] << 6) | (mask_m[43] << 4)
393 | (mask_m[44] << 2) | (mask_m[45] << 0);
394 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
395 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
396
397 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
398 | (mask_m[18] << 26) | (mask_m[18] << 24)
399 | (mask_m[20] << 22) | (mask_m[20] << 20)
400 | (mask_m[22] << 18) | (mask_m[22] << 16)
401 | (mask_m[24] << 14) | (mask_m[24] << 12)
402 | (mask_m[25] << 10) | (mask_m[26] << 8)
403 | (mask_m[27] << 6) | (mask_m[28] << 4)
404 | (mask_m[29] << 2) | (mask_m[30] << 0);
405 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
406 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
407
408 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
409 | (mask_m[2] << 26) | (mask_m[3] << 24)
410 | (mask_m[4] << 22) | (mask_m[5] << 20)
411 | (mask_m[6] << 18) | (mask_m[7] << 16)
412 | (mask_m[8] << 14) | (mask_m[9] << 12)
413 | (mask_m[10] << 10) | (mask_m[11] << 8)
414 | (mask_m[12] << 6) | (mask_m[13] << 4)
415 | (mask_m[14] << 2) | (mask_m[15] << 0);
416 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
417 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
418
419 tmp_mask = (mask_p[15] << 28)
420 | (mask_p[14] << 26) | (mask_p[13] << 24)
421 | (mask_p[12] << 22) | (mask_p[11] << 20)
422 | (mask_p[10] << 18) | (mask_p[9] << 16)
423 | (mask_p[8] << 14) | (mask_p[7] << 12)
424 | (mask_p[6] << 10) | (mask_p[5] << 8)
425 | (mask_p[4] << 6) | (mask_p[3] << 4)
426 | (mask_p[2] << 2) | (mask_p[1] << 0);
427 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
428 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
429
430 tmp_mask = (mask_p[30] << 28)
431 | (mask_p[29] << 26) | (mask_p[28] << 24)
432 | (mask_p[27] << 22) | (mask_p[26] << 20)
433 | (mask_p[25] << 18) | (mask_p[24] << 16)
434 | (mask_p[23] << 14) | (mask_p[22] << 12)
435 | (mask_p[21] << 10) | (mask_p[20] << 8)
436 | (mask_p[19] << 6) | (mask_p[18] << 4)
437 | (mask_p[17] << 2) | (mask_p[16] << 0);
438 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
439 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
440
441 tmp_mask = (mask_p[45] << 28)
442 | (mask_p[44] << 26) | (mask_p[43] << 24)
443 | (mask_p[42] << 22) | (mask_p[41] << 20)
444 | (mask_p[40] << 18) | (mask_p[39] << 16)
445 | (mask_p[38] << 14) | (mask_p[37] << 12)
446 | (mask_p[36] << 10) | (mask_p[35] << 8)
447 | (mask_p[34] << 6) | (mask_p[33] << 4)
448 | (mask_p[32] << 2) | (mask_p[31] << 0);
449 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
450 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
451
452 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
453 | (mask_p[59] << 26) | (mask_p[58] << 24)
454 | (mask_p[57] << 22) | (mask_p[56] << 20)
455 | (mask_p[55] << 18) | (mask_p[54] << 16)
456 | (mask_p[53] << 14) | (mask_p[52] << 12)
457 | (mask_p[51] << 10) | (mask_p[50] << 8)
458 | (mask_p[49] << 6) | (mask_p[48] << 4)
459 | (mask_p[47] << 2) | (mask_p[46] << 0);
460 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
461 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
462}
463
464/**
465 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
466 * @ah: atheros hardware structure
467 *
468 * Only required for older devices with external AR2133/AR5133 radios.
469 */
470static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
471{
472#define ATH_ALLOC_BANK(bank, size) do { \
473 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
474 if (!bank) { \
475 ath_err(common, "Cannot allocate RF banks\n"); \
476 return -ENOMEM; \
477 } \
478 } while (0);
479
480 struct ath_common *common = ath9k_hw_common(ah);
481
482 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
483
484 ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
485 ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
486 ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
487 ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
488 ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
489 ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
490 ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
491 ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
492
493 return 0;
494#undef ATH_ALLOC_BANK
495}
496
497
498/**
499 * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
500 * @ah: atheros hardware struture
501 * For the external AR2133/AR5133 radios banks.
502 */
503static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
504{
505#define ATH_FREE_BANK(bank) do { \
506 kfree(bank); \
507 bank = NULL; \
508 } while (0);
509
510 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
511
512 ATH_FREE_BANK(ah->analogBank0Data);
513 ATH_FREE_BANK(ah->analogBank1Data);
514 ATH_FREE_BANK(ah->analogBank2Data);
515 ATH_FREE_BANK(ah->analogBank3Data);
516 ATH_FREE_BANK(ah->analogBank6Data);
517 ATH_FREE_BANK(ah->analogBank6TPCData);
518 ATH_FREE_BANK(ah->analogBank7Data);
519 ATH_FREE_BANK(ah->bank6Temp);
520
521#undef ATH_FREE_BANK
522}
523
524/* *
525 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
526 * @ah: atheros hardware structure
527 * @chan:
528 * @modesIndex:
529 *
530 * Used for the external AR2133/AR5133 radios.
531 *
532 * Reads the EEPROM header info from the device structure and programs
533 * all rf registers. This routine requires access to the analog
534 * rf device. This is not required for single-chip devices.
535 */
536static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
537 struct ath9k_channel *chan,
538 u16 modesIndex)
539{
540 u32 eepMinorRev;
541 u32 ob5GHz = 0, db5GHz = 0;
542 u32 ob2GHz = 0, db2GHz = 0;
543 int regWrites = 0;
544
545 /*
546 * Software does not need to program bank data
547 * for single chip devices, that is AR9280 or anything
548 * after that.
549 */
550 if (AR_SREV_9280_20_OR_LATER(ah))
551 return true;
552
553 /* Setup rf parameters */
554 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
555
556 /* Setup Bank 0 Write */
557 ar5008_rf_bank_setup(ah->analogBank0Data, &ah->iniBank0, 1);
558
559 /* Setup Bank 1 Write */
560 ar5008_rf_bank_setup(ah->analogBank1Data, &ah->iniBank1, 1);
561
562 /* Setup Bank 2 Write */
563 ar5008_rf_bank_setup(ah->analogBank2Data, &ah->iniBank2, 1);
564
565 /* Setup Bank 6 Write */
566 ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3,
567 modesIndex);
568 {
569 int i;
570 for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
571 ah->analogBank6Data[i] =
572 INI_RA(&ah->iniBank6TPC, i, modesIndex);
573 }
574 }
575
576 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
577 if (eepMinorRev >= 2) {
578 if (IS_CHAN_2GHZ(chan)) {
579 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
580 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
581 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
582 ob2GHz, 3, 197, 0);
583 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
584 db2GHz, 3, 194, 0);
585 } else {
586 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
587 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
588 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
589 ob5GHz, 3, 203, 0);
590 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
591 db5GHz, 3, 200, 0);
592 }
593 }
594
595 /* Setup Bank 7 Setup */
596 ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1);
597
598 /* Write Analog registers */
599 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
600 regWrites);
601 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
602 regWrites);
603 REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
604 regWrites);
605 REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
606 regWrites);
607 REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
608 regWrites);
609 REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
610 regWrites);
611
612 return true;
613}
614
615static void ar5008_hw_init_bb(struct ath_hw *ah,
616 struct ath9k_channel *chan)
617{
618 u32 synthDelay;
619
620 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
621
622 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
623
624 ath9k_hw_synth_delay(ah, chan, synthDelay);
625}
626
627static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
628{
629 int rx_chainmask, tx_chainmask;
630
631 rx_chainmask = ah->rxchainmask;
632 tx_chainmask = ah->txchainmask;
633
634
635 switch (rx_chainmask) {
636 case 0x5:
637 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
638 AR_PHY_SWAP_ALT_CHAIN);
639 case 0x3:
640 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
641 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
642 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
643 break;
644 }
645 case 0x1:
646 case 0x2:
647 case 0x7:
648 ENABLE_REGWRITE_BUFFER(ah);
649 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
650 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
651 break;
652 default:
653 ENABLE_REGWRITE_BUFFER(ah);
654 break;
655 }
656
657 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
658
659 REGWRITE_BUFFER_FLUSH(ah);
660
661 if (tx_chainmask == 0x5) {
662 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
663 AR_PHY_SWAP_ALT_CHAIN);
664 }
665 if (AR_SREV_9100(ah))
666 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
667 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
668}
669
670static void ar5008_hw_override_ini(struct ath_hw *ah,
671 struct ath9k_channel *chan)
672{
673 u32 val;
674
675 /*
676 * Set the RX_ABORT and RX_DIS and clear if off only after
677 * RXE is set for MAC. This prevents frames with corrupted
678 * descriptor status.
679 */
680 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
681
682 if (AR_SREV_9280_20_OR_LATER(ah)) {
683 val = REG_READ(ah, AR_PCU_MISC_MODE2);
684
685 if (!AR_SREV_9271(ah))
686 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
687
688 if (AR_SREV_9287_11_OR_LATER(ah))
689 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
690
691 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
692 }
693
694 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
695 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
696
697 if (AR_SREV_9280_20_OR_LATER(ah))
698 return;
699 /*
700 * Disable BB clock gating
701 * Necessary to avoid issues on AR5416 2.0
702 */
703 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
704
705 /*
706 * Disable RIFS search on some chips to avoid baseband
707 * hang issues.
708 */
709 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
710 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
711 val &= ~AR_PHY_RIFS_INIT_DELAY;
712 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
713 }
714}
715
716static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
717 struct ath9k_channel *chan)
718{
719 u32 phymode;
720 u32 enableDacFifo = 0;
721
722 if (AR_SREV_9285_12_OR_LATER(ah))
723 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
724 AR_PHY_FC_ENABLE_DAC_FIFO);
725
726 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
727 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
728
729 if (IS_CHAN_HT40(chan)) {
730 phymode |= AR_PHY_FC_DYN2040_EN;
731
732 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
733 (chan->chanmode == CHANNEL_G_HT40PLUS))
734 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
735
736 }
737 REG_WRITE(ah, AR_PHY_TURBO, phymode);
738
739 ath9k_hw_set11nmac2040(ah);
740
741 ENABLE_REGWRITE_BUFFER(ah);
742
743 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
744 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
745
746 REGWRITE_BUFFER_FLUSH(ah);
747}
748
749
750static int ar5008_hw_process_ini(struct ath_hw *ah,
751 struct ath9k_channel *chan)
752{
753 struct ath_common *common = ath9k_hw_common(ah);
754 int i, regWrites = 0;
755 u32 modesIndex, freqIndex;
756
757 switch (chan->chanmode) {
758 case CHANNEL_A:
759 case CHANNEL_A_HT20:
760 modesIndex = 1;
761 freqIndex = 1;
762 break;
763 case CHANNEL_A_HT40PLUS:
764 case CHANNEL_A_HT40MINUS:
765 modesIndex = 2;
766 freqIndex = 1;
767 break;
768 case CHANNEL_G:
769 case CHANNEL_G_HT20:
770 case CHANNEL_B:
771 modesIndex = 4;
772 freqIndex = 2;
773 break;
774 case CHANNEL_G_HT40PLUS:
775 case CHANNEL_G_HT40MINUS:
776 modesIndex = 3;
777 freqIndex = 2;
778 break;
779
780 default:
781 return -EINVAL;
782 }
783
784 /*
785 * Set correct baseband to analog shift setting to
786 * access analog chips.
787 */
788 REG_WRITE(ah, AR_PHY(0), 0x00000007);
789
790 /* Write ADDAC shifts */
791 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
792 if (ah->eep_ops->set_addac)
793 ah->eep_ops->set_addac(ah, chan);
794
795 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
796 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
797
798 ENABLE_REGWRITE_BUFFER(ah);
799
800 for (i = 0; i < ah->iniModes.ia_rows; i++) {
801 u32 reg = INI_RA(&ah->iniModes, i, 0);
802 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
803
804 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
805 val &= ~AR_AN_TOP2_PWDCLKIND;
806
807 REG_WRITE(ah, reg, val);
808
809 if (reg >= 0x7800 && reg < 0x78a0
810 && ah->config.analog_shiftreg
811 && (common->bus_ops->ath_bus_type != ATH_USB)) {
812 udelay(100);
813 }
814
815 DO_DELAY(regWrites);
816 }
817
818 REGWRITE_BUFFER_FLUSH(ah);
819
820 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah))
821 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
822
823 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
824 AR_SREV_9287_11_OR_LATER(ah))
825 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
826
827 if (AR_SREV_9271_10(ah)) {
828 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA);
829 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_ADC_ON, 0xa);
830 }
831
832 ENABLE_REGWRITE_BUFFER(ah);
833
834 /* Write common array parameters */
835 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
836 u32 reg = INI_RA(&ah->iniCommon, i, 0);
837 u32 val = INI_RA(&ah->iniCommon, i, 1);
838
839 REG_WRITE(ah, reg, val);
840
841 if (reg >= 0x7800 && reg < 0x78a0
842 && ah->config.analog_shiftreg
843 && (common->bus_ops->ath_bus_type != ATH_USB)) {
844 udelay(100);
845 }
846
847 DO_DELAY(regWrites);
848 }
849
850 REGWRITE_BUFFER_FLUSH(ah);
851
852 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
853
854 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
855 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex,
856 regWrites);
857
858 ar5008_hw_override_ini(ah, chan);
859 ar5008_hw_set_channel_regs(ah, chan);
860 ar5008_hw_init_chain_masks(ah);
861 ath9k_olc_init(ah);
862 ath9k_hw_apply_txpower(ah, chan, false);
863
864 /* Write analog registers */
865 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
866 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n");
867 return -EIO;
868 }
869
870 return 0;
871}
872
873static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
874{
875 u32 rfMode = 0;
876
877 if (chan == NULL)
878 return;
879
880 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
881 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
882
883 if (!AR_SREV_9280_20_OR_LATER(ah))
884 rfMode |= (IS_CHAN_5GHZ(chan)) ?
885 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
886
887 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
888 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
889
890 REG_WRITE(ah, AR_PHY_MODE, rfMode);
891}
892
893static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
894{
895 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
896}
897
898static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
899 struct ath9k_channel *chan)
900{
901 u32 coef_scaled, ds_coef_exp, ds_coef_man;
902 u32 clockMhzScaled = 0x64000000;
903 struct chan_centers centers;
904
905 if (IS_CHAN_HALF_RATE(chan))
906 clockMhzScaled = clockMhzScaled >> 1;
907 else if (IS_CHAN_QUARTER_RATE(chan))
908 clockMhzScaled = clockMhzScaled >> 2;
909
910 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
911 coef_scaled = clockMhzScaled / centers.synth_center;
912
913 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
914 &ds_coef_exp);
915
916 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
917 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
918 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
919 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
920
921 coef_scaled = (9 * coef_scaled) / 10;
922
923 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
924 &ds_coef_exp);
925
926 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
927 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
928 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
929 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
930}
931
932static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
933{
934 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
935 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
936 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
937}
938
939static void ar5008_hw_rfbus_done(struct ath_hw *ah)
940{
941 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
942
943 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
944
945 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
946}
947
948static void ar5008_restore_chainmask(struct ath_hw *ah)
949{
950 int rx_chainmask = ah->rxchainmask;
951
952 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
953 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
954 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
955 }
956}
957
958static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
959 struct ath9k_channel *chan)
960{
961 u32 pll;
962
963 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
964
965 if (chan && IS_CHAN_HALF_RATE(chan))
966 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
967 else if (chan && IS_CHAN_QUARTER_RATE(chan))
968 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
969
970 if (chan && IS_CHAN_5GHZ(chan))
971 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
972 else
973 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
974
975 return pll;
976}
977
978static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
979 struct ath9k_channel *chan)
980{
981 u32 pll;
982
983 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
984
985 if (chan && IS_CHAN_HALF_RATE(chan))
986 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
987 else if (chan && IS_CHAN_QUARTER_RATE(chan))
988 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
989
990 if (chan && IS_CHAN_5GHZ(chan))
991 pll |= SM(0xa, AR_RTC_PLL_DIV);
992 else
993 pll |= SM(0xb, AR_RTC_PLL_DIV);
994
995 return pll;
996}
997
998static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
999 enum ath9k_ani_cmd cmd,
1000 int param)
1001{
1002 struct ar5416AniState *aniState = &ah->curchan->ani;
1003 struct ath_common *common = ath9k_hw_common(ah);
1004
1005 switch (cmd & ah->ani_function) {
1006 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
1007 u32 level = param;
1008
1009 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
1010 ath_dbg(common, ANI, "level out of range (%u > %zu)\n",
1011 level, ARRAY_SIZE(ah->totalSizeDesired));
1012 return false;
1013 }
1014
1015 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1016 AR_PHY_DESIRED_SZ_TOT_DES,
1017 ah->totalSizeDesired[level]);
1018 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1019 AR_PHY_AGC_CTL1_COARSE_LOW,
1020 ah->coarse_low[level]);
1021 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1022 AR_PHY_AGC_CTL1_COARSE_HIGH,
1023 ah->coarse_high[level]);
1024 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1025 AR_PHY_FIND_SIG_FIRPWR,
1026 ah->firpwr[level]);
1027
1028 if (level > aniState->noiseImmunityLevel)
1029 ah->stats.ast_ani_niup++;
1030 else if (level < aniState->noiseImmunityLevel)
1031 ah->stats.ast_ani_nidown++;
1032 aniState->noiseImmunityLevel = level;
1033 break;
1034 }
1035 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1036 u32 on = param ? 1 : 0;
1037
1038 if (on)
1039 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1040 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1041 else
1042 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1043 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1044
1045 if (!on != aniState->ofdmWeakSigDetectOff) {
1046 if (on)
1047 ah->stats.ast_ani_ofdmon++;
1048 else
1049 ah->stats.ast_ani_ofdmoff++;
1050 aniState->ofdmWeakSigDetectOff = !on;
1051 }
1052 break;
1053 }
1054 case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
1055 static const int weakSigThrCck[] = { 8, 6 };
1056 u32 high = param ? 1 : 0;
1057
1058 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
1059 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
1060 weakSigThrCck[high]);
1061 if (high != aniState->cckWeakSigThreshold) {
1062 if (high)
1063 ah->stats.ast_ani_cckhigh++;
1064 else
1065 ah->stats.ast_ani_ccklow++;
1066 aniState->cckWeakSigThreshold = high;
1067 }
1068 break;
1069 }
1070 case ATH9K_ANI_FIRSTEP_LEVEL:{
1071 static const int firstep[] = { 0, 4, 8 };
1072 u32 level = param;
1073
1074 if (level >= ARRAY_SIZE(firstep)) {
1075 ath_dbg(common, ANI, "level out of range (%u > %zu)\n",
1076 level, ARRAY_SIZE(firstep));
1077 return false;
1078 }
1079 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1080 AR_PHY_FIND_SIG_FIRSTEP,
1081 firstep[level]);
1082 if (level > aniState->firstepLevel)
1083 ah->stats.ast_ani_stepup++;
1084 else if (level < aniState->firstepLevel)
1085 ah->stats.ast_ani_stepdown++;
1086 aniState->firstepLevel = level;
1087 break;
1088 }
1089 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1090 static const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
1091 u32 level = param;
1092
1093 if (level >= ARRAY_SIZE(cycpwrThr1)) {
1094 ath_dbg(common, ANI, "level out of range (%u > %zu)\n",
1095 level, ARRAY_SIZE(cycpwrThr1));
1096 return false;
1097 }
1098 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1099 AR_PHY_TIMING5_CYCPWR_THR1,
1100 cycpwrThr1[level]);
1101 if (level > aniState->spurImmunityLevel)
1102 ah->stats.ast_ani_spurup++;
1103 else if (level < aniState->spurImmunityLevel)
1104 ah->stats.ast_ani_spurdown++;
1105 aniState->spurImmunityLevel = level;
1106 break;
1107 }
1108 case ATH9K_ANI_PRESENT:
1109 break;
1110 default:
1111 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1112 return false;
1113 }
1114
1115 ath_dbg(common, ANI, "ANI parameters:\n");
1116 ath_dbg(common, ANI,
1117 "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetectOff=%d\n",
1118 aniState->noiseImmunityLevel,
1119 aniState->spurImmunityLevel,
1120 !aniState->ofdmWeakSigDetectOff);
1121 ath_dbg(common, ANI,
1122 "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n",
1123 aniState->cckWeakSigThreshold,
1124 aniState->firstepLevel,
1125 aniState->listenTime);
1126 ath_dbg(common, ANI, "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
1127 aniState->ofdmPhyErrCount,
1128 aniState->cckPhyErrCount);
1129
1130 return true;
1131}
1132
1133static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1134 enum ath9k_ani_cmd cmd,
1135 int param)
1136{
1137 struct ath_common *common = ath9k_hw_common(ah);
1138 struct ath9k_channel *chan = ah->curchan;
1139 struct ar5416AniState *aniState = &chan->ani;
1140 s32 value, value2;
1141
1142 switch (cmd & ah->ani_function) {
1143 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1144 /*
1145 * on == 1 means ofdm weak signal detection is ON
1146 * on == 1 is the default, for less noise immunity
1147 *
1148 * on == 0 means ofdm weak signal detection is OFF
1149 * on == 0 means more noise imm
1150 */
1151 u32 on = param ? 1 : 0;
1152 /*
1153 * make register setting for default
1154 * (weak sig detect ON) come from INI file
1155 */
1156 int m1ThreshLow = on ?
1157 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
1158 int m2ThreshLow = on ?
1159 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
1160 int m1Thresh = on ?
1161 aniState->iniDef.m1Thresh : m1Thresh_off;
1162 int m2Thresh = on ?
1163 aniState->iniDef.m2Thresh : m2Thresh_off;
1164 int m2CountThr = on ?
1165 aniState->iniDef.m2CountThr : m2CountThr_off;
1166 int m2CountThrLow = on ?
1167 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
1168 int m1ThreshLowExt = on ?
1169 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
1170 int m2ThreshLowExt = on ?
1171 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
1172 int m1ThreshExt = on ?
1173 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
1174 int m2ThreshExt = on ?
1175 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
1176
1177 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1178 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1179 m1ThreshLow);
1180 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1181 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1182 m2ThreshLow);
1183 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1184 AR_PHY_SFCORR_M1_THRESH, m1Thresh);
1185 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1186 AR_PHY_SFCORR_M2_THRESH, m2Thresh);
1187 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1188 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
1189 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1190 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1191 m2CountThrLow);
1192
1193 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1194 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
1195 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1196 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
1197 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1198 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
1199 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1200 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
1201
1202 if (on)
1203 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1204 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1205 else
1206 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1207 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1208
1209 if (!on != aniState->ofdmWeakSigDetectOff) {
1210 ath_dbg(common, ANI,
1211 "** ch %d: ofdm weak signal: %s=>%s\n",
1212 chan->channel,
1213 !aniState->ofdmWeakSigDetectOff ?
1214 "on" : "off",
1215 on ? "on" : "off");
1216 if (on)
1217 ah->stats.ast_ani_ofdmon++;
1218 else
1219 ah->stats.ast_ani_ofdmoff++;
1220 aniState->ofdmWeakSigDetectOff = !on;
1221 }
1222 break;
1223 }
1224 case ATH9K_ANI_FIRSTEP_LEVEL:{
1225 u32 level = param;
1226
1227 if (level >= ARRAY_SIZE(firstep_table)) {
1228 ath_dbg(common, ANI,
1229 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1230 level, ARRAY_SIZE(firstep_table));
1231 return false;
1232 }
1233
1234 /*
1235 * make register setting relative to default
1236 * from INI file & cap value
1237 */
1238 value = firstep_table[level] -
1239 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
1240 aniState->iniDef.firstep;
1241 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1242 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1243 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1244 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1245 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1246 AR_PHY_FIND_SIG_FIRSTEP,
1247 value);
1248 /*
1249 * we need to set first step low register too
1250 * make register setting relative to default
1251 * from INI file & cap value
1252 */
1253 value2 = firstep_table[level] -
1254 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
1255 aniState->iniDef.firstepLow;
1256 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1257 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1258 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1259 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1260
1261 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1262 AR_PHY_FIND_SIG_FIRSTEP_LOW, value2);
1263
1264 if (level != aniState->firstepLevel) {
1265 ath_dbg(common, ANI,
1266 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1267 chan->channel,
1268 aniState->firstepLevel,
1269 level,
1270 ATH9K_ANI_FIRSTEP_LVL_NEW,
1271 value,
1272 aniState->iniDef.firstep);
1273 ath_dbg(common, ANI,
1274 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1275 chan->channel,
1276 aniState->firstepLevel,
1277 level,
1278 ATH9K_ANI_FIRSTEP_LVL_NEW,
1279 value2,
1280 aniState->iniDef.firstepLow);
1281 if (level > aniState->firstepLevel)
1282 ah->stats.ast_ani_stepup++;
1283 else if (level < aniState->firstepLevel)
1284 ah->stats.ast_ani_stepdown++;
1285 aniState->firstepLevel = level;
1286 }
1287 break;
1288 }
1289 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1290 u32 level = param;
1291
1292 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1293 ath_dbg(common, ANI,
1294 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1295 level, ARRAY_SIZE(cycpwrThr1_table));
1296 return false;
1297 }
1298 /*
1299 * make register setting relative to default
1300 * from INI file & cap value
1301 */
1302 value = cycpwrThr1_table[level] -
1303 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
1304 aniState->iniDef.cycpwrThr1;
1305 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1306 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1307 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1308 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1309 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1310 AR_PHY_TIMING5_CYCPWR_THR1,
1311 value);
1312
1313 /*
1314 * set AR_PHY_EXT_CCA for extension channel
1315 * make register setting relative to default
1316 * from INI file & cap value
1317 */
1318 value2 = cycpwrThr1_table[level] -
1319 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
1320 aniState->iniDef.cycpwrThr1Ext;
1321 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1322 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1323 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1324 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1325 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1326 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2);
1327
1328 if (level != aniState->spurImmunityLevel) {
1329 ath_dbg(common, ANI,
1330 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1331 chan->channel,
1332 aniState->spurImmunityLevel,
1333 level,
1334 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1335 value,
1336 aniState->iniDef.cycpwrThr1);
1337 ath_dbg(common, ANI,
1338 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1339 chan->channel,
1340 aniState->spurImmunityLevel,
1341 level,
1342 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1343 value2,
1344 aniState->iniDef.cycpwrThr1Ext);
1345 if (level > aniState->spurImmunityLevel)
1346 ah->stats.ast_ani_spurup++;
1347 else if (level < aniState->spurImmunityLevel)
1348 ah->stats.ast_ani_spurdown++;
1349 aniState->spurImmunityLevel = level;
1350 }
1351 break;
1352 }
1353 case ATH9K_ANI_MRC_CCK:
1354 /*
1355 * You should not see this as AR5008, AR9001, AR9002
1356 * does not have hardware support for MRC CCK.
1357 */
1358 WARN_ON(1);
1359 break;
1360 case ATH9K_ANI_PRESENT:
1361 break;
1362 default:
1363 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1364 return false;
1365 }
1366
1367 ath_dbg(common, ANI,
1368 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1369 aniState->spurImmunityLevel,
1370 !aniState->ofdmWeakSigDetectOff ? "on" : "off",
1371 aniState->firstepLevel,
1372 !aniState->mrcCCKOff ? "on" : "off",
1373 aniState->listenTime,
1374 aniState->ofdmPhyErrCount,
1375 aniState->cckPhyErrCount);
1376 return true;
1377}
1378
1379static void ar5008_hw_do_getnf(struct ath_hw *ah,
1380 int16_t nfarray[NUM_NF_READINGS])
1381{
1382 int16_t nf;
1383
1384 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
1385 nfarray[0] = sign_extend32(nf, 8);
1386
1387 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
1388 nfarray[1] = sign_extend32(nf, 8);
1389
1390 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
1391 nfarray[2] = sign_extend32(nf, 8);
1392
1393 if (!IS_CHAN_HT40(ah->curchan))
1394 return;
1395
1396 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
1397 nfarray[3] = sign_extend32(nf, 8);
1398
1399 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
1400 nfarray[4] = sign_extend32(nf, 8);
1401
1402 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
1403 nfarray[5] = sign_extend32(nf, 8);
1404}
1405
1406/*
1407 * Initialize the ANI register values with default (ini) values.
1408 * This routine is called during a (full) hardware reset after
1409 * all the registers are initialised from the INI.
1410 */
1411static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
1412{
1413 struct ath_common *common = ath9k_hw_common(ah);
1414 struct ath9k_channel *chan = ah->curchan;
1415 struct ar5416AniState *aniState = &chan->ani;
1416 struct ath9k_ani_default *iniDef;
1417 u32 val;
1418
1419 iniDef = &aniState->iniDef;
1420
1421 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1422 ah->hw_version.macVersion,
1423 ah->hw_version.macRev,
1424 ah->opmode,
1425 chan->channel,
1426 chan->channelFlags);
1427
1428 val = REG_READ(ah, AR_PHY_SFCORR);
1429 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1430 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1431 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1432
1433 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1434 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1435 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1436 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1437
1438 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1439 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1440 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1441 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1442 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1443 iniDef->firstep = REG_READ_FIELD(ah,
1444 AR_PHY_FIND_SIG,
1445 AR_PHY_FIND_SIG_FIRSTEP);
1446 iniDef->firstepLow = REG_READ_FIELD(ah,
1447 AR_PHY_FIND_SIG_LOW,
1448 AR_PHY_FIND_SIG_FIRSTEP_LOW);
1449 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1450 AR_PHY_TIMING5,
1451 AR_PHY_TIMING5_CYCPWR_THR1);
1452 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1453 AR_PHY_EXT_CCA,
1454 AR_PHY_EXT_TIMING5_CYCPWR_THR1);
1455
1456 /* these levels just got reset to defaults by the INI */
1457 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1458 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1459 aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
1460 aniState->mrcCCKOff = true; /* not available on pre AR9003 */
1461}
1462
1463static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
1464{
1465 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
1466 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
1467 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
1468 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
1469 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
1470 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
1471}
1472
1473static void ar5008_hw_set_radar_params(struct ath_hw *ah,
1474 struct ath_hw_radar_conf *conf)
1475{
1476 u32 radar_0 = 0, radar_1 = 0;
1477
1478 if (!conf) {
1479 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1480 return;
1481 }
1482
1483 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1484 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1485 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1486 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1487 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1488 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1489
1490 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1491 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1492 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1493 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1494 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1495
1496 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1497 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1498 if (conf->ext_channel)
1499 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1500 else
1501 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1502}
1503
1504static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
1505{
1506 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1507
1508 conf->fir_power = -33;
1509 conf->radar_rssi = 20;
1510 conf->pulse_height = 10;
1511 conf->pulse_rssi = 24;
1512 conf->pulse_inband = 15;
1513 conf->pulse_maxlen = 255;
1514 conf->pulse_inband_step = 12;
1515 conf->radar_inband = 8;
1516}
1517
1518void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
1519{
1520 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1521 static const u32 ar5416_cca_regs[6] = {
1522 AR_PHY_CCA,
1523 AR_PHY_CH1_CCA,
1524 AR_PHY_CH2_CCA,
1525 AR_PHY_EXT_CCA,
1526 AR_PHY_CH1_EXT_CCA,
1527 AR_PHY_CH2_EXT_CCA
1528 };
1529
1530 priv_ops->rf_set_freq = ar5008_hw_set_channel;
1531 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
1532
1533 priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks;
1534 priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks;
1535 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
1536 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
1537 priv_ops->init_bb = ar5008_hw_init_bb;
1538 priv_ops->process_ini = ar5008_hw_process_ini;
1539 priv_ops->set_rfmode = ar5008_hw_set_rfmode;
1540 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
1541 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
1542 priv_ops->rfbus_req = ar5008_hw_rfbus_req;
1543 priv_ops->rfbus_done = ar5008_hw_rfbus_done;
1544 priv_ops->restore_chainmask = ar5008_restore_chainmask;
1545 priv_ops->do_getnf = ar5008_hw_do_getnf;
1546 priv_ops->set_radar_params = ar5008_hw_set_radar_params;
1547
1548 if (modparam_force_new_ani) {
1549 priv_ops->ani_control = ar5008_hw_ani_control_new;
1550 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs;
1551 } else
1552 priv_ops->ani_control = ar5008_hw_ani_control_old;
1553
1554 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
1555 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
1556 else
1557 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
1558
1559 ar5008_hw_set_nf_limits(ah);
1560 ar5008_hw_set_radar_conf(ah);
1561 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
1562}