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1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30#include "drmP.h"
31#include "drm.h"
32#include "i915_drv.h"
33#include "i915_drm.h"
34#include "i915_trace.h"
35#include "intel_drv.h"
36
37static inline int ring_space(struct intel_ring_buffer *ring)
38{
39 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
40 if (space < 0)
41 space += ring->size;
42 return space;
43}
44
45static u32 i915_gem_get_seqno(struct drm_device *dev)
46{
47 drm_i915_private_t *dev_priv = dev->dev_private;
48 u32 seqno;
49
50 seqno = dev_priv->next_seqno;
51
52 /* reserve 0 for non-seqno */
53 if (++dev_priv->next_seqno == 0)
54 dev_priv->next_seqno = 1;
55
56 return seqno;
57}
58
59static int
60render_ring_flush(struct intel_ring_buffer *ring,
61 u32 invalidate_domains,
62 u32 flush_domains)
63{
64 struct drm_device *dev = ring->dev;
65 u32 cmd;
66 int ret;
67
68 /*
69 * read/write caches:
70 *
71 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
72 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
73 * also flushed at 2d versus 3d pipeline switches.
74 *
75 * read-only caches:
76 *
77 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
78 * MI_READ_FLUSH is set, and is always flushed on 965.
79 *
80 * I915_GEM_DOMAIN_COMMAND may not exist?
81 *
82 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
83 * invalidated when MI_EXE_FLUSH is set.
84 *
85 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
86 * invalidated with every MI_FLUSH.
87 *
88 * TLBs:
89 *
90 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
91 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
92 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
93 * are flushed at any MI_FLUSH.
94 */
95
96 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
97 if ((invalidate_domains|flush_domains) &
98 I915_GEM_DOMAIN_RENDER)
99 cmd &= ~MI_NO_WRITE_FLUSH;
100 if (INTEL_INFO(dev)->gen < 4) {
101 /*
102 * On the 965, the sampler cache always gets flushed
103 * and this bit is reserved.
104 */
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
107 }
108 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
109 cmd |= MI_EXE_FLUSH;
110
111 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
112 (IS_G4X(dev) || IS_GEN5(dev)))
113 cmd |= MI_INVALIDATE_ISP;
114
115 ret = intel_ring_begin(ring, 2);
116 if (ret)
117 return ret;
118
119 intel_ring_emit(ring, cmd);
120 intel_ring_emit(ring, MI_NOOP);
121 intel_ring_advance(ring);
122
123 return 0;
124}
125
126static void ring_write_tail(struct intel_ring_buffer *ring,
127 u32 value)
128{
129 drm_i915_private_t *dev_priv = ring->dev->dev_private;
130 I915_WRITE_TAIL(ring, value);
131}
132
133u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
134{
135 drm_i915_private_t *dev_priv = ring->dev->dev_private;
136 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
137 RING_ACTHD(ring->mmio_base) : ACTHD;
138
139 return I915_READ(acthd_reg);
140}
141
142static int init_ring_common(struct intel_ring_buffer *ring)
143{
144 drm_i915_private_t *dev_priv = ring->dev->dev_private;
145 struct drm_i915_gem_object *obj = ring->obj;
146 u32 head;
147
148 /* Stop the ring if it's running. */
149 I915_WRITE_CTL(ring, 0);
150 I915_WRITE_HEAD(ring, 0);
151 ring->write_tail(ring, 0);
152
153 /* Initialize the ring. */
154 I915_WRITE_START(ring, obj->gtt_offset);
155 head = I915_READ_HEAD(ring) & HEAD_ADDR;
156
157 /* G45 ring initialization fails to reset head to zero */
158 if (head != 0) {
159 DRM_DEBUG_KMS("%s head not reset to zero "
160 "ctl %08x head %08x tail %08x start %08x\n",
161 ring->name,
162 I915_READ_CTL(ring),
163 I915_READ_HEAD(ring),
164 I915_READ_TAIL(ring),
165 I915_READ_START(ring));
166
167 I915_WRITE_HEAD(ring, 0);
168
169 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
170 DRM_ERROR("failed to set %s head to zero "
171 "ctl %08x head %08x tail %08x start %08x\n",
172 ring->name,
173 I915_READ_CTL(ring),
174 I915_READ_HEAD(ring),
175 I915_READ_TAIL(ring),
176 I915_READ_START(ring));
177 }
178 }
179
180 I915_WRITE_CTL(ring,
181 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
182 | RING_REPORT_64K | RING_VALID);
183
184 /* If the head is still not zero, the ring is dead */
185 if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
186 I915_READ_START(ring) != obj->gtt_offset ||
187 (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
188 DRM_ERROR("%s initialization failed "
189 "ctl %08x head %08x tail %08x start %08x\n",
190 ring->name,
191 I915_READ_CTL(ring),
192 I915_READ_HEAD(ring),
193 I915_READ_TAIL(ring),
194 I915_READ_START(ring));
195 return -EIO;
196 }
197
198 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
199 i915_kernel_lost_context(ring->dev);
200 else {
201 ring->head = I915_READ_HEAD(ring);
202 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
203 ring->space = ring_space(ring);
204 }
205
206 return 0;
207}
208
209/*
210 * 965+ support PIPE_CONTROL commands, which provide finer grained control
211 * over cache flushing.
212 */
213struct pipe_control {
214 struct drm_i915_gem_object *obj;
215 volatile u32 *cpu_page;
216 u32 gtt_offset;
217};
218
219static int
220init_pipe_control(struct intel_ring_buffer *ring)
221{
222 struct pipe_control *pc;
223 struct drm_i915_gem_object *obj;
224 int ret;
225
226 if (ring->private)
227 return 0;
228
229 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
230 if (!pc)
231 return -ENOMEM;
232
233 obj = i915_gem_alloc_object(ring->dev, 4096);
234 if (obj == NULL) {
235 DRM_ERROR("Failed to allocate seqno page\n");
236 ret = -ENOMEM;
237 goto err;
238 }
239
240 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
241
242 ret = i915_gem_object_pin(obj, 4096, true);
243 if (ret)
244 goto err_unref;
245
246 pc->gtt_offset = obj->gtt_offset;
247 pc->cpu_page = kmap(obj->pages[0]);
248 if (pc->cpu_page == NULL)
249 goto err_unpin;
250
251 pc->obj = obj;
252 ring->private = pc;
253 return 0;
254
255err_unpin:
256 i915_gem_object_unpin(obj);
257err_unref:
258 drm_gem_object_unreference(&obj->base);
259err:
260 kfree(pc);
261 return ret;
262}
263
264static void
265cleanup_pipe_control(struct intel_ring_buffer *ring)
266{
267 struct pipe_control *pc = ring->private;
268 struct drm_i915_gem_object *obj;
269
270 if (!ring->private)
271 return;
272
273 obj = pc->obj;
274 kunmap(obj->pages[0]);
275 i915_gem_object_unpin(obj);
276 drm_gem_object_unreference(&obj->base);
277
278 kfree(pc);
279 ring->private = NULL;
280}
281
282static int init_render_ring(struct intel_ring_buffer *ring)
283{
284 struct drm_device *dev = ring->dev;
285 struct drm_i915_private *dev_priv = dev->dev_private;
286 int ret = init_ring_common(ring);
287
288 if (INTEL_INFO(dev)->gen > 3) {
289 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
290 if (IS_GEN6(dev) || IS_GEN7(dev))
291 mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
292 I915_WRITE(MI_MODE, mode);
293 if (IS_GEN7(dev))
294 I915_WRITE(GFX_MODE_GEN7,
295 GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
296 GFX_MODE_ENABLE(GFX_REPLAY_MODE));
297 }
298
299 if (INTEL_INFO(dev)->gen >= 6) {
300 } else if (IS_GEN5(dev)) {
301 ret = init_pipe_control(ring);
302 if (ret)
303 return ret;
304 }
305
306 return ret;
307}
308
309static void render_ring_cleanup(struct intel_ring_buffer *ring)
310{
311 if (!ring->private)
312 return;
313
314 cleanup_pipe_control(ring);
315}
316
317static void
318update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno)
319{
320 struct drm_device *dev = ring->dev;
321 struct drm_i915_private *dev_priv = dev->dev_private;
322 int id;
323
324 /*
325 * cs -> 1 = vcs, 0 = bcs
326 * vcs -> 1 = bcs, 0 = cs,
327 * bcs -> 1 = cs, 0 = vcs.
328 */
329 id = ring - dev_priv->ring;
330 id += 2 - i;
331 id %= 3;
332
333 intel_ring_emit(ring,
334 MI_SEMAPHORE_MBOX |
335 MI_SEMAPHORE_REGISTER |
336 MI_SEMAPHORE_UPDATE);
337 intel_ring_emit(ring, seqno);
338 intel_ring_emit(ring,
339 RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i);
340}
341
342static int
343gen6_add_request(struct intel_ring_buffer *ring,
344 u32 *result)
345{
346 u32 seqno;
347 int ret;
348
349 ret = intel_ring_begin(ring, 10);
350 if (ret)
351 return ret;
352
353 seqno = i915_gem_get_seqno(ring->dev);
354 update_semaphore(ring, 0, seqno);
355 update_semaphore(ring, 1, seqno);
356
357 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
358 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
359 intel_ring_emit(ring, seqno);
360 intel_ring_emit(ring, MI_USER_INTERRUPT);
361 intel_ring_advance(ring);
362
363 *result = seqno;
364 return 0;
365}
366
367int
368intel_ring_sync(struct intel_ring_buffer *ring,
369 struct intel_ring_buffer *to,
370 u32 seqno)
371{
372 int ret;
373
374 ret = intel_ring_begin(ring, 4);
375 if (ret)
376 return ret;
377
378 intel_ring_emit(ring,
379 MI_SEMAPHORE_MBOX |
380 MI_SEMAPHORE_REGISTER |
381 intel_ring_sync_index(ring, to) << 17 |
382 MI_SEMAPHORE_COMPARE);
383 intel_ring_emit(ring, seqno);
384 intel_ring_emit(ring, 0);
385 intel_ring_emit(ring, MI_NOOP);
386 intel_ring_advance(ring);
387
388 return 0;
389}
390
391#define PIPE_CONTROL_FLUSH(ring__, addr__) \
392do { \
393 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
394 PIPE_CONTROL_DEPTH_STALL | 2); \
395 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
396 intel_ring_emit(ring__, 0); \
397 intel_ring_emit(ring__, 0); \
398} while (0)
399
400static int
401pc_render_add_request(struct intel_ring_buffer *ring,
402 u32 *result)
403{
404 struct drm_device *dev = ring->dev;
405 u32 seqno = i915_gem_get_seqno(dev);
406 struct pipe_control *pc = ring->private;
407 u32 scratch_addr = pc->gtt_offset + 128;
408 int ret;
409
410 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
411 * incoherent with writes to memory, i.e. completely fubar,
412 * so we need to use PIPE_NOTIFY instead.
413 *
414 * However, we also need to workaround the qword write
415 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
416 * memory before requesting an interrupt.
417 */
418 ret = intel_ring_begin(ring, 32);
419 if (ret)
420 return ret;
421
422 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
423 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
424 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
425 intel_ring_emit(ring, seqno);
426 intel_ring_emit(ring, 0);
427 PIPE_CONTROL_FLUSH(ring, scratch_addr);
428 scratch_addr += 128; /* write to separate cachelines */
429 PIPE_CONTROL_FLUSH(ring, scratch_addr);
430 scratch_addr += 128;
431 PIPE_CONTROL_FLUSH(ring, scratch_addr);
432 scratch_addr += 128;
433 PIPE_CONTROL_FLUSH(ring, scratch_addr);
434 scratch_addr += 128;
435 PIPE_CONTROL_FLUSH(ring, scratch_addr);
436 scratch_addr += 128;
437 PIPE_CONTROL_FLUSH(ring, scratch_addr);
438 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
439 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
440 PIPE_CONTROL_NOTIFY);
441 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
442 intel_ring_emit(ring, seqno);
443 intel_ring_emit(ring, 0);
444 intel_ring_advance(ring);
445
446 *result = seqno;
447 return 0;
448}
449
450static int
451render_ring_add_request(struct intel_ring_buffer *ring,
452 u32 *result)
453{
454 struct drm_device *dev = ring->dev;
455 u32 seqno = i915_gem_get_seqno(dev);
456 int ret;
457
458 ret = intel_ring_begin(ring, 4);
459 if (ret)
460 return ret;
461
462 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
463 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
464 intel_ring_emit(ring, seqno);
465 intel_ring_emit(ring, MI_USER_INTERRUPT);
466 intel_ring_advance(ring);
467
468 *result = seqno;
469 return 0;
470}
471
472static u32
473ring_get_seqno(struct intel_ring_buffer *ring)
474{
475 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
476}
477
478static u32
479pc_render_get_seqno(struct intel_ring_buffer *ring)
480{
481 struct pipe_control *pc = ring->private;
482 return pc->cpu_page[0];
483}
484
485static void
486ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
487{
488 dev_priv->gt_irq_mask &= ~mask;
489 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
490 POSTING_READ(GTIMR);
491}
492
493static void
494ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
495{
496 dev_priv->gt_irq_mask |= mask;
497 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
498 POSTING_READ(GTIMR);
499}
500
501static void
502i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
503{
504 dev_priv->irq_mask &= ~mask;
505 I915_WRITE(IMR, dev_priv->irq_mask);
506 POSTING_READ(IMR);
507}
508
509static void
510i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
511{
512 dev_priv->irq_mask |= mask;
513 I915_WRITE(IMR, dev_priv->irq_mask);
514 POSTING_READ(IMR);
515}
516
517static bool
518render_ring_get_irq(struct intel_ring_buffer *ring)
519{
520 struct drm_device *dev = ring->dev;
521 drm_i915_private_t *dev_priv = dev->dev_private;
522
523 if (!dev->irq_enabled)
524 return false;
525
526 spin_lock(&ring->irq_lock);
527 if (ring->irq_refcount++ == 0) {
528 if (HAS_PCH_SPLIT(dev))
529 ironlake_enable_irq(dev_priv,
530 GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
531 else
532 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
533 }
534 spin_unlock(&ring->irq_lock);
535
536 return true;
537}
538
539static void
540render_ring_put_irq(struct intel_ring_buffer *ring)
541{
542 struct drm_device *dev = ring->dev;
543 drm_i915_private_t *dev_priv = dev->dev_private;
544
545 spin_lock(&ring->irq_lock);
546 if (--ring->irq_refcount == 0) {
547 if (HAS_PCH_SPLIT(dev))
548 ironlake_disable_irq(dev_priv,
549 GT_USER_INTERRUPT |
550 GT_PIPE_NOTIFY);
551 else
552 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
553 }
554 spin_unlock(&ring->irq_lock);
555}
556
557void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
558{
559 struct drm_device *dev = ring->dev;
560 drm_i915_private_t *dev_priv = ring->dev->dev_private;
561 u32 mmio = 0;
562
563 /* The ring status page addresses are no longer next to the rest of
564 * the ring registers as of gen7.
565 */
566 if (IS_GEN7(dev)) {
567 switch (ring->id) {
568 case RING_RENDER:
569 mmio = RENDER_HWS_PGA_GEN7;
570 break;
571 case RING_BLT:
572 mmio = BLT_HWS_PGA_GEN7;
573 break;
574 case RING_BSD:
575 mmio = BSD_HWS_PGA_GEN7;
576 break;
577 }
578 } else if (IS_GEN6(ring->dev)) {
579 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
580 } else {
581 mmio = RING_HWS_PGA(ring->mmio_base);
582 }
583
584 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
585 POSTING_READ(mmio);
586}
587
588static int
589bsd_ring_flush(struct intel_ring_buffer *ring,
590 u32 invalidate_domains,
591 u32 flush_domains)
592{
593 int ret;
594
595 ret = intel_ring_begin(ring, 2);
596 if (ret)
597 return ret;
598
599 intel_ring_emit(ring, MI_FLUSH);
600 intel_ring_emit(ring, MI_NOOP);
601 intel_ring_advance(ring);
602 return 0;
603}
604
605static int
606ring_add_request(struct intel_ring_buffer *ring,
607 u32 *result)
608{
609 u32 seqno;
610 int ret;
611
612 ret = intel_ring_begin(ring, 4);
613 if (ret)
614 return ret;
615
616 seqno = i915_gem_get_seqno(ring->dev);
617
618 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
619 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
620 intel_ring_emit(ring, seqno);
621 intel_ring_emit(ring, MI_USER_INTERRUPT);
622 intel_ring_advance(ring);
623
624 *result = seqno;
625 return 0;
626}
627
628static bool
629gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
630{
631 struct drm_device *dev = ring->dev;
632 drm_i915_private_t *dev_priv = dev->dev_private;
633
634 if (!dev->irq_enabled)
635 return false;
636
637 spin_lock(&ring->irq_lock);
638 if (ring->irq_refcount++ == 0) {
639 ring->irq_mask &= ~rflag;
640 I915_WRITE_IMR(ring, ring->irq_mask);
641 ironlake_enable_irq(dev_priv, gflag);
642 }
643 spin_unlock(&ring->irq_lock);
644
645 return true;
646}
647
648static void
649gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
650{
651 struct drm_device *dev = ring->dev;
652 drm_i915_private_t *dev_priv = dev->dev_private;
653
654 spin_lock(&ring->irq_lock);
655 if (--ring->irq_refcount == 0) {
656 ring->irq_mask |= rflag;
657 I915_WRITE_IMR(ring, ring->irq_mask);
658 ironlake_disable_irq(dev_priv, gflag);
659 }
660 spin_unlock(&ring->irq_lock);
661}
662
663static bool
664bsd_ring_get_irq(struct intel_ring_buffer *ring)
665{
666 struct drm_device *dev = ring->dev;
667 drm_i915_private_t *dev_priv = dev->dev_private;
668
669 if (!dev->irq_enabled)
670 return false;
671
672 spin_lock(&ring->irq_lock);
673 if (ring->irq_refcount++ == 0) {
674 if (IS_G4X(dev))
675 i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
676 else
677 ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
678 }
679 spin_unlock(&ring->irq_lock);
680
681 return true;
682}
683static void
684bsd_ring_put_irq(struct intel_ring_buffer *ring)
685{
686 struct drm_device *dev = ring->dev;
687 drm_i915_private_t *dev_priv = dev->dev_private;
688
689 spin_lock(&ring->irq_lock);
690 if (--ring->irq_refcount == 0) {
691 if (IS_G4X(dev))
692 i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
693 else
694 ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
695 }
696 spin_unlock(&ring->irq_lock);
697}
698
699static int
700ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
701{
702 int ret;
703
704 ret = intel_ring_begin(ring, 2);
705 if (ret)
706 return ret;
707
708 intel_ring_emit(ring,
709 MI_BATCH_BUFFER_START | (2 << 6) |
710 MI_BATCH_NON_SECURE_I965);
711 intel_ring_emit(ring, offset);
712 intel_ring_advance(ring);
713
714 return 0;
715}
716
717static int
718render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
719 u32 offset, u32 len)
720{
721 struct drm_device *dev = ring->dev;
722 int ret;
723
724 if (IS_I830(dev) || IS_845G(dev)) {
725 ret = intel_ring_begin(ring, 4);
726 if (ret)
727 return ret;
728
729 intel_ring_emit(ring, MI_BATCH_BUFFER);
730 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
731 intel_ring_emit(ring, offset + len - 8);
732 intel_ring_emit(ring, 0);
733 } else {
734 ret = intel_ring_begin(ring, 2);
735 if (ret)
736 return ret;
737
738 if (INTEL_INFO(dev)->gen >= 4) {
739 intel_ring_emit(ring,
740 MI_BATCH_BUFFER_START | (2 << 6) |
741 MI_BATCH_NON_SECURE_I965);
742 intel_ring_emit(ring, offset);
743 } else {
744 intel_ring_emit(ring,
745 MI_BATCH_BUFFER_START | (2 << 6));
746 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
747 }
748 }
749 intel_ring_advance(ring);
750
751 return 0;
752}
753
754static void cleanup_status_page(struct intel_ring_buffer *ring)
755{
756 drm_i915_private_t *dev_priv = ring->dev->dev_private;
757 struct drm_i915_gem_object *obj;
758
759 obj = ring->status_page.obj;
760 if (obj == NULL)
761 return;
762
763 kunmap(obj->pages[0]);
764 i915_gem_object_unpin(obj);
765 drm_gem_object_unreference(&obj->base);
766 ring->status_page.obj = NULL;
767
768 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
769}
770
771static int init_status_page(struct intel_ring_buffer *ring)
772{
773 struct drm_device *dev = ring->dev;
774 drm_i915_private_t *dev_priv = dev->dev_private;
775 struct drm_i915_gem_object *obj;
776 int ret;
777
778 obj = i915_gem_alloc_object(dev, 4096);
779 if (obj == NULL) {
780 DRM_ERROR("Failed to allocate status page\n");
781 ret = -ENOMEM;
782 goto err;
783 }
784
785 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
786
787 ret = i915_gem_object_pin(obj, 4096, true);
788 if (ret != 0) {
789 goto err_unref;
790 }
791
792 ring->status_page.gfx_addr = obj->gtt_offset;
793 ring->status_page.page_addr = kmap(obj->pages[0]);
794 if (ring->status_page.page_addr == NULL) {
795 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
796 goto err_unpin;
797 }
798 ring->status_page.obj = obj;
799 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
800
801 intel_ring_setup_status_page(ring);
802 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
803 ring->name, ring->status_page.gfx_addr);
804
805 return 0;
806
807err_unpin:
808 i915_gem_object_unpin(obj);
809err_unref:
810 drm_gem_object_unreference(&obj->base);
811err:
812 return ret;
813}
814
815int intel_init_ring_buffer(struct drm_device *dev,
816 struct intel_ring_buffer *ring)
817{
818 struct drm_i915_gem_object *obj;
819 int ret;
820
821 ring->dev = dev;
822 INIT_LIST_HEAD(&ring->active_list);
823 INIT_LIST_HEAD(&ring->request_list);
824 INIT_LIST_HEAD(&ring->gpu_write_list);
825
826 init_waitqueue_head(&ring->irq_queue);
827 spin_lock_init(&ring->irq_lock);
828 ring->irq_mask = ~0;
829
830 if (I915_NEED_GFX_HWS(dev)) {
831 ret = init_status_page(ring);
832 if (ret)
833 return ret;
834 }
835
836 obj = i915_gem_alloc_object(dev, ring->size);
837 if (obj == NULL) {
838 DRM_ERROR("Failed to allocate ringbuffer\n");
839 ret = -ENOMEM;
840 goto err_hws;
841 }
842
843 ring->obj = obj;
844
845 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
846 if (ret)
847 goto err_unref;
848
849 ring->map.size = ring->size;
850 ring->map.offset = dev->agp->base + obj->gtt_offset;
851 ring->map.type = 0;
852 ring->map.flags = 0;
853 ring->map.mtrr = 0;
854
855 drm_core_ioremap_wc(&ring->map, dev);
856 if (ring->map.handle == NULL) {
857 DRM_ERROR("Failed to map ringbuffer.\n");
858 ret = -EINVAL;
859 goto err_unpin;
860 }
861
862 ring->virtual_start = ring->map.handle;
863 ret = ring->init(ring);
864 if (ret)
865 goto err_unmap;
866
867 /* Workaround an erratum on the i830 which causes a hang if
868 * the TAIL pointer points to within the last 2 cachelines
869 * of the buffer.
870 */
871 ring->effective_size = ring->size;
872 if (IS_I830(ring->dev))
873 ring->effective_size -= 128;
874
875 return 0;
876
877err_unmap:
878 drm_core_ioremapfree(&ring->map, dev);
879err_unpin:
880 i915_gem_object_unpin(obj);
881err_unref:
882 drm_gem_object_unreference(&obj->base);
883 ring->obj = NULL;
884err_hws:
885 cleanup_status_page(ring);
886 return ret;
887}
888
889void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
890{
891 struct drm_i915_private *dev_priv;
892 int ret;
893
894 if (ring->obj == NULL)
895 return;
896
897 /* Disable the ring buffer. The ring must be idle at this point */
898 dev_priv = ring->dev->dev_private;
899 ret = intel_wait_ring_idle(ring);
900 if (ret)
901 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
902 ring->name, ret);
903
904 I915_WRITE_CTL(ring, 0);
905
906 drm_core_ioremapfree(&ring->map, ring->dev);
907
908 i915_gem_object_unpin(ring->obj);
909 drm_gem_object_unreference(&ring->obj->base);
910 ring->obj = NULL;
911
912 if (ring->cleanup)
913 ring->cleanup(ring);
914
915 cleanup_status_page(ring);
916}
917
918static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
919{
920 unsigned int *virt;
921 int rem = ring->size - ring->tail;
922
923 if (ring->space < rem) {
924 int ret = intel_wait_ring_buffer(ring, rem);
925 if (ret)
926 return ret;
927 }
928
929 virt = (unsigned int *)(ring->virtual_start + ring->tail);
930 rem /= 8;
931 while (rem--) {
932 *virt++ = MI_NOOP;
933 *virt++ = MI_NOOP;
934 }
935
936 ring->tail = 0;
937 ring->space = ring_space(ring);
938
939 return 0;
940}
941
942int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
943{
944 struct drm_device *dev = ring->dev;
945 struct drm_i915_private *dev_priv = dev->dev_private;
946 unsigned long end;
947 u32 head;
948
949 /* If the reported head position has wrapped or hasn't advanced,
950 * fallback to the slow and accurate path.
951 */
952 head = intel_read_status_page(ring, 4);
953 if (head > ring->head) {
954 ring->head = head;
955 ring->space = ring_space(ring);
956 if (ring->space >= n)
957 return 0;
958 }
959
960 trace_i915_ring_wait_begin(ring);
961 end = jiffies + 3 * HZ;
962 do {
963 ring->head = I915_READ_HEAD(ring);
964 ring->space = ring_space(ring);
965 if (ring->space >= n) {
966 trace_i915_ring_wait_end(ring);
967 return 0;
968 }
969
970 if (dev->primary->master) {
971 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
972 if (master_priv->sarea_priv)
973 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
974 }
975
976 msleep(1);
977 if (atomic_read(&dev_priv->mm.wedged))
978 return -EAGAIN;
979 } while (!time_after(jiffies, end));
980 trace_i915_ring_wait_end(ring);
981 return -EBUSY;
982}
983
984int intel_ring_begin(struct intel_ring_buffer *ring,
985 int num_dwords)
986{
987 struct drm_i915_private *dev_priv = ring->dev->dev_private;
988 int n = 4*num_dwords;
989 int ret;
990
991 if (unlikely(atomic_read(&dev_priv->mm.wedged)))
992 return -EIO;
993
994 if (unlikely(ring->tail + n > ring->effective_size)) {
995 ret = intel_wrap_ring_buffer(ring);
996 if (unlikely(ret))
997 return ret;
998 }
999
1000 if (unlikely(ring->space < n)) {
1001 ret = intel_wait_ring_buffer(ring, n);
1002 if (unlikely(ret))
1003 return ret;
1004 }
1005
1006 ring->space -= n;
1007 return 0;
1008}
1009
1010void intel_ring_advance(struct intel_ring_buffer *ring)
1011{
1012 ring->tail &= ring->size - 1;
1013 ring->write_tail(ring, ring->tail);
1014}
1015
1016static const struct intel_ring_buffer render_ring = {
1017 .name = "render ring",
1018 .id = RING_RENDER,
1019 .mmio_base = RENDER_RING_BASE,
1020 .size = 32 * PAGE_SIZE,
1021 .init = init_render_ring,
1022 .write_tail = ring_write_tail,
1023 .flush = render_ring_flush,
1024 .add_request = render_ring_add_request,
1025 .get_seqno = ring_get_seqno,
1026 .irq_get = render_ring_get_irq,
1027 .irq_put = render_ring_put_irq,
1028 .dispatch_execbuffer = render_ring_dispatch_execbuffer,
1029 .cleanup = render_ring_cleanup,
1030};
1031
1032/* ring buffer for bit-stream decoder */
1033
1034static const struct intel_ring_buffer bsd_ring = {
1035 .name = "bsd ring",
1036 .id = RING_BSD,
1037 .mmio_base = BSD_RING_BASE,
1038 .size = 32 * PAGE_SIZE,
1039 .init = init_ring_common,
1040 .write_tail = ring_write_tail,
1041 .flush = bsd_ring_flush,
1042 .add_request = ring_add_request,
1043 .get_seqno = ring_get_seqno,
1044 .irq_get = bsd_ring_get_irq,
1045 .irq_put = bsd_ring_put_irq,
1046 .dispatch_execbuffer = ring_dispatch_execbuffer,
1047};
1048
1049
1050static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1051 u32 value)
1052{
1053 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1054
1055 /* Every tail move must follow the sequence below */
1056 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1057 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1058 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1059 I915_WRITE(GEN6_BSD_RNCID, 0x0);
1060
1061 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1062 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1063 50))
1064 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1065
1066 I915_WRITE_TAIL(ring, value);
1067 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1068 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1069 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1070}
1071
1072static int gen6_ring_flush(struct intel_ring_buffer *ring,
1073 u32 invalidate, u32 flush)
1074{
1075 uint32_t cmd;
1076 int ret;
1077
1078 ret = intel_ring_begin(ring, 4);
1079 if (ret)
1080 return ret;
1081
1082 cmd = MI_FLUSH_DW;
1083 if (invalidate & I915_GEM_GPU_DOMAINS)
1084 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1085 intel_ring_emit(ring, cmd);
1086 intel_ring_emit(ring, 0);
1087 intel_ring_emit(ring, 0);
1088 intel_ring_emit(ring, MI_NOOP);
1089 intel_ring_advance(ring);
1090 return 0;
1091}
1092
1093static int
1094gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1095 u32 offset, u32 len)
1096{
1097 int ret;
1098
1099 ret = intel_ring_begin(ring, 2);
1100 if (ret)
1101 return ret;
1102
1103 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1104 /* bit0-7 is the length on GEN6+ */
1105 intel_ring_emit(ring, offset);
1106 intel_ring_advance(ring);
1107
1108 return 0;
1109}
1110
1111static bool
1112gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
1113{
1114 return gen6_ring_get_irq(ring,
1115 GT_USER_INTERRUPT,
1116 GEN6_RENDER_USER_INTERRUPT);
1117}
1118
1119static void
1120gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
1121{
1122 return gen6_ring_put_irq(ring,
1123 GT_USER_INTERRUPT,
1124 GEN6_RENDER_USER_INTERRUPT);
1125}
1126
1127static bool
1128gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1129{
1130 return gen6_ring_get_irq(ring,
1131 GT_GEN6_BSD_USER_INTERRUPT,
1132 GEN6_BSD_USER_INTERRUPT);
1133}
1134
1135static void
1136gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1137{
1138 return gen6_ring_put_irq(ring,
1139 GT_GEN6_BSD_USER_INTERRUPT,
1140 GEN6_BSD_USER_INTERRUPT);
1141}
1142
1143/* ring buffer for Video Codec for Gen6+ */
1144static const struct intel_ring_buffer gen6_bsd_ring = {
1145 .name = "gen6 bsd ring",
1146 .id = RING_BSD,
1147 .mmio_base = GEN6_BSD_RING_BASE,
1148 .size = 32 * PAGE_SIZE,
1149 .init = init_ring_common,
1150 .write_tail = gen6_bsd_ring_write_tail,
1151 .flush = gen6_ring_flush,
1152 .add_request = gen6_add_request,
1153 .get_seqno = ring_get_seqno,
1154 .irq_get = gen6_bsd_ring_get_irq,
1155 .irq_put = gen6_bsd_ring_put_irq,
1156 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
1157};
1158
1159/* Blitter support (SandyBridge+) */
1160
1161static bool
1162blt_ring_get_irq(struct intel_ring_buffer *ring)
1163{
1164 return gen6_ring_get_irq(ring,
1165 GT_BLT_USER_INTERRUPT,
1166 GEN6_BLITTER_USER_INTERRUPT);
1167}
1168
1169static void
1170blt_ring_put_irq(struct intel_ring_buffer *ring)
1171{
1172 gen6_ring_put_irq(ring,
1173 GT_BLT_USER_INTERRUPT,
1174 GEN6_BLITTER_USER_INTERRUPT);
1175}
1176
1177
1178/* Workaround for some stepping of SNB,
1179 * each time when BLT engine ring tail moved,
1180 * the first command in the ring to be parsed
1181 * should be MI_BATCH_BUFFER_START
1182 */
1183#define NEED_BLT_WORKAROUND(dev) \
1184 (IS_GEN6(dev) && (dev->pdev->revision < 8))
1185
1186static inline struct drm_i915_gem_object *
1187to_blt_workaround(struct intel_ring_buffer *ring)
1188{
1189 return ring->private;
1190}
1191
1192static int blt_ring_init(struct intel_ring_buffer *ring)
1193{
1194 if (NEED_BLT_WORKAROUND(ring->dev)) {
1195 struct drm_i915_gem_object *obj;
1196 u32 *ptr;
1197 int ret;
1198
1199 obj = i915_gem_alloc_object(ring->dev, 4096);
1200 if (obj == NULL)
1201 return -ENOMEM;
1202
1203 ret = i915_gem_object_pin(obj, 4096, true);
1204 if (ret) {
1205 drm_gem_object_unreference(&obj->base);
1206 return ret;
1207 }
1208
1209 ptr = kmap(obj->pages[0]);
1210 *ptr++ = MI_BATCH_BUFFER_END;
1211 *ptr++ = MI_NOOP;
1212 kunmap(obj->pages[0]);
1213
1214 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1215 if (ret) {
1216 i915_gem_object_unpin(obj);
1217 drm_gem_object_unreference(&obj->base);
1218 return ret;
1219 }
1220
1221 ring->private = obj;
1222 }
1223
1224 return init_ring_common(ring);
1225}
1226
1227static int blt_ring_begin(struct intel_ring_buffer *ring,
1228 int num_dwords)
1229{
1230 if (ring->private) {
1231 int ret = intel_ring_begin(ring, num_dwords+2);
1232 if (ret)
1233 return ret;
1234
1235 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
1236 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
1237
1238 return 0;
1239 } else
1240 return intel_ring_begin(ring, 4);
1241}
1242
1243static int blt_ring_flush(struct intel_ring_buffer *ring,
1244 u32 invalidate, u32 flush)
1245{
1246 uint32_t cmd;
1247 int ret;
1248
1249 ret = blt_ring_begin(ring, 4);
1250 if (ret)
1251 return ret;
1252
1253 cmd = MI_FLUSH_DW;
1254 if (invalidate & I915_GEM_DOMAIN_RENDER)
1255 cmd |= MI_INVALIDATE_TLB;
1256 intel_ring_emit(ring, cmd);
1257 intel_ring_emit(ring, 0);
1258 intel_ring_emit(ring, 0);
1259 intel_ring_emit(ring, MI_NOOP);
1260 intel_ring_advance(ring);
1261 return 0;
1262}
1263
1264static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1265{
1266 if (!ring->private)
1267 return;
1268
1269 i915_gem_object_unpin(ring->private);
1270 drm_gem_object_unreference(ring->private);
1271 ring->private = NULL;
1272}
1273
1274static const struct intel_ring_buffer gen6_blt_ring = {
1275 .name = "blt ring",
1276 .id = RING_BLT,
1277 .mmio_base = BLT_RING_BASE,
1278 .size = 32 * PAGE_SIZE,
1279 .init = blt_ring_init,
1280 .write_tail = ring_write_tail,
1281 .flush = blt_ring_flush,
1282 .add_request = gen6_add_request,
1283 .get_seqno = ring_get_seqno,
1284 .irq_get = blt_ring_get_irq,
1285 .irq_put = blt_ring_put_irq,
1286 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
1287 .cleanup = blt_ring_cleanup,
1288};
1289
1290int intel_init_render_ring_buffer(struct drm_device *dev)
1291{
1292 drm_i915_private_t *dev_priv = dev->dev_private;
1293 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1294
1295 *ring = render_ring;
1296 if (INTEL_INFO(dev)->gen >= 6) {
1297 ring->add_request = gen6_add_request;
1298 ring->irq_get = gen6_render_ring_get_irq;
1299 ring->irq_put = gen6_render_ring_put_irq;
1300 } else if (IS_GEN5(dev)) {
1301 ring->add_request = pc_render_add_request;
1302 ring->get_seqno = pc_render_get_seqno;
1303 }
1304
1305 if (!I915_NEED_GFX_HWS(dev)) {
1306 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1307 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1308 }
1309
1310 return intel_init_ring_buffer(dev, ring);
1311}
1312
1313int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1314{
1315 drm_i915_private_t *dev_priv = dev->dev_private;
1316 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1317
1318 *ring = render_ring;
1319 if (INTEL_INFO(dev)->gen >= 6) {
1320 ring->add_request = gen6_add_request;
1321 ring->irq_get = gen6_render_ring_get_irq;
1322 ring->irq_put = gen6_render_ring_put_irq;
1323 } else if (IS_GEN5(dev)) {
1324 ring->add_request = pc_render_add_request;
1325 ring->get_seqno = pc_render_get_seqno;
1326 }
1327
1328 if (!I915_NEED_GFX_HWS(dev))
1329 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1330
1331 ring->dev = dev;
1332 INIT_LIST_HEAD(&ring->active_list);
1333 INIT_LIST_HEAD(&ring->request_list);
1334 INIT_LIST_HEAD(&ring->gpu_write_list);
1335
1336 ring->size = size;
1337 ring->effective_size = ring->size;
1338 if (IS_I830(ring->dev))
1339 ring->effective_size -= 128;
1340
1341 ring->map.offset = start;
1342 ring->map.size = size;
1343 ring->map.type = 0;
1344 ring->map.flags = 0;
1345 ring->map.mtrr = 0;
1346
1347 drm_core_ioremap_wc(&ring->map, dev);
1348 if (ring->map.handle == NULL) {
1349 DRM_ERROR("can not ioremap virtual address for"
1350 " ring buffer\n");
1351 return -ENOMEM;
1352 }
1353
1354 ring->virtual_start = (void __force __iomem *)ring->map.handle;
1355 return 0;
1356}
1357
1358int intel_init_bsd_ring_buffer(struct drm_device *dev)
1359{
1360 drm_i915_private_t *dev_priv = dev->dev_private;
1361 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1362
1363 if (IS_GEN6(dev) || IS_GEN7(dev))
1364 *ring = gen6_bsd_ring;
1365 else
1366 *ring = bsd_ring;
1367
1368 return intel_init_ring_buffer(dev, ring);
1369}
1370
1371int intel_init_blt_ring_buffer(struct drm_device *dev)
1372{
1373 drm_i915_private_t *dev_priv = dev->dev_private;
1374 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1375
1376 *ring = gen6_blt_ring;
1377
1378 return intel_init_ring_buffer(dev, ring);
1379}
1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30#include "drmP.h"
31#include "drm.h"
32#include "i915_drv.h"
33#include "i915_drm.h"
34#include "i915_trace.h"
35#include "intel_drv.h"
36
37/*
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
40 */
41struct pipe_control {
42 struct drm_i915_gem_object *obj;
43 volatile u32 *cpu_page;
44 u32 gtt_offset;
45};
46
47static inline int ring_space(struct intel_ring_buffer *ring)
48{
49 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
50 if (space < 0)
51 space += ring->size;
52 return space;
53}
54
55static int
56gen2_render_ring_flush(struct intel_ring_buffer *ring,
57 u32 invalidate_domains,
58 u32 flush_domains)
59{
60 u32 cmd;
61 int ret;
62
63 cmd = MI_FLUSH;
64 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
65 cmd |= MI_NO_WRITE_FLUSH;
66
67 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
68 cmd |= MI_READ_FLUSH;
69
70 ret = intel_ring_begin(ring, 2);
71 if (ret)
72 return ret;
73
74 intel_ring_emit(ring, cmd);
75 intel_ring_emit(ring, MI_NOOP);
76 intel_ring_advance(ring);
77
78 return 0;
79}
80
81static int
82gen4_render_ring_flush(struct intel_ring_buffer *ring,
83 u32 invalidate_domains,
84 u32 flush_domains)
85{
86 struct drm_device *dev = ring->dev;
87 u32 cmd;
88 int ret;
89
90 /*
91 * read/write caches:
92 *
93 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
94 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
95 * also flushed at 2d versus 3d pipeline switches.
96 *
97 * read-only caches:
98 *
99 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
100 * MI_READ_FLUSH is set, and is always flushed on 965.
101 *
102 * I915_GEM_DOMAIN_COMMAND may not exist?
103 *
104 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
105 * invalidated when MI_EXE_FLUSH is set.
106 *
107 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
108 * invalidated with every MI_FLUSH.
109 *
110 * TLBs:
111 *
112 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
113 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
114 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
115 * are flushed at any MI_FLUSH.
116 */
117
118 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
119 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
120 cmd &= ~MI_NO_WRITE_FLUSH;
121 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
122 cmd |= MI_EXE_FLUSH;
123
124 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
125 (IS_G4X(dev) || IS_GEN5(dev)))
126 cmd |= MI_INVALIDATE_ISP;
127
128 ret = intel_ring_begin(ring, 2);
129 if (ret)
130 return ret;
131
132 intel_ring_emit(ring, cmd);
133 intel_ring_emit(ring, MI_NOOP);
134 intel_ring_advance(ring);
135
136 return 0;
137}
138
139/**
140 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
141 * implementing two workarounds on gen6. From section 1.4.7.1
142 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 *
144 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
145 * produced by non-pipelined state commands), software needs to first
146 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
147 * 0.
148 *
149 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
150 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 *
152 * And the workaround for these two requires this workaround first:
153 *
154 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
155 * BEFORE the pipe-control with a post-sync op and no write-cache
156 * flushes.
157 *
158 * And this last workaround is tricky because of the requirements on
159 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
160 * volume 2 part 1:
161 *
162 * "1 of the following must also be set:
163 * - Render Target Cache Flush Enable ([12] of DW1)
164 * - Depth Cache Flush Enable ([0] of DW1)
165 * - Stall at Pixel Scoreboard ([1] of DW1)
166 * - Depth Stall ([13] of DW1)
167 * - Post-Sync Operation ([13] of DW1)
168 * - Notify Enable ([8] of DW1)"
169 *
170 * The cache flushes require the workaround flush that triggered this
171 * one, so we can't use it. Depth stall would trigger the same.
172 * Post-sync nonzero is what triggered this second workaround, so we
173 * can't use that one either. Notify enable is IRQs, which aren't
174 * really our business. That leaves only stall at scoreboard.
175 */
176static int
177intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
178{
179 struct pipe_control *pc = ring->private;
180 u32 scratch_addr = pc->gtt_offset + 128;
181 int ret;
182
183
184 ret = intel_ring_begin(ring, 6);
185 if (ret)
186 return ret;
187
188 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
189 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
190 PIPE_CONTROL_STALL_AT_SCOREBOARD);
191 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
192 intel_ring_emit(ring, 0); /* low dword */
193 intel_ring_emit(ring, 0); /* high dword */
194 intel_ring_emit(ring, MI_NOOP);
195 intel_ring_advance(ring);
196
197 ret = intel_ring_begin(ring, 6);
198 if (ret)
199 return ret;
200
201 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
202 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
203 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
204 intel_ring_emit(ring, 0);
205 intel_ring_emit(ring, 0);
206 intel_ring_emit(ring, MI_NOOP);
207 intel_ring_advance(ring);
208
209 return 0;
210}
211
212static int
213gen6_render_ring_flush(struct intel_ring_buffer *ring,
214 u32 invalidate_domains, u32 flush_domains)
215{
216 u32 flags = 0;
217 struct pipe_control *pc = ring->private;
218 u32 scratch_addr = pc->gtt_offset + 128;
219 int ret;
220
221 /* Force SNB workarounds for PIPE_CONTROL flushes */
222 intel_emit_post_sync_nonzero_flush(ring);
223
224 /* Just flush everything. Experiments have shown that reducing the
225 * number of bits based on the write domains has little performance
226 * impact.
227 */
228 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
229 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
230 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
231 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
232 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
233 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
234 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
235
236 ret = intel_ring_begin(ring, 6);
237 if (ret)
238 return ret;
239
240 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
241 intel_ring_emit(ring, flags);
242 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
243 intel_ring_emit(ring, 0); /* lower dword */
244 intel_ring_emit(ring, 0); /* uppwer dword */
245 intel_ring_emit(ring, MI_NOOP);
246 intel_ring_advance(ring);
247
248 return 0;
249}
250
251static void ring_write_tail(struct intel_ring_buffer *ring,
252 u32 value)
253{
254 drm_i915_private_t *dev_priv = ring->dev->dev_private;
255 I915_WRITE_TAIL(ring, value);
256}
257
258u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
259{
260 drm_i915_private_t *dev_priv = ring->dev->dev_private;
261 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
262 RING_ACTHD(ring->mmio_base) : ACTHD;
263
264 return I915_READ(acthd_reg);
265}
266
267static int init_ring_common(struct intel_ring_buffer *ring)
268{
269 struct drm_device *dev = ring->dev;
270 drm_i915_private_t *dev_priv = dev->dev_private;
271 struct drm_i915_gem_object *obj = ring->obj;
272 int ret = 0;
273 u32 head;
274
275 if (HAS_FORCE_WAKE(dev))
276 gen6_gt_force_wake_get(dev_priv);
277
278 /* Stop the ring if it's running. */
279 I915_WRITE_CTL(ring, 0);
280 I915_WRITE_HEAD(ring, 0);
281 ring->write_tail(ring, 0);
282
283 head = I915_READ_HEAD(ring) & HEAD_ADDR;
284
285 /* G45 ring initialization fails to reset head to zero */
286 if (head != 0) {
287 DRM_DEBUG_KMS("%s head not reset to zero "
288 "ctl %08x head %08x tail %08x start %08x\n",
289 ring->name,
290 I915_READ_CTL(ring),
291 I915_READ_HEAD(ring),
292 I915_READ_TAIL(ring),
293 I915_READ_START(ring));
294
295 I915_WRITE_HEAD(ring, 0);
296
297 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
298 DRM_ERROR("failed to set %s head to zero "
299 "ctl %08x head %08x tail %08x start %08x\n",
300 ring->name,
301 I915_READ_CTL(ring),
302 I915_READ_HEAD(ring),
303 I915_READ_TAIL(ring),
304 I915_READ_START(ring));
305 }
306 }
307
308 /* Initialize the ring. This must happen _after_ we've cleared the ring
309 * registers with the above sequence (the readback of the HEAD registers
310 * also enforces ordering), otherwise the hw might lose the new ring
311 * register values. */
312 I915_WRITE_START(ring, obj->gtt_offset);
313 I915_WRITE_CTL(ring,
314 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
315 | RING_VALID);
316
317 /* If the head is still not zero, the ring is dead */
318 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
319 I915_READ_START(ring) == obj->gtt_offset &&
320 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
321 DRM_ERROR("%s initialization failed "
322 "ctl %08x head %08x tail %08x start %08x\n",
323 ring->name,
324 I915_READ_CTL(ring),
325 I915_READ_HEAD(ring),
326 I915_READ_TAIL(ring),
327 I915_READ_START(ring));
328 ret = -EIO;
329 goto out;
330 }
331
332 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
333 i915_kernel_lost_context(ring->dev);
334 else {
335 ring->head = I915_READ_HEAD(ring);
336 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
337 ring->space = ring_space(ring);
338 ring->last_retired_head = -1;
339 }
340
341out:
342 if (HAS_FORCE_WAKE(dev))
343 gen6_gt_force_wake_put(dev_priv);
344
345 return ret;
346}
347
348static int
349init_pipe_control(struct intel_ring_buffer *ring)
350{
351 struct pipe_control *pc;
352 struct drm_i915_gem_object *obj;
353 int ret;
354
355 if (ring->private)
356 return 0;
357
358 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
359 if (!pc)
360 return -ENOMEM;
361
362 obj = i915_gem_alloc_object(ring->dev, 4096);
363 if (obj == NULL) {
364 DRM_ERROR("Failed to allocate seqno page\n");
365 ret = -ENOMEM;
366 goto err;
367 }
368
369 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
370
371 ret = i915_gem_object_pin(obj, 4096, true);
372 if (ret)
373 goto err_unref;
374
375 pc->gtt_offset = obj->gtt_offset;
376 pc->cpu_page = kmap(obj->pages[0]);
377 if (pc->cpu_page == NULL)
378 goto err_unpin;
379
380 pc->obj = obj;
381 ring->private = pc;
382 return 0;
383
384err_unpin:
385 i915_gem_object_unpin(obj);
386err_unref:
387 drm_gem_object_unreference(&obj->base);
388err:
389 kfree(pc);
390 return ret;
391}
392
393static void
394cleanup_pipe_control(struct intel_ring_buffer *ring)
395{
396 struct pipe_control *pc = ring->private;
397 struct drm_i915_gem_object *obj;
398
399 if (!ring->private)
400 return;
401
402 obj = pc->obj;
403 kunmap(obj->pages[0]);
404 i915_gem_object_unpin(obj);
405 drm_gem_object_unreference(&obj->base);
406
407 kfree(pc);
408 ring->private = NULL;
409}
410
411static int init_render_ring(struct intel_ring_buffer *ring)
412{
413 struct drm_device *dev = ring->dev;
414 struct drm_i915_private *dev_priv = dev->dev_private;
415 int ret = init_ring_common(ring);
416
417 if (INTEL_INFO(dev)->gen > 3) {
418 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
419 if (IS_GEN7(dev))
420 I915_WRITE(GFX_MODE_GEN7,
421 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
422 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
423 }
424
425 if (INTEL_INFO(dev)->gen >= 5) {
426 ret = init_pipe_control(ring);
427 if (ret)
428 return ret;
429 }
430
431 if (IS_GEN6(dev)) {
432 /* From the Sandybridge PRM, volume 1 part 3, page 24:
433 * "If this bit is set, STCunit will have LRA as replacement
434 * policy. [...] This bit must be reset. LRA replacement
435 * policy is not supported."
436 */
437 I915_WRITE(CACHE_MODE_0,
438 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
439 }
440
441 if (INTEL_INFO(dev)->gen >= 6)
442 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
443
444 return ret;
445}
446
447static void render_ring_cleanup(struct intel_ring_buffer *ring)
448{
449 if (!ring->private)
450 return;
451
452 cleanup_pipe_control(ring);
453}
454
455static void
456update_mboxes(struct intel_ring_buffer *ring,
457 u32 seqno,
458 u32 mmio_offset)
459{
460 intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
461 MI_SEMAPHORE_GLOBAL_GTT |
462 MI_SEMAPHORE_REGISTER |
463 MI_SEMAPHORE_UPDATE);
464 intel_ring_emit(ring, seqno);
465 intel_ring_emit(ring, mmio_offset);
466}
467
468/**
469 * gen6_add_request - Update the semaphore mailbox registers
470 *
471 * @ring - ring that is adding a request
472 * @seqno - return seqno stuck into the ring
473 *
474 * Update the mailbox registers in the *other* rings with the current seqno.
475 * This acts like a signal in the canonical semaphore.
476 */
477static int
478gen6_add_request(struct intel_ring_buffer *ring,
479 u32 *seqno)
480{
481 u32 mbox1_reg;
482 u32 mbox2_reg;
483 int ret;
484
485 ret = intel_ring_begin(ring, 10);
486 if (ret)
487 return ret;
488
489 mbox1_reg = ring->signal_mbox[0];
490 mbox2_reg = ring->signal_mbox[1];
491
492 *seqno = i915_gem_next_request_seqno(ring);
493
494 update_mboxes(ring, *seqno, mbox1_reg);
495 update_mboxes(ring, *seqno, mbox2_reg);
496 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
497 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
498 intel_ring_emit(ring, *seqno);
499 intel_ring_emit(ring, MI_USER_INTERRUPT);
500 intel_ring_advance(ring);
501
502 return 0;
503}
504
505/**
506 * intel_ring_sync - sync the waiter to the signaller on seqno
507 *
508 * @waiter - ring that is waiting
509 * @signaller - ring which has, or will signal
510 * @seqno - seqno which the waiter will block on
511 */
512static int
513gen6_ring_sync(struct intel_ring_buffer *waiter,
514 struct intel_ring_buffer *signaller,
515 u32 seqno)
516{
517 int ret;
518 u32 dw1 = MI_SEMAPHORE_MBOX |
519 MI_SEMAPHORE_COMPARE |
520 MI_SEMAPHORE_REGISTER;
521
522 /* Throughout all of the GEM code, seqno passed implies our current
523 * seqno is >= the last seqno executed. However for hardware the
524 * comparison is strictly greater than.
525 */
526 seqno -= 1;
527
528 WARN_ON(signaller->semaphore_register[waiter->id] ==
529 MI_SEMAPHORE_SYNC_INVALID);
530
531 ret = intel_ring_begin(waiter, 4);
532 if (ret)
533 return ret;
534
535 intel_ring_emit(waiter,
536 dw1 | signaller->semaphore_register[waiter->id]);
537 intel_ring_emit(waiter, seqno);
538 intel_ring_emit(waiter, 0);
539 intel_ring_emit(waiter, MI_NOOP);
540 intel_ring_advance(waiter);
541
542 return 0;
543}
544
545#define PIPE_CONTROL_FLUSH(ring__, addr__) \
546do { \
547 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
548 PIPE_CONTROL_DEPTH_STALL); \
549 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
550 intel_ring_emit(ring__, 0); \
551 intel_ring_emit(ring__, 0); \
552} while (0)
553
554static int
555pc_render_add_request(struct intel_ring_buffer *ring,
556 u32 *result)
557{
558 u32 seqno = i915_gem_next_request_seqno(ring);
559 struct pipe_control *pc = ring->private;
560 u32 scratch_addr = pc->gtt_offset + 128;
561 int ret;
562
563 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
564 * incoherent with writes to memory, i.e. completely fubar,
565 * so we need to use PIPE_NOTIFY instead.
566 *
567 * However, we also need to workaround the qword write
568 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
569 * memory before requesting an interrupt.
570 */
571 ret = intel_ring_begin(ring, 32);
572 if (ret)
573 return ret;
574
575 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
576 PIPE_CONTROL_WRITE_FLUSH |
577 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
578 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
579 intel_ring_emit(ring, seqno);
580 intel_ring_emit(ring, 0);
581 PIPE_CONTROL_FLUSH(ring, scratch_addr);
582 scratch_addr += 128; /* write to separate cachelines */
583 PIPE_CONTROL_FLUSH(ring, scratch_addr);
584 scratch_addr += 128;
585 PIPE_CONTROL_FLUSH(ring, scratch_addr);
586 scratch_addr += 128;
587 PIPE_CONTROL_FLUSH(ring, scratch_addr);
588 scratch_addr += 128;
589 PIPE_CONTROL_FLUSH(ring, scratch_addr);
590 scratch_addr += 128;
591 PIPE_CONTROL_FLUSH(ring, scratch_addr);
592
593 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
594 PIPE_CONTROL_WRITE_FLUSH |
595 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
596 PIPE_CONTROL_NOTIFY);
597 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
598 intel_ring_emit(ring, seqno);
599 intel_ring_emit(ring, 0);
600 intel_ring_advance(ring);
601
602 *result = seqno;
603 return 0;
604}
605
606static u32
607gen6_ring_get_seqno(struct intel_ring_buffer *ring)
608{
609 struct drm_device *dev = ring->dev;
610
611 /* Workaround to force correct ordering between irq and seqno writes on
612 * ivb (and maybe also on snb) by reading from a CS register (like
613 * ACTHD) before reading the status page. */
614 if (IS_GEN6(dev) || IS_GEN7(dev))
615 intel_ring_get_active_head(ring);
616 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
617}
618
619static u32
620ring_get_seqno(struct intel_ring_buffer *ring)
621{
622 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
623}
624
625static u32
626pc_render_get_seqno(struct intel_ring_buffer *ring)
627{
628 struct pipe_control *pc = ring->private;
629 return pc->cpu_page[0];
630}
631
632static bool
633gen5_ring_get_irq(struct intel_ring_buffer *ring)
634{
635 struct drm_device *dev = ring->dev;
636 drm_i915_private_t *dev_priv = dev->dev_private;
637 unsigned long flags;
638
639 if (!dev->irq_enabled)
640 return false;
641
642 spin_lock_irqsave(&dev_priv->irq_lock, flags);
643 if (ring->irq_refcount++ == 0) {
644 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
645 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
646 POSTING_READ(GTIMR);
647 }
648 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
649
650 return true;
651}
652
653static void
654gen5_ring_put_irq(struct intel_ring_buffer *ring)
655{
656 struct drm_device *dev = ring->dev;
657 drm_i915_private_t *dev_priv = dev->dev_private;
658 unsigned long flags;
659
660 spin_lock_irqsave(&dev_priv->irq_lock, flags);
661 if (--ring->irq_refcount == 0) {
662 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
663 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
664 POSTING_READ(GTIMR);
665 }
666 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
667}
668
669static bool
670i9xx_ring_get_irq(struct intel_ring_buffer *ring)
671{
672 struct drm_device *dev = ring->dev;
673 drm_i915_private_t *dev_priv = dev->dev_private;
674 unsigned long flags;
675
676 if (!dev->irq_enabled)
677 return false;
678
679 spin_lock_irqsave(&dev_priv->irq_lock, flags);
680 if (ring->irq_refcount++ == 0) {
681 dev_priv->irq_mask &= ~ring->irq_enable_mask;
682 I915_WRITE(IMR, dev_priv->irq_mask);
683 POSTING_READ(IMR);
684 }
685 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
686
687 return true;
688}
689
690static void
691i9xx_ring_put_irq(struct intel_ring_buffer *ring)
692{
693 struct drm_device *dev = ring->dev;
694 drm_i915_private_t *dev_priv = dev->dev_private;
695 unsigned long flags;
696
697 spin_lock_irqsave(&dev_priv->irq_lock, flags);
698 if (--ring->irq_refcount == 0) {
699 dev_priv->irq_mask |= ring->irq_enable_mask;
700 I915_WRITE(IMR, dev_priv->irq_mask);
701 POSTING_READ(IMR);
702 }
703 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
704}
705
706static bool
707i8xx_ring_get_irq(struct intel_ring_buffer *ring)
708{
709 struct drm_device *dev = ring->dev;
710 drm_i915_private_t *dev_priv = dev->dev_private;
711 unsigned long flags;
712
713 if (!dev->irq_enabled)
714 return false;
715
716 spin_lock_irqsave(&dev_priv->irq_lock, flags);
717 if (ring->irq_refcount++ == 0) {
718 dev_priv->irq_mask &= ~ring->irq_enable_mask;
719 I915_WRITE16(IMR, dev_priv->irq_mask);
720 POSTING_READ16(IMR);
721 }
722 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
723
724 return true;
725}
726
727static void
728i8xx_ring_put_irq(struct intel_ring_buffer *ring)
729{
730 struct drm_device *dev = ring->dev;
731 drm_i915_private_t *dev_priv = dev->dev_private;
732 unsigned long flags;
733
734 spin_lock_irqsave(&dev_priv->irq_lock, flags);
735 if (--ring->irq_refcount == 0) {
736 dev_priv->irq_mask |= ring->irq_enable_mask;
737 I915_WRITE16(IMR, dev_priv->irq_mask);
738 POSTING_READ16(IMR);
739 }
740 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
741}
742
743void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
744{
745 struct drm_device *dev = ring->dev;
746 drm_i915_private_t *dev_priv = ring->dev->dev_private;
747 u32 mmio = 0;
748
749 /* The ring status page addresses are no longer next to the rest of
750 * the ring registers as of gen7.
751 */
752 if (IS_GEN7(dev)) {
753 switch (ring->id) {
754 case RCS:
755 mmio = RENDER_HWS_PGA_GEN7;
756 break;
757 case BCS:
758 mmio = BLT_HWS_PGA_GEN7;
759 break;
760 case VCS:
761 mmio = BSD_HWS_PGA_GEN7;
762 break;
763 }
764 } else if (IS_GEN6(ring->dev)) {
765 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
766 } else {
767 mmio = RING_HWS_PGA(ring->mmio_base);
768 }
769
770 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
771 POSTING_READ(mmio);
772}
773
774static int
775bsd_ring_flush(struct intel_ring_buffer *ring,
776 u32 invalidate_domains,
777 u32 flush_domains)
778{
779 int ret;
780
781 ret = intel_ring_begin(ring, 2);
782 if (ret)
783 return ret;
784
785 intel_ring_emit(ring, MI_FLUSH);
786 intel_ring_emit(ring, MI_NOOP);
787 intel_ring_advance(ring);
788 return 0;
789}
790
791static int
792i9xx_add_request(struct intel_ring_buffer *ring,
793 u32 *result)
794{
795 u32 seqno;
796 int ret;
797
798 ret = intel_ring_begin(ring, 4);
799 if (ret)
800 return ret;
801
802 seqno = i915_gem_next_request_seqno(ring);
803
804 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
805 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
806 intel_ring_emit(ring, seqno);
807 intel_ring_emit(ring, MI_USER_INTERRUPT);
808 intel_ring_advance(ring);
809
810 *result = seqno;
811 return 0;
812}
813
814static bool
815gen6_ring_get_irq(struct intel_ring_buffer *ring)
816{
817 struct drm_device *dev = ring->dev;
818 drm_i915_private_t *dev_priv = dev->dev_private;
819 unsigned long flags;
820
821 if (!dev->irq_enabled)
822 return false;
823
824 /* It looks like we need to prevent the gt from suspending while waiting
825 * for an notifiy irq, otherwise irqs seem to get lost on at least the
826 * blt/bsd rings on ivb. */
827 gen6_gt_force_wake_get(dev_priv);
828
829 spin_lock_irqsave(&dev_priv->irq_lock, flags);
830 if (ring->irq_refcount++ == 0) {
831 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
832 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
833 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
834 POSTING_READ(GTIMR);
835 }
836 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
837
838 return true;
839}
840
841static void
842gen6_ring_put_irq(struct intel_ring_buffer *ring)
843{
844 struct drm_device *dev = ring->dev;
845 drm_i915_private_t *dev_priv = dev->dev_private;
846 unsigned long flags;
847
848 spin_lock_irqsave(&dev_priv->irq_lock, flags);
849 if (--ring->irq_refcount == 0) {
850 I915_WRITE_IMR(ring, ~0);
851 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
852 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
853 POSTING_READ(GTIMR);
854 }
855 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
856
857 gen6_gt_force_wake_put(dev_priv);
858}
859
860static int
861i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
862{
863 int ret;
864
865 ret = intel_ring_begin(ring, 2);
866 if (ret)
867 return ret;
868
869 intel_ring_emit(ring,
870 MI_BATCH_BUFFER_START |
871 MI_BATCH_GTT |
872 MI_BATCH_NON_SECURE_I965);
873 intel_ring_emit(ring, offset);
874 intel_ring_advance(ring);
875
876 return 0;
877}
878
879static int
880i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
881 u32 offset, u32 len)
882{
883 int ret;
884
885 ret = intel_ring_begin(ring, 4);
886 if (ret)
887 return ret;
888
889 intel_ring_emit(ring, MI_BATCH_BUFFER);
890 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
891 intel_ring_emit(ring, offset + len - 8);
892 intel_ring_emit(ring, 0);
893 intel_ring_advance(ring);
894
895 return 0;
896}
897
898static int
899i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
900 u32 offset, u32 len)
901{
902 int ret;
903
904 ret = intel_ring_begin(ring, 2);
905 if (ret)
906 return ret;
907
908 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
909 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
910 intel_ring_advance(ring);
911
912 return 0;
913}
914
915static void cleanup_status_page(struct intel_ring_buffer *ring)
916{
917 struct drm_i915_gem_object *obj;
918
919 obj = ring->status_page.obj;
920 if (obj == NULL)
921 return;
922
923 kunmap(obj->pages[0]);
924 i915_gem_object_unpin(obj);
925 drm_gem_object_unreference(&obj->base);
926 ring->status_page.obj = NULL;
927}
928
929static int init_status_page(struct intel_ring_buffer *ring)
930{
931 struct drm_device *dev = ring->dev;
932 struct drm_i915_gem_object *obj;
933 int ret;
934
935 obj = i915_gem_alloc_object(dev, 4096);
936 if (obj == NULL) {
937 DRM_ERROR("Failed to allocate status page\n");
938 ret = -ENOMEM;
939 goto err;
940 }
941
942 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
943
944 ret = i915_gem_object_pin(obj, 4096, true);
945 if (ret != 0) {
946 goto err_unref;
947 }
948
949 ring->status_page.gfx_addr = obj->gtt_offset;
950 ring->status_page.page_addr = kmap(obj->pages[0]);
951 if (ring->status_page.page_addr == NULL) {
952 goto err_unpin;
953 }
954 ring->status_page.obj = obj;
955 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
956
957 intel_ring_setup_status_page(ring);
958 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
959 ring->name, ring->status_page.gfx_addr);
960
961 return 0;
962
963err_unpin:
964 i915_gem_object_unpin(obj);
965err_unref:
966 drm_gem_object_unreference(&obj->base);
967err:
968 return ret;
969}
970
971static int intel_init_ring_buffer(struct drm_device *dev,
972 struct intel_ring_buffer *ring)
973{
974 struct drm_i915_gem_object *obj;
975 int ret;
976
977 ring->dev = dev;
978 INIT_LIST_HEAD(&ring->active_list);
979 INIT_LIST_HEAD(&ring->request_list);
980 INIT_LIST_HEAD(&ring->gpu_write_list);
981 ring->size = 32 * PAGE_SIZE;
982
983 init_waitqueue_head(&ring->irq_queue);
984
985 if (I915_NEED_GFX_HWS(dev)) {
986 ret = init_status_page(ring);
987 if (ret)
988 return ret;
989 }
990
991 obj = i915_gem_alloc_object(dev, ring->size);
992 if (obj == NULL) {
993 DRM_ERROR("Failed to allocate ringbuffer\n");
994 ret = -ENOMEM;
995 goto err_hws;
996 }
997
998 ring->obj = obj;
999
1000 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
1001 if (ret)
1002 goto err_unref;
1003
1004 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1005 if (ret)
1006 goto err_unpin;
1007
1008 ring->virtual_start = ioremap_wc(dev->agp->base + obj->gtt_offset,
1009 ring->size);
1010 if (ring->virtual_start == NULL) {
1011 DRM_ERROR("Failed to map ringbuffer.\n");
1012 ret = -EINVAL;
1013 goto err_unpin;
1014 }
1015
1016 ret = ring->init(ring);
1017 if (ret)
1018 goto err_unmap;
1019
1020 /* Workaround an erratum on the i830 which causes a hang if
1021 * the TAIL pointer points to within the last 2 cachelines
1022 * of the buffer.
1023 */
1024 ring->effective_size = ring->size;
1025 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1026 ring->effective_size -= 128;
1027
1028 return 0;
1029
1030err_unmap:
1031 iounmap(ring->virtual_start);
1032err_unpin:
1033 i915_gem_object_unpin(obj);
1034err_unref:
1035 drm_gem_object_unreference(&obj->base);
1036 ring->obj = NULL;
1037err_hws:
1038 cleanup_status_page(ring);
1039 return ret;
1040}
1041
1042void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1043{
1044 struct drm_i915_private *dev_priv;
1045 int ret;
1046
1047 if (ring->obj == NULL)
1048 return;
1049
1050 /* Disable the ring buffer. The ring must be idle at this point */
1051 dev_priv = ring->dev->dev_private;
1052 ret = intel_wait_ring_idle(ring);
1053 if (ret)
1054 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1055 ring->name, ret);
1056
1057 I915_WRITE_CTL(ring, 0);
1058
1059 iounmap(ring->virtual_start);
1060
1061 i915_gem_object_unpin(ring->obj);
1062 drm_gem_object_unreference(&ring->obj->base);
1063 ring->obj = NULL;
1064
1065 if (ring->cleanup)
1066 ring->cleanup(ring);
1067
1068 cleanup_status_page(ring);
1069}
1070
1071static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1072{
1073 uint32_t __iomem *virt;
1074 int rem = ring->size - ring->tail;
1075
1076 if (ring->space < rem) {
1077 int ret = intel_wait_ring_buffer(ring, rem);
1078 if (ret)
1079 return ret;
1080 }
1081
1082 virt = ring->virtual_start + ring->tail;
1083 rem /= 4;
1084 while (rem--)
1085 iowrite32(MI_NOOP, virt++);
1086
1087 ring->tail = 0;
1088 ring->space = ring_space(ring);
1089
1090 return 0;
1091}
1092
1093static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1094{
1095 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1096 bool was_interruptible;
1097 int ret;
1098
1099 /* XXX As we have not yet audited all the paths to check that
1100 * they are ready for ERESTARTSYS from intel_ring_begin, do not
1101 * allow us to be interruptible by a signal.
1102 */
1103 was_interruptible = dev_priv->mm.interruptible;
1104 dev_priv->mm.interruptible = false;
1105
1106 ret = i915_wait_request(ring, seqno);
1107
1108 dev_priv->mm.interruptible = was_interruptible;
1109 if (!ret)
1110 i915_gem_retire_requests_ring(ring);
1111
1112 return ret;
1113}
1114
1115static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1116{
1117 struct drm_i915_gem_request *request;
1118 u32 seqno = 0;
1119 int ret;
1120
1121 i915_gem_retire_requests_ring(ring);
1122
1123 if (ring->last_retired_head != -1) {
1124 ring->head = ring->last_retired_head;
1125 ring->last_retired_head = -1;
1126 ring->space = ring_space(ring);
1127 if (ring->space >= n)
1128 return 0;
1129 }
1130
1131 list_for_each_entry(request, &ring->request_list, list) {
1132 int space;
1133
1134 if (request->tail == -1)
1135 continue;
1136
1137 space = request->tail - (ring->tail + 8);
1138 if (space < 0)
1139 space += ring->size;
1140 if (space >= n) {
1141 seqno = request->seqno;
1142 break;
1143 }
1144
1145 /* Consume this request in case we need more space than
1146 * is available and so need to prevent a race between
1147 * updating last_retired_head and direct reads of
1148 * I915_RING_HEAD. It also provides a nice sanity check.
1149 */
1150 request->tail = -1;
1151 }
1152
1153 if (seqno == 0)
1154 return -ENOSPC;
1155
1156 ret = intel_ring_wait_seqno(ring, seqno);
1157 if (ret)
1158 return ret;
1159
1160 if (WARN_ON(ring->last_retired_head == -1))
1161 return -ENOSPC;
1162
1163 ring->head = ring->last_retired_head;
1164 ring->last_retired_head = -1;
1165 ring->space = ring_space(ring);
1166 if (WARN_ON(ring->space < n))
1167 return -ENOSPC;
1168
1169 return 0;
1170}
1171
1172int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1173{
1174 struct drm_device *dev = ring->dev;
1175 struct drm_i915_private *dev_priv = dev->dev_private;
1176 unsigned long end;
1177 int ret;
1178
1179 ret = intel_ring_wait_request(ring, n);
1180 if (ret != -ENOSPC)
1181 return ret;
1182
1183 trace_i915_ring_wait_begin(ring);
1184 /* With GEM the hangcheck timer should kick us out of the loop,
1185 * leaving it early runs the risk of corrupting GEM state (due
1186 * to running on almost untested codepaths). But on resume
1187 * timers don't work yet, so prevent a complete hang in that
1188 * case by choosing an insanely large timeout. */
1189 end = jiffies + 60 * HZ;
1190
1191 do {
1192 ring->head = I915_READ_HEAD(ring);
1193 ring->space = ring_space(ring);
1194 if (ring->space >= n) {
1195 trace_i915_ring_wait_end(ring);
1196 return 0;
1197 }
1198
1199 if (dev->primary->master) {
1200 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1201 if (master_priv->sarea_priv)
1202 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1203 }
1204
1205 msleep(1);
1206 if (atomic_read(&dev_priv->mm.wedged))
1207 return -EAGAIN;
1208 } while (!time_after(jiffies, end));
1209 trace_i915_ring_wait_end(ring);
1210 return -EBUSY;
1211}
1212
1213int intel_ring_begin(struct intel_ring_buffer *ring,
1214 int num_dwords)
1215{
1216 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1217 int n = 4*num_dwords;
1218 int ret;
1219
1220 if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1221 return -EIO;
1222
1223 if (unlikely(ring->tail + n > ring->effective_size)) {
1224 ret = intel_wrap_ring_buffer(ring);
1225 if (unlikely(ret))
1226 return ret;
1227 }
1228
1229 if (unlikely(ring->space < n)) {
1230 ret = intel_wait_ring_buffer(ring, n);
1231 if (unlikely(ret))
1232 return ret;
1233 }
1234
1235 ring->space -= n;
1236 return 0;
1237}
1238
1239void intel_ring_advance(struct intel_ring_buffer *ring)
1240{
1241 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1242
1243 ring->tail &= ring->size - 1;
1244 if (dev_priv->stop_rings & intel_ring_flag(ring))
1245 return;
1246 ring->write_tail(ring, ring->tail);
1247}
1248
1249
1250static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1251 u32 value)
1252{
1253 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1254
1255 /* Every tail move must follow the sequence below */
1256 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1257 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1258 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1259 I915_WRITE(GEN6_BSD_RNCID, 0x0);
1260
1261 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1262 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1263 50))
1264 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1265
1266 I915_WRITE_TAIL(ring, value);
1267 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1268 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1269 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1270}
1271
1272static int gen6_ring_flush(struct intel_ring_buffer *ring,
1273 u32 invalidate, u32 flush)
1274{
1275 uint32_t cmd;
1276 int ret;
1277
1278 ret = intel_ring_begin(ring, 4);
1279 if (ret)
1280 return ret;
1281
1282 cmd = MI_FLUSH_DW;
1283 if (invalidate & I915_GEM_GPU_DOMAINS)
1284 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1285 intel_ring_emit(ring, cmd);
1286 intel_ring_emit(ring, 0);
1287 intel_ring_emit(ring, 0);
1288 intel_ring_emit(ring, MI_NOOP);
1289 intel_ring_advance(ring);
1290 return 0;
1291}
1292
1293static int
1294gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1295 u32 offset, u32 len)
1296{
1297 int ret;
1298
1299 ret = intel_ring_begin(ring, 2);
1300 if (ret)
1301 return ret;
1302
1303 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1304 /* bit0-7 is the length on GEN6+ */
1305 intel_ring_emit(ring, offset);
1306 intel_ring_advance(ring);
1307
1308 return 0;
1309}
1310
1311/* Blitter support (SandyBridge+) */
1312
1313static int blt_ring_flush(struct intel_ring_buffer *ring,
1314 u32 invalidate, u32 flush)
1315{
1316 uint32_t cmd;
1317 int ret;
1318
1319 ret = intel_ring_begin(ring, 4);
1320 if (ret)
1321 return ret;
1322
1323 cmd = MI_FLUSH_DW;
1324 if (invalidate & I915_GEM_DOMAIN_RENDER)
1325 cmd |= MI_INVALIDATE_TLB;
1326 intel_ring_emit(ring, cmd);
1327 intel_ring_emit(ring, 0);
1328 intel_ring_emit(ring, 0);
1329 intel_ring_emit(ring, MI_NOOP);
1330 intel_ring_advance(ring);
1331 return 0;
1332}
1333
1334int intel_init_render_ring_buffer(struct drm_device *dev)
1335{
1336 drm_i915_private_t *dev_priv = dev->dev_private;
1337 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1338
1339 ring->name = "render ring";
1340 ring->id = RCS;
1341 ring->mmio_base = RENDER_RING_BASE;
1342
1343 if (INTEL_INFO(dev)->gen >= 6) {
1344 ring->add_request = gen6_add_request;
1345 ring->flush = gen6_render_ring_flush;
1346 ring->irq_get = gen6_ring_get_irq;
1347 ring->irq_put = gen6_ring_put_irq;
1348 ring->irq_enable_mask = GT_USER_INTERRUPT;
1349 ring->get_seqno = gen6_ring_get_seqno;
1350 ring->sync_to = gen6_ring_sync;
1351 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1352 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1353 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1354 ring->signal_mbox[0] = GEN6_VRSYNC;
1355 ring->signal_mbox[1] = GEN6_BRSYNC;
1356 } else if (IS_GEN5(dev)) {
1357 ring->add_request = pc_render_add_request;
1358 ring->flush = gen4_render_ring_flush;
1359 ring->get_seqno = pc_render_get_seqno;
1360 ring->irq_get = gen5_ring_get_irq;
1361 ring->irq_put = gen5_ring_put_irq;
1362 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1363 } else {
1364 ring->add_request = i9xx_add_request;
1365 if (INTEL_INFO(dev)->gen < 4)
1366 ring->flush = gen2_render_ring_flush;
1367 else
1368 ring->flush = gen4_render_ring_flush;
1369 ring->get_seqno = ring_get_seqno;
1370 if (IS_GEN2(dev)) {
1371 ring->irq_get = i8xx_ring_get_irq;
1372 ring->irq_put = i8xx_ring_put_irq;
1373 } else {
1374 ring->irq_get = i9xx_ring_get_irq;
1375 ring->irq_put = i9xx_ring_put_irq;
1376 }
1377 ring->irq_enable_mask = I915_USER_INTERRUPT;
1378 }
1379 ring->write_tail = ring_write_tail;
1380 if (INTEL_INFO(dev)->gen >= 6)
1381 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1382 else if (INTEL_INFO(dev)->gen >= 4)
1383 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1384 else if (IS_I830(dev) || IS_845G(dev))
1385 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1386 else
1387 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1388 ring->init = init_render_ring;
1389 ring->cleanup = render_ring_cleanup;
1390
1391
1392 if (!I915_NEED_GFX_HWS(dev)) {
1393 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1394 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1395 }
1396
1397 return intel_init_ring_buffer(dev, ring);
1398}
1399
1400int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1401{
1402 drm_i915_private_t *dev_priv = dev->dev_private;
1403 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1404
1405 ring->name = "render ring";
1406 ring->id = RCS;
1407 ring->mmio_base = RENDER_RING_BASE;
1408
1409 if (INTEL_INFO(dev)->gen >= 6) {
1410 /* non-kms not supported on gen6+ */
1411 return -ENODEV;
1412 }
1413
1414 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1415 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1416 * the special gen5 functions. */
1417 ring->add_request = i9xx_add_request;
1418 if (INTEL_INFO(dev)->gen < 4)
1419 ring->flush = gen2_render_ring_flush;
1420 else
1421 ring->flush = gen4_render_ring_flush;
1422 ring->get_seqno = ring_get_seqno;
1423 if (IS_GEN2(dev)) {
1424 ring->irq_get = i8xx_ring_get_irq;
1425 ring->irq_put = i8xx_ring_put_irq;
1426 } else {
1427 ring->irq_get = i9xx_ring_get_irq;
1428 ring->irq_put = i9xx_ring_put_irq;
1429 }
1430 ring->irq_enable_mask = I915_USER_INTERRUPT;
1431 ring->write_tail = ring_write_tail;
1432 if (INTEL_INFO(dev)->gen >= 4)
1433 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1434 else if (IS_I830(dev) || IS_845G(dev))
1435 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1436 else
1437 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1438 ring->init = init_render_ring;
1439 ring->cleanup = render_ring_cleanup;
1440
1441 if (!I915_NEED_GFX_HWS(dev))
1442 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1443
1444 ring->dev = dev;
1445 INIT_LIST_HEAD(&ring->active_list);
1446 INIT_LIST_HEAD(&ring->request_list);
1447 INIT_LIST_HEAD(&ring->gpu_write_list);
1448
1449 ring->size = size;
1450 ring->effective_size = ring->size;
1451 if (IS_I830(ring->dev))
1452 ring->effective_size -= 128;
1453
1454 ring->virtual_start = ioremap_wc(start, size);
1455 if (ring->virtual_start == NULL) {
1456 DRM_ERROR("can not ioremap virtual address for"
1457 " ring buffer\n");
1458 return -ENOMEM;
1459 }
1460
1461 return 0;
1462}
1463
1464int intel_init_bsd_ring_buffer(struct drm_device *dev)
1465{
1466 drm_i915_private_t *dev_priv = dev->dev_private;
1467 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1468
1469 ring->name = "bsd ring";
1470 ring->id = VCS;
1471
1472 ring->write_tail = ring_write_tail;
1473 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1474 ring->mmio_base = GEN6_BSD_RING_BASE;
1475 /* gen6 bsd needs a special wa for tail updates */
1476 if (IS_GEN6(dev))
1477 ring->write_tail = gen6_bsd_ring_write_tail;
1478 ring->flush = gen6_ring_flush;
1479 ring->add_request = gen6_add_request;
1480 ring->get_seqno = gen6_ring_get_seqno;
1481 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1482 ring->irq_get = gen6_ring_get_irq;
1483 ring->irq_put = gen6_ring_put_irq;
1484 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1485 ring->sync_to = gen6_ring_sync;
1486 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1487 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1488 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1489 ring->signal_mbox[0] = GEN6_RVSYNC;
1490 ring->signal_mbox[1] = GEN6_BVSYNC;
1491 } else {
1492 ring->mmio_base = BSD_RING_BASE;
1493 ring->flush = bsd_ring_flush;
1494 ring->add_request = i9xx_add_request;
1495 ring->get_seqno = ring_get_seqno;
1496 if (IS_GEN5(dev)) {
1497 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1498 ring->irq_get = gen5_ring_get_irq;
1499 ring->irq_put = gen5_ring_put_irq;
1500 } else {
1501 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1502 ring->irq_get = i9xx_ring_get_irq;
1503 ring->irq_put = i9xx_ring_put_irq;
1504 }
1505 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1506 }
1507 ring->init = init_ring_common;
1508
1509
1510 return intel_init_ring_buffer(dev, ring);
1511}
1512
1513int intel_init_blt_ring_buffer(struct drm_device *dev)
1514{
1515 drm_i915_private_t *dev_priv = dev->dev_private;
1516 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1517
1518 ring->name = "blitter ring";
1519 ring->id = BCS;
1520
1521 ring->mmio_base = BLT_RING_BASE;
1522 ring->write_tail = ring_write_tail;
1523 ring->flush = blt_ring_flush;
1524 ring->add_request = gen6_add_request;
1525 ring->get_seqno = gen6_ring_get_seqno;
1526 ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1527 ring->irq_get = gen6_ring_get_irq;
1528 ring->irq_put = gen6_ring_put_irq;
1529 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1530 ring->sync_to = gen6_ring_sync;
1531 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1532 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1533 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1534 ring->signal_mbox[0] = GEN6_RBSYNC;
1535 ring->signal_mbox[1] = GEN6_VBSYNC;
1536 ring->init = init_ring_common;
1537
1538 return intel_init_ring_buffer(dev, ring);
1539}