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1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
29#include "radeon.h"
30#include "evergreend.h"
31#include "evergreen_reg_safe.h"
32#include "cayman_reg_safe.h"
33
34static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
35 struct radeon_cs_reloc **cs_reloc);
36
37struct evergreen_cs_track {
38 u32 group_size;
39 u32 nbanks;
40 u32 npipes;
41 /* value we track */
42 u32 nsamples;
43 u32 cb_color_base_last[12];
44 struct radeon_bo *cb_color_bo[12];
45 u32 cb_color_bo_offset[12];
46 struct radeon_bo *cb_color_fmask_bo[8];
47 struct radeon_bo *cb_color_cmask_bo[8];
48 u32 cb_color_info[12];
49 u32 cb_color_view[12];
50 u32 cb_color_pitch_idx[12];
51 u32 cb_color_slice_idx[12];
52 u32 cb_color_dim_idx[12];
53 u32 cb_color_dim[12];
54 u32 cb_color_pitch[12];
55 u32 cb_color_slice[12];
56 u32 cb_color_cmask_slice[8];
57 u32 cb_color_fmask_slice[8];
58 u32 cb_target_mask;
59 u32 cb_shader_mask;
60 u32 vgt_strmout_config;
61 u32 vgt_strmout_buffer_config;
62 u32 db_depth_control;
63 u32 db_depth_view;
64 u32 db_depth_size;
65 u32 db_depth_size_idx;
66 u32 db_z_info;
67 u32 db_z_idx;
68 u32 db_z_read_offset;
69 u32 db_z_write_offset;
70 struct radeon_bo *db_z_read_bo;
71 struct radeon_bo *db_z_write_bo;
72 u32 db_s_info;
73 u32 db_s_idx;
74 u32 db_s_read_offset;
75 u32 db_s_write_offset;
76 struct radeon_bo *db_s_read_bo;
77 struct radeon_bo *db_s_write_bo;
78};
79
80static void evergreen_cs_track_init(struct evergreen_cs_track *track)
81{
82 int i;
83
84 for (i = 0; i < 8; i++) {
85 track->cb_color_fmask_bo[i] = NULL;
86 track->cb_color_cmask_bo[i] = NULL;
87 track->cb_color_cmask_slice[i] = 0;
88 track->cb_color_fmask_slice[i] = 0;
89 }
90
91 for (i = 0; i < 12; i++) {
92 track->cb_color_base_last[i] = 0;
93 track->cb_color_bo[i] = NULL;
94 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
95 track->cb_color_info[i] = 0;
96 track->cb_color_view[i] = 0;
97 track->cb_color_pitch_idx[i] = 0;
98 track->cb_color_slice_idx[i] = 0;
99 track->cb_color_dim[i] = 0;
100 track->cb_color_pitch[i] = 0;
101 track->cb_color_slice[i] = 0;
102 track->cb_color_dim[i] = 0;
103 }
104 track->cb_target_mask = 0xFFFFFFFF;
105 track->cb_shader_mask = 0xFFFFFFFF;
106
107 track->db_depth_view = 0xFFFFC000;
108 track->db_depth_size = 0xFFFFFFFF;
109 track->db_depth_size_idx = 0;
110 track->db_depth_control = 0xFFFFFFFF;
111 track->db_z_info = 0xFFFFFFFF;
112 track->db_z_idx = 0xFFFFFFFF;
113 track->db_z_read_offset = 0xFFFFFFFF;
114 track->db_z_write_offset = 0xFFFFFFFF;
115 track->db_z_read_bo = NULL;
116 track->db_z_write_bo = NULL;
117 track->db_s_info = 0xFFFFFFFF;
118 track->db_s_idx = 0xFFFFFFFF;
119 track->db_s_read_offset = 0xFFFFFFFF;
120 track->db_s_write_offset = 0xFFFFFFFF;
121 track->db_s_read_bo = NULL;
122 track->db_s_write_bo = NULL;
123}
124
125static inline int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
126{
127 /* XXX fill in */
128 return 0;
129}
130
131static int evergreen_cs_track_check(struct radeon_cs_parser *p)
132{
133 struct evergreen_cs_track *track = p->track;
134
135 /* we don't support stream out buffer yet */
136 if (track->vgt_strmout_config || track->vgt_strmout_buffer_config) {
137 dev_warn(p->dev, "this kernel doesn't support SMX output buffer\n");
138 return -EINVAL;
139 }
140
141 /* XXX fill in */
142 return 0;
143}
144
145/**
146 * evergreen_cs_packet_parse() - parse cp packet and point ib index to next packet
147 * @parser: parser structure holding parsing context.
148 * @pkt: where to store packet informations
149 *
150 * Assume that chunk_ib_index is properly set. Will return -EINVAL
151 * if packet is bigger than remaining ib size. or if packets is unknown.
152 **/
153int evergreen_cs_packet_parse(struct radeon_cs_parser *p,
154 struct radeon_cs_packet *pkt,
155 unsigned idx)
156{
157 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
158 uint32_t header;
159
160 if (idx >= ib_chunk->length_dw) {
161 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
162 idx, ib_chunk->length_dw);
163 return -EINVAL;
164 }
165 header = radeon_get_ib_value(p, idx);
166 pkt->idx = idx;
167 pkt->type = CP_PACKET_GET_TYPE(header);
168 pkt->count = CP_PACKET_GET_COUNT(header);
169 pkt->one_reg_wr = 0;
170 switch (pkt->type) {
171 case PACKET_TYPE0:
172 pkt->reg = CP_PACKET0_GET_REG(header);
173 break;
174 case PACKET_TYPE3:
175 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
176 break;
177 case PACKET_TYPE2:
178 pkt->count = -1;
179 break;
180 default:
181 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
182 return -EINVAL;
183 }
184 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
185 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
186 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
187 return -EINVAL;
188 }
189 return 0;
190}
191
192/**
193 * evergreen_cs_packet_next_reloc() - parse next packet which should be reloc packet3
194 * @parser: parser structure holding parsing context.
195 * @data: pointer to relocation data
196 * @offset_start: starting offset
197 * @offset_mask: offset mask (to align start offset on)
198 * @reloc: reloc informations
199 *
200 * Check next packet is relocation packet3, do bo validation and compute
201 * GPU offset using the provided start.
202 **/
203static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
204 struct radeon_cs_reloc **cs_reloc)
205{
206 struct radeon_cs_chunk *relocs_chunk;
207 struct radeon_cs_packet p3reloc;
208 unsigned idx;
209 int r;
210
211 if (p->chunk_relocs_idx == -1) {
212 DRM_ERROR("No relocation chunk !\n");
213 return -EINVAL;
214 }
215 *cs_reloc = NULL;
216 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
217 r = evergreen_cs_packet_parse(p, &p3reloc, p->idx);
218 if (r) {
219 return r;
220 }
221 p->idx += p3reloc.count + 2;
222 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
223 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
224 p3reloc.idx);
225 return -EINVAL;
226 }
227 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
228 if (idx >= relocs_chunk->length_dw) {
229 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
230 idx, relocs_chunk->length_dw);
231 return -EINVAL;
232 }
233 /* FIXME: we assume reloc size is 4 dwords */
234 *cs_reloc = p->relocs_ptr[(idx / 4)];
235 return 0;
236}
237
238/**
239 * evergreen_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
240 * @parser: parser structure holding parsing context.
241 *
242 * Check next packet is relocation packet3, do bo validation and compute
243 * GPU offset using the provided start.
244 **/
245static inline int evergreen_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
246{
247 struct radeon_cs_packet p3reloc;
248 int r;
249
250 r = evergreen_cs_packet_parse(p, &p3reloc, p->idx);
251 if (r) {
252 return 0;
253 }
254 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
255 return 0;
256 }
257 return 1;
258}
259
260/**
261 * evergreen_cs_packet_next_vline() - parse userspace VLINE packet
262 * @parser: parser structure holding parsing context.
263 *
264 * Userspace sends a special sequence for VLINE waits.
265 * PACKET0 - VLINE_START_END + value
266 * PACKET3 - WAIT_REG_MEM poll vline status reg
267 * RELOC (P3) - crtc_id in reloc.
268 *
269 * This function parses this and relocates the VLINE START END
270 * and WAIT_REG_MEM packets to the correct crtc.
271 * It also detects a switched off crtc and nulls out the
272 * wait in that case.
273 */
274static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
275{
276 struct drm_mode_object *obj;
277 struct drm_crtc *crtc;
278 struct radeon_crtc *radeon_crtc;
279 struct radeon_cs_packet p3reloc, wait_reg_mem;
280 int crtc_id;
281 int r;
282 uint32_t header, h_idx, reg, wait_reg_mem_info;
283 volatile uint32_t *ib;
284
285 ib = p->ib->ptr;
286
287 /* parse the WAIT_REG_MEM */
288 r = evergreen_cs_packet_parse(p, &wait_reg_mem, p->idx);
289 if (r)
290 return r;
291
292 /* check its a WAIT_REG_MEM */
293 if (wait_reg_mem.type != PACKET_TYPE3 ||
294 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
295 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
296 return -EINVAL;
297 }
298
299 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
300 /* bit 4 is reg (0) or mem (1) */
301 if (wait_reg_mem_info & 0x10) {
302 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
303 return -EINVAL;
304 }
305 /* waiting for value to be equal */
306 if ((wait_reg_mem_info & 0x7) != 0x3) {
307 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
308 return -EINVAL;
309 }
310 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != EVERGREEN_VLINE_STATUS) {
311 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
312 return -EINVAL;
313 }
314
315 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != EVERGREEN_VLINE_STAT) {
316 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
317 return -EINVAL;
318 }
319
320 /* jump over the NOP */
321 r = evergreen_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
322 if (r)
323 return r;
324
325 h_idx = p->idx - 2;
326 p->idx += wait_reg_mem.count + 2;
327 p->idx += p3reloc.count + 2;
328
329 header = radeon_get_ib_value(p, h_idx);
330 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
331 reg = CP_PACKET0_GET_REG(header);
332 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
333 if (!obj) {
334 DRM_ERROR("cannot find crtc %d\n", crtc_id);
335 return -EINVAL;
336 }
337 crtc = obj_to_crtc(obj);
338 radeon_crtc = to_radeon_crtc(crtc);
339 crtc_id = radeon_crtc->crtc_id;
340
341 if (!crtc->enabled) {
342 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
343 ib[h_idx + 2] = PACKET2(0);
344 ib[h_idx + 3] = PACKET2(0);
345 ib[h_idx + 4] = PACKET2(0);
346 ib[h_idx + 5] = PACKET2(0);
347 ib[h_idx + 6] = PACKET2(0);
348 ib[h_idx + 7] = PACKET2(0);
349 ib[h_idx + 8] = PACKET2(0);
350 } else {
351 switch (reg) {
352 case EVERGREEN_VLINE_START_END:
353 header &= ~R600_CP_PACKET0_REG_MASK;
354 header |= (EVERGREEN_VLINE_START_END + radeon_crtc->crtc_offset) >> 2;
355 ib[h_idx] = header;
356 ib[h_idx + 4] = (EVERGREEN_VLINE_STATUS + radeon_crtc->crtc_offset) >> 2;
357 break;
358 default:
359 DRM_ERROR("unknown crtc reloc\n");
360 return -EINVAL;
361 }
362 }
363 return 0;
364}
365
366static int evergreen_packet0_check(struct radeon_cs_parser *p,
367 struct radeon_cs_packet *pkt,
368 unsigned idx, unsigned reg)
369{
370 int r;
371
372 switch (reg) {
373 case EVERGREEN_VLINE_START_END:
374 r = evergreen_cs_packet_parse_vline(p);
375 if (r) {
376 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
377 idx, reg);
378 return r;
379 }
380 break;
381 default:
382 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
383 reg, idx);
384 return -EINVAL;
385 }
386 return 0;
387}
388
389static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p,
390 struct radeon_cs_packet *pkt)
391{
392 unsigned reg, i;
393 unsigned idx;
394 int r;
395
396 idx = pkt->idx + 1;
397 reg = pkt->reg;
398 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
399 r = evergreen_packet0_check(p, pkt, idx, reg);
400 if (r) {
401 return r;
402 }
403 }
404 return 0;
405}
406
407/**
408 * evergreen_cs_check_reg() - check if register is authorized or not
409 * @parser: parser structure holding parsing context
410 * @reg: register we are testing
411 * @idx: index into the cs buffer
412 *
413 * This function will test against evergreen_reg_safe_bm and return 0
414 * if register is safe. If register is not flag as safe this function
415 * will test it against a list of register needind special handling.
416 */
417static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
418{
419 struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;
420 struct radeon_cs_reloc *reloc;
421 u32 last_reg;
422 u32 m, i, tmp, *ib;
423 int r;
424
425 if (p->rdev->family >= CHIP_CAYMAN)
426 last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
427 else
428 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
429
430 i = (reg >> 7);
431 if (i >= last_reg) {
432 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
433 return -EINVAL;
434 }
435 m = 1 << ((reg >> 2) & 31);
436 if (p->rdev->family >= CHIP_CAYMAN) {
437 if (!(cayman_reg_safe_bm[i] & m))
438 return 0;
439 } else {
440 if (!(evergreen_reg_safe_bm[i] & m))
441 return 0;
442 }
443 ib = p->ib->ptr;
444 switch (reg) {
445 /* force following reg to 0 in an attempt to disable out buffer
446 * which will need us to better understand how it works to perform
447 * security check on it (Jerome)
448 */
449 case SQ_ESGS_RING_SIZE:
450 case SQ_GSVS_RING_SIZE:
451 case SQ_ESTMP_RING_SIZE:
452 case SQ_GSTMP_RING_SIZE:
453 case SQ_HSTMP_RING_SIZE:
454 case SQ_LSTMP_RING_SIZE:
455 case SQ_PSTMP_RING_SIZE:
456 case SQ_VSTMP_RING_SIZE:
457 case SQ_ESGS_RING_ITEMSIZE:
458 case SQ_ESTMP_RING_ITEMSIZE:
459 case SQ_GSTMP_RING_ITEMSIZE:
460 case SQ_GSVS_RING_ITEMSIZE:
461 case SQ_GS_VERT_ITEMSIZE:
462 case SQ_GS_VERT_ITEMSIZE_1:
463 case SQ_GS_VERT_ITEMSIZE_2:
464 case SQ_GS_VERT_ITEMSIZE_3:
465 case SQ_GSVS_RING_OFFSET_1:
466 case SQ_GSVS_RING_OFFSET_2:
467 case SQ_GSVS_RING_OFFSET_3:
468 case SQ_HSTMP_RING_ITEMSIZE:
469 case SQ_LSTMP_RING_ITEMSIZE:
470 case SQ_PSTMP_RING_ITEMSIZE:
471 case SQ_VSTMP_RING_ITEMSIZE:
472 case VGT_TF_RING_SIZE:
473 /* get value to populate the IB don't remove */
474 /*tmp =radeon_get_ib_value(p, idx);
475 ib[idx] = 0;*/
476 break;
477 case SQ_ESGS_RING_BASE:
478 case SQ_GSVS_RING_BASE:
479 case SQ_ESTMP_RING_BASE:
480 case SQ_GSTMP_RING_BASE:
481 case SQ_HSTMP_RING_BASE:
482 case SQ_LSTMP_RING_BASE:
483 case SQ_PSTMP_RING_BASE:
484 case SQ_VSTMP_RING_BASE:
485 r = evergreen_cs_packet_next_reloc(p, &reloc);
486 if (r) {
487 dev_warn(p->dev, "bad SET_CONTEXT_REG "
488 "0x%04X\n", reg);
489 return -EINVAL;
490 }
491 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
492 break;
493 case DB_DEPTH_CONTROL:
494 track->db_depth_control = radeon_get_ib_value(p, idx);
495 break;
496 case CAYMAN_DB_EQAA:
497 if (p->rdev->family < CHIP_CAYMAN) {
498 dev_warn(p->dev, "bad SET_CONTEXT_REG "
499 "0x%04X\n", reg);
500 return -EINVAL;
501 }
502 break;
503 case CAYMAN_DB_DEPTH_INFO:
504 if (p->rdev->family < CHIP_CAYMAN) {
505 dev_warn(p->dev, "bad SET_CONTEXT_REG "
506 "0x%04X\n", reg);
507 return -EINVAL;
508 }
509 break;
510 case DB_Z_INFO:
511 r = evergreen_cs_packet_next_reloc(p, &reloc);
512 if (r) {
513 dev_warn(p->dev, "bad SET_CONTEXT_REG "
514 "0x%04X\n", reg);
515 return -EINVAL;
516 }
517 track->db_z_info = radeon_get_ib_value(p, idx);
518 ib[idx] &= ~Z_ARRAY_MODE(0xf);
519 track->db_z_info &= ~Z_ARRAY_MODE(0xf);
520 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
521 ib[idx] |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
522 track->db_z_info |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
523 } else {
524 ib[idx] |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
525 track->db_z_info |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
526 }
527 break;
528 case DB_STENCIL_INFO:
529 track->db_s_info = radeon_get_ib_value(p, idx);
530 break;
531 case DB_DEPTH_VIEW:
532 track->db_depth_view = radeon_get_ib_value(p, idx);
533 break;
534 case DB_DEPTH_SIZE:
535 track->db_depth_size = radeon_get_ib_value(p, idx);
536 track->db_depth_size_idx = idx;
537 break;
538 case DB_Z_READ_BASE:
539 r = evergreen_cs_packet_next_reloc(p, &reloc);
540 if (r) {
541 dev_warn(p->dev, "bad SET_CONTEXT_REG "
542 "0x%04X\n", reg);
543 return -EINVAL;
544 }
545 track->db_z_read_offset = radeon_get_ib_value(p, idx);
546 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
547 track->db_z_read_bo = reloc->robj;
548 break;
549 case DB_Z_WRITE_BASE:
550 r = evergreen_cs_packet_next_reloc(p, &reloc);
551 if (r) {
552 dev_warn(p->dev, "bad SET_CONTEXT_REG "
553 "0x%04X\n", reg);
554 return -EINVAL;
555 }
556 track->db_z_write_offset = radeon_get_ib_value(p, idx);
557 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
558 track->db_z_write_bo = reloc->robj;
559 break;
560 case DB_STENCIL_READ_BASE:
561 r = evergreen_cs_packet_next_reloc(p, &reloc);
562 if (r) {
563 dev_warn(p->dev, "bad SET_CONTEXT_REG "
564 "0x%04X\n", reg);
565 return -EINVAL;
566 }
567 track->db_s_read_offset = radeon_get_ib_value(p, idx);
568 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
569 track->db_s_read_bo = reloc->robj;
570 break;
571 case DB_STENCIL_WRITE_BASE:
572 r = evergreen_cs_packet_next_reloc(p, &reloc);
573 if (r) {
574 dev_warn(p->dev, "bad SET_CONTEXT_REG "
575 "0x%04X\n", reg);
576 return -EINVAL;
577 }
578 track->db_s_write_offset = radeon_get_ib_value(p, idx);
579 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
580 track->db_s_write_bo = reloc->robj;
581 break;
582 case VGT_STRMOUT_CONFIG:
583 track->vgt_strmout_config = radeon_get_ib_value(p, idx);
584 break;
585 case VGT_STRMOUT_BUFFER_CONFIG:
586 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx);
587 break;
588 case CB_TARGET_MASK:
589 track->cb_target_mask = radeon_get_ib_value(p, idx);
590 break;
591 case CB_SHADER_MASK:
592 track->cb_shader_mask = radeon_get_ib_value(p, idx);
593 break;
594 case PA_SC_AA_CONFIG:
595 if (p->rdev->family >= CHIP_CAYMAN) {
596 dev_warn(p->dev, "bad SET_CONTEXT_REG "
597 "0x%04X\n", reg);
598 return -EINVAL;
599 }
600 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
601 track->nsamples = 1 << tmp;
602 break;
603 case CAYMAN_PA_SC_AA_CONFIG:
604 if (p->rdev->family < CHIP_CAYMAN) {
605 dev_warn(p->dev, "bad SET_CONTEXT_REG "
606 "0x%04X\n", reg);
607 return -EINVAL;
608 }
609 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;
610 track->nsamples = 1 << tmp;
611 break;
612 case CB_COLOR0_VIEW:
613 case CB_COLOR1_VIEW:
614 case CB_COLOR2_VIEW:
615 case CB_COLOR3_VIEW:
616 case CB_COLOR4_VIEW:
617 case CB_COLOR5_VIEW:
618 case CB_COLOR6_VIEW:
619 case CB_COLOR7_VIEW:
620 tmp = (reg - CB_COLOR0_VIEW) / 0x3c;
621 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
622 break;
623 case CB_COLOR8_VIEW:
624 case CB_COLOR9_VIEW:
625 case CB_COLOR10_VIEW:
626 case CB_COLOR11_VIEW:
627 tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8;
628 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
629 break;
630 case CB_COLOR0_INFO:
631 case CB_COLOR1_INFO:
632 case CB_COLOR2_INFO:
633 case CB_COLOR3_INFO:
634 case CB_COLOR4_INFO:
635 case CB_COLOR5_INFO:
636 case CB_COLOR6_INFO:
637 case CB_COLOR7_INFO:
638 r = evergreen_cs_packet_next_reloc(p, &reloc);
639 if (r) {
640 dev_warn(p->dev, "bad SET_CONTEXT_REG "
641 "0x%04X\n", reg);
642 return -EINVAL;
643 }
644 tmp = (reg - CB_COLOR0_INFO) / 0x3c;
645 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
646 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
647 ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
648 track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
649 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
650 ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
651 track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
652 }
653 break;
654 case CB_COLOR8_INFO:
655 case CB_COLOR9_INFO:
656 case CB_COLOR10_INFO:
657 case CB_COLOR11_INFO:
658 r = evergreen_cs_packet_next_reloc(p, &reloc);
659 if (r) {
660 dev_warn(p->dev, "bad SET_CONTEXT_REG "
661 "0x%04X\n", reg);
662 return -EINVAL;
663 }
664 tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8;
665 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
666 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
667 ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
668 track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
669 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
670 ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
671 track->cb_color_info[tmp] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
672 }
673 break;
674 case CB_COLOR0_PITCH:
675 case CB_COLOR1_PITCH:
676 case CB_COLOR2_PITCH:
677 case CB_COLOR3_PITCH:
678 case CB_COLOR4_PITCH:
679 case CB_COLOR5_PITCH:
680 case CB_COLOR6_PITCH:
681 case CB_COLOR7_PITCH:
682 tmp = (reg - CB_COLOR0_PITCH) / 0x3c;
683 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
684 track->cb_color_pitch_idx[tmp] = idx;
685 break;
686 case CB_COLOR8_PITCH:
687 case CB_COLOR9_PITCH:
688 case CB_COLOR10_PITCH:
689 case CB_COLOR11_PITCH:
690 tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8;
691 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
692 track->cb_color_pitch_idx[tmp] = idx;
693 break;
694 case CB_COLOR0_SLICE:
695 case CB_COLOR1_SLICE:
696 case CB_COLOR2_SLICE:
697 case CB_COLOR3_SLICE:
698 case CB_COLOR4_SLICE:
699 case CB_COLOR5_SLICE:
700 case CB_COLOR6_SLICE:
701 case CB_COLOR7_SLICE:
702 tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
703 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
704 track->cb_color_slice_idx[tmp] = idx;
705 break;
706 case CB_COLOR8_SLICE:
707 case CB_COLOR9_SLICE:
708 case CB_COLOR10_SLICE:
709 case CB_COLOR11_SLICE:
710 tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
711 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
712 track->cb_color_slice_idx[tmp] = idx;
713 break;
714 case CB_COLOR0_ATTRIB:
715 case CB_COLOR1_ATTRIB:
716 case CB_COLOR2_ATTRIB:
717 case CB_COLOR3_ATTRIB:
718 case CB_COLOR4_ATTRIB:
719 case CB_COLOR5_ATTRIB:
720 case CB_COLOR6_ATTRIB:
721 case CB_COLOR7_ATTRIB:
722 case CB_COLOR8_ATTRIB:
723 case CB_COLOR9_ATTRIB:
724 case CB_COLOR10_ATTRIB:
725 case CB_COLOR11_ATTRIB:
726 break;
727 case CB_COLOR0_DIM:
728 case CB_COLOR1_DIM:
729 case CB_COLOR2_DIM:
730 case CB_COLOR3_DIM:
731 case CB_COLOR4_DIM:
732 case CB_COLOR5_DIM:
733 case CB_COLOR6_DIM:
734 case CB_COLOR7_DIM:
735 tmp = (reg - CB_COLOR0_DIM) / 0x3c;
736 track->cb_color_dim[tmp] = radeon_get_ib_value(p, idx);
737 track->cb_color_dim_idx[tmp] = idx;
738 break;
739 case CB_COLOR8_DIM:
740 case CB_COLOR9_DIM:
741 case CB_COLOR10_DIM:
742 case CB_COLOR11_DIM:
743 tmp = ((reg - CB_COLOR8_DIM) / 0x1c) + 8;
744 track->cb_color_dim[tmp] = radeon_get_ib_value(p, idx);
745 track->cb_color_dim_idx[tmp] = idx;
746 break;
747 case CB_COLOR0_FMASK:
748 case CB_COLOR1_FMASK:
749 case CB_COLOR2_FMASK:
750 case CB_COLOR3_FMASK:
751 case CB_COLOR4_FMASK:
752 case CB_COLOR5_FMASK:
753 case CB_COLOR6_FMASK:
754 case CB_COLOR7_FMASK:
755 tmp = (reg - CB_COLOR0_FMASK) / 0x3c;
756 r = evergreen_cs_packet_next_reloc(p, &reloc);
757 if (r) {
758 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
759 return -EINVAL;
760 }
761 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
762 track->cb_color_fmask_bo[tmp] = reloc->robj;
763 break;
764 case CB_COLOR0_CMASK:
765 case CB_COLOR1_CMASK:
766 case CB_COLOR2_CMASK:
767 case CB_COLOR3_CMASK:
768 case CB_COLOR4_CMASK:
769 case CB_COLOR5_CMASK:
770 case CB_COLOR6_CMASK:
771 case CB_COLOR7_CMASK:
772 tmp = (reg - CB_COLOR0_CMASK) / 0x3c;
773 r = evergreen_cs_packet_next_reloc(p, &reloc);
774 if (r) {
775 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
776 return -EINVAL;
777 }
778 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
779 track->cb_color_cmask_bo[tmp] = reloc->robj;
780 break;
781 case CB_COLOR0_FMASK_SLICE:
782 case CB_COLOR1_FMASK_SLICE:
783 case CB_COLOR2_FMASK_SLICE:
784 case CB_COLOR3_FMASK_SLICE:
785 case CB_COLOR4_FMASK_SLICE:
786 case CB_COLOR5_FMASK_SLICE:
787 case CB_COLOR6_FMASK_SLICE:
788 case CB_COLOR7_FMASK_SLICE:
789 tmp = (reg - CB_COLOR0_FMASK_SLICE) / 0x3c;
790 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx);
791 break;
792 case CB_COLOR0_CMASK_SLICE:
793 case CB_COLOR1_CMASK_SLICE:
794 case CB_COLOR2_CMASK_SLICE:
795 case CB_COLOR3_CMASK_SLICE:
796 case CB_COLOR4_CMASK_SLICE:
797 case CB_COLOR5_CMASK_SLICE:
798 case CB_COLOR6_CMASK_SLICE:
799 case CB_COLOR7_CMASK_SLICE:
800 tmp = (reg - CB_COLOR0_CMASK_SLICE) / 0x3c;
801 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx);
802 break;
803 case CB_COLOR0_BASE:
804 case CB_COLOR1_BASE:
805 case CB_COLOR2_BASE:
806 case CB_COLOR3_BASE:
807 case CB_COLOR4_BASE:
808 case CB_COLOR5_BASE:
809 case CB_COLOR6_BASE:
810 case CB_COLOR7_BASE:
811 r = evergreen_cs_packet_next_reloc(p, &reloc);
812 if (r) {
813 dev_warn(p->dev, "bad SET_CONTEXT_REG "
814 "0x%04X\n", reg);
815 return -EINVAL;
816 }
817 tmp = (reg - CB_COLOR0_BASE) / 0x3c;
818 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
819 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
820 track->cb_color_base_last[tmp] = ib[idx];
821 track->cb_color_bo[tmp] = reloc->robj;
822 break;
823 case CB_COLOR8_BASE:
824 case CB_COLOR9_BASE:
825 case CB_COLOR10_BASE:
826 case CB_COLOR11_BASE:
827 r = evergreen_cs_packet_next_reloc(p, &reloc);
828 if (r) {
829 dev_warn(p->dev, "bad SET_CONTEXT_REG "
830 "0x%04X\n", reg);
831 return -EINVAL;
832 }
833 tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8;
834 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
835 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
836 track->cb_color_base_last[tmp] = ib[idx];
837 track->cb_color_bo[tmp] = reloc->robj;
838 break;
839 case CB_IMMED0_BASE:
840 case CB_IMMED1_BASE:
841 case CB_IMMED2_BASE:
842 case CB_IMMED3_BASE:
843 case CB_IMMED4_BASE:
844 case CB_IMMED5_BASE:
845 case CB_IMMED6_BASE:
846 case CB_IMMED7_BASE:
847 case CB_IMMED8_BASE:
848 case CB_IMMED9_BASE:
849 case CB_IMMED10_BASE:
850 case CB_IMMED11_BASE:
851 case DB_HTILE_DATA_BASE:
852 case SQ_PGM_START_FS:
853 case SQ_PGM_START_ES:
854 case SQ_PGM_START_VS:
855 case SQ_PGM_START_GS:
856 case SQ_PGM_START_PS:
857 case SQ_PGM_START_HS:
858 case SQ_PGM_START_LS:
859 case SQ_CONST_MEM_BASE:
860 case SQ_ALU_CONST_CACHE_GS_0:
861 case SQ_ALU_CONST_CACHE_GS_1:
862 case SQ_ALU_CONST_CACHE_GS_2:
863 case SQ_ALU_CONST_CACHE_GS_3:
864 case SQ_ALU_CONST_CACHE_GS_4:
865 case SQ_ALU_CONST_CACHE_GS_5:
866 case SQ_ALU_CONST_CACHE_GS_6:
867 case SQ_ALU_CONST_CACHE_GS_7:
868 case SQ_ALU_CONST_CACHE_GS_8:
869 case SQ_ALU_CONST_CACHE_GS_9:
870 case SQ_ALU_CONST_CACHE_GS_10:
871 case SQ_ALU_CONST_CACHE_GS_11:
872 case SQ_ALU_CONST_CACHE_GS_12:
873 case SQ_ALU_CONST_CACHE_GS_13:
874 case SQ_ALU_CONST_CACHE_GS_14:
875 case SQ_ALU_CONST_CACHE_GS_15:
876 case SQ_ALU_CONST_CACHE_PS_0:
877 case SQ_ALU_CONST_CACHE_PS_1:
878 case SQ_ALU_CONST_CACHE_PS_2:
879 case SQ_ALU_CONST_CACHE_PS_3:
880 case SQ_ALU_CONST_CACHE_PS_4:
881 case SQ_ALU_CONST_CACHE_PS_5:
882 case SQ_ALU_CONST_CACHE_PS_6:
883 case SQ_ALU_CONST_CACHE_PS_7:
884 case SQ_ALU_CONST_CACHE_PS_8:
885 case SQ_ALU_CONST_CACHE_PS_9:
886 case SQ_ALU_CONST_CACHE_PS_10:
887 case SQ_ALU_CONST_CACHE_PS_11:
888 case SQ_ALU_CONST_CACHE_PS_12:
889 case SQ_ALU_CONST_CACHE_PS_13:
890 case SQ_ALU_CONST_CACHE_PS_14:
891 case SQ_ALU_CONST_CACHE_PS_15:
892 case SQ_ALU_CONST_CACHE_VS_0:
893 case SQ_ALU_CONST_CACHE_VS_1:
894 case SQ_ALU_CONST_CACHE_VS_2:
895 case SQ_ALU_CONST_CACHE_VS_3:
896 case SQ_ALU_CONST_CACHE_VS_4:
897 case SQ_ALU_CONST_CACHE_VS_5:
898 case SQ_ALU_CONST_CACHE_VS_6:
899 case SQ_ALU_CONST_CACHE_VS_7:
900 case SQ_ALU_CONST_CACHE_VS_8:
901 case SQ_ALU_CONST_CACHE_VS_9:
902 case SQ_ALU_CONST_CACHE_VS_10:
903 case SQ_ALU_CONST_CACHE_VS_11:
904 case SQ_ALU_CONST_CACHE_VS_12:
905 case SQ_ALU_CONST_CACHE_VS_13:
906 case SQ_ALU_CONST_CACHE_VS_14:
907 case SQ_ALU_CONST_CACHE_VS_15:
908 case SQ_ALU_CONST_CACHE_HS_0:
909 case SQ_ALU_CONST_CACHE_HS_1:
910 case SQ_ALU_CONST_CACHE_HS_2:
911 case SQ_ALU_CONST_CACHE_HS_3:
912 case SQ_ALU_CONST_CACHE_HS_4:
913 case SQ_ALU_CONST_CACHE_HS_5:
914 case SQ_ALU_CONST_CACHE_HS_6:
915 case SQ_ALU_CONST_CACHE_HS_7:
916 case SQ_ALU_CONST_CACHE_HS_8:
917 case SQ_ALU_CONST_CACHE_HS_9:
918 case SQ_ALU_CONST_CACHE_HS_10:
919 case SQ_ALU_CONST_CACHE_HS_11:
920 case SQ_ALU_CONST_CACHE_HS_12:
921 case SQ_ALU_CONST_CACHE_HS_13:
922 case SQ_ALU_CONST_CACHE_HS_14:
923 case SQ_ALU_CONST_CACHE_HS_15:
924 case SQ_ALU_CONST_CACHE_LS_0:
925 case SQ_ALU_CONST_CACHE_LS_1:
926 case SQ_ALU_CONST_CACHE_LS_2:
927 case SQ_ALU_CONST_CACHE_LS_3:
928 case SQ_ALU_CONST_CACHE_LS_4:
929 case SQ_ALU_CONST_CACHE_LS_5:
930 case SQ_ALU_CONST_CACHE_LS_6:
931 case SQ_ALU_CONST_CACHE_LS_7:
932 case SQ_ALU_CONST_CACHE_LS_8:
933 case SQ_ALU_CONST_CACHE_LS_9:
934 case SQ_ALU_CONST_CACHE_LS_10:
935 case SQ_ALU_CONST_CACHE_LS_11:
936 case SQ_ALU_CONST_CACHE_LS_12:
937 case SQ_ALU_CONST_CACHE_LS_13:
938 case SQ_ALU_CONST_CACHE_LS_14:
939 case SQ_ALU_CONST_CACHE_LS_15:
940 r = evergreen_cs_packet_next_reloc(p, &reloc);
941 if (r) {
942 dev_warn(p->dev, "bad SET_CONTEXT_REG "
943 "0x%04X\n", reg);
944 return -EINVAL;
945 }
946 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
947 break;
948 case SX_MEMORY_EXPORT_BASE:
949 if (p->rdev->family >= CHIP_CAYMAN) {
950 dev_warn(p->dev, "bad SET_CONFIG_REG "
951 "0x%04X\n", reg);
952 return -EINVAL;
953 }
954 r = evergreen_cs_packet_next_reloc(p, &reloc);
955 if (r) {
956 dev_warn(p->dev, "bad SET_CONFIG_REG "
957 "0x%04X\n", reg);
958 return -EINVAL;
959 }
960 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
961 break;
962 case CAYMAN_SX_SCATTER_EXPORT_BASE:
963 if (p->rdev->family < CHIP_CAYMAN) {
964 dev_warn(p->dev, "bad SET_CONTEXT_REG "
965 "0x%04X\n", reg);
966 return -EINVAL;
967 }
968 r = evergreen_cs_packet_next_reloc(p, &reloc);
969 if (r) {
970 dev_warn(p->dev, "bad SET_CONTEXT_REG "
971 "0x%04X\n", reg);
972 return -EINVAL;
973 }
974 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
975 break;
976 default:
977 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
978 return -EINVAL;
979 }
980 return 0;
981}
982
983/**
984 * evergreen_check_texture_resource() - check if register is authorized or not
985 * @p: parser structure holding parsing context
986 * @idx: index into the cs buffer
987 * @texture: texture's bo structure
988 * @mipmap: mipmap's bo structure
989 *
990 * This function will check that the resource has valid field and that
991 * the texture and mipmap bo object are big enough to cover this resource.
992 */
993static inline int evergreen_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
994 struct radeon_bo *texture,
995 struct radeon_bo *mipmap)
996{
997 /* XXX fill in */
998 return 0;
999}
1000
1001static int evergreen_packet3_check(struct radeon_cs_parser *p,
1002 struct radeon_cs_packet *pkt)
1003{
1004 struct radeon_cs_reloc *reloc;
1005 struct evergreen_cs_track *track;
1006 volatile u32 *ib;
1007 unsigned idx;
1008 unsigned i;
1009 unsigned start_reg, end_reg, reg;
1010 int r;
1011 u32 idx_value;
1012
1013 track = (struct evergreen_cs_track *)p->track;
1014 ib = p->ib->ptr;
1015 idx = pkt->idx + 1;
1016 idx_value = radeon_get_ib_value(p, idx);
1017
1018 switch (pkt->opcode) {
1019 case PACKET3_SET_PREDICATION:
1020 {
1021 int pred_op;
1022 int tmp;
1023 if (pkt->count != 1) {
1024 DRM_ERROR("bad SET PREDICATION\n");
1025 return -EINVAL;
1026 }
1027
1028 tmp = radeon_get_ib_value(p, idx + 1);
1029 pred_op = (tmp >> 16) & 0x7;
1030
1031 /* for the clear predicate operation */
1032 if (pred_op == 0)
1033 return 0;
1034
1035 if (pred_op > 2) {
1036 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1037 return -EINVAL;
1038 }
1039
1040 r = evergreen_cs_packet_next_reloc(p, &reloc);
1041 if (r) {
1042 DRM_ERROR("bad SET PREDICATION\n");
1043 return -EINVAL;
1044 }
1045
1046 ib[idx + 0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1047 ib[idx + 1] = tmp + (upper_32_bits(reloc->lobj.gpu_offset) & 0xff);
1048 }
1049 break;
1050 case PACKET3_CONTEXT_CONTROL:
1051 if (pkt->count != 1) {
1052 DRM_ERROR("bad CONTEXT_CONTROL\n");
1053 return -EINVAL;
1054 }
1055 break;
1056 case PACKET3_INDEX_TYPE:
1057 case PACKET3_NUM_INSTANCES:
1058 case PACKET3_CLEAR_STATE:
1059 if (pkt->count) {
1060 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
1061 return -EINVAL;
1062 }
1063 break;
1064 case CAYMAN_PACKET3_DEALLOC_STATE:
1065 if (p->rdev->family < CHIP_CAYMAN) {
1066 DRM_ERROR("bad PACKET3_DEALLOC_STATE\n");
1067 return -EINVAL;
1068 }
1069 if (pkt->count) {
1070 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
1071 return -EINVAL;
1072 }
1073 break;
1074 case PACKET3_INDEX_BASE:
1075 if (pkt->count != 1) {
1076 DRM_ERROR("bad INDEX_BASE\n");
1077 return -EINVAL;
1078 }
1079 r = evergreen_cs_packet_next_reloc(p, &reloc);
1080 if (r) {
1081 DRM_ERROR("bad INDEX_BASE\n");
1082 return -EINVAL;
1083 }
1084 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1085 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1086 r = evergreen_cs_track_check(p);
1087 if (r) {
1088 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1089 return r;
1090 }
1091 break;
1092 case PACKET3_DRAW_INDEX:
1093 if (pkt->count != 3) {
1094 DRM_ERROR("bad DRAW_INDEX\n");
1095 return -EINVAL;
1096 }
1097 r = evergreen_cs_packet_next_reloc(p, &reloc);
1098 if (r) {
1099 DRM_ERROR("bad DRAW_INDEX\n");
1100 return -EINVAL;
1101 }
1102 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1103 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1104 r = evergreen_cs_track_check(p);
1105 if (r) {
1106 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1107 return r;
1108 }
1109 break;
1110 case PACKET3_DRAW_INDEX_2:
1111 if (pkt->count != 4) {
1112 DRM_ERROR("bad DRAW_INDEX_2\n");
1113 return -EINVAL;
1114 }
1115 r = evergreen_cs_packet_next_reloc(p, &reloc);
1116 if (r) {
1117 DRM_ERROR("bad DRAW_INDEX_2\n");
1118 return -EINVAL;
1119 }
1120 ib[idx+1] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1121 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1122 r = evergreen_cs_track_check(p);
1123 if (r) {
1124 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1125 return r;
1126 }
1127 break;
1128 case PACKET3_DRAW_INDEX_AUTO:
1129 if (pkt->count != 1) {
1130 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1131 return -EINVAL;
1132 }
1133 r = evergreen_cs_track_check(p);
1134 if (r) {
1135 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1136 return r;
1137 }
1138 break;
1139 case PACKET3_DRAW_INDEX_MULTI_AUTO:
1140 if (pkt->count != 2) {
1141 DRM_ERROR("bad DRAW_INDEX_MULTI_AUTO\n");
1142 return -EINVAL;
1143 }
1144 r = evergreen_cs_track_check(p);
1145 if (r) {
1146 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1147 return r;
1148 }
1149 break;
1150 case PACKET3_DRAW_INDEX_IMMD:
1151 if (pkt->count < 2) {
1152 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1153 return -EINVAL;
1154 }
1155 r = evergreen_cs_track_check(p);
1156 if (r) {
1157 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1158 return r;
1159 }
1160 break;
1161 case PACKET3_DRAW_INDEX_OFFSET:
1162 if (pkt->count != 2) {
1163 DRM_ERROR("bad DRAW_INDEX_OFFSET\n");
1164 return -EINVAL;
1165 }
1166 r = evergreen_cs_track_check(p);
1167 if (r) {
1168 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1169 return r;
1170 }
1171 break;
1172 case PACKET3_DRAW_INDEX_OFFSET_2:
1173 if (pkt->count != 3) {
1174 DRM_ERROR("bad DRAW_INDEX_OFFSET_2\n");
1175 return -EINVAL;
1176 }
1177 r = evergreen_cs_track_check(p);
1178 if (r) {
1179 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1180 return r;
1181 }
1182 break;
1183 case PACKET3_DISPATCH_DIRECT:
1184 if (pkt->count != 3) {
1185 DRM_ERROR("bad DISPATCH_DIRECT\n");
1186 return -EINVAL;
1187 }
1188 r = evergreen_cs_track_check(p);
1189 if (r) {
1190 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1191 return r;
1192 }
1193 break;
1194 case PACKET3_DISPATCH_INDIRECT:
1195 if (pkt->count != 1) {
1196 DRM_ERROR("bad DISPATCH_INDIRECT\n");
1197 return -EINVAL;
1198 }
1199 r = evergreen_cs_packet_next_reloc(p, &reloc);
1200 if (r) {
1201 DRM_ERROR("bad DISPATCH_INDIRECT\n");
1202 return -EINVAL;
1203 }
1204 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1205 r = evergreen_cs_track_check(p);
1206 if (r) {
1207 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1208 return r;
1209 }
1210 break;
1211 case PACKET3_WAIT_REG_MEM:
1212 if (pkt->count != 5) {
1213 DRM_ERROR("bad WAIT_REG_MEM\n");
1214 return -EINVAL;
1215 }
1216 /* bit 4 is reg (0) or mem (1) */
1217 if (idx_value & 0x10) {
1218 r = evergreen_cs_packet_next_reloc(p, &reloc);
1219 if (r) {
1220 DRM_ERROR("bad WAIT_REG_MEM\n");
1221 return -EINVAL;
1222 }
1223 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1224 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1225 }
1226 break;
1227 case PACKET3_SURFACE_SYNC:
1228 if (pkt->count != 3) {
1229 DRM_ERROR("bad SURFACE_SYNC\n");
1230 return -EINVAL;
1231 }
1232 /* 0xffffffff/0x0 is flush all cache flag */
1233 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1234 radeon_get_ib_value(p, idx + 2) != 0) {
1235 r = evergreen_cs_packet_next_reloc(p, &reloc);
1236 if (r) {
1237 DRM_ERROR("bad SURFACE_SYNC\n");
1238 return -EINVAL;
1239 }
1240 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1241 }
1242 break;
1243 case PACKET3_EVENT_WRITE:
1244 if (pkt->count != 2 && pkt->count != 0) {
1245 DRM_ERROR("bad EVENT_WRITE\n");
1246 return -EINVAL;
1247 }
1248 if (pkt->count) {
1249 r = evergreen_cs_packet_next_reloc(p, &reloc);
1250 if (r) {
1251 DRM_ERROR("bad EVENT_WRITE\n");
1252 return -EINVAL;
1253 }
1254 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1255 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1256 }
1257 break;
1258 case PACKET3_EVENT_WRITE_EOP:
1259 if (pkt->count != 4) {
1260 DRM_ERROR("bad EVENT_WRITE_EOP\n");
1261 return -EINVAL;
1262 }
1263 r = evergreen_cs_packet_next_reloc(p, &reloc);
1264 if (r) {
1265 DRM_ERROR("bad EVENT_WRITE_EOP\n");
1266 return -EINVAL;
1267 }
1268 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1269 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1270 break;
1271 case PACKET3_EVENT_WRITE_EOS:
1272 if (pkt->count != 3) {
1273 DRM_ERROR("bad EVENT_WRITE_EOS\n");
1274 return -EINVAL;
1275 }
1276 r = evergreen_cs_packet_next_reloc(p, &reloc);
1277 if (r) {
1278 DRM_ERROR("bad EVENT_WRITE_EOS\n");
1279 return -EINVAL;
1280 }
1281 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1282 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1283 break;
1284 case PACKET3_SET_CONFIG_REG:
1285 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
1286 end_reg = 4 * pkt->count + start_reg - 4;
1287 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
1288 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1289 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1290 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1291 return -EINVAL;
1292 }
1293 for (i = 0; i < pkt->count; i++) {
1294 reg = start_reg + (4 * i);
1295 r = evergreen_cs_check_reg(p, reg, idx+1+i);
1296 if (r)
1297 return r;
1298 }
1299 break;
1300 case PACKET3_SET_CONTEXT_REG:
1301 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START;
1302 end_reg = 4 * pkt->count + start_reg - 4;
1303 if ((start_reg < PACKET3_SET_CONTEXT_REG_START) ||
1304 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
1305 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
1306 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1307 return -EINVAL;
1308 }
1309 for (i = 0; i < pkt->count; i++) {
1310 reg = start_reg + (4 * i);
1311 r = evergreen_cs_check_reg(p, reg, idx+1+i);
1312 if (r)
1313 return r;
1314 }
1315 break;
1316 case PACKET3_SET_RESOURCE:
1317 if (pkt->count % 8) {
1318 DRM_ERROR("bad SET_RESOURCE\n");
1319 return -EINVAL;
1320 }
1321 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START;
1322 end_reg = 4 * pkt->count + start_reg - 4;
1323 if ((start_reg < PACKET3_SET_RESOURCE_START) ||
1324 (start_reg >= PACKET3_SET_RESOURCE_END) ||
1325 (end_reg >= PACKET3_SET_RESOURCE_END)) {
1326 DRM_ERROR("bad SET_RESOURCE\n");
1327 return -EINVAL;
1328 }
1329 for (i = 0; i < (pkt->count / 8); i++) {
1330 struct radeon_bo *texture, *mipmap;
1331 u32 size, offset;
1332
1333 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) {
1334 case SQ_TEX_VTX_VALID_TEXTURE:
1335 /* tex base */
1336 r = evergreen_cs_packet_next_reloc(p, &reloc);
1337 if (r) {
1338 DRM_ERROR("bad SET_RESOURCE (tex)\n");
1339 return -EINVAL;
1340 }
1341 ib[idx+1+(i*8)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1342 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1343 ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
1344 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1345 ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
1346 texture = reloc->robj;
1347 /* tex mip base */
1348 r = evergreen_cs_packet_next_reloc(p, &reloc);
1349 if (r) {
1350 DRM_ERROR("bad SET_RESOURCE (tex)\n");
1351 return -EINVAL;
1352 }
1353 ib[idx+1+(i*8)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1354 mipmap = reloc->robj;
1355 r = evergreen_check_texture_resource(p, idx+1+(i*8),
1356 texture, mipmap);
1357 if (r)
1358 return r;
1359 break;
1360 case SQ_TEX_VTX_VALID_BUFFER:
1361 /* vtx base */
1362 r = evergreen_cs_packet_next_reloc(p, &reloc);
1363 if (r) {
1364 DRM_ERROR("bad SET_RESOURCE (vtx)\n");
1365 return -EINVAL;
1366 }
1367 offset = radeon_get_ib_value(p, idx+1+(i*8)+0);
1368 size = radeon_get_ib_value(p, idx+1+(i*8)+1);
1369 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
1370 /* force size to size of the buffer */
1371 dev_warn(p->dev, "vbo resource seems too big for the bo\n");
1372 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj);
1373 }
1374 ib[idx+1+(i*8)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
1375 ib[idx+1+(i*8)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1376 break;
1377 case SQ_TEX_VTX_INVALID_TEXTURE:
1378 case SQ_TEX_VTX_INVALID_BUFFER:
1379 default:
1380 DRM_ERROR("bad SET_RESOURCE\n");
1381 return -EINVAL;
1382 }
1383 }
1384 break;
1385 case PACKET3_SET_ALU_CONST:
1386 /* XXX fix me ALU const buffers only */
1387 break;
1388 case PACKET3_SET_BOOL_CONST:
1389 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_START;
1390 end_reg = 4 * pkt->count + start_reg - 4;
1391 if ((start_reg < PACKET3_SET_BOOL_CONST_START) ||
1392 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
1393 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
1394 DRM_ERROR("bad SET_BOOL_CONST\n");
1395 return -EINVAL;
1396 }
1397 break;
1398 case PACKET3_SET_LOOP_CONST:
1399 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_START;
1400 end_reg = 4 * pkt->count + start_reg - 4;
1401 if ((start_reg < PACKET3_SET_LOOP_CONST_START) ||
1402 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
1403 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
1404 DRM_ERROR("bad SET_LOOP_CONST\n");
1405 return -EINVAL;
1406 }
1407 break;
1408 case PACKET3_SET_CTL_CONST:
1409 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_START;
1410 end_reg = 4 * pkt->count + start_reg - 4;
1411 if ((start_reg < PACKET3_SET_CTL_CONST_START) ||
1412 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
1413 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
1414 DRM_ERROR("bad SET_CTL_CONST\n");
1415 return -EINVAL;
1416 }
1417 break;
1418 case PACKET3_SET_SAMPLER:
1419 if (pkt->count % 3) {
1420 DRM_ERROR("bad SET_SAMPLER\n");
1421 return -EINVAL;
1422 }
1423 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_START;
1424 end_reg = 4 * pkt->count + start_reg - 4;
1425 if ((start_reg < PACKET3_SET_SAMPLER_START) ||
1426 (start_reg >= PACKET3_SET_SAMPLER_END) ||
1427 (end_reg >= PACKET3_SET_SAMPLER_END)) {
1428 DRM_ERROR("bad SET_SAMPLER\n");
1429 return -EINVAL;
1430 }
1431 break;
1432 case PACKET3_NOP:
1433 break;
1434 default:
1435 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1436 return -EINVAL;
1437 }
1438 return 0;
1439}
1440
1441int evergreen_cs_parse(struct radeon_cs_parser *p)
1442{
1443 struct radeon_cs_packet pkt;
1444 struct evergreen_cs_track *track;
1445 int r;
1446
1447 if (p->track == NULL) {
1448 /* initialize tracker, we are in kms */
1449 track = kzalloc(sizeof(*track), GFP_KERNEL);
1450 if (track == NULL)
1451 return -ENOMEM;
1452 evergreen_cs_track_init(track);
1453 track->npipes = p->rdev->config.evergreen.tiling_npipes;
1454 track->nbanks = p->rdev->config.evergreen.tiling_nbanks;
1455 track->group_size = p->rdev->config.evergreen.tiling_group_size;
1456 p->track = track;
1457 }
1458 do {
1459 r = evergreen_cs_packet_parse(p, &pkt, p->idx);
1460 if (r) {
1461 kfree(p->track);
1462 p->track = NULL;
1463 return r;
1464 }
1465 p->idx += pkt.count + 2;
1466 switch (pkt.type) {
1467 case PACKET_TYPE0:
1468 r = evergreen_cs_parse_packet0(p, &pkt);
1469 break;
1470 case PACKET_TYPE2:
1471 break;
1472 case PACKET_TYPE3:
1473 r = evergreen_packet3_check(p, &pkt);
1474 break;
1475 default:
1476 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1477 kfree(p->track);
1478 p->track = NULL;
1479 return -EINVAL;
1480 }
1481 if (r) {
1482 kfree(p->track);
1483 p->track = NULL;
1484 return r;
1485 }
1486 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1487#if 0
1488 for (r = 0; r < p->ib->length_dw; r++) {
1489 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib->ptr[r]);
1490 mdelay(1);
1491 }
1492#endif
1493 kfree(p->track);
1494 p->track = NULL;
1495 return 0;
1496}
1497
1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
29#include "radeon.h"
30#include "evergreend.h"
31#include "evergreen_reg_safe.h"
32#include "cayman_reg_safe.h"
33
34#define MAX(a,b) (((a)>(b))?(a):(b))
35#define MIN(a,b) (((a)<(b))?(a):(b))
36
37static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
38 struct radeon_cs_reloc **cs_reloc);
39
40struct evergreen_cs_track {
41 u32 group_size;
42 u32 nbanks;
43 u32 npipes;
44 u32 row_size;
45 /* value we track */
46 u32 nsamples; /* unused */
47 struct radeon_bo *cb_color_bo[12];
48 u32 cb_color_bo_offset[12];
49 struct radeon_bo *cb_color_fmask_bo[8]; /* unused */
50 struct radeon_bo *cb_color_cmask_bo[8]; /* unused */
51 u32 cb_color_info[12];
52 u32 cb_color_view[12];
53 u32 cb_color_pitch[12];
54 u32 cb_color_slice[12];
55 u32 cb_color_slice_idx[12];
56 u32 cb_color_attrib[12];
57 u32 cb_color_cmask_slice[8];/* unused */
58 u32 cb_color_fmask_slice[8];/* unused */
59 u32 cb_target_mask;
60 u32 cb_shader_mask; /* unused */
61 u32 vgt_strmout_config;
62 u32 vgt_strmout_buffer_config;
63 struct radeon_bo *vgt_strmout_bo[4];
64 u32 vgt_strmout_bo_offset[4];
65 u32 vgt_strmout_size[4];
66 u32 db_depth_control;
67 u32 db_depth_view;
68 u32 db_depth_slice;
69 u32 db_depth_size;
70 u32 db_z_info;
71 u32 db_z_read_offset;
72 u32 db_z_write_offset;
73 struct radeon_bo *db_z_read_bo;
74 struct radeon_bo *db_z_write_bo;
75 u32 db_s_info;
76 u32 db_s_read_offset;
77 u32 db_s_write_offset;
78 struct radeon_bo *db_s_read_bo;
79 struct radeon_bo *db_s_write_bo;
80 bool sx_misc_kill_all_prims;
81 bool cb_dirty;
82 bool db_dirty;
83 bool streamout_dirty;
84 u32 htile_offset;
85 u32 htile_surface;
86 struct radeon_bo *htile_bo;
87};
88
89static u32 evergreen_cs_get_aray_mode(u32 tiling_flags)
90{
91 if (tiling_flags & RADEON_TILING_MACRO)
92 return ARRAY_2D_TILED_THIN1;
93 else if (tiling_flags & RADEON_TILING_MICRO)
94 return ARRAY_1D_TILED_THIN1;
95 else
96 return ARRAY_LINEAR_GENERAL;
97}
98
99static u32 evergreen_cs_get_num_banks(u32 nbanks)
100{
101 switch (nbanks) {
102 case 2:
103 return ADDR_SURF_2_BANK;
104 case 4:
105 return ADDR_SURF_4_BANK;
106 case 8:
107 default:
108 return ADDR_SURF_8_BANK;
109 case 16:
110 return ADDR_SURF_16_BANK;
111 }
112}
113
114static void evergreen_cs_track_init(struct evergreen_cs_track *track)
115{
116 int i;
117
118 for (i = 0; i < 8; i++) {
119 track->cb_color_fmask_bo[i] = NULL;
120 track->cb_color_cmask_bo[i] = NULL;
121 track->cb_color_cmask_slice[i] = 0;
122 track->cb_color_fmask_slice[i] = 0;
123 }
124
125 for (i = 0; i < 12; i++) {
126 track->cb_color_bo[i] = NULL;
127 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
128 track->cb_color_info[i] = 0;
129 track->cb_color_view[i] = 0xFFFFFFFF;
130 track->cb_color_pitch[i] = 0;
131 track->cb_color_slice[i] = 0xfffffff;
132 track->cb_color_slice_idx[i] = 0;
133 }
134 track->cb_target_mask = 0xFFFFFFFF;
135 track->cb_shader_mask = 0xFFFFFFFF;
136 track->cb_dirty = true;
137
138 track->db_depth_slice = 0xffffffff;
139 track->db_depth_view = 0xFFFFC000;
140 track->db_depth_size = 0xFFFFFFFF;
141 track->db_depth_control = 0xFFFFFFFF;
142 track->db_z_info = 0xFFFFFFFF;
143 track->db_z_read_offset = 0xFFFFFFFF;
144 track->db_z_write_offset = 0xFFFFFFFF;
145 track->db_z_read_bo = NULL;
146 track->db_z_write_bo = NULL;
147 track->db_s_info = 0xFFFFFFFF;
148 track->db_s_read_offset = 0xFFFFFFFF;
149 track->db_s_write_offset = 0xFFFFFFFF;
150 track->db_s_read_bo = NULL;
151 track->db_s_write_bo = NULL;
152 track->db_dirty = true;
153 track->htile_bo = NULL;
154 track->htile_offset = 0xFFFFFFFF;
155 track->htile_surface = 0;
156
157 for (i = 0; i < 4; i++) {
158 track->vgt_strmout_size[i] = 0;
159 track->vgt_strmout_bo[i] = NULL;
160 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
161 }
162 track->streamout_dirty = true;
163 track->sx_misc_kill_all_prims = false;
164}
165
166struct eg_surface {
167 /* value gathered from cs */
168 unsigned nbx;
169 unsigned nby;
170 unsigned format;
171 unsigned mode;
172 unsigned nbanks;
173 unsigned bankw;
174 unsigned bankh;
175 unsigned tsplit;
176 unsigned mtilea;
177 unsigned nsamples;
178 /* output value */
179 unsigned bpe;
180 unsigned layer_size;
181 unsigned palign;
182 unsigned halign;
183 unsigned long base_align;
184};
185
186static int evergreen_surface_check_linear(struct radeon_cs_parser *p,
187 struct eg_surface *surf,
188 const char *prefix)
189{
190 surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples;
191 surf->base_align = surf->bpe;
192 surf->palign = 1;
193 surf->halign = 1;
194 return 0;
195}
196
197static int evergreen_surface_check_linear_aligned(struct radeon_cs_parser *p,
198 struct eg_surface *surf,
199 const char *prefix)
200{
201 struct evergreen_cs_track *track = p->track;
202 unsigned palign;
203
204 palign = MAX(64, track->group_size / surf->bpe);
205 surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples;
206 surf->base_align = track->group_size;
207 surf->palign = palign;
208 surf->halign = 1;
209 if (surf->nbx & (palign - 1)) {
210 if (prefix) {
211 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n",
212 __func__, __LINE__, prefix, surf->nbx, palign);
213 }
214 return -EINVAL;
215 }
216 return 0;
217}
218
219static int evergreen_surface_check_1d(struct radeon_cs_parser *p,
220 struct eg_surface *surf,
221 const char *prefix)
222{
223 struct evergreen_cs_track *track = p->track;
224 unsigned palign;
225
226 palign = track->group_size / (8 * surf->bpe * surf->nsamples);
227 palign = MAX(8, palign);
228 surf->layer_size = surf->nbx * surf->nby * surf->bpe;
229 surf->base_align = track->group_size;
230 surf->palign = palign;
231 surf->halign = 8;
232 if ((surf->nbx & (palign - 1))) {
233 if (prefix) {
234 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d (%d %d %d)\n",
235 __func__, __LINE__, prefix, surf->nbx, palign,
236 track->group_size, surf->bpe, surf->nsamples);
237 }
238 return -EINVAL;
239 }
240 if ((surf->nby & (8 - 1))) {
241 if (prefix) {
242 dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with 8\n",
243 __func__, __LINE__, prefix, surf->nby);
244 }
245 return -EINVAL;
246 }
247 return 0;
248}
249
250static int evergreen_surface_check_2d(struct radeon_cs_parser *p,
251 struct eg_surface *surf,
252 const char *prefix)
253{
254 struct evergreen_cs_track *track = p->track;
255 unsigned palign, halign, tileb, slice_pt;
256 unsigned mtile_pr, mtile_ps, mtileb;
257
258 tileb = 64 * surf->bpe * surf->nsamples;
259 slice_pt = 1;
260 if (tileb > surf->tsplit) {
261 slice_pt = tileb / surf->tsplit;
262 }
263 tileb = tileb / slice_pt;
264 /* macro tile width & height */
265 palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
266 halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
267 mtileb = (palign / 8) * (halign / 8) * tileb;;
268 mtile_pr = surf->nbx / palign;
269 mtile_ps = (mtile_pr * surf->nby) / halign;
270 surf->layer_size = mtile_ps * mtileb * slice_pt;
271 surf->base_align = (palign / 8) * (halign / 8) * tileb;
272 surf->palign = palign;
273 surf->halign = halign;
274
275 if ((surf->nbx & (palign - 1))) {
276 if (prefix) {
277 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n",
278 __func__, __LINE__, prefix, surf->nbx, palign);
279 }
280 return -EINVAL;
281 }
282 if ((surf->nby & (halign - 1))) {
283 if (prefix) {
284 dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with %d\n",
285 __func__, __LINE__, prefix, surf->nby, halign);
286 }
287 return -EINVAL;
288 }
289
290 return 0;
291}
292
293static int evergreen_surface_check(struct radeon_cs_parser *p,
294 struct eg_surface *surf,
295 const char *prefix)
296{
297 /* some common value computed here */
298 surf->bpe = r600_fmt_get_blocksize(surf->format);
299
300 switch (surf->mode) {
301 case ARRAY_LINEAR_GENERAL:
302 return evergreen_surface_check_linear(p, surf, prefix);
303 case ARRAY_LINEAR_ALIGNED:
304 return evergreen_surface_check_linear_aligned(p, surf, prefix);
305 case ARRAY_1D_TILED_THIN1:
306 return evergreen_surface_check_1d(p, surf, prefix);
307 case ARRAY_2D_TILED_THIN1:
308 return evergreen_surface_check_2d(p, surf, prefix);
309 default:
310 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n",
311 __func__, __LINE__, prefix, surf->mode);
312 return -EINVAL;
313 }
314 return -EINVAL;
315}
316
317static int evergreen_surface_value_conv_check(struct radeon_cs_parser *p,
318 struct eg_surface *surf,
319 const char *prefix)
320{
321 switch (surf->mode) {
322 case ARRAY_2D_TILED_THIN1:
323 break;
324 case ARRAY_LINEAR_GENERAL:
325 case ARRAY_LINEAR_ALIGNED:
326 case ARRAY_1D_TILED_THIN1:
327 return 0;
328 default:
329 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n",
330 __func__, __LINE__, prefix, surf->mode);
331 return -EINVAL;
332 }
333
334 switch (surf->nbanks) {
335 case 0: surf->nbanks = 2; break;
336 case 1: surf->nbanks = 4; break;
337 case 2: surf->nbanks = 8; break;
338 case 3: surf->nbanks = 16; break;
339 default:
340 dev_warn(p->dev, "%s:%d %s invalid number of banks %d\n",
341 __func__, __LINE__, prefix, surf->nbanks);
342 return -EINVAL;
343 }
344 switch (surf->bankw) {
345 case 0: surf->bankw = 1; break;
346 case 1: surf->bankw = 2; break;
347 case 2: surf->bankw = 4; break;
348 case 3: surf->bankw = 8; break;
349 default:
350 dev_warn(p->dev, "%s:%d %s invalid bankw %d\n",
351 __func__, __LINE__, prefix, surf->bankw);
352 return -EINVAL;
353 }
354 switch (surf->bankh) {
355 case 0: surf->bankh = 1; break;
356 case 1: surf->bankh = 2; break;
357 case 2: surf->bankh = 4; break;
358 case 3: surf->bankh = 8; break;
359 default:
360 dev_warn(p->dev, "%s:%d %s invalid bankh %d\n",
361 __func__, __LINE__, prefix, surf->bankh);
362 return -EINVAL;
363 }
364 switch (surf->mtilea) {
365 case 0: surf->mtilea = 1; break;
366 case 1: surf->mtilea = 2; break;
367 case 2: surf->mtilea = 4; break;
368 case 3: surf->mtilea = 8; break;
369 default:
370 dev_warn(p->dev, "%s:%d %s invalid macro tile aspect %d\n",
371 __func__, __LINE__, prefix, surf->mtilea);
372 return -EINVAL;
373 }
374 switch (surf->tsplit) {
375 case 0: surf->tsplit = 64; break;
376 case 1: surf->tsplit = 128; break;
377 case 2: surf->tsplit = 256; break;
378 case 3: surf->tsplit = 512; break;
379 case 4: surf->tsplit = 1024; break;
380 case 5: surf->tsplit = 2048; break;
381 case 6: surf->tsplit = 4096; break;
382 default:
383 dev_warn(p->dev, "%s:%d %s invalid tile split %d\n",
384 __func__, __LINE__, prefix, surf->tsplit);
385 return -EINVAL;
386 }
387 return 0;
388}
389
390static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned id)
391{
392 struct evergreen_cs_track *track = p->track;
393 struct eg_surface surf;
394 unsigned pitch, slice, mslice;
395 unsigned long offset;
396 int r;
397
398 mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1;
399 pitch = track->cb_color_pitch[id];
400 slice = track->cb_color_slice[id];
401 surf.nbx = (pitch + 1) * 8;
402 surf.nby = ((slice + 1) * 64) / surf.nbx;
403 surf.mode = G_028C70_ARRAY_MODE(track->cb_color_info[id]);
404 surf.format = G_028C70_FORMAT(track->cb_color_info[id]);
405 surf.tsplit = G_028C74_TILE_SPLIT(track->cb_color_attrib[id]);
406 surf.nbanks = G_028C74_NUM_BANKS(track->cb_color_attrib[id]);
407 surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]);
408 surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id]);
409 surf.mtilea = G_028C74_MACRO_TILE_ASPECT(track->cb_color_attrib[id]);
410 surf.nsamples = 1;
411
412 if (!r600_fmt_is_valid_color(surf.format)) {
413 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08x)\n",
414 __func__, __LINE__, surf.format,
415 id, track->cb_color_info[id]);
416 return -EINVAL;
417 }
418
419 r = evergreen_surface_value_conv_check(p, &surf, "cb");
420 if (r) {
421 return r;
422 }
423
424 r = evergreen_surface_check(p, &surf, "cb");
425 if (r) {
426 dev_warn(p->dev, "%s:%d cb[%d] invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
427 __func__, __LINE__, id, track->cb_color_pitch[id],
428 track->cb_color_slice[id], track->cb_color_attrib[id],
429 track->cb_color_info[id]);
430 return r;
431 }
432
433 offset = track->cb_color_bo_offset[id] << 8;
434 if (offset & (surf.base_align - 1)) {
435 dev_warn(p->dev, "%s:%d cb[%d] bo base %ld not aligned with %ld\n",
436 __func__, __LINE__, id, offset, surf.base_align);
437 return -EINVAL;
438 }
439
440 offset += surf.layer_size * mslice;
441 if (offset > radeon_bo_size(track->cb_color_bo[id])) {
442 /* old ddx are broken they allocate bo with w*h*bpp but
443 * program slice with ALIGN(h, 8), catch this and patch
444 * command stream.
445 */
446 if (!surf.mode) {
447 volatile u32 *ib = p->ib.ptr;
448 unsigned long tmp, nby, bsize, size, min = 0;
449
450 /* find the height the ddx wants */
451 if (surf.nby > 8) {
452 min = surf.nby - 8;
453 }
454 bsize = radeon_bo_size(track->cb_color_bo[id]);
455 tmp = track->cb_color_bo_offset[id] << 8;
456 for (nby = surf.nby; nby > min; nby--) {
457 size = nby * surf.nbx * surf.bpe * surf.nsamples;
458 if ((tmp + size * mslice) <= bsize) {
459 break;
460 }
461 }
462 if (nby > min) {
463 surf.nby = nby;
464 slice = ((nby * surf.nbx) / 64) - 1;
465 if (!evergreen_surface_check(p, &surf, "cb")) {
466 /* check if this one works */
467 tmp += surf.layer_size * mslice;
468 if (tmp <= bsize) {
469 ib[track->cb_color_slice_idx[id]] = slice;
470 goto old_ddx_ok;
471 }
472 }
473 }
474 }
475 dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, "
476 "offset %d, max layer %d, bo size %ld, slice %d)\n",
477 __func__, __LINE__, id, surf.layer_size,
478 track->cb_color_bo_offset[id] << 8, mslice,
479 radeon_bo_size(track->cb_color_bo[id]), slice);
480 dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
481 __func__, __LINE__, surf.nbx, surf.nby,
482 surf.mode, surf.bpe, surf.nsamples,
483 surf.bankw, surf.bankh,
484 surf.tsplit, surf.mtilea);
485 return -EINVAL;
486 }
487old_ddx_ok:
488
489 return 0;
490}
491
492static int evergreen_cs_track_validate_htile(struct radeon_cs_parser *p,
493 unsigned nbx, unsigned nby)
494{
495 struct evergreen_cs_track *track = p->track;
496 unsigned long size;
497
498 if (track->htile_bo == NULL) {
499 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n",
500 __func__, __LINE__, track->db_z_info);
501 return -EINVAL;
502 }
503
504 if (G_028ABC_LINEAR(track->htile_surface)) {
505 /* pitch must be 16 htiles aligned == 16 * 8 pixel aligned */
506 nbx = round_up(nbx, 16 * 8);
507 /* height is npipes htiles aligned == npipes * 8 pixel aligned */
508 nby = round_up(nby, track->npipes * 8);
509 } else {
510 switch (track->npipes) {
511 case 8:
512 nbx = round_up(nbx, 64 * 8);
513 nby = round_up(nby, 64 * 8);
514 break;
515 case 4:
516 nbx = round_up(nbx, 64 * 8);
517 nby = round_up(nby, 32 * 8);
518 break;
519 case 2:
520 nbx = round_up(nbx, 32 * 8);
521 nby = round_up(nby, 32 * 8);
522 break;
523 case 1:
524 nbx = round_up(nbx, 32 * 8);
525 nby = round_up(nby, 16 * 8);
526 break;
527 default:
528 dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
529 __func__, __LINE__, track->npipes);
530 return -EINVAL;
531 }
532 }
533 /* compute number of htile */
534 nbx = nbx / 8;
535 nby = nby / 8;
536 size = nbx * nby * 4;
537 size += track->htile_offset;
538
539 if (size > radeon_bo_size(track->htile_bo)) {
540 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
541 __func__, __LINE__, radeon_bo_size(track->htile_bo),
542 size, nbx, nby);
543 return -EINVAL;
544 }
545 return 0;
546}
547
548static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p)
549{
550 struct evergreen_cs_track *track = p->track;
551 struct eg_surface surf;
552 unsigned pitch, slice, mslice;
553 unsigned long offset;
554 int r;
555
556 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
557 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
558 slice = track->db_depth_slice;
559 surf.nbx = (pitch + 1) * 8;
560 surf.nby = ((slice + 1) * 64) / surf.nbx;
561 surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
562 surf.format = G_028044_FORMAT(track->db_s_info);
563 surf.tsplit = G_028044_TILE_SPLIT(track->db_s_info);
564 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
565 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
566 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
567 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
568 surf.nsamples = 1;
569
570 if (surf.format != 1) {
571 dev_warn(p->dev, "%s:%d stencil invalid format %d\n",
572 __func__, __LINE__, surf.format);
573 return -EINVAL;
574 }
575 /* replace by color format so we can use same code */
576 surf.format = V_028C70_COLOR_8;
577
578 r = evergreen_surface_value_conv_check(p, &surf, "stencil");
579 if (r) {
580 return r;
581 }
582
583 r = evergreen_surface_check(p, &surf, NULL);
584 if (r) {
585 /* old userspace doesn't compute proper depth/stencil alignment
586 * check that alignment against a bigger byte per elements and
587 * only report if that alignment is wrong too.
588 */
589 surf.format = V_028C70_COLOR_8_8_8_8;
590 r = evergreen_surface_check(p, &surf, "stencil");
591 if (r) {
592 dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
593 __func__, __LINE__, track->db_depth_size,
594 track->db_depth_slice, track->db_s_info, track->db_z_info);
595 }
596 return r;
597 }
598
599 offset = track->db_s_read_offset << 8;
600 if (offset & (surf.base_align - 1)) {
601 dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
602 __func__, __LINE__, offset, surf.base_align);
603 return -EINVAL;
604 }
605 offset += surf.layer_size * mslice;
606 if (offset > radeon_bo_size(track->db_s_read_bo)) {
607 dev_warn(p->dev, "%s:%d stencil read bo too small (layer size %d, "
608 "offset %ld, max layer %d, bo size %ld)\n",
609 __func__, __LINE__, surf.layer_size,
610 (unsigned long)track->db_s_read_offset << 8, mslice,
611 radeon_bo_size(track->db_s_read_bo));
612 dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
613 __func__, __LINE__, track->db_depth_size,
614 track->db_depth_slice, track->db_s_info, track->db_z_info);
615 return -EINVAL;
616 }
617
618 offset = track->db_s_write_offset << 8;
619 if (offset & (surf.base_align - 1)) {
620 dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
621 __func__, __LINE__, offset, surf.base_align);
622 return -EINVAL;
623 }
624 offset += surf.layer_size * mslice;
625 if (offset > radeon_bo_size(track->db_s_write_bo)) {
626 dev_warn(p->dev, "%s:%d stencil write bo too small (layer size %d, "
627 "offset %ld, max layer %d, bo size %ld)\n",
628 __func__, __LINE__, surf.layer_size,
629 (unsigned long)track->db_s_write_offset << 8, mslice,
630 radeon_bo_size(track->db_s_write_bo));
631 return -EINVAL;
632 }
633
634 /* hyperz */
635 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) {
636 r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby);
637 if (r) {
638 return r;
639 }
640 }
641
642 return 0;
643}
644
645static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p)
646{
647 struct evergreen_cs_track *track = p->track;
648 struct eg_surface surf;
649 unsigned pitch, slice, mslice;
650 unsigned long offset;
651 int r;
652
653 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
654 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
655 slice = track->db_depth_slice;
656 surf.nbx = (pitch + 1) * 8;
657 surf.nby = ((slice + 1) * 64) / surf.nbx;
658 surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
659 surf.format = G_028040_FORMAT(track->db_z_info);
660 surf.tsplit = G_028040_TILE_SPLIT(track->db_z_info);
661 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
662 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
663 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
664 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
665 surf.nsamples = 1;
666
667 switch (surf.format) {
668 case V_028040_Z_16:
669 surf.format = V_028C70_COLOR_16;
670 break;
671 case V_028040_Z_24:
672 case V_028040_Z_32_FLOAT:
673 surf.format = V_028C70_COLOR_8_8_8_8;
674 break;
675 default:
676 dev_warn(p->dev, "%s:%d depth invalid format %d\n",
677 __func__, __LINE__, surf.format);
678 return -EINVAL;
679 }
680
681 r = evergreen_surface_value_conv_check(p, &surf, "depth");
682 if (r) {
683 dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n",
684 __func__, __LINE__, track->db_depth_size,
685 track->db_depth_slice, track->db_z_info);
686 return r;
687 }
688
689 r = evergreen_surface_check(p, &surf, "depth");
690 if (r) {
691 dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n",
692 __func__, __LINE__, track->db_depth_size,
693 track->db_depth_slice, track->db_z_info);
694 return r;
695 }
696
697 offset = track->db_z_read_offset << 8;
698 if (offset & (surf.base_align - 1)) {
699 dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
700 __func__, __LINE__, offset, surf.base_align);
701 return -EINVAL;
702 }
703 offset += surf.layer_size * mslice;
704 if (offset > radeon_bo_size(track->db_z_read_bo)) {
705 dev_warn(p->dev, "%s:%d depth read bo too small (layer size %d, "
706 "offset %ld, max layer %d, bo size %ld)\n",
707 __func__, __LINE__, surf.layer_size,
708 (unsigned long)track->db_z_read_offset << 8, mslice,
709 radeon_bo_size(track->db_z_read_bo));
710 return -EINVAL;
711 }
712
713 offset = track->db_z_write_offset << 8;
714 if (offset & (surf.base_align - 1)) {
715 dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
716 __func__, __LINE__, offset, surf.base_align);
717 return -EINVAL;
718 }
719 offset += surf.layer_size * mslice;
720 if (offset > radeon_bo_size(track->db_z_write_bo)) {
721 dev_warn(p->dev, "%s:%d depth write bo too small (layer size %d, "
722 "offset %ld, max layer %d, bo size %ld)\n",
723 __func__, __LINE__, surf.layer_size,
724 (unsigned long)track->db_z_write_offset << 8, mslice,
725 radeon_bo_size(track->db_z_write_bo));
726 return -EINVAL;
727 }
728
729 /* hyperz */
730 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) {
731 r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby);
732 if (r) {
733 return r;
734 }
735 }
736
737 return 0;
738}
739
740static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p,
741 struct radeon_bo *texture,
742 struct radeon_bo *mipmap,
743 unsigned idx)
744{
745 struct eg_surface surf;
746 unsigned long toffset, moffset;
747 unsigned dim, llevel, mslice, width, height, depth, i;
748 u32 texdw[8];
749 int r;
750
751 texdw[0] = radeon_get_ib_value(p, idx + 0);
752 texdw[1] = radeon_get_ib_value(p, idx + 1);
753 texdw[2] = radeon_get_ib_value(p, idx + 2);
754 texdw[3] = radeon_get_ib_value(p, idx + 3);
755 texdw[4] = radeon_get_ib_value(p, idx + 4);
756 texdw[5] = radeon_get_ib_value(p, idx + 5);
757 texdw[6] = radeon_get_ib_value(p, idx + 6);
758 texdw[7] = radeon_get_ib_value(p, idx + 7);
759 dim = G_030000_DIM(texdw[0]);
760 llevel = G_030014_LAST_LEVEL(texdw[5]);
761 mslice = G_030014_LAST_ARRAY(texdw[5]) + 1;
762 width = G_030000_TEX_WIDTH(texdw[0]) + 1;
763 height = G_030004_TEX_HEIGHT(texdw[1]) + 1;
764 depth = G_030004_TEX_DEPTH(texdw[1]) + 1;
765 surf.format = G_03001C_DATA_FORMAT(texdw[7]);
766 surf.nbx = (G_030000_PITCH(texdw[0]) + 1) * 8;
767 surf.nbx = r600_fmt_get_nblocksx(surf.format, surf.nbx);
768 surf.nby = r600_fmt_get_nblocksy(surf.format, height);
769 surf.mode = G_030004_ARRAY_MODE(texdw[1]);
770 surf.tsplit = G_030018_TILE_SPLIT(texdw[6]);
771 surf.nbanks = G_03001C_NUM_BANKS(texdw[7]);
772 surf.bankw = G_03001C_BANK_WIDTH(texdw[7]);
773 surf.bankh = G_03001C_BANK_HEIGHT(texdw[7]);
774 surf.mtilea = G_03001C_MACRO_TILE_ASPECT(texdw[7]);
775 surf.nsamples = 1;
776 toffset = texdw[2] << 8;
777 moffset = texdw[3] << 8;
778
779 if (!r600_fmt_is_valid_texture(surf.format, p->family)) {
780 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
781 __func__, __LINE__, surf.format);
782 return -EINVAL;
783 }
784 switch (dim) {
785 case V_030000_SQ_TEX_DIM_1D:
786 case V_030000_SQ_TEX_DIM_2D:
787 case V_030000_SQ_TEX_DIM_CUBEMAP:
788 case V_030000_SQ_TEX_DIM_1D_ARRAY:
789 case V_030000_SQ_TEX_DIM_2D_ARRAY:
790 depth = 1;
791 case V_030000_SQ_TEX_DIM_3D:
792 break;
793 default:
794 dev_warn(p->dev, "%s:%d texture invalid dimension %d\n",
795 __func__, __LINE__, dim);
796 return -EINVAL;
797 }
798
799 r = evergreen_surface_value_conv_check(p, &surf, "texture");
800 if (r) {
801 return r;
802 }
803
804 /* align height */
805 evergreen_surface_check(p, &surf, NULL);
806 surf.nby = ALIGN(surf.nby, surf.halign);
807
808 r = evergreen_surface_check(p, &surf, "texture");
809 if (r) {
810 dev_warn(p->dev, "%s:%d texture invalid 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
811 __func__, __LINE__, texdw[0], texdw[1], texdw[4],
812 texdw[5], texdw[6], texdw[7]);
813 return r;
814 }
815
816 /* check texture size */
817 if (toffset & (surf.base_align - 1)) {
818 dev_warn(p->dev, "%s:%d texture bo base %ld not aligned with %ld\n",
819 __func__, __LINE__, toffset, surf.base_align);
820 return -EINVAL;
821 }
822 if (moffset & (surf.base_align - 1)) {
823 dev_warn(p->dev, "%s:%d mipmap bo base %ld not aligned with %ld\n",
824 __func__, __LINE__, moffset, surf.base_align);
825 return -EINVAL;
826 }
827 if (dim == SQ_TEX_DIM_3D) {
828 toffset += surf.layer_size * depth;
829 } else {
830 toffset += surf.layer_size * mslice;
831 }
832 if (toffset > radeon_bo_size(texture)) {
833 dev_warn(p->dev, "%s:%d texture bo too small (layer size %d, "
834 "offset %ld, max layer %d, depth %d, bo size %ld) (%d %d)\n",
835 __func__, __LINE__, surf.layer_size,
836 (unsigned long)texdw[2] << 8, mslice,
837 depth, radeon_bo_size(texture),
838 surf.nbx, surf.nby);
839 return -EINVAL;
840 }
841
842 /* check mipmap size */
843 for (i = 1; i <= llevel; i++) {
844 unsigned w, h, d;
845
846 w = r600_mip_minify(width, i);
847 h = r600_mip_minify(height, i);
848 d = r600_mip_minify(depth, i);
849 surf.nbx = r600_fmt_get_nblocksx(surf.format, w);
850 surf.nby = r600_fmt_get_nblocksy(surf.format, h);
851
852 switch (surf.mode) {
853 case ARRAY_2D_TILED_THIN1:
854 if (surf.nbx < surf.palign || surf.nby < surf.halign) {
855 surf.mode = ARRAY_1D_TILED_THIN1;
856 }
857 /* recompute alignment */
858 evergreen_surface_check(p, &surf, NULL);
859 break;
860 case ARRAY_LINEAR_GENERAL:
861 case ARRAY_LINEAR_ALIGNED:
862 case ARRAY_1D_TILED_THIN1:
863 break;
864 default:
865 dev_warn(p->dev, "%s:%d invalid array mode %d\n",
866 __func__, __LINE__, surf.mode);
867 return -EINVAL;
868 }
869 surf.nbx = ALIGN(surf.nbx, surf.palign);
870 surf.nby = ALIGN(surf.nby, surf.halign);
871
872 r = evergreen_surface_check(p, &surf, "mipmap");
873 if (r) {
874 return r;
875 }
876
877 if (dim == SQ_TEX_DIM_3D) {
878 moffset += surf.layer_size * d;
879 } else {
880 moffset += surf.layer_size * mslice;
881 }
882 if (moffset > radeon_bo_size(mipmap)) {
883 dev_warn(p->dev, "%s:%d mipmap [%d] bo too small (layer size %d, "
884 "offset %ld, coffset %ld, max layer %d, depth %d, "
885 "bo size %ld) level0 (%d %d %d)\n",
886 __func__, __LINE__, i, surf.layer_size,
887 (unsigned long)texdw[3] << 8, moffset, mslice,
888 d, radeon_bo_size(mipmap),
889 width, height, depth);
890 dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
891 __func__, __LINE__, surf.nbx, surf.nby,
892 surf.mode, surf.bpe, surf.nsamples,
893 surf.bankw, surf.bankh,
894 surf.tsplit, surf.mtilea);
895 return -EINVAL;
896 }
897 }
898
899 return 0;
900}
901
902static int evergreen_cs_track_check(struct radeon_cs_parser *p)
903{
904 struct evergreen_cs_track *track = p->track;
905 unsigned tmp, i;
906 int r;
907 unsigned buffer_mask = 0;
908
909 /* check streamout */
910 if (track->streamout_dirty && track->vgt_strmout_config) {
911 for (i = 0; i < 4; i++) {
912 if (track->vgt_strmout_config & (1 << i)) {
913 buffer_mask |= (track->vgt_strmout_buffer_config >> (i * 4)) & 0xf;
914 }
915 }
916
917 for (i = 0; i < 4; i++) {
918 if (buffer_mask & (1 << i)) {
919 if (track->vgt_strmout_bo[i]) {
920 u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
921 (u64)track->vgt_strmout_size[i];
922 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
923 DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
924 i, offset,
925 radeon_bo_size(track->vgt_strmout_bo[i]));
926 return -EINVAL;
927 }
928 } else {
929 dev_warn(p->dev, "No buffer for streamout %d\n", i);
930 return -EINVAL;
931 }
932 }
933 }
934 track->streamout_dirty = false;
935 }
936
937 if (track->sx_misc_kill_all_prims)
938 return 0;
939
940 /* check that we have a cb for each enabled target
941 */
942 if (track->cb_dirty) {
943 tmp = track->cb_target_mask;
944 for (i = 0; i < 8; i++) {
945 if ((tmp >> (i * 4)) & 0xF) {
946 /* at least one component is enabled */
947 if (track->cb_color_bo[i] == NULL) {
948 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
949 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
950 return -EINVAL;
951 }
952 /* check cb */
953 r = evergreen_cs_track_validate_cb(p, i);
954 if (r) {
955 return r;
956 }
957 }
958 }
959 track->cb_dirty = false;
960 }
961
962 if (track->db_dirty) {
963 /* Check stencil buffer */
964 if (G_028044_FORMAT(track->db_s_info) != V_028044_STENCIL_INVALID &&
965 G_028800_STENCIL_ENABLE(track->db_depth_control)) {
966 r = evergreen_cs_track_validate_stencil(p);
967 if (r)
968 return r;
969 }
970 /* Check depth buffer */
971 if (G_028040_FORMAT(track->db_z_info) != V_028040_Z_INVALID &&
972 G_028800_Z_ENABLE(track->db_depth_control)) {
973 r = evergreen_cs_track_validate_depth(p);
974 if (r)
975 return r;
976 }
977 track->db_dirty = false;
978 }
979
980 return 0;
981}
982
983/**
984 * evergreen_cs_packet_parse() - parse cp packet and point ib index to next packet
985 * @parser: parser structure holding parsing context.
986 * @pkt: where to store packet informations
987 *
988 * Assume that chunk_ib_index is properly set. Will return -EINVAL
989 * if packet is bigger than remaining ib size. or if packets is unknown.
990 **/
991int evergreen_cs_packet_parse(struct radeon_cs_parser *p,
992 struct radeon_cs_packet *pkt,
993 unsigned idx)
994{
995 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
996 uint32_t header;
997
998 if (idx >= ib_chunk->length_dw) {
999 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1000 idx, ib_chunk->length_dw);
1001 return -EINVAL;
1002 }
1003 header = radeon_get_ib_value(p, idx);
1004 pkt->idx = idx;
1005 pkt->type = CP_PACKET_GET_TYPE(header);
1006 pkt->count = CP_PACKET_GET_COUNT(header);
1007 pkt->one_reg_wr = 0;
1008 switch (pkt->type) {
1009 case PACKET_TYPE0:
1010 pkt->reg = CP_PACKET0_GET_REG(header);
1011 break;
1012 case PACKET_TYPE3:
1013 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1014 break;
1015 case PACKET_TYPE2:
1016 pkt->count = -1;
1017 break;
1018 default:
1019 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1020 return -EINVAL;
1021 }
1022 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1023 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1024 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1025 return -EINVAL;
1026 }
1027 return 0;
1028}
1029
1030/**
1031 * evergreen_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1032 * @parser: parser structure holding parsing context.
1033 * @data: pointer to relocation data
1034 * @offset_start: starting offset
1035 * @offset_mask: offset mask (to align start offset on)
1036 * @reloc: reloc informations
1037 *
1038 * Check next packet is relocation packet3, do bo validation and compute
1039 * GPU offset using the provided start.
1040 **/
1041static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
1042 struct radeon_cs_reloc **cs_reloc)
1043{
1044 struct radeon_cs_chunk *relocs_chunk;
1045 struct radeon_cs_packet p3reloc;
1046 unsigned idx;
1047 int r;
1048
1049 if (p->chunk_relocs_idx == -1) {
1050 DRM_ERROR("No relocation chunk !\n");
1051 return -EINVAL;
1052 }
1053 *cs_reloc = NULL;
1054 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1055 r = evergreen_cs_packet_parse(p, &p3reloc, p->idx);
1056 if (r) {
1057 return r;
1058 }
1059 p->idx += p3reloc.count + 2;
1060 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1061 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1062 p3reloc.idx);
1063 return -EINVAL;
1064 }
1065 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1066 if (idx >= relocs_chunk->length_dw) {
1067 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1068 idx, relocs_chunk->length_dw);
1069 return -EINVAL;
1070 }
1071 /* FIXME: we assume reloc size is 4 dwords */
1072 *cs_reloc = p->relocs_ptr[(idx / 4)];
1073 return 0;
1074}
1075
1076/**
1077 * evergreen_cs_packet_next_vline() - parse userspace VLINE packet
1078 * @parser: parser structure holding parsing context.
1079 *
1080 * Userspace sends a special sequence for VLINE waits.
1081 * PACKET0 - VLINE_START_END + value
1082 * PACKET3 - WAIT_REG_MEM poll vline status reg
1083 * RELOC (P3) - crtc_id in reloc.
1084 *
1085 * This function parses this and relocates the VLINE START END
1086 * and WAIT_REG_MEM packets to the correct crtc.
1087 * It also detects a switched off crtc and nulls out the
1088 * wait in that case.
1089 */
1090static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
1091{
1092 struct drm_mode_object *obj;
1093 struct drm_crtc *crtc;
1094 struct radeon_crtc *radeon_crtc;
1095 struct radeon_cs_packet p3reloc, wait_reg_mem;
1096 int crtc_id;
1097 int r;
1098 uint32_t header, h_idx, reg, wait_reg_mem_info;
1099 volatile uint32_t *ib;
1100
1101 ib = p->ib.ptr;
1102
1103 /* parse the WAIT_REG_MEM */
1104 r = evergreen_cs_packet_parse(p, &wait_reg_mem, p->idx);
1105 if (r)
1106 return r;
1107
1108 /* check its a WAIT_REG_MEM */
1109 if (wait_reg_mem.type != PACKET_TYPE3 ||
1110 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
1111 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
1112 return -EINVAL;
1113 }
1114
1115 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
1116 /* bit 4 is reg (0) or mem (1) */
1117 if (wait_reg_mem_info & 0x10) {
1118 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
1119 return -EINVAL;
1120 }
1121 /* waiting for value to be equal */
1122 if ((wait_reg_mem_info & 0x7) != 0x3) {
1123 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
1124 return -EINVAL;
1125 }
1126 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != EVERGREEN_VLINE_STATUS) {
1127 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
1128 return -EINVAL;
1129 }
1130
1131 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != EVERGREEN_VLINE_STAT) {
1132 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
1133 return -EINVAL;
1134 }
1135
1136 /* jump over the NOP */
1137 r = evergreen_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
1138 if (r)
1139 return r;
1140
1141 h_idx = p->idx - 2;
1142 p->idx += wait_reg_mem.count + 2;
1143 p->idx += p3reloc.count + 2;
1144
1145 header = radeon_get_ib_value(p, h_idx);
1146 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
1147 reg = CP_PACKET0_GET_REG(header);
1148 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1149 if (!obj) {
1150 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1151 return -EINVAL;
1152 }
1153 crtc = obj_to_crtc(obj);
1154 radeon_crtc = to_radeon_crtc(crtc);
1155 crtc_id = radeon_crtc->crtc_id;
1156
1157 if (!crtc->enabled) {
1158 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
1159 ib[h_idx + 2] = PACKET2(0);
1160 ib[h_idx + 3] = PACKET2(0);
1161 ib[h_idx + 4] = PACKET2(0);
1162 ib[h_idx + 5] = PACKET2(0);
1163 ib[h_idx + 6] = PACKET2(0);
1164 ib[h_idx + 7] = PACKET2(0);
1165 ib[h_idx + 8] = PACKET2(0);
1166 } else {
1167 switch (reg) {
1168 case EVERGREEN_VLINE_START_END:
1169 header &= ~R600_CP_PACKET0_REG_MASK;
1170 header |= (EVERGREEN_VLINE_START_END + radeon_crtc->crtc_offset) >> 2;
1171 ib[h_idx] = header;
1172 ib[h_idx + 4] = (EVERGREEN_VLINE_STATUS + radeon_crtc->crtc_offset) >> 2;
1173 break;
1174 default:
1175 DRM_ERROR("unknown crtc reloc\n");
1176 return -EINVAL;
1177 }
1178 }
1179 return 0;
1180}
1181
1182static int evergreen_packet0_check(struct radeon_cs_parser *p,
1183 struct radeon_cs_packet *pkt,
1184 unsigned idx, unsigned reg)
1185{
1186 int r;
1187
1188 switch (reg) {
1189 case EVERGREEN_VLINE_START_END:
1190 r = evergreen_cs_packet_parse_vline(p);
1191 if (r) {
1192 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1193 idx, reg);
1194 return r;
1195 }
1196 break;
1197 default:
1198 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1199 reg, idx);
1200 return -EINVAL;
1201 }
1202 return 0;
1203}
1204
1205static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p,
1206 struct radeon_cs_packet *pkt)
1207{
1208 unsigned reg, i;
1209 unsigned idx;
1210 int r;
1211
1212 idx = pkt->idx + 1;
1213 reg = pkt->reg;
1214 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
1215 r = evergreen_packet0_check(p, pkt, idx, reg);
1216 if (r) {
1217 return r;
1218 }
1219 }
1220 return 0;
1221}
1222
1223/**
1224 * evergreen_cs_check_reg() - check if register is authorized or not
1225 * @parser: parser structure holding parsing context
1226 * @reg: register we are testing
1227 * @idx: index into the cs buffer
1228 *
1229 * This function will test against evergreen_reg_safe_bm and return 0
1230 * if register is safe. If register is not flag as safe this function
1231 * will test it against a list of register needind special handling.
1232 */
1233static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1234{
1235 struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;
1236 struct radeon_cs_reloc *reloc;
1237 u32 last_reg;
1238 u32 m, i, tmp, *ib;
1239 int r;
1240
1241 if (p->rdev->family >= CHIP_CAYMAN)
1242 last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
1243 else
1244 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
1245
1246 i = (reg >> 7);
1247 if (i >= last_reg) {
1248 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1249 return -EINVAL;
1250 }
1251 m = 1 << ((reg >> 2) & 31);
1252 if (p->rdev->family >= CHIP_CAYMAN) {
1253 if (!(cayman_reg_safe_bm[i] & m))
1254 return 0;
1255 } else {
1256 if (!(evergreen_reg_safe_bm[i] & m))
1257 return 0;
1258 }
1259 ib = p->ib.ptr;
1260 switch (reg) {
1261 /* force following reg to 0 in an attempt to disable out buffer
1262 * which will need us to better understand how it works to perform
1263 * security check on it (Jerome)
1264 */
1265 case SQ_ESGS_RING_SIZE:
1266 case SQ_GSVS_RING_SIZE:
1267 case SQ_ESTMP_RING_SIZE:
1268 case SQ_GSTMP_RING_SIZE:
1269 case SQ_HSTMP_RING_SIZE:
1270 case SQ_LSTMP_RING_SIZE:
1271 case SQ_PSTMP_RING_SIZE:
1272 case SQ_VSTMP_RING_SIZE:
1273 case SQ_ESGS_RING_ITEMSIZE:
1274 case SQ_ESTMP_RING_ITEMSIZE:
1275 case SQ_GSTMP_RING_ITEMSIZE:
1276 case SQ_GSVS_RING_ITEMSIZE:
1277 case SQ_GS_VERT_ITEMSIZE:
1278 case SQ_GS_VERT_ITEMSIZE_1:
1279 case SQ_GS_VERT_ITEMSIZE_2:
1280 case SQ_GS_VERT_ITEMSIZE_3:
1281 case SQ_GSVS_RING_OFFSET_1:
1282 case SQ_GSVS_RING_OFFSET_2:
1283 case SQ_GSVS_RING_OFFSET_3:
1284 case SQ_HSTMP_RING_ITEMSIZE:
1285 case SQ_LSTMP_RING_ITEMSIZE:
1286 case SQ_PSTMP_RING_ITEMSIZE:
1287 case SQ_VSTMP_RING_ITEMSIZE:
1288 case VGT_TF_RING_SIZE:
1289 /* get value to populate the IB don't remove */
1290 /*tmp =radeon_get_ib_value(p, idx);
1291 ib[idx] = 0;*/
1292 break;
1293 case SQ_ESGS_RING_BASE:
1294 case SQ_GSVS_RING_BASE:
1295 case SQ_ESTMP_RING_BASE:
1296 case SQ_GSTMP_RING_BASE:
1297 case SQ_HSTMP_RING_BASE:
1298 case SQ_LSTMP_RING_BASE:
1299 case SQ_PSTMP_RING_BASE:
1300 case SQ_VSTMP_RING_BASE:
1301 r = evergreen_cs_packet_next_reloc(p, &reloc);
1302 if (r) {
1303 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1304 "0x%04X\n", reg);
1305 return -EINVAL;
1306 }
1307 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1308 break;
1309 case DB_DEPTH_CONTROL:
1310 track->db_depth_control = radeon_get_ib_value(p, idx);
1311 track->db_dirty = true;
1312 break;
1313 case CAYMAN_DB_EQAA:
1314 if (p->rdev->family < CHIP_CAYMAN) {
1315 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1316 "0x%04X\n", reg);
1317 return -EINVAL;
1318 }
1319 break;
1320 case CAYMAN_DB_DEPTH_INFO:
1321 if (p->rdev->family < CHIP_CAYMAN) {
1322 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1323 "0x%04X\n", reg);
1324 return -EINVAL;
1325 }
1326 break;
1327 case DB_Z_INFO:
1328 track->db_z_info = radeon_get_ib_value(p, idx);
1329 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1330 r = evergreen_cs_packet_next_reloc(p, &reloc);
1331 if (r) {
1332 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1333 "0x%04X\n", reg);
1334 return -EINVAL;
1335 }
1336 ib[idx] &= ~Z_ARRAY_MODE(0xf);
1337 track->db_z_info &= ~Z_ARRAY_MODE(0xf);
1338 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1339 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1340 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1341 unsigned bankw, bankh, mtaspect, tile_split;
1342
1343 evergreen_tiling_fields(reloc->lobj.tiling_flags,
1344 &bankw, &bankh, &mtaspect,
1345 &tile_split);
1346 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1347 ib[idx] |= DB_TILE_SPLIT(tile_split) |
1348 DB_BANK_WIDTH(bankw) |
1349 DB_BANK_HEIGHT(bankh) |
1350 DB_MACRO_TILE_ASPECT(mtaspect);
1351 }
1352 }
1353 track->db_dirty = true;
1354 break;
1355 case DB_STENCIL_INFO:
1356 track->db_s_info = radeon_get_ib_value(p, idx);
1357 track->db_dirty = true;
1358 break;
1359 case DB_DEPTH_VIEW:
1360 track->db_depth_view = radeon_get_ib_value(p, idx);
1361 track->db_dirty = true;
1362 break;
1363 case DB_DEPTH_SIZE:
1364 track->db_depth_size = radeon_get_ib_value(p, idx);
1365 track->db_dirty = true;
1366 break;
1367 case R_02805C_DB_DEPTH_SLICE:
1368 track->db_depth_slice = radeon_get_ib_value(p, idx);
1369 track->db_dirty = true;
1370 break;
1371 case DB_Z_READ_BASE:
1372 r = evergreen_cs_packet_next_reloc(p, &reloc);
1373 if (r) {
1374 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1375 "0x%04X\n", reg);
1376 return -EINVAL;
1377 }
1378 track->db_z_read_offset = radeon_get_ib_value(p, idx);
1379 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1380 track->db_z_read_bo = reloc->robj;
1381 track->db_dirty = true;
1382 break;
1383 case DB_Z_WRITE_BASE:
1384 r = evergreen_cs_packet_next_reloc(p, &reloc);
1385 if (r) {
1386 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1387 "0x%04X\n", reg);
1388 return -EINVAL;
1389 }
1390 track->db_z_write_offset = radeon_get_ib_value(p, idx);
1391 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1392 track->db_z_write_bo = reloc->robj;
1393 track->db_dirty = true;
1394 break;
1395 case DB_STENCIL_READ_BASE:
1396 r = evergreen_cs_packet_next_reloc(p, &reloc);
1397 if (r) {
1398 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1399 "0x%04X\n", reg);
1400 return -EINVAL;
1401 }
1402 track->db_s_read_offset = radeon_get_ib_value(p, idx);
1403 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1404 track->db_s_read_bo = reloc->robj;
1405 track->db_dirty = true;
1406 break;
1407 case DB_STENCIL_WRITE_BASE:
1408 r = evergreen_cs_packet_next_reloc(p, &reloc);
1409 if (r) {
1410 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1411 "0x%04X\n", reg);
1412 return -EINVAL;
1413 }
1414 track->db_s_write_offset = radeon_get_ib_value(p, idx);
1415 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1416 track->db_s_write_bo = reloc->robj;
1417 track->db_dirty = true;
1418 break;
1419 case VGT_STRMOUT_CONFIG:
1420 track->vgt_strmout_config = radeon_get_ib_value(p, idx);
1421 track->streamout_dirty = true;
1422 break;
1423 case VGT_STRMOUT_BUFFER_CONFIG:
1424 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx);
1425 track->streamout_dirty = true;
1426 break;
1427 case VGT_STRMOUT_BUFFER_BASE_0:
1428 case VGT_STRMOUT_BUFFER_BASE_1:
1429 case VGT_STRMOUT_BUFFER_BASE_2:
1430 case VGT_STRMOUT_BUFFER_BASE_3:
1431 r = evergreen_cs_packet_next_reloc(p, &reloc);
1432 if (r) {
1433 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1434 "0x%04X\n", reg);
1435 return -EINVAL;
1436 }
1437 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1438 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1439 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1440 track->vgt_strmout_bo[tmp] = reloc->robj;
1441 track->streamout_dirty = true;
1442 break;
1443 case VGT_STRMOUT_BUFFER_SIZE_0:
1444 case VGT_STRMOUT_BUFFER_SIZE_1:
1445 case VGT_STRMOUT_BUFFER_SIZE_2:
1446 case VGT_STRMOUT_BUFFER_SIZE_3:
1447 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1448 /* size in register is DWs, convert to bytes */
1449 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1450 track->streamout_dirty = true;
1451 break;
1452 case CP_COHER_BASE:
1453 r = evergreen_cs_packet_next_reloc(p, &reloc);
1454 if (r) {
1455 dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1456 "0x%04X\n", reg);
1457 return -EINVAL;
1458 }
1459 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1460 case CB_TARGET_MASK:
1461 track->cb_target_mask = radeon_get_ib_value(p, idx);
1462 track->cb_dirty = true;
1463 break;
1464 case CB_SHADER_MASK:
1465 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1466 track->cb_dirty = true;
1467 break;
1468 case PA_SC_AA_CONFIG:
1469 if (p->rdev->family >= CHIP_CAYMAN) {
1470 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1471 "0x%04X\n", reg);
1472 return -EINVAL;
1473 }
1474 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
1475 track->nsamples = 1 << tmp;
1476 break;
1477 case CAYMAN_PA_SC_AA_CONFIG:
1478 if (p->rdev->family < CHIP_CAYMAN) {
1479 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1480 "0x%04X\n", reg);
1481 return -EINVAL;
1482 }
1483 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;
1484 track->nsamples = 1 << tmp;
1485 break;
1486 case CB_COLOR0_VIEW:
1487 case CB_COLOR1_VIEW:
1488 case CB_COLOR2_VIEW:
1489 case CB_COLOR3_VIEW:
1490 case CB_COLOR4_VIEW:
1491 case CB_COLOR5_VIEW:
1492 case CB_COLOR6_VIEW:
1493 case CB_COLOR7_VIEW:
1494 tmp = (reg - CB_COLOR0_VIEW) / 0x3c;
1495 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1496 track->cb_dirty = true;
1497 break;
1498 case CB_COLOR8_VIEW:
1499 case CB_COLOR9_VIEW:
1500 case CB_COLOR10_VIEW:
1501 case CB_COLOR11_VIEW:
1502 tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8;
1503 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1504 track->cb_dirty = true;
1505 break;
1506 case CB_COLOR0_INFO:
1507 case CB_COLOR1_INFO:
1508 case CB_COLOR2_INFO:
1509 case CB_COLOR3_INFO:
1510 case CB_COLOR4_INFO:
1511 case CB_COLOR5_INFO:
1512 case CB_COLOR6_INFO:
1513 case CB_COLOR7_INFO:
1514 tmp = (reg - CB_COLOR0_INFO) / 0x3c;
1515 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1516 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1517 r = evergreen_cs_packet_next_reloc(p, &reloc);
1518 if (r) {
1519 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1520 "0x%04X\n", reg);
1521 return -EINVAL;
1522 }
1523 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1524 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1525 }
1526 track->cb_dirty = true;
1527 break;
1528 case CB_COLOR8_INFO:
1529 case CB_COLOR9_INFO:
1530 case CB_COLOR10_INFO:
1531 case CB_COLOR11_INFO:
1532 tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8;
1533 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1534 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1535 r = evergreen_cs_packet_next_reloc(p, &reloc);
1536 if (r) {
1537 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1538 "0x%04X\n", reg);
1539 return -EINVAL;
1540 }
1541 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1542 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1543 }
1544 track->cb_dirty = true;
1545 break;
1546 case CB_COLOR0_PITCH:
1547 case CB_COLOR1_PITCH:
1548 case CB_COLOR2_PITCH:
1549 case CB_COLOR3_PITCH:
1550 case CB_COLOR4_PITCH:
1551 case CB_COLOR5_PITCH:
1552 case CB_COLOR6_PITCH:
1553 case CB_COLOR7_PITCH:
1554 tmp = (reg - CB_COLOR0_PITCH) / 0x3c;
1555 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1556 track->cb_dirty = true;
1557 break;
1558 case CB_COLOR8_PITCH:
1559 case CB_COLOR9_PITCH:
1560 case CB_COLOR10_PITCH:
1561 case CB_COLOR11_PITCH:
1562 tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8;
1563 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1564 track->cb_dirty = true;
1565 break;
1566 case CB_COLOR0_SLICE:
1567 case CB_COLOR1_SLICE:
1568 case CB_COLOR2_SLICE:
1569 case CB_COLOR3_SLICE:
1570 case CB_COLOR4_SLICE:
1571 case CB_COLOR5_SLICE:
1572 case CB_COLOR6_SLICE:
1573 case CB_COLOR7_SLICE:
1574 tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
1575 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1576 track->cb_color_slice_idx[tmp] = idx;
1577 track->cb_dirty = true;
1578 break;
1579 case CB_COLOR8_SLICE:
1580 case CB_COLOR9_SLICE:
1581 case CB_COLOR10_SLICE:
1582 case CB_COLOR11_SLICE:
1583 tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
1584 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1585 track->cb_color_slice_idx[tmp] = idx;
1586 track->cb_dirty = true;
1587 break;
1588 case CB_COLOR0_ATTRIB:
1589 case CB_COLOR1_ATTRIB:
1590 case CB_COLOR2_ATTRIB:
1591 case CB_COLOR3_ATTRIB:
1592 case CB_COLOR4_ATTRIB:
1593 case CB_COLOR5_ATTRIB:
1594 case CB_COLOR6_ATTRIB:
1595 case CB_COLOR7_ATTRIB:
1596 r = evergreen_cs_packet_next_reloc(p, &reloc);
1597 if (r) {
1598 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1599 "0x%04X\n", reg);
1600 return -EINVAL;
1601 }
1602 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1603 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1604 unsigned bankw, bankh, mtaspect, tile_split;
1605
1606 evergreen_tiling_fields(reloc->lobj.tiling_flags,
1607 &bankw, &bankh, &mtaspect,
1608 &tile_split);
1609 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1610 ib[idx] |= CB_TILE_SPLIT(tile_split) |
1611 CB_BANK_WIDTH(bankw) |
1612 CB_BANK_HEIGHT(bankh) |
1613 CB_MACRO_TILE_ASPECT(mtaspect);
1614 }
1615 }
1616 tmp = ((reg - CB_COLOR0_ATTRIB) / 0x3c);
1617 track->cb_color_attrib[tmp] = ib[idx];
1618 track->cb_dirty = true;
1619 break;
1620 case CB_COLOR8_ATTRIB:
1621 case CB_COLOR9_ATTRIB:
1622 case CB_COLOR10_ATTRIB:
1623 case CB_COLOR11_ATTRIB:
1624 r = evergreen_cs_packet_next_reloc(p, &reloc);
1625 if (r) {
1626 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1627 "0x%04X\n", reg);
1628 return -EINVAL;
1629 }
1630 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1631 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1632 unsigned bankw, bankh, mtaspect, tile_split;
1633
1634 evergreen_tiling_fields(reloc->lobj.tiling_flags,
1635 &bankw, &bankh, &mtaspect,
1636 &tile_split);
1637 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1638 ib[idx] |= CB_TILE_SPLIT(tile_split) |
1639 CB_BANK_WIDTH(bankw) |
1640 CB_BANK_HEIGHT(bankh) |
1641 CB_MACRO_TILE_ASPECT(mtaspect);
1642 }
1643 }
1644 tmp = ((reg - CB_COLOR8_ATTRIB) / 0x1c) + 8;
1645 track->cb_color_attrib[tmp] = ib[idx];
1646 track->cb_dirty = true;
1647 break;
1648 case CB_COLOR0_FMASK:
1649 case CB_COLOR1_FMASK:
1650 case CB_COLOR2_FMASK:
1651 case CB_COLOR3_FMASK:
1652 case CB_COLOR4_FMASK:
1653 case CB_COLOR5_FMASK:
1654 case CB_COLOR6_FMASK:
1655 case CB_COLOR7_FMASK:
1656 tmp = (reg - CB_COLOR0_FMASK) / 0x3c;
1657 r = evergreen_cs_packet_next_reloc(p, &reloc);
1658 if (r) {
1659 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1660 return -EINVAL;
1661 }
1662 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1663 track->cb_color_fmask_bo[tmp] = reloc->robj;
1664 break;
1665 case CB_COLOR0_CMASK:
1666 case CB_COLOR1_CMASK:
1667 case CB_COLOR2_CMASK:
1668 case CB_COLOR3_CMASK:
1669 case CB_COLOR4_CMASK:
1670 case CB_COLOR5_CMASK:
1671 case CB_COLOR6_CMASK:
1672 case CB_COLOR7_CMASK:
1673 tmp = (reg - CB_COLOR0_CMASK) / 0x3c;
1674 r = evergreen_cs_packet_next_reloc(p, &reloc);
1675 if (r) {
1676 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1677 return -EINVAL;
1678 }
1679 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1680 track->cb_color_cmask_bo[tmp] = reloc->robj;
1681 break;
1682 case CB_COLOR0_FMASK_SLICE:
1683 case CB_COLOR1_FMASK_SLICE:
1684 case CB_COLOR2_FMASK_SLICE:
1685 case CB_COLOR3_FMASK_SLICE:
1686 case CB_COLOR4_FMASK_SLICE:
1687 case CB_COLOR5_FMASK_SLICE:
1688 case CB_COLOR6_FMASK_SLICE:
1689 case CB_COLOR7_FMASK_SLICE:
1690 tmp = (reg - CB_COLOR0_FMASK_SLICE) / 0x3c;
1691 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx);
1692 break;
1693 case CB_COLOR0_CMASK_SLICE:
1694 case CB_COLOR1_CMASK_SLICE:
1695 case CB_COLOR2_CMASK_SLICE:
1696 case CB_COLOR3_CMASK_SLICE:
1697 case CB_COLOR4_CMASK_SLICE:
1698 case CB_COLOR5_CMASK_SLICE:
1699 case CB_COLOR6_CMASK_SLICE:
1700 case CB_COLOR7_CMASK_SLICE:
1701 tmp = (reg - CB_COLOR0_CMASK_SLICE) / 0x3c;
1702 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx);
1703 break;
1704 case CB_COLOR0_BASE:
1705 case CB_COLOR1_BASE:
1706 case CB_COLOR2_BASE:
1707 case CB_COLOR3_BASE:
1708 case CB_COLOR4_BASE:
1709 case CB_COLOR5_BASE:
1710 case CB_COLOR6_BASE:
1711 case CB_COLOR7_BASE:
1712 r = evergreen_cs_packet_next_reloc(p, &reloc);
1713 if (r) {
1714 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1715 "0x%04X\n", reg);
1716 return -EINVAL;
1717 }
1718 tmp = (reg - CB_COLOR0_BASE) / 0x3c;
1719 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1720 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1721 track->cb_color_bo[tmp] = reloc->robj;
1722 track->cb_dirty = true;
1723 break;
1724 case CB_COLOR8_BASE:
1725 case CB_COLOR9_BASE:
1726 case CB_COLOR10_BASE:
1727 case CB_COLOR11_BASE:
1728 r = evergreen_cs_packet_next_reloc(p, &reloc);
1729 if (r) {
1730 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1731 "0x%04X\n", reg);
1732 return -EINVAL;
1733 }
1734 tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8;
1735 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1736 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1737 track->cb_color_bo[tmp] = reloc->robj;
1738 track->cb_dirty = true;
1739 break;
1740 case DB_HTILE_DATA_BASE:
1741 r = evergreen_cs_packet_next_reloc(p, &reloc);
1742 if (r) {
1743 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1744 "0x%04X\n", reg);
1745 return -EINVAL;
1746 }
1747 track->htile_offset = radeon_get_ib_value(p, idx);
1748 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1749 track->htile_bo = reloc->robj;
1750 track->db_dirty = true;
1751 break;
1752 case DB_HTILE_SURFACE:
1753 /* 8x8 only */
1754 track->htile_surface = radeon_get_ib_value(p, idx);
1755 track->db_dirty = true;
1756 break;
1757 case CB_IMMED0_BASE:
1758 case CB_IMMED1_BASE:
1759 case CB_IMMED2_BASE:
1760 case CB_IMMED3_BASE:
1761 case CB_IMMED4_BASE:
1762 case CB_IMMED5_BASE:
1763 case CB_IMMED6_BASE:
1764 case CB_IMMED7_BASE:
1765 case CB_IMMED8_BASE:
1766 case CB_IMMED9_BASE:
1767 case CB_IMMED10_BASE:
1768 case CB_IMMED11_BASE:
1769 case SQ_PGM_START_FS:
1770 case SQ_PGM_START_ES:
1771 case SQ_PGM_START_VS:
1772 case SQ_PGM_START_GS:
1773 case SQ_PGM_START_PS:
1774 case SQ_PGM_START_HS:
1775 case SQ_PGM_START_LS:
1776 case SQ_CONST_MEM_BASE:
1777 case SQ_ALU_CONST_CACHE_GS_0:
1778 case SQ_ALU_CONST_CACHE_GS_1:
1779 case SQ_ALU_CONST_CACHE_GS_2:
1780 case SQ_ALU_CONST_CACHE_GS_3:
1781 case SQ_ALU_CONST_CACHE_GS_4:
1782 case SQ_ALU_CONST_CACHE_GS_5:
1783 case SQ_ALU_CONST_CACHE_GS_6:
1784 case SQ_ALU_CONST_CACHE_GS_7:
1785 case SQ_ALU_CONST_CACHE_GS_8:
1786 case SQ_ALU_CONST_CACHE_GS_9:
1787 case SQ_ALU_CONST_CACHE_GS_10:
1788 case SQ_ALU_CONST_CACHE_GS_11:
1789 case SQ_ALU_CONST_CACHE_GS_12:
1790 case SQ_ALU_CONST_CACHE_GS_13:
1791 case SQ_ALU_CONST_CACHE_GS_14:
1792 case SQ_ALU_CONST_CACHE_GS_15:
1793 case SQ_ALU_CONST_CACHE_PS_0:
1794 case SQ_ALU_CONST_CACHE_PS_1:
1795 case SQ_ALU_CONST_CACHE_PS_2:
1796 case SQ_ALU_CONST_CACHE_PS_3:
1797 case SQ_ALU_CONST_CACHE_PS_4:
1798 case SQ_ALU_CONST_CACHE_PS_5:
1799 case SQ_ALU_CONST_CACHE_PS_6:
1800 case SQ_ALU_CONST_CACHE_PS_7:
1801 case SQ_ALU_CONST_CACHE_PS_8:
1802 case SQ_ALU_CONST_CACHE_PS_9:
1803 case SQ_ALU_CONST_CACHE_PS_10:
1804 case SQ_ALU_CONST_CACHE_PS_11:
1805 case SQ_ALU_CONST_CACHE_PS_12:
1806 case SQ_ALU_CONST_CACHE_PS_13:
1807 case SQ_ALU_CONST_CACHE_PS_14:
1808 case SQ_ALU_CONST_CACHE_PS_15:
1809 case SQ_ALU_CONST_CACHE_VS_0:
1810 case SQ_ALU_CONST_CACHE_VS_1:
1811 case SQ_ALU_CONST_CACHE_VS_2:
1812 case SQ_ALU_CONST_CACHE_VS_3:
1813 case SQ_ALU_CONST_CACHE_VS_4:
1814 case SQ_ALU_CONST_CACHE_VS_5:
1815 case SQ_ALU_CONST_CACHE_VS_6:
1816 case SQ_ALU_CONST_CACHE_VS_7:
1817 case SQ_ALU_CONST_CACHE_VS_8:
1818 case SQ_ALU_CONST_CACHE_VS_9:
1819 case SQ_ALU_CONST_CACHE_VS_10:
1820 case SQ_ALU_CONST_CACHE_VS_11:
1821 case SQ_ALU_CONST_CACHE_VS_12:
1822 case SQ_ALU_CONST_CACHE_VS_13:
1823 case SQ_ALU_CONST_CACHE_VS_14:
1824 case SQ_ALU_CONST_CACHE_VS_15:
1825 case SQ_ALU_CONST_CACHE_HS_0:
1826 case SQ_ALU_CONST_CACHE_HS_1:
1827 case SQ_ALU_CONST_CACHE_HS_2:
1828 case SQ_ALU_CONST_CACHE_HS_3:
1829 case SQ_ALU_CONST_CACHE_HS_4:
1830 case SQ_ALU_CONST_CACHE_HS_5:
1831 case SQ_ALU_CONST_CACHE_HS_6:
1832 case SQ_ALU_CONST_CACHE_HS_7:
1833 case SQ_ALU_CONST_CACHE_HS_8:
1834 case SQ_ALU_CONST_CACHE_HS_9:
1835 case SQ_ALU_CONST_CACHE_HS_10:
1836 case SQ_ALU_CONST_CACHE_HS_11:
1837 case SQ_ALU_CONST_CACHE_HS_12:
1838 case SQ_ALU_CONST_CACHE_HS_13:
1839 case SQ_ALU_CONST_CACHE_HS_14:
1840 case SQ_ALU_CONST_CACHE_HS_15:
1841 case SQ_ALU_CONST_CACHE_LS_0:
1842 case SQ_ALU_CONST_CACHE_LS_1:
1843 case SQ_ALU_CONST_CACHE_LS_2:
1844 case SQ_ALU_CONST_CACHE_LS_3:
1845 case SQ_ALU_CONST_CACHE_LS_4:
1846 case SQ_ALU_CONST_CACHE_LS_5:
1847 case SQ_ALU_CONST_CACHE_LS_6:
1848 case SQ_ALU_CONST_CACHE_LS_7:
1849 case SQ_ALU_CONST_CACHE_LS_8:
1850 case SQ_ALU_CONST_CACHE_LS_9:
1851 case SQ_ALU_CONST_CACHE_LS_10:
1852 case SQ_ALU_CONST_CACHE_LS_11:
1853 case SQ_ALU_CONST_CACHE_LS_12:
1854 case SQ_ALU_CONST_CACHE_LS_13:
1855 case SQ_ALU_CONST_CACHE_LS_14:
1856 case SQ_ALU_CONST_CACHE_LS_15:
1857 r = evergreen_cs_packet_next_reloc(p, &reloc);
1858 if (r) {
1859 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1860 "0x%04X\n", reg);
1861 return -EINVAL;
1862 }
1863 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1864 break;
1865 case SX_MEMORY_EXPORT_BASE:
1866 if (p->rdev->family >= CHIP_CAYMAN) {
1867 dev_warn(p->dev, "bad SET_CONFIG_REG "
1868 "0x%04X\n", reg);
1869 return -EINVAL;
1870 }
1871 r = evergreen_cs_packet_next_reloc(p, &reloc);
1872 if (r) {
1873 dev_warn(p->dev, "bad SET_CONFIG_REG "
1874 "0x%04X\n", reg);
1875 return -EINVAL;
1876 }
1877 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1878 break;
1879 case CAYMAN_SX_SCATTER_EXPORT_BASE:
1880 if (p->rdev->family < CHIP_CAYMAN) {
1881 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1882 "0x%04X\n", reg);
1883 return -EINVAL;
1884 }
1885 r = evergreen_cs_packet_next_reloc(p, &reloc);
1886 if (r) {
1887 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1888 "0x%04X\n", reg);
1889 return -EINVAL;
1890 }
1891 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1892 break;
1893 case SX_MISC:
1894 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1895 break;
1896 default:
1897 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1898 return -EINVAL;
1899 }
1900 return 0;
1901}
1902
1903static bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1904{
1905 u32 last_reg, m, i;
1906
1907 if (p->rdev->family >= CHIP_CAYMAN)
1908 last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
1909 else
1910 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
1911
1912 i = (reg >> 7);
1913 if (i >= last_reg) {
1914 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1915 return false;
1916 }
1917 m = 1 << ((reg >> 2) & 31);
1918 if (p->rdev->family >= CHIP_CAYMAN) {
1919 if (!(cayman_reg_safe_bm[i] & m))
1920 return true;
1921 } else {
1922 if (!(evergreen_reg_safe_bm[i] & m))
1923 return true;
1924 }
1925 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1926 return false;
1927}
1928
1929static int evergreen_packet3_check(struct radeon_cs_parser *p,
1930 struct radeon_cs_packet *pkt)
1931{
1932 struct radeon_cs_reloc *reloc;
1933 struct evergreen_cs_track *track;
1934 volatile u32 *ib;
1935 unsigned idx;
1936 unsigned i;
1937 unsigned start_reg, end_reg, reg;
1938 int r;
1939 u32 idx_value;
1940
1941 track = (struct evergreen_cs_track *)p->track;
1942 ib = p->ib.ptr;
1943 idx = pkt->idx + 1;
1944 idx_value = radeon_get_ib_value(p, idx);
1945
1946 switch (pkt->opcode) {
1947 case PACKET3_SET_PREDICATION:
1948 {
1949 int pred_op;
1950 int tmp;
1951 uint64_t offset;
1952
1953 if (pkt->count != 1) {
1954 DRM_ERROR("bad SET PREDICATION\n");
1955 return -EINVAL;
1956 }
1957
1958 tmp = radeon_get_ib_value(p, idx + 1);
1959 pred_op = (tmp >> 16) & 0x7;
1960
1961 /* for the clear predicate operation */
1962 if (pred_op == 0)
1963 return 0;
1964
1965 if (pred_op > 2) {
1966 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1967 return -EINVAL;
1968 }
1969
1970 r = evergreen_cs_packet_next_reloc(p, &reloc);
1971 if (r) {
1972 DRM_ERROR("bad SET PREDICATION\n");
1973 return -EINVAL;
1974 }
1975
1976 offset = reloc->lobj.gpu_offset +
1977 (idx_value & 0xfffffff0) +
1978 ((u64)(tmp & 0xff) << 32);
1979
1980 ib[idx + 0] = offset;
1981 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1982 }
1983 break;
1984 case PACKET3_CONTEXT_CONTROL:
1985 if (pkt->count != 1) {
1986 DRM_ERROR("bad CONTEXT_CONTROL\n");
1987 return -EINVAL;
1988 }
1989 break;
1990 case PACKET3_INDEX_TYPE:
1991 case PACKET3_NUM_INSTANCES:
1992 case PACKET3_CLEAR_STATE:
1993 if (pkt->count) {
1994 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
1995 return -EINVAL;
1996 }
1997 break;
1998 case CAYMAN_PACKET3_DEALLOC_STATE:
1999 if (p->rdev->family < CHIP_CAYMAN) {
2000 DRM_ERROR("bad PACKET3_DEALLOC_STATE\n");
2001 return -EINVAL;
2002 }
2003 if (pkt->count) {
2004 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
2005 return -EINVAL;
2006 }
2007 break;
2008 case PACKET3_INDEX_BASE:
2009 {
2010 uint64_t offset;
2011
2012 if (pkt->count != 1) {
2013 DRM_ERROR("bad INDEX_BASE\n");
2014 return -EINVAL;
2015 }
2016 r = evergreen_cs_packet_next_reloc(p, &reloc);
2017 if (r) {
2018 DRM_ERROR("bad INDEX_BASE\n");
2019 return -EINVAL;
2020 }
2021
2022 offset = reloc->lobj.gpu_offset +
2023 idx_value +
2024 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
2025
2026 ib[idx+0] = offset;
2027 ib[idx+1] = upper_32_bits(offset) & 0xff;
2028
2029 r = evergreen_cs_track_check(p);
2030 if (r) {
2031 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2032 return r;
2033 }
2034 break;
2035 }
2036 case PACKET3_DRAW_INDEX:
2037 {
2038 uint64_t offset;
2039 if (pkt->count != 3) {
2040 DRM_ERROR("bad DRAW_INDEX\n");
2041 return -EINVAL;
2042 }
2043 r = evergreen_cs_packet_next_reloc(p, &reloc);
2044 if (r) {
2045 DRM_ERROR("bad DRAW_INDEX\n");
2046 return -EINVAL;
2047 }
2048
2049 offset = reloc->lobj.gpu_offset +
2050 idx_value +
2051 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
2052
2053 ib[idx+0] = offset;
2054 ib[idx+1] = upper_32_bits(offset) & 0xff;
2055
2056 r = evergreen_cs_track_check(p);
2057 if (r) {
2058 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2059 return r;
2060 }
2061 break;
2062 }
2063 case PACKET3_DRAW_INDEX_2:
2064 {
2065 uint64_t offset;
2066
2067 if (pkt->count != 4) {
2068 DRM_ERROR("bad DRAW_INDEX_2\n");
2069 return -EINVAL;
2070 }
2071 r = evergreen_cs_packet_next_reloc(p, &reloc);
2072 if (r) {
2073 DRM_ERROR("bad DRAW_INDEX_2\n");
2074 return -EINVAL;
2075 }
2076
2077 offset = reloc->lobj.gpu_offset +
2078 radeon_get_ib_value(p, idx+1) +
2079 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2080
2081 ib[idx+1] = offset;
2082 ib[idx+2] = upper_32_bits(offset) & 0xff;
2083
2084 r = evergreen_cs_track_check(p);
2085 if (r) {
2086 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2087 return r;
2088 }
2089 break;
2090 }
2091 case PACKET3_DRAW_INDEX_AUTO:
2092 if (pkt->count != 1) {
2093 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
2094 return -EINVAL;
2095 }
2096 r = evergreen_cs_track_check(p);
2097 if (r) {
2098 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
2099 return r;
2100 }
2101 break;
2102 case PACKET3_DRAW_INDEX_MULTI_AUTO:
2103 if (pkt->count != 2) {
2104 DRM_ERROR("bad DRAW_INDEX_MULTI_AUTO\n");
2105 return -EINVAL;
2106 }
2107 r = evergreen_cs_track_check(p);
2108 if (r) {
2109 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
2110 return r;
2111 }
2112 break;
2113 case PACKET3_DRAW_INDEX_IMMD:
2114 if (pkt->count < 2) {
2115 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
2116 return -EINVAL;
2117 }
2118 r = evergreen_cs_track_check(p);
2119 if (r) {
2120 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2121 return r;
2122 }
2123 break;
2124 case PACKET3_DRAW_INDEX_OFFSET:
2125 if (pkt->count != 2) {
2126 DRM_ERROR("bad DRAW_INDEX_OFFSET\n");
2127 return -EINVAL;
2128 }
2129 r = evergreen_cs_track_check(p);
2130 if (r) {
2131 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2132 return r;
2133 }
2134 break;
2135 case PACKET3_DRAW_INDEX_OFFSET_2:
2136 if (pkt->count != 3) {
2137 DRM_ERROR("bad DRAW_INDEX_OFFSET_2\n");
2138 return -EINVAL;
2139 }
2140 r = evergreen_cs_track_check(p);
2141 if (r) {
2142 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2143 return r;
2144 }
2145 break;
2146 case PACKET3_DISPATCH_DIRECT:
2147 if (pkt->count != 3) {
2148 DRM_ERROR("bad DISPATCH_DIRECT\n");
2149 return -EINVAL;
2150 }
2151 r = evergreen_cs_track_check(p);
2152 if (r) {
2153 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
2154 return r;
2155 }
2156 break;
2157 case PACKET3_DISPATCH_INDIRECT:
2158 if (pkt->count != 1) {
2159 DRM_ERROR("bad DISPATCH_INDIRECT\n");
2160 return -EINVAL;
2161 }
2162 r = evergreen_cs_packet_next_reloc(p, &reloc);
2163 if (r) {
2164 DRM_ERROR("bad DISPATCH_INDIRECT\n");
2165 return -EINVAL;
2166 }
2167 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
2168 r = evergreen_cs_track_check(p);
2169 if (r) {
2170 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2171 return r;
2172 }
2173 break;
2174 case PACKET3_WAIT_REG_MEM:
2175 if (pkt->count != 5) {
2176 DRM_ERROR("bad WAIT_REG_MEM\n");
2177 return -EINVAL;
2178 }
2179 /* bit 4 is reg (0) or mem (1) */
2180 if (idx_value & 0x10) {
2181 uint64_t offset;
2182
2183 r = evergreen_cs_packet_next_reloc(p, &reloc);
2184 if (r) {
2185 DRM_ERROR("bad WAIT_REG_MEM\n");
2186 return -EINVAL;
2187 }
2188
2189 offset = reloc->lobj.gpu_offset +
2190 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2191 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2192
2193 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc);
2194 ib[idx+2] = upper_32_bits(offset) & 0xff;
2195 }
2196 break;
2197 case PACKET3_SURFACE_SYNC:
2198 if (pkt->count != 3) {
2199 DRM_ERROR("bad SURFACE_SYNC\n");
2200 return -EINVAL;
2201 }
2202 /* 0xffffffff/0x0 is flush all cache flag */
2203 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
2204 radeon_get_ib_value(p, idx + 2) != 0) {
2205 r = evergreen_cs_packet_next_reloc(p, &reloc);
2206 if (r) {
2207 DRM_ERROR("bad SURFACE_SYNC\n");
2208 return -EINVAL;
2209 }
2210 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2211 }
2212 break;
2213 case PACKET3_EVENT_WRITE:
2214 if (pkt->count != 2 && pkt->count != 0) {
2215 DRM_ERROR("bad EVENT_WRITE\n");
2216 return -EINVAL;
2217 }
2218 if (pkt->count) {
2219 uint64_t offset;
2220
2221 r = evergreen_cs_packet_next_reloc(p, &reloc);
2222 if (r) {
2223 DRM_ERROR("bad EVENT_WRITE\n");
2224 return -EINVAL;
2225 }
2226 offset = reloc->lobj.gpu_offset +
2227 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
2228 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2229
2230 ib[idx+1] = offset & 0xfffffff8;
2231 ib[idx+2] = upper_32_bits(offset) & 0xff;
2232 }
2233 break;
2234 case PACKET3_EVENT_WRITE_EOP:
2235 {
2236 uint64_t offset;
2237
2238 if (pkt->count != 4) {
2239 DRM_ERROR("bad EVENT_WRITE_EOP\n");
2240 return -EINVAL;
2241 }
2242 r = evergreen_cs_packet_next_reloc(p, &reloc);
2243 if (r) {
2244 DRM_ERROR("bad EVENT_WRITE_EOP\n");
2245 return -EINVAL;
2246 }
2247
2248 offset = reloc->lobj.gpu_offset +
2249 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2250 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2251
2252 ib[idx+1] = offset & 0xfffffffc;
2253 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2254 break;
2255 }
2256 case PACKET3_EVENT_WRITE_EOS:
2257 {
2258 uint64_t offset;
2259
2260 if (pkt->count != 3) {
2261 DRM_ERROR("bad EVENT_WRITE_EOS\n");
2262 return -EINVAL;
2263 }
2264 r = evergreen_cs_packet_next_reloc(p, &reloc);
2265 if (r) {
2266 DRM_ERROR("bad EVENT_WRITE_EOS\n");
2267 return -EINVAL;
2268 }
2269
2270 offset = reloc->lobj.gpu_offset +
2271 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2272 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2273
2274 ib[idx+1] = offset & 0xfffffffc;
2275 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2276 break;
2277 }
2278 case PACKET3_SET_CONFIG_REG:
2279 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2280 end_reg = 4 * pkt->count + start_reg - 4;
2281 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2282 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2283 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2284 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2285 return -EINVAL;
2286 }
2287 for (i = 0; i < pkt->count; i++) {
2288 reg = start_reg + (4 * i);
2289 r = evergreen_cs_check_reg(p, reg, idx+1+i);
2290 if (r)
2291 return r;
2292 }
2293 break;
2294 case PACKET3_SET_CONTEXT_REG:
2295 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START;
2296 end_reg = 4 * pkt->count + start_reg - 4;
2297 if ((start_reg < PACKET3_SET_CONTEXT_REG_START) ||
2298 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
2299 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
2300 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
2301 return -EINVAL;
2302 }
2303 for (i = 0; i < pkt->count; i++) {
2304 reg = start_reg + (4 * i);
2305 r = evergreen_cs_check_reg(p, reg, idx+1+i);
2306 if (r)
2307 return r;
2308 }
2309 break;
2310 case PACKET3_SET_RESOURCE:
2311 if (pkt->count % 8) {
2312 DRM_ERROR("bad SET_RESOURCE\n");
2313 return -EINVAL;
2314 }
2315 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START;
2316 end_reg = 4 * pkt->count + start_reg - 4;
2317 if ((start_reg < PACKET3_SET_RESOURCE_START) ||
2318 (start_reg >= PACKET3_SET_RESOURCE_END) ||
2319 (end_reg >= PACKET3_SET_RESOURCE_END)) {
2320 DRM_ERROR("bad SET_RESOURCE\n");
2321 return -EINVAL;
2322 }
2323 for (i = 0; i < (pkt->count / 8); i++) {
2324 struct radeon_bo *texture, *mipmap;
2325 u32 toffset, moffset;
2326 u32 size, offset;
2327
2328 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) {
2329 case SQ_TEX_VTX_VALID_TEXTURE:
2330 /* tex base */
2331 r = evergreen_cs_packet_next_reloc(p, &reloc);
2332 if (r) {
2333 DRM_ERROR("bad SET_RESOURCE (tex)\n");
2334 return -EINVAL;
2335 }
2336 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
2337 ib[idx+1+(i*8)+1] |=
2338 TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
2339 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
2340 unsigned bankw, bankh, mtaspect, tile_split;
2341
2342 evergreen_tiling_fields(reloc->lobj.tiling_flags,
2343 &bankw, &bankh, &mtaspect,
2344 &tile_split);
2345 ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split);
2346 ib[idx+1+(i*8)+7] |=
2347 TEX_BANK_WIDTH(bankw) |
2348 TEX_BANK_HEIGHT(bankh) |
2349 MACRO_TILE_ASPECT(mtaspect) |
2350 TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
2351 }
2352 }
2353 texture = reloc->robj;
2354 toffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2355 /* tex mip base */
2356 r = evergreen_cs_packet_next_reloc(p, &reloc);
2357 if (r) {
2358 DRM_ERROR("bad SET_RESOURCE (tex)\n");
2359 return -EINVAL;
2360 }
2361 moffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2362 mipmap = reloc->robj;
2363 r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8));
2364 if (r)
2365 return r;
2366 ib[idx+1+(i*8)+2] += toffset;
2367 ib[idx+1+(i*8)+3] += moffset;
2368 break;
2369 case SQ_TEX_VTX_VALID_BUFFER:
2370 {
2371 uint64_t offset64;
2372 /* vtx base */
2373 r = evergreen_cs_packet_next_reloc(p, &reloc);
2374 if (r) {
2375 DRM_ERROR("bad SET_RESOURCE (vtx)\n");
2376 return -EINVAL;
2377 }
2378 offset = radeon_get_ib_value(p, idx+1+(i*8)+0);
2379 size = radeon_get_ib_value(p, idx+1+(i*8)+1);
2380 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2381 /* force size to size of the buffer */
2382 dev_warn(p->dev, "vbo resource seems too big for the bo\n");
2383 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset;
2384 }
2385
2386 offset64 = reloc->lobj.gpu_offset + offset;
2387 ib[idx+1+(i*8)+0] = offset64;
2388 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
2389 (upper_32_bits(offset64) & 0xff);
2390 break;
2391 }
2392 case SQ_TEX_VTX_INVALID_TEXTURE:
2393 case SQ_TEX_VTX_INVALID_BUFFER:
2394 default:
2395 DRM_ERROR("bad SET_RESOURCE\n");
2396 return -EINVAL;
2397 }
2398 }
2399 break;
2400 case PACKET3_SET_ALU_CONST:
2401 /* XXX fix me ALU const buffers only */
2402 break;
2403 case PACKET3_SET_BOOL_CONST:
2404 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_START;
2405 end_reg = 4 * pkt->count + start_reg - 4;
2406 if ((start_reg < PACKET3_SET_BOOL_CONST_START) ||
2407 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
2408 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
2409 DRM_ERROR("bad SET_BOOL_CONST\n");
2410 return -EINVAL;
2411 }
2412 break;
2413 case PACKET3_SET_LOOP_CONST:
2414 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_START;
2415 end_reg = 4 * pkt->count + start_reg - 4;
2416 if ((start_reg < PACKET3_SET_LOOP_CONST_START) ||
2417 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
2418 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
2419 DRM_ERROR("bad SET_LOOP_CONST\n");
2420 return -EINVAL;
2421 }
2422 break;
2423 case PACKET3_SET_CTL_CONST:
2424 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_START;
2425 end_reg = 4 * pkt->count + start_reg - 4;
2426 if ((start_reg < PACKET3_SET_CTL_CONST_START) ||
2427 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
2428 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
2429 DRM_ERROR("bad SET_CTL_CONST\n");
2430 return -EINVAL;
2431 }
2432 break;
2433 case PACKET3_SET_SAMPLER:
2434 if (pkt->count % 3) {
2435 DRM_ERROR("bad SET_SAMPLER\n");
2436 return -EINVAL;
2437 }
2438 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_START;
2439 end_reg = 4 * pkt->count + start_reg - 4;
2440 if ((start_reg < PACKET3_SET_SAMPLER_START) ||
2441 (start_reg >= PACKET3_SET_SAMPLER_END) ||
2442 (end_reg >= PACKET3_SET_SAMPLER_END)) {
2443 DRM_ERROR("bad SET_SAMPLER\n");
2444 return -EINVAL;
2445 }
2446 break;
2447 case PACKET3_STRMOUT_BUFFER_UPDATE:
2448 if (pkt->count != 4) {
2449 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
2450 return -EINVAL;
2451 }
2452 /* Updating memory at DST_ADDRESS. */
2453 if (idx_value & 0x1) {
2454 u64 offset;
2455 r = evergreen_cs_packet_next_reloc(p, &reloc);
2456 if (r) {
2457 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2458 return -EINVAL;
2459 }
2460 offset = radeon_get_ib_value(p, idx+1);
2461 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2462 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2463 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",
2464 offset + 4, radeon_bo_size(reloc->robj));
2465 return -EINVAL;
2466 }
2467 offset += reloc->lobj.gpu_offset;
2468 ib[idx+1] = offset;
2469 ib[idx+2] = upper_32_bits(offset) & 0xff;
2470 }
2471 /* Reading data from SRC_ADDRESS. */
2472 if (((idx_value >> 1) & 0x3) == 2) {
2473 u64 offset;
2474 r = evergreen_cs_packet_next_reloc(p, &reloc);
2475 if (r) {
2476 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2477 return -EINVAL;
2478 }
2479 offset = radeon_get_ib_value(p, idx+3);
2480 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2481 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2482 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",
2483 offset + 4, radeon_bo_size(reloc->robj));
2484 return -EINVAL;
2485 }
2486 offset += reloc->lobj.gpu_offset;
2487 ib[idx+3] = offset;
2488 ib[idx+4] = upper_32_bits(offset) & 0xff;
2489 }
2490 break;
2491 case PACKET3_COPY_DW:
2492 if (pkt->count != 4) {
2493 DRM_ERROR("bad COPY_DW (invalid count)\n");
2494 return -EINVAL;
2495 }
2496 if (idx_value & 0x1) {
2497 u64 offset;
2498 /* SRC is memory. */
2499 r = evergreen_cs_packet_next_reloc(p, &reloc);
2500 if (r) {
2501 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2502 return -EINVAL;
2503 }
2504 offset = radeon_get_ib_value(p, idx+1);
2505 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2506 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2507 DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",
2508 offset + 4, radeon_bo_size(reloc->robj));
2509 return -EINVAL;
2510 }
2511 offset += reloc->lobj.gpu_offset;
2512 ib[idx+1] = offset;
2513 ib[idx+2] = upper_32_bits(offset) & 0xff;
2514 } else {
2515 /* SRC is a reg. */
2516 reg = radeon_get_ib_value(p, idx+1) << 2;
2517 if (!evergreen_is_safe_reg(p, reg, idx+1))
2518 return -EINVAL;
2519 }
2520 if (idx_value & 0x2) {
2521 u64 offset;
2522 /* DST is memory. */
2523 r = evergreen_cs_packet_next_reloc(p, &reloc);
2524 if (r) {
2525 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2526 return -EINVAL;
2527 }
2528 offset = radeon_get_ib_value(p, idx+3);
2529 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2530 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2531 DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",
2532 offset + 4, radeon_bo_size(reloc->robj));
2533 return -EINVAL;
2534 }
2535 offset += reloc->lobj.gpu_offset;
2536 ib[idx+3] = offset;
2537 ib[idx+4] = upper_32_bits(offset) & 0xff;
2538 } else {
2539 /* DST is a reg. */
2540 reg = radeon_get_ib_value(p, idx+3) << 2;
2541 if (!evergreen_is_safe_reg(p, reg, idx+3))
2542 return -EINVAL;
2543 }
2544 break;
2545 case PACKET3_NOP:
2546 break;
2547 default:
2548 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2549 return -EINVAL;
2550 }
2551 return 0;
2552}
2553
2554int evergreen_cs_parse(struct radeon_cs_parser *p)
2555{
2556 struct radeon_cs_packet pkt;
2557 struct evergreen_cs_track *track;
2558 u32 tmp;
2559 int r;
2560
2561 if (p->track == NULL) {
2562 /* initialize tracker, we are in kms */
2563 track = kzalloc(sizeof(*track), GFP_KERNEL);
2564 if (track == NULL)
2565 return -ENOMEM;
2566 evergreen_cs_track_init(track);
2567 if (p->rdev->family >= CHIP_CAYMAN)
2568 tmp = p->rdev->config.cayman.tile_config;
2569 else
2570 tmp = p->rdev->config.evergreen.tile_config;
2571
2572 switch (tmp & 0xf) {
2573 case 0:
2574 track->npipes = 1;
2575 break;
2576 case 1:
2577 default:
2578 track->npipes = 2;
2579 break;
2580 case 2:
2581 track->npipes = 4;
2582 break;
2583 case 3:
2584 track->npipes = 8;
2585 break;
2586 }
2587
2588 switch ((tmp & 0xf0) >> 4) {
2589 case 0:
2590 track->nbanks = 4;
2591 break;
2592 case 1:
2593 default:
2594 track->nbanks = 8;
2595 break;
2596 case 2:
2597 track->nbanks = 16;
2598 break;
2599 }
2600
2601 switch ((tmp & 0xf00) >> 8) {
2602 case 0:
2603 track->group_size = 256;
2604 break;
2605 case 1:
2606 default:
2607 track->group_size = 512;
2608 break;
2609 }
2610
2611 switch ((tmp & 0xf000) >> 12) {
2612 case 0:
2613 track->row_size = 1;
2614 break;
2615 case 1:
2616 default:
2617 track->row_size = 2;
2618 break;
2619 case 2:
2620 track->row_size = 4;
2621 break;
2622 }
2623
2624 p->track = track;
2625 }
2626 do {
2627 r = evergreen_cs_packet_parse(p, &pkt, p->idx);
2628 if (r) {
2629 kfree(p->track);
2630 p->track = NULL;
2631 return r;
2632 }
2633 p->idx += pkt.count + 2;
2634 switch (pkt.type) {
2635 case PACKET_TYPE0:
2636 r = evergreen_cs_parse_packet0(p, &pkt);
2637 break;
2638 case PACKET_TYPE2:
2639 break;
2640 case PACKET_TYPE3:
2641 r = evergreen_packet3_check(p, &pkt);
2642 break;
2643 default:
2644 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
2645 kfree(p->track);
2646 p->track = NULL;
2647 return -EINVAL;
2648 }
2649 if (r) {
2650 kfree(p->track);
2651 p->track = NULL;
2652 return r;
2653 }
2654 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2655#if 0
2656 for (r = 0; r < p->ib.length_dw; r++) {
2657 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]);
2658 mdelay(1);
2659 }
2660#endif
2661 kfree(p->track);
2662 p->track = NULL;
2663 return 0;
2664}
2665
2666/* vm parser */
2667static bool evergreen_vm_reg_valid(u32 reg)
2668{
2669 /* context regs are fine */
2670 if (reg >= 0x28000)
2671 return true;
2672
2673 /* check config regs */
2674 switch (reg) {
2675 case GRBM_GFX_INDEX:
2676 case VGT_VTX_VECT_EJECT_REG:
2677 case VGT_CACHE_INVALIDATION:
2678 case VGT_GS_VERTEX_REUSE:
2679 case VGT_PRIMITIVE_TYPE:
2680 case VGT_INDEX_TYPE:
2681 case VGT_NUM_INDICES:
2682 case VGT_NUM_INSTANCES:
2683 case VGT_COMPUTE_DIM_X:
2684 case VGT_COMPUTE_DIM_Y:
2685 case VGT_COMPUTE_DIM_Z:
2686 case VGT_COMPUTE_START_X:
2687 case VGT_COMPUTE_START_Y:
2688 case VGT_COMPUTE_START_Z:
2689 case VGT_COMPUTE_INDEX:
2690 case VGT_COMPUTE_THREAD_GROUP_SIZE:
2691 case VGT_HS_OFFCHIP_PARAM:
2692 case PA_CL_ENHANCE:
2693 case PA_SU_LINE_STIPPLE_VALUE:
2694 case PA_SC_LINE_STIPPLE_STATE:
2695 case PA_SC_ENHANCE:
2696 case SQ_DYN_GPR_CNTL_PS_FLUSH_REQ:
2697 case SQ_DYN_GPR_SIMD_LOCK_EN:
2698 case SQ_CONFIG:
2699 case SQ_GPR_RESOURCE_MGMT_1:
2700 case SQ_GLOBAL_GPR_RESOURCE_MGMT_1:
2701 case SQ_GLOBAL_GPR_RESOURCE_MGMT_2:
2702 case SQ_CONST_MEM_BASE:
2703 case SQ_STATIC_THREAD_MGMT_1:
2704 case SQ_STATIC_THREAD_MGMT_2:
2705 case SQ_STATIC_THREAD_MGMT_3:
2706 case SPI_CONFIG_CNTL:
2707 case SPI_CONFIG_CNTL_1:
2708 case TA_CNTL_AUX:
2709 case DB_DEBUG:
2710 case DB_DEBUG2:
2711 case DB_DEBUG3:
2712 case DB_DEBUG4:
2713 case DB_WATERMARKS:
2714 case TD_PS_BORDER_COLOR_INDEX:
2715 case TD_PS_BORDER_COLOR_RED:
2716 case TD_PS_BORDER_COLOR_GREEN:
2717 case TD_PS_BORDER_COLOR_BLUE:
2718 case TD_PS_BORDER_COLOR_ALPHA:
2719 case TD_VS_BORDER_COLOR_INDEX:
2720 case TD_VS_BORDER_COLOR_RED:
2721 case TD_VS_BORDER_COLOR_GREEN:
2722 case TD_VS_BORDER_COLOR_BLUE:
2723 case TD_VS_BORDER_COLOR_ALPHA:
2724 case TD_GS_BORDER_COLOR_INDEX:
2725 case TD_GS_BORDER_COLOR_RED:
2726 case TD_GS_BORDER_COLOR_GREEN:
2727 case TD_GS_BORDER_COLOR_BLUE:
2728 case TD_GS_BORDER_COLOR_ALPHA:
2729 case TD_HS_BORDER_COLOR_INDEX:
2730 case TD_HS_BORDER_COLOR_RED:
2731 case TD_HS_BORDER_COLOR_GREEN:
2732 case TD_HS_BORDER_COLOR_BLUE:
2733 case TD_HS_BORDER_COLOR_ALPHA:
2734 case TD_LS_BORDER_COLOR_INDEX:
2735 case TD_LS_BORDER_COLOR_RED:
2736 case TD_LS_BORDER_COLOR_GREEN:
2737 case TD_LS_BORDER_COLOR_BLUE:
2738 case TD_LS_BORDER_COLOR_ALPHA:
2739 case TD_CS_BORDER_COLOR_INDEX:
2740 case TD_CS_BORDER_COLOR_RED:
2741 case TD_CS_BORDER_COLOR_GREEN:
2742 case TD_CS_BORDER_COLOR_BLUE:
2743 case TD_CS_BORDER_COLOR_ALPHA:
2744 case SQ_ESGS_RING_SIZE:
2745 case SQ_GSVS_RING_SIZE:
2746 case SQ_ESTMP_RING_SIZE:
2747 case SQ_GSTMP_RING_SIZE:
2748 case SQ_HSTMP_RING_SIZE:
2749 case SQ_LSTMP_RING_SIZE:
2750 case SQ_PSTMP_RING_SIZE:
2751 case SQ_VSTMP_RING_SIZE:
2752 case SQ_ESGS_RING_ITEMSIZE:
2753 case SQ_ESTMP_RING_ITEMSIZE:
2754 case SQ_GSTMP_RING_ITEMSIZE:
2755 case SQ_GSVS_RING_ITEMSIZE:
2756 case SQ_GS_VERT_ITEMSIZE:
2757 case SQ_GS_VERT_ITEMSIZE_1:
2758 case SQ_GS_VERT_ITEMSIZE_2:
2759 case SQ_GS_VERT_ITEMSIZE_3:
2760 case SQ_GSVS_RING_OFFSET_1:
2761 case SQ_GSVS_RING_OFFSET_2:
2762 case SQ_GSVS_RING_OFFSET_3:
2763 case SQ_HSTMP_RING_ITEMSIZE:
2764 case SQ_LSTMP_RING_ITEMSIZE:
2765 case SQ_PSTMP_RING_ITEMSIZE:
2766 case SQ_VSTMP_RING_ITEMSIZE:
2767 case VGT_TF_RING_SIZE:
2768 case SQ_ESGS_RING_BASE:
2769 case SQ_GSVS_RING_BASE:
2770 case SQ_ESTMP_RING_BASE:
2771 case SQ_GSTMP_RING_BASE:
2772 case SQ_HSTMP_RING_BASE:
2773 case SQ_LSTMP_RING_BASE:
2774 case SQ_PSTMP_RING_BASE:
2775 case SQ_VSTMP_RING_BASE:
2776 case CAYMAN_VGT_OFFCHIP_LDS_BASE:
2777 case CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS:
2778 return true;
2779 default:
2780 return false;
2781 }
2782}
2783
2784static int evergreen_vm_packet3_check(struct radeon_device *rdev,
2785 u32 *ib, struct radeon_cs_packet *pkt)
2786{
2787 u32 idx = pkt->idx + 1;
2788 u32 idx_value = ib[idx];
2789 u32 start_reg, end_reg, reg, i;
2790
2791 switch (pkt->opcode) {
2792 case PACKET3_NOP:
2793 case PACKET3_SET_BASE:
2794 case PACKET3_CLEAR_STATE:
2795 case PACKET3_INDEX_BUFFER_SIZE:
2796 case PACKET3_DISPATCH_DIRECT:
2797 case PACKET3_DISPATCH_INDIRECT:
2798 case PACKET3_MODE_CONTROL:
2799 case PACKET3_SET_PREDICATION:
2800 case PACKET3_COND_EXEC:
2801 case PACKET3_PRED_EXEC:
2802 case PACKET3_DRAW_INDIRECT:
2803 case PACKET3_DRAW_INDEX_INDIRECT:
2804 case PACKET3_INDEX_BASE:
2805 case PACKET3_DRAW_INDEX_2:
2806 case PACKET3_CONTEXT_CONTROL:
2807 case PACKET3_DRAW_INDEX_OFFSET:
2808 case PACKET3_INDEX_TYPE:
2809 case PACKET3_DRAW_INDEX:
2810 case PACKET3_DRAW_INDEX_AUTO:
2811 case PACKET3_DRAW_INDEX_IMMD:
2812 case PACKET3_NUM_INSTANCES:
2813 case PACKET3_DRAW_INDEX_MULTI_AUTO:
2814 case PACKET3_STRMOUT_BUFFER_UPDATE:
2815 case PACKET3_DRAW_INDEX_OFFSET_2:
2816 case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
2817 case PACKET3_MPEG_INDEX:
2818 case PACKET3_WAIT_REG_MEM:
2819 case PACKET3_MEM_WRITE:
2820 case PACKET3_SURFACE_SYNC:
2821 case PACKET3_EVENT_WRITE:
2822 case PACKET3_EVENT_WRITE_EOP:
2823 case PACKET3_EVENT_WRITE_EOS:
2824 case PACKET3_SET_CONTEXT_REG:
2825 case PACKET3_SET_BOOL_CONST:
2826 case PACKET3_SET_LOOP_CONST:
2827 case PACKET3_SET_RESOURCE:
2828 case PACKET3_SET_SAMPLER:
2829 case PACKET3_SET_CTL_CONST:
2830 case PACKET3_SET_RESOURCE_OFFSET:
2831 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2832 case PACKET3_SET_RESOURCE_INDIRECT:
2833 case CAYMAN_PACKET3_DEALLOC_STATE:
2834 break;
2835 case PACKET3_COND_WRITE:
2836 if (idx_value & 0x100) {
2837 reg = ib[idx + 5] * 4;
2838 if (!evergreen_vm_reg_valid(reg))
2839 return -EINVAL;
2840 }
2841 break;
2842 case PACKET3_COPY_DW:
2843 if (idx_value & 0x2) {
2844 reg = ib[idx + 3] * 4;
2845 if (!evergreen_vm_reg_valid(reg))
2846 return -EINVAL;
2847 }
2848 break;
2849 case PACKET3_SET_CONFIG_REG:
2850 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2851 end_reg = 4 * pkt->count + start_reg - 4;
2852 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2853 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2854 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2855 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2856 return -EINVAL;
2857 }
2858 for (i = 0; i < pkt->count; i++) {
2859 reg = start_reg + (4 * i);
2860 if (!evergreen_vm_reg_valid(reg))
2861 return -EINVAL;
2862 }
2863 break;
2864 default:
2865 return -EINVAL;
2866 }
2867 return 0;
2868}
2869
2870int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
2871{
2872 int ret = 0;
2873 u32 idx = 0;
2874 struct radeon_cs_packet pkt;
2875
2876 do {
2877 pkt.idx = idx;
2878 pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]);
2879 pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]);
2880 pkt.one_reg_wr = 0;
2881 switch (pkt.type) {
2882 case PACKET_TYPE0:
2883 dev_err(rdev->dev, "Packet0 not allowed!\n");
2884 ret = -EINVAL;
2885 break;
2886 case PACKET_TYPE2:
2887 idx += 1;
2888 break;
2889 case PACKET_TYPE3:
2890 pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
2891 ret = evergreen_vm_packet3_check(rdev, ib->ptr, &pkt);
2892 idx += pkt.count + 2;
2893 break;
2894 default:
2895 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
2896 ret = -EINVAL;
2897 break;
2898 }
2899 if (ret)
2900 break;
2901 } while (idx < ib->length_dw);
2902
2903 return ret;
2904}