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1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#ifndef EVERGREEND_H
25#define EVERGREEND_H
26
27#define EVERGREEN_MAX_SH_GPRS 256
28#define EVERGREEN_MAX_TEMP_GPRS 16
29#define EVERGREEN_MAX_SH_THREADS 256
30#define EVERGREEN_MAX_SH_STACK_ENTRIES 4096
31#define EVERGREEN_MAX_FRC_EOV_CNT 16384
32#define EVERGREEN_MAX_BACKENDS 8
33#define EVERGREEN_MAX_BACKENDS_MASK 0xFF
34#define EVERGREEN_MAX_SIMDS 16
35#define EVERGREEN_MAX_SIMDS_MASK 0xFFFF
36#define EVERGREEN_MAX_PIPES 8
37#define EVERGREEN_MAX_PIPES_MASK 0xFF
38#define EVERGREEN_MAX_LDS_NUM 0xFFFF
39
40#define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003
41#define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003
42#define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
43#define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002
44#define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002
45#define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002
46#define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001
47#define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001
48
49/* Registers */
50
51#define RCU_IND_INDEX 0x100
52#define RCU_IND_DATA 0x104
53
54#define GRBM_GFX_INDEX 0x802C
55#define INSTANCE_INDEX(x) ((x) << 0)
56#define SE_INDEX(x) ((x) << 16)
57#define INSTANCE_BROADCAST_WRITES (1 << 30)
58#define SE_BROADCAST_WRITES (1 << 31)
59#define RLC_GFX_INDEX 0x3fC4
60#define CC_GC_SHADER_PIPE_CONFIG 0x8950
61#define WRITE_DIS (1 << 0)
62#define CC_RB_BACKEND_DISABLE 0x98F4
63#define BACKEND_DISABLE(x) ((x) << 16)
64#define GB_ADDR_CONFIG 0x98F8
65#define NUM_PIPES(x) ((x) << 0)
66#define NUM_PIPES_MASK 0x0000000f
67#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
68#define BANK_INTERLEAVE_SIZE(x) ((x) << 8)
69#define NUM_SHADER_ENGINES(x) ((x) << 12)
70#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
71#define NUM_GPUS(x) ((x) << 20)
72#define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
73#define ROW_SIZE(x) ((x) << 28)
74#define GB_BACKEND_MAP 0x98FC
75#define DMIF_ADDR_CONFIG 0xBD4
76#define HDP_ADDR_CONFIG 0x2F48
77#define HDP_MISC_CNTL 0x2F4C
78#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
79
80#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
81#define GC_USER_RB_BACKEND_DISABLE 0x9B7C
82
83#define CGTS_SYS_TCC_DISABLE 0x3F90
84#define CGTS_TCC_DISABLE 0x9148
85#define CGTS_USER_SYS_TCC_DISABLE 0x3F94
86#define CGTS_USER_TCC_DISABLE 0x914C
87
88#define CONFIG_MEMSIZE 0x5428
89
90#define CP_COHER_BASE 0x85F8
91#define CP_ME_CNTL 0x86D8
92#define CP_ME_HALT (1 << 28)
93#define CP_PFP_HALT (1 << 26)
94#define CP_ME_RAM_DATA 0xC160
95#define CP_ME_RAM_RADDR 0xC158
96#define CP_ME_RAM_WADDR 0xC15C
97#define CP_MEQ_THRESHOLDS 0x8764
98#define STQ_SPLIT(x) ((x) << 0)
99#define CP_PERFMON_CNTL 0x87FC
100#define CP_PFP_UCODE_ADDR 0xC150
101#define CP_PFP_UCODE_DATA 0xC154
102#define CP_QUEUE_THRESHOLDS 0x8760
103#define ROQ_IB1_START(x) ((x) << 0)
104#define ROQ_IB2_START(x) ((x) << 8)
105#define CP_RB_BASE 0xC100
106#define CP_RB_CNTL 0xC104
107#define RB_BUFSZ(x) ((x) << 0)
108#define RB_BLKSZ(x) ((x) << 8)
109#define RB_NO_UPDATE (1 << 27)
110#define RB_RPTR_WR_ENA (1 << 31)
111#define BUF_SWAP_32BIT (2 << 16)
112#define CP_RB_RPTR 0x8700
113#define CP_RB_RPTR_ADDR 0xC10C
114#define RB_RPTR_SWAP(x) ((x) << 0)
115#define CP_RB_RPTR_ADDR_HI 0xC110
116#define CP_RB_RPTR_WR 0xC108
117#define CP_RB_WPTR 0xC114
118#define CP_RB_WPTR_ADDR 0xC118
119#define CP_RB_WPTR_ADDR_HI 0xC11C
120#define CP_RB_WPTR_DELAY 0x8704
121#define CP_SEM_WAIT_TIMER 0x85BC
122#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
123#define CP_DEBUG 0xC1FC
124
125/* Audio clocks */
126#define DCCG_AUDIO_DTO_SOURCE 0x05ac
127# define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */
128# define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */
129
130#define DCCG_AUDIO_DTO0_PHASE 0x05b0
131#define DCCG_AUDIO_DTO0_MODULE 0x05b4
132#define DCCG_AUDIO_DTO0_LOAD 0x05b8
133#define DCCG_AUDIO_DTO0_CNTL 0x05bc
134
135#define DCCG_AUDIO_DTO1_PHASE 0x05c0
136#define DCCG_AUDIO_DTO1_MODULE 0x05c4
137#define DCCG_AUDIO_DTO1_LOAD 0x05c8
138#define DCCG_AUDIO_DTO1_CNTL 0x05cc
139
140/* DCE 4.0 AFMT */
141#define HDMI_CONTROL 0x7030
142# define HDMI_KEEPOUT_MODE (1 << 0)
143# define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */
144# define HDMI_ERROR_ACK (1 << 8)
145# define HDMI_ERROR_MASK (1 << 9)
146# define HDMI_DEEP_COLOR_ENABLE (1 << 24)
147# define HDMI_DEEP_COLOR_DEPTH (((x) & 3) << 28)
148# define HDMI_24BIT_DEEP_COLOR 0
149# define HDMI_30BIT_DEEP_COLOR 1
150# define HDMI_36BIT_DEEP_COLOR 2
151#define HDMI_STATUS 0x7034
152# define HDMI_ACTIVE_AVMUTE (1 << 0)
153# define HDMI_AUDIO_PACKET_ERROR (1 << 16)
154# define HDMI_VBI_PACKET_ERROR (1 << 20)
155#define HDMI_AUDIO_PACKET_CONTROL 0x7038
156# define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4)
157# define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16)
158#define HDMI_ACR_PACKET_CONTROL 0x703c
159# define HDMI_ACR_SEND (1 << 0)
160# define HDMI_ACR_CONT (1 << 1)
161# define HDMI_ACR_SELECT(x) (((x) & 3) << 4)
162# define HDMI_ACR_HW 0
163# define HDMI_ACR_32 1
164# define HDMI_ACR_44 2
165# define HDMI_ACR_48 3
166# define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */
167# define HDMI_ACR_AUTO_SEND (1 << 12)
168# define HDMI_ACR_N_MULTIPLE(x) (((x) & 7) << 16)
169# define HDMI_ACR_X1 1
170# define HDMI_ACR_X2 2
171# define HDMI_ACR_X4 4
172# define HDMI_ACR_AUDIO_PRIORITY (1 << 31)
173#define HDMI_VBI_PACKET_CONTROL 0x7040
174# define HDMI_NULL_SEND (1 << 0)
175# define HDMI_GC_SEND (1 << 4)
176# define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */
177#define HDMI_INFOFRAME_CONTROL0 0x7044
178# define HDMI_AVI_INFO_SEND (1 << 0)
179# define HDMI_AVI_INFO_CONT (1 << 1)
180# define HDMI_AUDIO_INFO_SEND (1 << 4)
181# define HDMI_AUDIO_INFO_CONT (1 << 5)
182# define HDMI_MPEG_INFO_SEND (1 << 8)
183# define HDMI_MPEG_INFO_CONT (1 << 9)
184#define HDMI_INFOFRAME_CONTROL1 0x7048
185# define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0)
186# define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8)
187# define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16)
188#define HDMI_GENERIC_PACKET_CONTROL 0x704c
189# define HDMI_GENERIC0_SEND (1 << 0)
190# define HDMI_GENERIC0_CONT (1 << 1)
191# define HDMI_GENERIC1_SEND (1 << 4)
192# define HDMI_GENERIC1_CONT (1 << 5)
193# define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16)
194# define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24)
195#define HDMI_GC 0x7058
196# define HDMI_GC_AVMUTE (1 << 0)
197# define HDMI_GC_AVMUTE_CONT (1 << 2)
198#define AFMT_AUDIO_PACKET_CONTROL2 0x705c
199# define AFMT_AUDIO_LAYOUT_OVRD (1 << 0)
200# define AFMT_AUDIO_LAYOUT_SELECT (1 << 1)
201# define AFMT_60958_CS_SOURCE (1 << 4)
202# define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8)
203# define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16)
204#define AFMT_AVI_INFO0 0x7084
205# define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
206# define AFMT_AVI_INFO_S(x) (((x) & 3) << 8)
207# define AFMT_AVI_INFO_B(x) (((x) & 3) << 10)
208# define AFMT_AVI_INFO_A(x) (((x) & 1) << 12)
209# define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13)
210# define AFMT_AVI_INFO_Y_RGB 0
211# define AFMT_AVI_INFO_Y_YCBCR422 1
212# define AFMT_AVI_INFO_Y_YCBCR444 2
213# define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8)
214# define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16)
215# define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20)
216# define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22)
217# define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16)
218# define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24)
219# define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26)
220# define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28)
221# define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31)
222# define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24)
223#define AFMT_AVI_INFO1 0x7088
224# define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */
225# define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */
226# define AFMT_AVI_INFO_CN(x) (((x) & 0x3) << 12)
227# define AFMT_AVI_INFO_YQ(x) (((x) & 0x3) << 14)
228# define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16)
229#define AFMT_AVI_INFO2 0x708c
230# define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0)
231# define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16)
232#define AFMT_AVI_INFO3 0x7090
233# define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0)
234# define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24)
235#define AFMT_MPEG_INFO0 0x7094
236# define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
237# define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8)
238# define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16)
239# define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24)
240#define AFMT_MPEG_INFO1 0x7098
241# define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0)
242# define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8)
243# define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12)
244#define AFMT_GENERIC0_HDR 0x709c
245#define AFMT_GENERIC0_0 0x70a0
246#define AFMT_GENERIC0_1 0x70a4
247#define AFMT_GENERIC0_2 0x70a8
248#define AFMT_GENERIC0_3 0x70ac
249#define AFMT_GENERIC0_4 0x70b0
250#define AFMT_GENERIC0_5 0x70b4
251#define AFMT_GENERIC0_6 0x70b8
252#define AFMT_GENERIC1_HDR 0x70bc
253#define AFMT_GENERIC1_0 0x70c0
254#define AFMT_GENERIC1_1 0x70c4
255#define AFMT_GENERIC1_2 0x70c8
256#define AFMT_GENERIC1_3 0x70cc
257#define AFMT_GENERIC1_4 0x70d0
258#define AFMT_GENERIC1_5 0x70d4
259#define AFMT_GENERIC1_6 0x70d8
260#define HDMI_ACR_32_0 0x70dc
261# define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12)
262#define HDMI_ACR_32_1 0x70e0
263# define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0)
264#define HDMI_ACR_44_0 0x70e4
265# define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12)
266#define HDMI_ACR_44_1 0x70e8
267# define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0)
268#define HDMI_ACR_48_0 0x70ec
269# define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12)
270#define HDMI_ACR_48_1 0x70f0
271# define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0)
272#define HDMI_ACR_STATUS_0 0x70f4
273#define HDMI_ACR_STATUS_1 0x70f8
274#define AFMT_AUDIO_INFO0 0x70fc
275# define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
276# define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8)
277# define AFMT_AUDIO_INFO_CT(x) (((x) & 0xf) << 11)
278# define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16)
279# define AFMT_AUDIO_INFO_CXT(x) (((x) & 0x1f) << 24)
280#define AFMT_AUDIO_INFO1 0x7100
281# define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0)
282# define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11)
283# define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15)
284# define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8)
285# define AFMT_AUDIO_INFO_LFEBPL(x) (((x) & 3) << 16)
286#define AFMT_60958_0 0x7104
287# define AFMT_60958_CS_A(x) (((x) & 1) << 0)
288# define AFMT_60958_CS_B(x) (((x) & 1) << 1)
289# define AFMT_60958_CS_C(x) (((x) & 1) << 2)
290# define AFMT_60958_CS_D(x) (((x) & 3) << 3)
291# define AFMT_60958_CS_MODE(x) (((x) & 3) << 6)
292# define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8)
293# define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16)
294# define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20)
295# define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24)
296# define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28)
297#define AFMT_60958_1 0x7108
298# define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0)
299# define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4)
300# define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16)
301# define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18)
302# define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20)
303#define AFMT_AUDIO_CRC_CONTROL 0x710c
304# define AFMT_AUDIO_CRC_EN (1 << 0)
305#define AFMT_RAMP_CONTROL0 0x7110
306# define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0)
307# define AFMT_RAMP_DATA_SIGN (1 << 31)
308#define AFMT_RAMP_CONTROL1 0x7114
309# define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0)
310# define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24)
311#define AFMT_RAMP_CONTROL2 0x7118
312# define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0)
313#define AFMT_RAMP_CONTROL3 0x711c
314# define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0)
315#define AFMT_60958_2 0x7120
316# define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0)
317# define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4)
318# define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8)
319# define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12)
320# define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16)
321# define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20)
322#define AFMT_STATUS 0x7128
323# define AFMT_AUDIO_ENABLE (1 << 4)
324# define AFMT_AUDIO_HBR_ENABLE (1 << 8)
325# define AFMT_AZ_FORMAT_WTRIG (1 << 28)
326# define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29)
327# define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30)
328#define AFMT_AUDIO_PACKET_CONTROL 0x712c
329# define AFMT_AUDIO_SAMPLE_SEND (1 << 0)
330# define AFMT_RESET_FIFO_WHEN_AUDIO_DIS (1 << 11) /* set to 1 */
331# define AFMT_AUDIO_TEST_EN (1 << 12)
332# define AFMT_AUDIO_CHANNEL_SWAP (1 << 24)
333# define AFMT_60958_CS_UPDATE (1 << 26)
334# define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27)
335# define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28)
336# define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29)
337# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)
338#define AFMT_VBI_PACKET_CONTROL 0x7130
339# define AFMT_GENERIC0_UPDATE (1 << 2)
340#define AFMT_INFOFRAME_CONTROL0 0x7134
341# define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - afmt regs */
342# define AFMT_AUDIO_INFO_UPDATE (1 << 7)
343# define AFMT_MPEG_INFO_UPDATE (1 << 10)
344#define AFMT_GENERIC0_7 0x7138
345
346#define GC_USER_SHADER_PIPE_CONFIG 0x8954
347#define INACTIVE_QD_PIPES(x) ((x) << 8)
348#define INACTIVE_QD_PIPES_MASK 0x0000FF00
349#define INACTIVE_SIMDS(x) ((x) << 16)
350#define INACTIVE_SIMDS_MASK 0x00FF0000
351
352#define GRBM_CNTL 0x8000
353#define GRBM_READ_TIMEOUT(x) ((x) << 0)
354#define GRBM_SOFT_RESET 0x8020
355#define SOFT_RESET_CP (1 << 0)
356#define SOFT_RESET_CB (1 << 1)
357#define SOFT_RESET_DB (1 << 3)
358#define SOFT_RESET_PA (1 << 5)
359#define SOFT_RESET_SC (1 << 6)
360#define SOFT_RESET_SPI (1 << 8)
361#define SOFT_RESET_SH (1 << 9)
362#define SOFT_RESET_SX (1 << 10)
363#define SOFT_RESET_TC (1 << 11)
364#define SOFT_RESET_TA (1 << 12)
365#define SOFT_RESET_VC (1 << 13)
366#define SOFT_RESET_VGT (1 << 14)
367
368#define GRBM_STATUS 0x8010
369#define CMDFIFO_AVAIL_MASK 0x0000000F
370#define SRBM_RQ_PENDING (1 << 5)
371#define CF_RQ_PENDING (1 << 7)
372#define PF_RQ_PENDING (1 << 8)
373#define GRBM_EE_BUSY (1 << 10)
374#define SX_CLEAN (1 << 11)
375#define DB_CLEAN (1 << 12)
376#define CB_CLEAN (1 << 13)
377#define TA_BUSY (1 << 14)
378#define VGT_BUSY_NO_DMA (1 << 16)
379#define VGT_BUSY (1 << 17)
380#define SX_BUSY (1 << 20)
381#define SH_BUSY (1 << 21)
382#define SPI_BUSY (1 << 22)
383#define SC_BUSY (1 << 24)
384#define PA_BUSY (1 << 25)
385#define DB_BUSY (1 << 26)
386#define CP_COHERENCY_BUSY (1 << 28)
387#define CP_BUSY (1 << 29)
388#define CB_BUSY (1 << 30)
389#define GUI_ACTIVE (1 << 31)
390#define GRBM_STATUS_SE0 0x8014
391#define GRBM_STATUS_SE1 0x8018
392#define SE_SX_CLEAN (1 << 0)
393#define SE_DB_CLEAN (1 << 1)
394#define SE_CB_CLEAN (1 << 2)
395#define SE_TA_BUSY (1 << 25)
396#define SE_SX_BUSY (1 << 26)
397#define SE_SPI_BUSY (1 << 27)
398#define SE_SH_BUSY (1 << 28)
399#define SE_SC_BUSY (1 << 29)
400#define SE_DB_BUSY (1 << 30)
401#define SE_CB_BUSY (1 << 31)
402/* evergreen */
403#define CG_THERMAL_CTRL 0x72c
404#define TOFFSET_MASK 0x00003FE0
405#define TOFFSET_SHIFT 5
406#define CG_MULT_THERMAL_STATUS 0x740
407#define ASIC_T(x) ((x) << 16)
408#define ASIC_T_MASK 0x07FF0000
409#define ASIC_T_SHIFT 16
410#define CG_TS0_STATUS 0x760
411#define TS0_ADC_DOUT_MASK 0x000003FF
412#define TS0_ADC_DOUT_SHIFT 0
413/* APU */
414#define CG_THERMAL_STATUS 0x678
415
416#define HDP_HOST_PATH_CNTL 0x2C00
417#define HDP_NONSURFACE_BASE 0x2C04
418#define HDP_NONSURFACE_INFO 0x2C08
419#define HDP_NONSURFACE_SIZE 0x2C0C
420#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
421#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
422#define HDP_TILING_CONFIG 0x2F3C
423
424#define MC_SHARED_CHMAP 0x2004
425#define NOOFCHAN_SHIFT 12
426#define NOOFCHAN_MASK 0x00003000
427#define MC_SHARED_CHREMAP 0x2008
428
429#define MC_ARB_RAMCFG 0x2760
430#define NOOFBANK_SHIFT 0
431#define NOOFBANK_MASK 0x00000003
432#define NOOFRANK_SHIFT 2
433#define NOOFRANK_MASK 0x00000004
434#define NOOFROWS_SHIFT 3
435#define NOOFROWS_MASK 0x00000038
436#define NOOFCOLS_SHIFT 6
437#define NOOFCOLS_MASK 0x000000C0
438#define CHANSIZE_SHIFT 8
439#define CHANSIZE_MASK 0x00000100
440#define BURSTLENGTH_SHIFT 9
441#define BURSTLENGTH_MASK 0x00000200
442#define CHANSIZE_OVERRIDE (1 << 11)
443#define FUS_MC_ARB_RAMCFG 0x2768
444#define MC_VM_AGP_TOP 0x2028
445#define MC_VM_AGP_BOT 0x202C
446#define MC_VM_AGP_BASE 0x2030
447#define MC_VM_FB_LOCATION 0x2024
448#define MC_FUS_VM_FB_OFFSET 0x2898
449#define MC_VM_MB_L1_TLB0_CNTL 0x2234
450#define MC_VM_MB_L1_TLB1_CNTL 0x2238
451#define MC_VM_MB_L1_TLB2_CNTL 0x223C
452#define MC_VM_MB_L1_TLB3_CNTL 0x2240
453#define ENABLE_L1_TLB (1 << 0)
454#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
455#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
456#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
457#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
458#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
459#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
460#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
461#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
462#define MC_VM_MD_L1_TLB0_CNTL 0x2654
463#define MC_VM_MD_L1_TLB1_CNTL 0x2658
464#define MC_VM_MD_L1_TLB2_CNTL 0x265C
465#define MC_VM_MD_L1_TLB3_CNTL 0x2698
466
467#define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C
468#define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660
469#define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664
470
471#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
472#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
473#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
474
475#define PA_CL_ENHANCE 0x8A14
476#define CLIP_VTX_REORDER_ENA (1 << 0)
477#define NUM_CLIP_SEQ(x) ((x) << 1)
478#define PA_SC_ENHANCE 0x8BF0
479#define PA_SC_AA_CONFIG 0x28C04
480#define MSAA_NUM_SAMPLES_SHIFT 0
481#define MSAA_NUM_SAMPLES_MASK 0x3
482#define PA_SC_CLIPRECT_RULE 0x2820C
483#define PA_SC_EDGERULE 0x28230
484#define PA_SC_FIFO_SIZE 0x8BCC
485#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
486#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
487#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
488#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
489#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
490#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
491#define PA_SC_LINE_STIPPLE 0x28A0C
492#define PA_SU_LINE_STIPPLE_VALUE 0x8A60
493#define PA_SC_LINE_STIPPLE_STATE 0x8B10
494
495#define SCRATCH_REG0 0x8500
496#define SCRATCH_REG1 0x8504
497#define SCRATCH_REG2 0x8508
498#define SCRATCH_REG3 0x850C
499#define SCRATCH_REG4 0x8510
500#define SCRATCH_REG5 0x8514
501#define SCRATCH_REG6 0x8518
502#define SCRATCH_REG7 0x851C
503#define SCRATCH_UMSK 0x8540
504#define SCRATCH_ADDR 0x8544
505
506#define SMX_SAR_CTL0 0xA008
507#define SMX_DC_CTL0 0xA020
508#define USE_HASH_FUNCTION (1 << 0)
509#define NUMBER_OF_SETS(x) ((x) << 1)
510#define FLUSH_ALL_ON_EVENT (1 << 10)
511#define STALL_ON_EVENT (1 << 11)
512#define SMX_EVENT_CTL 0xA02C
513#define ES_FLUSH_CTL(x) ((x) << 0)
514#define GS_FLUSH_CTL(x) ((x) << 3)
515#define ACK_FLUSH_CTL(x) ((x) << 6)
516#define SYNC_FLUSH_CTL (1 << 8)
517
518#define SPI_CONFIG_CNTL 0x9100
519#define GPR_WRITE_PRIORITY(x) ((x) << 0)
520#define SPI_CONFIG_CNTL_1 0x913C
521#define VTX_DONE_DELAY(x) ((x) << 0)
522#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
523#define SPI_INPUT_Z 0x286D8
524#define SPI_PS_IN_CONTROL_0 0x286CC
525#define NUM_INTERP(x) ((x)<<0)
526#define POSITION_ENA (1<<8)
527#define POSITION_CENTROID (1<<9)
528#define POSITION_ADDR(x) ((x)<<10)
529#define PARAM_GEN(x) ((x)<<15)
530#define PARAM_GEN_ADDR(x) ((x)<<19)
531#define BARYC_SAMPLE_CNTL(x) ((x)<<26)
532#define PERSP_GRADIENT_ENA (1<<28)
533#define LINEAR_GRADIENT_ENA (1<<29)
534#define POSITION_SAMPLE (1<<30)
535#define BARYC_AT_SAMPLE_ENA (1<<31)
536
537#define SQ_CONFIG 0x8C00
538#define VC_ENABLE (1 << 0)
539#define EXPORT_SRC_C (1 << 1)
540#define CS_PRIO(x) ((x) << 18)
541#define LS_PRIO(x) ((x) << 20)
542#define HS_PRIO(x) ((x) << 22)
543#define PS_PRIO(x) ((x) << 24)
544#define VS_PRIO(x) ((x) << 26)
545#define GS_PRIO(x) ((x) << 28)
546#define ES_PRIO(x) ((x) << 30)
547#define SQ_GPR_RESOURCE_MGMT_1 0x8C04
548#define NUM_PS_GPRS(x) ((x) << 0)
549#define NUM_VS_GPRS(x) ((x) << 16)
550#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
551#define SQ_GPR_RESOURCE_MGMT_2 0x8C08
552#define NUM_GS_GPRS(x) ((x) << 0)
553#define NUM_ES_GPRS(x) ((x) << 16)
554#define SQ_GPR_RESOURCE_MGMT_3 0x8C0C
555#define NUM_HS_GPRS(x) ((x) << 0)
556#define NUM_LS_GPRS(x) ((x) << 16)
557#define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 0x8C10
558#define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 0x8C14
559#define SQ_THREAD_RESOURCE_MGMT 0x8C18
560#define NUM_PS_THREADS(x) ((x) << 0)
561#define NUM_VS_THREADS(x) ((x) << 8)
562#define NUM_GS_THREADS(x) ((x) << 16)
563#define NUM_ES_THREADS(x) ((x) << 24)
564#define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C
565#define NUM_HS_THREADS(x) ((x) << 0)
566#define NUM_LS_THREADS(x) ((x) << 8)
567#define SQ_STACK_RESOURCE_MGMT_1 0x8C20
568#define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
569#define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
570#define SQ_STACK_RESOURCE_MGMT_2 0x8C24
571#define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
572#define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
573#define SQ_STACK_RESOURCE_MGMT_3 0x8C28
574#define NUM_HS_STACK_ENTRIES(x) ((x) << 0)
575#define NUM_LS_STACK_ENTRIES(x) ((x) << 16)
576#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C
577#define SQ_DYN_GPR_SIMD_LOCK_EN 0x8D94
578#define SQ_STATIC_THREAD_MGMT_1 0x8E20
579#define SQ_STATIC_THREAD_MGMT_2 0x8E24
580#define SQ_STATIC_THREAD_MGMT_3 0x8E28
581#define SQ_LDS_RESOURCE_MGMT 0x8E2C
582
583#define SQ_MS_FIFO_SIZES 0x8CF0
584#define CACHE_FIFO_SIZE(x) ((x) << 0)
585#define FETCH_FIFO_HIWATER(x) ((x) << 8)
586#define DONE_FIFO_HIWATER(x) ((x) << 16)
587#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
588
589#define SX_DEBUG_1 0x9058
590#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
591#define SX_EXPORT_BUFFER_SIZES 0x900C
592#define COLOR_BUFFER_SIZE(x) ((x) << 0)
593#define POSITION_BUFFER_SIZE(x) ((x) << 8)
594#define SMX_BUFFER_SIZE(x) ((x) << 16)
595#define SX_MEMORY_EXPORT_BASE 0x9010
596#define SX_MISC 0x28350
597
598#define CB_PERF_CTR0_SEL_0 0x9A20
599#define CB_PERF_CTR0_SEL_1 0x9A24
600#define CB_PERF_CTR1_SEL_0 0x9A28
601#define CB_PERF_CTR1_SEL_1 0x9A2C
602#define CB_PERF_CTR2_SEL_0 0x9A30
603#define CB_PERF_CTR2_SEL_1 0x9A34
604#define CB_PERF_CTR3_SEL_0 0x9A38
605#define CB_PERF_CTR3_SEL_1 0x9A3C
606
607#define TA_CNTL_AUX 0x9508
608#define DISABLE_CUBE_WRAP (1 << 0)
609#define DISABLE_CUBE_ANISO (1 << 1)
610#define SYNC_GRADIENT (1 << 24)
611#define SYNC_WALKER (1 << 25)
612#define SYNC_ALIGNER (1 << 26)
613
614#define TCP_CHAN_STEER_LO 0x960c
615#define TCP_CHAN_STEER_HI 0x9610
616
617#define VGT_CACHE_INVALIDATION 0x88C4
618#define CACHE_INVALIDATION(x) ((x) << 0)
619#define VC_ONLY 0
620#define TC_ONLY 1
621#define VC_AND_TC 2
622#define AUTO_INVLD_EN(x) ((x) << 6)
623#define NO_AUTO 0
624#define ES_AUTO 1
625#define GS_AUTO 2
626#define ES_AND_GS_AUTO 3
627#define VGT_GS_VERTEX_REUSE 0x88D4
628#define VGT_NUM_INSTANCES 0x8974
629#define VGT_OUT_DEALLOC_CNTL 0x28C5C
630#define DEALLOC_DIST_MASK 0x0000007F
631#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
632#define VTX_REUSE_DEPTH_MASK 0x000000FF
633
634#define VM_CONTEXT0_CNTL 0x1410
635#define ENABLE_CONTEXT (1 << 0)
636#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
637#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
638#define VM_CONTEXT1_CNTL 0x1414
639#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
640#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
641#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
642#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
643#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
644#define REQUEST_TYPE(x) (((x) & 0xf) << 0)
645#define RESPONSE_TYPE_MASK 0x000000F0
646#define RESPONSE_TYPE_SHIFT 4
647#define VM_L2_CNTL 0x1400
648#define ENABLE_L2_CACHE (1 << 0)
649#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
650#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
651#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
652#define VM_L2_CNTL2 0x1404
653#define INVALIDATE_ALL_L1_TLBS (1 << 0)
654#define INVALIDATE_L2_CACHE (1 << 1)
655#define VM_L2_CNTL3 0x1408
656#define BANK_SELECT(x) ((x) << 0)
657#define CACHE_UPDATE_MODE(x) ((x) << 6)
658#define VM_L2_STATUS 0x140C
659#define L2_BUSY (1 << 0)
660
661#define WAIT_UNTIL 0x8040
662
663#define SRBM_STATUS 0x0E50
664#define SRBM_SOFT_RESET 0x0E60
665#define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6
666#define SOFT_RESET_BIF (1 << 1)
667#define SOFT_RESET_CG (1 << 2)
668#define SOFT_RESET_DC (1 << 5)
669#define SOFT_RESET_GRBM (1 << 8)
670#define SOFT_RESET_HDP (1 << 9)
671#define SOFT_RESET_IH (1 << 10)
672#define SOFT_RESET_MC (1 << 11)
673#define SOFT_RESET_RLC (1 << 13)
674#define SOFT_RESET_ROM (1 << 14)
675#define SOFT_RESET_SEM (1 << 15)
676#define SOFT_RESET_VMC (1 << 17)
677#define SOFT_RESET_TST (1 << 21)
678#define SOFT_RESET_REGBB (1 << 22)
679#define SOFT_RESET_ORB (1 << 23)
680
681/* display watermarks */
682#define DC_LB_MEMORY_SPLIT 0x6b0c
683#define PRIORITY_A_CNT 0x6b18
684#define PRIORITY_MARK_MASK 0x7fff
685#define PRIORITY_OFF (1 << 16)
686#define PRIORITY_ALWAYS_ON (1 << 20)
687#define PRIORITY_B_CNT 0x6b1c
688#define PIPE0_ARBITRATION_CONTROL3 0x0bf0
689# define LATENCY_WATERMARK_MASK(x) ((x) << 16)
690#define PIPE0_LATENCY_CONTROL 0x0bf4
691# define LATENCY_LOW_WATERMARK(x) ((x) << 0)
692# define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
693
694#define IH_RB_CNTL 0x3e00
695# define IH_RB_ENABLE (1 << 0)
696# define IH_IB_SIZE(x) ((x) << 1) /* log2 */
697# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
698# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
699# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
700# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
701# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
702#define IH_RB_BASE 0x3e04
703#define IH_RB_RPTR 0x3e08
704#define IH_RB_WPTR 0x3e0c
705# define RB_OVERFLOW (1 << 0)
706# define WPTR_OFFSET_MASK 0x3fffc
707#define IH_RB_WPTR_ADDR_HI 0x3e10
708#define IH_RB_WPTR_ADDR_LO 0x3e14
709#define IH_CNTL 0x3e18
710# define ENABLE_INTR (1 << 0)
711# define IH_MC_SWAP(x) ((x) << 1)
712# define IH_MC_SWAP_NONE 0
713# define IH_MC_SWAP_16BIT 1
714# define IH_MC_SWAP_32BIT 2
715# define IH_MC_SWAP_64BIT 3
716# define RPTR_REARM (1 << 4)
717# define MC_WRREQ_CREDIT(x) ((x) << 15)
718# define MC_WR_CLEAN_CNT(x) ((x) << 20)
719
720#define CP_INT_CNTL 0xc124
721# define CNTX_BUSY_INT_ENABLE (1 << 19)
722# define CNTX_EMPTY_INT_ENABLE (1 << 20)
723# define SCRATCH_INT_ENABLE (1 << 25)
724# define TIME_STAMP_INT_ENABLE (1 << 26)
725# define IB2_INT_ENABLE (1 << 29)
726# define IB1_INT_ENABLE (1 << 30)
727# define RB_INT_ENABLE (1 << 31)
728#define CP_INT_STATUS 0xc128
729# define SCRATCH_INT_STAT (1 << 25)
730# define TIME_STAMP_INT_STAT (1 << 26)
731# define IB2_INT_STAT (1 << 29)
732# define IB1_INT_STAT (1 << 30)
733# define RB_INT_STAT (1 << 31)
734
735#define GRBM_INT_CNTL 0x8060
736# define RDERR_INT_ENABLE (1 << 0)
737# define GUI_IDLE_INT_ENABLE (1 << 19)
738
739/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
740#define CRTC_STATUS_FRAME_COUNT 0x6e98
741
742/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
743#define VLINE_STATUS 0x6bb8
744# define VLINE_OCCURRED (1 << 0)
745# define VLINE_ACK (1 << 4)
746# define VLINE_STAT (1 << 12)
747# define VLINE_INTERRUPT (1 << 16)
748# define VLINE_INTERRUPT_TYPE (1 << 17)
749/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
750#define VBLANK_STATUS 0x6bbc
751# define VBLANK_OCCURRED (1 << 0)
752# define VBLANK_ACK (1 << 4)
753# define VBLANK_STAT (1 << 12)
754# define VBLANK_INTERRUPT (1 << 16)
755# define VBLANK_INTERRUPT_TYPE (1 << 17)
756
757/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
758#define INT_MASK 0x6b40
759# define VBLANK_INT_MASK (1 << 0)
760# define VLINE_INT_MASK (1 << 4)
761
762#define DISP_INTERRUPT_STATUS 0x60f4
763# define LB_D1_VLINE_INTERRUPT (1 << 2)
764# define LB_D1_VBLANK_INTERRUPT (1 << 3)
765# define DC_HPD1_INTERRUPT (1 << 17)
766# define DC_HPD1_RX_INTERRUPT (1 << 18)
767# define DACA_AUTODETECT_INTERRUPT (1 << 22)
768# define DACB_AUTODETECT_INTERRUPT (1 << 23)
769# define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
770# define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
771#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
772# define LB_D2_VLINE_INTERRUPT (1 << 2)
773# define LB_D2_VBLANK_INTERRUPT (1 << 3)
774# define DC_HPD2_INTERRUPT (1 << 17)
775# define DC_HPD2_RX_INTERRUPT (1 << 18)
776# define DISP_TIMER_INTERRUPT (1 << 24)
777#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
778# define LB_D3_VLINE_INTERRUPT (1 << 2)
779# define LB_D3_VBLANK_INTERRUPT (1 << 3)
780# define DC_HPD3_INTERRUPT (1 << 17)
781# define DC_HPD3_RX_INTERRUPT (1 << 18)
782#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
783# define LB_D4_VLINE_INTERRUPT (1 << 2)
784# define LB_D4_VBLANK_INTERRUPT (1 << 3)
785# define DC_HPD4_INTERRUPT (1 << 17)
786# define DC_HPD4_RX_INTERRUPT (1 << 18)
787#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
788# define LB_D5_VLINE_INTERRUPT (1 << 2)
789# define LB_D5_VBLANK_INTERRUPT (1 << 3)
790# define DC_HPD5_INTERRUPT (1 << 17)
791# define DC_HPD5_RX_INTERRUPT (1 << 18)
792#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
793# define LB_D6_VLINE_INTERRUPT (1 << 2)
794# define LB_D6_VBLANK_INTERRUPT (1 << 3)
795# define DC_HPD6_INTERRUPT (1 << 17)
796# define DC_HPD6_RX_INTERRUPT (1 << 18)
797
798/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
799#define GRPH_INT_STATUS 0x6858
800# define GRPH_PFLIP_INT_OCCURRED (1 << 0)
801# define GRPH_PFLIP_INT_CLEAR (1 << 8)
802/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
803#define GRPH_INT_CONTROL 0x685c
804# define GRPH_PFLIP_INT_MASK (1 << 0)
805# define GRPH_PFLIP_INT_TYPE (1 << 8)
806
807#define DACA_AUTODETECT_INT_CONTROL 0x66c8
808#define DACB_AUTODETECT_INT_CONTROL 0x67c8
809
810#define DC_HPD1_INT_STATUS 0x601c
811#define DC_HPD2_INT_STATUS 0x6028
812#define DC_HPD3_INT_STATUS 0x6034
813#define DC_HPD4_INT_STATUS 0x6040
814#define DC_HPD5_INT_STATUS 0x604c
815#define DC_HPD6_INT_STATUS 0x6058
816# define DC_HPDx_INT_STATUS (1 << 0)
817# define DC_HPDx_SENSE (1 << 1)
818# define DC_HPDx_RX_INT_STATUS (1 << 8)
819
820#define DC_HPD1_INT_CONTROL 0x6020
821#define DC_HPD2_INT_CONTROL 0x602c
822#define DC_HPD3_INT_CONTROL 0x6038
823#define DC_HPD4_INT_CONTROL 0x6044
824#define DC_HPD5_INT_CONTROL 0x6050
825#define DC_HPD6_INT_CONTROL 0x605c
826# define DC_HPDx_INT_ACK (1 << 0)
827# define DC_HPDx_INT_POLARITY (1 << 8)
828# define DC_HPDx_INT_EN (1 << 16)
829# define DC_HPDx_RX_INT_ACK (1 << 20)
830# define DC_HPDx_RX_INT_EN (1 << 24)
831
832#define DC_HPD1_CONTROL 0x6024
833#define DC_HPD2_CONTROL 0x6030
834#define DC_HPD3_CONTROL 0x603c
835#define DC_HPD4_CONTROL 0x6048
836#define DC_HPD5_CONTROL 0x6054
837#define DC_HPD6_CONTROL 0x6060
838# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
839# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
840# define DC_HPDx_EN (1 << 28)
841
842/* PCIE link stuff */
843#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
844#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
845# define LC_LINK_WIDTH_SHIFT 0
846# define LC_LINK_WIDTH_MASK 0x7
847# define LC_LINK_WIDTH_X0 0
848# define LC_LINK_WIDTH_X1 1
849# define LC_LINK_WIDTH_X2 2
850# define LC_LINK_WIDTH_X4 3
851# define LC_LINK_WIDTH_X8 4
852# define LC_LINK_WIDTH_X16 6
853# define LC_LINK_WIDTH_RD_SHIFT 4
854# define LC_LINK_WIDTH_RD_MASK 0x70
855# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
856# define LC_RECONFIG_NOW (1 << 8)
857# define LC_RENEGOTIATION_SUPPORT (1 << 9)
858# define LC_RENEGOTIATE_EN (1 << 10)
859# define LC_SHORT_RECONFIG_EN (1 << 11)
860# define LC_UPCONFIGURE_SUPPORT (1 << 12)
861# define LC_UPCONFIGURE_DIS (1 << 13)
862#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
863# define LC_GEN2_EN_STRAP (1 << 0)
864# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
865# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
866# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
867# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
868# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
869# define LC_CURRENT_DATA_RATE (1 << 11)
870# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
871# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
872# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
873# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
874#define MM_CFGREGS_CNTL 0x544c
875# define MM_WR_TO_CFG_EN (1 << 3)
876#define LINK_CNTL2 0x88 /* F0 */
877# define TARGET_LINK_SPEED_MASK (0xf << 0)
878# define SELECTABLE_DEEMPHASIS (1 << 6)
879
880/*
881 * PM4
882 */
883#define PACKET_TYPE0 0
884#define PACKET_TYPE1 1
885#define PACKET_TYPE2 2
886#define PACKET_TYPE3 3
887
888#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
889#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
890#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
891#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
892#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
893 (((reg) >> 2) & 0xFFFF) | \
894 ((n) & 0x3FFF) << 16)
895#define CP_PACKET2 0x80000000
896#define PACKET2_PAD_SHIFT 0
897#define PACKET2_PAD_MASK (0x3fffffff << 0)
898
899#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
900
901#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
902 (((op) & 0xFF) << 8) | \
903 ((n) & 0x3FFF) << 16)
904
905/* Packet 3 types */
906#define PACKET3_NOP 0x10
907#define PACKET3_SET_BASE 0x11
908#define PACKET3_CLEAR_STATE 0x12
909#define PACKET3_INDEX_BUFFER_SIZE 0x13
910#define PACKET3_DISPATCH_DIRECT 0x15
911#define PACKET3_DISPATCH_INDIRECT 0x16
912#define PACKET3_INDIRECT_BUFFER_END 0x17
913#define PACKET3_MODE_CONTROL 0x18
914#define PACKET3_SET_PREDICATION 0x20
915#define PACKET3_REG_RMW 0x21
916#define PACKET3_COND_EXEC 0x22
917#define PACKET3_PRED_EXEC 0x23
918#define PACKET3_DRAW_INDIRECT 0x24
919#define PACKET3_DRAW_INDEX_INDIRECT 0x25
920#define PACKET3_INDEX_BASE 0x26
921#define PACKET3_DRAW_INDEX_2 0x27
922#define PACKET3_CONTEXT_CONTROL 0x28
923#define PACKET3_DRAW_INDEX_OFFSET 0x29
924#define PACKET3_INDEX_TYPE 0x2A
925#define PACKET3_DRAW_INDEX 0x2B
926#define PACKET3_DRAW_INDEX_AUTO 0x2D
927#define PACKET3_DRAW_INDEX_IMMD 0x2E
928#define PACKET3_NUM_INSTANCES 0x2F
929#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
930#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
931#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
932#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
933#define PACKET3_MEM_SEMAPHORE 0x39
934#define PACKET3_MPEG_INDEX 0x3A
935#define PACKET3_COPY_DW 0x3B
936#define PACKET3_WAIT_REG_MEM 0x3C
937#define PACKET3_MEM_WRITE 0x3D
938#define PACKET3_INDIRECT_BUFFER 0x32
939#define PACKET3_SURFACE_SYNC 0x43
940# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
941# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
942# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
943# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
944# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
945# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
946# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
947# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
948# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
949# define PACKET3_CB8_DEST_BASE_ENA (1 << 15)
950# define PACKET3_CB9_DEST_BASE_ENA (1 << 16)
951# define PACKET3_CB10_DEST_BASE_ENA (1 << 17)
952# define PACKET3_CB11_DEST_BASE_ENA (1 << 18)
953# define PACKET3_FULL_CACHE_ENA (1 << 20)
954# define PACKET3_TC_ACTION_ENA (1 << 23)
955# define PACKET3_VC_ACTION_ENA (1 << 24)
956# define PACKET3_CB_ACTION_ENA (1 << 25)
957# define PACKET3_DB_ACTION_ENA (1 << 26)
958# define PACKET3_SH_ACTION_ENA (1 << 27)
959# define PACKET3_SX_ACTION_ENA (1 << 28)
960#define PACKET3_ME_INITIALIZE 0x44
961#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
962#define PACKET3_COND_WRITE 0x45
963#define PACKET3_EVENT_WRITE 0x46
964#define PACKET3_EVENT_WRITE_EOP 0x47
965#define PACKET3_EVENT_WRITE_EOS 0x48
966#define PACKET3_PREAMBLE_CNTL 0x4A
967# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
968# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
969#define PACKET3_RB_OFFSET 0x4B
970#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C
971#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D
972#define PACKET3_ALU_PS_CONST_UPDATE 0x4E
973#define PACKET3_ALU_VS_CONST_UPDATE 0x4F
974#define PACKET3_ONE_REG_WRITE 0x57
975#define PACKET3_SET_CONFIG_REG 0x68
976#define PACKET3_SET_CONFIG_REG_START 0x00008000
977#define PACKET3_SET_CONFIG_REG_END 0x0000ac00
978#define PACKET3_SET_CONTEXT_REG 0x69
979#define PACKET3_SET_CONTEXT_REG_START 0x00028000
980#define PACKET3_SET_CONTEXT_REG_END 0x00029000
981#define PACKET3_SET_ALU_CONST 0x6A
982/* alu const buffers only; no reg file */
983#define PACKET3_SET_BOOL_CONST 0x6B
984#define PACKET3_SET_BOOL_CONST_START 0x0003a500
985#define PACKET3_SET_BOOL_CONST_END 0x0003a518
986#define PACKET3_SET_LOOP_CONST 0x6C
987#define PACKET3_SET_LOOP_CONST_START 0x0003a200
988#define PACKET3_SET_LOOP_CONST_END 0x0003a500
989#define PACKET3_SET_RESOURCE 0x6D
990#define PACKET3_SET_RESOURCE_START 0x00030000
991#define PACKET3_SET_RESOURCE_END 0x00038000
992#define PACKET3_SET_SAMPLER 0x6E
993#define PACKET3_SET_SAMPLER_START 0x0003c000
994#define PACKET3_SET_SAMPLER_END 0x0003c600
995#define PACKET3_SET_CTL_CONST 0x6F
996#define PACKET3_SET_CTL_CONST_START 0x0003cff0
997#define PACKET3_SET_CTL_CONST_END 0x0003ff0c
998#define PACKET3_SET_RESOURCE_OFFSET 0x70
999#define PACKET3_SET_ALU_CONST_VS 0x71
1000#define PACKET3_SET_ALU_CONST_DI 0x72
1001#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
1002#define PACKET3_SET_RESOURCE_INDIRECT 0x74
1003#define PACKET3_SET_APPEND_CNT 0x75
1004
1005#define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c
1006#define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30)
1007#define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3)
1008#define SQ_TEX_VTX_INVALID_TEXTURE 0x0
1009#define SQ_TEX_VTX_INVALID_BUFFER 0x1
1010#define SQ_TEX_VTX_VALID_TEXTURE 0x2
1011#define SQ_TEX_VTX_VALID_BUFFER 0x3
1012
1013#define VGT_VTX_VECT_EJECT_REG 0x88b0
1014
1015#define SQ_CONST_MEM_BASE 0x8df8
1016
1017#define SQ_ESGS_RING_BASE 0x8c40
1018#define SQ_ESGS_RING_SIZE 0x8c44
1019#define SQ_GSVS_RING_BASE 0x8c48
1020#define SQ_GSVS_RING_SIZE 0x8c4c
1021#define SQ_ESTMP_RING_BASE 0x8c50
1022#define SQ_ESTMP_RING_SIZE 0x8c54
1023#define SQ_GSTMP_RING_BASE 0x8c58
1024#define SQ_GSTMP_RING_SIZE 0x8c5c
1025#define SQ_VSTMP_RING_BASE 0x8c60
1026#define SQ_VSTMP_RING_SIZE 0x8c64
1027#define SQ_PSTMP_RING_BASE 0x8c68
1028#define SQ_PSTMP_RING_SIZE 0x8c6c
1029#define SQ_LSTMP_RING_BASE 0x8e10
1030#define SQ_LSTMP_RING_SIZE 0x8e14
1031#define SQ_HSTMP_RING_BASE 0x8e18
1032#define SQ_HSTMP_RING_SIZE 0x8e1c
1033#define VGT_TF_RING_SIZE 0x8988
1034
1035#define SQ_ESGS_RING_ITEMSIZE 0x28900
1036#define SQ_GSVS_RING_ITEMSIZE 0x28904
1037#define SQ_ESTMP_RING_ITEMSIZE 0x28908
1038#define SQ_GSTMP_RING_ITEMSIZE 0x2890c
1039#define SQ_VSTMP_RING_ITEMSIZE 0x28910
1040#define SQ_PSTMP_RING_ITEMSIZE 0x28914
1041#define SQ_LSTMP_RING_ITEMSIZE 0x28830
1042#define SQ_HSTMP_RING_ITEMSIZE 0x28834
1043
1044#define SQ_GS_VERT_ITEMSIZE 0x2891c
1045#define SQ_GS_VERT_ITEMSIZE_1 0x28920
1046#define SQ_GS_VERT_ITEMSIZE_2 0x28924
1047#define SQ_GS_VERT_ITEMSIZE_3 0x28928
1048#define SQ_GSVS_RING_OFFSET_1 0x2892c
1049#define SQ_GSVS_RING_OFFSET_2 0x28930
1050#define SQ_GSVS_RING_OFFSET_3 0x28934
1051
1052#define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140
1053#define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80
1054
1055#define SQ_ALU_CONST_CACHE_PS_0 0x28940
1056#define SQ_ALU_CONST_CACHE_PS_1 0x28944
1057#define SQ_ALU_CONST_CACHE_PS_2 0x28948
1058#define SQ_ALU_CONST_CACHE_PS_3 0x2894c
1059#define SQ_ALU_CONST_CACHE_PS_4 0x28950
1060#define SQ_ALU_CONST_CACHE_PS_5 0x28954
1061#define SQ_ALU_CONST_CACHE_PS_6 0x28958
1062#define SQ_ALU_CONST_CACHE_PS_7 0x2895c
1063#define SQ_ALU_CONST_CACHE_PS_8 0x28960
1064#define SQ_ALU_CONST_CACHE_PS_9 0x28964
1065#define SQ_ALU_CONST_CACHE_PS_10 0x28968
1066#define SQ_ALU_CONST_CACHE_PS_11 0x2896c
1067#define SQ_ALU_CONST_CACHE_PS_12 0x28970
1068#define SQ_ALU_CONST_CACHE_PS_13 0x28974
1069#define SQ_ALU_CONST_CACHE_PS_14 0x28978
1070#define SQ_ALU_CONST_CACHE_PS_15 0x2897c
1071#define SQ_ALU_CONST_CACHE_VS_0 0x28980
1072#define SQ_ALU_CONST_CACHE_VS_1 0x28984
1073#define SQ_ALU_CONST_CACHE_VS_2 0x28988
1074#define SQ_ALU_CONST_CACHE_VS_3 0x2898c
1075#define SQ_ALU_CONST_CACHE_VS_4 0x28990
1076#define SQ_ALU_CONST_CACHE_VS_5 0x28994
1077#define SQ_ALU_CONST_CACHE_VS_6 0x28998
1078#define SQ_ALU_CONST_CACHE_VS_7 0x2899c
1079#define SQ_ALU_CONST_CACHE_VS_8 0x289a0
1080#define SQ_ALU_CONST_CACHE_VS_9 0x289a4
1081#define SQ_ALU_CONST_CACHE_VS_10 0x289a8
1082#define SQ_ALU_CONST_CACHE_VS_11 0x289ac
1083#define SQ_ALU_CONST_CACHE_VS_12 0x289b0
1084#define SQ_ALU_CONST_CACHE_VS_13 0x289b4
1085#define SQ_ALU_CONST_CACHE_VS_14 0x289b8
1086#define SQ_ALU_CONST_CACHE_VS_15 0x289bc
1087#define SQ_ALU_CONST_CACHE_GS_0 0x289c0
1088#define SQ_ALU_CONST_CACHE_GS_1 0x289c4
1089#define SQ_ALU_CONST_CACHE_GS_2 0x289c8
1090#define SQ_ALU_CONST_CACHE_GS_3 0x289cc
1091#define SQ_ALU_CONST_CACHE_GS_4 0x289d0
1092#define SQ_ALU_CONST_CACHE_GS_5 0x289d4
1093#define SQ_ALU_CONST_CACHE_GS_6 0x289d8
1094#define SQ_ALU_CONST_CACHE_GS_7 0x289dc
1095#define SQ_ALU_CONST_CACHE_GS_8 0x289e0
1096#define SQ_ALU_CONST_CACHE_GS_9 0x289e4
1097#define SQ_ALU_CONST_CACHE_GS_10 0x289e8
1098#define SQ_ALU_CONST_CACHE_GS_11 0x289ec
1099#define SQ_ALU_CONST_CACHE_GS_12 0x289f0
1100#define SQ_ALU_CONST_CACHE_GS_13 0x289f4
1101#define SQ_ALU_CONST_CACHE_GS_14 0x289f8
1102#define SQ_ALU_CONST_CACHE_GS_15 0x289fc
1103#define SQ_ALU_CONST_CACHE_HS_0 0x28f00
1104#define SQ_ALU_CONST_CACHE_HS_1 0x28f04
1105#define SQ_ALU_CONST_CACHE_HS_2 0x28f08
1106#define SQ_ALU_CONST_CACHE_HS_3 0x28f0c
1107#define SQ_ALU_CONST_CACHE_HS_4 0x28f10
1108#define SQ_ALU_CONST_CACHE_HS_5 0x28f14
1109#define SQ_ALU_CONST_CACHE_HS_6 0x28f18
1110#define SQ_ALU_CONST_CACHE_HS_7 0x28f1c
1111#define SQ_ALU_CONST_CACHE_HS_8 0x28f20
1112#define SQ_ALU_CONST_CACHE_HS_9 0x28f24
1113#define SQ_ALU_CONST_CACHE_HS_10 0x28f28
1114#define SQ_ALU_CONST_CACHE_HS_11 0x28f2c
1115#define SQ_ALU_CONST_CACHE_HS_12 0x28f30
1116#define SQ_ALU_CONST_CACHE_HS_13 0x28f34
1117#define SQ_ALU_CONST_CACHE_HS_14 0x28f38
1118#define SQ_ALU_CONST_CACHE_HS_15 0x28f3c
1119#define SQ_ALU_CONST_CACHE_LS_0 0x28f40
1120#define SQ_ALU_CONST_CACHE_LS_1 0x28f44
1121#define SQ_ALU_CONST_CACHE_LS_2 0x28f48
1122#define SQ_ALU_CONST_CACHE_LS_3 0x28f4c
1123#define SQ_ALU_CONST_CACHE_LS_4 0x28f50
1124#define SQ_ALU_CONST_CACHE_LS_5 0x28f54
1125#define SQ_ALU_CONST_CACHE_LS_6 0x28f58
1126#define SQ_ALU_CONST_CACHE_LS_7 0x28f5c
1127#define SQ_ALU_CONST_CACHE_LS_8 0x28f60
1128#define SQ_ALU_CONST_CACHE_LS_9 0x28f64
1129#define SQ_ALU_CONST_CACHE_LS_10 0x28f68
1130#define SQ_ALU_CONST_CACHE_LS_11 0x28f6c
1131#define SQ_ALU_CONST_CACHE_LS_12 0x28f70
1132#define SQ_ALU_CONST_CACHE_LS_13 0x28f74
1133#define SQ_ALU_CONST_CACHE_LS_14 0x28f78
1134#define SQ_ALU_CONST_CACHE_LS_15 0x28f7c
1135
1136#define PA_SC_SCREEN_SCISSOR_TL 0x28030
1137#define PA_SC_GENERIC_SCISSOR_TL 0x28240
1138#define PA_SC_WINDOW_SCISSOR_TL 0x28204
1139
1140#define VGT_PRIMITIVE_TYPE 0x8958
1141#define VGT_INDEX_TYPE 0x895C
1142
1143#define VGT_NUM_INDICES 0x8970
1144
1145#define VGT_COMPUTE_DIM_X 0x8990
1146#define VGT_COMPUTE_DIM_Y 0x8994
1147#define VGT_COMPUTE_DIM_Z 0x8998
1148#define VGT_COMPUTE_START_X 0x899C
1149#define VGT_COMPUTE_START_Y 0x89A0
1150#define VGT_COMPUTE_START_Z 0x89A4
1151#define VGT_COMPUTE_INDEX 0x89A8
1152#define VGT_COMPUTE_THREAD_GROUP_SIZE 0x89AC
1153#define VGT_HS_OFFCHIP_PARAM 0x89B0
1154
1155#define DB_DEBUG 0x9830
1156#define DB_DEBUG2 0x9834
1157#define DB_DEBUG3 0x9838
1158#define DB_DEBUG4 0x983C
1159#define DB_WATERMARKS 0x9854
1160#define DB_DEPTH_CONTROL 0x28800
1161#define R_028800_DB_DEPTH_CONTROL 0x028800
1162#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)
1163#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)
1164#define C_028800_STENCIL_ENABLE 0xFFFFFFFE
1165#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1)
1166#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1)
1167#define C_028800_Z_ENABLE 0xFFFFFFFD
1168#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2)
1169#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1)
1170#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB
1171#define S_028800_ZFUNC(x) (((x) & 0x7) << 4)
1172#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7)
1173#define C_028800_ZFUNC 0xFFFFFF8F
1174#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7)
1175#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1)
1176#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F
1177#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8)
1178#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7)
1179#define C_028800_STENCILFUNC 0xFFFFF8FF
1180#define V_028800_STENCILFUNC_NEVER 0x00000000
1181#define V_028800_STENCILFUNC_LESS 0x00000001
1182#define V_028800_STENCILFUNC_EQUAL 0x00000002
1183#define V_028800_STENCILFUNC_LEQUAL 0x00000003
1184#define V_028800_STENCILFUNC_GREATER 0x00000004
1185#define V_028800_STENCILFUNC_NOTEQUAL 0x00000005
1186#define V_028800_STENCILFUNC_GEQUAL 0x00000006
1187#define V_028800_STENCILFUNC_ALWAYS 0x00000007
1188#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11)
1189#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7)
1190#define C_028800_STENCILFAIL 0xFFFFC7FF
1191#define V_028800_STENCIL_KEEP 0x00000000
1192#define V_028800_STENCIL_ZERO 0x00000001
1193#define V_028800_STENCIL_REPLACE 0x00000002
1194#define V_028800_STENCIL_INCR 0x00000003
1195#define V_028800_STENCIL_DECR 0x00000004
1196#define V_028800_STENCIL_INVERT 0x00000005
1197#define V_028800_STENCIL_INCR_WRAP 0x00000006
1198#define V_028800_STENCIL_DECR_WRAP 0x00000007
1199#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14)
1200#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7)
1201#define C_028800_STENCILZPASS 0xFFFE3FFF
1202#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17)
1203#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7)
1204#define C_028800_STENCILZFAIL 0xFFF1FFFF
1205#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20)
1206#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7)
1207#define C_028800_STENCILFUNC_BF 0xFF8FFFFF
1208#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23)
1209#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7)
1210#define C_028800_STENCILFAIL_BF 0xFC7FFFFF
1211#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26)
1212#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7)
1213#define C_028800_STENCILZPASS_BF 0xE3FFFFFF
1214#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29)
1215#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7)
1216#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF
1217#define DB_DEPTH_VIEW 0x28008
1218#define R_028008_DB_DEPTH_VIEW 0x00028008
1219#define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0)
1220#define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF)
1221#define C_028008_SLICE_START 0xFFFFF800
1222#define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13)
1223#define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
1224#define C_028008_SLICE_MAX 0xFF001FFF
1225#define DB_HTILE_DATA_BASE 0x28014
1226#define DB_HTILE_SURFACE 0x28abc
1227#define S_028ABC_HTILE_WIDTH(x) (((x) & 0x1) << 0)
1228#define G_028ABC_HTILE_WIDTH(x) (((x) >> 0) & 0x1)
1229#define C_028ABC_HTILE_WIDTH 0xFFFFFFFE
1230#define S_028ABC_HTILE_HEIGHT(x) (((x) & 0x1) << 1)
1231#define G_028ABC_HTILE_HEIGHT(x) (((x) >> 1) & 0x1)
1232#define C_028ABC_HTILE_HEIGHT 0xFFFFFFFD
1233#define G_028ABC_LINEAR(x) (((x) >> 2) & 0x1)
1234#define DB_Z_INFO 0x28040
1235# define Z_ARRAY_MODE(x) ((x) << 4)
1236# define DB_TILE_SPLIT(x) (((x) & 0x7) << 8)
1237# define DB_NUM_BANKS(x) (((x) & 0x3) << 12)
1238# define DB_BANK_WIDTH(x) (((x) & 0x3) << 16)
1239# define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20)
1240# define DB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24)
1241#define R_028040_DB_Z_INFO 0x028040
1242#define S_028040_FORMAT(x) (((x) & 0x3) << 0)
1243#define G_028040_FORMAT(x) (((x) >> 0) & 0x3)
1244#define C_028040_FORMAT 0xFFFFFFFC
1245#define V_028040_Z_INVALID 0x00000000
1246#define V_028040_Z_16 0x00000001
1247#define V_028040_Z_24 0x00000002
1248#define V_028040_Z_32_FLOAT 0x00000003
1249#define S_028040_ARRAY_MODE(x) (((x) & 0xF) << 4)
1250#define G_028040_ARRAY_MODE(x) (((x) >> 4) & 0xF)
1251#define C_028040_ARRAY_MODE 0xFFFFFF0F
1252#define S_028040_READ_SIZE(x) (((x) & 0x1) << 28)
1253#define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1)
1254#define C_028040_READ_SIZE 0xEFFFFFFF
1255#define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29)
1256#define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1)
1257#define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF
1258#define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)
1259#define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)
1260#define C_028040_ZRANGE_PRECISION 0x7FFFFFFF
1261#define S_028040_TILE_SPLIT(x) (((x) & 0x7) << 8)
1262#define G_028040_TILE_SPLIT(x) (((x) >> 8) & 0x7)
1263#define S_028040_NUM_BANKS(x) (((x) & 0x3) << 12)
1264#define G_028040_NUM_BANKS(x) (((x) >> 12) & 0x3)
1265#define S_028040_BANK_WIDTH(x) (((x) & 0x3) << 16)
1266#define G_028040_BANK_WIDTH(x) (((x) >> 16) & 0x3)
1267#define S_028040_BANK_HEIGHT(x) (((x) & 0x3) << 20)
1268#define G_028040_BANK_HEIGHT(x) (((x) >> 20) & 0x3)
1269#define S_028040_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24)
1270#define G_028040_MACRO_TILE_ASPECT(x) (((x) >> 24) & 0x3)
1271#define DB_STENCIL_INFO 0x28044
1272#define R_028044_DB_STENCIL_INFO 0x028044
1273#define S_028044_FORMAT(x) (((x) & 0x1) << 0)
1274#define G_028044_FORMAT(x) (((x) >> 0) & 0x1)
1275#define C_028044_FORMAT 0xFFFFFFFE
1276#define V_028044_STENCIL_INVALID 0
1277#define V_028044_STENCIL_8 1
1278#define G_028044_TILE_SPLIT(x) (((x) >> 8) & 0x7)
1279#define DB_Z_READ_BASE 0x28048
1280#define DB_STENCIL_READ_BASE 0x2804c
1281#define DB_Z_WRITE_BASE 0x28050
1282#define DB_STENCIL_WRITE_BASE 0x28054
1283#define DB_DEPTH_SIZE 0x28058
1284#define R_028058_DB_DEPTH_SIZE 0x028058
1285#define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0)
1286#define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF)
1287#define C_028058_PITCH_TILE_MAX 0xFFFFF800
1288#define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11)
1289#define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF)
1290#define C_028058_HEIGHT_TILE_MAX 0xFFC007FF
1291#define R_02805C_DB_DEPTH_SLICE 0x02805C
1292#define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0)
1293#define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF)
1294#define C_02805C_SLICE_TILE_MAX 0xFFC00000
1295
1296#define SQ_PGM_START_PS 0x28840
1297#define SQ_PGM_START_VS 0x2885c
1298#define SQ_PGM_START_GS 0x28874
1299#define SQ_PGM_START_ES 0x2888c
1300#define SQ_PGM_START_FS 0x288a4
1301#define SQ_PGM_START_HS 0x288b8
1302#define SQ_PGM_START_LS 0x288d0
1303
1304#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8
1305#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8
1306#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8
1307#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08
1308#define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0
1309#define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0
1310#define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0
1311#define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00
1312#define VGT_STRMOUT_CONFIG 0x28b94
1313#define VGT_STRMOUT_BUFFER_CONFIG 0x28b98
1314
1315#define CB_TARGET_MASK 0x28238
1316#define CB_SHADER_MASK 0x2823c
1317
1318#define GDS_ADDR_BASE 0x28720
1319
1320#define CB_IMMED0_BASE 0x28b9c
1321#define CB_IMMED1_BASE 0x28ba0
1322#define CB_IMMED2_BASE 0x28ba4
1323#define CB_IMMED3_BASE 0x28ba8
1324#define CB_IMMED4_BASE 0x28bac
1325#define CB_IMMED5_BASE 0x28bb0
1326#define CB_IMMED6_BASE 0x28bb4
1327#define CB_IMMED7_BASE 0x28bb8
1328#define CB_IMMED8_BASE 0x28bbc
1329#define CB_IMMED9_BASE 0x28bc0
1330#define CB_IMMED10_BASE 0x28bc4
1331#define CB_IMMED11_BASE 0x28bc8
1332
1333/* all 12 CB blocks have these regs */
1334#define CB_COLOR0_BASE 0x28c60
1335#define CB_COLOR0_PITCH 0x28c64
1336#define CB_COLOR0_SLICE 0x28c68
1337#define CB_COLOR0_VIEW 0x28c6c
1338#define R_028C6C_CB_COLOR0_VIEW 0x00028C6C
1339#define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0)
1340#define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF)
1341#define C_028C6C_SLICE_START 0xFFFFF800
1342#define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13)
1343#define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
1344#define C_028C6C_SLICE_MAX 0xFF001FFF
1345#define R_028C70_CB_COLOR0_INFO 0x028C70
1346#define S_028C70_ENDIAN(x) (((x) & 0x3) << 0)
1347#define G_028C70_ENDIAN(x) (((x) >> 0) & 0x3)
1348#define C_028C70_ENDIAN 0xFFFFFFFC
1349#define S_028C70_FORMAT(x) (((x) & 0x3F) << 2)
1350#define G_028C70_FORMAT(x) (((x) >> 2) & 0x3F)
1351#define C_028C70_FORMAT 0xFFFFFF03
1352#define V_028C70_COLOR_INVALID 0x00000000
1353#define V_028C70_COLOR_8 0x00000001
1354#define V_028C70_COLOR_4_4 0x00000002
1355#define V_028C70_COLOR_3_3_2 0x00000003
1356#define V_028C70_COLOR_16 0x00000005
1357#define V_028C70_COLOR_16_FLOAT 0x00000006
1358#define V_028C70_COLOR_8_8 0x00000007
1359#define V_028C70_COLOR_5_6_5 0x00000008
1360#define V_028C70_COLOR_6_5_5 0x00000009
1361#define V_028C70_COLOR_1_5_5_5 0x0000000A
1362#define V_028C70_COLOR_4_4_4_4 0x0000000B
1363#define V_028C70_COLOR_5_5_5_1 0x0000000C
1364#define V_028C70_COLOR_32 0x0000000D
1365#define V_028C70_COLOR_32_FLOAT 0x0000000E
1366#define V_028C70_COLOR_16_16 0x0000000F
1367#define V_028C70_COLOR_16_16_FLOAT 0x00000010
1368#define V_028C70_COLOR_8_24 0x00000011
1369#define V_028C70_COLOR_8_24_FLOAT 0x00000012
1370#define V_028C70_COLOR_24_8 0x00000013
1371#define V_028C70_COLOR_24_8_FLOAT 0x00000014
1372#define V_028C70_COLOR_10_11_11 0x00000015
1373#define V_028C70_COLOR_10_11_11_FLOAT 0x00000016
1374#define V_028C70_COLOR_11_11_10 0x00000017
1375#define V_028C70_COLOR_11_11_10_FLOAT 0x00000018
1376#define V_028C70_COLOR_2_10_10_10 0x00000019
1377#define V_028C70_COLOR_8_8_8_8 0x0000001A
1378#define V_028C70_COLOR_10_10_10_2 0x0000001B
1379#define V_028C70_COLOR_X24_8_32_FLOAT 0x0000001C
1380#define V_028C70_COLOR_32_32 0x0000001D
1381#define V_028C70_COLOR_32_32_FLOAT 0x0000001E
1382#define V_028C70_COLOR_16_16_16_16 0x0000001F
1383#define V_028C70_COLOR_16_16_16_16_FLOAT 0x00000020
1384#define V_028C70_COLOR_32_32_32_32 0x00000022
1385#define V_028C70_COLOR_32_32_32_32_FLOAT 0x00000023
1386#define V_028C70_COLOR_32_32_32_FLOAT 0x00000030
1387#define S_028C70_ARRAY_MODE(x) (((x) & 0xF) << 8)
1388#define G_028C70_ARRAY_MODE(x) (((x) >> 8) & 0xF)
1389#define C_028C70_ARRAY_MODE 0xFFFFF0FF
1390#define V_028C70_ARRAY_LINEAR_GENERAL 0x00000000
1391#define V_028C70_ARRAY_LINEAR_ALIGNED 0x00000001
1392#define V_028C70_ARRAY_1D_TILED_THIN1 0x00000002
1393#define V_028C70_ARRAY_2D_TILED_THIN1 0x00000004
1394#define S_028C70_NUMBER_TYPE(x) (((x) & 0x7) << 12)
1395#define G_028C70_NUMBER_TYPE(x) (((x) >> 12) & 0x7)
1396#define C_028C70_NUMBER_TYPE 0xFFFF8FFF
1397#define V_028C70_NUMBER_UNORM 0x00000000
1398#define V_028C70_NUMBER_SNORM 0x00000001
1399#define V_028C70_NUMBER_USCALED 0x00000002
1400#define V_028C70_NUMBER_SSCALED 0x00000003
1401#define V_028C70_NUMBER_UINT 0x00000004
1402#define V_028C70_NUMBER_SINT 0x00000005
1403#define V_028C70_NUMBER_SRGB 0x00000006
1404#define V_028C70_NUMBER_FLOAT 0x00000007
1405#define S_028C70_COMP_SWAP(x) (((x) & 0x3) << 15)
1406#define G_028C70_COMP_SWAP(x) (((x) >> 15) & 0x3)
1407#define C_028C70_COMP_SWAP 0xFFFE7FFF
1408#define V_028C70_SWAP_STD 0x00000000
1409#define V_028C70_SWAP_ALT 0x00000001
1410#define V_028C70_SWAP_STD_REV 0x00000002
1411#define V_028C70_SWAP_ALT_REV 0x00000003
1412#define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17)
1413#define G_028C70_FAST_CLEAR(x) (((x) >> 17) & 0x1)
1414#define C_028C70_FAST_CLEAR 0xFFFDFFFF
1415#define S_028C70_COMPRESSION(x) (((x) & 0x3) << 18)
1416#define G_028C70_COMPRESSION(x) (((x) >> 18) & 0x3)
1417#define C_028C70_COMPRESSION 0xFFF3FFFF
1418#define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 19)
1419#define G_028C70_BLEND_CLAMP(x) (((x) >> 19) & 0x1)
1420#define C_028C70_BLEND_CLAMP 0xFFF7FFFF
1421#define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 20)
1422#define G_028C70_BLEND_BYPASS(x) (((x) >> 20) & 0x1)
1423#define C_028C70_BLEND_BYPASS 0xFFEFFFFF
1424#define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 21)
1425#define G_028C70_SIMPLE_FLOAT(x) (((x) >> 21) & 0x1)
1426#define C_028C70_SIMPLE_FLOAT 0xFFDFFFFF
1427#define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 22)
1428#define G_028C70_ROUND_MODE(x) (((x) >> 22) & 0x1)
1429#define C_028C70_ROUND_MODE 0xFFBFFFFF
1430#define S_028C70_TILE_COMPACT(x) (((x) & 0x1) << 23)
1431#define G_028C70_TILE_COMPACT(x) (((x) >> 23) & 0x1)
1432#define C_028C70_TILE_COMPACT 0xFF7FFFFF
1433#define S_028C70_SOURCE_FORMAT(x) (((x) & 0x3) << 24)
1434#define G_028C70_SOURCE_FORMAT(x) (((x) >> 24) & 0x3)
1435#define C_028C70_SOURCE_FORMAT 0xFCFFFFFF
1436#define V_028C70_EXPORT_4C_32BPC 0x0
1437#define V_028C70_EXPORT_4C_16BPC 0x1
1438#define V_028C70_EXPORT_2C_32BPC 0x2 /* Do not use */
1439#define S_028C70_RAT(x) (((x) & 0x1) << 26)
1440#define G_028C70_RAT(x) (((x) >> 26) & 0x1)
1441#define C_028C70_RAT 0xFBFFFFFF
1442#define S_028C70_RESOURCE_TYPE(x) (((x) & 0x7) << 27)
1443#define G_028C70_RESOURCE_TYPE(x) (((x) >> 27) & 0x7)
1444#define C_028C70_RESOURCE_TYPE 0xC7FFFFFF
1445
1446#define CB_COLOR0_INFO 0x28c70
1447# define CB_FORMAT(x) ((x) << 2)
1448# define CB_ARRAY_MODE(x) ((x) << 8)
1449# define ARRAY_LINEAR_GENERAL 0
1450# define ARRAY_LINEAR_ALIGNED 1
1451# define ARRAY_1D_TILED_THIN1 2
1452# define ARRAY_2D_TILED_THIN1 4
1453# define CB_SOURCE_FORMAT(x) ((x) << 24)
1454# define CB_SF_EXPORT_FULL 0
1455# define CB_SF_EXPORT_NORM 1
1456#define R_028C74_CB_COLOR0_ATTRIB 0x028C74
1457#define S_028C74_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 4)
1458#define G_028C74_NON_DISP_TILING_ORDER(x) (((x) >> 4) & 0x1)
1459#define C_028C74_NON_DISP_TILING_ORDER 0xFFFFFFEF
1460#define S_028C74_TILE_SPLIT(x) (((x) & 0xf) << 5)
1461#define G_028C74_TILE_SPLIT(x) (((x) >> 5) & 0xf)
1462#define S_028C74_NUM_BANKS(x) (((x) & 0x3) << 10)
1463#define G_028C74_NUM_BANKS(x) (((x) >> 10) & 0x3)
1464#define S_028C74_BANK_WIDTH(x) (((x) & 0x3) << 13)
1465#define G_028C74_BANK_WIDTH(x) (((x) >> 13) & 0x3)
1466#define S_028C74_BANK_HEIGHT(x) (((x) & 0x3) << 16)
1467#define G_028C74_BANK_HEIGHT(x) (((x) >> 16) & 0x3)
1468#define S_028C74_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19)
1469#define G_028C74_MACRO_TILE_ASPECT(x) (((x) >> 19) & 0x3)
1470#define CB_COLOR0_ATTRIB 0x28c74
1471# define CB_TILE_SPLIT(x) (((x) & 0x7) << 5)
1472# define ADDR_SURF_TILE_SPLIT_64B 0
1473# define ADDR_SURF_TILE_SPLIT_128B 1
1474# define ADDR_SURF_TILE_SPLIT_256B 2
1475# define ADDR_SURF_TILE_SPLIT_512B 3
1476# define ADDR_SURF_TILE_SPLIT_1KB 4
1477# define ADDR_SURF_TILE_SPLIT_2KB 5
1478# define ADDR_SURF_TILE_SPLIT_4KB 6
1479# define CB_NUM_BANKS(x) (((x) & 0x3) << 10)
1480# define ADDR_SURF_2_BANK 0
1481# define ADDR_SURF_4_BANK 1
1482# define ADDR_SURF_8_BANK 2
1483# define ADDR_SURF_16_BANK 3
1484# define CB_BANK_WIDTH(x) (((x) & 0x3) << 13)
1485# define ADDR_SURF_BANK_WIDTH_1 0
1486# define ADDR_SURF_BANK_WIDTH_2 1
1487# define ADDR_SURF_BANK_WIDTH_4 2
1488# define ADDR_SURF_BANK_WIDTH_8 3
1489# define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16)
1490# define ADDR_SURF_BANK_HEIGHT_1 0
1491# define ADDR_SURF_BANK_HEIGHT_2 1
1492# define ADDR_SURF_BANK_HEIGHT_4 2
1493# define ADDR_SURF_BANK_HEIGHT_8 3
1494# define CB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19)
1495#define CB_COLOR0_DIM 0x28c78
1496/* only CB0-7 blocks have these regs */
1497#define CB_COLOR0_CMASK 0x28c7c
1498#define CB_COLOR0_CMASK_SLICE 0x28c80
1499#define CB_COLOR0_FMASK 0x28c84
1500#define CB_COLOR0_FMASK_SLICE 0x28c88
1501#define CB_COLOR0_CLEAR_WORD0 0x28c8c
1502#define CB_COLOR0_CLEAR_WORD1 0x28c90
1503#define CB_COLOR0_CLEAR_WORD2 0x28c94
1504#define CB_COLOR0_CLEAR_WORD3 0x28c98
1505
1506#define CB_COLOR1_BASE 0x28c9c
1507#define CB_COLOR2_BASE 0x28cd8
1508#define CB_COLOR3_BASE 0x28d14
1509#define CB_COLOR4_BASE 0x28d50
1510#define CB_COLOR5_BASE 0x28d8c
1511#define CB_COLOR6_BASE 0x28dc8
1512#define CB_COLOR7_BASE 0x28e04
1513#define CB_COLOR8_BASE 0x28e40
1514#define CB_COLOR9_BASE 0x28e5c
1515#define CB_COLOR10_BASE 0x28e78
1516#define CB_COLOR11_BASE 0x28e94
1517
1518#define CB_COLOR1_PITCH 0x28ca0
1519#define CB_COLOR2_PITCH 0x28cdc
1520#define CB_COLOR3_PITCH 0x28d18
1521#define CB_COLOR4_PITCH 0x28d54
1522#define CB_COLOR5_PITCH 0x28d90
1523#define CB_COLOR6_PITCH 0x28dcc
1524#define CB_COLOR7_PITCH 0x28e08
1525#define CB_COLOR8_PITCH 0x28e44
1526#define CB_COLOR9_PITCH 0x28e60
1527#define CB_COLOR10_PITCH 0x28e7c
1528#define CB_COLOR11_PITCH 0x28e98
1529
1530#define CB_COLOR1_SLICE 0x28ca4
1531#define CB_COLOR2_SLICE 0x28ce0
1532#define CB_COLOR3_SLICE 0x28d1c
1533#define CB_COLOR4_SLICE 0x28d58
1534#define CB_COLOR5_SLICE 0x28d94
1535#define CB_COLOR6_SLICE 0x28dd0
1536#define CB_COLOR7_SLICE 0x28e0c
1537#define CB_COLOR8_SLICE 0x28e48
1538#define CB_COLOR9_SLICE 0x28e64
1539#define CB_COLOR10_SLICE 0x28e80
1540#define CB_COLOR11_SLICE 0x28e9c
1541
1542#define CB_COLOR1_VIEW 0x28ca8
1543#define CB_COLOR2_VIEW 0x28ce4
1544#define CB_COLOR3_VIEW 0x28d20
1545#define CB_COLOR4_VIEW 0x28d5c
1546#define CB_COLOR5_VIEW 0x28d98
1547#define CB_COLOR6_VIEW 0x28dd4
1548#define CB_COLOR7_VIEW 0x28e10
1549#define CB_COLOR8_VIEW 0x28e4c
1550#define CB_COLOR9_VIEW 0x28e68
1551#define CB_COLOR10_VIEW 0x28e84
1552#define CB_COLOR11_VIEW 0x28ea0
1553
1554#define CB_COLOR1_INFO 0x28cac
1555#define CB_COLOR2_INFO 0x28ce8
1556#define CB_COLOR3_INFO 0x28d24
1557#define CB_COLOR4_INFO 0x28d60
1558#define CB_COLOR5_INFO 0x28d9c
1559#define CB_COLOR6_INFO 0x28dd8
1560#define CB_COLOR7_INFO 0x28e14
1561#define CB_COLOR8_INFO 0x28e50
1562#define CB_COLOR9_INFO 0x28e6c
1563#define CB_COLOR10_INFO 0x28e88
1564#define CB_COLOR11_INFO 0x28ea4
1565
1566#define CB_COLOR1_ATTRIB 0x28cb0
1567#define CB_COLOR2_ATTRIB 0x28cec
1568#define CB_COLOR3_ATTRIB 0x28d28
1569#define CB_COLOR4_ATTRIB 0x28d64
1570#define CB_COLOR5_ATTRIB 0x28da0
1571#define CB_COLOR6_ATTRIB 0x28ddc
1572#define CB_COLOR7_ATTRIB 0x28e18
1573#define CB_COLOR8_ATTRIB 0x28e54
1574#define CB_COLOR9_ATTRIB 0x28e70
1575#define CB_COLOR10_ATTRIB 0x28e8c
1576#define CB_COLOR11_ATTRIB 0x28ea8
1577
1578#define CB_COLOR1_DIM 0x28cb4
1579#define CB_COLOR2_DIM 0x28cf0
1580#define CB_COLOR3_DIM 0x28d2c
1581#define CB_COLOR4_DIM 0x28d68
1582#define CB_COLOR5_DIM 0x28da4
1583#define CB_COLOR6_DIM 0x28de0
1584#define CB_COLOR7_DIM 0x28e1c
1585#define CB_COLOR8_DIM 0x28e58
1586#define CB_COLOR9_DIM 0x28e74
1587#define CB_COLOR10_DIM 0x28e90
1588#define CB_COLOR11_DIM 0x28eac
1589
1590#define CB_COLOR1_CMASK 0x28cb8
1591#define CB_COLOR2_CMASK 0x28cf4
1592#define CB_COLOR3_CMASK 0x28d30
1593#define CB_COLOR4_CMASK 0x28d6c
1594#define CB_COLOR5_CMASK 0x28da8
1595#define CB_COLOR6_CMASK 0x28de4
1596#define CB_COLOR7_CMASK 0x28e20
1597
1598#define CB_COLOR1_CMASK_SLICE 0x28cbc
1599#define CB_COLOR2_CMASK_SLICE 0x28cf8
1600#define CB_COLOR3_CMASK_SLICE 0x28d34
1601#define CB_COLOR4_CMASK_SLICE 0x28d70
1602#define CB_COLOR5_CMASK_SLICE 0x28dac
1603#define CB_COLOR6_CMASK_SLICE 0x28de8
1604#define CB_COLOR7_CMASK_SLICE 0x28e24
1605
1606#define CB_COLOR1_FMASK 0x28cc0
1607#define CB_COLOR2_FMASK 0x28cfc
1608#define CB_COLOR3_FMASK 0x28d38
1609#define CB_COLOR4_FMASK 0x28d74
1610#define CB_COLOR5_FMASK 0x28db0
1611#define CB_COLOR6_FMASK 0x28dec
1612#define CB_COLOR7_FMASK 0x28e28
1613
1614#define CB_COLOR1_FMASK_SLICE 0x28cc4
1615#define CB_COLOR2_FMASK_SLICE 0x28d00
1616#define CB_COLOR3_FMASK_SLICE 0x28d3c
1617#define CB_COLOR4_FMASK_SLICE 0x28d78
1618#define CB_COLOR5_FMASK_SLICE 0x28db4
1619#define CB_COLOR6_FMASK_SLICE 0x28df0
1620#define CB_COLOR7_FMASK_SLICE 0x28e2c
1621
1622#define CB_COLOR1_CLEAR_WORD0 0x28cc8
1623#define CB_COLOR2_CLEAR_WORD0 0x28d04
1624#define CB_COLOR3_CLEAR_WORD0 0x28d40
1625#define CB_COLOR4_CLEAR_WORD0 0x28d7c
1626#define CB_COLOR5_CLEAR_WORD0 0x28db8
1627#define CB_COLOR6_CLEAR_WORD0 0x28df4
1628#define CB_COLOR7_CLEAR_WORD0 0x28e30
1629
1630#define CB_COLOR1_CLEAR_WORD1 0x28ccc
1631#define CB_COLOR2_CLEAR_WORD1 0x28d08
1632#define CB_COLOR3_CLEAR_WORD1 0x28d44
1633#define CB_COLOR4_CLEAR_WORD1 0x28d80
1634#define CB_COLOR5_CLEAR_WORD1 0x28dbc
1635#define CB_COLOR6_CLEAR_WORD1 0x28df8
1636#define CB_COLOR7_CLEAR_WORD1 0x28e34
1637
1638#define CB_COLOR1_CLEAR_WORD2 0x28cd0
1639#define CB_COLOR2_CLEAR_WORD2 0x28d0c
1640#define CB_COLOR3_CLEAR_WORD2 0x28d48
1641#define CB_COLOR4_CLEAR_WORD2 0x28d84
1642#define CB_COLOR5_CLEAR_WORD2 0x28dc0
1643#define CB_COLOR6_CLEAR_WORD2 0x28dfc
1644#define CB_COLOR7_CLEAR_WORD2 0x28e38
1645
1646#define CB_COLOR1_CLEAR_WORD3 0x28cd4
1647#define CB_COLOR2_CLEAR_WORD3 0x28d10
1648#define CB_COLOR3_CLEAR_WORD3 0x28d4c
1649#define CB_COLOR4_CLEAR_WORD3 0x28d88
1650#define CB_COLOR5_CLEAR_WORD3 0x28dc4
1651#define CB_COLOR6_CLEAR_WORD3 0x28e00
1652#define CB_COLOR7_CLEAR_WORD3 0x28e3c
1653
1654#define SQ_TEX_RESOURCE_WORD0_0 0x30000
1655# define TEX_DIM(x) ((x) << 0)
1656# define SQ_TEX_DIM_1D 0
1657# define SQ_TEX_DIM_2D 1
1658# define SQ_TEX_DIM_3D 2
1659# define SQ_TEX_DIM_CUBEMAP 3
1660# define SQ_TEX_DIM_1D_ARRAY 4
1661# define SQ_TEX_DIM_2D_ARRAY 5
1662# define SQ_TEX_DIM_2D_MSAA 6
1663# define SQ_TEX_DIM_2D_ARRAY_MSAA 7
1664#define SQ_TEX_RESOURCE_WORD1_0 0x30004
1665# define TEX_ARRAY_MODE(x) ((x) << 28)
1666#define SQ_TEX_RESOURCE_WORD2_0 0x30008
1667#define SQ_TEX_RESOURCE_WORD3_0 0x3000C
1668#define SQ_TEX_RESOURCE_WORD4_0 0x30010
1669# define TEX_DST_SEL_X(x) ((x) << 16)
1670# define TEX_DST_SEL_Y(x) ((x) << 19)
1671# define TEX_DST_SEL_Z(x) ((x) << 22)
1672# define TEX_DST_SEL_W(x) ((x) << 25)
1673# define SQ_SEL_X 0
1674# define SQ_SEL_Y 1
1675# define SQ_SEL_Z 2
1676# define SQ_SEL_W 3
1677# define SQ_SEL_0 4
1678# define SQ_SEL_1 5
1679#define SQ_TEX_RESOURCE_WORD5_0 0x30014
1680#define SQ_TEX_RESOURCE_WORD6_0 0x30018
1681# define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29)
1682#define SQ_TEX_RESOURCE_WORD7_0 0x3001c
1683# define MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6)
1684# define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8)
1685# define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10)
1686# define TEX_NUM_BANKS(x) (((x) & 0x3) << 16)
1687#define R_030000_SQ_TEX_RESOURCE_WORD0_0 0x030000
1688#define S_030000_DIM(x) (((x) & 0x7) << 0)
1689#define G_030000_DIM(x) (((x) >> 0) & 0x7)
1690#define C_030000_DIM 0xFFFFFFF8
1691#define V_030000_SQ_TEX_DIM_1D 0x00000000
1692#define V_030000_SQ_TEX_DIM_2D 0x00000001
1693#define V_030000_SQ_TEX_DIM_3D 0x00000002
1694#define V_030000_SQ_TEX_DIM_CUBEMAP 0x00000003
1695#define V_030000_SQ_TEX_DIM_1D_ARRAY 0x00000004
1696#define V_030000_SQ_TEX_DIM_2D_ARRAY 0x00000005
1697#define V_030000_SQ_TEX_DIM_2D_MSAA 0x00000006
1698#define V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007
1699#define S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 5)
1700#define G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 5) & 0x1)
1701#define C_030000_NON_DISP_TILING_ORDER 0xFFFFFFDF
1702#define S_030000_PITCH(x) (((x) & 0xFFF) << 6)
1703#define G_030000_PITCH(x) (((x) >> 6) & 0xFFF)
1704#define C_030000_PITCH 0xFFFC003F
1705#define S_030000_TEX_WIDTH(x) (((x) & 0x3FFF) << 18)
1706#define G_030000_TEX_WIDTH(x) (((x) >> 18) & 0x3FFF)
1707#define C_030000_TEX_WIDTH 0x0003FFFF
1708#define R_030004_SQ_TEX_RESOURCE_WORD1_0 0x030004
1709#define S_030004_TEX_HEIGHT(x) (((x) & 0x3FFF) << 0)
1710#define G_030004_TEX_HEIGHT(x) (((x) >> 0) & 0x3FFF)
1711#define C_030004_TEX_HEIGHT 0xFFFFC000
1712#define S_030004_TEX_DEPTH(x) (((x) & 0x1FFF) << 14)
1713#define G_030004_TEX_DEPTH(x) (((x) >> 14) & 0x1FFF)
1714#define C_030004_TEX_DEPTH 0xF8003FFF
1715#define S_030004_ARRAY_MODE(x) (((x) & 0xF) << 28)
1716#define G_030004_ARRAY_MODE(x) (((x) >> 28) & 0xF)
1717#define C_030004_ARRAY_MODE 0x0FFFFFFF
1718#define R_030008_SQ_TEX_RESOURCE_WORD2_0 0x030008
1719#define S_030008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
1720#define G_030008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
1721#define C_030008_BASE_ADDRESS 0x00000000
1722#define R_03000C_SQ_TEX_RESOURCE_WORD3_0 0x03000C
1723#define S_03000C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
1724#define G_03000C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
1725#define C_03000C_MIP_ADDRESS 0x00000000
1726#define R_030010_SQ_TEX_RESOURCE_WORD4_0 0x030010
1727#define S_030010_FORMAT_COMP_X(x) (((x) & 0x3) << 0)
1728#define G_030010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3)
1729#define C_030010_FORMAT_COMP_X 0xFFFFFFFC
1730#define V_030010_SQ_FORMAT_COMP_UNSIGNED 0x00000000
1731#define V_030010_SQ_FORMAT_COMP_SIGNED 0x00000001
1732#define V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED 0x00000002
1733#define S_030010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2)
1734#define G_030010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3)
1735#define C_030010_FORMAT_COMP_Y 0xFFFFFFF3
1736#define S_030010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4)
1737#define G_030010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3)
1738#define C_030010_FORMAT_COMP_Z 0xFFFFFFCF
1739#define S_030010_FORMAT_COMP_W(x) (((x) & 0x3) << 6)
1740#define G_030010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3)
1741#define C_030010_FORMAT_COMP_W 0xFFFFFF3F
1742#define S_030010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8)
1743#define G_030010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3)
1744#define C_030010_NUM_FORMAT_ALL 0xFFFFFCFF
1745#define V_030010_SQ_NUM_FORMAT_NORM 0x00000000
1746#define V_030010_SQ_NUM_FORMAT_INT 0x00000001
1747#define V_030010_SQ_NUM_FORMAT_SCALED 0x00000002
1748#define S_030010_SRF_MODE_ALL(x) (((x) & 0x1) << 10)
1749#define G_030010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1)
1750#define C_030010_SRF_MODE_ALL 0xFFFFFBFF
1751#define V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE 0x00000000
1752#define V_030010_SRF_MODE_NO_ZERO 0x00000001
1753#define S_030010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11)
1754#define G_030010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1)
1755#define C_030010_FORCE_DEGAMMA 0xFFFFF7FF
1756#define S_030010_ENDIAN_SWAP(x) (((x) & 0x3) << 12)
1757#define G_030010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3)
1758#define C_030010_ENDIAN_SWAP 0xFFFFCFFF
1759#define S_030010_DST_SEL_X(x) (((x) & 0x7) << 16)
1760#define G_030010_DST_SEL_X(x) (((x) >> 16) & 0x7)
1761#define C_030010_DST_SEL_X 0xFFF8FFFF
1762#define V_030010_SQ_SEL_X 0x00000000
1763#define V_030010_SQ_SEL_Y 0x00000001
1764#define V_030010_SQ_SEL_Z 0x00000002
1765#define V_030010_SQ_SEL_W 0x00000003
1766#define V_030010_SQ_SEL_0 0x00000004
1767#define V_030010_SQ_SEL_1 0x00000005
1768#define S_030010_DST_SEL_Y(x) (((x) & 0x7) << 19)
1769#define G_030010_DST_SEL_Y(x) (((x) >> 19) & 0x7)
1770#define C_030010_DST_SEL_Y 0xFFC7FFFF
1771#define S_030010_DST_SEL_Z(x) (((x) & 0x7) << 22)
1772#define G_030010_DST_SEL_Z(x) (((x) >> 22) & 0x7)
1773#define C_030010_DST_SEL_Z 0xFE3FFFFF
1774#define S_030010_DST_SEL_W(x) (((x) & 0x7) << 25)
1775#define G_030010_DST_SEL_W(x) (((x) >> 25) & 0x7)
1776#define C_030010_DST_SEL_W 0xF1FFFFFF
1777#define S_030010_BASE_LEVEL(x) (((x) & 0xF) << 28)
1778#define G_030010_BASE_LEVEL(x) (((x) >> 28) & 0xF)
1779#define C_030010_BASE_LEVEL 0x0FFFFFFF
1780#define R_030014_SQ_TEX_RESOURCE_WORD5_0 0x030014
1781#define S_030014_LAST_LEVEL(x) (((x) & 0xF) << 0)
1782#define G_030014_LAST_LEVEL(x) (((x) >> 0) & 0xF)
1783#define C_030014_LAST_LEVEL 0xFFFFFFF0
1784#define S_030014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4)
1785#define G_030014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF)
1786#define C_030014_BASE_ARRAY 0xFFFE000F
1787#define S_030014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17)
1788#define G_030014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF)
1789#define C_030014_LAST_ARRAY 0xC001FFFF
1790#define R_030018_SQ_TEX_RESOURCE_WORD6_0 0x030018
1791#define S_030018_MAX_ANISO(x) (((x) & 0x7) << 0)
1792#define G_030018_MAX_ANISO(x) (((x) >> 0) & 0x7)
1793#define C_030018_MAX_ANISO 0xFFFFFFF8
1794#define S_030018_PERF_MODULATION(x) (((x) & 0x7) << 3)
1795#define G_030018_PERF_MODULATION(x) (((x) >> 3) & 0x7)
1796#define C_030018_PERF_MODULATION 0xFFFFFFC7
1797#define S_030018_INTERLACED(x) (((x) & 0x1) << 6)
1798#define G_030018_INTERLACED(x) (((x) >> 6) & 0x1)
1799#define C_030018_INTERLACED 0xFFFFFFBF
1800#define S_030018_TILE_SPLIT(x) (((x) & 0x7) << 29)
1801#define G_030018_TILE_SPLIT(x) (((x) >> 29) & 0x7)
1802#define R_03001C_SQ_TEX_RESOURCE_WORD7_0 0x03001C
1803#define S_03001C_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6)
1804#define G_03001C_MACRO_TILE_ASPECT(x) (((x) >> 6) & 0x3)
1805#define S_03001C_BANK_WIDTH(x) (((x) & 0x3) << 8)
1806#define G_03001C_BANK_WIDTH(x) (((x) >> 8) & 0x3)
1807#define S_03001C_BANK_HEIGHT(x) (((x) & 0x3) << 10)
1808#define G_03001C_BANK_HEIGHT(x) (((x) >> 10) & 0x3)
1809#define S_03001C_NUM_BANKS(x) (((x) & 0x3) << 16)
1810#define G_03001C_NUM_BANKS(x) (((x) >> 16) & 0x3)
1811#define S_03001C_TYPE(x) (((x) & 0x3) << 30)
1812#define G_03001C_TYPE(x) (((x) >> 30) & 0x3)
1813#define C_03001C_TYPE 0x3FFFFFFF
1814#define V_03001C_SQ_TEX_VTX_INVALID_TEXTURE 0x00000000
1815#define V_03001C_SQ_TEX_VTX_INVALID_BUFFER 0x00000001
1816#define V_03001C_SQ_TEX_VTX_VALID_TEXTURE 0x00000002
1817#define V_03001C_SQ_TEX_VTX_VALID_BUFFER 0x00000003
1818#define S_03001C_DATA_FORMAT(x) (((x) & 0x3F) << 0)
1819#define G_03001C_DATA_FORMAT(x) (((x) >> 0) & 0x3F)
1820#define C_03001C_DATA_FORMAT 0xFFFFFFC0
1821
1822#define SQ_VTX_CONSTANT_WORD0_0 0x30000
1823#define SQ_VTX_CONSTANT_WORD1_0 0x30004
1824#define SQ_VTX_CONSTANT_WORD2_0 0x30008
1825# define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0)
1826# define SQ_VTXC_STRIDE(x) ((x) << 8)
1827# define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30)
1828# define SQ_ENDIAN_NONE 0
1829# define SQ_ENDIAN_8IN16 1
1830# define SQ_ENDIAN_8IN32 2
1831#define SQ_VTX_CONSTANT_WORD3_0 0x3000C
1832# define SQ_VTCX_SEL_X(x) ((x) << 3)
1833# define SQ_VTCX_SEL_Y(x) ((x) << 6)
1834# define SQ_VTCX_SEL_Z(x) ((x) << 9)
1835# define SQ_VTCX_SEL_W(x) ((x) << 12)
1836#define SQ_VTX_CONSTANT_WORD4_0 0x30010
1837#define SQ_VTX_CONSTANT_WORD5_0 0x30014
1838#define SQ_VTX_CONSTANT_WORD6_0 0x30018
1839#define SQ_VTX_CONSTANT_WORD7_0 0x3001c
1840
1841#define TD_PS_BORDER_COLOR_INDEX 0xA400
1842#define TD_PS_BORDER_COLOR_RED 0xA404
1843#define TD_PS_BORDER_COLOR_GREEN 0xA408
1844#define TD_PS_BORDER_COLOR_BLUE 0xA40C
1845#define TD_PS_BORDER_COLOR_ALPHA 0xA410
1846#define TD_VS_BORDER_COLOR_INDEX 0xA414
1847#define TD_VS_BORDER_COLOR_RED 0xA418
1848#define TD_VS_BORDER_COLOR_GREEN 0xA41C
1849#define TD_VS_BORDER_COLOR_BLUE 0xA420
1850#define TD_VS_BORDER_COLOR_ALPHA 0xA424
1851#define TD_GS_BORDER_COLOR_INDEX 0xA428
1852#define TD_GS_BORDER_COLOR_RED 0xA42C
1853#define TD_GS_BORDER_COLOR_GREEN 0xA430
1854#define TD_GS_BORDER_COLOR_BLUE 0xA434
1855#define TD_GS_BORDER_COLOR_ALPHA 0xA438
1856#define TD_HS_BORDER_COLOR_INDEX 0xA43C
1857#define TD_HS_BORDER_COLOR_RED 0xA440
1858#define TD_HS_BORDER_COLOR_GREEN 0xA444
1859#define TD_HS_BORDER_COLOR_BLUE 0xA448
1860#define TD_HS_BORDER_COLOR_ALPHA 0xA44C
1861#define TD_LS_BORDER_COLOR_INDEX 0xA450
1862#define TD_LS_BORDER_COLOR_RED 0xA454
1863#define TD_LS_BORDER_COLOR_GREEN 0xA458
1864#define TD_LS_BORDER_COLOR_BLUE 0xA45C
1865#define TD_LS_BORDER_COLOR_ALPHA 0xA460
1866#define TD_CS_BORDER_COLOR_INDEX 0xA464
1867#define TD_CS_BORDER_COLOR_RED 0xA468
1868#define TD_CS_BORDER_COLOR_GREEN 0xA46C
1869#define TD_CS_BORDER_COLOR_BLUE 0xA470
1870#define TD_CS_BORDER_COLOR_ALPHA 0xA474
1871
1872/* cayman 3D regs */
1873#define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B4
1874#define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS 0x8E48
1875#define CAYMAN_DB_EQAA 0x28804
1876#define CAYMAN_DB_DEPTH_INFO 0x2803C
1877#define CAYMAN_PA_SC_AA_CONFIG 0x28BE0
1878#define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0
1879#define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7
1880#define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358
1881/* cayman packet3 addition */
1882#define CAYMAN_PACKET3_DEALLOC_STATE 0x14
1883
1884#endif