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1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
27#include "drmP.h"
28#include "radeon.h"
29#include "radeon_asic.h"
30#include "radeon_drm.h"
31#include "evergreend.h"
32#include "atom.h"
33#include "avivod.h"
34#include "evergreen_reg.h"
35#include "evergreen_blit_shaders.h"
36
37#define EVERGREEN_PFP_UCODE_SIZE 1120
38#define EVERGREEN_PM4_UCODE_SIZE 1376
39
40static void evergreen_gpu_init(struct radeon_device *rdev);
41void evergreen_fini(struct radeon_device *rdev);
42static void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
43
44void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
45{
46 u16 ctl, v;
47 int cap, err;
48
49 cap = pci_pcie_cap(rdev->pdev);
50 if (!cap)
51 return;
52
53 err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
54 if (err)
55 return;
56
57 v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
58
59 /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
60 * to avoid hangs or perfomance issues
61 */
62 if ((v == 0) || (v == 6) || (v == 7)) {
63 ctl &= ~PCI_EXP_DEVCTL_READRQ;
64 ctl |= (2 << 12);
65 pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
66 }
67}
68
69void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
70{
71 /* enable the pflip int */
72 radeon_irq_kms_pflip_irq_get(rdev, crtc);
73}
74
75void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
76{
77 /* disable the pflip int */
78 radeon_irq_kms_pflip_irq_put(rdev, crtc);
79}
80
81u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
82{
83 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
84 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
85
86 /* Lock the graphics update lock */
87 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
88 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
89
90 /* update the scanout addresses */
91 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
92 upper_32_bits(crtc_base));
93 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
94 (u32)crtc_base);
95
96 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
97 upper_32_bits(crtc_base));
98 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
99 (u32)crtc_base);
100
101 /* Wait for update_pending to go high. */
102 while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING));
103 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
104
105 /* Unlock the lock, so double-buffering can take place inside vblank */
106 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
107 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
108
109 /* Return current update_pending status: */
110 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
111}
112
113/* get temperature in millidegrees */
114int evergreen_get_temp(struct radeon_device *rdev)
115{
116 u32 temp, toffset;
117 int actual_temp = 0;
118
119 if (rdev->family == CHIP_JUNIPER) {
120 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
121 TOFFSET_SHIFT;
122 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
123 TS0_ADC_DOUT_SHIFT;
124
125 if (toffset & 0x100)
126 actual_temp = temp / 2 - (0x200 - toffset);
127 else
128 actual_temp = temp / 2 + toffset;
129
130 actual_temp = actual_temp * 1000;
131
132 } else {
133 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
134 ASIC_T_SHIFT;
135
136 if (temp & 0x400)
137 actual_temp = -256;
138 else if (temp & 0x200)
139 actual_temp = 255;
140 else if (temp & 0x100) {
141 actual_temp = temp & 0x1ff;
142 actual_temp |= ~0x1ff;
143 } else
144 actual_temp = temp & 0xff;
145
146 actual_temp = (actual_temp * 1000) / 2;
147 }
148
149 return actual_temp;
150}
151
152int sumo_get_temp(struct radeon_device *rdev)
153{
154 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
155 int actual_temp = temp - 49;
156
157 return actual_temp * 1000;
158}
159
160void evergreen_pm_misc(struct radeon_device *rdev)
161{
162 int req_ps_idx = rdev->pm.requested_power_state_index;
163 int req_cm_idx = rdev->pm.requested_clock_mode_index;
164 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
165 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
166
167 if (voltage->type == VOLTAGE_SW) {
168 /* 0xff01 is a flag rather then an actual voltage */
169 if (voltage->voltage == 0xff01)
170 return;
171 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
172 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
173 rdev->pm.current_vddc = voltage->voltage;
174 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
175 }
176 /* 0xff01 is a flag rather then an actual voltage */
177 if (voltage->vddci == 0xff01)
178 return;
179 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
180 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
181 rdev->pm.current_vddci = voltage->vddci;
182 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
183 }
184 }
185}
186
187void evergreen_pm_prepare(struct radeon_device *rdev)
188{
189 struct drm_device *ddev = rdev->ddev;
190 struct drm_crtc *crtc;
191 struct radeon_crtc *radeon_crtc;
192 u32 tmp;
193
194 /* disable any active CRTCs */
195 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
196 radeon_crtc = to_radeon_crtc(crtc);
197 if (radeon_crtc->enabled) {
198 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
199 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
200 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
201 }
202 }
203}
204
205void evergreen_pm_finish(struct radeon_device *rdev)
206{
207 struct drm_device *ddev = rdev->ddev;
208 struct drm_crtc *crtc;
209 struct radeon_crtc *radeon_crtc;
210 u32 tmp;
211
212 /* enable any active CRTCs */
213 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
214 radeon_crtc = to_radeon_crtc(crtc);
215 if (radeon_crtc->enabled) {
216 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
217 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
218 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
219 }
220 }
221}
222
223bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
224{
225 bool connected = false;
226
227 switch (hpd) {
228 case RADEON_HPD_1:
229 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
230 connected = true;
231 break;
232 case RADEON_HPD_2:
233 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
234 connected = true;
235 break;
236 case RADEON_HPD_3:
237 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
238 connected = true;
239 break;
240 case RADEON_HPD_4:
241 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
242 connected = true;
243 break;
244 case RADEON_HPD_5:
245 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
246 connected = true;
247 break;
248 case RADEON_HPD_6:
249 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
250 connected = true;
251 break;
252 default:
253 break;
254 }
255
256 return connected;
257}
258
259void evergreen_hpd_set_polarity(struct radeon_device *rdev,
260 enum radeon_hpd_id hpd)
261{
262 u32 tmp;
263 bool connected = evergreen_hpd_sense(rdev, hpd);
264
265 switch (hpd) {
266 case RADEON_HPD_1:
267 tmp = RREG32(DC_HPD1_INT_CONTROL);
268 if (connected)
269 tmp &= ~DC_HPDx_INT_POLARITY;
270 else
271 tmp |= DC_HPDx_INT_POLARITY;
272 WREG32(DC_HPD1_INT_CONTROL, tmp);
273 break;
274 case RADEON_HPD_2:
275 tmp = RREG32(DC_HPD2_INT_CONTROL);
276 if (connected)
277 tmp &= ~DC_HPDx_INT_POLARITY;
278 else
279 tmp |= DC_HPDx_INT_POLARITY;
280 WREG32(DC_HPD2_INT_CONTROL, tmp);
281 break;
282 case RADEON_HPD_3:
283 tmp = RREG32(DC_HPD3_INT_CONTROL);
284 if (connected)
285 tmp &= ~DC_HPDx_INT_POLARITY;
286 else
287 tmp |= DC_HPDx_INT_POLARITY;
288 WREG32(DC_HPD3_INT_CONTROL, tmp);
289 break;
290 case RADEON_HPD_4:
291 tmp = RREG32(DC_HPD4_INT_CONTROL);
292 if (connected)
293 tmp &= ~DC_HPDx_INT_POLARITY;
294 else
295 tmp |= DC_HPDx_INT_POLARITY;
296 WREG32(DC_HPD4_INT_CONTROL, tmp);
297 break;
298 case RADEON_HPD_5:
299 tmp = RREG32(DC_HPD5_INT_CONTROL);
300 if (connected)
301 tmp &= ~DC_HPDx_INT_POLARITY;
302 else
303 tmp |= DC_HPDx_INT_POLARITY;
304 WREG32(DC_HPD5_INT_CONTROL, tmp);
305 break;
306 case RADEON_HPD_6:
307 tmp = RREG32(DC_HPD6_INT_CONTROL);
308 if (connected)
309 tmp &= ~DC_HPDx_INT_POLARITY;
310 else
311 tmp |= DC_HPDx_INT_POLARITY;
312 WREG32(DC_HPD6_INT_CONTROL, tmp);
313 break;
314 default:
315 break;
316 }
317}
318
319void evergreen_hpd_init(struct radeon_device *rdev)
320{
321 struct drm_device *dev = rdev->ddev;
322 struct drm_connector *connector;
323 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
324 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
325
326 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
327 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
328 switch (radeon_connector->hpd.hpd) {
329 case RADEON_HPD_1:
330 WREG32(DC_HPD1_CONTROL, tmp);
331 rdev->irq.hpd[0] = true;
332 break;
333 case RADEON_HPD_2:
334 WREG32(DC_HPD2_CONTROL, tmp);
335 rdev->irq.hpd[1] = true;
336 break;
337 case RADEON_HPD_3:
338 WREG32(DC_HPD3_CONTROL, tmp);
339 rdev->irq.hpd[2] = true;
340 break;
341 case RADEON_HPD_4:
342 WREG32(DC_HPD4_CONTROL, tmp);
343 rdev->irq.hpd[3] = true;
344 break;
345 case RADEON_HPD_5:
346 WREG32(DC_HPD5_CONTROL, tmp);
347 rdev->irq.hpd[4] = true;
348 break;
349 case RADEON_HPD_6:
350 WREG32(DC_HPD6_CONTROL, tmp);
351 rdev->irq.hpd[5] = true;
352 break;
353 default:
354 break;
355 }
356 }
357 if (rdev->irq.installed)
358 evergreen_irq_set(rdev);
359}
360
361void evergreen_hpd_fini(struct radeon_device *rdev)
362{
363 struct drm_device *dev = rdev->ddev;
364 struct drm_connector *connector;
365
366 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
367 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
368 switch (radeon_connector->hpd.hpd) {
369 case RADEON_HPD_1:
370 WREG32(DC_HPD1_CONTROL, 0);
371 rdev->irq.hpd[0] = false;
372 break;
373 case RADEON_HPD_2:
374 WREG32(DC_HPD2_CONTROL, 0);
375 rdev->irq.hpd[1] = false;
376 break;
377 case RADEON_HPD_3:
378 WREG32(DC_HPD3_CONTROL, 0);
379 rdev->irq.hpd[2] = false;
380 break;
381 case RADEON_HPD_4:
382 WREG32(DC_HPD4_CONTROL, 0);
383 rdev->irq.hpd[3] = false;
384 break;
385 case RADEON_HPD_5:
386 WREG32(DC_HPD5_CONTROL, 0);
387 rdev->irq.hpd[4] = false;
388 break;
389 case RADEON_HPD_6:
390 WREG32(DC_HPD6_CONTROL, 0);
391 rdev->irq.hpd[5] = false;
392 break;
393 default:
394 break;
395 }
396 }
397}
398
399/* watermark setup */
400
401static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
402 struct radeon_crtc *radeon_crtc,
403 struct drm_display_mode *mode,
404 struct drm_display_mode *other_mode)
405{
406 u32 tmp;
407 /*
408 * Line Buffer Setup
409 * There are 3 line buffers, each one shared by 2 display controllers.
410 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
411 * the display controllers. The paritioning is done via one of four
412 * preset allocations specified in bits 2:0:
413 * first display controller
414 * 0 - first half of lb (3840 * 2)
415 * 1 - first 3/4 of lb (5760 * 2)
416 * 2 - whole lb (7680 * 2), other crtc must be disabled
417 * 3 - first 1/4 of lb (1920 * 2)
418 * second display controller
419 * 4 - second half of lb (3840 * 2)
420 * 5 - second 3/4 of lb (5760 * 2)
421 * 6 - whole lb (7680 * 2), other crtc must be disabled
422 * 7 - last 1/4 of lb (1920 * 2)
423 */
424 /* this can get tricky if we have two large displays on a paired group
425 * of crtcs. Ideally for multiple large displays we'd assign them to
426 * non-linked crtcs for maximum line buffer allocation.
427 */
428 if (radeon_crtc->base.enabled && mode) {
429 if (other_mode)
430 tmp = 0; /* 1/2 */
431 else
432 tmp = 2; /* whole */
433 } else
434 tmp = 0;
435
436 /* second controller of the pair uses second half of the lb */
437 if (radeon_crtc->crtc_id % 2)
438 tmp += 4;
439 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
440
441 if (radeon_crtc->base.enabled && mode) {
442 switch (tmp) {
443 case 0:
444 case 4:
445 default:
446 if (ASIC_IS_DCE5(rdev))
447 return 4096 * 2;
448 else
449 return 3840 * 2;
450 case 1:
451 case 5:
452 if (ASIC_IS_DCE5(rdev))
453 return 6144 * 2;
454 else
455 return 5760 * 2;
456 case 2:
457 case 6:
458 if (ASIC_IS_DCE5(rdev))
459 return 8192 * 2;
460 else
461 return 7680 * 2;
462 case 3:
463 case 7:
464 if (ASIC_IS_DCE5(rdev))
465 return 2048 * 2;
466 else
467 return 1920 * 2;
468 }
469 }
470
471 /* controller not enabled, so no lb used */
472 return 0;
473}
474
475static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
476{
477 u32 tmp = RREG32(MC_SHARED_CHMAP);
478
479 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
480 case 0:
481 default:
482 return 1;
483 case 1:
484 return 2;
485 case 2:
486 return 4;
487 case 3:
488 return 8;
489 }
490}
491
492struct evergreen_wm_params {
493 u32 dram_channels; /* number of dram channels */
494 u32 yclk; /* bandwidth per dram data pin in kHz */
495 u32 sclk; /* engine clock in kHz */
496 u32 disp_clk; /* display clock in kHz */
497 u32 src_width; /* viewport width */
498 u32 active_time; /* active display time in ns */
499 u32 blank_time; /* blank time in ns */
500 bool interlaced; /* mode is interlaced */
501 fixed20_12 vsc; /* vertical scale ratio */
502 u32 num_heads; /* number of active crtcs */
503 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
504 u32 lb_size; /* line buffer allocated to pipe */
505 u32 vtaps; /* vertical scaler taps */
506};
507
508static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
509{
510 /* Calculate DRAM Bandwidth and the part allocated to display. */
511 fixed20_12 dram_efficiency; /* 0.7 */
512 fixed20_12 yclk, dram_channels, bandwidth;
513 fixed20_12 a;
514
515 a.full = dfixed_const(1000);
516 yclk.full = dfixed_const(wm->yclk);
517 yclk.full = dfixed_div(yclk, a);
518 dram_channels.full = dfixed_const(wm->dram_channels * 4);
519 a.full = dfixed_const(10);
520 dram_efficiency.full = dfixed_const(7);
521 dram_efficiency.full = dfixed_div(dram_efficiency, a);
522 bandwidth.full = dfixed_mul(dram_channels, yclk);
523 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
524
525 return dfixed_trunc(bandwidth);
526}
527
528static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
529{
530 /* Calculate DRAM Bandwidth and the part allocated to display. */
531 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
532 fixed20_12 yclk, dram_channels, bandwidth;
533 fixed20_12 a;
534
535 a.full = dfixed_const(1000);
536 yclk.full = dfixed_const(wm->yclk);
537 yclk.full = dfixed_div(yclk, a);
538 dram_channels.full = dfixed_const(wm->dram_channels * 4);
539 a.full = dfixed_const(10);
540 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
541 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
542 bandwidth.full = dfixed_mul(dram_channels, yclk);
543 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
544
545 return dfixed_trunc(bandwidth);
546}
547
548static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
549{
550 /* Calculate the display Data return Bandwidth */
551 fixed20_12 return_efficiency; /* 0.8 */
552 fixed20_12 sclk, bandwidth;
553 fixed20_12 a;
554
555 a.full = dfixed_const(1000);
556 sclk.full = dfixed_const(wm->sclk);
557 sclk.full = dfixed_div(sclk, a);
558 a.full = dfixed_const(10);
559 return_efficiency.full = dfixed_const(8);
560 return_efficiency.full = dfixed_div(return_efficiency, a);
561 a.full = dfixed_const(32);
562 bandwidth.full = dfixed_mul(a, sclk);
563 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
564
565 return dfixed_trunc(bandwidth);
566}
567
568static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
569{
570 /* Calculate the DMIF Request Bandwidth */
571 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
572 fixed20_12 disp_clk, bandwidth;
573 fixed20_12 a;
574
575 a.full = dfixed_const(1000);
576 disp_clk.full = dfixed_const(wm->disp_clk);
577 disp_clk.full = dfixed_div(disp_clk, a);
578 a.full = dfixed_const(10);
579 disp_clk_request_efficiency.full = dfixed_const(8);
580 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
581 a.full = dfixed_const(32);
582 bandwidth.full = dfixed_mul(a, disp_clk);
583 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
584
585 return dfixed_trunc(bandwidth);
586}
587
588static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
589{
590 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
591 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
592 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
593 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
594
595 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
596}
597
598static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
599{
600 /* Calculate the display mode Average Bandwidth
601 * DisplayMode should contain the source and destination dimensions,
602 * timing, etc.
603 */
604 fixed20_12 bpp;
605 fixed20_12 line_time;
606 fixed20_12 src_width;
607 fixed20_12 bandwidth;
608 fixed20_12 a;
609
610 a.full = dfixed_const(1000);
611 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
612 line_time.full = dfixed_div(line_time, a);
613 bpp.full = dfixed_const(wm->bytes_per_pixel);
614 src_width.full = dfixed_const(wm->src_width);
615 bandwidth.full = dfixed_mul(src_width, bpp);
616 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
617 bandwidth.full = dfixed_div(bandwidth, line_time);
618
619 return dfixed_trunc(bandwidth);
620}
621
622static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
623{
624 /* First calcualte the latency in ns */
625 u32 mc_latency = 2000; /* 2000 ns. */
626 u32 available_bandwidth = evergreen_available_bandwidth(wm);
627 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
628 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
629 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
630 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
631 (wm->num_heads * cursor_line_pair_return_time);
632 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
633 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
634 fixed20_12 a, b, c;
635
636 if (wm->num_heads == 0)
637 return 0;
638
639 a.full = dfixed_const(2);
640 b.full = dfixed_const(1);
641 if ((wm->vsc.full > a.full) ||
642 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
643 (wm->vtaps >= 5) ||
644 ((wm->vsc.full >= a.full) && wm->interlaced))
645 max_src_lines_per_dst_line = 4;
646 else
647 max_src_lines_per_dst_line = 2;
648
649 a.full = dfixed_const(available_bandwidth);
650 b.full = dfixed_const(wm->num_heads);
651 a.full = dfixed_div(a, b);
652
653 b.full = dfixed_const(1000);
654 c.full = dfixed_const(wm->disp_clk);
655 b.full = dfixed_div(c, b);
656 c.full = dfixed_const(wm->bytes_per_pixel);
657 b.full = dfixed_mul(b, c);
658
659 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
660
661 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
662 b.full = dfixed_const(1000);
663 c.full = dfixed_const(lb_fill_bw);
664 b.full = dfixed_div(c, b);
665 a.full = dfixed_div(a, b);
666 line_fill_time = dfixed_trunc(a);
667
668 if (line_fill_time < wm->active_time)
669 return latency;
670 else
671 return latency + (line_fill_time - wm->active_time);
672
673}
674
675static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
676{
677 if (evergreen_average_bandwidth(wm) <=
678 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
679 return true;
680 else
681 return false;
682};
683
684static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
685{
686 if (evergreen_average_bandwidth(wm) <=
687 (evergreen_available_bandwidth(wm) / wm->num_heads))
688 return true;
689 else
690 return false;
691};
692
693static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
694{
695 u32 lb_partitions = wm->lb_size / wm->src_width;
696 u32 line_time = wm->active_time + wm->blank_time;
697 u32 latency_tolerant_lines;
698 u32 latency_hiding;
699 fixed20_12 a;
700
701 a.full = dfixed_const(1);
702 if (wm->vsc.full > a.full)
703 latency_tolerant_lines = 1;
704 else {
705 if (lb_partitions <= (wm->vtaps + 1))
706 latency_tolerant_lines = 1;
707 else
708 latency_tolerant_lines = 2;
709 }
710
711 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
712
713 if (evergreen_latency_watermark(wm) <= latency_hiding)
714 return true;
715 else
716 return false;
717}
718
719static void evergreen_program_watermarks(struct radeon_device *rdev,
720 struct radeon_crtc *radeon_crtc,
721 u32 lb_size, u32 num_heads)
722{
723 struct drm_display_mode *mode = &radeon_crtc->base.mode;
724 struct evergreen_wm_params wm;
725 u32 pixel_period;
726 u32 line_time = 0;
727 u32 latency_watermark_a = 0, latency_watermark_b = 0;
728 u32 priority_a_mark = 0, priority_b_mark = 0;
729 u32 priority_a_cnt = PRIORITY_OFF;
730 u32 priority_b_cnt = PRIORITY_OFF;
731 u32 pipe_offset = radeon_crtc->crtc_id * 16;
732 u32 tmp, arb_control3;
733 fixed20_12 a, b, c;
734
735 if (radeon_crtc->base.enabled && num_heads && mode) {
736 pixel_period = 1000000 / (u32)mode->clock;
737 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
738 priority_a_cnt = 0;
739 priority_b_cnt = 0;
740
741 wm.yclk = rdev->pm.current_mclk * 10;
742 wm.sclk = rdev->pm.current_sclk * 10;
743 wm.disp_clk = mode->clock;
744 wm.src_width = mode->crtc_hdisplay;
745 wm.active_time = mode->crtc_hdisplay * pixel_period;
746 wm.blank_time = line_time - wm.active_time;
747 wm.interlaced = false;
748 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
749 wm.interlaced = true;
750 wm.vsc = radeon_crtc->vsc;
751 wm.vtaps = 1;
752 if (radeon_crtc->rmx_type != RMX_OFF)
753 wm.vtaps = 2;
754 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
755 wm.lb_size = lb_size;
756 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
757 wm.num_heads = num_heads;
758
759 /* set for high clocks */
760 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
761 /* set for low clocks */
762 /* wm.yclk = low clk; wm.sclk = low clk */
763 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
764
765 /* possibly force display priority to high */
766 /* should really do this at mode validation time... */
767 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
768 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
769 !evergreen_check_latency_hiding(&wm) ||
770 (rdev->disp_priority == 2)) {
771 DRM_DEBUG_KMS("force priority to high\n");
772 priority_a_cnt |= PRIORITY_ALWAYS_ON;
773 priority_b_cnt |= PRIORITY_ALWAYS_ON;
774 }
775
776 a.full = dfixed_const(1000);
777 b.full = dfixed_const(mode->clock);
778 b.full = dfixed_div(b, a);
779 c.full = dfixed_const(latency_watermark_a);
780 c.full = dfixed_mul(c, b);
781 c.full = dfixed_mul(c, radeon_crtc->hsc);
782 c.full = dfixed_div(c, a);
783 a.full = dfixed_const(16);
784 c.full = dfixed_div(c, a);
785 priority_a_mark = dfixed_trunc(c);
786 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
787
788 a.full = dfixed_const(1000);
789 b.full = dfixed_const(mode->clock);
790 b.full = dfixed_div(b, a);
791 c.full = dfixed_const(latency_watermark_b);
792 c.full = dfixed_mul(c, b);
793 c.full = dfixed_mul(c, radeon_crtc->hsc);
794 c.full = dfixed_div(c, a);
795 a.full = dfixed_const(16);
796 c.full = dfixed_div(c, a);
797 priority_b_mark = dfixed_trunc(c);
798 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
799 }
800
801 /* select wm A */
802 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
803 tmp = arb_control3;
804 tmp &= ~LATENCY_WATERMARK_MASK(3);
805 tmp |= LATENCY_WATERMARK_MASK(1);
806 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
807 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
808 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
809 LATENCY_HIGH_WATERMARK(line_time)));
810 /* select wm B */
811 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
812 tmp &= ~LATENCY_WATERMARK_MASK(3);
813 tmp |= LATENCY_WATERMARK_MASK(2);
814 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
815 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
816 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
817 LATENCY_HIGH_WATERMARK(line_time)));
818 /* restore original selection */
819 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
820
821 /* write the priority marks */
822 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
823 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
824
825}
826
827void evergreen_bandwidth_update(struct radeon_device *rdev)
828{
829 struct drm_display_mode *mode0 = NULL;
830 struct drm_display_mode *mode1 = NULL;
831 u32 num_heads = 0, lb_size;
832 int i;
833
834 radeon_update_display_priority(rdev);
835
836 for (i = 0; i < rdev->num_crtc; i++) {
837 if (rdev->mode_info.crtcs[i]->base.enabled)
838 num_heads++;
839 }
840 for (i = 0; i < rdev->num_crtc; i += 2) {
841 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
842 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
843 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
844 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
845 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
846 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
847 }
848}
849
850int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
851{
852 unsigned i;
853 u32 tmp;
854
855 for (i = 0; i < rdev->usec_timeout; i++) {
856 /* read MC_STATUS */
857 tmp = RREG32(SRBM_STATUS) & 0x1F00;
858 if (!tmp)
859 return 0;
860 udelay(1);
861 }
862 return -1;
863}
864
865/*
866 * GART
867 */
868void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
869{
870 unsigned i;
871 u32 tmp;
872
873 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
874
875 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
876 for (i = 0; i < rdev->usec_timeout; i++) {
877 /* read MC_STATUS */
878 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
879 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
880 if (tmp == 2) {
881 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
882 return;
883 }
884 if (tmp) {
885 return;
886 }
887 udelay(1);
888 }
889}
890
891int evergreen_pcie_gart_enable(struct radeon_device *rdev)
892{
893 u32 tmp;
894 int r;
895
896 if (rdev->gart.table.vram.robj == NULL) {
897 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
898 return -EINVAL;
899 }
900 r = radeon_gart_table_vram_pin(rdev);
901 if (r)
902 return r;
903 radeon_gart_restore(rdev);
904 /* Setup L2 cache */
905 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
906 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
907 EFFECTIVE_L2_QUEUE_SIZE(7));
908 WREG32(VM_L2_CNTL2, 0);
909 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
910 /* Setup TLB control */
911 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
912 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
913 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
914 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
915 if (rdev->flags & RADEON_IS_IGP) {
916 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
917 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
918 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
919 } else {
920 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
921 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
922 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
923 }
924 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
925 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
926 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
927 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
928 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
929 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
930 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
931 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
932 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
933 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
934 (u32)(rdev->dummy_page.addr >> 12));
935 WREG32(VM_CONTEXT1_CNTL, 0);
936
937 evergreen_pcie_gart_tlb_flush(rdev);
938 rdev->gart.ready = true;
939 return 0;
940}
941
942void evergreen_pcie_gart_disable(struct radeon_device *rdev)
943{
944 u32 tmp;
945 int r;
946
947 /* Disable all tables */
948 WREG32(VM_CONTEXT0_CNTL, 0);
949 WREG32(VM_CONTEXT1_CNTL, 0);
950
951 /* Setup L2 cache */
952 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
953 EFFECTIVE_L2_QUEUE_SIZE(7));
954 WREG32(VM_L2_CNTL2, 0);
955 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
956 /* Setup TLB control */
957 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
958 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
959 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
960 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
961 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
962 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
963 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
964 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
965 if (rdev->gart.table.vram.robj) {
966 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
967 if (likely(r == 0)) {
968 radeon_bo_kunmap(rdev->gart.table.vram.robj);
969 radeon_bo_unpin(rdev->gart.table.vram.robj);
970 radeon_bo_unreserve(rdev->gart.table.vram.robj);
971 }
972 }
973}
974
975void evergreen_pcie_gart_fini(struct radeon_device *rdev)
976{
977 evergreen_pcie_gart_disable(rdev);
978 radeon_gart_table_vram_free(rdev);
979 radeon_gart_fini(rdev);
980}
981
982
983void evergreen_agp_enable(struct radeon_device *rdev)
984{
985 u32 tmp;
986
987 /* Setup L2 cache */
988 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
989 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
990 EFFECTIVE_L2_QUEUE_SIZE(7));
991 WREG32(VM_L2_CNTL2, 0);
992 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
993 /* Setup TLB control */
994 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
995 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
996 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
997 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
998 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
999 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1000 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1001 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1002 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1003 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1004 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1005 WREG32(VM_CONTEXT0_CNTL, 0);
1006 WREG32(VM_CONTEXT1_CNTL, 0);
1007}
1008
1009void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1010{
1011 save->vga_control[0] = RREG32(D1VGA_CONTROL);
1012 save->vga_control[1] = RREG32(D2VGA_CONTROL);
1013 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1014 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1015 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
1016 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
1017 if (rdev->num_crtc >= 4) {
1018 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
1019 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
1020 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
1021 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
1022 }
1023 if (rdev->num_crtc >= 6) {
1024 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1025 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
1026 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
1027 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
1028 }
1029
1030 /* Stop all video */
1031 WREG32(VGA_RENDER_CONTROL, 0);
1032 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1033 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1034 if (rdev->num_crtc >= 4) {
1035 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1036 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1037 }
1038 if (rdev->num_crtc >= 6) {
1039 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1040 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1041 }
1042 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1043 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1044 if (rdev->num_crtc >= 4) {
1045 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1046 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1047 }
1048 if (rdev->num_crtc >= 6) {
1049 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1050 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1051 }
1052 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1053 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1054 if (rdev->num_crtc >= 4) {
1055 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1056 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1057 }
1058 if (rdev->num_crtc >= 6) {
1059 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1060 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1061 }
1062
1063 WREG32(D1VGA_CONTROL, 0);
1064 WREG32(D2VGA_CONTROL, 0);
1065 if (rdev->num_crtc >= 4) {
1066 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1067 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1068 }
1069 if (rdev->num_crtc >= 6) {
1070 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1071 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1072 }
1073}
1074
1075void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1076{
1077 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1078 upper_32_bits(rdev->mc.vram_start));
1079 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1080 upper_32_bits(rdev->mc.vram_start));
1081 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1082 (u32)rdev->mc.vram_start);
1083 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1084 (u32)rdev->mc.vram_start);
1085
1086 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1087 upper_32_bits(rdev->mc.vram_start));
1088 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1089 upper_32_bits(rdev->mc.vram_start));
1090 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1091 (u32)rdev->mc.vram_start);
1092 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1093 (u32)rdev->mc.vram_start);
1094
1095 if (rdev->num_crtc >= 4) {
1096 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1097 upper_32_bits(rdev->mc.vram_start));
1098 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1099 upper_32_bits(rdev->mc.vram_start));
1100 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1101 (u32)rdev->mc.vram_start);
1102 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1103 (u32)rdev->mc.vram_start);
1104
1105 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1106 upper_32_bits(rdev->mc.vram_start));
1107 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1108 upper_32_bits(rdev->mc.vram_start));
1109 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1110 (u32)rdev->mc.vram_start);
1111 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1112 (u32)rdev->mc.vram_start);
1113 }
1114 if (rdev->num_crtc >= 6) {
1115 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1116 upper_32_bits(rdev->mc.vram_start));
1117 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1118 upper_32_bits(rdev->mc.vram_start));
1119 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1120 (u32)rdev->mc.vram_start);
1121 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1122 (u32)rdev->mc.vram_start);
1123
1124 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1125 upper_32_bits(rdev->mc.vram_start));
1126 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1127 upper_32_bits(rdev->mc.vram_start));
1128 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1129 (u32)rdev->mc.vram_start);
1130 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1131 (u32)rdev->mc.vram_start);
1132 }
1133
1134 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1135 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1136 /* Unlock host access */
1137 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1138 mdelay(1);
1139 /* Restore video state */
1140 WREG32(D1VGA_CONTROL, save->vga_control[0]);
1141 WREG32(D2VGA_CONTROL, save->vga_control[1]);
1142 if (rdev->num_crtc >= 4) {
1143 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1144 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1145 }
1146 if (rdev->num_crtc >= 6) {
1147 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1148 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1149 }
1150 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1151 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1152 if (rdev->num_crtc >= 4) {
1153 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1154 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1155 }
1156 if (rdev->num_crtc >= 6) {
1157 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1158 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1159 }
1160 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1161 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1162 if (rdev->num_crtc >= 4) {
1163 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1164 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1165 }
1166 if (rdev->num_crtc >= 6) {
1167 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1168 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1169 }
1170 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1171 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1172 if (rdev->num_crtc >= 4) {
1173 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1174 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1175 }
1176 if (rdev->num_crtc >= 6) {
1177 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1178 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1179 }
1180 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1181}
1182
1183void evergreen_mc_program(struct radeon_device *rdev)
1184{
1185 struct evergreen_mc_save save;
1186 u32 tmp;
1187 int i, j;
1188
1189 /* Initialize HDP */
1190 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1191 WREG32((0x2c14 + j), 0x00000000);
1192 WREG32((0x2c18 + j), 0x00000000);
1193 WREG32((0x2c1c + j), 0x00000000);
1194 WREG32((0x2c20 + j), 0x00000000);
1195 WREG32((0x2c24 + j), 0x00000000);
1196 }
1197 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1198
1199 evergreen_mc_stop(rdev, &save);
1200 if (evergreen_mc_wait_for_idle(rdev)) {
1201 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1202 }
1203 /* Lockout access through VGA aperture*/
1204 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1205 /* Update configuration */
1206 if (rdev->flags & RADEON_IS_AGP) {
1207 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1208 /* VRAM before AGP */
1209 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1210 rdev->mc.vram_start >> 12);
1211 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1212 rdev->mc.gtt_end >> 12);
1213 } else {
1214 /* VRAM after AGP */
1215 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1216 rdev->mc.gtt_start >> 12);
1217 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1218 rdev->mc.vram_end >> 12);
1219 }
1220 } else {
1221 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1222 rdev->mc.vram_start >> 12);
1223 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1224 rdev->mc.vram_end >> 12);
1225 }
1226 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1227 if (rdev->flags & RADEON_IS_IGP) {
1228 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1229 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1230 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1231 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1232 }
1233 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1234 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1235 WREG32(MC_VM_FB_LOCATION, tmp);
1236 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1237 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1238 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1239 if (rdev->flags & RADEON_IS_AGP) {
1240 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1241 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1242 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1243 } else {
1244 WREG32(MC_VM_AGP_BASE, 0);
1245 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1246 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1247 }
1248 if (evergreen_mc_wait_for_idle(rdev)) {
1249 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1250 }
1251 evergreen_mc_resume(rdev, &save);
1252 /* we need to own VRAM, so turn off the VGA renderer here
1253 * to stop it overwriting our objects */
1254 rv515_vga_render_disable(rdev);
1255}
1256
1257/*
1258 * CP.
1259 */
1260void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1261{
1262 /* set to DX10/11 mode */
1263 radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
1264 radeon_ring_write(rdev, 1);
1265 /* FIXME: implement */
1266 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1267 radeon_ring_write(rdev,
1268#ifdef __BIG_ENDIAN
1269 (2 << 0) |
1270#endif
1271 (ib->gpu_addr & 0xFFFFFFFC));
1272 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1273 radeon_ring_write(rdev, ib->length_dw);
1274}
1275
1276
1277static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1278{
1279 const __be32 *fw_data;
1280 int i;
1281
1282 if (!rdev->me_fw || !rdev->pfp_fw)
1283 return -EINVAL;
1284
1285 r700_cp_stop(rdev);
1286 WREG32(CP_RB_CNTL,
1287#ifdef __BIG_ENDIAN
1288 BUF_SWAP_32BIT |
1289#endif
1290 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1291
1292 fw_data = (const __be32 *)rdev->pfp_fw->data;
1293 WREG32(CP_PFP_UCODE_ADDR, 0);
1294 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1295 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1296 WREG32(CP_PFP_UCODE_ADDR, 0);
1297
1298 fw_data = (const __be32 *)rdev->me_fw->data;
1299 WREG32(CP_ME_RAM_WADDR, 0);
1300 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1301 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1302
1303 WREG32(CP_PFP_UCODE_ADDR, 0);
1304 WREG32(CP_ME_RAM_WADDR, 0);
1305 WREG32(CP_ME_RAM_RADDR, 0);
1306 return 0;
1307}
1308
1309static int evergreen_cp_start(struct radeon_device *rdev)
1310{
1311 int r, i;
1312 uint32_t cp_me;
1313
1314 r = radeon_ring_lock(rdev, 7);
1315 if (r) {
1316 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1317 return r;
1318 }
1319 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1320 radeon_ring_write(rdev, 0x1);
1321 radeon_ring_write(rdev, 0x0);
1322 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1323 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1324 radeon_ring_write(rdev, 0);
1325 radeon_ring_write(rdev, 0);
1326 radeon_ring_unlock_commit(rdev);
1327
1328 cp_me = 0xff;
1329 WREG32(CP_ME_CNTL, cp_me);
1330
1331 r = radeon_ring_lock(rdev, evergreen_default_size + 19);
1332 if (r) {
1333 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1334 return r;
1335 }
1336
1337 /* setup clear context state */
1338 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1339 radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1340
1341 for (i = 0; i < evergreen_default_size; i++)
1342 radeon_ring_write(rdev, evergreen_default_state[i]);
1343
1344 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1345 radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1346
1347 /* set clear context state */
1348 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1349 radeon_ring_write(rdev, 0);
1350
1351 /* SQ_VTX_BASE_VTX_LOC */
1352 radeon_ring_write(rdev, 0xc0026f00);
1353 radeon_ring_write(rdev, 0x00000000);
1354 radeon_ring_write(rdev, 0x00000000);
1355 radeon_ring_write(rdev, 0x00000000);
1356
1357 /* Clear consts */
1358 radeon_ring_write(rdev, 0xc0036f00);
1359 radeon_ring_write(rdev, 0x00000bc4);
1360 radeon_ring_write(rdev, 0xffffffff);
1361 radeon_ring_write(rdev, 0xffffffff);
1362 radeon_ring_write(rdev, 0xffffffff);
1363
1364 radeon_ring_write(rdev, 0xc0026900);
1365 radeon_ring_write(rdev, 0x00000316);
1366 radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1367 radeon_ring_write(rdev, 0x00000010); /* */
1368
1369 radeon_ring_unlock_commit(rdev);
1370
1371 return 0;
1372}
1373
1374int evergreen_cp_resume(struct radeon_device *rdev)
1375{
1376 u32 tmp;
1377 u32 rb_bufsz;
1378 int r;
1379
1380 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1381 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1382 SOFT_RESET_PA |
1383 SOFT_RESET_SH |
1384 SOFT_RESET_VGT |
1385 SOFT_RESET_SPI |
1386 SOFT_RESET_SX));
1387 RREG32(GRBM_SOFT_RESET);
1388 mdelay(15);
1389 WREG32(GRBM_SOFT_RESET, 0);
1390 RREG32(GRBM_SOFT_RESET);
1391
1392 /* Set ring buffer size */
1393 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1394 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1395#ifdef __BIG_ENDIAN
1396 tmp |= BUF_SWAP_32BIT;
1397#endif
1398 WREG32(CP_RB_CNTL, tmp);
1399 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1400
1401 /* Set the write pointer delay */
1402 WREG32(CP_RB_WPTR_DELAY, 0);
1403
1404 /* Initialize the ring buffer's read and write pointers */
1405 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1406 WREG32(CP_RB_RPTR_WR, 0);
1407 rdev->cp.wptr = 0;
1408 WREG32(CP_RB_WPTR, rdev->cp.wptr);
1409
1410 /* set the wb address wether it's enabled or not */
1411 WREG32(CP_RB_RPTR_ADDR,
1412 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1413 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1414 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1415
1416 if (rdev->wb.enabled)
1417 WREG32(SCRATCH_UMSK, 0xff);
1418 else {
1419 tmp |= RB_NO_UPDATE;
1420 WREG32(SCRATCH_UMSK, 0);
1421 }
1422
1423 mdelay(1);
1424 WREG32(CP_RB_CNTL, tmp);
1425
1426 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1427 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1428
1429 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1430
1431 evergreen_cp_start(rdev);
1432 rdev->cp.ready = true;
1433 r = radeon_ring_test(rdev);
1434 if (r) {
1435 rdev->cp.ready = false;
1436 return r;
1437 }
1438 return 0;
1439}
1440
1441/*
1442 * Core functions
1443 */
1444static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1445 u32 num_tile_pipes,
1446 u32 num_backends,
1447 u32 backend_disable_mask)
1448{
1449 u32 backend_map = 0;
1450 u32 enabled_backends_mask = 0;
1451 u32 enabled_backends_count = 0;
1452 u32 cur_pipe;
1453 u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1454 u32 cur_backend = 0;
1455 u32 i;
1456 bool force_no_swizzle;
1457
1458 if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1459 num_tile_pipes = EVERGREEN_MAX_PIPES;
1460 if (num_tile_pipes < 1)
1461 num_tile_pipes = 1;
1462 if (num_backends > EVERGREEN_MAX_BACKENDS)
1463 num_backends = EVERGREEN_MAX_BACKENDS;
1464 if (num_backends < 1)
1465 num_backends = 1;
1466
1467 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1468 if (((backend_disable_mask >> i) & 1) == 0) {
1469 enabled_backends_mask |= (1 << i);
1470 ++enabled_backends_count;
1471 }
1472 if (enabled_backends_count == num_backends)
1473 break;
1474 }
1475
1476 if (enabled_backends_count == 0) {
1477 enabled_backends_mask = 1;
1478 enabled_backends_count = 1;
1479 }
1480
1481 if (enabled_backends_count != num_backends)
1482 num_backends = enabled_backends_count;
1483
1484 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1485 switch (rdev->family) {
1486 case CHIP_CEDAR:
1487 case CHIP_REDWOOD:
1488 case CHIP_PALM:
1489 case CHIP_SUMO:
1490 case CHIP_SUMO2:
1491 case CHIP_TURKS:
1492 case CHIP_CAICOS:
1493 force_no_swizzle = false;
1494 break;
1495 case CHIP_CYPRESS:
1496 case CHIP_HEMLOCK:
1497 case CHIP_JUNIPER:
1498 case CHIP_BARTS:
1499 default:
1500 force_no_swizzle = true;
1501 break;
1502 }
1503 if (force_no_swizzle) {
1504 bool last_backend_enabled = false;
1505
1506 force_no_swizzle = false;
1507 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1508 if (((enabled_backends_mask >> i) & 1) == 1) {
1509 if (last_backend_enabled)
1510 force_no_swizzle = true;
1511 last_backend_enabled = true;
1512 } else
1513 last_backend_enabled = false;
1514 }
1515 }
1516
1517 switch (num_tile_pipes) {
1518 case 1:
1519 case 3:
1520 case 5:
1521 case 7:
1522 DRM_ERROR("odd number of pipes!\n");
1523 break;
1524 case 2:
1525 swizzle_pipe[0] = 0;
1526 swizzle_pipe[1] = 1;
1527 break;
1528 case 4:
1529 if (force_no_swizzle) {
1530 swizzle_pipe[0] = 0;
1531 swizzle_pipe[1] = 1;
1532 swizzle_pipe[2] = 2;
1533 swizzle_pipe[3] = 3;
1534 } else {
1535 swizzle_pipe[0] = 0;
1536 swizzle_pipe[1] = 2;
1537 swizzle_pipe[2] = 1;
1538 swizzle_pipe[3] = 3;
1539 }
1540 break;
1541 case 6:
1542 if (force_no_swizzle) {
1543 swizzle_pipe[0] = 0;
1544 swizzle_pipe[1] = 1;
1545 swizzle_pipe[2] = 2;
1546 swizzle_pipe[3] = 3;
1547 swizzle_pipe[4] = 4;
1548 swizzle_pipe[5] = 5;
1549 } else {
1550 swizzle_pipe[0] = 0;
1551 swizzle_pipe[1] = 2;
1552 swizzle_pipe[2] = 4;
1553 swizzle_pipe[3] = 1;
1554 swizzle_pipe[4] = 3;
1555 swizzle_pipe[5] = 5;
1556 }
1557 break;
1558 case 8:
1559 if (force_no_swizzle) {
1560 swizzle_pipe[0] = 0;
1561 swizzle_pipe[1] = 1;
1562 swizzle_pipe[2] = 2;
1563 swizzle_pipe[3] = 3;
1564 swizzle_pipe[4] = 4;
1565 swizzle_pipe[5] = 5;
1566 swizzle_pipe[6] = 6;
1567 swizzle_pipe[7] = 7;
1568 } else {
1569 swizzle_pipe[0] = 0;
1570 swizzle_pipe[1] = 2;
1571 swizzle_pipe[2] = 4;
1572 swizzle_pipe[3] = 6;
1573 swizzle_pipe[4] = 1;
1574 swizzle_pipe[5] = 3;
1575 swizzle_pipe[6] = 5;
1576 swizzle_pipe[7] = 7;
1577 }
1578 break;
1579 }
1580
1581 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1582 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1583 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1584
1585 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1586
1587 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1588 }
1589
1590 return backend_map;
1591}
1592
1593static void evergreen_gpu_init(struct radeon_device *rdev)
1594{
1595 u32 cc_rb_backend_disable = 0;
1596 u32 cc_gc_shader_pipe_config;
1597 u32 gb_addr_config = 0;
1598 u32 mc_shared_chmap, mc_arb_ramcfg;
1599 u32 gb_backend_map;
1600 u32 grbm_gfx_index;
1601 u32 sx_debug_1;
1602 u32 smx_dc_ctl0;
1603 u32 sq_config;
1604 u32 sq_lds_resource_mgmt;
1605 u32 sq_gpr_resource_mgmt_1;
1606 u32 sq_gpr_resource_mgmt_2;
1607 u32 sq_gpr_resource_mgmt_3;
1608 u32 sq_thread_resource_mgmt;
1609 u32 sq_thread_resource_mgmt_2;
1610 u32 sq_stack_resource_mgmt_1;
1611 u32 sq_stack_resource_mgmt_2;
1612 u32 sq_stack_resource_mgmt_3;
1613 u32 vgt_cache_invalidation;
1614 u32 hdp_host_path_cntl, tmp;
1615 int i, j, num_shader_engines, ps_thread_count;
1616
1617 switch (rdev->family) {
1618 case CHIP_CYPRESS:
1619 case CHIP_HEMLOCK:
1620 rdev->config.evergreen.num_ses = 2;
1621 rdev->config.evergreen.max_pipes = 4;
1622 rdev->config.evergreen.max_tile_pipes = 8;
1623 rdev->config.evergreen.max_simds = 10;
1624 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1625 rdev->config.evergreen.max_gprs = 256;
1626 rdev->config.evergreen.max_threads = 248;
1627 rdev->config.evergreen.max_gs_threads = 32;
1628 rdev->config.evergreen.max_stack_entries = 512;
1629 rdev->config.evergreen.sx_num_of_sets = 4;
1630 rdev->config.evergreen.sx_max_export_size = 256;
1631 rdev->config.evergreen.sx_max_export_pos_size = 64;
1632 rdev->config.evergreen.sx_max_export_smx_size = 192;
1633 rdev->config.evergreen.max_hw_contexts = 8;
1634 rdev->config.evergreen.sq_num_cf_insts = 2;
1635
1636 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1637 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1638 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1639 break;
1640 case CHIP_JUNIPER:
1641 rdev->config.evergreen.num_ses = 1;
1642 rdev->config.evergreen.max_pipes = 4;
1643 rdev->config.evergreen.max_tile_pipes = 4;
1644 rdev->config.evergreen.max_simds = 10;
1645 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1646 rdev->config.evergreen.max_gprs = 256;
1647 rdev->config.evergreen.max_threads = 248;
1648 rdev->config.evergreen.max_gs_threads = 32;
1649 rdev->config.evergreen.max_stack_entries = 512;
1650 rdev->config.evergreen.sx_num_of_sets = 4;
1651 rdev->config.evergreen.sx_max_export_size = 256;
1652 rdev->config.evergreen.sx_max_export_pos_size = 64;
1653 rdev->config.evergreen.sx_max_export_smx_size = 192;
1654 rdev->config.evergreen.max_hw_contexts = 8;
1655 rdev->config.evergreen.sq_num_cf_insts = 2;
1656
1657 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1658 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1659 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1660 break;
1661 case CHIP_REDWOOD:
1662 rdev->config.evergreen.num_ses = 1;
1663 rdev->config.evergreen.max_pipes = 4;
1664 rdev->config.evergreen.max_tile_pipes = 4;
1665 rdev->config.evergreen.max_simds = 5;
1666 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1667 rdev->config.evergreen.max_gprs = 256;
1668 rdev->config.evergreen.max_threads = 248;
1669 rdev->config.evergreen.max_gs_threads = 32;
1670 rdev->config.evergreen.max_stack_entries = 256;
1671 rdev->config.evergreen.sx_num_of_sets = 4;
1672 rdev->config.evergreen.sx_max_export_size = 256;
1673 rdev->config.evergreen.sx_max_export_pos_size = 64;
1674 rdev->config.evergreen.sx_max_export_smx_size = 192;
1675 rdev->config.evergreen.max_hw_contexts = 8;
1676 rdev->config.evergreen.sq_num_cf_insts = 2;
1677
1678 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1679 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1680 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1681 break;
1682 case CHIP_CEDAR:
1683 default:
1684 rdev->config.evergreen.num_ses = 1;
1685 rdev->config.evergreen.max_pipes = 2;
1686 rdev->config.evergreen.max_tile_pipes = 2;
1687 rdev->config.evergreen.max_simds = 2;
1688 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1689 rdev->config.evergreen.max_gprs = 256;
1690 rdev->config.evergreen.max_threads = 192;
1691 rdev->config.evergreen.max_gs_threads = 16;
1692 rdev->config.evergreen.max_stack_entries = 256;
1693 rdev->config.evergreen.sx_num_of_sets = 4;
1694 rdev->config.evergreen.sx_max_export_size = 128;
1695 rdev->config.evergreen.sx_max_export_pos_size = 32;
1696 rdev->config.evergreen.sx_max_export_smx_size = 96;
1697 rdev->config.evergreen.max_hw_contexts = 4;
1698 rdev->config.evergreen.sq_num_cf_insts = 1;
1699
1700 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1701 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1702 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1703 break;
1704 case CHIP_PALM:
1705 rdev->config.evergreen.num_ses = 1;
1706 rdev->config.evergreen.max_pipes = 2;
1707 rdev->config.evergreen.max_tile_pipes = 2;
1708 rdev->config.evergreen.max_simds = 2;
1709 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1710 rdev->config.evergreen.max_gprs = 256;
1711 rdev->config.evergreen.max_threads = 192;
1712 rdev->config.evergreen.max_gs_threads = 16;
1713 rdev->config.evergreen.max_stack_entries = 256;
1714 rdev->config.evergreen.sx_num_of_sets = 4;
1715 rdev->config.evergreen.sx_max_export_size = 128;
1716 rdev->config.evergreen.sx_max_export_pos_size = 32;
1717 rdev->config.evergreen.sx_max_export_smx_size = 96;
1718 rdev->config.evergreen.max_hw_contexts = 4;
1719 rdev->config.evergreen.sq_num_cf_insts = 1;
1720
1721 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1722 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1723 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1724 break;
1725 case CHIP_SUMO:
1726 rdev->config.evergreen.num_ses = 1;
1727 rdev->config.evergreen.max_pipes = 4;
1728 rdev->config.evergreen.max_tile_pipes = 2;
1729 if (rdev->pdev->device == 0x9648)
1730 rdev->config.evergreen.max_simds = 3;
1731 else if ((rdev->pdev->device == 0x9647) ||
1732 (rdev->pdev->device == 0x964a))
1733 rdev->config.evergreen.max_simds = 4;
1734 else
1735 rdev->config.evergreen.max_simds = 5;
1736 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1737 rdev->config.evergreen.max_gprs = 256;
1738 rdev->config.evergreen.max_threads = 248;
1739 rdev->config.evergreen.max_gs_threads = 32;
1740 rdev->config.evergreen.max_stack_entries = 256;
1741 rdev->config.evergreen.sx_num_of_sets = 4;
1742 rdev->config.evergreen.sx_max_export_size = 256;
1743 rdev->config.evergreen.sx_max_export_pos_size = 64;
1744 rdev->config.evergreen.sx_max_export_smx_size = 192;
1745 rdev->config.evergreen.max_hw_contexts = 8;
1746 rdev->config.evergreen.sq_num_cf_insts = 2;
1747
1748 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1749 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1750 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1751 break;
1752 case CHIP_SUMO2:
1753 rdev->config.evergreen.num_ses = 1;
1754 rdev->config.evergreen.max_pipes = 4;
1755 rdev->config.evergreen.max_tile_pipes = 4;
1756 rdev->config.evergreen.max_simds = 2;
1757 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1758 rdev->config.evergreen.max_gprs = 256;
1759 rdev->config.evergreen.max_threads = 248;
1760 rdev->config.evergreen.max_gs_threads = 32;
1761 rdev->config.evergreen.max_stack_entries = 512;
1762 rdev->config.evergreen.sx_num_of_sets = 4;
1763 rdev->config.evergreen.sx_max_export_size = 256;
1764 rdev->config.evergreen.sx_max_export_pos_size = 64;
1765 rdev->config.evergreen.sx_max_export_smx_size = 192;
1766 rdev->config.evergreen.max_hw_contexts = 8;
1767 rdev->config.evergreen.sq_num_cf_insts = 2;
1768
1769 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1770 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1771 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1772 break;
1773 case CHIP_BARTS:
1774 rdev->config.evergreen.num_ses = 2;
1775 rdev->config.evergreen.max_pipes = 4;
1776 rdev->config.evergreen.max_tile_pipes = 8;
1777 rdev->config.evergreen.max_simds = 7;
1778 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1779 rdev->config.evergreen.max_gprs = 256;
1780 rdev->config.evergreen.max_threads = 248;
1781 rdev->config.evergreen.max_gs_threads = 32;
1782 rdev->config.evergreen.max_stack_entries = 512;
1783 rdev->config.evergreen.sx_num_of_sets = 4;
1784 rdev->config.evergreen.sx_max_export_size = 256;
1785 rdev->config.evergreen.sx_max_export_pos_size = 64;
1786 rdev->config.evergreen.sx_max_export_smx_size = 192;
1787 rdev->config.evergreen.max_hw_contexts = 8;
1788 rdev->config.evergreen.sq_num_cf_insts = 2;
1789
1790 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1791 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1792 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1793 break;
1794 case CHIP_TURKS:
1795 rdev->config.evergreen.num_ses = 1;
1796 rdev->config.evergreen.max_pipes = 4;
1797 rdev->config.evergreen.max_tile_pipes = 4;
1798 rdev->config.evergreen.max_simds = 6;
1799 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1800 rdev->config.evergreen.max_gprs = 256;
1801 rdev->config.evergreen.max_threads = 248;
1802 rdev->config.evergreen.max_gs_threads = 32;
1803 rdev->config.evergreen.max_stack_entries = 256;
1804 rdev->config.evergreen.sx_num_of_sets = 4;
1805 rdev->config.evergreen.sx_max_export_size = 256;
1806 rdev->config.evergreen.sx_max_export_pos_size = 64;
1807 rdev->config.evergreen.sx_max_export_smx_size = 192;
1808 rdev->config.evergreen.max_hw_contexts = 8;
1809 rdev->config.evergreen.sq_num_cf_insts = 2;
1810
1811 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1812 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1813 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1814 break;
1815 case CHIP_CAICOS:
1816 rdev->config.evergreen.num_ses = 1;
1817 rdev->config.evergreen.max_pipes = 4;
1818 rdev->config.evergreen.max_tile_pipes = 2;
1819 rdev->config.evergreen.max_simds = 2;
1820 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1821 rdev->config.evergreen.max_gprs = 256;
1822 rdev->config.evergreen.max_threads = 192;
1823 rdev->config.evergreen.max_gs_threads = 16;
1824 rdev->config.evergreen.max_stack_entries = 256;
1825 rdev->config.evergreen.sx_num_of_sets = 4;
1826 rdev->config.evergreen.sx_max_export_size = 128;
1827 rdev->config.evergreen.sx_max_export_pos_size = 32;
1828 rdev->config.evergreen.sx_max_export_smx_size = 96;
1829 rdev->config.evergreen.max_hw_contexts = 4;
1830 rdev->config.evergreen.sq_num_cf_insts = 1;
1831
1832 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1833 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1834 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1835 break;
1836 }
1837
1838 /* Initialize HDP */
1839 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1840 WREG32((0x2c14 + j), 0x00000000);
1841 WREG32((0x2c18 + j), 0x00000000);
1842 WREG32((0x2c1c + j), 0x00000000);
1843 WREG32((0x2c20 + j), 0x00000000);
1844 WREG32((0x2c24 + j), 0x00000000);
1845 }
1846
1847 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1848
1849 evergreen_fix_pci_max_read_req_size(rdev);
1850
1851 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1852
1853 cc_gc_shader_pipe_config |=
1854 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1855 & EVERGREEN_MAX_PIPES_MASK);
1856 cc_gc_shader_pipe_config |=
1857 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1858 & EVERGREEN_MAX_SIMDS_MASK);
1859
1860 cc_rb_backend_disable =
1861 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1862 & EVERGREEN_MAX_BACKENDS_MASK);
1863
1864
1865 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1866 if (rdev->flags & RADEON_IS_IGP)
1867 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1868 else
1869 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1870
1871 switch (rdev->config.evergreen.max_tile_pipes) {
1872 case 1:
1873 default:
1874 gb_addr_config |= NUM_PIPES(0);
1875 break;
1876 case 2:
1877 gb_addr_config |= NUM_PIPES(1);
1878 break;
1879 case 4:
1880 gb_addr_config |= NUM_PIPES(2);
1881 break;
1882 case 8:
1883 gb_addr_config |= NUM_PIPES(3);
1884 break;
1885 }
1886
1887 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1888 gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1889 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1890 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1891 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1892 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1893
1894 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1895 gb_addr_config |= ROW_SIZE(2);
1896 else
1897 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1898
1899 if (rdev->ddev->pdev->device == 0x689e) {
1900 u32 efuse_straps_4;
1901 u32 efuse_straps_3;
1902 u8 efuse_box_bit_131_124;
1903
1904 WREG32(RCU_IND_INDEX, 0x204);
1905 efuse_straps_4 = RREG32(RCU_IND_DATA);
1906 WREG32(RCU_IND_INDEX, 0x203);
1907 efuse_straps_3 = RREG32(RCU_IND_DATA);
1908 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1909
1910 switch(efuse_box_bit_131_124) {
1911 case 0x00:
1912 gb_backend_map = 0x76543210;
1913 break;
1914 case 0x55:
1915 gb_backend_map = 0x77553311;
1916 break;
1917 case 0x56:
1918 gb_backend_map = 0x77553300;
1919 break;
1920 case 0x59:
1921 gb_backend_map = 0x77552211;
1922 break;
1923 case 0x66:
1924 gb_backend_map = 0x77443300;
1925 break;
1926 case 0x99:
1927 gb_backend_map = 0x66552211;
1928 break;
1929 case 0x5a:
1930 gb_backend_map = 0x77552200;
1931 break;
1932 case 0xaa:
1933 gb_backend_map = 0x66442200;
1934 break;
1935 case 0x95:
1936 gb_backend_map = 0x66553311;
1937 break;
1938 default:
1939 DRM_ERROR("bad backend map, using default\n");
1940 gb_backend_map =
1941 evergreen_get_tile_pipe_to_backend_map(rdev,
1942 rdev->config.evergreen.max_tile_pipes,
1943 rdev->config.evergreen.max_backends,
1944 ((EVERGREEN_MAX_BACKENDS_MASK <<
1945 rdev->config.evergreen.max_backends) &
1946 EVERGREEN_MAX_BACKENDS_MASK));
1947 break;
1948 }
1949 } else if (rdev->ddev->pdev->device == 0x68b9) {
1950 u32 efuse_straps_3;
1951 u8 efuse_box_bit_127_124;
1952
1953 WREG32(RCU_IND_INDEX, 0x203);
1954 efuse_straps_3 = RREG32(RCU_IND_DATA);
1955 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
1956
1957 switch(efuse_box_bit_127_124) {
1958 case 0x0:
1959 gb_backend_map = 0x00003210;
1960 break;
1961 case 0x5:
1962 case 0x6:
1963 case 0x9:
1964 case 0xa:
1965 gb_backend_map = 0x00003311;
1966 break;
1967 default:
1968 DRM_ERROR("bad backend map, using default\n");
1969 gb_backend_map =
1970 evergreen_get_tile_pipe_to_backend_map(rdev,
1971 rdev->config.evergreen.max_tile_pipes,
1972 rdev->config.evergreen.max_backends,
1973 ((EVERGREEN_MAX_BACKENDS_MASK <<
1974 rdev->config.evergreen.max_backends) &
1975 EVERGREEN_MAX_BACKENDS_MASK));
1976 break;
1977 }
1978 } else {
1979 switch (rdev->family) {
1980 case CHIP_CYPRESS:
1981 case CHIP_HEMLOCK:
1982 case CHIP_BARTS:
1983 gb_backend_map = 0x66442200;
1984 break;
1985 case CHIP_JUNIPER:
1986 gb_backend_map = 0x00002200;
1987 break;
1988 default:
1989 gb_backend_map =
1990 evergreen_get_tile_pipe_to_backend_map(rdev,
1991 rdev->config.evergreen.max_tile_pipes,
1992 rdev->config.evergreen.max_backends,
1993 ((EVERGREEN_MAX_BACKENDS_MASK <<
1994 rdev->config.evergreen.max_backends) &
1995 EVERGREEN_MAX_BACKENDS_MASK));
1996 }
1997 }
1998
1999 /* setup tiling info dword. gb_addr_config is not adequate since it does
2000 * not have bank info, so create a custom tiling dword.
2001 * bits 3:0 num_pipes
2002 * bits 7:4 num_banks
2003 * bits 11:8 group_size
2004 * bits 15:12 row_size
2005 */
2006 rdev->config.evergreen.tile_config = 0;
2007 switch (rdev->config.evergreen.max_tile_pipes) {
2008 case 1:
2009 default:
2010 rdev->config.evergreen.tile_config |= (0 << 0);
2011 break;
2012 case 2:
2013 rdev->config.evergreen.tile_config |= (1 << 0);
2014 break;
2015 case 4:
2016 rdev->config.evergreen.tile_config |= (2 << 0);
2017 break;
2018 case 8:
2019 rdev->config.evergreen.tile_config |= (3 << 0);
2020 break;
2021 }
2022 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
2023 if (rdev->flags & RADEON_IS_IGP)
2024 rdev->config.evergreen.tile_config |= 1 << 4;
2025 else
2026 rdev->config.evergreen.tile_config |=
2027 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
2028 rdev->config.evergreen.tile_config |=
2029 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
2030 rdev->config.evergreen.tile_config |=
2031 ((gb_addr_config & 0x30000000) >> 28) << 12;
2032
2033 rdev->config.evergreen.backend_map = gb_backend_map;
2034 WREG32(GB_BACKEND_MAP, gb_backend_map);
2035 WREG32(GB_ADDR_CONFIG, gb_addr_config);
2036 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2037 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2038
2039 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
2040 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
2041
2042 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
2043 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
2044 u32 sp = cc_gc_shader_pipe_config;
2045 u32 gfx = grbm_gfx_index | SE_INDEX(i);
2046
2047 if (i == num_shader_engines) {
2048 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
2049 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
2050 }
2051
2052 WREG32(GRBM_GFX_INDEX, gfx);
2053 WREG32(RLC_GFX_INDEX, gfx);
2054
2055 WREG32(CC_RB_BACKEND_DISABLE, rb);
2056 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
2057 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
2058 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
2059 }
2060
2061 grbm_gfx_index |= SE_BROADCAST_WRITES;
2062 WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
2063 WREG32(RLC_GFX_INDEX, grbm_gfx_index);
2064
2065 WREG32(CGTS_SYS_TCC_DISABLE, 0);
2066 WREG32(CGTS_TCC_DISABLE, 0);
2067 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2068 WREG32(CGTS_USER_TCC_DISABLE, 0);
2069
2070 /* set HW defaults for 3D engine */
2071 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2072 ROQ_IB2_START(0x2b)));
2073
2074 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2075
2076 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2077 SYNC_GRADIENT |
2078 SYNC_WALKER |
2079 SYNC_ALIGNER));
2080
2081 sx_debug_1 = RREG32(SX_DEBUG_1);
2082 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2083 WREG32(SX_DEBUG_1, sx_debug_1);
2084
2085
2086 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2087 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2088 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2089 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2090
2091 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2092 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2093 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2094
2095 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2096 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2097 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2098
2099 WREG32(VGT_NUM_INSTANCES, 1);
2100 WREG32(SPI_CONFIG_CNTL, 0);
2101 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2102 WREG32(CP_PERFMON_CNTL, 0);
2103
2104 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2105 FETCH_FIFO_HIWATER(0x4) |
2106 DONE_FIFO_HIWATER(0xe0) |
2107 ALU_UPDATE_FIFO_HIWATER(0x8)));
2108
2109 sq_config = RREG32(SQ_CONFIG);
2110 sq_config &= ~(PS_PRIO(3) |
2111 VS_PRIO(3) |
2112 GS_PRIO(3) |
2113 ES_PRIO(3));
2114 sq_config |= (VC_ENABLE |
2115 EXPORT_SRC_C |
2116 PS_PRIO(0) |
2117 VS_PRIO(1) |
2118 GS_PRIO(2) |
2119 ES_PRIO(3));
2120
2121 switch (rdev->family) {
2122 case CHIP_CEDAR:
2123 case CHIP_PALM:
2124 case CHIP_SUMO:
2125 case CHIP_SUMO2:
2126 case CHIP_CAICOS:
2127 /* no vertex cache */
2128 sq_config &= ~VC_ENABLE;
2129 break;
2130 default:
2131 break;
2132 }
2133
2134 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2135
2136 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2137 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2138 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2139 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2140 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2141 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2142 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2143
2144 switch (rdev->family) {
2145 case CHIP_CEDAR:
2146 case CHIP_PALM:
2147 case CHIP_SUMO:
2148 case CHIP_SUMO2:
2149 ps_thread_count = 96;
2150 break;
2151 default:
2152 ps_thread_count = 128;
2153 break;
2154 }
2155
2156 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2157 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2158 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2159 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2160 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2161 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2162
2163 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2164 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2165 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2166 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2167 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2168 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2169
2170 WREG32(SQ_CONFIG, sq_config);
2171 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2172 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2173 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2174 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2175 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2176 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2177 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2178 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2179 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2180 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2181
2182 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2183 FORCE_EOV_MAX_REZ_CNT(255)));
2184
2185 switch (rdev->family) {
2186 case CHIP_CEDAR:
2187 case CHIP_PALM:
2188 case CHIP_SUMO:
2189 case CHIP_SUMO2:
2190 case CHIP_CAICOS:
2191 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2192 break;
2193 default:
2194 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2195 break;
2196 }
2197 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2198 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2199
2200 WREG32(VGT_GS_VERTEX_REUSE, 16);
2201 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2202 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2203
2204 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2205 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2206
2207 WREG32(CB_PERF_CTR0_SEL_0, 0);
2208 WREG32(CB_PERF_CTR0_SEL_1, 0);
2209 WREG32(CB_PERF_CTR1_SEL_0, 0);
2210 WREG32(CB_PERF_CTR1_SEL_1, 0);
2211 WREG32(CB_PERF_CTR2_SEL_0, 0);
2212 WREG32(CB_PERF_CTR2_SEL_1, 0);
2213 WREG32(CB_PERF_CTR3_SEL_0, 0);
2214 WREG32(CB_PERF_CTR3_SEL_1, 0);
2215
2216 /* clear render buffer base addresses */
2217 WREG32(CB_COLOR0_BASE, 0);
2218 WREG32(CB_COLOR1_BASE, 0);
2219 WREG32(CB_COLOR2_BASE, 0);
2220 WREG32(CB_COLOR3_BASE, 0);
2221 WREG32(CB_COLOR4_BASE, 0);
2222 WREG32(CB_COLOR5_BASE, 0);
2223 WREG32(CB_COLOR6_BASE, 0);
2224 WREG32(CB_COLOR7_BASE, 0);
2225 WREG32(CB_COLOR8_BASE, 0);
2226 WREG32(CB_COLOR9_BASE, 0);
2227 WREG32(CB_COLOR10_BASE, 0);
2228 WREG32(CB_COLOR11_BASE, 0);
2229
2230 /* set the shader const cache sizes to 0 */
2231 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2232 WREG32(i, 0);
2233 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2234 WREG32(i, 0);
2235
2236 tmp = RREG32(HDP_MISC_CNTL);
2237 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2238 WREG32(HDP_MISC_CNTL, tmp);
2239
2240 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2241 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2242
2243 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2244
2245 udelay(50);
2246
2247}
2248
2249int evergreen_mc_init(struct radeon_device *rdev)
2250{
2251 u32 tmp;
2252 int chansize, numchan;
2253
2254 /* Get VRAM informations */
2255 rdev->mc.vram_is_ddr = true;
2256 if (rdev->flags & RADEON_IS_IGP)
2257 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2258 else
2259 tmp = RREG32(MC_ARB_RAMCFG);
2260 if (tmp & CHANSIZE_OVERRIDE) {
2261 chansize = 16;
2262 } else if (tmp & CHANSIZE_MASK) {
2263 chansize = 64;
2264 } else {
2265 chansize = 32;
2266 }
2267 tmp = RREG32(MC_SHARED_CHMAP);
2268 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2269 case 0:
2270 default:
2271 numchan = 1;
2272 break;
2273 case 1:
2274 numchan = 2;
2275 break;
2276 case 2:
2277 numchan = 4;
2278 break;
2279 case 3:
2280 numchan = 8;
2281 break;
2282 }
2283 rdev->mc.vram_width = numchan * chansize;
2284 /* Could aper size report 0 ? */
2285 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2286 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2287 /* Setup GPU memory space */
2288 if (rdev->flags & RADEON_IS_IGP) {
2289 /* size in bytes on fusion */
2290 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2291 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2292 } else {
2293 /* size in MB on evergreen */
2294 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2295 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2296 }
2297 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2298 r700_vram_gtt_location(rdev, &rdev->mc);
2299 radeon_update_bandwidth_info(rdev);
2300
2301 return 0;
2302}
2303
2304bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
2305{
2306 u32 srbm_status;
2307 u32 grbm_status;
2308 u32 grbm_status_se0, grbm_status_se1;
2309 struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2310 int r;
2311
2312 srbm_status = RREG32(SRBM_STATUS);
2313 grbm_status = RREG32(GRBM_STATUS);
2314 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2315 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2316 if (!(grbm_status & GUI_ACTIVE)) {
2317 r100_gpu_lockup_update(lockup, &rdev->cp);
2318 return false;
2319 }
2320 /* force CP activities */
2321 r = radeon_ring_lock(rdev, 2);
2322 if (!r) {
2323 /* PACKET2 NOP */
2324 radeon_ring_write(rdev, 0x80000000);
2325 radeon_ring_write(rdev, 0x80000000);
2326 radeon_ring_unlock_commit(rdev);
2327 }
2328 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2329 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
2330}
2331
2332static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2333{
2334 struct evergreen_mc_save save;
2335 u32 grbm_reset = 0;
2336
2337 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2338 return 0;
2339
2340 dev_info(rdev->dev, "GPU softreset \n");
2341 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2342 RREG32(GRBM_STATUS));
2343 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2344 RREG32(GRBM_STATUS_SE0));
2345 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2346 RREG32(GRBM_STATUS_SE1));
2347 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2348 RREG32(SRBM_STATUS));
2349 evergreen_mc_stop(rdev, &save);
2350 if (evergreen_mc_wait_for_idle(rdev)) {
2351 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2352 }
2353 /* Disable CP parsing/prefetching */
2354 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2355
2356 /* reset all the gfx blocks */
2357 grbm_reset = (SOFT_RESET_CP |
2358 SOFT_RESET_CB |
2359 SOFT_RESET_DB |
2360 SOFT_RESET_PA |
2361 SOFT_RESET_SC |
2362 SOFT_RESET_SPI |
2363 SOFT_RESET_SH |
2364 SOFT_RESET_SX |
2365 SOFT_RESET_TC |
2366 SOFT_RESET_TA |
2367 SOFT_RESET_VC |
2368 SOFT_RESET_VGT);
2369
2370 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2371 WREG32(GRBM_SOFT_RESET, grbm_reset);
2372 (void)RREG32(GRBM_SOFT_RESET);
2373 udelay(50);
2374 WREG32(GRBM_SOFT_RESET, 0);
2375 (void)RREG32(GRBM_SOFT_RESET);
2376 /* Wait a little for things to settle down */
2377 udelay(50);
2378 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2379 RREG32(GRBM_STATUS));
2380 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2381 RREG32(GRBM_STATUS_SE0));
2382 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2383 RREG32(GRBM_STATUS_SE1));
2384 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2385 RREG32(SRBM_STATUS));
2386 evergreen_mc_resume(rdev, &save);
2387 return 0;
2388}
2389
2390int evergreen_asic_reset(struct radeon_device *rdev)
2391{
2392 return evergreen_gpu_soft_reset(rdev);
2393}
2394
2395/* Interrupts */
2396
2397u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2398{
2399 switch (crtc) {
2400 case 0:
2401 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2402 case 1:
2403 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2404 case 2:
2405 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2406 case 3:
2407 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2408 case 4:
2409 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2410 case 5:
2411 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2412 default:
2413 return 0;
2414 }
2415}
2416
2417void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2418{
2419 u32 tmp;
2420
2421 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2422 WREG32(GRBM_INT_CNTL, 0);
2423 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2424 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2425 if (rdev->num_crtc >= 4) {
2426 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2427 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2428 }
2429 if (rdev->num_crtc >= 6) {
2430 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2431 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2432 }
2433
2434 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2435 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2436 if (rdev->num_crtc >= 4) {
2437 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2438 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2439 }
2440 if (rdev->num_crtc >= 6) {
2441 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2442 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2443 }
2444
2445 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2446 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2447
2448 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2449 WREG32(DC_HPD1_INT_CONTROL, tmp);
2450 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2451 WREG32(DC_HPD2_INT_CONTROL, tmp);
2452 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2453 WREG32(DC_HPD3_INT_CONTROL, tmp);
2454 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2455 WREG32(DC_HPD4_INT_CONTROL, tmp);
2456 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2457 WREG32(DC_HPD5_INT_CONTROL, tmp);
2458 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2459 WREG32(DC_HPD6_INT_CONTROL, tmp);
2460
2461}
2462
2463int evergreen_irq_set(struct radeon_device *rdev)
2464{
2465 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2466 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2467 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2468 u32 grbm_int_cntl = 0;
2469 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2470
2471 if (!rdev->irq.installed) {
2472 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2473 return -EINVAL;
2474 }
2475 /* don't enable anything if the ih is disabled */
2476 if (!rdev->ih.enabled) {
2477 r600_disable_interrupts(rdev);
2478 /* force the active interrupt state to all disabled */
2479 evergreen_disable_interrupt_state(rdev);
2480 return 0;
2481 }
2482
2483 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2484 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2485 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2486 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2487 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2488 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2489
2490 if (rdev->irq.sw_int) {
2491 DRM_DEBUG("evergreen_irq_set: sw int\n");
2492 cp_int_cntl |= RB_INT_ENABLE;
2493 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2494 }
2495 if (rdev->irq.crtc_vblank_int[0] ||
2496 rdev->irq.pflip[0]) {
2497 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2498 crtc1 |= VBLANK_INT_MASK;
2499 }
2500 if (rdev->irq.crtc_vblank_int[1] ||
2501 rdev->irq.pflip[1]) {
2502 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2503 crtc2 |= VBLANK_INT_MASK;
2504 }
2505 if (rdev->irq.crtc_vblank_int[2] ||
2506 rdev->irq.pflip[2]) {
2507 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2508 crtc3 |= VBLANK_INT_MASK;
2509 }
2510 if (rdev->irq.crtc_vblank_int[3] ||
2511 rdev->irq.pflip[3]) {
2512 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2513 crtc4 |= VBLANK_INT_MASK;
2514 }
2515 if (rdev->irq.crtc_vblank_int[4] ||
2516 rdev->irq.pflip[4]) {
2517 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2518 crtc5 |= VBLANK_INT_MASK;
2519 }
2520 if (rdev->irq.crtc_vblank_int[5] ||
2521 rdev->irq.pflip[5]) {
2522 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2523 crtc6 |= VBLANK_INT_MASK;
2524 }
2525 if (rdev->irq.hpd[0]) {
2526 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2527 hpd1 |= DC_HPDx_INT_EN;
2528 }
2529 if (rdev->irq.hpd[1]) {
2530 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2531 hpd2 |= DC_HPDx_INT_EN;
2532 }
2533 if (rdev->irq.hpd[2]) {
2534 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2535 hpd3 |= DC_HPDx_INT_EN;
2536 }
2537 if (rdev->irq.hpd[3]) {
2538 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2539 hpd4 |= DC_HPDx_INT_EN;
2540 }
2541 if (rdev->irq.hpd[4]) {
2542 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2543 hpd5 |= DC_HPDx_INT_EN;
2544 }
2545 if (rdev->irq.hpd[5]) {
2546 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2547 hpd6 |= DC_HPDx_INT_EN;
2548 }
2549 if (rdev->irq.gui_idle) {
2550 DRM_DEBUG("gui idle\n");
2551 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2552 }
2553
2554 WREG32(CP_INT_CNTL, cp_int_cntl);
2555 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2556
2557 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2558 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2559 if (rdev->num_crtc >= 4) {
2560 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2561 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2562 }
2563 if (rdev->num_crtc >= 6) {
2564 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2565 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2566 }
2567
2568 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2569 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2570 if (rdev->num_crtc >= 4) {
2571 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2572 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2573 }
2574 if (rdev->num_crtc >= 6) {
2575 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2576 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2577 }
2578
2579 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2580 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2581 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2582 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2583 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2584 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2585
2586 return 0;
2587}
2588
2589static inline void evergreen_irq_ack(struct radeon_device *rdev)
2590{
2591 u32 tmp;
2592
2593 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2594 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2595 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2596 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2597 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2598 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2599 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2600 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2601 if (rdev->num_crtc >= 4) {
2602 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2603 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2604 }
2605 if (rdev->num_crtc >= 6) {
2606 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2607 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2608 }
2609
2610 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2611 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2612 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2613 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2614 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2615 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2616 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2617 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2618 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2619 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2620 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2621 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2622
2623 if (rdev->num_crtc >= 4) {
2624 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2625 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2626 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2627 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2628 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2629 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2630 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2631 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2632 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2633 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2634 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2635 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2636 }
2637
2638 if (rdev->num_crtc >= 6) {
2639 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2640 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2641 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2642 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2643 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2644 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2645 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2646 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2647 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2648 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2649 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2650 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2651 }
2652
2653 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2654 tmp = RREG32(DC_HPD1_INT_CONTROL);
2655 tmp |= DC_HPDx_INT_ACK;
2656 WREG32(DC_HPD1_INT_CONTROL, tmp);
2657 }
2658 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2659 tmp = RREG32(DC_HPD2_INT_CONTROL);
2660 tmp |= DC_HPDx_INT_ACK;
2661 WREG32(DC_HPD2_INT_CONTROL, tmp);
2662 }
2663 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2664 tmp = RREG32(DC_HPD3_INT_CONTROL);
2665 tmp |= DC_HPDx_INT_ACK;
2666 WREG32(DC_HPD3_INT_CONTROL, tmp);
2667 }
2668 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2669 tmp = RREG32(DC_HPD4_INT_CONTROL);
2670 tmp |= DC_HPDx_INT_ACK;
2671 WREG32(DC_HPD4_INT_CONTROL, tmp);
2672 }
2673 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2674 tmp = RREG32(DC_HPD5_INT_CONTROL);
2675 tmp |= DC_HPDx_INT_ACK;
2676 WREG32(DC_HPD5_INT_CONTROL, tmp);
2677 }
2678 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2679 tmp = RREG32(DC_HPD5_INT_CONTROL);
2680 tmp |= DC_HPDx_INT_ACK;
2681 WREG32(DC_HPD6_INT_CONTROL, tmp);
2682 }
2683}
2684
2685void evergreen_irq_disable(struct radeon_device *rdev)
2686{
2687 r600_disable_interrupts(rdev);
2688 /* Wait and acknowledge irq */
2689 mdelay(1);
2690 evergreen_irq_ack(rdev);
2691 evergreen_disable_interrupt_state(rdev);
2692}
2693
2694void evergreen_irq_suspend(struct radeon_device *rdev)
2695{
2696 evergreen_irq_disable(rdev);
2697 r600_rlc_stop(rdev);
2698}
2699
2700static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2701{
2702 u32 wptr, tmp;
2703
2704 if (rdev->wb.enabled)
2705 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
2706 else
2707 wptr = RREG32(IH_RB_WPTR);
2708
2709 if (wptr & RB_OVERFLOW) {
2710 /* When a ring buffer overflow happen start parsing interrupt
2711 * from the last not overwritten vector (wptr + 16). Hopefully
2712 * this should allow us to catchup.
2713 */
2714 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2715 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2716 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2717 tmp = RREG32(IH_RB_CNTL);
2718 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2719 WREG32(IH_RB_CNTL, tmp);
2720 }
2721 return (wptr & rdev->ih.ptr_mask);
2722}
2723
2724int evergreen_irq_process(struct radeon_device *rdev)
2725{
2726 u32 wptr;
2727 u32 rptr;
2728 u32 src_id, src_data;
2729 u32 ring_index;
2730 unsigned long flags;
2731 bool queue_hotplug = false;
2732
2733 if (!rdev->ih.enabled || rdev->shutdown)
2734 return IRQ_NONE;
2735
2736 wptr = evergreen_get_ih_wptr(rdev);
2737 rptr = rdev->ih.rptr;
2738 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2739
2740 spin_lock_irqsave(&rdev->ih.lock, flags);
2741 if (rptr == wptr) {
2742 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2743 return IRQ_NONE;
2744 }
2745restart_ih:
2746 /* Order reading of wptr vs. reading of IH ring data */
2747 rmb();
2748
2749 /* display interrupts */
2750 evergreen_irq_ack(rdev);
2751
2752 rdev->ih.wptr = wptr;
2753 while (rptr != wptr) {
2754 /* wptr/rptr are in bytes! */
2755 ring_index = rptr / 4;
2756 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2757 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2758
2759 switch (src_id) {
2760 case 1: /* D1 vblank/vline */
2761 switch (src_data) {
2762 case 0: /* D1 vblank */
2763 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2764 if (rdev->irq.crtc_vblank_int[0]) {
2765 drm_handle_vblank(rdev->ddev, 0);
2766 rdev->pm.vblank_sync = true;
2767 wake_up(&rdev->irq.vblank_queue);
2768 }
2769 if (rdev->irq.pflip[0])
2770 radeon_crtc_handle_flip(rdev, 0);
2771 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2772 DRM_DEBUG("IH: D1 vblank\n");
2773 }
2774 break;
2775 case 1: /* D1 vline */
2776 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2777 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2778 DRM_DEBUG("IH: D1 vline\n");
2779 }
2780 break;
2781 default:
2782 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2783 break;
2784 }
2785 break;
2786 case 2: /* D2 vblank/vline */
2787 switch (src_data) {
2788 case 0: /* D2 vblank */
2789 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2790 if (rdev->irq.crtc_vblank_int[1]) {
2791 drm_handle_vblank(rdev->ddev, 1);
2792 rdev->pm.vblank_sync = true;
2793 wake_up(&rdev->irq.vblank_queue);
2794 }
2795 if (rdev->irq.pflip[1])
2796 radeon_crtc_handle_flip(rdev, 1);
2797 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2798 DRM_DEBUG("IH: D2 vblank\n");
2799 }
2800 break;
2801 case 1: /* D2 vline */
2802 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2803 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2804 DRM_DEBUG("IH: D2 vline\n");
2805 }
2806 break;
2807 default:
2808 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2809 break;
2810 }
2811 break;
2812 case 3: /* D3 vblank/vline */
2813 switch (src_data) {
2814 case 0: /* D3 vblank */
2815 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2816 if (rdev->irq.crtc_vblank_int[2]) {
2817 drm_handle_vblank(rdev->ddev, 2);
2818 rdev->pm.vblank_sync = true;
2819 wake_up(&rdev->irq.vblank_queue);
2820 }
2821 if (rdev->irq.pflip[2])
2822 radeon_crtc_handle_flip(rdev, 2);
2823 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2824 DRM_DEBUG("IH: D3 vblank\n");
2825 }
2826 break;
2827 case 1: /* D3 vline */
2828 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2829 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2830 DRM_DEBUG("IH: D3 vline\n");
2831 }
2832 break;
2833 default:
2834 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2835 break;
2836 }
2837 break;
2838 case 4: /* D4 vblank/vline */
2839 switch (src_data) {
2840 case 0: /* D4 vblank */
2841 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2842 if (rdev->irq.crtc_vblank_int[3]) {
2843 drm_handle_vblank(rdev->ddev, 3);
2844 rdev->pm.vblank_sync = true;
2845 wake_up(&rdev->irq.vblank_queue);
2846 }
2847 if (rdev->irq.pflip[3])
2848 radeon_crtc_handle_flip(rdev, 3);
2849 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2850 DRM_DEBUG("IH: D4 vblank\n");
2851 }
2852 break;
2853 case 1: /* D4 vline */
2854 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2855 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2856 DRM_DEBUG("IH: D4 vline\n");
2857 }
2858 break;
2859 default:
2860 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2861 break;
2862 }
2863 break;
2864 case 5: /* D5 vblank/vline */
2865 switch (src_data) {
2866 case 0: /* D5 vblank */
2867 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2868 if (rdev->irq.crtc_vblank_int[4]) {
2869 drm_handle_vblank(rdev->ddev, 4);
2870 rdev->pm.vblank_sync = true;
2871 wake_up(&rdev->irq.vblank_queue);
2872 }
2873 if (rdev->irq.pflip[4])
2874 radeon_crtc_handle_flip(rdev, 4);
2875 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2876 DRM_DEBUG("IH: D5 vblank\n");
2877 }
2878 break;
2879 case 1: /* D5 vline */
2880 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2881 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2882 DRM_DEBUG("IH: D5 vline\n");
2883 }
2884 break;
2885 default:
2886 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2887 break;
2888 }
2889 break;
2890 case 6: /* D6 vblank/vline */
2891 switch (src_data) {
2892 case 0: /* D6 vblank */
2893 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2894 if (rdev->irq.crtc_vblank_int[5]) {
2895 drm_handle_vblank(rdev->ddev, 5);
2896 rdev->pm.vblank_sync = true;
2897 wake_up(&rdev->irq.vblank_queue);
2898 }
2899 if (rdev->irq.pflip[5])
2900 radeon_crtc_handle_flip(rdev, 5);
2901 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2902 DRM_DEBUG("IH: D6 vblank\n");
2903 }
2904 break;
2905 case 1: /* D6 vline */
2906 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2907 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2908 DRM_DEBUG("IH: D6 vline\n");
2909 }
2910 break;
2911 default:
2912 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2913 break;
2914 }
2915 break;
2916 case 42: /* HPD hotplug */
2917 switch (src_data) {
2918 case 0:
2919 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2920 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
2921 queue_hotplug = true;
2922 DRM_DEBUG("IH: HPD1\n");
2923 }
2924 break;
2925 case 1:
2926 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2927 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
2928 queue_hotplug = true;
2929 DRM_DEBUG("IH: HPD2\n");
2930 }
2931 break;
2932 case 2:
2933 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2934 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2935 queue_hotplug = true;
2936 DRM_DEBUG("IH: HPD3\n");
2937 }
2938 break;
2939 case 3:
2940 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2941 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2942 queue_hotplug = true;
2943 DRM_DEBUG("IH: HPD4\n");
2944 }
2945 break;
2946 case 4:
2947 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2948 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2949 queue_hotplug = true;
2950 DRM_DEBUG("IH: HPD5\n");
2951 }
2952 break;
2953 case 5:
2954 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2955 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
2956 queue_hotplug = true;
2957 DRM_DEBUG("IH: HPD6\n");
2958 }
2959 break;
2960 default:
2961 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2962 break;
2963 }
2964 break;
2965 case 176: /* CP_INT in ring buffer */
2966 case 177: /* CP_INT in IB1 */
2967 case 178: /* CP_INT in IB2 */
2968 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2969 radeon_fence_process(rdev);
2970 break;
2971 case 181: /* CP EOP event */
2972 DRM_DEBUG("IH: CP EOP\n");
2973 radeon_fence_process(rdev);
2974 break;
2975 case 233: /* GUI IDLE */
2976 DRM_DEBUG("IH: GUI idle\n");
2977 rdev->pm.gui_idle = true;
2978 wake_up(&rdev->irq.idle_queue);
2979 break;
2980 default:
2981 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2982 break;
2983 }
2984
2985 /* wptr/rptr are in bytes! */
2986 rptr += 16;
2987 rptr &= rdev->ih.ptr_mask;
2988 }
2989 /* make sure wptr hasn't changed while processing */
2990 wptr = evergreen_get_ih_wptr(rdev);
2991 if (wptr != rdev->ih.wptr)
2992 goto restart_ih;
2993 if (queue_hotplug)
2994 schedule_work(&rdev->hotplug_work);
2995 rdev->ih.rptr = rptr;
2996 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2997 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2998 return IRQ_HANDLED;
2999}
3000
3001static int evergreen_startup(struct radeon_device *rdev)
3002{
3003 int r;
3004
3005 /* enable pcie gen2 link */
3006 if (!ASIC_IS_DCE5(rdev))
3007 evergreen_pcie_gen2_enable(rdev);
3008
3009 if (ASIC_IS_DCE5(rdev)) {
3010 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3011 r = ni_init_microcode(rdev);
3012 if (r) {
3013 DRM_ERROR("Failed to load firmware!\n");
3014 return r;
3015 }
3016 }
3017 r = ni_mc_load_microcode(rdev);
3018 if (r) {
3019 DRM_ERROR("Failed to load MC firmware!\n");
3020 return r;
3021 }
3022 } else {
3023 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3024 r = r600_init_microcode(rdev);
3025 if (r) {
3026 DRM_ERROR("Failed to load firmware!\n");
3027 return r;
3028 }
3029 }
3030 }
3031
3032 evergreen_mc_program(rdev);
3033 if (rdev->flags & RADEON_IS_AGP) {
3034 evergreen_agp_enable(rdev);
3035 } else {
3036 r = evergreen_pcie_gart_enable(rdev);
3037 if (r)
3038 return r;
3039 }
3040 evergreen_gpu_init(rdev);
3041
3042 r = evergreen_blit_init(rdev);
3043 if (r) {
3044 evergreen_blit_fini(rdev);
3045 rdev->asic->copy = NULL;
3046 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3047 }
3048
3049 /* allocate wb buffer */
3050 r = radeon_wb_init(rdev);
3051 if (r)
3052 return r;
3053
3054 /* Enable IRQ */
3055 r = r600_irq_init(rdev);
3056 if (r) {
3057 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3058 radeon_irq_kms_fini(rdev);
3059 return r;
3060 }
3061 evergreen_irq_set(rdev);
3062
3063 r = radeon_ring_init(rdev, rdev->cp.ring_size);
3064 if (r)
3065 return r;
3066 r = evergreen_cp_load_microcode(rdev);
3067 if (r)
3068 return r;
3069 r = evergreen_cp_resume(rdev);
3070 if (r)
3071 return r;
3072
3073 return 0;
3074}
3075
3076int evergreen_resume(struct radeon_device *rdev)
3077{
3078 int r;
3079
3080 /* reset the asic, the gfx blocks are often in a bad state
3081 * after the driver is unloaded or after a resume
3082 */
3083 if (radeon_asic_reset(rdev))
3084 dev_warn(rdev->dev, "GPU reset failed !\n");
3085 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3086 * posting will perform necessary task to bring back GPU into good
3087 * shape.
3088 */
3089 /* post card */
3090 atom_asic_init(rdev->mode_info.atom_context);
3091
3092 r = evergreen_startup(rdev);
3093 if (r) {
3094 DRM_ERROR("evergreen startup failed on resume\n");
3095 return r;
3096 }
3097
3098 r = r600_ib_test(rdev);
3099 if (r) {
3100 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3101 return r;
3102 }
3103
3104 return r;
3105
3106}
3107
3108int evergreen_suspend(struct radeon_device *rdev)
3109{
3110 int r;
3111
3112 /* FIXME: we should wait for ring to be empty */
3113 r700_cp_stop(rdev);
3114 rdev->cp.ready = false;
3115 evergreen_irq_suspend(rdev);
3116 radeon_wb_disable(rdev);
3117 evergreen_pcie_gart_disable(rdev);
3118
3119 /* unpin shaders bo */
3120 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
3121 if (likely(r == 0)) {
3122 radeon_bo_unpin(rdev->r600_blit.shader_obj);
3123 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
3124 }
3125
3126 return 0;
3127}
3128
3129int evergreen_copy_blit(struct radeon_device *rdev,
3130 uint64_t src_offset,
3131 uint64_t dst_offset,
3132 unsigned num_gpu_pages,
3133 struct radeon_fence *fence)
3134{
3135 int r;
3136
3137 mutex_lock(&rdev->r600_blit.mutex);
3138 rdev->r600_blit.vb_ib = NULL;
3139 r = evergreen_blit_prepare_copy(rdev, num_gpu_pages * RADEON_GPU_PAGE_SIZE);
3140 if (r) {
3141 if (rdev->r600_blit.vb_ib)
3142 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
3143 mutex_unlock(&rdev->r600_blit.mutex);
3144 return r;
3145 }
3146 evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages * RADEON_GPU_PAGE_SIZE);
3147 evergreen_blit_done_copy(rdev, fence);
3148 mutex_unlock(&rdev->r600_blit.mutex);
3149 return 0;
3150}
3151
3152/* Plan is to move initialization in that function and use
3153 * helper function so that radeon_device_init pretty much
3154 * do nothing more than calling asic specific function. This
3155 * should also allow to remove a bunch of callback function
3156 * like vram_info.
3157 */
3158int evergreen_init(struct radeon_device *rdev)
3159{
3160 int r;
3161
3162 /* This don't do much */
3163 r = radeon_gem_init(rdev);
3164 if (r)
3165 return r;
3166 /* Read BIOS */
3167 if (!radeon_get_bios(rdev)) {
3168 if (ASIC_IS_AVIVO(rdev))
3169 return -EINVAL;
3170 }
3171 /* Must be an ATOMBIOS */
3172 if (!rdev->is_atom_bios) {
3173 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3174 return -EINVAL;
3175 }
3176 r = radeon_atombios_init(rdev);
3177 if (r)
3178 return r;
3179 /* reset the asic, the gfx blocks are often in a bad state
3180 * after the driver is unloaded or after a resume
3181 */
3182 if (radeon_asic_reset(rdev))
3183 dev_warn(rdev->dev, "GPU reset failed !\n");
3184 /* Post card if necessary */
3185 if (!radeon_card_posted(rdev)) {
3186 if (!rdev->bios) {
3187 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3188 return -EINVAL;
3189 }
3190 DRM_INFO("GPU not posted. posting now...\n");
3191 atom_asic_init(rdev->mode_info.atom_context);
3192 }
3193 /* Initialize scratch registers */
3194 r600_scratch_init(rdev);
3195 /* Initialize surface registers */
3196 radeon_surface_init(rdev);
3197 /* Initialize clocks */
3198 radeon_get_clock_info(rdev->ddev);
3199 /* Fence driver */
3200 r = radeon_fence_driver_init(rdev);
3201 if (r)
3202 return r;
3203 /* initialize AGP */
3204 if (rdev->flags & RADEON_IS_AGP) {
3205 r = radeon_agp_init(rdev);
3206 if (r)
3207 radeon_agp_disable(rdev);
3208 }
3209 /* initialize memory controller */
3210 r = evergreen_mc_init(rdev);
3211 if (r)
3212 return r;
3213 /* Memory manager */
3214 r = radeon_bo_init(rdev);
3215 if (r)
3216 return r;
3217
3218 r = radeon_irq_kms_init(rdev);
3219 if (r)
3220 return r;
3221
3222 rdev->cp.ring_obj = NULL;
3223 r600_ring_init(rdev, 1024 * 1024);
3224
3225 rdev->ih.ring_obj = NULL;
3226 r600_ih_ring_init(rdev, 64 * 1024);
3227
3228 r = r600_pcie_gart_init(rdev);
3229 if (r)
3230 return r;
3231
3232 rdev->accel_working = true;
3233 r = evergreen_startup(rdev);
3234 if (r) {
3235 dev_err(rdev->dev, "disabling GPU acceleration\n");
3236 r700_cp_fini(rdev);
3237 r600_irq_fini(rdev);
3238 radeon_wb_fini(rdev);
3239 radeon_irq_kms_fini(rdev);
3240 evergreen_pcie_gart_fini(rdev);
3241 rdev->accel_working = false;
3242 }
3243 if (rdev->accel_working) {
3244 r = radeon_ib_pool_init(rdev);
3245 if (r) {
3246 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
3247 rdev->accel_working = false;
3248 }
3249 r = r600_ib_test(rdev);
3250 if (r) {
3251 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3252 rdev->accel_working = false;
3253 }
3254 }
3255 return 0;
3256}
3257
3258void evergreen_fini(struct radeon_device *rdev)
3259{
3260 evergreen_blit_fini(rdev);
3261 r700_cp_fini(rdev);
3262 r600_irq_fini(rdev);
3263 radeon_wb_fini(rdev);
3264 radeon_ib_pool_fini(rdev);
3265 radeon_irq_kms_fini(rdev);
3266 evergreen_pcie_gart_fini(rdev);
3267 radeon_gem_fini(rdev);
3268 radeon_fence_driver_fini(rdev);
3269 radeon_agp_fini(rdev);
3270 radeon_bo_fini(rdev);
3271 radeon_atombios_fini(rdev);
3272 kfree(rdev->bios);
3273 rdev->bios = NULL;
3274}
3275
3276static void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3277{
3278 u32 link_width_cntl, speed_cntl;
3279
3280 if (radeon_pcie_gen2 == 0)
3281 return;
3282
3283 if (rdev->flags & RADEON_IS_IGP)
3284 return;
3285
3286 if (!(rdev->flags & RADEON_IS_PCIE))
3287 return;
3288
3289 /* x2 cards have a special sequence */
3290 if (ASIC_IS_X2(rdev))
3291 return;
3292
3293 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3294 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3295 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3296
3297 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3298 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3299 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3300
3301 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3302 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3303 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3304
3305 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3306 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3307 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3308
3309 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3310 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3311 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3312
3313 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3314 speed_cntl |= LC_GEN2_EN_STRAP;
3315 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3316
3317 } else {
3318 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3319 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3320 if (1)
3321 link_width_cntl |= LC_UPCONFIGURE_DIS;
3322 else
3323 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3324 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3325 }
3326}
1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
27#include "drmP.h"
28#include "radeon.h"
29#include "radeon_asic.h"
30#include "radeon_drm.h"
31#include "evergreend.h"
32#include "atom.h"
33#include "avivod.h"
34#include "evergreen_reg.h"
35#include "evergreen_blit_shaders.h"
36
37#define EVERGREEN_PFP_UCODE_SIZE 1120
38#define EVERGREEN_PM4_UCODE_SIZE 1376
39
40static void evergreen_gpu_init(struct radeon_device *rdev);
41void evergreen_fini(struct radeon_device *rdev);
42void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
43extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
44 int ring, u32 cp_int_cntl);
45
46void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
47 unsigned *bankh, unsigned *mtaspect,
48 unsigned *tile_split)
49{
50 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
51 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
52 *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
53 *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
54 switch (*bankw) {
55 default:
56 case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
57 case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
58 case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
59 case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
60 }
61 switch (*bankh) {
62 default:
63 case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
64 case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
65 case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
66 case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
67 }
68 switch (*mtaspect) {
69 default:
70 case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
71 case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
72 case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
73 case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
74 }
75}
76
77void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
78{
79 u16 ctl, v;
80 int cap, err;
81
82 cap = pci_pcie_cap(rdev->pdev);
83 if (!cap)
84 return;
85
86 err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
87 if (err)
88 return;
89
90 v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
91
92 /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
93 * to avoid hangs or perfomance issues
94 */
95 if ((v == 0) || (v == 6) || (v == 7)) {
96 ctl &= ~PCI_EXP_DEVCTL_READRQ;
97 ctl |= (2 << 12);
98 pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
99 }
100}
101
102void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
103{
104 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
105 int i;
106
107 if (RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_MASTER_EN) {
108 for (i = 0; i < rdev->usec_timeout; i++) {
109 if (!(RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK))
110 break;
111 udelay(1);
112 }
113 for (i = 0; i < rdev->usec_timeout; i++) {
114 if (RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK)
115 break;
116 udelay(1);
117 }
118 }
119}
120
121void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
122{
123 /* enable the pflip int */
124 radeon_irq_kms_pflip_irq_get(rdev, crtc);
125}
126
127void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
128{
129 /* disable the pflip int */
130 radeon_irq_kms_pflip_irq_put(rdev, crtc);
131}
132
133u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
134{
135 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
136 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
137 int i;
138
139 /* Lock the graphics update lock */
140 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
141 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
142
143 /* update the scanout addresses */
144 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
145 upper_32_bits(crtc_base));
146 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
147 (u32)crtc_base);
148
149 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
150 upper_32_bits(crtc_base));
151 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
152 (u32)crtc_base);
153
154 /* Wait for update_pending to go high. */
155 for (i = 0; i < rdev->usec_timeout; i++) {
156 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
157 break;
158 udelay(1);
159 }
160 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
161
162 /* Unlock the lock, so double-buffering can take place inside vblank */
163 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
164 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
165
166 /* Return current update_pending status: */
167 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
168}
169
170/* get temperature in millidegrees */
171int evergreen_get_temp(struct radeon_device *rdev)
172{
173 u32 temp, toffset;
174 int actual_temp = 0;
175
176 if (rdev->family == CHIP_JUNIPER) {
177 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
178 TOFFSET_SHIFT;
179 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
180 TS0_ADC_DOUT_SHIFT;
181
182 if (toffset & 0x100)
183 actual_temp = temp / 2 - (0x200 - toffset);
184 else
185 actual_temp = temp / 2 + toffset;
186
187 actual_temp = actual_temp * 1000;
188
189 } else {
190 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
191 ASIC_T_SHIFT;
192
193 if (temp & 0x400)
194 actual_temp = -256;
195 else if (temp & 0x200)
196 actual_temp = 255;
197 else if (temp & 0x100) {
198 actual_temp = temp & 0x1ff;
199 actual_temp |= ~0x1ff;
200 } else
201 actual_temp = temp & 0xff;
202
203 actual_temp = (actual_temp * 1000) / 2;
204 }
205
206 return actual_temp;
207}
208
209int sumo_get_temp(struct radeon_device *rdev)
210{
211 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
212 int actual_temp = temp - 49;
213
214 return actual_temp * 1000;
215}
216
217void sumo_pm_init_profile(struct radeon_device *rdev)
218{
219 int idx;
220
221 /* default */
222 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
223 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
224 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
225 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
226
227 /* low,mid sh/mh */
228 if (rdev->flags & RADEON_IS_MOBILITY)
229 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
230 else
231 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
232
233 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
234 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
235 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
236 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
237
238 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
239 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
240 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
241 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
242
243 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
244 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
245 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
246 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
247
248 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
249 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
250 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
251 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
252
253 /* high sh/mh */
254 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
255 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
256 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
257 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
258 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
259 rdev->pm.power_state[idx].num_clock_modes - 1;
260
261 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
262 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
263 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
264 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
265 rdev->pm.power_state[idx].num_clock_modes - 1;
266}
267
268void evergreen_pm_misc(struct radeon_device *rdev)
269{
270 int req_ps_idx = rdev->pm.requested_power_state_index;
271 int req_cm_idx = rdev->pm.requested_clock_mode_index;
272 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
273 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
274
275 if (voltage->type == VOLTAGE_SW) {
276 /* 0xff01 is a flag rather then an actual voltage */
277 if (voltage->voltage == 0xff01)
278 return;
279 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
280 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
281 rdev->pm.current_vddc = voltage->voltage;
282 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
283 }
284 /* 0xff01 is a flag rather then an actual voltage */
285 if (voltage->vddci == 0xff01)
286 return;
287 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
288 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
289 rdev->pm.current_vddci = voltage->vddci;
290 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
291 }
292 }
293}
294
295void evergreen_pm_prepare(struct radeon_device *rdev)
296{
297 struct drm_device *ddev = rdev->ddev;
298 struct drm_crtc *crtc;
299 struct radeon_crtc *radeon_crtc;
300 u32 tmp;
301
302 /* disable any active CRTCs */
303 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
304 radeon_crtc = to_radeon_crtc(crtc);
305 if (radeon_crtc->enabled) {
306 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
307 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
308 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
309 }
310 }
311}
312
313void evergreen_pm_finish(struct radeon_device *rdev)
314{
315 struct drm_device *ddev = rdev->ddev;
316 struct drm_crtc *crtc;
317 struct radeon_crtc *radeon_crtc;
318 u32 tmp;
319
320 /* enable any active CRTCs */
321 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
322 radeon_crtc = to_radeon_crtc(crtc);
323 if (radeon_crtc->enabled) {
324 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
325 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
326 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
327 }
328 }
329}
330
331bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
332{
333 bool connected = false;
334
335 switch (hpd) {
336 case RADEON_HPD_1:
337 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
338 connected = true;
339 break;
340 case RADEON_HPD_2:
341 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
342 connected = true;
343 break;
344 case RADEON_HPD_3:
345 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
346 connected = true;
347 break;
348 case RADEON_HPD_4:
349 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
350 connected = true;
351 break;
352 case RADEON_HPD_5:
353 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
354 connected = true;
355 break;
356 case RADEON_HPD_6:
357 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
358 connected = true;
359 break;
360 default:
361 break;
362 }
363
364 return connected;
365}
366
367void evergreen_hpd_set_polarity(struct radeon_device *rdev,
368 enum radeon_hpd_id hpd)
369{
370 u32 tmp;
371 bool connected = evergreen_hpd_sense(rdev, hpd);
372
373 switch (hpd) {
374 case RADEON_HPD_1:
375 tmp = RREG32(DC_HPD1_INT_CONTROL);
376 if (connected)
377 tmp &= ~DC_HPDx_INT_POLARITY;
378 else
379 tmp |= DC_HPDx_INT_POLARITY;
380 WREG32(DC_HPD1_INT_CONTROL, tmp);
381 break;
382 case RADEON_HPD_2:
383 tmp = RREG32(DC_HPD2_INT_CONTROL);
384 if (connected)
385 tmp &= ~DC_HPDx_INT_POLARITY;
386 else
387 tmp |= DC_HPDx_INT_POLARITY;
388 WREG32(DC_HPD2_INT_CONTROL, tmp);
389 break;
390 case RADEON_HPD_3:
391 tmp = RREG32(DC_HPD3_INT_CONTROL);
392 if (connected)
393 tmp &= ~DC_HPDx_INT_POLARITY;
394 else
395 tmp |= DC_HPDx_INT_POLARITY;
396 WREG32(DC_HPD3_INT_CONTROL, tmp);
397 break;
398 case RADEON_HPD_4:
399 tmp = RREG32(DC_HPD4_INT_CONTROL);
400 if (connected)
401 tmp &= ~DC_HPDx_INT_POLARITY;
402 else
403 tmp |= DC_HPDx_INT_POLARITY;
404 WREG32(DC_HPD4_INT_CONTROL, tmp);
405 break;
406 case RADEON_HPD_5:
407 tmp = RREG32(DC_HPD5_INT_CONTROL);
408 if (connected)
409 tmp &= ~DC_HPDx_INT_POLARITY;
410 else
411 tmp |= DC_HPDx_INT_POLARITY;
412 WREG32(DC_HPD5_INT_CONTROL, tmp);
413 break;
414 case RADEON_HPD_6:
415 tmp = RREG32(DC_HPD6_INT_CONTROL);
416 if (connected)
417 tmp &= ~DC_HPDx_INT_POLARITY;
418 else
419 tmp |= DC_HPDx_INT_POLARITY;
420 WREG32(DC_HPD6_INT_CONTROL, tmp);
421 break;
422 default:
423 break;
424 }
425}
426
427void evergreen_hpd_init(struct radeon_device *rdev)
428{
429 struct drm_device *dev = rdev->ddev;
430 struct drm_connector *connector;
431 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
432 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
433
434 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
435 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
436 switch (radeon_connector->hpd.hpd) {
437 case RADEON_HPD_1:
438 WREG32(DC_HPD1_CONTROL, tmp);
439 rdev->irq.hpd[0] = true;
440 break;
441 case RADEON_HPD_2:
442 WREG32(DC_HPD2_CONTROL, tmp);
443 rdev->irq.hpd[1] = true;
444 break;
445 case RADEON_HPD_3:
446 WREG32(DC_HPD3_CONTROL, tmp);
447 rdev->irq.hpd[2] = true;
448 break;
449 case RADEON_HPD_4:
450 WREG32(DC_HPD4_CONTROL, tmp);
451 rdev->irq.hpd[3] = true;
452 break;
453 case RADEON_HPD_5:
454 WREG32(DC_HPD5_CONTROL, tmp);
455 rdev->irq.hpd[4] = true;
456 break;
457 case RADEON_HPD_6:
458 WREG32(DC_HPD6_CONTROL, tmp);
459 rdev->irq.hpd[5] = true;
460 break;
461 default:
462 break;
463 }
464 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
465 }
466 if (rdev->irq.installed)
467 evergreen_irq_set(rdev);
468}
469
470void evergreen_hpd_fini(struct radeon_device *rdev)
471{
472 struct drm_device *dev = rdev->ddev;
473 struct drm_connector *connector;
474
475 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
476 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
477 switch (radeon_connector->hpd.hpd) {
478 case RADEON_HPD_1:
479 WREG32(DC_HPD1_CONTROL, 0);
480 rdev->irq.hpd[0] = false;
481 break;
482 case RADEON_HPD_2:
483 WREG32(DC_HPD2_CONTROL, 0);
484 rdev->irq.hpd[1] = false;
485 break;
486 case RADEON_HPD_3:
487 WREG32(DC_HPD3_CONTROL, 0);
488 rdev->irq.hpd[2] = false;
489 break;
490 case RADEON_HPD_4:
491 WREG32(DC_HPD4_CONTROL, 0);
492 rdev->irq.hpd[3] = false;
493 break;
494 case RADEON_HPD_5:
495 WREG32(DC_HPD5_CONTROL, 0);
496 rdev->irq.hpd[4] = false;
497 break;
498 case RADEON_HPD_6:
499 WREG32(DC_HPD6_CONTROL, 0);
500 rdev->irq.hpd[5] = false;
501 break;
502 default:
503 break;
504 }
505 }
506}
507
508/* watermark setup */
509
510static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
511 struct radeon_crtc *radeon_crtc,
512 struct drm_display_mode *mode,
513 struct drm_display_mode *other_mode)
514{
515 u32 tmp;
516 /*
517 * Line Buffer Setup
518 * There are 3 line buffers, each one shared by 2 display controllers.
519 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
520 * the display controllers. The paritioning is done via one of four
521 * preset allocations specified in bits 2:0:
522 * first display controller
523 * 0 - first half of lb (3840 * 2)
524 * 1 - first 3/4 of lb (5760 * 2)
525 * 2 - whole lb (7680 * 2), other crtc must be disabled
526 * 3 - first 1/4 of lb (1920 * 2)
527 * second display controller
528 * 4 - second half of lb (3840 * 2)
529 * 5 - second 3/4 of lb (5760 * 2)
530 * 6 - whole lb (7680 * 2), other crtc must be disabled
531 * 7 - last 1/4 of lb (1920 * 2)
532 */
533 /* this can get tricky if we have two large displays on a paired group
534 * of crtcs. Ideally for multiple large displays we'd assign them to
535 * non-linked crtcs for maximum line buffer allocation.
536 */
537 if (radeon_crtc->base.enabled && mode) {
538 if (other_mode)
539 tmp = 0; /* 1/2 */
540 else
541 tmp = 2; /* whole */
542 } else
543 tmp = 0;
544
545 /* second controller of the pair uses second half of the lb */
546 if (radeon_crtc->crtc_id % 2)
547 tmp += 4;
548 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
549
550 if (radeon_crtc->base.enabled && mode) {
551 switch (tmp) {
552 case 0:
553 case 4:
554 default:
555 if (ASIC_IS_DCE5(rdev))
556 return 4096 * 2;
557 else
558 return 3840 * 2;
559 case 1:
560 case 5:
561 if (ASIC_IS_DCE5(rdev))
562 return 6144 * 2;
563 else
564 return 5760 * 2;
565 case 2:
566 case 6:
567 if (ASIC_IS_DCE5(rdev))
568 return 8192 * 2;
569 else
570 return 7680 * 2;
571 case 3:
572 case 7:
573 if (ASIC_IS_DCE5(rdev))
574 return 2048 * 2;
575 else
576 return 1920 * 2;
577 }
578 }
579
580 /* controller not enabled, so no lb used */
581 return 0;
582}
583
584u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
585{
586 u32 tmp = RREG32(MC_SHARED_CHMAP);
587
588 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
589 case 0:
590 default:
591 return 1;
592 case 1:
593 return 2;
594 case 2:
595 return 4;
596 case 3:
597 return 8;
598 }
599}
600
601struct evergreen_wm_params {
602 u32 dram_channels; /* number of dram channels */
603 u32 yclk; /* bandwidth per dram data pin in kHz */
604 u32 sclk; /* engine clock in kHz */
605 u32 disp_clk; /* display clock in kHz */
606 u32 src_width; /* viewport width */
607 u32 active_time; /* active display time in ns */
608 u32 blank_time; /* blank time in ns */
609 bool interlaced; /* mode is interlaced */
610 fixed20_12 vsc; /* vertical scale ratio */
611 u32 num_heads; /* number of active crtcs */
612 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
613 u32 lb_size; /* line buffer allocated to pipe */
614 u32 vtaps; /* vertical scaler taps */
615};
616
617static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
618{
619 /* Calculate DRAM Bandwidth and the part allocated to display. */
620 fixed20_12 dram_efficiency; /* 0.7 */
621 fixed20_12 yclk, dram_channels, bandwidth;
622 fixed20_12 a;
623
624 a.full = dfixed_const(1000);
625 yclk.full = dfixed_const(wm->yclk);
626 yclk.full = dfixed_div(yclk, a);
627 dram_channels.full = dfixed_const(wm->dram_channels * 4);
628 a.full = dfixed_const(10);
629 dram_efficiency.full = dfixed_const(7);
630 dram_efficiency.full = dfixed_div(dram_efficiency, a);
631 bandwidth.full = dfixed_mul(dram_channels, yclk);
632 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
633
634 return dfixed_trunc(bandwidth);
635}
636
637static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
638{
639 /* Calculate DRAM Bandwidth and the part allocated to display. */
640 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
641 fixed20_12 yclk, dram_channels, bandwidth;
642 fixed20_12 a;
643
644 a.full = dfixed_const(1000);
645 yclk.full = dfixed_const(wm->yclk);
646 yclk.full = dfixed_div(yclk, a);
647 dram_channels.full = dfixed_const(wm->dram_channels * 4);
648 a.full = dfixed_const(10);
649 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
650 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
651 bandwidth.full = dfixed_mul(dram_channels, yclk);
652 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
653
654 return dfixed_trunc(bandwidth);
655}
656
657static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
658{
659 /* Calculate the display Data return Bandwidth */
660 fixed20_12 return_efficiency; /* 0.8 */
661 fixed20_12 sclk, bandwidth;
662 fixed20_12 a;
663
664 a.full = dfixed_const(1000);
665 sclk.full = dfixed_const(wm->sclk);
666 sclk.full = dfixed_div(sclk, a);
667 a.full = dfixed_const(10);
668 return_efficiency.full = dfixed_const(8);
669 return_efficiency.full = dfixed_div(return_efficiency, a);
670 a.full = dfixed_const(32);
671 bandwidth.full = dfixed_mul(a, sclk);
672 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
673
674 return dfixed_trunc(bandwidth);
675}
676
677static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
678{
679 /* Calculate the DMIF Request Bandwidth */
680 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
681 fixed20_12 disp_clk, bandwidth;
682 fixed20_12 a;
683
684 a.full = dfixed_const(1000);
685 disp_clk.full = dfixed_const(wm->disp_clk);
686 disp_clk.full = dfixed_div(disp_clk, a);
687 a.full = dfixed_const(10);
688 disp_clk_request_efficiency.full = dfixed_const(8);
689 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
690 a.full = dfixed_const(32);
691 bandwidth.full = dfixed_mul(a, disp_clk);
692 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
693
694 return dfixed_trunc(bandwidth);
695}
696
697static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
698{
699 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
700 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
701 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
702 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
703
704 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
705}
706
707static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
708{
709 /* Calculate the display mode Average Bandwidth
710 * DisplayMode should contain the source and destination dimensions,
711 * timing, etc.
712 */
713 fixed20_12 bpp;
714 fixed20_12 line_time;
715 fixed20_12 src_width;
716 fixed20_12 bandwidth;
717 fixed20_12 a;
718
719 a.full = dfixed_const(1000);
720 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
721 line_time.full = dfixed_div(line_time, a);
722 bpp.full = dfixed_const(wm->bytes_per_pixel);
723 src_width.full = dfixed_const(wm->src_width);
724 bandwidth.full = dfixed_mul(src_width, bpp);
725 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
726 bandwidth.full = dfixed_div(bandwidth, line_time);
727
728 return dfixed_trunc(bandwidth);
729}
730
731static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
732{
733 /* First calcualte the latency in ns */
734 u32 mc_latency = 2000; /* 2000 ns. */
735 u32 available_bandwidth = evergreen_available_bandwidth(wm);
736 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
737 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
738 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
739 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
740 (wm->num_heads * cursor_line_pair_return_time);
741 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
742 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
743 fixed20_12 a, b, c;
744
745 if (wm->num_heads == 0)
746 return 0;
747
748 a.full = dfixed_const(2);
749 b.full = dfixed_const(1);
750 if ((wm->vsc.full > a.full) ||
751 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
752 (wm->vtaps >= 5) ||
753 ((wm->vsc.full >= a.full) && wm->interlaced))
754 max_src_lines_per_dst_line = 4;
755 else
756 max_src_lines_per_dst_line = 2;
757
758 a.full = dfixed_const(available_bandwidth);
759 b.full = dfixed_const(wm->num_heads);
760 a.full = dfixed_div(a, b);
761
762 b.full = dfixed_const(1000);
763 c.full = dfixed_const(wm->disp_clk);
764 b.full = dfixed_div(c, b);
765 c.full = dfixed_const(wm->bytes_per_pixel);
766 b.full = dfixed_mul(b, c);
767
768 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
769
770 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
771 b.full = dfixed_const(1000);
772 c.full = dfixed_const(lb_fill_bw);
773 b.full = dfixed_div(c, b);
774 a.full = dfixed_div(a, b);
775 line_fill_time = dfixed_trunc(a);
776
777 if (line_fill_time < wm->active_time)
778 return latency;
779 else
780 return latency + (line_fill_time - wm->active_time);
781
782}
783
784static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
785{
786 if (evergreen_average_bandwidth(wm) <=
787 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
788 return true;
789 else
790 return false;
791};
792
793static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
794{
795 if (evergreen_average_bandwidth(wm) <=
796 (evergreen_available_bandwidth(wm) / wm->num_heads))
797 return true;
798 else
799 return false;
800};
801
802static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
803{
804 u32 lb_partitions = wm->lb_size / wm->src_width;
805 u32 line_time = wm->active_time + wm->blank_time;
806 u32 latency_tolerant_lines;
807 u32 latency_hiding;
808 fixed20_12 a;
809
810 a.full = dfixed_const(1);
811 if (wm->vsc.full > a.full)
812 latency_tolerant_lines = 1;
813 else {
814 if (lb_partitions <= (wm->vtaps + 1))
815 latency_tolerant_lines = 1;
816 else
817 latency_tolerant_lines = 2;
818 }
819
820 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
821
822 if (evergreen_latency_watermark(wm) <= latency_hiding)
823 return true;
824 else
825 return false;
826}
827
828static void evergreen_program_watermarks(struct radeon_device *rdev,
829 struct radeon_crtc *radeon_crtc,
830 u32 lb_size, u32 num_heads)
831{
832 struct drm_display_mode *mode = &radeon_crtc->base.mode;
833 struct evergreen_wm_params wm;
834 u32 pixel_period;
835 u32 line_time = 0;
836 u32 latency_watermark_a = 0, latency_watermark_b = 0;
837 u32 priority_a_mark = 0, priority_b_mark = 0;
838 u32 priority_a_cnt = PRIORITY_OFF;
839 u32 priority_b_cnt = PRIORITY_OFF;
840 u32 pipe_offset = radeon_crtc->crtc_id * 16;
841 u32 tmp, arb_control3;
842 fixed20_12 a, b, c;
843
844 if (radeon_crtc->base.enabled && num_heads && mode) {
845 pixel_period = 1000000 / (u32)mode->clock;
846 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
847 priority_a_cnt = 0;
848 priority_b_cnt = 0;
849
850 wm.yclk = rdev->pm.current_mclk * 10;
851 wm.sclk = rdev->pm.current_sclk * 10;
852 wm.disp_clk = mode->clock;
853 wm.src_width = mode->crtc_hdisplay;
854 wm.active_time = mode->crtc_hdisplay * pixel_period;
855 wm.blank_time = line_time - wm.active_time;
856 wm.interlaced = false;
857 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
858 wm.interlaced = true;
859 wm.vsc = radeon_crtc->vsc;
860 wm.vtaps = 1;
861 if (radeon_crtc->rmx_type != RMX_OFF)
862 wm.vtaps = 2;
863 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
864 wm.lb_size = lb_size;
865 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
866 wm.num_heads = num_heads;
867
868 /* set for high clocks */
869 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
870 /* set for low clocks */
871 /* wm.yclk = low clk; wm.sclk = low clk */
872 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
873
874 /* possibly force display priority to high */
875 /* should really do this at mode validation time... */
876 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
877 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
878 !evergreen_check_latency_hiding(&wm) ||
879 (rdev->disp_priority == 2)) {
880 DRM_DEBUG_KMS("force priority to high\n");
881 priority_a_cnt |= PRIORITY_ALWAYS_ON;
882 priority_b_cnt |= PRIORITY_ALWAYS_ON;
883 }
884
885 a.full = dfixed_const(1000);
886 b.full = dfixed_const(mode->clock);
887 b.full = dfixed_div(b, a);
888 c.full = dfixed_const(latency_watermark_a);
889 c.full = dfixed_mul(c, b);
890 c.full = dfixed_mul(c, radeon_crtc->hsc);
891 c.full = dfixed_div(c, a);
892 a.full = dfixed_const(16);
893 c.full = dfixed_div(c, a);
894 priority_a_mark = dfixed_trunc(c);
895 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
896
897 a.full = dfixed_const(1000);
898 b.full = dfixed_const(mode->clock);
899 b.full = dfixed_div(b, a);
900 c.full = dfixed_const(latency_watermark_b);
901 c.full = dfixed_mul(c, b);
902 c.full = dfixed_mul(c, radeon_crtc->hsc);
903 c.full = dfixed_div(c, a);
904 a.full = dfixed_const(16);
905 c.full = dfixed_div(c, a);
906 priority_b_mark = dfixed_trunc(c);
907 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
908 }
909
910 /* select wm A */
911 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
912 tmp = arb_control3;
913 tmp &= ~LATENCY_WATERMARK_MASK(3);
914 tmp |= LATENCY_WATERMARK_MASK(1);
915 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
916 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
917 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
918 LATENCY_HIGH_WATERMARK(line_time)));
919 /* select wm B */
920 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
921 tmp &= ~LATENCY_WATERMARK_MASK(3);
922 tmp |= LATENCY_WATERMARK_MASK(2);
923 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
924 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
925 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
926 LATENCY_HIGH_WATERMARK(line_time)));
927 /* restore original selection */
928 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
929
930 /* write the priority marks */
931 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
932 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
933
934}
935
936void evergreen_bandwidth_update(struct radeon_device *rdev)
937{
938 struct drm_display_mode *mode0 = NULL;
939 struct drm_display_mode *mode1 = NULL;
940 u32 num_heads = 0, lb_size;
941 int i;
942
943 radeon_update_display_priority(rdev);
944
945 for (i = 0; i < rdev->num_crtc; i++) {
946 if (rdev->mode_info.crtcs[i]->base.enabled)
947 num_heads++;
948 }
949 for (i = 0; i < rdev->num_crtc; i += 2) {
950 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
951 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
952 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
953 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
954 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
955 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
956 }
957}
958
959int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
960{
961 unsigned i;
962 u32 tmp;
963
964 for (i = 0; i < rdev->usec_timeout; i++) {
965 /* read MC_STATUS */
966 tmp = RREG32(SRBM_STATUS) & 0x1F00;
967 if (!tmp)
968 return 0;
969 udelay(1);
970 }
971 return -1;
972}
973
974/*
975 * GART
976 */
977void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
978{
979 unsigned i;
980 u32 tmp;
981
982 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
983
984 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
985 for (i = 0; i < rdev->usec_timeout; i++) {
986 /* read MC_STATUS */
987 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
988 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
989 if (tmp == 2) {
990 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
991 return;
992 }
993 if (tmp) {
994 return;
995 }
996 udelay(1);
997 }
998}
999
1000int evergreen_pcie_gart_enable(struct radeon_device *rdev)
1001{
1002 u32 tmp;
1003 int r;
1004
1005 if (rdev->gart.robj == NULL) {
1006 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1007 return -EINVAL;
1008 }
1009 r = radeon_gart_table_vram_pin(rdev);
1010 if (r)
1011 return r;
1012 radeon_gart_restore(rdev);
1013 /* Setup L2 cache */
1014 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1015 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1016 EFFECTIVE_L2_QUEUE_SIZE(7));
1017 WREG32(VM_L2_CNTL2, 0);
1018 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1019 /* Setup TLB control */
1020 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1021 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1022 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1023 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1024 if (rdev->flags & RADEON_IS_IGP) {
1025 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
1026 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
1027 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
1028 } else {
1029 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1030 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1031 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1032 if ((rdev->family == CHIP_JUNIPER) ||
1033 (rdev->family == CHIP_CYPRESS) ||
1034 (rdev->family == CHIP_HEMLOCK) ||
1035 (rdev->family == CHIP_BARTS))
1036 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
1037 }
1038 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1039 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1040 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1041 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1042 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1043 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1044 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1045 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1046 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1047 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1048 (u32)(rdev->dummy_page.addr >> 12));
1049 WREG32(VM_CONTEXT1_CNTL, 0);
1050
1051 evergreen_pcie_gart_tlb_flush(rdev);
1052 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1053 (unsigned)(rdev->mc.gtt_size >> 20),
1054 (unsigned long long)rdev->gart.table_addr);
1055 rdev->gart.ready = true;
1056 return 0;
1057}
1058
1059void evergreen_pcie_gart_disable(struct radeon_device *rdev)
1060{
1061 u32 tmp;
1062
1063 /* Disable all tables */
1064 WREG32(VM_CONTEXT0_CNTL, 0);
1065 WREG32(VM_CONTEXT1_CNTL, 0);
1066
1067 /* Setup L2 cache */
1068 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1069 EFFECTIVE_L2_QUEUE_SIZE(7));
1070 WREG32(VM_L2_CNTL2, 0);
1071 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1072 /* Setup TLB control */
1073 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1074 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1075 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1076 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1077 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1078 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1079 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1080 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1081 radeon_gart_table_vram_unpin(rdev);
1082}
1083
1084void evergreen_pcie_gart_fini(struct radeon_device *rdev)
1085{
1086 evergreen_pcie_gart_disable(rdev);
1087 radeon_gart_table_vram_free(rdev);
1088 radeon_gart_fini(rdev);
1089}
1090
1091
1092void evergreen_agp_enable(struct radeon_device *rdev)
1093{
1094 u32 tmp;
1095
1096 /* Setup L2 cache */
1097 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1098 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1099 EFFECTIVE_L2_QUEUE_SIZE(7));
1100 WREG32(VM_L2_CNTL2, 0);
1101 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1102 /* Setup TLB control */
1103 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1104 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1105 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1106 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1107 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1108 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1109 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1110 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1111 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1112 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1113 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1114 WREG32(VM_CONTEXT0_CNTL, 0);
1115 WREG32(VM_CONTEXT1_CNTL, 0);
1116}
1117
1118void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1119{
1120 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1121 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1122
1123 /* Stop all video */
1124 WREG32(VGA_RENDER_CONTROL, 0);
1125 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1126 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1127 if (rdev->num_crtc >= 4) {
1128 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1129 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1130 }
1131 if (rdev->num_crtc >= 6) {
1132 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1133 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1134 }
1135 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1136 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1137 if (rdev->num_crtc >= 4) {
1138 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1139 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1140 }
1141 if (rdev->num_crtc >= 6) {
1142 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1143 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1144 }
1145 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1146 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1147 if (rdev->num_crtc >= 4) {
1148 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1149 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1150 }
1151 if (rdev->num_crtc >= 6) {
1152 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1153 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1154 }
1155
1156 WREG32(D1VGA_CONTROL, 0);
1157 WREG32(D2VGA_CONTROL, 0);
1158 if (rdev->num_crtc >= 4) {
1159 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1160 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1161 }
1162 if (rdev->num_crtc >= 6) {
1163 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1164 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1165 }
1166}
1167
1168void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1169{
1170 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1171 upper_32_bits(rdev->mc.vram_start));
1172 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1173 upper_32_bits(rdev->mc.vram_start));
1174 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1175 (u32)rdev->mc.vram_start);
1176 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1177 (u32)rdev->mc.vram_start);
1178
1179 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1180 upper_32_bits(rdev->mc.vram_start));
1181 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1182 upper_32_bits(rdev->mc.vram_start));
1183 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1184 (u32)rdev->mc.vram_start);
1185 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1186 (u32)rdev->mc.vram_start);
1187
1188 if (rdev->num_crtc >= 4) {
1189 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1190 upper_32_bits(rdev->mc.vram_start));
1191 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1192 upper_32_bits(rdev->mc.vram_start));
1193 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1194 (u32)rdev->mc.vram_start);
1195 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1196 (u32)rdev->mc.vram_start);
1197
1198 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1199 upper_32_bits(rdev->mc.vram_start));
1200 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1201 upper_32_bits(rdev->mc.vram_start));
1202 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1203 (u32)rdev->mc.vram_start);
1204 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1205 (u32)rdev->mc.vram_start);
1206 }
1207 if (rdev->num_crtc >= 6) {
1208 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1209 upper_32_bits(rdev->mc.vram_start));
1210 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1211 upper_32_bits(rdev->mc.vram_start));
1212 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1213 (u32)rdev->mc.vram_start);
1214 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1215 (u32)rdev->mc.vram_start);
1216
1217 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1218 upper_32_bits(rdev->mc.vram_start));
1219 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1220 upper_32_bits(rdev->mc.vram_start));
1221 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1222 (u32)rdev->mc.vram_start);
1223 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1224 (u32)rdev->mc.vram_start);
1225 }
1226
1227 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1228 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1229 /* Unlock host access */
1230 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1231 mdelay(1);
1232 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1233}
1234
1235void evergreen_mc_program(struct radeon_device *rdev)
1236{
1237 struct evergreen_mc_save save;
1238 u32 tmp;
1239 int i, j;
1240
1241 /* Initialize HDP */
1242 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1243 WREG32((0x2c14 + j), 0x00000000);
1244 WREG32((0x2c18 + j), 0x00000000);
1245 WREG32((0x2c1c + j), 0x00000000);
1246 WREG32((0x2c20 + j), 0x00000000);
1247 WREG32((0x2c24 + j), 0x00000000);
1248 }
1249 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1250
1251 evergreen_mc_stop(rdev, &save);
1252 if (evergreen_mc_wait_for_idle(rdev)) {
1253 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1254 }
1255 /* Lockout access through VGA aperture*/
1256 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1257 /* Update configuration */
1258 if (rdev->flags & RADEON_IS_AGP) {
1259 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1260 /* VRAM before AGP */
1261 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1262 rdev->mc.vram_start >> 12);
1263 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1264 rdev->mc.gtt_end >> 12);
1265 } else {
1266 /* VRAM after AGP */
1267 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1268 rdev->mc.gtt_start >> 12);
1269 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1270 rdev->mc.vram_end >> 12);
1271 }
1272 } else {
1273 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1274 rdev->mc.vram_start >> 12);
1275 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1276 rdev->mc.vram_end >> 12);
1277 }
1278 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1279 /* llano/ontario only */
1280 if ((rdev->family == CHIP_PALM) ||
1281 (rdev->family == CHIP_SUMO) ||
1282 (rdev->family == CHIP_SUMO2)) {
1283 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1284 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1285 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1286 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1287 }
1288 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1289 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1290 WREG32(MC_VM_FB_LOCATION, tmp);
1291 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1292 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1293 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1294 if (rdev->flags & RADEON_IS_AGP) {
1295 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1296 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1297 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1298 } else {
1299 WREG32(MC_VM_AGP_BASE, 0);
1300 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1301 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1302 }
1303 if (evergreen_mc_wait_for_idle(rdev)) {
1304 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1305 }
1306 evergreen_mc_resume(rdev, &save);
1307 /* we need to own VRAM, so turn off the VGA renderer here
1308 * to stop it overwriting our objects */
1309 rv515_vga_render_disable(rdev);
1310}
1311
1312/*
1313 * CP.
1314 */
1315void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1316{
1317 struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
1318
1319 /* set to DX10/11 mode */
1320 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1321 radeon_ring_write(ring, 1);
1322 /* FIXME: implement */
1323 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1324 radeon_ring_write(ring,
1325#ifdef __BIG_ENDIAN
1326 (2 << 0) |
1327#endif
1328 (ib->gpu_addr & 0xFFFFFFFC));
1329 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1330 radeon_ring_write(ring, ib->length_dw);
1331}
1332
1333
1334static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1335{
1336 const __be32 *fw_data;
1337 int i;
1338
1339 if (!rdev->me_fw || !rdev->pfp_fw)
1340 return -EINVAL;
1341
1342 r700_cp_stop(rdev);
1343 WREG32(CP_RB_CNTL,
1344#ifdef __BIG_ENDIAN
1345 BUF_SWAP_32BIT |
1346#endif
1347 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1348
1349 fw_data = (const __be32 *)rdev->pfp_fw->data;
1350 WREG32(CP_PFP_UCODE_ADDR, 0);
1351 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1352 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1353 WREG32(CP_PFP_UCODE_ADDR, 0);
1354
1355 fw_data = (const __be32 *)rdev->me_fw->data;
1356 WREG32(CP_ME_RAM_WADDR, 0);
1357 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1358 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1359
1360 WREG32(CP_PFP_UCODE_ADDR, 0);
1361 WREG32(CP_ME_RAM_WADDR, 0);
1362 WREG32(CP_ME_RAM_RADDR, 0);
1363 return 0;
1364}
1365
1366static int evergreen_cp_start(struct radeon_device *rdev)
1367{
1368 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1369 int r, i;
1370 uint32_t cp_me;
1371
1372 r = radeon_ring_lock(rdev, ring, 7);
1373 if (r) {
1374 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1375 return r;
1376 }
1377 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1378 radeon_ring_write(ring, 0x1);
1379 radeon_ring_write(ring, 0x0);
1380 radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
1381 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1382 radeon_ring_write(ring, 0);
1383 radeon_ring_write(ring, 0);
1384 radeon_ring_unlock_commit(rdev, ring);
1385
1386 cp_me = 0xff;
1387 WREG32(CP_ME_CNTL, cp_me);
1388
1389 r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
1390 if (r) {
1391 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1392 return r;
1393 }
1394
1395 /* setup clear context state */
1396 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1397 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1398
1399 for (i = 0; i < evergreen_default_size; i++)
1400 radeon_ring_write(ring, evergreen_default_state[i]);
1401
1402 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1403 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1404
1405 /* set clear context state */
1406 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1407 radeon_ring_write(ring, 0);
1408
1409 /* SQ_VTX_BASE_VTX_LOC */
1410 radeon_ring_write(ring, 0xc0026f00);
1411 radeon_ring_write(ring, 0x00000000);
1412 radeon_ring_write(ring, 0x00000000);
1413 radeon_ring_write(ring, 0x00000000);
1414
1415 /* Clear consts */
1416 radeon_ring_write(ring, 0xc0036f00);
1417 radeon_ring_write(ring, 0x00000bc4);
1418 radeon_ring_write(ring, 0xffffffff);
1419 radeon_ring_write(ring, 0xffffffff);
1420 radeon_ring_write(ring, 0xffffffff);
1421
1422 radeon_ring_write(ring, 0xc0026900);
1423 radeon_ring_write(ring, 0x00000316);
1424 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1425 radeon_ring_write(ring, 0x00000010); /* */
1426
1427 radeon_ring_unlock_commit(rdev, ring);
1428
1429 return 0;
1430}
1431
1432int evergreen_cp_resume(struct radeon_device *rdev)
1433{
1434 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1435 u32 tmp;
1436 u32 rb_bufsz;
1437 int r;
1438
1439 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1440 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1441 SOFT_RESET_PA |
1442 SOFT_RESET_SH |
1443 SOFT_RESET_VGT |
1444 SOFT_RESET_SPI |
1445 SOFT_RESET_SX));
1446 RREG32(GRBM_SOFT_RESET);
1447 mdelay(15);
1448 WREG32(GRBM_SOFT_RESET, 0);
1449 RREG32(GRBM_SOFT_RESET);
1450
1451 /* Set ring buffer size */
1452 rb_bufsz = drm_order(ring->ring_size / 8);
1453 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1454#ifdef __BIG_ENDIAN
1455 tmp |= BUF_SWAP_32BIT;
1456#endif
1457 WREG32(CP_RB_CNTL, tmp);
1458 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1459 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1460
1461 /* Set the write pointer delay */
1462 WREG32(CP_RB_WPTR_DELAY, 0);
1463
1464 /* Initialize the ring buffer's read and write pointers */
1465 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1466 WREG32(CP_RB_RPTR_WR, 0);
1467 ring->wptr = 0;
1468 WREG32(CP_RB_WPTR, ring->wptr);
1469
1470 /* set the wb address wether it's enabled or not */
1471 WREG32(CP_RB_RPTR_ADDR,
1472 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1473 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1474 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1475
1476 if (rdev->wb.enabled)
1477 WREG32(SCRATCH_UMSK, 0xff);
1478 else {
1479 tmp |= RB_NO_UPDATE;
1480 WREG32(SCRATCH_UMSK, 0);
1481 }
1482
1483 mdelay(1);
1484 WREG32(CP_RB_CNTL, tmp);
1485
1486 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
1487 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1488
1489 ring->rptr = RREG32(CP_RB_RPTR);
1490
1491 evergreen_cp_start(rdev);
1492 ring->ready = true;
1493 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1494 if (r) {
1495 ring->ready = false;
1496 return r;
1497 }
1498 return 0;
1499}
1500
1501/*
1502 * Core functions
1503 */
1504static void evergreen_gpu_init(struct radeon_device *rdev)
1505{
1506 u32 gb_addr_config;
1507 u32 mc_shared_chmap, mc_arb_ramcfg;
1508 u32 sx_debug_1;
1509 u32 smx_dc_ctl0;
1510 u32 sq_config;
1511 u32 sq_lds_resource_mgmt;
1512 u32 sq_gpr_resource_mgmt_1;
1513 u32 sq_gpr_resource_mgmt_2;
1514 u32 sq_gpr_resource_mgmt_3;
1515 u32 sq_thread_resource_mgmt;
1516 u32 sq_thread_resource_mgmt_2;
1517 u32 sq_stack_resource_mgmt_1;
1518 u32 sq_stack_resource_mgmt_2;
1519 u32 sq_stack_resource_mgmt_3;
1520 u32 vgt_cache_invalidation;
1521 u32 hdp_host_path_cntl, tmp;
1522 u32 disabled_rb_mask;
1523 int i, j, num_shader_engines, ps_thread_count;
1524
1525 switch (rdev->family) {
1526 case CHIP_CYPRESS:
1527 case CHIP_HEMLOCK:
1528 rdev->config.evergreen.num_ses = 2;
1529 rdev->config.evergreen.max_pipes = 4;
1530 rdev->config.evergreen.max_tile_pipes = 8;
1531 rdev->config.evergreen.max_simds = 10;
1532 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1533 rdev->config.evergreen.max_gprs = 256;
1534 rdev->config.evergreen.max_threads = 248;
1535 rdev->config.evergreen.max_gs_threads = 32;
1536 rdev->config.evergreen.max_stack_entries = 512;
1537 rdev->config.evergreen.sx_num_of_sets = 4;
1538 rdev->config.evergreen.sx_max_export_size = 256;
1539 rdev->config.evergreen.sx_max_export_pos_size = 64;
1540 rdev->config.evergreen.sx_max_export_smx_size = 192;
1541 rdev->config.evergreen.max_hw_contexts = 8;
1542 rdev->config.evergreen.sq_num_cf_insts = 2;
1543
1544 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1545 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1546 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1547 gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN;
1548 break;
1549 case CHIP_JUNIPER:
1550 rdev->config.evergreen.num_ses = 1;
1551 rdev->config.evergreen.max_pipes = 4;
1552 rdev->config.evergreen.max_tile_pipes = 4;
1553 rdev->config.evergreen.max_simds = 10;
1554 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1555 rdev->config.evergreen.max_gprs = 256;
1556 rdev->config.evergreen.max_threads = 248;
1557 rdev->config.evergreen.max_gs_threads = 32;
1558 rdev->config.evergreen.max_stack_entries = 512;
1559 rdev->config.evergreen.sx_num_of_sets = 4;
1560 rdev->config.evergreen.sx_max_export_size = 256;
1561 rdev->config.evergreen.sx_max_export_pos_size = 64;
1562 rdev->config.evergreen.sx_max_export_smx_size = 192;
1563 rdev->config.evergreen.max_hw_contexts = 8;
1564 rdev->config.evergreen.sq_num_cf_insts = 2;
1565
1566 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1567 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1568 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1569 gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN;
1570 break;
1571 case CHIP_REDWOOD:
1572 rdev->config.evergreen.num_ses = 1;
1573 rdev->config.evergreen.max_pipes = 4;
1574 rdev->config.evergreen.max_tile_pipes = 4;
1575 rdev->config.evergreen.max_simds = 5;
1576 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1577 rdev->config.evergreen.max_gprs = 256;
1578 rdev->config.evergreen.max_threads = 248;
1579 rdev->config.evergreen.max_gs_threads = 32;
1580 rdev->config.evergreen.max_stack_entries = 256;
1581 rdev->config.evergreen.sx_num_of_sets = 4;
1582 rdev->config.evergreen.sx_max_export_size = 256;
1583 rdev->config.evergreen.sx_max_export_pos_size = 64;
1584 rdev->config.evergreen.sx_max_export_smx_size = 192;
1585 rdev->config.evergreen.max_hw_contexts = 8;
1586 rdev->config.evergreen.sq_num_cf_insts = 2;
1587
1588 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1589 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1590 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1591 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
1592 break;
1593 case CHIP_CEDAR:
1594 default:
1595 rdev->config.evergreen.num_ses = 1;
1596 rdev->config.evergreen.max_pipes = 2;
1597 rdev->config.evergreen.max_tile_pipes = 2;
1598 rdev->config.evergreen.max_simds = 2;
1599 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1600 rdev->config.evergreen.max_gprs = 256;
1601 rdev->config.evergreen.max_threads = 192;
1602 rdev->config.evergreen.max_gs_threads = 16;
1603 rdev->config.evergreen.max_stack_entries = 256;
1604 rdev->config.evergreen.sx_num_of_sets = 4;
1605 rdev->config.evergreen.sx_max_export_size = 128;
1606 rdev->config.evergreen.sx_max_export_pos_size = 32;
1607 rdev->config.evergreen.sx_max_export_smx_size = 96;
1608 rdev->config.evergreen.max_hw_contexts = 4;
1609 rdev->config.evergreen.sq_num_cf_insts = 1;
1610
1611 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1612 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1613 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1614 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
1615 break;
1616 case CHIP_PALM:
1617 rdev->config.evergreen.num_ses = 1;
1618 rdev->config.evergreen.max_pipes = 2;
1619 rdev->config.evergreen.max_tile_pipes = 2;
1620 rdev->config.evergreen.max_simds = 2;
1621 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1622 rdev->config.evergreen.max_gprs = 256;
1623 rdev->config.evergreen.max_threads = 192;
1624 rdev->config.evergreen.max_gs_threads = 16;
1625 rdev->config.evergreen.max_stack_entries = 256;
1626 rdev->config.evergreen.sx_num_of_sets = 4;
1627 rdev->config.evergreen.sx_max_export_size = 128;
1628 rdev->config.evergreen.sx_max_export_pos_size = 32;
1629 rdev->config.evergreen.sx_max_export_smx_size = 96;
1630 rdev->config.evergreen.max_hw_contexts = 4;
1631 rdev->config.evergreen.sq_num_cf_insts = 1;
1632
1633 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1634 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1635 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1636 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
1637 break;
1638 case CHIP_SUMO:
1639 rdev->config.evergreen.num_ses = 1;
1640 rdev->config.evergreen.max_pipes = 4;
1641 rdev->config.evergreen.max_tile_pipes = 2;
1642 if (rdev->pdev->device == 0x9648)
1643 rdev->config.evergreen.max_simds = 3;
1644 else if ((rdev->pdev->device == 0x9647) ||
1645 (rdev->pdev->device == 0x964a))
1646 rdev->config.evergreen.max_simds = 4;
1647 else
1648 rdev->config.evergreen.max_simds = 5;
1649 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1650 rdev->config.evergreen.max_gprs = 256;
1651 rdev->config.evergreen.max_threads = 248;
1652 rdev->config.evergreen.max_gs_threads = 32;
1653 rdev->config.evergreen.max_stack_entries = 256;
1654 rdev->config.evergreen.sx_num_of_sets = 4;
1655 rdev->config.evergreen.sx_max_export_size = 256;
1656 rdev->config.evergreen.sx_max_export_pos_size = 64;
1657 rdev->config.evergreen.sx_max_export_smx_size = 192;
1658 rdev->config.evergreen.max_hw_contexts = 8;
1659 rdev->config.evergreen.sq_num_cf_insts = 2;
1660
1661 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1662 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1663 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1664 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
1665 break;
1666 case CHIP_SUMO2:
1667 rdev->config.evergreen.num_ses = 1;
1668 rdev->config.evergreen.max_pipes = 4;
1669 rdev->config.evergreen.max_tile_pipes = 4;
1670 rdev->config.evergreen.max_simds = 2;
1671 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1672 rdev->config.evergreen.max_gprs = 256;
1673 rdev->config.evergreen.max_threads = 248;
1674 rdev->config.evergreen.max_gs_threads = 32;
1675 rdev->config.evergreen.max_stack_entries = 512;
1676 rdev->config.evergreen.sx_num_of_sets = 4;
1677 rdev->config.evergreen.sx_max_export_size = 256;
1678 rdev->config.evergreen.sx_max_export_pos_size = 64;
1679 rdev->config.evergreen.sx_max_export_smx_size = 192;
1680 rdev->config.evergreen.max_hw_contexts = 8;
1681 rdev->config.evergreen.sq_num_cf_insts = 2;
1682
1683 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1684 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1685 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1686 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
1687 break;
1688 case CHIP_BARTS:
1689 rdev->config.evergreen.num_ses = 2;
1690 rdev->config.evergreen.max_pipes = 4;
1691 rdev->config.evergreen.max_tile_pipes = 8;
1692 rdev->config.evergreen.max_simds = 7;
1693 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1694 rdev->config.evergreen.max_gprs = 256;
1695 rdev->config.evergreen.max_threads = 248;
1696 rdev->config.evergreen.max_gs_threads = 32;
1697 rdev->config.evergreen.max_stack_entries = 512;
1698 rdev->config.evergreen.sx_num_of_sets = 4;
1699 rdev->config.evergreen.sx_max_export_size = 256;
1700 rdev->config.evergreen.sx_max_export_pos_size = 64;
1701 rdev->config.evergreen.sx_max_export_smx_size = 192;
1702 rdev->config.evergreen.max_hw_contexts = 8;
1703 rdev->config.evergreen.sq_num_cf_insts = 2;
1704
1705 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1706 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1707 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1708 gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN;
1709 break;
1710 case CHIP_TURKS:
1711 rdev->config.evergreen.num_ses = 1;
1712 rdev->config.evergreen.max_pipes = 4;
1713 rdev->config.evergreen.max_tile_pipes = 4;
1714 rdev->config.evergreen.max_simds = 6;
1715 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1716 rdev->config.evergreen.max_gprs = 256;
1717 rdev->config.evergreen.max_threads = 248;
1718 rdev->config.evergreen.max_gs_threads = 32;
1719 rdev->config.evergreen.max_stack_entries = 256;
1720 rdev->config.evergreen.sx_num_of_sets = 4;
1721 rdev->config.evergreen.sx_max_export_size = 256;
1722 rdev->config.evergreen.sx_max_export_pos_size = 64;
1723 rdev->config.evergreen.sx_max_export_smx_size = 192;
1724 rdev->config.evergreen.max_hw_contexts = 8;
1725 rdev->config.evergreen.sq_num_cf_insts = 2;
1726
1727 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1728 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1729 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1730 gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN;
1731 break;
1732 case CHIP_CAICOS:
1733 rdev->config.evergreen.num_ses = 1;
1734 rdev->config.evergreen.max_pipes = 4;
1735 rdev->config.evergreen.max_tile_pipes = 2;
1736 rdev->config.evergreen.max_simds = 2;
1737 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1738 rdev->config.evergreen.max_gprs = 256;
1739 rdev->config.evergreen.max_threads = 192;
1740 rdev->config.evergreen.max_gs_threads = 16;
1741 rdev->config.evergreen.max_stack_entries = 256;
1742 rdev->config.evergreen.sx_num_of_sets = 4;
1743 rdev->config.evergreen.sx_max_export_size = 128;
1744 rdev->config.evergreen.sx_max_export_pos_size = 32;
1745 rdev->config.evergreen.sx_max_export_smx_size = 96;
1746 rdev->config.evergreen.max_hw_contexts = 4;
1747 rdev->config.evergreen.sq_num_cf_insts = 1;
1748
1749 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1750 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1751 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1752 gb_addr_config = CAICOS_GB_ADDR_CONFIG_GOLDEN;
1753 break;
1754 }
1755
1756 /* Initialize HDP */
1757 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1758 WREG32((0x2c14 + j), 0x00000000);
1759 WREG32((0x2c18 + j), 0x00000000);
1760 WREG32((0x2c1c + j), 0x00000000);
1761 WREG32((0x2c20 + j), 0x00000000);
1762 WREG32((0x2c24 + j), 0x00000000);
1763 }
1764
1765 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1766
1767 evergreen_fix_pci_max_read_req_size(rdev);
1768
1769 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1770 if ((rdev->family == CHIP_PALM) ||
1771 (rdev->family == CHIP_SUMO) ||
1772 (rdev->family == CHIP_SUMO2))
1773 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1774 else
1775 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1776
1777 /* setup tiling info dword. gb_addr_config is not adequate since it does
1778 * not have bank info, so create a custom tiling dword.
1779 * bits 3:0 num_pipes
1780 * bits 7:4 num_banks
1781 * bits 11:8 group_size
1782 * bits 15:12 row_size
1783 */
1784 rdev->config.evergreen.tile_config = 0;
1785 switch (rdev->config.evergreen.max_tile_pipes) {
1786 case 1:
1787 default:
1788 rdev->config.evergreen.tile_config |= (0 << 0);
1789 break;
1790 case 2:
1791 rdev->config.evergreen.tile_config |= (1 << 0);
1792 break;
1793 case 4:
1794 rdev->config.evergreen.tile_config |= (2 << 0);
1795 break;
1796 case 8:
1797 rdev->config.evergreen.tile_config |= (3 << 0);
1798 break;
1799 }
1800 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1801 if (rdev->flags & RADEON_IS_IGP)
1802 rdev->config.evergreen.tile_config |= 1 << 4;
1803 else {
1804 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1805 case 0: /* four banks */
1806 rdev->config.evergreen.tile_config |= 0 << 4;
1807 break;
1808 case 1: /* eight banks */
1809 rdev->config.evergreen.tile_config |= 1 << 4;
1810 break;
1811 case 2: /* sixteen banks */
1812 default:
1813 rdev->config.evergreen.tile_config |= 2 << 4;
1814 break;
1815 }
1816 }
1817 rdev->config.evergreen.tile_config |= 0 << 8;
1818 rdev->config.evergreen.tile_config |=
1819 ((gb_addr_config & 0x30000000) >> 28) << 12;
1820
1821 num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1;
1822
1823 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
1824 u32 efuse_straps_4;
1825 u32 efuse_straps_3;
1826
1827 WREG32(RCU_IND_INDEX, 0x204);
1828 efuse_straps_4 = RREG32(RCU_IND_DATA);
1829 WREG32(RCU_IND_INDEX, 0x203);
1830 efuse_straps_3 = RREG32(RCU_IND_DATA);
1831 tmp = (((efuse_straps_4 & 0xf) << 4) |
1832 ((efuse_straps_3 & 0xf0000000) >> 28));
1833 } else {
1834 tmp = 0;
1835 for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {
1836 u32 rb_disable_bitmap;
1837
1838 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1839 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1840 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
1841 tmp <<= 4;
1842 tmp |= rb_disable_bitmap;
1843 }
1844 }
1845 /* enabled rb are just the one not disabled :) */
1846 disabled_rb_mask = tmp;
1847
1848 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1849 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1850
1851 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1852 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1853 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1854
1855 tmp = gb_addr_config & NUM_PIPES_MASK;
1856 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
1857 EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
1858 WREG32(GB_BACKEND_MAP, tmp);
1859
1860 WREG32(CGTS_SYS_TCC_DISABLE, 0);
1861 WREG32(CGTS_TCC_DISABLE, 0);
1862 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1863 WREG32(CGTS_USER_TCC_DISABLE, 0);
1864
1865 /* set HW defaults for 3D engine */
1866 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1867 ROQ_IB2_START(0x2b)));
1868
1869 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1870
1871 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1872 SYNC_GRADIENT |
1873 SYNC_WALKER |
1874 SYNC_ALIGNER));
1875
1876 sx_debug_1 = RREG32(SX_DEBUG_1);
1877 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1878 WREG32(SX_DEBUG_1, sx_debug_1);
1879
1880
1881 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1882 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1883 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
1884 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1885
1886 if (rdev->family <= CHIP_SUMO2)
1887 WREG32(SMX_SAR_CTL0, 0x00010000);
1888
1889 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
1890 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
1891 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
1892
1893 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
1894 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
1895 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
1896
1897 WREG32(VGT_NUM_INSTANCES, 1);
1898 WREG32(SPI_CONFIG_CNTL, 0);
1899 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1900 WREG32(CP_PERFMON_CNTL, 0);
1901
1902 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
1903 FETCH_FIFO_HIWATER(0x4) |
1904 DONE_FIFO_HIWATER(0xe0) |
1905 ALU_UPDATE_FIFO_HIWATER(0x8)));
1906
1907 sq_config = RREG32(SQ_CONFIG);
1908 sq_config &= ~(PS_PRIO(3) |
1909 VS_PRIO(3) |
1910 GS_PRIO(3) |
1911 ES_PRIO(3));
1912 sq_config |= (VC_ENABLE |
1913 EXPORT_SRC_C |
1914 PS_PRIO(0) |
1915 VS_PRIO(1) |
1916 GS_PRIO(2) |
1917 ES_PRIO(3));
1918
1919 switch (rdev->family) {
1920 case CHIP_CEDAR:
1921 case CHIP_PALM:
1922 case CHIP_SUMO:
1923 case CHIP_SUMO2:
1924 case CHIP_CAICOS:
1925 /* no vertex cache */
1926 sq_config &= ~VC_ENABLE;
1927 break;
1928 default:
1929 break;
1930 }
1931
1932 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
1933
1934 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
1935 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
1936 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
1937 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1938 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1939 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1940 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1941
1942 switch (rdev->family) {
1943 case CHIP_CEDAR:
1944 case CHIP_PALM:
1945 case CHIP_SUMO:
1946 case CHIP_SUMO2:
1947 ps_thread_count = 96;
1948 break;
1949 default:
1950 ps_thread_count = 128;
1951 break;
1952 }
1953
1954 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
1955 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1956 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1957 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1958 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1959 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1960
1961 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1962 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1963 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1964 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1965 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1966 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1967
1968 WREG32(SQ_CONFIG, sq_config);
1969 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1970 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1971 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
1972 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1973 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
1974 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1975 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1976 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
1977 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
1978 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
1979
1980 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1981 FORCE_EOV_MAX_REZ_CNT(255)));
1982
1983 switch (rdev->family) {
1984 case CHIP_CEDAR:
1985 case CHIP_PALM:
1986 case CHIP_SUMO:
1987 case CHIP_SUMO2:
1988 case CHIP_CAICOS:
1989 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
1990 break;
1991 default:
1992 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
1993 break;
1994 }
1995 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
1996 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
1997
1998 WREG32(VGT_GS_VERTEX_REUSE, 16);
1999 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2000 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2001
2002 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2003 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2004
2005 WREG32(CB_PERF_CTR0_SEL_0, 0);
2006 WREG32(CB_PERF_CTR0_SEL_1, 0);
2007 WREG32(CB_PERF_CTR1_SEL_0, 0);
2008 WREG32(CB_PERF_CTR1_SEL_1, 0);
2009 WREG32(CB_PERF_CTR2_SEL_0, 0);
2010 WREG32(CB_PERF_CTR2_SEL_1, 0);
2011 WREG32(CB_PERF_CTR3_SEL_0, 0);
2012 WREG32(CB_PERF_CTR3_SEL_1, 0);
2013
2014 /* clear render buffer base addresses */
2015 WREG32(CB_COLOR0_BASE, 0);
2016 WREG32(CB_COLOR1_BASE, 0);
2017 WREG32(CB_COLOR2_BASE, 0);
2018 WREG32(CB_COLOR3_BASE, 0);
2019 WREG32(CB_COLOR4_BASE, 0);
2020 WREG32(CB_COLOR5_BASE, 0);
2021 WREG32(CB_COLOR6_BASE, 0);
2022 WREG32(CB_COLOR7_BASE, 0);
2023 WREG32(CB_COLOR8_BASE, 0);
2024 WREG32(CB_COLOR9_BASE, 0);
2025 WREG32(CB_COLOR10_BASE, 0);
2026 WREG32(CB_COLOR11_BASE, 0);
2027
2028 /* set the shader const cache sizes to 0 */
2029 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2030 WREG32(i, 0);
2031 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2032 WREG32(i, 0);
2033
2034 tmp = RREG32(HDP_MISC_CNTL);
2035 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2036 WREG32(HDP_MISC_CNTL, tmp);
2037
2038 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2039 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2040
2041 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2042
2043 udelay(50);
2044
2045}
2046
2047int evergreen_mc_init(struct radeon_device *rdev)
2048{
2049 u32 tmp;
2050 int chansize, numchan;
2051
2052 /* Get VRAM informations */
2053 rdev->mc.vram_is_ddr = true;
2054 if ((rdev->family == CHIP_PALM) ||
2055 (rdev->family == CHIP_SUMO) ||
2056 (rdev->family == CHIP_SUMO2))
2057 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2058 else
2059 tmp = RREG32(MC_ARB_RAMCFG);
2060 if (tmp & CHANSIZE_OVERRIDE) {
2061 chansize = 16;
2062 } else if (tmp & CHANSIZE_MASK) {
2063 chansize = 64;
2064 } else {
2065 chansize = 32;
2066 }
2067 tmp = RREG32(MC_SHARED_CHMAP);
2068 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2069 case 0:
2070 default:
2071 numchan = 1;
2072 break;
2073 case 1:
2074 numchan = 2;
2075 break;
2076 case 2:
2077 numchan = 4;
2078 break;
2079 case 3:
2080 numchan = 8;
2081 break;
2082 }
2083 rdev->mc.vram_width = numchan * chansize;
2084 /* Could aper size report 0 ? */
2085 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2086 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2087 /* Setup GPU memory space */
2088 if ((rdev->family == CHIP_PALM) ||
2089 (rdev->family == CHIP_SUMO) ||
2090 (rdev->family == CHIP_SUMO2)) {
2091 /* size in bytes on fusion */
2092 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2093 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2094 } else {
2095 /* size in MB on evergreen/cayman/tn */
2096 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2097 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2098 }
2099 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2100 r700_vram_gtt_location(rdev, &rdev->mc);
2101 radeon_update_bandwidth_info(rdev);
2102
2103 return 0;
2104}
2105
2106bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2107{
2108 u32 srbm_status;
2109 u32 grbm_status;
2110 u32 grbm_status_se0, grbm_status_se1;
2111
2112 srbm_status = RREG32(SRBM_STATUS);
2113 grbm_status = RREG32(GRBM_STATUS);
2114 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2115 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2116 if (!(grbm_status & GUI_ACTIVE)) {
2117 radeon_ring_lockup_update(ring);
2118 return false;
2119 }
2120 /* force CP activities */
2121 radeon_ring_force_activity(rdev, ring);
2122 return radeon_ring_test_lockup(rdev, ring);
2123}
2124
2125static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2126{
2127 struct evergreen_mc_save save;
2128 u32 grbm_reset = 0;
2129
2130 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2131 return 0;
2132
2133 dev_info(rdev->dev, "GPU softreset \n");
2134 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2135 RREG32(GRBM_STATUS));
2136 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2137 RREG32(GRBM_STATUS_SE0));
2138 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2139 RREG32(GRBM_STATUS_SE1));
2140 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2141 RREG32(SRBM_STATUS));
2142 evergreen_mc_stop(rdev, &save);
2143 if (evergreen_mc_wait_for_idle(rdev)) {
2144 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2145 }
2146 /* Disable CP parsing/prefetching */
2147 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2148
2149 /* reset all the gfx blocks */
2150 grbm_reset = (SOFT_RESET_CP |
2151 SOFT_RESET_CB |
2152 SOFT_RESET_DB |
2153 SOFT_RESET_PA |
2154 SOFT_RESET_SC |
2155 SOFT_RESET_SPI |
2156 SOFT_RESET_SH |
2157 SOFT_RESET_SX |
2158 SOFT_RESET_TC |
2159 SOFT_RESET_TA |
2160 SOFT_RESET_VC |
2161 SOFT_RESET_VGT);
2162
2163 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2164 WREG32(GRBM_SOFT_RESET, grbm_reset);
2165 (void)RREG32(GRBM_SOFT_RESET);
2166 udelay(50);
2167 WREG32(GRBM_SOFT_RESET, 0);
2168 (void)RREG32(GRBM_SOFT_RESET);
2169 /* Wait a little for things to settle down */
2170 udelay(50);
2171 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2172 RREG32(GRBM_STATUS));
2173 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2174 RREG32(GRBM_STATUS_SE0));
2175 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2176 RREG32(GRBM_STATUS_SE1));
2177 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2178 RREG32(SRBM_STATUS));
2179 evergreen_mc_resume(rdev, &save);
2180 return 0;
2181}
2182
2183int evergreen_asic_reset(struct radeon_device *rdev)
2184{
2185 return evergreen_gpu_soft_reset(rdev);
2186}
2187
2188/* Interrupts */
2189
2190u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2191{
2192 switch (crtc) {
2193 case 0:
2194 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2195 case 1:
2196 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2197 case 2:
2198 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2199 case 3:
2200 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2201 case 4:
2202 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2203 case 5:
2204 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2205 default:
2206 return 0;
2207 }
2208}
2209
2210void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2211{
2212 u32 tmp;
2213
2214 if (rdev->family >= CHIP_CAYMAN) {
2215 cayman_cp_int_cntl_setup(rdev, 0,
2216 CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2217 cayman_cp_int_cntl_setup(rdev, 1, 0);
2218 cayman_cp_int_cntl_setup(rdev, 2, 0);
2219 } else
2220 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2221 WREG32(GRBM_INT_CNTL, 0);
2222 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2223 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2224 if (rdev->num_crtc >= 4) {
2225 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2226 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2227 }
2228 if (rdev->num_crtc >= 6) {
2229 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2230 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2231 }
2232
2233 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2234 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2235 if (rdev->num_crtc >= 4) {
2236 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2237 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2238 }
2239 if (rdev->num_crtc >= 6) {
2240 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2241 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2242 }
2243
2244 /* only one DAC on DCE6 */
2245 if (!ASIC_IS_DCE6(rdev))
2246 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2247 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2248
2249 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2250 WREG32(DC_HPD1_INT_CONTROL, tmp);
2251 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2252 WREG32(DC_HPD2_INT_CONTROL, tmp);
2253 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2254 WREG32(DC_HPD3_INT_CONTROL, tmp);
2255 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2256 WREG32(DC_HPD4_INT_CONTROL, tmp);
2257 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2258 WREG32(DC_HPD5_INT_CONTROL, tmp);
2259 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2260 WREG32(DC_HPD6_INT_CONTROL, tmp);
2261
2262}
2263
2264int evergreen_irq_set(struct radeon_device *rdev)
2265{
2266 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2267 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
2268 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2269 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2270 u32 grbm_int_cntl = 0;
2271 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2272 u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
2273
2274 if (!rdev->irq.installed) {
2275 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2276 return -EINVAL;
2277 }
2278 /* don't enable anything if the ih is disabled */
2279 if (!rdev->ih.enabled) {
2280 r600_disable_interrupts(rdev);
2281 /* force the active interrupt state to all disabled */
2282 evergreen_disable_interrupt_state(rdev);
2283 return 0;
2284 }
2285
2286 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2287 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2288 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2289 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2290 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2291 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2292
2293 afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2294 afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2295 afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2296 afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2297 afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2298 afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2299
2300 if (rdev->family >= CHIP_CAYMAN) {
2301 /* enable CP interrupts on all rings */
2302 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
2303 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2304 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2305 }
2306 if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) {
2307 DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2308 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
2309 }
2310 if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) {
2311 DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2312 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
2313 }
2314 } else {
2315 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
2316 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2317 cp_int_cntl |= RB_INT_ENABLE;
2318 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2319 }
2320 }
2321
2322 if (rdev->irq.crtc_vblank_int[0] ||
2323 rdev->irq.pflip[0]) {
2324 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2325 crtc1 |= VBLANK_INT_MASK;
2326 }
2327 if (rdev->irq.crtc_vblank_int[1] ||
2328 rdev->irq.pflip[1]) {
2329 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2330 crtc2 |= VBLANK_INT_MASK;
2331 }
2332 if (rdev->irq.crtc_vblank_int[2] ||
2333 rdev->irq.pflip[2]) {
2334 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2335 crtc3 |= VBLANK_INT_MASK;
2336 }
2337 if (rdev->irq.crtc_vblank_int[3] ||
2338 rdev->irq.pflip[3]) {
2339 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2340 crtc4 |= VBLANK_INT_MASK;
2341 }
2342 if (rdev->irq.crtc_vblank_int[4] ||
2343 rdev->irq.pflip[4]) {
2344 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2345 crtc5 |= VBLANK_INT_MASK;
2346 }
2347 if (rdev->irq.crtc_vblank_int[5] ||
2348 rdev->irq.pflip[5]) {
2349 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2350 crtc6 |= VBLANK_INT_MASK;
2351 }
2352 if (rdev->irq.hpd[0]) {
2353 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2354 hpd1 |= DC_HPDx_INT_EN;
2355 }
2356 if (rdev->irq.hpd[1]) {
2357 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2358 hpd2 |= DC_HPDx_INT_EN;
2359 }
2360 if (rdev->irq.hpd[2]) {
2361 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2362 hpd3 |= DC_HPDx_INT_EN;
2363 }
2364 if (rdev->irq.hpd[3]) {
2365 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2366 hpd4 |= DC_HPDx_INT_EN;
2367 }
2368 if (rdev->irq.hpd[4]) {
2369 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2370 hpd5 |= DC_HPDx_INT_EN;
2371 }
2372 if (rdev->irq.hpd[5]) {
2373 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2374 hpd6 |= DC_HPDx_INT_EN;
2375 }
2376 if (rdev->irq.afmt[0]) {
2377 DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
2378 afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2379 }
2380 if (rdev->irq.afmt[1]) {
2381 DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
2382 afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2383 }
2384 if (rdev->irq.afmt[2]) {
2385 DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
2386 afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2387 }
2388 if (rdev->irq.afmt[3]) {
2389 DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
2390 afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2391 }
2392 if (rdev->irq.afmt[4]) {
2393 DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
2394 afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2395 }
2396 if (rdev->irq.afmt[5]) {
2397 DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
2398 afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2399 }
2400 if (rdev->irq.gui_idle) {
2401 DRM_DEBUG("gui idle\n");
2402 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2403 }
2404
2405 if (rdev->family >= CHIP_CAYMAN) {
2406 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
2407 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
2408 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
2409 } else
2410 WREG32(CP_INT_CNTL, cp_int_cntl);
2411 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2412
2413 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2414 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2415 if (rdev->num_crtc >= 4) {
2416 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2417 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2418 }
2419 if (rdev->num_crtc >= 6) {
2420 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2421 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2422 }
2423
2424 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2425 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2426 if (rdev->num_crtc >= 4) {
2427 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2428 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2429 }
2430 if (rdev->num_crtc >= 6) {
2431 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2432 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2433 }
2434
2435 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2436 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2437 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2438 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2439 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2440 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2441
2442 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);
2443 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2);
2444 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3);
2445 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4);
2446 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5);
2447 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6);
2448
2449 return 0;
2450}
2451
2452static void evergreen_irq_ack(struct radeon_device *rdev)
2453{
2454 u32 tmp;
2455
2456 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2457 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2458 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2459 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2460 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2461 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2462 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2463 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2464 if (rdev->num_crtc >= 4) {
2465 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2466 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2467 }
2468 if (rdev->num_crtc >= 6) {
2469 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2470 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2471 }
2472
2473 rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2474 rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2475 rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2476 rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2477 rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2478 rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2479
2480 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2481 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2482 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2483 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2484 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2485 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2486 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2487 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2488 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2489 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2490 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2491 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2492
2493 if (rdev->num_crtc >= 4) {
2494 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2495 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2496 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2497 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2498 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2499 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2500 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2501 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2502 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2503 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2504 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2505 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2506 }
2507
2508 if (rdev->num_crtc >= 6) {
2509 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2510 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2511 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2512 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2513 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2514 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2515 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2516 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2517 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2518 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2519 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2520 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2521 }
2522
2523 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2524 tmp = RREG32(DC_HPD1_INT_CONTROL);
2525 tmp |= DC_HPDx_INT_ACK;
2526 WREG32(DC_HPD1_INT_CONTROL, tmp);
2527 }
2528 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2529 tmp = RREG32(DC_HPD2_INT_CONTROL);
2530 tmp |= DC_HPDx_INT_ACK;
2531 WREG32(DC_HPD2_INT_CONTROL, tmp);
2532 }
2533 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2534 tmp = RREG32(DC_HPD3_INT_CONTROL);
2535 tmp |= DC_HPDx_INT_ACK;
2536 WREG32(DC_HPD3_INT_CONTROL, tmp);
2537 }
2538 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2539 tmp = RREG32(DC_HPD4_INT_CONTROL);
2540 tmp |= DC_HPDx_INT_ACK;
2541 WREG32(DC_HPD4_INT_CONTROL, tmp);
2542 }
2543 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2544 tmp = RREG32(DC_HPD5_INT_CONTROL);
2545 tmp |= DC_HPDx_INT_ACK;
2546 WREG32(DC_HPD5_INT_CONTROL, tmp);
2547 }
2548 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2549 tmp = RREG32(DC_HPD5_INT_CONTROL);
2550 tmp |= DC_HPDx_INT_ACK;
2551 WREG32(DC_HPD6_INT_CONTROL, tmp);
2552 }
2553 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
2554 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
2555 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2556 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp);
2557 }
2558 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
2559 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
2560 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2561 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp);
2562 }
2563 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
2564 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
2565 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2566 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp);
2567 }
2568 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
2569 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
2570 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2571 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp);
2572 }
2573 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
2574 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
2575 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2576 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp);
2577 }
2578 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
2579 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2580 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2581 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp);
2582 }
2583}
2584
2585void evergreen_irq_disable(struct radeon_device *rdev)
2586{
2587 r600_disable_interrupts(rdev);
2588 /* Wait and acknowledge irq */
2589 mdelay(1);
2590 evergreen_irq_ack(rdev);
2591 evergreen_disable_interrupt_state(rdev);
2592}
2593
2594void evergreen_irq_suspend(struct radeon_device *rdev)
2595{
2596 evergreen_irq_disable(rdev);
2597 r600_rlc_stop(rdev);
2598}
2599
2600static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2601{
2602 u32 wptr, tmp;
2603
2604 if (rdev->wb.enabled)
2605 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
2606 else
2607 wptr = RREG32(IH_RB_WPTR);
2608
2609 if (wptr & RB_OVERFLOW) {
2610 /* When a ring buffer overflow happen start parsing interrupt
2611 * from the last not overwritten vector (wptr + 16). Hopefully
2612 * this should allow us to catchup.
2613 */
2614 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2615 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2616 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2617 tmp = RREG32(IH_RB_CNTL);
2618 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2619 WREG32(IH_RB_CNTL, tmp);
2620 }
2621 return (wptr & rdev->ih.ptr_mask);
2622}
2623
2624int evergreen_irq_process(struct radeon_device *rdev)
2625{
2626 u32 wptr;
2627 u32 rptr;
2628 u32 src_id, src_data;
2629 u32 ring_index;
2630 unsigned long flags;
2631 bool queue_hotplug = false;
2632 bool queue_hdmi = false;
2633
2634 if (!rdev->ih.enabled || rdev->shutdown)
2635 return IRQ_NONE;
2636
2637 wptr = evergreen_get_ih_wptr(rdev);
2638 rptr = rdev->ih.rptr;
2639 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2640
2641 spin_lock_irqsave(&rdev->ih.lock, flags);
2642 if (rptr == wptr) {
2643 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2644 return IRQ_NONE;
2645 }
2646restart_ih:
2647 /* Order reading of wptr vs. reading of IH ring data */
2648 rmb();
2649
2650 /* display interrupts */
2651 evergreen_irq_ack(rdev);
2652
2653 rdev->ih.wptr = wptr;
2654 while (rptr != wptr) {
2655 /* wptr/rptr are in bytes! */
2656 ring_index = rptr / 4;
2657 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2658 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2659
2660 switch (src_id) {
2661 case 1: /* D1 vblank/vline */
2662 switch (src_data) {
2663 case 0: /* D1 vblank */
2664 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2665 if (rdev->irq.crtc_vblank_int[0]) {
2666 drm_handle_vblank(rdev->ddev, 0);
2667 rdev->pm.vblank_sync = true;
2668 wake_up(&rdev->irq.vblank_queue);
2669 }
2670 if (rdev->irq.pflip[0])
2671 radeon_crtc_handle_flip(rdev, 0);
2672 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2673 DRM_DEBUG("IH: D1 vblank\n");
2674 }
2675 break;
2676 case 1: /* D1 vline */
2677 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2678 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2679 DRM_DEBUG("IH: D1 vline\n");
2680 }
2681 break;
2682 default:
2683 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2684 break;
2685 }
2686 break;
2687 case 2: /* D2 vblank/vline */
2688 switch (src_data) {
2689 case 0: /* D2 vblank */
2690 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2691 if (rdev->irq.crtc_vblank_int[1]) {
2692 drm_handle_vblank(rdev->ddev, 1);
2693 rdev->pm.vblank_sync = true;
2694 wake_up(&rdev->irq.vblank_queue);
2695 }
2696 if (rdev->irq.pflip[1])
2697 radeon_crtc_handle_flip(rdev, 1);
2698 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2699 DRM_DEBUG("IH: D2 vblank\n");
2700 }
2701 break;
2702 case 1: /* D2 vline */
2703 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2704 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2705 DRM_DEBUG("IH: D2 vline\n");
2706 }
2707 break;
2708 default:
2709 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2710 break;
2711 }
2712 break;
2713 case 3: /* D3 vblank/vline */
2714 switch (src_data) {
2715 case 0: /* D3 vblank */
2716 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2717 if (rdev->irq.crtc_vblank_int[2]) {
2718 drm_handle_vblank(rdev->ddev, 2);
2719 rdev->pm.vblank_sync = true;
2720 wake_up(&rdev->irq.vblank_queue);
2721 }
2722 if (rdev->irq.pflip[2])
2723 radeon_crtc_handle_flip(rdev, 2);
2724 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2725 DRM_DEBUG("IH: D3 vblank\n");
2726 }
2727 break;
2728 case 1: /* D3 vline */
2729 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2730 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2731 DRM_DEBUG("IH: D3 vline\n");
2732 }
2733 break;
2734 default:
2735 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2736 break;
2737 }
2738 break;
2739 case 4: /* D4 vblank/vline */
2740 switch (src_data) {
2741 case 0: /* D4 vblank */
2742 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2743 if (rdev->irq.crtc_vblank_int[3]) {
2744 drm_handle_vblank(rdev->ddev, 3);
2745 rdev->pm.vblank_sync = true;
2746 wake_up(&rdev->irq.vblank_queue);
2747 }
2748 if (rdev->irq.pflip[3])
2749 radeon_crtc_handle_flip(rdev, 3);
2750 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2751 DRM_DEBUG("IH: D4 vblank\n");
2752 }
2753 break;
2754 case 1: /* D4 vline */
2755 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2756 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2757 DRM_DEBUG("IH: D4 vline\n");
2758 }
2759 break;
2760 default:
2761 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2762 break;
2763 }
2764 break;
2765 case 5: /* D5 vblank/vline */
2766 switch (src_data) {
2767 case 0: /* D5 vblank */
2768 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2769 if (rdev->irq.crtc_vblank_int[4]) {
2770 drm_handle_vblank(rdev->ddev, 4);
2771 rdev->pm.vblank_sync = true;
2772 wake_up(&rdev->irq.vblank_queue);
2773 }
2774 if (rdev->irq.pflip[4])
2775 radeon_crtc_handle_flip(rdev, 4);
2776 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2777 DRM_DEBUG("IH: D5 vblank\n");
2778 }
2779 break;
2780 case 1: /* D5 vline */
2781 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2782 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2783 DRM_DEBUG("IH: D5 vline\n");
2784 }
2785 break;
2786 default:
2787 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2788 break;
2789 }
2790 break;
2791 case 6: /* D6 vblank/vline */
2792 switch (src_data) {
2793 case 0: /* D6 vblank */
2794 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2795 if (rdev->irq.crtc_vblank_int[5]) {
2796 drm_handle_vblank(rdev->ddev, 5);
2797 rdev->pm.vblank_sync = true;
2798 wake_up(&rdev->irq.vblank_queue);
2799 }
2800 if (rdev->irq.pflip[5])
2801 radeon_crtc_handle_flip(rdev, 5);
2802 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2803 DRM_DEBUG("IH: D6 vblank\n");
2804 }
2805 break;
2806 case 1: /* D6 vline */
2807 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2808 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2809 DRM_DEBUG("IH: D6 vline\n");
2810 }
2811 break;
2812 default:
2813 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2814 break;
2815 }
2816 break;
2817 case 42: /* HPD hotplug */
2818 switch (src_data) {
2819 case 0:
2820 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2821 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
2822 queue_hotplug = true;
2823 DRM_DEBUG("IH: HPD1\n");
2824 }
2825 break;
2826 case 1:
2827 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2828 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
2829 queue_hotplug = true;
2830 DRM_DEBUG("IH: HPD2\n");
2831 }
2832 break;
2833 case 2:
2834 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2835 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2836 queue_hotplug = true;
2837 DRM_DEBUG("IH: HPD3\n");
2838 }
2839 break;
2840 case 3:
2841 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2842 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2843 queue_hotplug = true;
2844 DRM_DEBUG("IH: HPD4\n");
2845 }
2846 break;
2847 case 4:
2848 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2849 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2850 queue_hotplug = true;
2851 DRM_DEBUG("IH: HPD5\n");
2852 }
2853 break;
2854 case 5:
2855 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2856 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
2857 queue_hotplug = true;
2858 DRM_DEBUG("IH: HPD6\n");
2859 }
2860 break;
2861 default:
2862 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2863 break;
2864 }
2865 break;
2866 case 44: /* hdmi */
2867 switch (src_data) {
2868 case 0:
2869 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
2870 rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG;
2871 queue_hdmi = true;
2872 DRM_DEBUG("IH: HDMI0\n");
2873 }
2874 break;
2875 case 1:
2876 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
2877 rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG;
2878 queue_hdmi = true;
2879 DRM_DEBUG("IH: HDMI1\n");
2880 }
2881 break;
2882 case 2:
2883 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
2884 rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG;
2885 queue_hdmi = true;
2886 DRM_DEBUG("IH: HDMI2\n");
2887 }
2888 break;
2889 case 3:
2890 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
2891 rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG;
2892 queue_hdmi = true;
2893 DRM_DEBUG("IH: HDMI3\n");
2894 }
2895 break;
2896 case 4:
2897 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
2898 rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG;
2899 queue_hdmi = true;
2900 DRM_DEBUG("IH: HDMI4\n");
2901 }
2902 break;
2903 case 5:
2904 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
2905 rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG;
2906 queue_hdmi = true;
2907 DRM_DEBUG("IH: HDMI5\n");
2908 }
2909 break;
2910 default:
2911 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
2912 break;
2913 }
2914 break;
2915 case 176: /* CP_INT in ring buffer */
2916 case 177: /* CP_INT in IB1 */
2917 case 178: /* CP_INT in IB2 */
2918 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2919 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
2920 break;
2921 case 181: /* CP EOP event */
2922 DRM_DEBUG("IH: CP EOP\n");
2923 if (rdev->family >= CHIP_CAYMAN) {
2924 switch (src_data) {
2925 case 0:
2926 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
2927 break;
2928 case 1:
2929 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
2930 break;
2931 case 2:
2932 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
2933 break;
2934 }
2935 } else
2936 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
2937 break;
2938 case 233: /* GUI IDLE */
2939 DRM_DEBUG("IH: GUI idle\n");
2940 rdev->pm.gui_idle = true;
2941 wake_up(&rdev->irq.idle_queue);
2942 break;
2943 default:
2944 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2945 break;
2946 }
2947
2948 /* wptr/rptr are in bytes! */
2949 rptr += 16;
2950 rptr &= rdev->ih.ptr_mask;
2951 }
2952 /* make sure wptr hasn't changed while processing */
2953 wptr = evergreen_get_ih_wptr(rdev);
2954 if (wptr != rdev->ih.wptr)
2955 goto restart_ih;
2956 if (queue_hotplug)
2957 schedule_work(&rdev->hotplug_work);
2958 if (queue_hdmi)
2959 schedule_work(&rdev->audio_work);
2960 rdev->ih.rptr = rptr;
2961 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2962 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2963 return IRQ_HANDLED;
2964}
2965
2966static int evergreen_startup(struct radeon_device *rdev)
2967{
2968 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2969 int r;
2970
2971 /* enable pcie gen2 link */
2972 evergreen_pcie_gen2_enable(rdev);
2973
2974 if (ASIC_IS_DCE5(rdev)) {
2975 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
2976 r = ni_init_microcode(rdev);
2977 if (r) {
2978 DRM_ERROR("Failed to load firmware!\n");
2979 return r;
2980 }
2981 }
2982 r = ni_mc_load_microcode(rdev);
2983 if (r) {
2984 DRM_ERROR("Failed to load MC firmware!\n");
2985 return r;
2986 }
2987 } else {
2988 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2989 r = r600_init_microcode(rdev);
2990 if (r) {
2991 DRM_ERROR("Failed to load firmware!\n");
2992 return r;
2993 }
2994 }
2995 }
2996
2997 r = r600_vram_scratch_init(rdev);
2998 if (r)
2999 return r;
3000
3001 evergreen_mc_program(rdev);
3002 if (rdev->flags & RADEON_IS_AGP) {
3003 evergreen_agp_enable(rdev);
3004 } else {
3005 r = evergreen_pcie_gart_enable(rdev);
3006 if (r)
3007 return r;
3008 }
3009 evergreen_gpu_init(rdev);
3010
3011 r = evergreen_blit_init(rdev);
3012 if (r) {
3013 r600_blit_fini(rdev);
3014 rdev->asic->copy.copy = NULL;
3015 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3016 }
3017
3018 /* allocate wb buffer */
3019 r = radeon_wb_init(rdev);
3020 if (r)
3021 return r;
3022
3023 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3024 if (r) {
3025 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3026 return r;
3027 }
3028
3029 /* Enable IRQ */
3030 r = r600_irq_init(rdev);
3031 if (r) {
3032 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3033 radeon_irq_kms_fini(rdev);
3034 return r;
3035 }
3036 evergreen_irq_set(rdev);
3037
3038 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3039 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3040 0, 0xfffff, RADEON_CP_PACKET2);
3041 if (r)
3042 return r;
3043 r = evergreen_cp_load_microcode(rdev);
3044 if (r)
3045 return r;
3046 r = evergreen_cp_resume(rdev);
3047 if (r)
3048 return r;
3049
3050 r = radeon_ib_pool_start(rdev);
3051 if (r)
3052 return r;
3053
3054 r = radeon_ib_ring_tests(rdev);
3055 if (r)
3056 return r;
3057
3058 r = r600_audio_init(rdev);
3059 if (r) {
3060 DRM_ERROR("radeon: audio init failed\n");
3061 return r;
3062 }
3063
3064 return 0;
3065}
3066
3067int evergreen_resume(struct radeon_device *rdev)
3068{
3069 int r;
3070
3071 /* reset the asic, the gfx blocks are often in a bad state
3072 * after the driver is unloaded or after a resume
3073 */
3074 if (radeon_asic_reset(rdev))
3075 dev_warn(rdev->dev, "GPU reset failed !\n");
3076 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3077 * posting will perform necessary task to bring back GPU into good
3078 * shape.
3079 */
3080 /* post card */
3081 atom_asic_init(rdev->mode_info.atom_context);
3082
3083 rdev->accel_working = true;
3084 r = evergreen_startup(rdev);
3085 if (r) {
3086 DRM_ERROR("evergreen startup failed on resume\n");
3087 rdev->accel_working = false;
3088 return r;
3089 }
3090
3091 return r;
3092
3093}
3094
3095int evergreen_suspend(struct radeon_device *rdev)
3096{
3097 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3098
3099 r600_audio_fini(rdev);
3100 /* FIXME: we should wait for ring to be empty */
3101 radeon_ib_pool_suspend(rdev);
3102 r600_blit_suspend(rdev);
3103 r700_cp_stop(rdev);
3104 ring->ready = false;
3105 evergreen_irq_suspend(rdev);
3106 radeon_wb_disable(rdev);
3107 evergreen_pcie_gart_disable(rdev);
3108
3109 return 0;
3110}
3111
3112/* Plan is to move initialization in that function and use
3113 * helper function so that radeon_device_init pretty much
3114 * do nothing more than calling asic specific function. This
3115 * should also allow to remove a bunch of callback function
3116 * like vram_info.
3117 */
3118int evergreen_init(struct radeon_device *rdev)
3119{
3120 int r;
3121
3122 /* Read BIOS */
3123 if (!radeon_get_bios(rdev)) {
3124 if (ASIC_IS_AVIVO(rdev))
3125 return -EINVAL;
3126 }
3127 /* Must be an ATOMBIOS */
3128 if (!rdev->is_atom_bios) {
3129 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3130 return -EINVAL;
3131 }
3132 r = radeon_atombios_init(rdev);
3133 if (r)
3134 return r;
3135 /* reset the asic, the gfx blocks are often in a bad state
3136 * after the driver is unloaded or after a resume
3137 */
3138 if (radeon_asic_reset(rdev))
3139 dev_warn(rdev->dev, "GPU reset failed !\n");
3140 /* Post card if necessary */
3141 if (!radeon_card_posted(rdev)) {
3142 if (!rdev->bios) {
3143 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3144 return -EINVAL;
3145 }
3146 DRM_INFO("GPU not posted. posting now...\n");
3147 atom_asic_init(rdev->mode_info.atom_context);
3148 }
3149 /* Initialize scratch registers */
3150 r600_scratch_init(rdev);
3151 /* Initialize surface registers */
3152 radeon_surface_init(rdev);
3153 /* Initialize clocks */
3154 radeon_get_clock_info(rdev->ddev);
3155 /* Fence driver */
3156 r = radeon_fence_driver_init(rdev);
3157 if (r)
3158 return r;
3159 /* initialize AGP */
3160 if (rdev->flags & RADEON_IS_AGP) {
3161 r = radeon_agp_init(rdev);
3162 if (r)
3163 radeon_agp_disable(rdev);
3164 }
3165 /* initialize memory controller */
3166 r = evergreen_mc_init(rdev);
3167 if (r)
3168 return r;
3169 /* Memory manager */
3170 r = radeon_bo_init(rdev);
3171 if (r)
3172 return r;
3173
3174 r = radeon_irq_kms_init(rdev);
3175 if (r)
3176 return r;
3177
3178 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3179 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3180
3181 rdev->ih.ring_obj = NULL;
3182 r600_ih_ring_init(rdev, 64 * 1024);
3183
3184 r = r600_pcie_gart_init(rdev);
3185 if (r)
3186 return r;
3187
3188 r = radeon_ib_pool_init(rdev);
3189 rdev->accel_working = true;
3190 if (r) {
3191 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3192 rdev->accel_working = false;
3193 }
3194
3195 r = evergreen_startup(rdev);
3196 if (r) {
3197 dev_err(rdev->dev, "disabling GPU acceleration\n");
3198 r700_cp_fini(rdev);
3199 r600_irq_fini(rdev);
3200 radeon_wb_fini(rdev);
3201 r100_ib_fini(rdev);
3202 radeon_irq_kms_fini(rdev);
3203 evergreen_pcie_gart_fini(rdev);
3204 rdev->accel_working = false;
3205 }
3206
3207 /* Don't start up if the MC ucode is missing on BTC parts.
3208 * The default clocks and voltages before the MC ucode
3209 * is loaded are not suffient for advanced operations.
3210 */
3211 if (ASIC_IS_DCE5(rdev)) {
3212 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
3213 DRM_ERROR("radeon: MC ucode required for NI+.\n");
3214 return -EINVAL;
3215 }
3216 }
3217
3218 return 0;
3219}
3220
3221void evergreen_fini(struct radeon_device *rdev)
3222{
3223 r600_audio_fini(rdev);
3224 r600_blit_fini(rdev);
3225 r700_cp_fini(rdev);
3226 r600_irq_fini(rdev);
3227 radeon_wb_fini(rdev);
3228 r100_ib_fini(rdev);
3229 radeon_irq_kms_fini(rdev);
3230 evergreen_pcie_gart_fini(rdev);
3231 r600_vram_scratch_fini(rdev);
3232 radeon_gem_fini(rdev);
3233 radeon_fence_driver_fini(rdev);
3234 radeon_agp_fini(rdev);
3235 radeon_bo_fini(rdev);
3236 radeon_atombios_fini(rdev);
3237 kfree(rdev->bios);
3238 rdev->bios = NULL;
3239}
3240
3241void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3242{
3243 u32 link_width_cntl, speed_cntl;
3244
3245 if (radeon_pcie_gen2 == 0)
3246 return;
3247
3248 if (rdev->flags & RADEON_IS_IGP)
3249 return;
3250
3251 if (!(rdev->flags & RADEON_IS_PCIE))
3252 return;
3253
3254 /* x2 cards have a special sequence */
3255 if (ASIC_IS_X2(rdev))
3256 return;
3257
3258 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3259 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3260 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3261
3262 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3263 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3264 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3265
3266 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3267 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3268 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3269
3270 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3271 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3272 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3273
3274 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3275 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3276 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3277
3278 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3279 speed_cntl |= LC_GEN2_EN_STRAP;
3280 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3281
3282 } else {
3283 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3284 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3285 if (1)
3286 link_width_cntl |= LC_UPCONFIGURE_DIS;
3287 else
3288 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3289 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3290 }
3291}