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1/**
2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/slab.h>
21#include <linux/spinlock.h>
22#include <linux/platform_device.h>
23#include <linux/pm_runtime.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/list.h>
27#include <linux/dma-mapping.h>
28
29#include <linux/usb/ch9.h>
30#include <linux/usb/gadget.h>
31#include <linux/usb/composite.h>
32
33#include "core.h"
34#include "gadget.h"
35#include "io.h"
36
37static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
38static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
39 struct dwc3_ep *dep, struct dwc3_request *req);
40
41static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
42{
43 switch (state) {
44 case EP0_UNCONNECTED:
45 return "Unconnected";
46 case EP0_SETUP_PHASE:
47 return "Setup Phase";
48 case EP0_DATA_PHASE:
49 return "Data Phase";
50 case EP0_STATUS_PHASE:
51 return "Status Phase";
52 default:
53 return "UNKNOWN";
54 }
55}
56
57static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
58 u32 len, u32 type)
59{
60 struct dwc3_gadget_ep_cmd_params params;
61 struct dwc3_trb *trb;
62 struct dwc3_ep *dep;
63
64 int ret;
65
66 dep = dwc->eps[epnum];
67 if (dep->flags & DWC3_EP_BUSY) {
68 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
69 return 0;
70 }
71
72 trb = dwc->ep0_trb;
73
74 trb->bpl = lower_32_bits(buf_dma);
75 trb->bph = upper_32_bits(buf_dma);
76 trb->size = len;
77 trb->ctrl = type;
78
79 trb->ctrl |= (DWC3_TRB_CTRL_HWO
80 | DWC3_TRB_CTRL_LST
81 | DWC3_TRB_CTRL_IOC
82 | DWC3_TRB_CTRL_ISP_IMI);
83
84 memset(¶ms, 0, sizeof(params));
85 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
86 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
87
88 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
89 DWC3_DEPCMD_STARTTRANSFER, ¶ms);
90 if (ret < 0) {
91 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
92 return ret;
93 }
94
95 dep->flags |= DWC3_EP_BUSY;
96 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
97 dep->number);
98
99 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
100
101 return 0;
102}
103
104static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
105 struct dwc3_request *req)
106{
107 struct dwc3 *dwc = dep->dwc;
108
109 req->request.actual = 0;
110 req->request.status = -EINPROGRESS;
111 req->epnum = dep->number;
112
113 list_add_tail(&req->list, &dep->request_list);
114
115 /*
116 * Gadget driver might not be quick enough to queue a request
117 * before we get a Transfer Not Ready event on this endpoint.
118 *
119 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
120 * flag is set, it's telling us that as soon as Gadget queues the
121 * required request, we should kick the transfer here because the
122 * IRQ we were waiting for is long gone.
123 */
124 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
125 unsigned direction;
126
127 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
128
129 if (dwc->ep0state != EP0_DATA_PHASE) {
130 dev_WARN(dwc->dev, "Unexpected pending request\n");
131 return 0;
132 }
133
134 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
135
136 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
137 DWC3_EP0_DIR_IN);
138
139 return 0;
140 }
141
142 /*
143 * In case gadget driver asked us to delay the STATUS phase,
144 * handle it here.
145 */
146 if (dwc->delayed_status) {
147 unsigned direction;
148
149 direction = !dwc->ep0_expect_in;
150 dwc->delayed_status = false;
151 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
152
153 if (dwc->ep0state == EP0_STATUS_PHASE)
154 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
155 else
156 dev_dbg(dwc->dev, "too early for delayed status\n");
157
158 return 0;
159 }
160
161 /*
162 * Unfortunately we have uncovered a limitation wrt the Data Phase.
163 *
164 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
165 * come before issueing Start Transfer command, but if we do, we will
166 * miss situations where the host starts another SETUP phase instead of
167 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
168 * Layer Compliance Suite.
169 *
170 * The problem surfaces due to the fact that in case of back-to-back
171 * SETUP packets there will be no XferNotReady(DATA) generated and we
172 * will be stuck waiting for XferNotReady(DATA) forever.
173 *
174 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
175 * it tells us to start Data Phase right away. It also mentions that if
176 * we receive a SETUP phase instead of the DATA phase, core will issue
177 * XferComplete for the DATA phase, before actually initiating it in
178 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
179 * can only be used to print some debugging logs, as the core expects
180 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
181 * just so it completes right away, without transferring anything and,
182 * only then, we can go back to the SETUP phase.
183 *
184 * Because of this scenario, SNPS decided to change the programming
185 * model of control transfers and support on-demand transfers only for
186 * the STATUS phase. To fix the issue we have now, we will always wait
187 * for gadget driver to queue the DATA phase's struct usb_request, then
188 * start it right away.
189 *
190 * If we're actually in a 2-stage transfer, we will wait for
191 * XferNotReady(STATUS).
192 */
193 if (dwc->three_stage_setup) {
194 unsigned direction;
195
196 direction = dwc->ep0_expect_in;
197 dwc->ep0state = EP0_DATA_PHASE;
198
199 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
200
201 dep->flags &= ~DWC3_EP0_DIR_IN;
202 }
203
204 return 0;
205}
206
207int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
208 gfp_t gfp_flags)
209{
210 struct dwc3_request *req = to_dwc3_request(request);
211 struct dwc3_ep *dep = to_dwc3_ep(ep);
212 struct dwc3 *dwc = dep->dwc;
213
214 unsigned long flags;
215
216 int ret;
217
218 spin_lock_irqsave(&dwc->lock, flags);
219 if (!dep->endpoint.desc) {
220 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
221 request, dep->name);
222 ret = -ESHUTDOWN;
223 goto out;
224 }
225
226 /* we share one TRB for ep0/1 */
227 if (!list_empty(&dep->request_list)) {
228 ret = -EBUSY;
229 goto out;
230 }
231
232 dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
233 request, dep->name, request->length,
234 dwc3_ep0_state_string(dwc->ep0state));
235
236 ret = __dwc3_gadget_ep0_queue(dep, req);
237
238out:
239 spin_unlock_irqrestore(&dwc->lock, flags);
240
241 return ret;
242}
243
244static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
245{
246 struct dwc3_ep *dep;
247
248 /* reinitialize physical ep1 */
249 dep = dwc->eps[1];
250 dep->flags = DWC3_EP_ENABLED;
251
252 /* stall is always issued on EP0 */
253 dep = dwc->eps[0];
254 __dwc3_gadget_ep_set_halt(dep, 1);
255 dep->flags = DWC3_EP_ENABLED;
256 dwc->delayed_status = false;
257
258 if (!list_empty(&dep->request_list)) {
259 struct dwc3_request *req;
260
261 req = next_request(&dep->request_list);
262 dwc3_gadget_giveback(dep, req, -ECONNRESET);
263 }
264
265 dwc->ep0state = EP0_SETUP_PHASE;
266 dwc3_ep0_out_start(dwc);
267}
268
269int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
270{
271 struct dwc3_ep *dep = to_dwc3_ep(ep);
272 struct dwc3 *dwc = dep->dwc;
273
274 dwc3_ep0_stall_and_restart(dwc);
275
276 return 0;
277}
278
279void dwc3_ep0_out_start(struct dwc3 *dwc)
280{
281 int ret;
282
283 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
284 DWC3_TRBCTL_CONTROL_SETUP);
285 WARN_ON(ret < 0);
286}
287
288static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
289{
290 struct dwc3_ep *dep;
291 u32 windex = le16_to_cpu(wIndex_le);
292 u32 epnum;
293
294 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
295 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
296 epnum |= 1;
297
298 dep = dwc->eps[epnum];
299 if (dep->flags & DWC3_EP_ENABLED)
300 return dep;
301
302 return NULL;
303}
304
305static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
306{
307}
308/*
309 * ch 9.4.5
310 */
311static int dwc3_ep0_handle_status(struct dwc3 *dwc,
312 struct usb_ctrlrequest *ctrl)
313{
314 struct dwc3_ep *dep;
315 u32 recip;
316 u32 reg;
317 u16 usb_status = 0;
318 __le16 *response_pkt;
319
320 recip = ctrl->bRequestType & USB_RECIP_MASK;
321 switch (recip) {
322 case USB_RECIP_DEVICE:
323 /*
324 * LTM will be set once we know how to set this in HW.
325 */
326 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
327
328 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
329 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
330 if (reg & DWC3_DCTL_INITU1ENA)
331 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
332 if (reg & DWC3_DCTL_INITU2ENA)
333 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
334 }
335
336 break;
337
338 case USB_RECIP_INTERFACE:
339 /*
340 * Function Remote Wake Capable D0
341 * Function Remote Wakeup D1
342 */
343 break;
344
345 case USB_RECIP_ENDPOINT:
346 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
347 if (!dep)
348 return -EINVAL;
349
350 if (dep->flags & DWC3_EP_STALL)
351 usb_status = 1 << USB_ENDPOINT_HALT;
352 break;
353 default:
354 return -EINVAL;
355 }
356
357 response_pkt = (__le16 *) dwc->setup_buf;
358 *response_pkt = cpu_to_le16(usb_status);
359
360 dep = dwc->eps[0];
361 dwc->ep0_usb_req.dep = dep;
362 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
363 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
364 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
365
366 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
367}
368
369static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
370 struct usb_ctrlrequest *ctrl, int set)
371{
372 struct dwc3_ep *dep;
373 u32 recip;
374 u32 wValue;
375 u32 wIndex;
376 u32 reg;
377 int ret;
378 enum usb_device_state state;
379
380 wValue = le16_to_cpu(ctrl->wValue);
381 wIndex = le16_to_cpu(ctrl->wIndex);
382 recip = ctrl->bRequestType & USB_RECIP_MASK;
383 state = dwc->gadget.state;
384
385 switch (recip) {
386 case USB_RECIP_DEVICE:
387
388 switch (wValue) {
389 case USB_DEVICE_REMOTE_WAKEUP:
390 break;
391 /*
392 * 9.4.1 says only only for SS, in AddressState only for
393 * default control pipe
394 */
395 case USB_DEVICE_U1_ENABLE:
396 if (state != USB_STATE_CONFIGURED)
397 return -EINVAL;
398 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
399 return -EINVAL;
400
401 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
402 if (set)
403 reg |= DWC3_DCTL_INITU1ENA;
404 else
405 reg &= ~DWC3_DCTL_INITU1ENA;
406 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
407 break;
408
409 case USB_DEVICE_U2_ENABLE:
410 if (state != USB_STATE_CONFIGURED)
411 return -EINVAL;
412 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
413 return -EINVAL;
414
415 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
416 if (set)
417 reg |= DWC3_DCTL_INITU2ENA;
418 else
419 reg &= ~DWC3_DCTL_INITU2ENA;
420 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
421 break;
422
423 case USB_DEVICE_LTM_ENABLE:
424 return -EINVAL;
425 break;
426
427 case USB_DEVICE_TEST_MODE:
428 if ((wIndex & 0xff) != 0)
429 return -EINVAL;
430 if (!set)
431 return -EINVAL;
432
433 dwc->test_mode_nr = wIndex >> 8;
434 dwc->test_mode = true;
435 break;
436 default:
437 return -EINVAL;
438 }
439 break;
440
441 case USB_RECIP_INTERFACE:
442 switch (wValue) {
443 case USB_INTRF_FUNC_SUSPEND:
444 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
445 /* XXX enable Low power suspend */
446 ;
447 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
448 /* XXX enable remote wakeup */
449 ;
450 break;
451 default:
452 return -EINVAL;
453 }
454 break;
455
456 case USB_RECIP_ENDPOINT:
457 switch (wValue) {
458 case USB_ENDPOINT_HALT:
459 dep = dwc3_wIndex_to_dep(dwc, wIndex);
460 if (!dep)
461 return -EINVAL;
462 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
463 break;
464 ret = __dwc3_gadget_ep_set_halt(dep, set);
465 if (ret)
466 return -EINVAL;
467 break;
468 default:
469 return -EINVAL;
470 }
471 break;
472
473 default:
474 return -EINVAL;
475 }
476
477 return 0;
478}
479
480static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
481{
482 enum usb_device_state state = dwc->gadget.state;
483 u32 addr;
484 u32 reg;
485
486 addr = le16_to_cpu(ctrl->wValue);
487 if (addr > 127) {
488 dev_dbg(dwc->dev, "invalid device address %d\n", addr);
489 return -EINVAL;
490 }
491
492 if (state == USB_STATE_CONFIGURED) {
493 dev_dbg(dwc->dev, "trying to set address when configured\n");
494 return -EINVAL;
495 }
496
497 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
498 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
499 reg |= DWC3_DCFG_DEVADDR(addr);
500 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
501
502 if (addr)
503 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
504 else
505 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
506
507 return 0;
508}
509
510static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
511{
512 int ret;
513
514 spin_unlock(&dwc->lock);
515 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
516 spin_lock(&dwc->lock);
517 return ret;
518}
519
520static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
521{
522 enum usb_device_state state = dwc->gadget.state;
523 u32 cfg;
524 int ret;
525 u32 reg;
526
527 dwc->start_config_issued = false;
528 cfg = le16_to_cpu(ctrl->wValue);
529
530 switch (state) {
531 case USB_STATE_DEFAULT:
532 return -EINVAL;
533 break;
534
535 case USB_STATE_ADDRESS:
536 ret = dwc3_ep0_delegate_req(dwc, ctrl);
537 /* if the cfg matches and the cfg is non zero */
538 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
539
540 /*
541 * only change state if set_config has already
542 * been processed. If gadget driver returns
543 * USB_GADGET_DELAYED_STATUS, we will wait
544 * to change the state on the next usb_ep_queue()
545 */
546 if (ret == 0)
547 usb_gadget_set_state(&dwc->gadget,
548 USB_STATE_CONFIGURED);
549
550 /*
551 * Enable transition to U1/U2 state when
552 * nothing is pending from application.
553 */
554 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
555 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
556 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
557
558 dwc->resize_fifos = true;
559 dev_dbg(dwc->dev, "resize fifos flag SET\n");
560 }
561 break;
562
563 case USB_STATE_CONFIGURED:
564 ret = dwc3_ep0_delegate_req(dwc, ctrl);
565 if (!cfg && !ret)
566 usb_gadget_set_state(&dwc->gadget,
567 USB_STATE_ADDRESS);
568 break;
569 default:
570 ret = -EINVAL;
571 }
572 return ret;
573}
574
575static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
576{
577 struct dwc3_ep *dep = to_dwc3_ep(ep);
578 struct dwc3 *dwc = dep->dwc;
579
580 u32 param = 0;
581 u32 reg;
582
583 struct timing {
584 u8 u1sel;
585 u8 u1pel;
586 u16 u2sel;
587 u16 u2pel;
588 } __packed timing;
589
590 int ret;
591
592 memcpy(&timing, req->buf, sizeof(timing));
593
594 dwc->u1sel = timing.u1sel;
595 dwc->u1pel = timing.u1pel;
596 dwc->u2sel = le16_to_cpu(timing.u2sel);
597 dwc->u2pel = le16_to_cpu(timing.u2pel);
598
599 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
600 if (reg & DWC3_DCTL_INITU2ENA)
601 param = dwc->u2pel;
602 if (reg & DWC3_DCTL_INITU1ENA)
603 param = dwc->u1pel;
604
605 /*
606 * According to Synopsys Databook, if parameter is
607 * greater than 125, a value of zero should be
608 * programmed in the register.
609 */
610 if (param > 125)
611 param = 0;
612
613 /* now that we have the time, issue DGCMD Set Sel */
614 ret = dwc3_send_gadget_generic_command(dwc,
615 DWC3_DGCMD_SET_PERIODIC_PAR, param);
616 WARN_ON(ret < 0);
617}
618
619static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
620{
621 struct dwc3_ep *dep;
622 enum usb_device_state state = dwc->gadget.state;
623 u16 wLength;
624 u16 wValue;
625
626 if (state == USB_STATE_DEFAULT)
627 return -EINVAL;
628
629 wValue = le16_to_cpu(ctrl->wValue);
630 wLength = le16_to_cpu(ctrl->wLength);
631
632 if (wLength != 6) {
633 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
634 wLength);
635 return -EINVAL;
636 }
637
638 /*
639 * To handle Set SEL we need to receive 6 bytes from Host. So let's
640 * queue a usb_request for 6 bytes.
641 *
642 * Remember, though, this controller can't handle non-wMaxPacketSize
643 * aligned transfers on the OUT direction, so we queue a request for
644 * wMaxPacketSize instead.
645 */
646 dep = dwc->eps[0];
647 dwc->ep0_usb_req.dep = dep;
648 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
649 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
650 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
651
652 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
653}
654
655static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
656{
657 u16 wLength;
658 u16 wValue;
659 u16 wIndex;
660
661 wValue = le16_to_cpu(ctrl->wValue);
662 wLength = le16_to_cpu(ctrl->wLength);
663 wIndex = le16_to_cpu(ctrl->wIndex);
664
665 if (wIndex || wLength)
666 return -EINVAL;
667
668 /*
669 * REVISIT It's unclear from Databook what to do with this
670 * value. For now, just cache it.
671 */
672 dwc->isoch_delay = wValue;
673
674 return 0;
675}
676
677static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
678{
679 int ret;
680
681 switch (ctrl->bRequest) {
682 case USB_REQ_GET_STATUS:
683 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
684 ret = dwc3_ep0_handle_status(dwc, ctrl);
685 break;
686 case USB_REQ_CLEAR_FEATURE:
687 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
688 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
689 break;
690 case USB_REQ_SET_FEATURE:
691 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
692 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
693 break;
694 case USB_REQ_SET_ADDRESS:
695 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
696 ret = dwc3_ep0_set_address(dwc, ctrl);
697 break;
698 case USB_REQ_SET_CONFIGURATION:
699 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
700 ret = dwc3_ep0_set_config(dwc, ctrl);
701 break;
702 case USB_REQ_SET_SEL:
703 dev_vdbg(dwc->dev, "USB_REQ_SET_SEL\n");
704 ret = dwc3_ep0_set_sel(dwc, ctrl);
705 break;
706 case USB_REQ_SET_ISOCH_DELAY:
707 dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY\n");
708 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
709 break;
710 default:
711 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
712 ret = dwc3_ep0_delegate_req(dwc, ctrl);
713 break;
714 }
715
716 return ret;
717}
718
719static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
720 const struct dwc3_event_depevt *event)
721{
722 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
723 int ret = -EINVAL;
724 u32 len;
725
726 if (!dwc->gadget_driver)
727 goto out;
728
729 len = le16_to_cpu(ctrl->wLength);
730 if (!len) {
731 dwc->three_stage_setup = false;
732 dwc->ep0_expect_in = false;
733 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
734 } else {
735 dwc->three_stage_setup = true;
736 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
737 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
738 }
739
740 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
741 ret = dwc3_ep0_std_request(dwc, ctrl);
742 else
743 ret = dwc3_ep0_delegate_req(dwc, ctrl);
744
745 if (ret == USB_GADGET_DELAYED_STATUS)
746 dwc->delayed_status = true;
747
748out:
749 if (ret < 0)
750 dwc3_ep0_stall_and_restart(dwc);
751}
752
753static void dwc3_ep0_complete_data(struct dwc3 *dwc,
754 const struct dwc3_event_depevt *event)
755{
756 struct dwc3_request *r = NULL;
757 struct usb_request *ur;
758 struct dwc3_trb *trb;
759 struct dwc3_ep *ep0;
760 u32 transferred;
761 u32 status;
762 u32 length;
763 u8 epnum;
764
765 epnum = event->endpoint_number;
766 ep0 = dwc->eps[0];
767
768 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
769
770 r = next_request(&ep0->request_list);
771 ur = &r->request;
772
773 trb = dwc->ep0_trb;
774
775 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
776 if (status == DWC3_TRBSTS_SETUP_PENDING) {
777 dev_dbg(dwc->dev, "Setup Pending received\n");
778
779 if (r)
780 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
781
782 return;
783 }
784
785 length = trb->size & DWC3_TRB_SIZE_MASK;
786
787 if (dwc->ep0_bounced) {
788 unsigned transfer_size = ur->length;
789 unsigned maxp = ep0->endpoint.maxpacket;
790
791 transfer_size += (maxp - (transfer_size % maxp));
792 transferred = min_t(u32, ur->length,
793 transfer_size - length);
794 memcpy(ur->buf, dwc->ep0_bounce, transferred);
795 } else {
796 transferred = ur->length - length;
797 }
798
799 ur->actual += transferred;
800
801 if ((epnum & 1) && ur->actual < ur->length) {
802 /* for some reason we did not get everything out */
803
804 dwc3_ep0_stall_and_restart(dwc);
805 } else {
806 /*
807 * handle the case where we have to send a zero packet. This
808 * seems to be case when req.length > maxpacket. Could it be?
809 */
810 if (r)
811 dwc3_gadget_giveback(ep0, r, 0);
812 }
813}
814
815static void dwc3_ep0_complete_status(struct dwc3 *dwc,
816 const struct dwc3_event_depevt *event)
817{
818 struct dwc3_request *r;
819 struct dwc3_ep *dep;
820 struct dwc3_trb *trb;
821 u32 status;
822
823 dep = dwc->eps[0];
824 trb = dwc->ep0_trb;
825
826 if (!list_empty(&dep->request_list)) {
827 r = next_request(&dep->request_list);
828
829 dwc3_gadget_giveback(dep, r, 0);
830 }
831
832 if (dwc->test_mode) {
833 int ret;
834
835 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
836 if (ret < 0) {
837 dev_dbg(dwc->dev, "Invalid Test #%d\n",
838 dwc->test_mode_nr);
839 dwc3_ep0_stall_and_restart(dwc);
840 return;
841 }
842 }
843
844 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
845 if (status == DWC3_TRBSTS_SETUP_PENDING)
846 dev_dbg(dwc->dev, "Setup Pending received\n");
847
848 dwc->ep0state = EP0_SETUP_PHASE;
849 dwc3_ep0_out_start(dwc);
850}
851
852static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
853 const struct dwc3_event_depevt *event)
854{
855 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
856
857 dep->flags &= ~DWC3_EP_BUSY;
858 dep->resource_index = 0;
859 dwc->setup_packet_pending = false;
860
861 switch (dwc->ep0state) {
862 case EP0_SETUP_PHASE:
863 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
864 dwc3_ep0_inspect_setup(dwc, event);
865 break;
866
867 case EP0_DATA_PHASE:
868 dev_vdbg(dwc->dev, "Data Phase\n");
869 dwc3_ep0_complete_data(dwc, event);
870 break;
871
872 case EP0_STATUS_PHASE:
873 dev_vdbg(dwc->dev, "Status Phase\n");
874 dwc3_ep0_complete_status(dwc, event);
875 break;
876 default:
877 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
878 }
879}
880
881static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
882 struct dwc3_ep *dep, struct dwc3_request *req)
883{
884 int ret;
885
886 req->direction = !!dep->number;
887
888 if (req->request.length == 0) {
889 ret = dwc3_ep0_start_trans(dwc, dep->number,
890 dwc->ctrl_req_addr, 0,
891 DWC3_TRBCTL_CONTROL_DATA);
892 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
893 && (dep->number == 0)) {
894 u32 transfer_size;
895 u32 maxpacket;
896
897 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
898 dep->number);
899 if (ret) {
900 dev_dbg(dwc->dev, "failed to map request\n");
901 return;
902 }
903
904 WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE);
905
906 maxpacket = dep->endpoint.maxpacket;
907 transfer_size = roundup(req->request.length, maxpacket);
908
909 dwc->ep0_bounced = true;
910
911 /*
912 * REVISIT in case request length is bigger than
913 * DWC3_EP0_BOUNCE_SIZE we will need two chained
914 * TRBs to handle the transfer.
915 */
916 ret = dwc3_ep0_start_trans(dwc, dep->number,
917 dwc->ep0_bounce_addr, transfer_size,
918 DWC3_TRBCTL_CONTROL_DATA);
919 } else {
920 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
921 dep->number);
922 if (ret) {
923 dev_dbg(dwc->dev, "failed to map request\n");
924 return;
925 }
926
927 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
928 req->request.length, DWC3_TRBCTL_CONTROL_DATA);
929 }
930
931 WARN_ON(ret < 0);
932}
933
934static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
935{
936 struct dwc3 *dwc = dep->dwc;
937 u32 type;
938
939 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
940 : DWC3_TRBCTL_CONTROL_STATUS2;
941
942 return dwc3_ep0_start_trans(dwc, dep->number,
943 dwc->ctrl_req_addr, 0, type);
944}
945
946static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
947{
948 if (dwc->resize_fifos) {
949 dev_dbg(dwc->dev, "starting to resize fifos\n");
950 dwc3_gadget_resize_tx_fifos(dwc);
951 dwc->resize_fifos = 0;
952 }
953
954 WARN_ON(dwc3_ep0_start_control_status(dep));
955}
956
957static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
958 const struct dwc3_event_depevt *event)
959{
960 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
961
962 __dwc3_ep0_do_control_status(dwc, dep);
963}
964
965static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
966{
967 struct dwc3_gadget_ep_cmd_params params;
968 u32 cmd;
969 int ret;
970
971 if (!dep->resource_index)
972 return;
973
974 cmd = DWC3_DEPCMD_ENDTRANSFER;
975 cmd |= DWC3_DEPCMD_CMDIOC;
976 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
977 memset(¶ms, 0, sizeof(params));
978 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
979 WARN_ON_ONCE(ret);
980 dep->resource_index = 0;
981}
982
983static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
984 const struct dwc3_event_depevt *event)
985{
986 dwc->setup_packet_pending = true;
987
988 switch (event->status) {
989 case DEPEVT_STATUS_CONTROL_DATA:
990 dev_vdbg(dwc->dev, "Control Data\n");
991
992 /*
993 * We already have a DATA transfer in the controller's cache,
994 * if we receive a XferNotReady(DATA) we will ignore it, unless
995 * it's for the wrong direction.
996 *
997 * In that case, we must issue END_TRANSFER command to the Data
998 * Phase we already have started and issue SetStall on the
999 * control endpoint.
1000 */
1001 if (dwc->ep0_expect_in != event->endpoint_number) {
1002 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1003
1004 dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
1005 dwc3_ep0_end_control_data(dwc, dep);
1006 dwc3_ep0_stall_and_restart(dwc);
1007 return;
1008 }
1009
1010 break;
1011
1012 case DEPEVT_STATUS_CONTROL_STATUS:
1013 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1014 return;
1015
1016 dev_vdbg(dwc->dev, "Control Status\n");
1017
1018 dwc->ep0state = EP0_STATUS_PHASE;
1019
1020 if (dwc->delayed_status) {
1021 WARN_ON_ONCE(event->endpoint_number != 1);
1022 dev_vdbg(dwc->dev, "Mass Storage delayed status\n");
1023 return;
1024 }
1025
1026 dwc3_ep0_do_control_status(dwc, event);
1027 }
1028}
1029
1030void dwc3_ep0_interrupt(struct dwc3 *dwc,
1031 const struct dwc3_event_depevt *event)
1032{
1033 u8 epnum = event->endpoint_number;
1034
1035 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
1036 dwc3_ep_event_string(event->endpoint_event),
1037 epnum >> 1, (epnum & 1) ? "in" : "out",
1038 dwc3_ep0_state_string(dwc->ep0state));
1039
1040 switch (event->endpoint_event) {
1041 case DWC3_DEPEVT_XFERCOMPLETE:
1042 dwc3_ep0_xfer_complete(dwc, event);
1043 break;
1044
1045 case DWC3_DEPEVT_XFERNOTREADY:
1046 dwc3_ep0_xfernotready(dwc, event);
1047 break;
1048
1049 case DWC3_DEPEVT_XFERINPROGRESS:
1050 case DWC3_DEPEVT_RXTXFIFOEVT:
1051 case DWC3_DEPEVT_STREAMEVT:
1052 case DWC3_DEPEVT_EPCMDCMPLT:
1053 break;
1054 }
1055}