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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/slab.h>
13#include <linux/spinlock.h>
14#include <linux/platform_device.h>
15#include <linux/pm_runtime.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/list.h>
19#include <linux/dma-mapping.h>
20
21#include <linux/usb/ch9.h>
22#include <linux/usb/gadget.h>
23#include <linux/usb/composite.h>
24
25#include "core.h"
26#include "debug.h"
27#include "gadget.h"
28#include "io.h"
29
30static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
32 struct dwc3_ep *dep, struct dwc3_request *req);
33static int dwc3_ep0_delegate_req(struct dwc3 *dwc,
34 struct usb_ctrlrequest *ctrl);
35
36static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
37 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
38{
39 struct dwc3_trb *trb;
40 struct dwc3 *dwc;
41
42 dwc = dep->dwc;
43 trb = &dwc->ep0_trb[dep->trb_enqueue];
44
45 if (chain)
46 dep->trb_enqueue++;
47
48 trb->bpl = lower_32_bits(buf_dma);
49 trb->bph = upper_32_bits(buf_dma);
50 trb->size = len;
51 trb->ctrl = type;
52
53 trb->ctrl |= (DWC3_TRB_CTRL_HWO
54 | DWC3_TRB_CTRL_ISP_IMI);
55
56 if (chain)
57 trb->ctrl |= DWC3_TRB_CTRL_CHN;
58 else
59 trb->ctrl |= (DWC3_TRB_CTRL_IOC
60 | DWC3_TRB_CTRL_LST);
61
62 trace_dwc3_prepare_trb(dep, trb);
63}
64
65static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
66{
67 struct dwc3_gadget_ep_cmd_params params;
68 struct dwc3 *dwc;
69 int ret;
70
71 if (dep->flags & DWC3_EP_TRANSFER_STARTED)
72 return 0;
73
74 dwc = dep->dwc;
75
76 memset(¶ms, 0, sizeof(params));
77 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
78 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
79
80 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms);
81 if (ret < 0)
82 return ret;
83
84 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
85
86 return 0;
87}
88
89static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
90 struct dwc3_request *req)
91{
92 struct dwc3 *dwc = dep->dwc;
93
94 req->request.actual = 0;
95 req->request.status = -EINPROGRESS;
96 req->epnum = dep->number;
97
98 list_add_tail(&req->list, &dep->pending_list);
99
100 /*
101 * Gadget driver might not be quick enough to queue a request
102 * before we get a Transfer Not Ready event on this endpoint.
103 *
104 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
105 * flag is set, it's telling us that as soon as Gadget queues the
106 * required request, we should kick the transfer here because the
107 * IRQ we were waiting for is long gone.
108 */
109 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
110 unsigned int direction;
111
112 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
113
114 if (dwc->ep0state != EP0_DATA_PHASE) {
115 dev_WARN(dwc->dev, "Unexpected pending request\n");
116 return 0;
117 }
118
119 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
120
121 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
122 DWC3_EP0_DIR_IN);
123
124 return 0;
125 }
126
127 /*
128 * In case gadget driver asked us to delay the STATUS phase,
129 * handle it here.
130 */
131 if (dwc->delayed_status) {
132 unsigned int direction;
133
134 direction = !dwc->ep0_expect_in;
135 dwc->delayed_status = false;
136 usb_gadget_set_state(dwc->gadget, USB_STATE_CONFIGURED);
137
138 if (dwc->ep0state == EP0_STATUS_PHASE)
139 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
140
141 return 0;
142 }
143
144 /*
145 * Unfortunately we have uncovered a limitation wrt the Data Phase.
146 *
147 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
148 * come before issueing Start Transfer command, but if we do, we will
149 * miss situations where the host starts another SETUP phase instead of
150 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
151 * Layer Compliance Suite.
152 *
153 * The problem surfaces due to the fact that in case of back-to-back
154 * SETUP packets there will be no XferNotReady(DATA) generated and we
155 * will be stuck waiting for XferNotReady(DATA) forever.
156 *
157 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
158 * it tells us to start Data Phase right away. It also mentions that if
159 * we receive a SETUP phase instead of the DATA phase, core will issue
160 * XferComplete for the DATA phase, before actually initiating it in
161 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
162 * can only be used to print some debugging logs, as the core expects
163 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
164 * just so it completes right away, without transferring anything and,
165 * only then, we can go back to the SETUP phase.
166 *
167 * Because of this scenario, SNPS decided to change the programming
168 * model of control transfers and support on-demand transfers only for
169 * the STATUS phase. To fix the issue we have now, we will always wait
170 * for gadget driver to queue the DATA phase's struct usb_request, then
171 * start it right away.
172 *
173 * If we're actually in a 2-stage transfer, we will wait for
174 * XferNotReady(STATUS).
175 */
176 if (dwc->three_stage_setup) {
177 unsigned int direction;
178
179 direction = dwc->ep0_expect_in;
180 dwc->ep0state = EP0_DATA_PHASE;
181
182 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
183
184 dep->flags &= ~DWC3_EP0_DIR_IN;
185 }
186
187 return 0;
188}
189
190int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
191 gfp_t gfp_flags)
192{
193 struct dwc3_request *req = to_dwc3_request(request);
194 struct dwc3_ep *dep = to_dwc3_ep(ep);
195 struct dwc3 *dwc = dep->dwc;
196
197 unsigned long flags;
198
199 int ret;
200
201 spin_lock_irqsave(&dwc->lock, flags);
202 if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
203 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
204 dep->name);
205 ret = -ESHUTDOWN;
206 goto out;
207 }
208
209 /* we share one TRB for ep0/1 */
210 if (!list_empty(&dep->pending_list)) {
211 ret = -EBUSY;
212 goto out;
213 }
214
215 ret = __dwc3_gadget_ep0_queue(dep, req);
216
217out:
218 spin_unlock_irqrestore(&dwc->lock, flags);
219
220 return ret;
221}
222
223void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
224{
225 struct dwc3_ep *dep;
226
227 /* reinitialize physical ep1 */
228 dep = dwc->eps[1];
229 dep->flags &= DWC3_EP_RESOURCE_ALLOCATED;
230 dep->flags |= DWC3_EP_ENABLED;
231
232 /* stall is always issued on EP0 */
233 dep = dwc->eps[0];
234 __dwc3_gadget_ep_set_halt(dep, 1, false);
235 dep->flags = DWC3_EP_ENABLED;
236 dwc->delayed_status = false;
237
238 if (!list_empty(&dep->pending_list)) {
239 struct dwc3_request *req;
240
241 req = next_request(&dep->pending_list);
242 if (!dwc->connected)
243 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
244 else
245 dwc3_gadget_giveback(dep, req, -ECONNRESET);
246 }
247
248 dwc->eps[0]->trb_enqueue = 0;
249 dwc->eps[1]->trb_enqueue = 0;
250 dwc->ep0state = EP0_SETUP_PHASE;
251 dwc3_ep0_out_start(dwc);
252}
253
254int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
255{
256 struct dwc3_ep *dep = to_dwc3_ep(ep);
257 struct dwc3 *dwc = dep->dwc;
258
259 dwc3_ep0_stall_and_restart(dwc);
260
261 return 0;
262}
263
264int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
265{
266 struct dwc3_ep *dep = to_dwc3_ep(ep);
267 struct dwc3 *dwc = dep->dwc;
268 unsigned long flags;
269 int ret;
270
271 spin_lock_irqsave(&dwc->lock, flags);
272 ret = __dwc3_gadget_ep0_set_halt(ep, value);
273 spin_unlock_irqrestore(&dwc->lock, flags);
274
275 return ret;
276}
277
278void dwc3_ep0_out_start(struct dwc3 *dwc)
279{
280 struct dwc3_ep *dep;
281 int ret;
282 int i;
283
284 complete(&dwc->ep0_in_setup);
285
286 dep = dwc->eps[0];
287 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
288 DWC3_TRBCTL_CONTROL_SETUP, false);
289 ret = dwc3_ep0_start_trans(dep);
290 WARN_ON(ret < 0);
291 for (i = 2; i < DWC3_ENDPOINTS_NUM; i++) {
292 struct dwc3_ep *dwc3_ep;
293
294 dwc3_ep = dwc->eps[i];
295 if (!dwc3_ep)
296 continue;
297
298 if (!(dwc3_ep->flags & DWC3_EP_DELAY_STOP))
299 continue;
300
301 dwc3_ep->flags &= ~DWC3_EP_DELAY_STOP;
302 if (dwc->connected)
303 dwc3_stop_active_transfer(dwc3_ep, true, true);
304 else
305 dwc3_remove_requests(dwc, dwc3_ep, -ESHUTDOWN);
306 }
307}
308
309static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
310{
311 struct dwc3_ep *dep;
312 u32 windex = le16_to_cpu(wIndex_le);
313 u32 epnum;
314
315 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
316 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
317 epnum |= 1;
318
319 dep = dwc->eps[epnum];
320 if (dep == NULL)
321 return NULL;
322
323 if (dep->flags & DWC3_EP_ENABLED)
324 return dep;
325
326 return NULL;
327}
328
329static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
330{
331}
332/*
333 * ch 9.4.5
334 */
335static int dwc3_ep0_handle_status(struct dwc3 *dwc,
336 struct usb_ctrlrequest *ctrl)
337{
338 struct dwc3_ep *dep;
339 u32 recip;
340 u32 value;
341 u32 reg;
342 u16 usb_status = 0;
343 __le16 *response_pkt;
344
345 /* We don't support PTM_STATUS */
346 value = le16_to_cpu(ctrl->wValue);
347 if (value != 0)
348 return -EINVAL;
349
350 recip = ctrl->bRequestType & USB_RECIP_MASK;
351 switch (recip) {
352 case USB_RECIP_DEVICE:
353 /*
354 * LTM will be set once we know how to set this in HW.
355 */
356 usb_status |= dwc->gadget->is_selfpowered;
357
358 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
359 (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
360 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
361 if (reg & DWC3_DCTL_INITU1ENA)
362 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
363 if (reg & DWC3_DCTL_INITU2ENA)
364 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
365 } else {
366 usb_status |= dwc->gadget->wakeup_armed <<
367 USB_DEVICE_REMOTE_WAKEUP;
368 }
369
370 break;
371
372 case USB_RECIP_INTERFACE:
373 /*
374 * Function Remote Wake Capable D0
375 * Function Remote Wakeup D1
376 */
377 return dwc3_ep0_delegate_req(dwc, ctrl);
378
379 case USB_RECIP_ENDPOINT:
380 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
381 if (!dep)
382 return -EINVAL;
383
384 if (dep->flags & DWC3_EP_STALL)
385 usb_status = 1 << USB_ENDPOINT_HALT;
386 break;
387 default:
388 return -EINVAL;
389 }
390
391 response_pkt = (__le16 *) dwc->setup_buf;
392 *response_pkt = cpu_to_le16(usb_status);
393
394 dep = dwc->eps[0];
395 dwc->ep0_usb_req.dep = dep;
396 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
397 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
398 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
399
400 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
401}
402
403static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
404 int set)
405{
406 u32 reg;
407
408 if (state != USB_STATE_CONFIGURED)
409 return -EINVAL;
410 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
411 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
412 return -EINVAL;
413 if (set && dwc->dis_u1_entry_quirk)
414 return -EINVAL;
415
416 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
417 if (set)
418 reg |= DWC3_DCTL_INITU1ENA;
419 else
420 reg &= ~DWC3_DCTL_INITU1ENA;
421 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
422
423 return 0;
424}
425
426static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
427 int set)
428{
429 u32 reg;
430
431
432 if (state != USB_STATE_CONFIGURED)
433 return -EINVAL;
434 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
435 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
436 return -EINVAL;
437 if (set && dwc->dis_u2_entry_quirk)
438 return -EINVAL;
439
440 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
441 if (set)
442 reg |= DWC3_DCTL_INITU2ENA;
443 else
444 reg &= ~DWC3_DCTL_INITU2ENA;
445 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
446
447 return 0;
448}
449
450static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
451 u32 wIndex, int set)
452{
453 if ((wIndex & 0xff) != 0)
454 return -EINVAL;
455 if (!set)
456 return -EINVAL;
457
458 switch (wIndex >> 8) {
459 case USB_TEST_J:
460 case USB_TEST_K:
461 case USB_TEST_SE0_NAK:
462 case USB_TEST_PACKET:
463 case USB_TEST_FORCE_ENABLE:
464 dwc->test_mode_nr = wIndex >> 8;
465 dwc->test_mode = true;
466 break;
467 default:
468 return -EINVAL;
469 }
470
471 return 0;
472}
473
474static int dwc3_ep0_handle_device(struct dwc3 *dwc,
475 struct usb_ctrlrequest *ctrl, int set)
476{
477 enum usb_device_state state;
478 u32 wValue;
479 u32 wIndex;
480 int ret = 0;
481
482 wValue = le16_to_cpu(ctrl->wValue);
483 wIndex = le16_to_cpu(ctrl->wIndex);
484 state = dwc->gadget->state;
485
486 switch (wValue) {
487 case USB_DEVICE_REMOTE_WAKEUP:
488 if (dwc->wakeup_configured)
489 dwc->gadget->wakeup_armed = set;
490 else
491 ret = -EINVAL;
492 break;
493 /*
494 * 9.4.1 says only for SS, in AddressState only for
495 * default control pipe
496 */
497 case USB_DEVICE_U1_ENABLE:
498 ret = dwc3_ep0_handle_u1(dwc, state, set);
499 break;
500 case USB_DEVICE_U2_ENABLE:
501 ret = dwc3_ep0_handle_u2(dwc, state, set);
502 break;
503 case USB_DEVICE_LTM_ENABLE:
504 ret = -EINVAL;
505 break;
506 case USB_DEVICE_TEST_MODE:
507 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
508 break;
509 default:
510 ret = -EINVAL;
511 }
512
513 return ret;
514}
515
516static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
517 struct usb_ctrlrequest *ctrl, int set)
518{
519 u32 wValue;
520 int ret = 0;
521
522 wValue = le16_to_cpu(ctrl->wValue);
523
524 switch (wValue) {
525 case USB_INTRF_FUNC_SUSPEND:
526 ret = dwc3_ep0_delegate_req(dwc, ctrl);
527 break;
528 default:
529 ret = -EINVAL;
530 }
531
532 return ret;
533}
534
535static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
536 struct usb_ctrlrequest *ctrl, int set)
537{
538 struct dwc3_ep *dep;
539 u32 wValue;
540 int ret;
541
542 wValue = le16_to_cpu(ctrl->wValue);
543
544 switch (wValue) {
545 case USB_ENDPOINT_HALT:
546 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
547 if (!dep)
548 return -EINVAL;
549
550 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
551 break;
552
553 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
554 if (ret)
555 return -EINVAL;
556
557 /* ClearFeature(Halt) may need delayed status */
558 if (!set && (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
559 return USB_GADGET_DELAYED_STATUS;
560
561 break;
562 default:
563 return -EINVAL;
564 }
565
566 return 0;
567}
568
569static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
570 struct usb_ctrlrequest *ctrl, int set)
571{
572 u32 recip;
573 int ret;
574
575 recip = ctrl->bRequestType & USB_RECIP_MASK;
576
577 switch (recip) {
578 case USB_RECIP_DEVICE:
579 ret = dwc3_ep0_handle_device(dwc, ctrl, set);
580 break;
581 case USB_RECIP_INTERFACE:
582 ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
583 break;
584 case USB_RECIP_ENDPOINT:
585 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
586 break;
587 default:
588 ret = -EINVAL;
589 }
590
591 return ret;
592}
593
594static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
595{
596 enum usb_device_state state = dwc->gadget->state;
597 u32 addr;
598 u32 reg;
599
600 addr = le16_to_cpu(ctrl->wValue);
601 if (addr > 127) {
602 dev_err(dwc->dev, "invalid device address %d\n", addr);
603 return -EINVAL;
604 }
605
606 if (state == USB_STATE_CONFIGURED) {
607 dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
608 return -EINVAL;
609 }
610
611 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
612 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
613 reg |= DWC3_DCFG_DEVADDR(addr);
614 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
615
616 if (addr)
617 usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS);
618 else
619 usb_gadget_set_state(dwc->gadget, USB_STATE_DEFAULT);
620
621 return 0;
622}
623
624static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
625{
626 int ret = -EINVAL;
627
628 if (dwc->async_callbacks) {
629 spin_unlock(&dwc->lock);
630 ret = dwc->gadget_driver->setup(dwc->gadget, ctrl);
631 spin_lock(&dwc->lock);
632 }
633 return ret;
634}
635
636static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
637{
638 enum usb_device_state state = dwc->gadget->state;
639 u32 cfg;
640 int ret;
641 u32 reg;
642
643 cfg = le16_to_cpu(ctrl->wValue);
644
645 switch (state) {
646 case USB_STATE_DEFAULT:
647 return -EINVAL;
648
649 case USB_STATE_ADDRESS:
650 dwc3_gadget_start_config(dwc, 2);
651 dwc3_gadget_clear_tx_fifos(dwc);
652
653 ret = dwc3_ep0_delegate_req(dwc, ctrl);
654 /* if the cfg matches and the cfg is non zero */
655 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
656
657 /*
658 * only change state if set_config has already
659 * been processed. If gadget driver returns
660 * USB_GADGET_DELAYED_STATUS, we will wait
661 * to change the state on the next usb_ep_queue()
662 */
663 if (ret == 0)
664 usb_gadget_set_state(dwc->gadget,
665 USB_STATE_CONFIGURED);
666
667 /*
668 * Enable transition to U1/U2 state when
669 * nothing is pending from application.
670 */
671 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
672 if (!dwc->dis_u1_entry_quirk)
673 reg |= DWC3_DCTL_ACCEPTU1ENA;
674 if (!dwc->dis_u2_entry_quirk)
675 reg |= DWC3_DCTL_ACCEPTU2ENA;
676 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
677 }
678 break;
679
680 case USB_STATE_CONFIGURED:
681 ret = dwc3_ep0_delegate_req(dwc, ctrl);
682 if (!cfg && !ret)
683 usb_gadget_set_state(dwc->gadget,
684 USB_STATE_ADDRESS);
685 break;
686 default:
687 ret = -EINVAL;
688 }
689 return ret;
690}
691
692static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
693{
694 struct dwc3_ep *dep = to_dwc3_ep(ep);
695 struct dwc3 *dwc = dep->dwc;
696
697 u32 param = 0;
698 u32 reg;
699
700 struct timing {
701 u8 u1sel;
702 u8 u1pel;
703 __le16 u2sel;
704 __le16 u2pel;
705 } __packed timing;
706
707 int ret;
708
709 memcpy(&timing, req->buf, sizeof(timing));
710
711 dwc->u1sel = timing.u1sel;
712 dwc->u1pel = timing.u1pel;
713 dwc->u2sel = le16_to_cpu(timing.u2sel);
714 dwc->u2pel = le16_to_cpu(timing.u2pel);
715
716 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
717 if (reg & DWC3_DCTL_INITU2ENA)
718 param = dwc->u2pel;
719 if (reg & DWC3_DCTL_INITU1ENA)
720 param = dwc->u1pel;
721
722 /*
723 * According to Synopsys Databook, if parameter is
724 * greater than 125, a value of zero should be
725 * programmed in the register.
726 */
727 if (param > 125)
728 param = 0;
729
730 /* now that we have the time, issue DGCMD Set Sel */
731 ret = dwc3_send_gadget_generic_command(dwc,
732 DWC3_DGCMD_SET_PERIODIC_PAR, param);
733 WARN_ON(ret < 0);
734}
735
736static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
737{
738 struct dwc3_ep *dep;
739 enum usb_device_state state = dwc->gadget->state;
740 u16 wLength;
741
742 if (state == USB_STATE_DEFAULT)
743 return -EINVAL;
744
745 wLength = le16_to_cpu(ctrl->wLength);
746
747 if (wLength != 6) {
748 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
749 wLength);
750 return -EINVAL;
751 }
752
753 /*
754 * To handle Set SEL we need to receive 6 bytes from Host. So let's
755 * queue a usb_request for 6 bytes.
756 *
757 * Remember, though, this controller can't handle non-wMaxPacketSize
758 * aligned transfers on the OUT direction, so we queue a request for
759 * wMaxPacketSize instead.
760 */
761 dep = dwc->eps[0];
762 dwc->ep0_usb_req.dep = dep;
763 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
764 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
765 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
766
767 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
768}
769
770static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
771{
772 u16 wLength;
773 u16 wValue;
774 u16 wIndex;
775
776 wValue = le16_to_cpu(ctrl->wValue);
777 wLength = le16_to_cpu(ctrl->wLength);
778 wIndex = le16_to_cpu(ctrl->wIndex);
779
780 if (wIndex || wLength)
781 return -EINVAL;
782
783 dwc->gadget->isoch_delay = wValue;
784
785 return 0;
786}
787
788static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
789{
790 int ret;
791
792 switch (ctrl->bRequest) {
793 case USB_REQ_GET_STATUS:
794 ret = dwc3_ep0_handle_status(dwc, ctrl);
795 break;
796 case USB_REQ_CLEAR_FEATURE:
797 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
798 break;
799 case USB_REQ_SET_FEATURE:
800 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
801 break;
802 case USB_REQ_SET_ADDRESS:
803 ret = dwc3_ep0_set_address(dwc, ctrl);
804 break;
805 case USB_REQ_SET_CONFIGURATION:
806 ret = dwc3_ep0_set_config(dwc, ctrl);
807 break;
808 case USB_REQ_SET_SEL:
809 ret = dwc3_ep0_set_sel(dwc, ctrl);
810 break;
811 case USB_REQ_SET_ISOCH_DELAY:
812 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
813 break;
814 default:
815 ret = dwc3_ep0_delegate_req(dwc, ctrl);
816 break;
817 }
818
819 return ret;
820}
821
822static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
823 const struct dwc3_event_depevt *event)
824{
825 struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
826 int ret = -EINVAL;
827 u32 len;
828
829 if (!dwc->gadget_driver || !dwc->softconnect || !dwc->connected)
830 goto out;
831
832 trace_dwc3_ctrl_req(ctrl);
833
834 len = le16_to_cpu(ctrl->wLength);
835 if (!len) {
836 dwc->three_stage_setup = false;
837 dwc->ep0_expect_in = false;
838 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
839 } else {
840 dwc->three_stage_setup = true;
841 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
842 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
843 }
844
845 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
846 ret = dwc3_ep0_std_request(dwc, ctrl);
847 else
848 ret = dwc3_ep0_delegate_req(dwc, ctrl);
849
850 if (ret == USB_GADGET_DELAYED_STATUS)
851 dwc->delayed_status = true;
852
853out:
854 if (ret < 0)
855 dwc3_ep0_stall_and_restart(dwc);
856}
857
858static void dwc3_ep0_complete_data(struct dwc3 *dwc,
859 const struct dwc3_event_depevt *event)
860{
861 struct dwc3_request *r;
862 struct usb_request *ur;
863 struct dwc3_trb *trb;
864 struct dwc3_ep *ep0;
865 u32 transferred = 0;
866 u32 status;
867 u32 length;
868 u8 epnum;
869
870 epnum = event->endpoint_number;
871 ep0 = dwc->eps[0];
872
873 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
874 trb = dwc->ep0_trb;
875 trace_dwc3_complete_trb(ep0, trb);
876
877 r = next_request(&ep0->pending_list);
878 if (!r)
879 return;
880
881 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
882 if (status == DWC3_TRBSTS_SETUP_PENDING) {
883 dwc->setup_packet_pending = true;
884 if (r)
885 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
886
887 return;
888 }
889
890 ur = &r->request;
891
892 length = trb->size & DWC3_TRB_SIZE_MASK;
893 transferred = ur->length - length;
894 ur->actual += transferred;
895
896 if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
897 ur->length && ur->zero) || dwc->ep0_bounced) {
898 trb++;
899 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
900 trace_dwc3_complete_trb(ep0, trb);
901
902 if (r->direction)
903 dwc->eps[1]->trb_enqueue = 0;
904 else
905 dwc->eps[0]->trb_enqueue = 0;
906
907 dwc->ep0_bounced = false;
908 }
909
910 if ((epnum & 1) && ur->actual < ur->length)
911 dwc3_ep0_stall_and_restart(dwc);
912 else
913 dwc3_gadget_giveback(ep0, r, 0);
914}
915
916static void dwc3_ep0_complete_status(struct dwc3 *dwc,
917 const struct dwc3_event_depevt *event)
918{
919 struct dwc3_request *r;
920 struct dwc3_ep *dep;
921 struct dwc3_trb *trb;
922 u32 status;
923
924 dep = dwc->eps[0];
925 trb = dwc->ep0_trb;
926
927 trace_dwc3_complete_trb(dep, trb);
928
929 if (!list_empty(&dep->pending_list)) {
930 r = next_request(&dep->pending_list);
931
932 dwc3_gadget_giveback(dep, r, 0);
933 }
934
935 if (dwc->test_mode) {
936 int ret;
937
938 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
939 if (ret < 0) {
940 dev_err(dwc->dev, "invalid test #%d\n",
941 dwc->test_mode_nr);
942 dwc3_ep0_stall_and_restart(dwc);
943 return;
944 }
945 }
946
947 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
948 if (status == DWC3_TRBSTS_SETUP_PENDING)
949 dwc->setup_packet_pending = true;
950
951 dwc->ep0state = EP0_SETUP_PHASE;
952 dwc3_ep0_out_start(dwc);
953}
954
955static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
956 const struct dwc3_event_depevt *event)
957{
958 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
959
960 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
961 dep->resource_index = 0;
962 dwc->setup_packet_pending = false;
963
964 switch (dwc->ep0state) {
965 case EP0_SETUP_PHASE:
966 dwc3_ep0_inspect_setup(dwc, event);
967 break;
968
969 case EP0_DATA_PHASE:
970 dwc3_ep0_complete_data(dwc, event);
971 break;
972
973 case EP0_STATUS_PHASE:
974 dwc3_ep0_complete_status(dwc, event);
975 break;
976 default:
977 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
978 }
979}
980
981static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
982 struct dwc3_ep *dep, struct dwc3_request *req)
983{
984 unsigned int trb_length = 0;
985 int ret;
986
987 req->direction = !!dep->number;
988
989 if (req->request.length == 0) {
990 if (!req->direction)
991 trb_length = dep->endpoint.maxpacket;
992
993 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length,
994 DWC3_TRBCTL_CONTROL_DATA, false);
995 ret = dwc3_ep0_start_trans(dep);
996 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
997 && (dep->number == 0)) {
998 u32 maxpacket;
999 u32 rem;
1000
1001 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1002 &req->request, dep->number);
1003 if (ret)
1004 return;
1005
1006 maxpacket = dep->endpoint.maxpacket;
1007 rem = req->request.length % maxpacket;
1008 dwc->ep0_bounced = true;
1009
1010 /* prepare normal TRB */
1011 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1012 req->request.length,
1013 DWC3_TRBCTL_CONTROL_DATA,
1014 true);
1015
1016 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1017
1018 /* Now prepare one extra TRB to align transfer size */
1019 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1020 maxpacket - rem,
1021 DWC3_TRBCTL_CONTROL_DATA,
1022 false);
1023 ret = dwc3_ep0_start_trans(dep);
1024 } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
1025 req->request.length && req->request.zero) {
1026
1027 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1028 &req->request, dep->number);
1029 if (ret)
1030 return;
1031
1032 /* prepare normal TRB */
1033 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1034 req->request.length,
1035 DWC3_TRBCTL_CONTROL_DATA,
1036 true);
1037
1038 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1039
1040 if (!req->direction)
1041 trb_length = dep->endpoint.maxpacket;
1042
1043 /* Now prepare one extra TRB to align transfer size */
1044 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1045 trb_length, DWC3_TRBCTL_CONTROL_DATA,
1046 false);
1047 ret = dwc3_ep0_start_trans(dep);
1048 } else {
1049 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1050 &req->request, dep->number);
1051 if (ret)
1052 return;
1053
1054 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1055 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1056 false);
1057
1058 req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1059
1060 ret = dwc3_ep0_start_trans(dep);
1061 }
1062
1063 WARN_ON(ret < 0);
1064}
1065
1066static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1067{
1068 struct dwc3 *dwc = dep->dwc;
1069 u32 type;
1070
1071 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1072 : DWC3_TRBCTL_CONTROL_STATUS2;
1073
1074 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1075 return dwc3_ep0_start_trans(dep);
1076}
1077
1078static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1079{
1080 WARN_ON(dwc3_ep0_start_control_status(dep));
1081}
1082
1083static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1084 const struct dwc3_event_depevt *event)
1085{
1086 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1087
1088 __dwc3_ep0_do_control_status(dwc, dep);
1089}
1090
1091void dwc3_ep0_send_delayed_status(struct dwc3 *dwc)
1092{
1093 unsigned int direction = !dwc->ep0_expect_in;
1094
1095 dwc->delayed_status = false;
1096 dwc->clear_stall_protocol = 0;
1097
1098 if (dwc->ep0state != EP0_STATUS_PHASE)
1099 return;
1100
1101 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
1102}
1103
1104void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1105{
1106 struct dwc3_gadget_ep_cmd_params params;
1107 u32 cmd;
1108 int ret;
1109
1110 /*
1111 * For status/DATA OUT stage, TRB will be queued on ep0 out
1112 * endpoint for which resource index is zero. Hence allow
1113 * queuing ENDXFER command for ep0 out endpoint.
1114 */
1115 if (!dep->resource_index && dep->number)
1116 return;
1117
1118 cmd = DWC3_DEPCMD_ENDTRANSFER;
1119 cmd |= DWC3_DEPCMD_CMDIOC;
1120 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1121 memset(¶ms, 0, sizeof(params));
1122 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1123 WARN_ON_ONCE(ret);
1124 dep->resource_index = 0;
1125}
1126
1127static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1128 const struct dwc3_event_depevt *event)
1129{
1130 switch (event->status) {
1131 case DEPEVT_STATUS_CONTROL_DATA:
1132 if (!dwc->softconnect || !dwc->connected)
1133 return;
1134 /*
1135 * We already have a DATA transfer in the controller's cache,
1136 * if we receive a XferNotReady(DATA) we will ignore it, unless
1137 * it's for the wrong direction.
1138 *
1139 * In that case, we must issue END_TRANSFER command to the Data
1140 * Phase we already have started and issue SetStall on the
1141 * control endpoint.
1142 */
1143 if (dwc->ep0_expect_in != event->endpoint_number) {
1144 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1145
1146 dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1147 dwc3_ep0_end_control_data(dwc, dep);
1148 dwc3_ep0_stall_and_restart(dwc);
1149 return;
1150 }
1151
1152 break;
1153
1154 case DEPEVT_STATUS_CONTROL_STATUS:
1155 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1156 return;
1157
1158 if (dwc->setup_packet_pending) {
1159 dwc3_ep0_stall_and_restart(dwc);
1160 return;
1161 }
1162
1163 dwc->ep0state = EP0_STATUS_PHASE;
1164
1165 if (dwc->delayed_status) {
1166 struct dwc3_ep *dep = dwc->eps[0];
1167
1168 WARN_ON_ONCE(event->endpoint_number != 1);
1169 /*
1170 * We should handle the delay STATUS phase here if the
1171 * request for handling delay STATUS has been queued
1172 * into the list.
1173 */
1174 if (!list_empty(&dep->pending_list)) {
1175 dwc->delayed_status = false;
1176 usb_gadget_set_state(dwc->gadget,
1177 USB_STATE_CONFIGURED);
1178 dwc3_ep0_do_control_status(dwc, event);
1179 }
1180
1181 return;
1182 }
1183
1184 dwc3_ep0_do_control_status(dwc, event);
1185 }
1186}
1187
1188void dwc3_ep0_interrupt(struct dwc3 *dwc,
1189 const struct dwc3_event_depevt *event)
1190{
1191 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1192 u8 cmd;
1193
1194 switch (event->endpoint_event) {
1195 case DWC3_DEPEVT_XFERCOMPLETE:
1196 dwc3_ep0_xfer_complete(dwc, event);
1197 break;
1198
1199 case DWC3_DEPEVT_XFERNOTREADY:
1200 dwc3_ep0_xfernotready(dwc, event);
1201 break;
1202
1203 case DWC3_DEPEVT_XFERINPROGRESS:
1204 case DWC3_DEPEVT_RXTXFIFOEVT:
1205 case DWC3_DEPEVT_STREAMEVT:
1206 break;
1207 case DWC3_DEPEVT_EPCMDCMPLT:
1208 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
1209
1210 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
1211 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
1212 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1213 }
1214 break;
1215 default:
1216 dev_err(dwc->dev, "unknown endpoint event %d\n", event->endpoint_event);
1217 break;
1218 }
1219}