Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/slab.h>
13#include <linux/spinlock.h>
14#include <linux/platform_device.h>
15#include <linux/pm_runtime.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/list.h>
19#include <linux/dma-mapping.h>
20
21#include <linux/usb/ch9.h>
22#include <linux/usb/gadget.h>
23#include <linux/usb/composite.h>
24
25#include "core.h"
26#include "debug.h"
27#include "gadget.h"
28#include "io.h"
29
30static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
32 struct dwc3_ep *dep, struct dwc3_request *req);
33
34static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
35 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
36{
37 struct dwc3_trb *trb;
38 struct dwc3 *dwc;
39
40 dwc = dep->dwc;
41 trb = &dwc->ep0_trb[dep->trb_enqueue];
42
43 if (chain)
44 dep->trb_enqueue++;
45
46 trb->bpl = lower_32_bits(buf_dma);
47 trb->bph = upper_32_bits(buf_dma);
48 trb->size = len;
49 trb->ctrl = type;
50
51 trb->ctrl |= (DWC3_TRB_CTRL_HWO
52 | DWC3_TRB_CTRL_ISP_IMI);
53
54 if (chain)
55 trb->ctrl |= DWC3_TRB_CTRL_CHN;
56 else
57 trb->ctrl |= (DWC3_TRB_CTRL_IOC
58 | DWC3_TRB_CTRL_LST);
59
60 trace_dwc3_prepare_trb(dep, trb);
61}
62
63static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
64{
65 struct dwc3_gadget_ep_cmd_params params;
66 struct dwc3 *dwc;
67 int ret;
68
69 if (dep->flags & DWC3_EP_TRANSFER_STARTED)
70 return 0;
71
72 dwc = dep->dwc;
73
74 memset(¶ms, 0, sizeof(params));
75 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
76 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
77
78 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms);
79 if (ret < 0)
80 return ret;
81
82 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
83
84 return 0;
85}
86
87static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
88 struct dwc3_request *req)
89{
90 struct dwc3 *dwc = dep->dwc;
91
92 req->request.actual = 0;
93 req->request.status = -EINPROGRESS;
94 req->epnum = dep->number;
95
96 list_add_tail(&req->list, &dep->pending_list);
97
98 /*
99 * Gadget driver might not be quick enough to queue a request
100 * before we get a Transfer Not Ready event on this endpoint.
101 *
102 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
103 * flag is set, it's telling us that as soon as Gadget queues the
104 * required request, we should kick the transfer here because the
105 * IRQ we were waiting for is long gone.
106 */
107 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
108 unsigned direction;
109
110 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
111
112 if (dwc->ep0state != EP0_DATA_PHASE) {
113 dev_WARN(dwc->dev, "Unexpected pending request\n");
114 return 0;
115 }
116
117 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
118
119 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
120 DWC3_EP0_DIR_IN);
121
122 return 0;
123 }
124
125 /*
126 * In case gadget driver asked us to delay the STATUS phase,
127 * handle it here.
128 */
129 if (dwc->delayed_status) {
130 unsigned direction;
131
132 direction = !dwc->ep0_expect_in;
133 dwc->delayed_status = false;
134 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
135
136 if (dwc->ep0state == EP0_STATUS_PHASE)
137 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
138
139 return 0;
140 }
141
142 /*
143 * Unfortunately we have uncovered a limitation wrt the Data Phase.
144 *
145 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
146 * come before issueing Start Transfer command, but if we do, we will
147 * miss situations where the host starts another SETUP phase instead of
148 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
149 * Layer Compliance Suite.
150 *
151 * The problem surfaces due to the fact that in case of back-to-back
152 * SETUP packets there will be no XferNotReady(DATA) generated and we
153 * will be stuck waiting for XferNotReady(DATA) forever.
154 *
155 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
156 * it tells us to start Data Phase right away. It also mentions that if
157 * we receive a SETUP phase instead of the DATA phase, core will issue
158 * XferComplete for the DATA phase, before actually initiating it in
159 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
160 * can only be used to print some debugging logs, as the core expects
161 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
162 * just so it completes right away, without transferring anything and,
163 * only then, we can go back to the SETUP phase.
164 *
165 * Because of this scenario, SNPS decided to change the programming
166 * model of control transfers and support on-demand transfers only for
167 * the STATUS phase. To fix the issue we have now, we will always wait
168 * for gadget driver to queue the DATA phase's struct usb_request, then
169 * start it right away.
170 *
171 * If we're actually in a 2-stage transfer, we will wait for
172 * XferNotReady(STATUS).
173 */
174 if (dwc->three_stage_setup) {
175 unsigned direction;
176
177 direction = dwc->ep0_expect_in;
178 dwc->ep0state = EP0_DATA_PHASE;
179
180 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
181
182 dep->flags &= ~DWC3_EP0_DIR_IN;
183 }
184
185 return 0;
186}
187
188int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
189 gfp_t gfp_flags)
190{
191 struct dwc3_request *req = to_dwc3_request(request);
192 struct dwc3_ep *dep = to_dwc3_ep(ep);
193 struct dwc3 *dwc = dep->dwc;
194
195 unsigned long flags;
196
197 int ret;
198
199 spin_lock_irqsave(&dwc->lock, flags);
200 if (!dep->endpoint.desc) {
201 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
202 dep->name);
203 ret = -ESHUTDOWN;
204 goto out;
205 }
206
207 /* we share one TRB for ep0/1 */
208 if (!list_empty(&dep->pending_list)) {
209 ret = -EBUSY;
210 goto out;
211 }
212
213 ret = __dwc3_gadget_ep0_queue(dep, req);
214
215out:
216 spin_unlock_irqrestore(&dwc->lock, flags);
217
218 return ret;
219}
220
221static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
222{
223 struct dwc3_ep *dep;
224
225 /* reinitialize physical ep1 */
226 dep = dwc->eps[1];
227 dep->flags = DWC3_EP_ENABLED;
228
229 /* stall is always issued on EP0 */
230 dep = dwc->eps[0];
231 __dwc3_gadget_ep_set_halt(dep, 1, false);
232 dep->flags = DWC3_EP_ENABLED;
233 dwc->delayed_status = false;
234
235 if (!list_empty(&dep->pending_list)) {
236 struct dwc3_request *req;
237
238 req = next_request(&dep->pending_list);
239 dwc3_gadget_giveback(dep, req, -ECONNRESET);
240 }
241
242 dwc->ep0state = EP0_SETUP_PHASE;
243 dwc3_ep0_out_start(dwc);
244}
245
246int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
247{
248 struct dwc3_ep *dep = to_dwc3_ep(ep);
249 struct dwc3 *dwc = dep->dwc;
250
251 dwc3_ep0_stall_and_restart(dwc);
252
253 return 0;
254}
255
256int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
257{
258 struct dwc3_ep *dep = to_dwc3_ep(ep);
259 struct dwc3 *dwc = dep->dwc;
260 unsigned long flags;
261 int ret;
262
263 spin_lock_irqsave(&dwc->lock, flags);
264 ret = __dwc3_gadget_ep0_set_halt(ep, value);
265 spin_unlock_irqrestore(&dwc->lock, flags);
266
267 return ret;
268}
269
270void dwc3_ep0_out_start(struct dwc3 *dwc)
271{
272 struct dwc3_ep *dep;
273 int ret;
274
275 complete(&dwc->ep0_in_setup);
276
277 dep = dwc->eps[0];
278 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
279 DWC3_TRBCTL_CONTROL_SETUP, false);
280 ret = dwc3_ep0_start_trans(dep);
281 WARN_ON(ret < 0);
282}
283
284static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
285{
286 struct dwc3_ep *dep;
287 u32 windex = le16_to_cpu(wIndex_le);
288 u32 epnum;
289
290 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
291 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
292 epnum |= 1;
293
294 dep = dwc->eps[epnum];
295 if (dep->flags & DWC3_EP_ENABLED)
296 return dep;
297
298 return NULL;
299}
300
301static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
302{
303}
304/*
305 * ch 9.4.5
306 */
307static int dwc3_ep0_handle_status(struct dwc3 *dwc,
308 struct usb_ctrlrequest *ctrl)
309{
310 struct dwc3_ep *dep;
311 u32 recip;
312 u32 value;
313 u32 reg;
314 u16 usb_status = 0;
315 __le16 *response_pkt;
316
317 /* We don't support PTM_STATUS */
318 value = le16_to_cpu(ctrl->wValue);
319 if (value != 0)
320 return -EINVAL;
321
322 recip = ctrl->bRequestType & USB_RECIP_MASK;
323 switch (recip) {
324 case USB_RECIP_DEVICE:
325 /*
326 * LTM will be set once we know how to set this in HW.
327 */
328 usb_status |= dwc->gadget.is_selfpowered;
329
330 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
331 (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
332 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
333 if (reg & DWC3_DCTL_INITU1ENA)
334 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
335 if (reg & DWC3_DCTL_INITU2ENA)
336 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
337 }
338
339 break;
340
341 case USB_RECIP_INTERFACE:
342 /*
343 * Function Remote Wake Capable D0
344 * Function Remote Wakeup D1
345 */
346 break;
347
348 case USB_RECIP_ENDPOINT:
349 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
350 if (!dep)
351 return -EINVAL;
352
353 if (dep->flags & DWC3_EP_STALL)
354 usb_status = 1 << USB_ENDPOINT_HALT;
355 break;
356 default:
357 return -EINVAL;
358 }
359
360 response_pkt = (__le16 *) dwc->setup_buf;
361 *response_pkt = cpu_to_le16(usb_status);
362
363 dep = dwc->eps[0];
364 dwc->ep0_usb_req.dep = dep;
365 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
366 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
367 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
368
369 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
370}
371
372static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
373 int set)
374{
375 u32 reg;
376
377 if (state != USB_STATE_CONFIGURED)
378 return -EINVAL;
379 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
380 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
381 return -EINVAL;
382 if (set && dwc->dis_u1_entry_quirk)
383 return -EINVAL;
384
385 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
386 if (set)
387 reg |= DWC3_DCTL_INITU1ENA;
388 else
389 reg &= ~DWC3_DCTL_INITU1ENA;
390 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
391
392 return 0;
393}
394
395static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
396 int set)
397{
398 u32 reg;
399
400
401 if (state != USB_STATE_CONFIGURED)
402 return -EINVAL;
403 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
404 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
405 return -EINVAL;
406 if (set && dwc->dis_u2_entry_quirk)
407 return -EINVAL;
408
409 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
410 if (set)
411 reg |= DWC3_DCTL_INITU2ENA;
412 else
413 reg &= ~DWC3_DCTL_INITU2ENA;
414 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
415
416 return 0;
417}
418
419static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
420 u32 wIndex, int set)
421{
422 if ((wIndex & 0xff) != 0)
423 return -EINVAL;
424 if (!set)
425 return -EINVAL;
426
427 switch (wIndex >> 8) {
428 case TEST_J:
429 case TEST_K:
430 case TEST_SE0_NAK:
431 case TEST_PACKET:
432 case TEST_FORCE_EN:
433 dwc->test_mode_nr = wIndex >> 8;
434 dwc->test_mode = true;
435 break;
436 default:
437 return -EINVAL;
438 }
439
440 return 0;
441}
442
443static int dwc3_ep0_handle_device(struct dwc3 *dwc,
444 struct usb_ctrlrequest *ctrl, int set)
445{
446 enum usb_device_state state;
447 u32 wValue;
448 u32 wIndex;
449 int ret = 0;
450
451 wValue = le16_to_cpu(ctrl->wValue);
452 wIndex = le16_to_cpu(ctrl->wIndex);
453 state = dwc->gadget.state;
454
455 switch (wValue) {
456 case USB_DEVICE_REMOTE_WAKEUP:
457 break;
458 /*
459 * 9.4.1 says only only for SS, in AddressState only for
460 * default control pipe
461 */
462 case USB_DEVICE_U1_ENABLE:
463 ret = dwc3_ep0_handle_u1(dwc, state, set);
464 break;
465 case USB_DEVICE_U2_ENABLE:
466 ret = dwc3_ep0_handle_u2(dwc, state, set);
467 break;
468 case USB_DEVICE_LTM_ENABLE:
469 ret = -EINVAL;
470 break;
471 case USB_DEVICE_TEST_MODE:
472 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
473 break;
474 default:
475 ret = -EINVAL;
476 }
477
478 return ret;
479}
480
481static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
482 struct usb_ctrlrequest *ctrl, int set)
483{
484 u32 wValue;
485 int ret = 0;
486
487 wValue = le16_to_cpu(ctrl->wValue);
488
489 switch (wValue) {
490 case USB_INTRF_FUNC_SUSPEND:
491 /*
492 * REVISIT: Ideally we would enable some low power mode here,
493 * however it's unclear what we should be doing here.
494 *
495 * For now, we're not doing anything, just making sure we return
496 * 0 so USB Command Verifier tests pass without any errors.
497 */
498 break;
499 default:
500 ret = -EINVAL;
501 }
502
503 return ret;
504}
505
506static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
507 struct usb_ctrlrequest *ctrl, int set)
508{
509 struct dwc3_ep *dep;
510 u32 wValue;
511 int ret;
512
513 wValue = le16_to_cpu(ctrl->wValue);
514
515 switch (wValue) {
516 case USB_ENDPOINT_HALT:
517 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
518 if (!dep)
519 return -EINVAL;
520
521 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
522 break;
523
524 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
525 if (ret)
526 return -EINVAL;
527 break;
528 default:
529 return -EINVAL;
530 }
531
532 return 0;
533}
534
535static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
536 struct usb_ctrlrequest *ctrl, int set)
537{
538 u32 recip;
539 int ret;
540
541 recip = ctrl->bRequestType & USB_RECIP_MASK;
542
543 switch (recip) {
544 case USB_RECIP_DEVICE:
545 ret = dwc3_ep0_handle_device(dwc, ctrl, set);
546 break;
547 case USB_RECIP_INTERFACE:
548 ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
549 break;
550 case USB_RECIP_ENDPOINT:
551 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
552 break;
553 default:
554 ret = -EINVAL;
555 }
556
557 return ret;
558}
559
560static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
561{
562 enum usb_device_state state = dwc->gadget.state;
563 u32 addr;
564 u32 reg;
565
566 addr = le16_to_cpu(ctrl->wValue);
567 if (addr > 127) {
568 dev_err(dwc->dev, "invalid device address %d\n", addr);
569 return -EINVAL;
570 }
571
572 if (state == USB_STATE_CONFIGURED) {
573 dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
574 return -EINVAL;
575 }
576
577 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
578 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
579 reg |= DWC3_DCFG_DEVADDR(addr);
580 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
581
582 if (addr)
583 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
584 else
585 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
586
587 return 0;
588}
589
590static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
591{
592 int ret;
593
594 spin_unlock(&dwc->lock);
595 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
596 spin_lock(&dwc->lock);
597 return ret;
598}
599
600static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
601{
602 enum usb_device_state state = dwc->gadget.state;
603 u32 cfg;
604 int ret;
605 u32 reg;
606
607 cfg = le16_to_cpu(ctrl->wValue);
608
609 switch (state) {
610 case USB_STATE_DEFAULT:
611 return -EINVAL;
612
613 case USB_STATE_ADDRESS:
614 ret = dwc3_ep0_delegate_req(dwc, ctrl);
615 /* if the cfg matches and the cfg is non zero */
616 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
617
618 /*
619 * only change state if set_config has already
620 * been processed. If gadget driver returns
621 * USB_GADGET_DELAYED_STATUS, we will wait
622 * to change the state on the next usb_ep_queue()
623 */
624 if (ret == 0)
625 usb_gadget_set_state(&dwc->gadget,
626 USB_STATE_CONFIGURED);
627
628 /*
629 * Enable transition to U1/U2 state when
630 * nothing is pending from application.
631 */
632 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
633 if (!dwc->dis_u1_entry_quirk)
634 reg |= DWC3_DCTL_ACCEPTU1ENA;
635 if (!dwc->dis_u2_entry_quirk)
636 reg |= DWC3_DCTL_ACCEPTU2ENA;
637 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
638 }
639 break;
640
641 case USB_STATE_CONFIGURED:
642 ret = dwc3_ep0_delegate_req(dwc, ctrl);
643 if (!cfg && !ret)
644 usb_gadget_set_state(&dwc->gadget,
645 USB_STATE_ADDRESS);
646 break;
647 default:
648 ret = -EINVAL;
649 }
650 return ret;
651}
652
653static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
654{
655 struct dwc3_ep *dep = to_dwc3_ep(ep);
656 struct dwc3 *dwc = dep->dwc;
657
658 u32 param = 0;
659 u32 reg;
660
661 struct timing {
662 u8 u1sel;
663 u8 u1pel;
664 __le16 u2sel;
665 __le16 u2pel;
666 } __packed timing;
667
668 int ret;
669
670 memcpy(&timing, req->buf, sizeof(timing));
671
672 dwc->u1sel = timing.u1sel;
673 dwc->u1pel = timing.u1pel;
674 dwc->u2sel = le16_to_cpu(timing.u2sel);
675 dwc->u2pel = le16_to_cpu(timing.u2pel);
676
677 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
678 if (reg & DWC3_DCTL_INITU2ENA)
679 param = dwc->u2pel;
680 if (reg & DWC3_DCTL_INITU1ENA)
681 param = dwc->u1pel;
682
683 /*
684 * According to Synopsys Databook, if parameter is
685 * greater than 125, a value of zero should be
686 * programmed in the register.
687 */
688 if (param > 125)
689 param = 0;
690
691 /* now that we have the time, issue DGCMD Set Sel */
692 ret = dwc3_send_gadget_generic_command(dwc,
693 DWC3_DGCMD_SET_PERIODIC_PAR, param);
694 WARN_ON(ret < 0);
695}
696
697static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
698{
699 struct dwc3_ep *dep;
700 enum usb_device_state state = dwc->gadget.state;
701 u16 wLength;
702
703 if (state == USB_STATE_DEFAULT)
704 return -EINVAL;
705
706 wLength = le16_to_cpu(ctrl->wLength);
707
708 if (wLength != 6) {
709 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
710 wLength);
711 return -EINVAL;
712 }
713
714 /*
715 * To handle Set SEL we need to receive 6 bytes from Host. So let's
716 * queue a usb_request for 6 bytes.
717 *
718 * Remember, though, this controller can't handle non-wMaxPacketSize
719 * aligned transfers on the OUT direction, so we queue a request for
720 * wMaxPacketSize instead.
721 */
722 dep = dwc->eps[0];
723 dwc->ep0_usb_req.dep = dep;
724 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
725 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
726 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
727
728 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
729}
730
731static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
732{
733 u16 wLength;
734 u16 wValue;
735 u16 wIndex;
736
737 wValue = le16_to_cpu(ctrl->wValue);
738 wLength = le16_to_cpu(ctrl->wLength);
739 wIndex = le16_to_cpu(ctrl->wIndex);
740
741 if (wIndex || wLength)
742 return -EINVAL;
743
744 dwc->gadget.isoch_delay = wValue;
745
746 return 0;
747}
748
749static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
750{
751 int ret;
752
753 switch (ctrl->bRequest) {
754 case USB_REQ_GET_STATUS:
755 ret = dwc3_ep0_handle_status(dwc, ctrl);
756 break;
757 case USB_REQ_CLEAR_FEATURE:
758 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
759 break;
760 case USB_REQ_SET_FEATURE:
761 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
762 break;
763 case USB_REQ_SET_ADDRESS:
764 ret = dwc3_ep0_set_address(dwc, ctrl);
765 break;
766 case USB_REQ_SET_CONFIGURATION:
767 ret = dwc3_ep0_set_config(dwc, ctrl);
768 break;
769 case USB_REQ_SET_SEL:
770 ret = dwc3_ep0_set_sel(dwc, ctrl);
771 break;
772 case USB_REQ_SET_ISOCH_DELAY:
773 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
774 break;
775 default:
776 ret = dwc3_ep0_delegate_req(dwc, ctrl);
777 break;
778 }
779
780 return ret;
781}
782
783static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
784 const struct dwc3_event_depevt *event)
785{
786 struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
787 int ret = -EINVAL;
788 u32 len;
789
790 if (!dwc->gadget_driver)
791 goto out;
792
793 trace_dwc3_ctrl_req(ctrl);
794
795 len = le16_to_cpu(ctrl->wLength);
796 if (!len) {
797 dwc->three_stage_setup = false;
798 dwc->ep0_expect_in = false;
799 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
800 } else {
801 dwc->three_stage_setup = true;
802 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
803 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
804 }
805
806 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
807 ret = dwc3_ep0_std_request(dwc, ctrl);
808 else
809 ret = dwc3_ep0_delegate_req(dwc, ctrl);
810
811 if (ret == USB_GADGET_DELAYED_STATUS)
812 dwc->delayed_status = true;
813
814out:
815 if (ret < 0)
816 dwc3_ep0_stall_and_restart(dwc);
817}
818
819static void dwc3_ep0_complete_data(struct dwc3 *dwc,
820 const struct dwc3_event_depevt *event)
821{
822 struct dwc3_request *r;
823 struct usb_request *ur;
824 struct dwc3_trb *trb;
825 struct dwc3_ep *ep0;
826 u32 transferred = 0;
827 u32 status;
828 u32 length;
829 u8 epnum;
830
831 epnum = event->endpoint_number;
832 ep0 = dwc->eps[0];
833
834 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
835 trb = dwc->ep0_trb;
836 trace_dwc3_complete_trb(ep0, trb);
837
838 r = next_request(&ep0->pending_list);
839 if (!r)
840 return;
841
842 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
843 if (status == DWC3_TRBSTS_SETUP_PENDING) {
844 dwc->setup_packet_pending = true;
845 if (r)
846 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
847
848 return;
849 }
850
851 ur = &r->request;
852
853 length = trb->size & DWC3_TRB_SIZE_MASK;
854 transferred = ur->length - length;
855 ur->actual += transferred;
856
857 if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
858 ur->length && ur->zero) || dwc->ep0_bounced) {
859 trb++;
860 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
861 trace_dwc3_complete_trb(ep0, trb);
862
863 if (r->direction)
864 dwc->eps[1]->trb_enqueue = 0;
865 else
866 dwc->eps[0]->trb_enqueue = 0;
867
868 dwc->ep0_bounced = false;
869 }
870
871 if ((epnum & 1) && ur->actual < ur->length)
872 dwc3_ep0_stall_and_restart(dwc);
873 else
874 dwc3_gadget_giveback(ep0, r, 0);
875}
876
877static void dwc3_ep0_complete_status(struct dwc3 *dwc,
878 const struct dwc3_event_depevt *event)
879{
880 struct dwc3_request *r;
881 struct dwc3_ep *dep;
882 struct dwc3_trb *trb;
883 u32 status;
884
885 dep = dwc->eps[0];
886 trb = dwc->ep0_trb;
887
888 trace_dwc3_complete_trb(dep, trb);
889
890 if (!list_empty(&dep->pending_list)) {
891 r = next_request(&dep->pending_list);
892
893 dwc3_gadget_giveback(dep, r, 0);
894 }
895
896 if (dwc->test_mode) {
897 int ret;
898
899 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
900 if (ret < 0) {
901 dev_err(dwc->dev, "invalid test #%d\n",
902 dwc->test_mode_nr);
903 dwc3_ep0_stall_and_restart(dwc);
904 return;
905 }
906 }
907
908 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
909 if (status == DWC3_TRBSTS_SETUP_PENDING)
910 dwc->setup_packet_pending = true;
911
912 dwc->ep0state = EP0_SETUP_PHASE;
913 dwc3_ep0_out_start(dwc);
914}
915
916static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
917 const struct dwc3_event_depevt *event)
918{
919 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
920
921 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
922 dep->resource_index = 0;
923 dwc->setup_packet_pending = false;
924
925 switch (dwc->ep0state) {
926 case EP0_SETUP_PHASE:
927 dwc3_ep0_inspect_setup(dwc, event);
928 break;
929
930 case EP0_DATA_PHASE:
931 dwc3_ep0_complete_data(dwc, event);
932 break;
933
934 case EP0_STATUS_PHASE:
935 dwc3_ep0_complete_status(dwc, event);
936 break;
937 default:
938 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
939 }
940}
941
942static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
943 struct dwc3_ep *dep, struct dwc3_request *req)
944{
945 int ret;
946
947 req->direction = !!dep->number;
948
949 if (req->request.length == 0) {
950 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0,
951 DWC3_TRBCTL_CONTROL_DATA, false);
952 ret = dwc3_ep0_start_trans(dep);
953 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
954 && (dep->number == 0)) {
955 u32 maxpacket;
956 u32 rem;
957
958 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
959 &req->request, dep->number);
960 if (ret)
961 return;
962
963 maxpacket = dep->endpoint.maxpacket;
964 rem = req->request.length % maxpacket;
965 dwc->ep0_bounced = true;
966
967 /* prepare normal TRB */
968 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
969 req->request.length,
970 DWC3_TRBCTL_CONTROL_DATA,
971 true);
972
973 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
974
975 /* Now prepare one extra TRB to align transfer size */
976 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
977 maxpacket - rem,
978 DWC3_TRBCTL_CONTROL_DATA,
979 false);
980 ret = dwc3_ep0_start_trans(dep);
981 } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
982 req->request.length && req->request.zero) {
983
984 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
985 &req->request, dep->number);
986 if (ret)
987 return;
988
989 /* prepare normal TRB */
990 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
991 req->request.length,
992 DWC3_TRBCTL_CONTROL_DATA,
993 true);
994
995 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
996
997 /* Now prepare one extra TRB to align transfer size */
998 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
999 0, DWC3_TRBCTL_CONTROL_DATA,
1000 false);
1001 ret = dwc3_ep0_start_trans(dep);
1002 } else {
1003 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1004 &req->request, dep->number);
1005 if (ret)
1006 return;
1007
1008 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1009 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1010 false);
1011
1012 req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1013
1014 ret = dwc3_ep0_start_trans(dep);
1015 }
1016
1017 WARN_ON(ret < 0);
1018}
1019
1020static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1021{
1022 struct dwc3 *dwc = dep->dwc;
1023 u32 type;
1024
1025 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1026 : DWC3_TRBCTL_CONTROL_STATUS2;
1027
1028 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1029 return dwc3_ep0_start_trans(dep);
1030}
1031
1032static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1033{
1034 WARN_ON(dwc3_ep0_start_control_status(dep));
1035}
1036
1037static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1038 const struct dwc3_event_depevt *event)
1039{
1040 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1041
1042 __dwc3_ep0_do_control_status(dwc, dep);
1043}
1044
1045static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1046{
1047 struct dwc3_gadget_ep_cmd_params params;
1048 u32 cmd;
1049 int ret;
1050
1051 if (!dep->resource_index)
1052 return;
1053
1054 cmd = DWC3_DEPCMD_ENDTRANSFER;
1055 cmd |= DWC3_DEPCMD_CMDIOC;
1056 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1057 memset(¶ms, 0, sizeof(params));
1058 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1059 WARN_ON_ONCE(ret);
1060 dep->resource_index = 0;
1061}
1062
1063static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1064 const struct dwc3_event_depevt *event)
1065{
1066 switch (event->status) {
1067 case DEPEVT_STATUS_CONTROL_DATA:
1068 /*
1069 * We already have a DATA transfer in the controller's cache,
1070 * if we receive a XferNotReady(DATA) we will ignore it, unless
1071 * it's for the wrong direction.
1072 *
1073 * In that case, we must issue END_TRANSFER command to the Data
1074 * Phase we already have started and issue SetStall on the
1075 * control endpoint.
1076 */
1077 if (dwc->ep0_expect_in != event->endpoint_number) {
1078 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1079
1080 dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1081 dwc3_ep0_end_control_data(dwc, dep);
1082 dwc3_ep0_stall_and_restart(dwc);
1083 return;
1084 }
1085
1086 break;
1087
1088 case DEPEVT_STATUS_CONTROL_STATUS:
1089 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1090 return;
1091
1092 dwc->ep0state = EP0_STATUS_PHASE;
1093
1094 if (dwc->delayed_status) {
1095 struct dwc3_ep *dep = dwc->eps[0];
1096
1097 WARN_ON_ONCE(event->endpoint_number != 1);
1098 /*
1099 * We should handle the delay STATUS phase here if the
1100 * request for handling delay STATUS has been queued
1101 * into the list.
1102 */
1103 if (!list_empty(&dep->pending_list)) {
1104 dwc->delayed_status = false;
1105 usb_gadget_set_state(&dwc->gadget,
1106 USB_STATE_CONFIGURED);
1107 dwc3_ep0_do_control_status(dwc, event);
1108 }
1109
1110 return;
1111 }
1112
1113 dwc3_ep0_do_control_status(dwc, event);
1114 }
1115}
1116
1117void dwc3_ep0_interrupt(struct dwc3 *dwc,
1118 const struct dwc3_event_depevt *event)
1119{
1120 switch (event->endpoint_event) {
1121 case DWC3_DEPEVT_XFERCOMPLETE:
1122 dwc3_ep0_xfer_complete(dwc, event);
1123 break;
1124
1125 case DWC3_DEPEVT_XFERNOTREADY:
1126 dwc3_ep0_xfernotready(dwc, event);
1127 break;
1128
1129 case DWC3_DEPEVT_XFERINPROGRESS:
1130 case DWC3_DEPEVT_RXTXFIFOEVT:
1131 case DWC3_DEPEVT_STREAMEVT:
1132 case DWC3_DEPEVT_EPCMDCMPLT:
1133 break;
1134 }
1135}