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1/*
2 * linux/arch/arm/kernel/setup.c
3 *
4 * Copyright (C) 1995-2001 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/module.h>
11#include <linux/kernel.h>
12#include <linux/stddef.h>
13#include <linux/ioport.h>
14#include <linux/delay.h>
15#include <linux/utsname.h>
16#include <linux/initrd.h>
17#include <linux/console.h>
18#include <linux/bootmem.h>
19#include <linux/seq_file.h>
20#include <linux/screen_info.h>
21#include <linux/init.h>
22#include <linux/kexec.h>
23#include <linux/of_fdt.h>
24#include <linux/crash_dump.h>
25#include <linux/root_dev.h>
26#include <linux/cpu.h>
27#include <linux/interrupt.h>
28#include <linux/smp.h>
29#include <linux/fs.h>
30#include <linux/proc_fs.h>
31#include <linux/memblock.h>
32
33#include <asm/unified.h>
34#include <asm/cpu.h>
35#include <asm/cputype.h>
36#include <asm/elf.h>
37#include <asm/procinfo.h>
38#include <asm/sections.h>
39#include <asm/setup.h>
40#include <asm/smp_plat.h>
41#include <asm/mach-types.h>
42#include <asm/cacheflush.h>
43#include <asm/cachetype.h>
44#include <asm/tlbflush.h>
45
46#include <asm/prom.h>
47#include <asm/mach/arch.h>
48#include <asm/mach/irq.h>
49#include <asm/mach/time.h>
50#include <asm/traps.h>
51#include <asm/unwind.h>
52
53#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
54#include "compat.h"
55#endif
56#include "atags.h"
57#include "tcm.h"
58
59#ifndef MEM_SIZE
60#define MEM_SIZE (16*1024*1024)
61#endif
62
63#if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE)
64char fpe_type[8];
65
66static int __init fpe_setup(char *line)
67{
68 memcpy(fpe_type, line, 8);
69 return 1;
70}
71
72__setup("fpe=", fpe_setup);
73#endif
74
75extern void paging_init(struct machine_desc *desc);
76extern void sanity_check_meminfo(void);
77extern void reboot_setup(char *str);
78
79unsigned int processor_id;
80EXPORT_SYMBOL(processor_id);
81unsigned int __machine_arch_type __read_mostly;
82EXPORT_SYMBOL(__machine_arch_type);
83unsigned int cacheid __read_mostly;
84EXPORT_SYMBOL(cacheid);
85
86unsigned int __atags_pointer __initdata;
87
88unsigned int system_rev;
89EXPORT_SYMBOL(system_rev);
90
91unsigned int system_serial_low;
92EXPORT_SYMBOL(system_serial_low);
93
94unsigned int system_serial_high;
95EXPORT_SYMBOL(system_serial_high);
96
97unsigned int elf_hwcap __read_mostly;
98EXPORT_SYMBOL(elf_hwcap);
99
100
101#ifdef MULTI_CPU
102struct processor processor __read_mostly;
103#endif
104#ifdef MULTI_TLB
105struct cpu_tlb_fns cpu_tlb __read_mostly;
106#endif
107#ifdef MULTI_USER
108struct cpu_user_fns cpu_user __read_mostly;
109#endif
110#ifdef MULTI_CACHE
111struct cpu_cache_fns cpu_cache __read_mostly;
112#endif
113#ifdef CONFIG_OUTER_CACHE
114struct outer_cache_fns outer_cache __read_mostly;
115EXPORT_SYMBOL(outer_cache);
116#endif
117
118struct stack {
119 u32 irq[3];
120 u32 abt[3];
121 u32 und[3];
122} ____cacheline_aligned;
123
124static struct stack stacks[NR_CPUS];
125
126char elf_platform[ELF_PLATFORM_SIZE];
127EXPORT_SYMBOL(elf_platform);
128
129static const char *cpu_name;
130static const char *machine_name;
131static char __initdata cmd_line[COMMAND_LINE_SIZE];
132struct machine_desc *machine_desc __initdata;
133
134static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
135static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
136#define ENDIANNESS ((char)endian_test.l)
137
138DEFINE_PER_CPU(struct cpuinfo_arm, cpu_data);
139
140/*
141 * Standard memory resources
142 */
143static struct resource mem_res[] = {
144 {
145 .name = "Video RAM",
146 .start = 0,
147 .end = 0,
148 .flags = IORESOURCE_MEM
149 },
150 {
151 .name = "Kernel text",
152 .start = 0,
153 .end = 0,
154 .flags = IORESOURCE_MEM
155 },
156 {
157 .name = "Kernel data",
158 .start = 0,
159 .end = 0,
160 .flags = IORESOURCE_MEM
161 }
162};
163
164#define video_ram mem_res[0]
165#define kernel_code mem_res[1]
166#define kernel_data mem_res[2]
167
168static struct resource io_res[] = {
169 {
170 .name = "reserved",
171 .start = 0x3bc,
172 .end = 0x3be,
173 .flags = IORESOURCE_IO | IORESOURCE_BUSY
174 },
175 {
176 .name = "reserved",
177 .start = 0x378,
178 .end = 0x37f,
179 .flags = IORESOURCE_IO | IORESOURCE_BUSY
180 },
181 {
182 .name = "reserved",
183 .start = 0x278,
184 .end = 0x27f,
185 .flags = IORESOURCE_IO | IORESOURCE_BUSY
186 }
187};
188
189#define lp0 io_res[0]
190#define lp1 io_res[1]
191#define lp2 io_res[2]
192
193static const char *proc_arch[] = {
194 "undefined/unknown",
195 "3",
196 "4",
197 "4T",
198 "5",
199 "5T",
200 "5TE",
201 "5TEJ",
202 "6TEJ",
203 "7",
204 "?(11)",
205 "?(12)",
206 "?(13)",
207 "?(14)",
208 "?(15)",
209 "?(16)",
210 "?(17)",
211};
212
213int cpu_architecture(void)
214{
215 int cpu_arch;
216
217 if ((read_cpuid_id() & 0x0008f000) == 0) {
218 cpu_arch = CPU_ARCH_UNKNOWN;
219 } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
220 cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
221 } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
222 cpu_arch = (read_cpuid_id() >> 16) & 7;
223 if (cpu_arch)
224 cpu_arch += CPU_ARCH_ARMv3;
225 } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
226 unsigned int mmfr0;
227
228 /* Revised CPUID format. Read the Memory Model Feature
229 * Register 0 and check for VMSAv7 or PMSAv7 */
230 asm("mrc p15, 0, %0, c0, c1, 4"
231 : "=r" (mmfr0));
232 if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
233 (mmfr0 & 0x000000f0) >= 0x00000030)
234 cpu_arch = CPU_ARCH_ARMv7;
235 else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
236 (mmfr0 & 0x000000f0) == 0x00000020)
237 cpu_arch = CPU_ARCH_ARMv6;
238 else
239 cpu_arch = CPU_ARCH_UNKNOWN;
240 } else
241 cpu_arch = CPU_ARCH_UNKNOWN;
242
243 return cpu_arch;
244}
245
246static int cpu_has_aliasing_icache(unsigned int arch)
247{
248 int aliasing_icache;
249 unsigned int id_reg, num_sets, line_size;
250
251 /* arch specifies the register format */
252 switch (arch) {
253 case CPU_ARCH_ARMv7:
254 asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR"
255 : /* No output operands */
256 : "r" (1));
257 isb();
258 asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR"
259 : "=r" (id_reg));
260 line_size = 4 << ((id_reg & 0x7) + 2);
261 num_sets = ((id_reg >> 13) & 0x7fff) + 1;
262 aliasing_icache = (line_size * num_sets) > PAGE_SIZE;
263 break;
264 case CPU_ARCH_ARMv6:
265 aliasing_icache = read_cpuid_cachetype() & (1 << 11);
266 break;
267 default:
268 /* I-cache aliases will be handled by D-cache aliasing code */
269 aliasing_icache = 0;
270 }
271
272 return aliasing_icache;
273}
274
275static void __init cacheid_init(void)
276{
277 unsigned int cachetype = read_cpuid_cachetype();
278 unsigned int arch = cpu_architecture();
279
280 if (arch >= CPU_ARCH_ARMv6) {
281 if ((cachetype & (7 << 29)) == 4 << 29) {
282 /* ARMv7 register format */
283 arch = CPU_ARCH_ARMv7;
284 cacheid = CACHEID_VIPT_NONALIASING;
285 if ((cachetype & (3 << 14)) == 1 << 14)
286 cacheid |= CACHEID_ASID_TAGGED;
287 } else {
288 arch = CPU_ARCH_ARMv6;
289 if (cachetype & (1 << 23))
290 cacheid = CACHEID_VIPT_ALIASING;
291 else
292 cacheid = CACHEID_VIPT_NONALIASING;
293 }
294 if (cpu_has_aliasing_icache(arch))
295 cacheid |= CACHEID_VIPT_I_ALIASING;
296 } else {
297 cacheid = CACHEID_VIVT;
298 }
299
300 printk("CPU: %s data cache, %s instruction cache\n",
301 cache_is_vivt() ? "VIVT" :
302 cache_is_vipt_aliasing() ? "VIPT aliasing" :
303 cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown",
304 cache_is_vivt() ? "VIVT" :
305 icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" :
306 icache_is_vipt_aliasing() ? "VIPT aliasing" :
307 cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown");
308}
309
310/*
311 * These functions re-use the assembly code in head.S, which
312 * already provide the required functionality.
313 */
314extern struct proc_info_list *lookup_processor_type(unsigned int);
315
316void __init early_print(const char *str, ...)
317{
318 extern void printascii(const char *);
319 char buf[256];
320 va_list ap;
321
322 va_start(ap, str);
323 vsnprintf(buf, sizeof(buf), str, ap);
324 va_end(ap);
325
326#ifdef CONFIG_DEBUG_LL
327 printascii(buf);
328#endif
329 printk("%s", buf);
330}
331
332static void __init feat_v6_fixup(void)
333{
334 int id = read_cpuid_id();
335
336 if ((id & 0xff0f0000) != 0x41070000)
337 return;
338
339 /*
340 * HWCAP_TLS is available only on 1136 r1p0 and later,
341 * see also kuser_get_tls_init.
342 */
343 if ((((id >> 4) & 0xfff) == 0xb36) && (((id >> 20) & 3) == 0))
344 elf_hwcap &= ~HWCAP_TLS;
345}
346
347/*
348 * cpu_init - initialise one CPU.
349 *
350 * cpu_init sets up the per-CPU stacks.
351 */
352void cpu_init(void)
353{
354 unsigned int cpu = smp_processor_id();
355 struct stack *stk = &stacks[cpu];
356
357 if (cpu >= NR_CPUS) {
358 printk(KERN_CRIT "CPU%u: bad primary CPU number\n", cpu);
359 BUG();
360 }
361
362 cpu_proc_init();
363
364 /*
365 * Define the placement constraint for the inline asm directive below.
366 * In Thumb-2, msr with an immediate value is not allowed.
367 */
368#ifdef CONFIG_THUMB2_KERNEL
369#define PLC "r"
370#else
371#define PLC "I"
372#endif
373
374 /*
375 * setup stacks for re-entrant exception handlers
376 */
377 __asm__ (
378 "msr cpsr_c, %1\n\t"
379 "add r14, %0, %2\n\t"
380 "mov sp, r14\n\t"
381 "msr cpsr_c, %3\n\t"
382 "add r14, %0, %4\n\t"
383 "mov sp, r14\n\t"
384 "msr cpsr_c, %5\n\t"
385 "add r14, %0, %6\n\t"
386 "mov sp, r14\n\t"
387 "msr cpsr_c, %7"
388 :
389 : "r" (stk),
390 PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
391 "I" (offsetof(struct stack, irq[0])),
392 PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
393 "I" (offsetof(struct stack, abt[0])),
394 PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
395 "I" (offsetof(struct stack, und[0])),
396 PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
397 : "r14");
398}
399
400static void __init setup_processor(void)
401{
402 struct proc_info_list *list;
403
404 /*
405 * locate processor in the list of supported processor
406 * types. The linker builds this table for us from the
407 * entries in arch/arm/mm/proc-*.S
408 */
409 list = lookup_processor_type(read_cpuid_id());
410 if (!list) {
411 printk("CPU configuration botched (ID %08x), unable "
412 "to continue.\n", read_cpuid_id());
413 while (1);
414 }
415
416 cpu_name = list->cpu_name;
417
418#ifdef MULTI_CPU
419 processor = *list->proc;
420#endif
421#ifdef MULTI_TLB
422 cpu_tlb = *list->tlb;
423#endif
424#ifdef MULTI_USER
425 cpu_user = *list->user;
426#endif
427#ifdef MULTI_CACHE
428 cpu_cache = *list->cache;
429#endif
430
431 printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
432 cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
433 proc_arch[cpu_architecture()], cr_alignment);
434
435 sprintf(init_utsname()->machine, "%s%c", list->arch_name, ENDIANNESS);
436 sprintf(elf_platform, "%s%c", list->elf_name, ENDIANNESS);
437 elf_hwcap = list->elf_hwcap;
438#ifndef CONFIG_ARM_THUMB
439 elf_hwcap &= ~HWCAP_THUMB;
440#endif
441
442 feat_v6_fixup();
443
444 cacheid_init();
445 cpu_init();
446}
447
448void __init dump_machine_table(void)
449{
450 struct machine_desc *p;
451
452 early_print("Available machine support:\n\nID (hex)\tNAME\n");
453 for_each_machine_desc(p)
454 early_print("%08x\t%s\n", p->nr, p->name);
455
456 early_print("\nPlease check your kernel config and/or bootloader.\n");
457
458 while (true)
459 /* can't use cpu_relax() here as it may require MMU setup */;
460}
461
462int __init arm_add_memory(phys_addr_t start, unsigned long size)
463{
464 struct membank *bank = &meminfo.bank[meminfo.nr_banks];
465
466 if (meminfo.nr_banks >= NR_BANKS) {
467 printk(KERN_CRIT "NR_BANKS too low, "
468 "ignoring memory at 0x%08llx\n", (long long)start);
469 return -EINVAL;
470 }
471
472 /*
473 * Ensure that start/size are aligned to a page boundary.
474 * Size is appropriately rounded down, start is rounded up.
475 */
476 size -= start & ~PAGE_MASK;
477 bank->start = PAGE_ALIGN(start);
478 bank->size = size & PAGE_MASK;
479
480 /*
481 * Check whether this memory region has non-zero size or
482 * invalid node number.
483 */
484 if (bank->size == 0)
485 return -EINVAL;
486
487 meminfo.nr_banks++;
488 return 0;
489}
490
491/*
492 * Pick out the memory size. We look for mem=size@start,
493 * where start and size are "size[KkMm]"
494 */
495static int __init early_mem(char *p)
496{
497 static int usermem __initdata = 0;
498 unsigned long size;
499 phys_addr_t start;
500 char *endp;
501
502 /*
503 * If the user specifies memory size, we
504 * blow away any automatically generated
505 * size.
506 */
507 if (usermem == 0) {
508 usermem = 1;
509 meminfo.nr_banks = 0;
510 }
511
512 start = PHYS_OFFSET;
513 size = memparse(p, &endp);
514 if (*endp == '@')
515 start = memparse(endp + 1, NULL);
516
517 arm_add_memory(start, size);
518
519 return 0;
520}
521early_param("mem", early_mem);
522
523static void __init
524setup_ramdisk(int doload, int prompt, int image_start, unsigned int rd_sz)
525{
526#ifdef CONFIG_BLK_DEV_RAM
527 extern int rd_size, rd_image_start, rd_prompt, rd_doload;
528
529 rd_image_start = image_start;
530 rd_prompt = prompt;
531 rd_doload = doload;
532
533 if (rd_sz)
534 rd_size = rd_sz;
535#endif
536}
537
538static void __init request_standard_resources(struct machine_desc *mdesc)
539{
540 struct memblock_region *region;
541 struct resource *res;
542
543 kernel_code.start = virt_to_phys(_text);
544 kernel_code.end = virt_to_phys(_etext - 1);
545 kernel_data.start = virt_to_phys(_sdata);
546 kernel_data.end = virt_to_phys(_end - 1);
547
548 for_each_memblock(memory, region) {
549 res = alloc_bootmem_low(sizeof(*res));
550 res->name = "System RAM";
551 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
552 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
553 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
554
555 request_resource(&iomem_resource, res);
556
557 if (kernel_code.start >= res->start &&
558 kernel_code.end <= res->end)
559 request_resource(res, &kernel_code);
560 if (kernel_data.start >= res->start &&
561 kernel_data.end <= res->end)
562 request_resource(res, &kernel_data);
563 }
564
565 if (mdesc->video_start) {
566 video_ram.start = mdesc->video_start;
567 video_ram.end = mdesc->video_end;
568 request_resource(&iomem_resource, &video_ram);
569 }
570
571 /*
572 * Some machines don't have the possibility of ever
573 * possessing lp0, lp1 or lp2
574 */
575 if (mdesc->reserve_lp0)
576 request_resource(&ioport_resource, &lp0);
577 if (mdesc->reserve_lp1)
578 request_resource(&ioport_resource, &lp1);
579 if (mdesc->reserve_lp2)
580 request_resource(&ioport_resource, &lp2);
581}
582
583/*
584 * Tag parsing.
585 *
586 * This is the new way of passing data to the kernel at boot time. Rather
587 * than passing a fixed inflexible structure to the kernel, we pass a list
588 * of variable-sized tags to the kernel. The first tag must be a ATAG_CORE
589 * tag for the list to be recognised (to distinguish the tagged list from
590 * a param_struct). The list is terminated with a zero-length tag (this tag
591 * is not parsed in any way).
592 */
593static int __init parse_tag_core(const struct tag *tag)
594{
595 if (tag->hdr.size > 2) {
596 if ((tag->u.core.flags & 1) == 0)
597 root_mountflags &= ~MS_RDONLY;
598 ROOT_DEV = old_decode_dev(tag->u.core.rootdev);
599 }
600 return 0;
601}
602
603__tagtable(ATAG_CORE, parse_tag_core);
604
605static int __init parse_tag_mem32(const struct tag *tag)
606{
607 return arm_add_memory(tag->u.mem.start, tag->u.mem.size);
608}
609
610__tagtable(ATAG_MEM, parse_tag_mem32);
611
612#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
613struct screen_info screen_info = {
614 .orig_video_lines = 30,
615 .orig_video_cols = 80,
616 .orig_video_mode = 0,
617 .orig_video_ega_bx = 0,
618 .orig_video_isVGA = 1,
619 .orig_video_points = 8
620};
621
622static int __init parse_tag_videotext(const struct tag *tag)
623{
624 screen_info.orig_x = tag->u.videotext.x;
625 screen_info.orig_y = tag->u.videotext.y;
626 screen_info.orig_video_page = tag->u.videotext.video_page;
627 screen_info.orig_video_mode = tag->u.videotext.video_mode;
628 screen_info.orig_video_cols = tag->u.videotext.video_cols;
629 screen_info.orig_video_ega_bx = tag->u.videotext.video_ega_bx;
630 screen_info.orig_video_lines = tag->u.videotext.video_lines;
631 screen_info.orig_video_isVGA = tag->u.videotext.video_isvga;
632 screen_info.orig_video_points = tag->u.videotext.video_points;
633 return 0;
634}
635
636__tagtable(ATAG_VIDEOTEXT, parse_tag_videotext);
637#endif
638
639static int __init parse_tag_ramdisk(const struct tag *tag)
640{
641 setup_ramdisk((tag->u.ramdisk.flags & 1) == 0,
642 (tag->u.ramdisk.flags & 2) == 0,
643 tag->u.ramdisk.start, tag->u.ramdisk.size);
644 return 0;
645}
646
647__tagtable(ATAG_RAMDISK, parse_tag_ramdisk);
648
649static int __init parse_tag_serialnr(const struct tag *tag)
650{
651 system_serial_low = tag->u.serialnr.low;
652 system_serial_high = tag->u.serialnr.high;
653 return 0;
654}
655
656__tagtable(ATAG_SERIAL, parse_tag_serialnr);
657
658static int __init parse_tag_revision(const struct tag *tag)
659{
660 system_rev = tag->u.revision.rev;
661 return 0;
662}
663
664__tagtable(ATAG_REVISION, parse_tag_revision);
665
666static int __init parse_tag_cmdline(const struct tag *tag)
667{
668#if defined(CONFIG_CMDLINE_EXTEND)
669 strlcat(default_command_line, " ", COMMAND_LINE_SIZE);
670 strlcat(default_command_line, tag->u.cmdline.cmdline,
671 COMMAND_LINE_SIZE);
672#elif defined(CONFIG_CMDLINE_FORCE)
673 pr_warning("Ignoring tag cmdline (using the default kernel command line)\n");
674#else
675 strlcpy(default_command_line, tag->u.cmdline.cmdline,
676 COMMAND_LINE_SIZE);
677#endif
678 return 0;
679}
680
681__tagtable(ATAG_CMDLINE, parse_tag_cmdline);
682
683/*
684 * Scan the tag table for this tag, and call its parse function.
685 * The tag table is built by the linker from all the __tagtable
686 * declarations.
687 */
688static int __init parse_tag(const struct tag *tag)
689{
690 extern struct tagtable __tagtable_begin, __tagtable_end;
691 struct tagtable *t;
692
693 for (t = &__tagtable_begin; t < &__tagtable_end; t++)
694 if (tag->hdr.tag == t->tag) {
695 t->parse(tag);
696 break;
697 }
698
699 return t < &__tagtable_end;
700}
701
702/*
703 * Parse all tags in the list, checking both the global and architecture
704 * specific tag tables.
705 */
706static void __init parse_tags(const struct tag *t)
707{
708 for (; t->hdr.size; t = tag_next(t))
709 if (!parse_tag(t))
710 printk(KERN_WARNING
711 "Ignoring unrecognised tag 0x%08x\n",
712 t->hdr.tag);
713}
714
715/*
716 * This holds our defaults.
717 */
718static struct init_tags {
719 struct tag_header hdr1;
720 struct tag_core core;
721 struct tag_header hdr2;
722 struct tag_mem32 mem;
723 struct tag_header hdr3;
724} init_tags __initdata = {
725 { tag_size(tag_core), ATAG_CORE },
726 { 1, PAGE_SIZE, 0xff },
727 { tag_size(tag_mem32), ATAG_MEM },
728 { MEM_SIZE },
729 { 0, ATAG_NONE }
730};
731
732static int __init customize_machine(void)
733{
734 /* customizes platform devices, or adds new ones */
735 if (machine_desc->init_machine)
736 machine_desc->init_machine();
737 return 0;
738}
739arch_initcall(customize_machine);
740
741#ifdef CONFIG_KEXEC
742static inline unsigned long long get_total_mem(void)
743{
744 unsigned long total;
745
746 total = max_low_pfn - min_low_pfn;
747 return total << PAGE_SHIFT;
748}
749
750/**
751 * reserve_crashkernel() - reserves memory are for crash kernel
752 *
753 * This function reserves memory area given in "crashkernel=" kernel command
754 * line parameter. The memory reserved is used by a dump capture kernel when
755 * primary kernel is crashing.
756 */
757static void __init reserve_crashkernel(void)
758{
759 unsigned long long crash_size, crash_base;
760 unsigned long long total_mem;
761 int ret;
762
763 total_mem = get_total_mem();
764 ret = parse_crashkernel(boot_command_line, total_mem,
765 &crash_size, &crash_base);
766 if (ret)
767 return;
768
769 ret = reserve_bootmem(crash_base, crash_size, BOOTMEM_EXCLUSIVE);
770 if (ret < 0) {
771 printk(KERN_WARNING "crashkernel reservation failed - "
772 "memory is in use (0x%lx)\n", (unsigned long)crash_base);
773 return;
774 }
775
776 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
777 "for crashkernel (System RAM: %ldMB)\n",
778 (unsigned long)(crash_size >> 20),
779 (unsigned long)(crash_base >> 20),
780 (unsigned long)(total_mem >> 20));
781
782 crashk_res.start = crash_base;
783 crashk_res.end = crash_base + crash_size - 1;
784 insert_resource(&iomem_resource, &crashk_res);
785}
786#else
787static inline void reserve_crashkernel(void) {}
788#endif /* CONFIG_KEXEC */
789
790static void __init squash_mem_tags(struct tag *tag)
791{
792 for (; tag->hdr.size; tag = tag_next(tag))
793 if (tag->hdr.tag == ATAG_MEM)
794 tag->hdr.tag = ATAG_NONE;
795}
796
797static struct machine_desc * __init setup_machine_tags(unsigned int nr)
798{
799 struct tag *tags = (struct tag *)&init_tags;
800 struct machine_desc *mdesc = NULL, *p;
801 char *from = default_command_line;
802
803 init_tags.mem.start = PHYS_OFFSET;
804
805 /*
806 * locate machine in the list of supported machines.
807 */
808 for_each_machine_desc(p)
809 if (nr == p->nr) {
810 printk("Machine: %s\n", p->name);
811 mdesc = p;
812 break;
813 }
814
815 if (!mdesc) {
816 early_print("\nError: unrecognized/unsupported machine ID"
817 " (r1 = 0x%08x).\n\n", nr);
818 dump_machine_table(); /* does not return */
819 }
820
821 if (__atags_pointer)
822 tags = phys_to_virt(__atags_pointer);
823 else if (mdesc->boot_params) {
824#ifdef CONFIG_MMU
825 /*
826 * We still are executing with a minimal MMU mapping created
827 * with the presumption that the machine default for this
828 * is located in the first MB of RAM. Anything else will
829 * fault and silently hang the kernel at this point.
830 */
831 if (mdesc->boot_params < PHYS_OFFSET ||
832 mdesc->boot_params >= PHYS_OFFSET + SZ_1M) {
833 printk(KERN_WARNING
834 "Default boot params at physical 0x%08lx out of reach\n",
835 mdesc->boot_params);
836 } else
837#endif
838 {
839 tags = phys_to_virt(mdesc->boot_params);
840 }
841 }
842
843#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
844 /*
845 * If we have the old style parameters, convert them to
846 * a tag list.
847 */
848 if (tags->hdr.tag != ATAG_CORE)
849 convert_to_tag_list(tags);
850#endif
851
852 if (tags->hdr.tag != ATAG_CORE) {
853#if defined(CONFIG_OF)
854 /*
855 * If CONFIG_OF is set, then assume this is a reasonably
856 * modern system that should pass boot parameters
857 */
858 early_print("Warning: Neither atags nor dtb found\n");
859#endif
860 tags = (struct tag *)&init_tags;
861 }
862
863 if (mdesc->fixup)
864 mdesc->fixup(mdesc, tags, &from, &meminfo);
865
866 if (tags->hdr.tag == ATAG_CORE) {
867 if (meminfo.nr_banks != 0)
868 squash_mem_tags(tags);
869 save_atags(tags);
870 parse_tags(tags);
871 }
872
873 /* parse_early_param needs a boot_command_line */
874 strlcpy(boot_command_line, from, COMMAND_LINE_SIZE);
875
876 return mdesc;
877}
878
879
880void __init setup_arch(char **cmdline_p)
881{
882 struct machine_desc *mdesc;
883
884 unwind_init();
885
886 setup_processor();
887 mdesc = setup_machine_fdt(__atags_pointer);
888 if (!mdesc)
889 mdesc = setup_machine_tags(machine_arch_type);
890 machine_desc = mdesc;
891 machine_name = mdesc->name;
892
893 if (mdesc->soft_reboot)
894 reboot_setup("s");
895
896 init_mm.start_code = (unsigned long) _text;
897 init_mm.end_code = (unsigned long) _etext;
898 init_mm.end_data = (unsigned long) _edata;
899 init_mm.brk = (unsigned long) _end;
900
901 /* populate cmd_line too for later use, preserving boot_command_line */
902 strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE);
903 *cmdline_p = cmd_line;
904
905 parse_early_param();
906
907 sanity_check_meminfo();
908 arm_memblock_init(&meminfo, mdesc);
909
910 paging_init(mdesc);
911 request_standard_resources(mdesc);
912
913 unflatten_device_tree();
914
915#ifdef CONFIG_SMP
916 if (is_smp())
917 smp_init_cpus();
918#endif
919 reserve_crashkernel();
920
921 tcm_init();
922
923#ifdef CONFIG_ZONE_DMA
924 if (mdesc->dma_zone_size) {
925 extern unsigned long arm_dma_zone_size;
926 arm_dma_zone_size = mdesc->dma_zone_size;
927 }
928#endif
929#ifdef CONFIG_MULTI_IRQ_HANDLER
930 handle_arch_irq = mdesc->handle_irq;
931#endif
932
933#ifdef CONFIG_VT
934#if defined(CONFIG_VGA_CONSOLE)
935 conswitchp = &vga_con;
936#elif defined(CONFIG_DUMMY_CONSOLE)
937 conswitchp = &dummy_con;
938#endif
939#endif
940 early_trap_init();
941
942 if (mdesc->init_early)
943 mdesc->init_early();
944}
945
946
947static int __init topology_init(void)
948{
949 int cpu;
950
951 for_each_possible_cpu(cpu) {
952 struct cpuinfo_arm *cpuinfo = &per_cpu(cpu_data, cpu);
953 cpuinfo->cpu.hotpluggable = 1;
954 register_cpu(&cpuinfo->cpu, cpu);
955 }
956
957 return 0;
958}
959subsys_initcall(topology_init);
960
961#ifdef CONFIG_HAVE_PROC_CPU
962static int __init proc_cpu_init(void)
963{
964 struct proc_dir_entry *res;
965
966 res = proc_mkdir("cpu", NULL);
967 if (!res)
968 return -ENOMEM;
969 return 0;
970}
971fs_initcall(proc_cpu_init);
972#endif
973
974static const char *hwcap_str[] = {
975 "swp",
976 "half",
977 "thumb",
978 "26bit",
979 "fastmult",
980 "fpa",
981 "vfp",
982 "edsp",
983 "java",
984 "iwmmxt",
985 "crunch",
986 "thumbee",
987 "neon",
988 "vfpv3",
989 "vfpv3d16",
990 "tls",
991 "vfpv4",
992 "idiva",
993 "idivt",
994 NULL
995};
996
997static int c_show(struct seq_file *m, void *v)
998{
999 int i;
1000
1001 seq_printf(m, "Processor\t: %s rev %d (%s)\n",
1002 cpu_name, read_cpuid_id() & 15, elf_platform);
1003
1004#if defined(CONFIG_SMP)
1005 for_each_online_cpu(i) {
1006 /*
1007 * glibc reads /proc/cpuinfo to determine the number of
1008 * online processors, looking for lines beginning with
1009 * "processor". Give glibc what it expects.
1010 */
1011 seq_printf(m, "processor\t: %d\n", i);
1012 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n\n",
1013 per_cpu(cpu_data, i).loops_per_jiffy / (500000UL/HZ),
1014 (per_cpu(cpu_data, i).loops_per_jiffy / (5000UL/HZ)) % 100);
1015 }
1016#else /* CONFIG_SMP */
1017 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
1018 loops_per_jiffy / (500000/HZ),
1019 (loops_per_jiffy / (5000/HZ)) % 100);
1020#endif
1021
1022 /* dump out the processor features */
1023 seq_puts(m, "Features\t: ");
1024
1025 for (i = 0; hwcap_str[i]; i++)
1026 if (elf_hwcap & (1 << i))
1027 seq_printf(m, "%s ", hwcap_str[i]);
1028
1029 seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
1030 seq_printf(m, "CPU architecture: %s\n", proc_arch[cpu_architecture()]);
1031
1032 if ((read_cpuid_id() & 0x0008f000) == 0x00000000) {
1033 /* pre-ARM7 */
1034 seq_printf(m, "CPU part\t: %07x\n", read_cpuid_id() >> 4);
1035 } else {
1036 if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
1037 /* ARM7 */
1038 seq_printf(m, "CPU variant\t: 0x%02x\n",
1039 (read_cpuid_id() >> 16) & 127);
1040 } else {
1041 /* post-ARM7 */
1042 seq_printf(m, "CPU variant\t: 0x%x\n",
1043 (read_cpuid_id() >> 20) & 15);
1044 }
1045 seq_printf(m, "CPU part\t: 0x%03x\n",
1046 (read_cpuid_id() >> 4) & 0xfff);
1047 }
1048 seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
1049
1050 seq_puts(m, "\n");
1051
1052 seq_printf(m, "Hardware\t: %s\n", machine_name);
1053 seq_printf(m, "Revision\t: %04x\n", system_rev);
1054 seq_printf(m, "Serial\t\t: %08x%08x\n",
1055 system_serial_high, system_serial_low);
1056
1057 return 0;
1058}
1059
1060static void *c_start(struct seq_file *m, loff_t *pos)
1061{
1062 return *pos < 1 ? (void *)1 : NULL;
1063}
1064
1065static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1066{
1067 ++*pos;
1068 return NULL;
1069}
1070
1071static void c_stop(struct seq_file *m, void *v)
1072{
1073}
1074
1075const struct seq_operations cpuinfo_op = {
1076 .start = c_start,
1077 .next = c_next,
1078 .stop = c_stop,
1079 .show = c_show
1080};
1/*
2 * linux/arch/arm/kernel/setup.c
3 *
4 * Copyright (C) 1995-2001 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/export.h>
11#include <linux/kernel.h>
12#include <linux/stddef.h>
13#include <linux/ioport.h>
14#include <linux/delay.h>
15#include <linux/utsname.h>
16#include <linux/initrd.h>
17#include <linux/console.h>
18#include <linux/bootmem.h>
19#include <linux/seq_file.h>
20#include <linux/screen_info.h>
21#include <linux/of_platform.h>
22#include <linux/init.h>
23#include <linux/kexec.h>
24#include <linux/of_fdt.h>
25#include <linux/cpu.h>
26#include <linux/interrupt.h>
27#include <linux/smp.h>
28#include <linux/proc_fs.h>
29#include <linux/memblock.h>
30#include <linux/bug.h>
31#include <linux/compiler.h>
32#include <linux/sort.h>
33
34#include <asm/unified.h>
35#include <asm/cp15.h>
36#include <asm/cpu.h>
37#include <asm/cputype.h>
38#include <asm/elf.h>
39#include <asm/procinfo.h>
40#include <asm/psci.h>
41#include <asm/sections.h>
42#include <asm/setup.h>
43#include <asm/smp_plat.h>
44#include <asm/mach-types.h>
45#include <asm/cacheflush.h>
46#include <asm/cachetype.h>
47#include <asm/tlbflush.h>
48
49#include <asm/prom.h>
50#include <asm/mach/arch.h>
51#include <asm/mach/irq.h>
52#include <asm/mach/time.h>
53#include <asm/system_info.h>
54#include <asm/system_misc.h>
55#include <asm/traps.h>
56#include <asm/unwind.h>
57#include <asm/memblock.h>
58#include <asm/virt.h>
59
60#include "atags.h"
61
62
63#if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE)
64char fpe_type[8];
65
66static int __init fpe_setup(char *line)
67{
68 memcpy(fpe_type, line, 8);
69 return 1;
70}
71
72__setup("fpe=", fpe_setup);
73#endif
74
75extern void paging_init(const struct machine_desc *desc);
76extern void early_paging_init(const struct machine_desc *,
77 struct proc_info_list *);
78extern void sanity_check_meminfo(void);
79extern enum reboot_mode reboot_mode;
80extern void setup_dma_zone(const struct machine_desc *desc);
81
82unsigned int processor_id;
83EXPORT_SYMBOL(processor_id);
84unsigned int __machine_arch_type __read_mostly;
85EXPORT_SYMBOL(__machine_arch_type);
86unsigned int cacheid __read_mostly;
87EXPORT_SYMBOL(cacheid);
88
89unsigned int __atags_pointer __initdata;
90
91unsigned int system_rev;
92EXPORT_SYMBOL(system_rev);
93
94unsigned int system_serial_low;
95EXPORT_SYMBOL(system_serial_low);
96
97unsigned int system_serial_high;
98EXPORT_SYMBOL(system_serial_high);
99
100unsigned int elf_hwcap __read_mostly;
101EXPORT_SYMBOL(elf_hwcap);
102
103unsigned int elf_hwcap2 __read_mostly;
104EXPORT_SYMBOL(elf_hwcap2);
105
106
107#ifdef MULTI_CPU
108struct processor processor __read_mostly;
109#endif
110#ifdef MULTI_TLB
111struct cpu_tlb_fns cpu_tlb __read_mostly;
112#endif
113#ifdef MULTI_USER
114struct cpu_user_fns cpu_user __read_mostly;
115#endif
116#ifdef MULTI_CACHE
117struct cpu_cache_fns cpu_cache __read_mostly;
118#endif
119#ifdef CONFIG_OUTER_CACHE
120struct outer_cache_fns outer_cache __read_mostly;
121EXPORT_SYMBOL(outer_cache);
122#endif
123
124/*
125 * Cached cpu_architecture() result for use by assembler code.
126 * C code should use the cpu_architecture() function instead of accessing this
127 * variable directly.
128 */
129int __cpu_architecture __read_mostly = CPU_ARCH_UNKNOWN;
130
131struct stack {
132 u32 irq[3];
133 u32 abt[3];
134 u32 und[3];
135} ____cacheline_aligned;
136
137#ifndef CONFIG_CPU_V7M
138static struct stack stacks[NR_CPUS];
139#endif
140
141char elf_platform[ELF_PLATFORM_SIZE];
142EXPORT_SYMBOL(elf_platform);
143
144static const char *cpu_name;
145static const char *machine_name;
146static char __initdata cmd_line[COMMAND_LINE_SIZE];
147const struct machine_desc *machine_desc __initdata;
148
149static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
150#define ENDIANNESS ((char)endian_test.l)
151
152DEFINE_PER_CPU(struct cpuinfo_arm, cpu_data);
153
154/*
155 * Standard memory resources
156 */
157static struct resource mem_res[] = {
158 {
159 .name = "Video RAM",
160 .start = 0,
161 .end = 0,
162 .flags = IORESOURCE_MEM
163 },
164 {
165 .name = "Kernel code",
166 .start = 0,
167 .end = 0,
168 .flags = IORESOURCE_MEM
169 },
170 {
171 .name = "Kernel data",
172 .start = 0,
173 .end = 0,
174 .flags = IORESOURCE_MEM
175 }
176};
177
178#define video_ram mem_res[0]
179#define kernel_code mem_res[1]
180#define kernel_data mem_res[2]
181
182static struct resource io_res[] = {
183 {
184 .name = "reserved",
185 .start = 0x3bc,
186 .end = 0x3be,
187 .flags = IORESOURCE_IO | IORESOURCE_BUSY
188 },
189 {
190 .name = "reserved",
191 .start = 0x378,
192 .end = 0x37f,
193 .flags = IORESOURCE_IO | IORESOURCE_BUSY
194 },
195 {
196 .name = "reserved",
197 .start = 0x278,
198 .end = 0x27f,
199 .flags = IORESOURCE_IO | IORESOURCE_BUSY
200 }
201};
202
203#define lp0 io_res[0]
204#define lp1 io_res[1]
205#define lp2 io_res[2]
206
207static const char *proc_arch[] = {
208 "undefined/unknown",
209 "3",
210 "4",
211 "4T",
212 "5",
213 "5T",
214 "5TE",
215 "5TEJ",
216 "6TEJ",
217 "7",
218 "7M",
219 "?(12)",
220 "?(13)",
221 "?(14)",
222 "?(15)",
223 "?(16)",
224 "?(17)",
225};
226
227#ifdef CONFIG_CPU_V7M
228static int __get_cpu_architecture(void)
229{
230 return CPU_ARCH_ARMv7M;
231}
232#else
233static int __get_cpu_architecture(void)
234{
235 int cpu_arch;
236
237 if ((read_cpuid_id() & 0x0008f000) == 0) {
238 cpu_arch = CPU_ARCH_UNKNOWN;
239 } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
240 cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
241 } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
242 cpu_arch = (read_cpuid_id() >> 16) & 7;
243 if (cpu_arch)
244 cpu_arch += CPU_ARCH_ARMv3;
245 } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
246 unsigned int mmfr0;
247
248 /* Revised CPUID format. Read the Memory Model Feature
249 * Register 0 and check for VMSAv7 or PMSAv7 */
250 asm("mrc p15, 0, %0, c0, c1, 4"
251 : "=r" (mmfr0));
252 if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
253 (mmfr0 & 0x000000f0) >= 0x00000030)
254 cpu_arch = CPU_ARCH_ARMv7;
255 else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
256 (mmfr0 & 0x000000f0) == 0x00000020)
257 cpu_arch = CPU_ARCH_ARMv6;
258 else
259 cpu_arch = CPU_ARCH_UNKNOWN;
260 } else
261 cpu_arch = CPU_ARCH_UNKNOWN;
262
263 return cpu_arch;
264}
265#endif
266
267int __pure cpu_architecture(void)
268{
269 BUG_ON(__cpu_architecture == CPU_ARCH_UNKNOWN);
270
271 return __cpu_architecture;
272}
273
274static int cpu_has_aliasing_icache(unsigned int arch)
275{
276 int aliasing_icache;
277 unsigned int id_reg, num_sets, line_size;
278
279 /* PIPT caches never alias. */
280 if (icache_is_pipt())
281 return 0;
282
283 /* arch specifies the register format */
284 switch (arch) {
285 case CPU_ARCH_ARMv7:
286 asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR"
287 : /* No output operands */
288 : "r" (1));
289 isb();
290 asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR"
291 : "=r" (id_reg));
292 line_size = 4 << ((id_reg & 0x7) + 2);
293 num_sets = ((id_reg >> 13) & 0x7fff) + 1;
294 aliasing_icache = (line_size * num_sets) > PAGE_SIZE;
295 break;
296 case CPU_ARCH_ARMv6:
297 aliasing_icache = read_cpuid_cachetype() & (1 << 11);
298 break;
299 default:
300 /* I-cache aliases will be handled by D-cache aliasing code */
301 aliasing_icache = 0;
302 }
303
304 return aliasing_icache;
305}
306
307static void __init cacheid_init(void)
308{
309 unsigned int arch = cpu_architecture();
310
311 if (arch == CPU_ARCH_ARMv7M) {
312 cacheid = 0;
313 } else if (arch >= CPU_ARCH_ARMv6) {
314 unsigned int cachetype = read_cpuid_cachetype();
315 if ((cachetype & (7 << 29)) == 4 << 29) {
316 /* ARMv7 register format */
317 arch = CPU_ARCH_ARMv7;
318 cacheid = CACHEID_VIPT_NONALIASING;
319 switch (cachetype & (3 << 14)) {
320 case (1 << 14):
321 cacheid |= CACHEID_ASID_TAGGED;
322 break;
323 case (3 << 14):
324 cacheid |= CACHEID_PIPT;
325 break;
326 }
327 } else {
328 arch = CPU_ARCH_ARMv6;
329 if (cachetype & (1 << 23))
330 cacheid = CACHEID_VIPT_ALIASING;
331 else
332 cacheid = CACHEID_VIPT_NONALIASING;
333 }
334 if (cpu_has_aliasing_icache(arch))
335 cacheid |= CACHEID_VIPT_I_ALIASING;
336 } else {
337 cacheid = CACHEID_VIVT;
338 }
339
340 pr_info("CPU: %s data cache, %s instruction cache\n",
341 cache_is_vivt() ? "VIVT" :
342 cache_is_vipt_aliasing() ? "VIPT aliasing" :
343 cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown",
344 cache_is_vivt() ? "VIVT" :
345 icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" :
346 icache_is_vipt_aliasing() ? "VIPT aliasing" :
347 icache_is_pipt() ? "PIPT" :
348 cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown");
349}
350
351/*
352 * These functions re-use the assembly code in head.S, which
353 * already provide the required functionality.
354 */
355extern struct proc_info_list *lookup_processor_type(unsigned int);
356
357void __init early_print(const char *str, ...)
358{
359 extern void printascii(const char *);
360 char buf[256];
361 va_list ap;
362
363 va_start(ap, str);
364 vsnprintf(buf, sizeof(buf), str, ap);
365 va_end(ap);
366
367#ifdef CONFIG_DEBUG_LL
368 printascii(buf);
369#endif
370 printk("%s", buf);
371}
372
373static void __init cpuid_init_hwcaps(void)
374{
375 unsigned int divide_instrs, vmsa;
376
377 if (cpu_architecture() < CPU_ARCH_ARMv7)
378 return;
379
380 divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
381
382 switch (divide_instrs) {
383 case 2:
384 elf_hwcap |= HWCAP_IDIVA;
385 case 1:
386 elf_hwcap |= HWCAP_IDIVT;
387 }
388
389 /* LPAE implies atomic ldrd/strd instructions */
390 vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0;
391 if (vmsa >= 5)
392 elf_hwcap |= HWCAP_LPAE;
393}
394
395static void __init feat_v6_fixup(void)
396{
397 int id = read_cpuid_id();
398
399 if ((id & 0xff0f0000) != 0x41070000)
400 return;
401
402 /*
403 * HWCAP_TLS is available only on 1136 r1p0 and later,
404 * see also kuser_get_tls_init.
405 */
406 if ((((id >> 4) & 0xfff) == 0xb36) && (((id >> 20) & 3) == 0))
407 elf_hwcap &= ~HWCAP_TLS;
408}
409
410/*
411 * cpu_init - initialise one CPU.
412 *
413 * cpu_init sets up the per-CPU stacks.
414 */
415void notrace cpu_init(void)
416{
417#ifndef CONFIG_CPU_V7M
418 unsigned int cpu = smp_processor_id();
419 struct stack *stk = &stacks[cpu];
420
421 if (cpu >= NR_CPUS) {
422 pr_crit("CPU%u: bad primary CPU number\n", cpu);
423 BUG();
424 }
425
426 /*
427 * This only works on resume and secondary cores. For booting on the
428 * boot cpu, smp_prepare_boot_cpu is called after percpu area setup.
429 */
430 set_my_cpu_offset(per_cpu_offset(cpu));
431
432 cpu_proc_init();
433
434 /*
435 * Define the placement constraint for the inline asm directive below.
436 * In Thumb-2, msr with an immediate value is not allowed.
437 */
438#ifdef CONFIG_THUMB2_KERNEL
439#define PLC "r"
440#else
441#define PLC "I"
442#endif
443
444 /*
445 * setup stacks for re-entrant exception handlers
446 */
447 __asm__ (
448 "msr cpsr_c, %1\n\t"
449 "add r14, %0, %2\n\t"
450 "mov sp, r14\n\t"
451 "msr cpsr_c, %3\n\t"
452 "add r14, %0, %4\n\t"
453 "mov sp, r14\n\t"
454 "msr cpsr_c, %5\n\t"
455 "add r14, %0, %6\n\t"
456 "mov sp, r14\n\t"
457 "msr cpsr_c, %7"
458 :
459 : "r" (stk),
460 PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
461 "I" (offsetof(struct stack, irq[0])),
462 PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
463 "I" (offsetof(struct stack, abt[0])),
464 PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
465 "I" (offsetof(struct stack, und[0])),
466 PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
467 : "r14");
468#endif
469}
470
471u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
472
473void __init smp_setup_processor_id(void)
474{
475 int i;
476 u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
477 u32 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
478
479 cpu_logical_map(0) = cpu;
480 for (i = 1; i < nr_cpu_ids; ++i)
481 cpu_logical_map(i) = i == cpu ? 0 : i;
482
483 /*
484 * clear __my_cpu_offset on boot CPU to avoid hang caused by
485 * using percpu variable early, for example, lockdep will
486 * access percpu variable inside lock_release
487 */
488 set_my_cpu_offset(0);
489
490 pr_info("Booting Linux on physical CPU 0x%x\n", mpidr);
491}
492
493struct mpidr_hash mpidr_hash;
494#ifdef CONFIG_SMP
495/**
496 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
497 * level in order to build a linear index from an
498 * MPIDR value. Resulting algorithm is a collision
499 * free hash carried out through shifting and ORing
500 */
501static void __init smp_build_mpidr_hash(void)
502{
503 u32 i, affinity;
504 u32 fs[3], bits[3], ls, mask = 0;
505 /*
506 * Pre-scan the list of MPIDRS and filter out bits that do
507 * not contribute to affinity levels, ie they never toggle.
508 */
509 for_each_possible_cpu(i)
510 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
511 pr_debug("mask of set bits 0x%x\n", mask);
512 /*
513 * Find and stash the last and first bit set at all affinity levels to
514 * check how many bits are required to represent them.
515 */
516 for (i = 0; i < 3; i++) {
517 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
518 /*
519 * Find the MSB bit and LSB bits position
520 * to determine how many bits are required
521 * to express the affinity level.
522 */
523 ls = fls(affinity);
524 fs[i] = affinity ? ffs(affinity) - 1 : 0;
525 bits[i] = ls - fs[i];
526 }
527 /*
528 * An index can be created from the MPIDR by isolating the
529 * significant bits at each affinity level and by shifting
530 * them in order to compress the 24 bits values space to a
531 * compressed set of values. This is equivalent to hashing
532 * the MPIDR through shifting and ORing. It is a collision free
533 * hash though not minimal since some levels might contain a number
534 * of CPUs that is not an exact power of 2 and their bit
535 * representation might contain holes, eg MPIDR[7:0] = {0x2, 0x80}.
536 */
537 mpidr_hash.shift_aff[0] = fs[0];
538 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_BITS + fs[1] - bits[0];
539 mpidr_hash.shift_aff[2] = 2*MPIDR_LEVEL_BITS + fs[2] -
540 (bits[1] + bits[0]);
541 mpidr_hash.mask = mask;
542 mpidr_hash.bits = bits[2] + bits[1] + bits[0];
543 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] mask[0x%x] bits[%u]\n",
544 mpidr_hash.shift_aff[0],
545 mpidr_hash.shift_aff[1],
546 mpidr_hash.shift_aff[2],
547 mpidr_hash.mask,
548 mpidr_hash.bits);
549 /*
550 * 4x is an arbitrary value used to warn on a hash table much bigger
551 * than expected on most systems.
552 */
553 if (mpidr_hash_size() > 4 * num_possible_cpus())
554 pr_warn("Large number of MPIDR hash buckets detected\n");
555 sync_cache_w(&mpidr_hash);
556}
557#endif
558
559static void __init setup_processor(void)
560{
561 struct proc_info_list *list;
562
563 /*
564 * locate processor in the list of supported processor
565 * types. The linker builds this table for us from the
566 * entries in arch/arm/mm/proc-*.S
567 */
568 list = lookup_processor_type(read_cpuid_id());
569 if (!list) {
570 pr_err("CPU configuration botched (ID %08x), unable to continue.\n",
571 read_cpuid_id());
572 while (1);
573 }
574
575 cpu_name = list->cpu_name;
576 __cpu_architecture = __get_cpu_architecture();
577
578#ifdef MULTI_CPU
579 processor = *list->proc;
580#endif
581#ifdef MULTI_TLB
582 cpu_tlb = *list->tlb;
583#endif
584#ifdef MULTI_USER
585 cpu_user = *list->user;
586#endif
587#ifdef MULTI_CACHE
588 cpu_cache = *list->cache;
589#endif
590
591 pr_info("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
592 cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
593 proc_arch[cpu_architecture()], cr_alignment);
594
595 snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c",
596 list->arch_name, ENDIANNESS);
597 snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
598 list->elf_name, ENDIANNESS);
599 elf_hwcap = list->elf_hwcap;
600
601 cpuid_init_hwcaps();
602
603#ifndef CONFIG_ARM_THUMB
604 elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
605#endif
606
607 erratum_a15_798181_init();
608
609 feat_v6_fixup();
610
611 cacheid_init();
612 cpu_init();
613}
614
615void __init dump_machine_table(void)
616{
617 const struct machine_desc *p;
618
619 early_print("Available machine support:\n\nID (hex)\tNAME\n");
620 for_each_machine_desc(p)
621 early_print("%08x\t%s\n", p->nr, p->name);
622
623 early_print("\nPlease check your kernel config and/or bootloader.\n");
624
625 while (true)
626 /* can't use cpu_relax() here as it may require MMU setup */;
627}
628
629int __init arm_add_memory(u64 start, u64 size)
630{
631 struct membank *bank = &meminfo.bank[meminfo.nr_banks];
632 u64 aligned_start;
633
634 if (meminfo.nr_banks >= NR_BANKS) {
635 pr_crit("NR_BANKS too low, ignoring memory at 0x%08llx\n",
636 (long long)start);
637 return -EINVAL;
638 }
639
640 /*
641 * Ensure that start/size are aligned to a page boundary.
642 * Size is appropriately rounded down, start is rounded up.
643 */
644 size -= start & ~PAGE_MASK;
645 aligned_start = PAGE_ALIGN(start);
646
647#ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT
648 if (aligned_start > ULONG_MAX) {
649 pr_crit("Ignoring memory at 0x%08llx outside 32-bit physical address space\n",
650 (long long)start);
651 return -EINVAL;
652 }
653
654 if (aligned_start + size > ULONG_MAX) {
655 pr_crit("Truncating memory at 0x%08llx to fit in 32-bit physical address space\n",
656 (long long)start);
657 /*
658 * To ensure bank->start + bank->size is representable in
659 * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB.
660 * This means we lose a page after masking.
661 */
662 size = ULONG_MAX - aligned_start;
663 }
664#endif
665
666 if (aligned_start < PHYS_OFFSET) {
667 if (aligned_start + size <= PHYS_OFFSET) {
668 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
669 aligned_start, aligned_start + size);
670 return -EINVAL;
671 }
672
673 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
674 aligned_start, (u64)PHYS_OFFSET);
675
676 size -= PHYS_OFFSET - aligned_start;
677 aligned_start = PHYS_OFFSET;
678 }
679
680 bank->start = aligned_start;
681 bank->size = size & ~(phys_addr_t)(PAGE_SIZE - 1);
682
683 /*
684 * Check whether this memory region has non-zero size or
685 * invalid node number.
686 */
687 if (bank->size == 0)
688 return -EINVAL;
689
690 meminfo.nr_banks++;
691 return 0;
692}
693
694/*
695 * Pick out the memory size. We look for mem=size@start,
696 * where start and size are "size[KkMm]"
697 */
698static int __init early_mem(char *p)
699{
700 static int usermem __initdata = 0;
701 u64 size;
702 u64 start;
703 char *endp;
704
705 /*
706 * If the user specifies memory size, we
707 * blow away any automatically generated
708 * size.
709 */
710 if (usermem == 0) {
711 usermem = 1;
712 meminfo.nr_banks = 0;
713 }
714
715 start = PHYS_OFFSET;
716 size = memparse(p, &endp);
717 if (*endp == '@')
718 start = memparse(endp + 1, NULL);
719
720 arm_add_memory(start, size);
721
722 return 0;
723}
724early_param("mem", early_mem);
725
726static void __init request_standard_resources(const struct machine_desc *mdesc)
727{
728 struct memblock_region *region;
729 struct resource *res;
730
731 kernel_code.start = virt_to_phys(_text);
732 kernel_code.end = virt_to_phys(_etext - 1);
733 kernel_data.start = virt_to_phys(_sdata);
734 kernel_data.end = virt_to_phys(_end - 1);
735
736 for_each_memblock(memory, region) {
737 res = memblock_virt_alloc(sizeof(*res), 0);
738 res->name = "System RAM";
739 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
740 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
741 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
742
743 request_resource(&iomem_resource, res);
744
745 if (kernel_code.start >= res->start &&
746 kernel_code.end <= res->end)
747 request_resource(res, &kernel_code);
748 if (kernel_data.start >= res->start &&
749 kernel_data.end <= res->end)
750 request_resource(res, &kernel_data);
751 }
752
753 if (mdesc->video_start) {
754 video_ram.start = mdesc->video_start;
755 video_ram.end = mdesc->video_end;
756 request_resource(&iomem_resource, &video_ram);
757 }
758
759 /*
760 * Some machines don't have the possibility of ever
761 * possessing lp0, lp1 or lp2
762 */
763 if (mdesc->reserve_lp0)
764 request_resource(&ioport_resource, &lp0);
765 if (mdesc->reserve_lp1)
766 request_resource(&ioport_resource, &lp1);
767 if (mdesc->reserve_lp2)
768 request_resource(&ioport_resource, &lp2);
769}
770
771#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
772struct screen_info screen_info = {
773 .orig_video_lines = 30,
774 .orig_video_cols = 80,
775 .orig_video_mode = 0,
776 .orig_video_ega_bx = 0,
777 .orig_video_isVGA = 1,
778 .orig_video_points = 8
779};
780#endif
781
782static int __init customize_machine(void)
783{
784 /*
785 * customizes platform devices, or adds new ones
786 * On DT based machines, we fall back to populating the
787 * machine from the device tree, if no callback is provided,
788 * otherwise we would always need an init_machine callback.
789 */
790 if (machine_desc->init_machine)
791 machine_desc->init_machine();
792#ifdef CONFIG_OF
793 else
794 of_platform_populate(NULL, of_default_bus_match_table,
795 NULL, NULL);
796#endif
797 return 0;
798}
799arch_initcall(customize_machine);
800
801static int __init init_machine_late(void)
802{
803 if (machine_desc->init_late)
804 machine_desc->init_late();
805 return 0;
806}
807late_initcall(init_machine_late);
808
809#ifdef CONFIG_KEXEC
810static inline unsigned long long get_total_mem(void)
811{
812 unsigned long total;
813
814 total = max_low_pfn - min_low_pfn;
815 return total << PAGE_SHIFT;
816}
817
818/**
819 * reserve_crashkernel() - reserves memory are for crash kernel
820 *
821 * This function reserves memory area given in "crashkernel=" kernel command
822 * line parameter. The memory reserved is used by a dump capture kernel when
823 * primary kernel is crashing.
824 */
825static void __init reserve_crashkernel(void)
826{
827 unsigned long long crash_size, crash_base;
828 unsigned long long total_mem;
829 int ret;
830
831 total_mem = get_total_mem();
832 ret = parse_crashkernel(boot_command_line, total_mem,
833 &crash_size, &crash_base);
834 if (ret)
835 return;
836
837 ret = memblock_reserve(crash_base, crash_size);
838 if (ret < 0) {
839 pr_warn("crashkernel reservation failed - memory is in use (0x%lx)\n",
840 (unsigned long)crash_base);
841 return;
842 }
843
844 pr_info("Reserving %ldMB of memory at %ldMB for crashkernel (System RAM: %ldMB)\n",
845 (unsigned long)(crash_size >> 20),
846 (unsigned long)(crash_base >> 20),
847 (unsigned long)(total_mem >> 20));
848
849 crashk_res.start = crash_base;
850 crashk_res.end = crash_base + crash_size - 1;
851 insert_resource(&iomem_resource, &crashk_res);
852}
853#else
854static inline void reserve_crashkernel(void) {}
855#endif /* CONFIG_KEXEC */
856
857static int __init meminfo_cmp(const void *_a, const void *_b)
858{
859 const struct membank *a = _a, *b = _b;
860 long cmp = bank_pfn_start(a) - bank_pfn_start(b);
861 return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
862}
863
864void __init hyp_mode_check(void)
865{
866#ifdef CONFIG_ARM_VIRT_EXT
867 sync_boot_mode();
868
869 if (is_hyp_mode_available()) {
870 pr_info("CPU: All CPU(s) started in HYP mode.\n");
871 pr_info("CPU: Virtualization extensions available.\n");
872 } else if (is_hyp_mode_mismatched()) {
873 pr_warn("CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x%x)\n",
874 __boot_cpu_mode & MODE_MASK);
875 pr_warn("CPU: This may indicate a broken bootloader or firmware.\n");
876 } else
877 pr_info("CPU: All CPU(s) started in SVC mode.\n");
878#endif
879}
880
881void __init setup_arch(char **cmdline_p)
882{
883 const struct machine_desc *mdesc;
884
885 setup_processor();
886 mdesc = setup_machine_fdt(__atags_pointer);
887 if (!mdesc)
888 mdesc = setup_machine_tags(__atags_pointer, __machine_arch_type);
889 machine_desc = mdesc;
890 machine_name = mdesc->name;
891
892 if (mdesc->reboot_mode != REBOOT_HARD)
893 reboot_mode = mdesc->reboot_mode;
894
895 init_mm.start_code = (unsigned long) _text;
896 init_mm.end_code = (unsigned long) _etext;
897 init_mm.end_data = (unsigned long) _edata;
898 init_mm.brk = (unsigned long) _end;
899
900 /* populate cmd_line too for later use, preserving boot_command_line */
901 strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE);
902 *cmdline_p = cmd_line;
903
904 parse_early_param();
905
906 sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL);
907
908 early_paging_init(mdesc, lookup_processor_type(read_cpuid_id()));
909 setup_dma_zone(mdesc);
910 sanity_check_meminfo();
911 arm_memblock_init(&meminfo, mdesc);
912
913 paging_init(mdesc);
914 request_standard_resources(mdesc);
915
916 if (mdesc->restart)
917 arm_pm_restart = mdesc->restart;
918
919 unflatten_device_tree();
920
921 arm_dt_init_cpu_maps();
922 psci_init();
923#ifdef CONFIG_SMP
924 if (is_smp()) {
925 if (!mdesc->smp_init || !mdesc->smp_init()) {
926 if (psci_smp_available())
927 smp_set_ops(&psci_smp_ops);
928 else if (mdesc->smp)
929 smp_set_ops(mdesc->smp);
930 }
931 smp_init_cpus();
932 smp_build_mpidr_hash();
933 }
934#endif
935
936 if (!is_smp())
937 hyp_mode_check();
938
939 reserve_crashkernel();
940
941#ifdef CONFIG_MULTI_IRQ_HANDLER
942 handle_arch_irq = mdesc->handle_irq;
943#endif
944
945#ifdef CONFIG_VT
946#if defined(CONFIG_VGA_CONSOLE)
947 conswitchp = &vga_con;
948#elif defined(CONFIG_DUMMY_CONSOLE)
949 conswitchp = &dummy_con;
950#endif
951#endif
952
953 if (mdesc->init_early)
954 mdesc->init_early();
955}
956
957
958static int __init topology_init(void)
959{
960 int cpu;
961
962 for_each_possible_cpu(cpu) {
963 struct cpuinfo_arm *cpuinfo = &per_cpu(cpu_data, cpu);
964 cpuinfo->cpu.hotpluggable = 1;
965 register_cpu(&cpuinfo->cpu, cpu);
966 }
967
968 return 0;
969}
970subsys_initcall(topology_init);
971
972#ifdef CONFIG_HAVE_PROC_CPU
973static int __init proc_cpu_init(void)
974{
975 struct proc_dir_entry *res;
976
977 res = proc_mkdir("cpu", NULL);
978 if (!res)
979 return -ENOMEM;
980 return 0;
981}
982fs_initcall(proc_cpu_init);
983#endif
984
985static const char *hwcap_str[] = {
986 "swp",
987 "half",
988 "thumb",
989 "26bit",
990 "fastmult",
991 "fpa",
992 "vfp",
993 "edsp",
994 "java",
995 "iwmmxt",
996 "crunch",
997 "thumbee",
998 "neon",
999 "vfpv3",
1000 "vfpv3d16",
1001 "tls",
1002 "vfpv4",
1003 "idiva",
1004 "idivt",
1005 "vfpd32",
1006 "lpae",
1007 "evtstrm",
1008 NULL
1009};
1010
1011static const char *hwcap2_str[] = {
1012 "aes",
1013 "pmull",
1014 "sha1",
1015 "sha2",
1016 "crc32",
1017 NULL
1018};
1019
1020static int c_show(struct seq_file *m, void *v)
1021{
1022 int i, j;
1023 u32 cpuid;
1024
1025 for_each_online_cpu(i) {
1026 /*
1027 * glibc reads /proc/cpuinfo to determine the number of
1028 * online processors, looking for lines beginning with
1029 * "processor". Give glibc what it expects.
1030 */
1031 seq_printf(m, "processor\t: %d\n", i);
1032 cpuid = is_smp() ? per_cpu(cpu_data, i).cpuid : read_cpuid_id();
1033 seq_printf(m, "model name\t: %s rev %d (%s)\n",
1034 cpu_name, cpuid & 15, elf_platform);
1035
1036 /* dump out the processor features */
1037 seq_puts(m, "Features\t: ");
1038
1039 for (j = 0; hwcap_str[j]; j++)
1040 if (elf_hwcap & (1 << j))
1041 seq_printf(m, "%s ", hwcap_str[j]);
1042
1043 for (j = 0; hwcap2_str[j]; j++)
1044 if (elf_hwcap2 & (1 << j))
1045 seq_printf(m, "%s ", hwcap2_str[j]);
1046
1047 seq_printf(m, "\nCPU implementer\t: 0x%02x\n", cpuid >> 24);
1048 seq_printf(m, "CPU architecture: %s\n",
1049 proc_arch[cpu_architecture()]);
1050
1051 if ((cpuid & 0x0008f000) == 0x00000000) {
1052 /* pre-ARM7 */
1053 seq_printf(m, "CPU part\t: %07x\n", cpuid >> 4);
1054 } else {
1055 if ((cpuid & 0x0008f000) == 0x00007000) {
1056 /* ARM7 */
1057 seq_printf(m, "CPU variant\t: 0x%02x\n",
1058 (cpuid >> 16) & 127);
1059 } else {
1060 /* post-ARM7 */
1061 seq_printf(m, "CPU variant\t: 0x%x\n",
1062 (cpuid >> 20) & 15);
1063 }
1064 seq_printf(m, "CPU part\t: 0x%03x\n",
1065 (cpuid >> 4) & 0xfff);
1066 }
1067 seq_printf(m, "CPU revision\t: %d\n\n", cpuid & 15);
1068 }
1069
1070 seq_printf(m, "Hardware\t: %s\n", machine_name);
1071 seq_printf(m, "Revision\t: %04x\n", system_rev);
1072 seq_printf(m, "Serial\t\t: %08x%08x\n",
1073 system_serial_high, system_serial_low);
1074
1075 return 0;
1076}
1077
1078static void *c_start(struct seq_file *m, loff_t *pos)
1079{
1080 return *pos < 1 ? (void *)1 : NULL;
1081}
1082
1083static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1084{
1085 ++*pos;
1086 return NULL;
1087}
1088
1089static void c_stop(struct seq_file *m, void *v)
1090{
1091}
1092
1093const struct seq_operations cpuinfo_op = {
1094 .start = c_start,
1095 .next = c_next,
1096 .stop = c_stop,
1097 .show = c_show
1098};