Loading...
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/dma-fence-array.h>
30#include <linux/interval_tree_generic.h>
31#include <linux/idr.h>
32#include <linux/dma-buf.h>
33
34#include <drm/amdgpu_drm.h>
35#include <drm/drm_drv.h>
36#include <drm/ttm/ttm_tt.h>
37#include <drm/drm_exec.h>
38#include "amdgpu.h"
39#include "amdgpu_trace.h"
40#include "amdgpu_amdkfd.h"
41#include "amdgpu_gmc.h"
42#include "amdgpu_xgmi.h"
43#include "amdgpu_dma_buf.h"
44#include "amdgpu_res_cursor.h"
45#include "kfd_svm.h"
46
47/**
48 * DOC: GPUVM
49 *
50 * GPUVM is the MMU functionality provided on the GPU.
51 * GPUVM is similar to the legacy GART on older asics, however
52 * rather than there being a single global GART table
53 * for the entire GPU, there can be multiple GPUVM page tables active
54 * at any given time. The GPUVM page tables can contain a mix
55 * VRAM pages and system pages (both memory and MMIO) and system pages
56 * can be mapped as snooped (cached system pages) or unsnooped
57 * (uncached system pages).
58 *
59 * Each active GPUVM has an ID associated with it and there is a page table
60 * linked with each VMID. When executing a command buffer,
61 * the kernel tells the engine what VMID to use for that command
62 * buffer. VMIDs are allocated dynamically as commands are submitted.
63 * The userspace drivers maintain their own address space and the kernel
64 * sets up their pages tables accordingly when they submit their
65 * command buffers and a VMID is assigned.
66 * The hardware supports up to 16 active GPUVMs at any given time.
67 *
68 * Each GPUVM is represented by a 1-2 or 1-5 level page table, depending
69 * on the ASIC family. GPUVM supports RWX attributes on each page as well
70 * as other features such as encryption and caching attributes.
71 *
72 * VMID 0 is special. It is the GPUVM used for the kernel driver. In
73 * addition to an aperture managed by a page table, VMID 0 also has
74 * several other apertures. There is an aperture for direct access to VRAM
75 * and there is a legacy AGP aperture which just forwards accesses directly
76 * to the matching system physical addresses (or IOVAs when an IOMMU is
77 * present). These apertures provide direct access to these memories without
78 * incurring the overhead of a page table. VMID 0 is used by the kernel
79 * driver for tasks like memory management.
80 *
81 * GPU clients (i.e., engines on the GPU) use GPUVM VMIDs to access memory.
82 * For user applications, each application can have their own unique GPUVM
83 * address space. The application manages the address space and the kernel
84 * driver manages the GPUVM page tables for each process. If an GPU client
85 * accesses an invalid page, it will generate a GPU page fault, similar to
86 * accessing an invalid page on a CPU.
87 */
88
89#define START(node) ((node)->start)
90#define LAST(node) ((node)->last)
91
92INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
93 START, LAST, static, amdgpu_vm_it)
94
95#undef START
96#undef LAST
97
98/**
99 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
100 */
101struct amdgpu_prt_cb {
102
103 /**
104 * @adev: amdgpu device
105 */
106 struct amdgpu_device *adev;
107
108 /**
109 * @cb: callback
110 */
111 struct dma_fence_cb cb;
112};
113
114/**
115 * struct amdgpu_vm_tlb_seq_struct - Helper to increment the TLB flush sequence
116 */
117struct amdgpu_vm_tlb_seq_struct {
118 /**
119 * @vm: pointer to the amdgpu_vm structure to set the fence sequence on
120 */
121 struct amdgpu_vm *vm;
122
123 /**
124 * @cb: callback
125 */
126 struct dma_fence_cb cb;
127};
128
129/**
130 * amdgpu_vm_set_pasid - manage pasid and vm ptr mapping
131 *
132 * @adev: amdgpu_device pointer
133 * @vm: amdgpu_vm pointer
134 * @pasid: the pasid the VM is using on this GPU
135 *
136 * Set the pasid this VM is using on this GPU, can also be used to remove the
137 * pasid by passing in zero.
138 *
139 */
140int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm,
141 u32 pasid)
142{
143 int r;
144
145 if (vm->pasid == pasid)
146 return 0;
147
148 if (vm->pasid) {
149 r = xa_err(xa_erase_irq(&adev->vm_manager.pasids, vm->pasid));
150 if (r < 0)
151 return r;
152
153 vm->pasid = 0;
154 }
155
156 if (pasid) {
157 r = xa_err(xa_store_irq(&adev->vm_manager.pasids, pasid, vm,
158 GFP_KERNEL));
159 if (r < 0)
160 return r;
161
162 vm->pasid = pasid;
163 }
164
165
166 return 0;
167}
168
169/**
170 * amdgpu_vm_bo_evicted - vm_bo is evicted
171 *
172 * @vm_bo: vm_bo which is evicted
173 *
174 * State for PDs/PTs and per VM BOs which are not at the location they should
175 * be.
176 */
177static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
178{
179 struct amdgpu_vm *vm = vm_bo->vm;
180 struct amdgpu_bo *bo = vm_bo->bo;
181
182 vm_bo->moved = true;
183 spin_lock(&vm_bo->vm->status_lock);
184 if (bo->tbo.type == ttm_bo_type_kernel)
185 list_move(&vm_bo->vm_status, &vm->evicted);
186 else
187 list_move_tail(&vm_bo->vm_status, &vm->evicted);
188 spin_unlock(&vm_bo->vm->status_lock);
189}
190/**
191 * amdgpu_vm_bo_moved - vm_bo is moved
192 *
193 * @vm_bo: vm_bo which is moved
194 *
195 * State for per VM BOs which are moved, but that change is not yet reflected
196 * in the page tables.
197 */
198static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
199{
200 spin_lock(&vm_bo->vm->status_lock);
201 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
202 spin_unlock(&vm_bo->vm->status_lock);
203}
204
205/**
206 * amdgpu_vm_bo_idle - vm_bo is idle
207 *
208 * @vm_bo: vm_bo which is now idle
209 *
210 * State for PDs/PTs and per VM BOs which have gone through the state machine
211 * and are now idle.
212 */
213static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
214{
215 spin_lock(&vm_bo->vm->status_lock);
216 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
217 spin_unlock(&vm_bo->vm->status_lock);
218 vm_bo->moved = false;
219}
220
221/**
222 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
223 *
224 * @vm_bo: vm_bo which is now invalidated
225 *
226 * State for normal BOs which are invalidated and that change not yet reflected
227 * in the PTs.
228 */
229static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
230{
231 spin_lock(&vm_bo->vm->status_lock);
232 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
233 spin_unlock(&vm_bo->vm->status_lock);
234}
235
236/**
237 * amdgpu_vm_bo_evicted_user - vm_bo is evicted
238 *
239 * @vm_bo: vm_bo which is evicted
240 *
241 * State for BOs used by user mode queues which are not at the location they
242 * should be.
243 */
244static void amdgpu_vm_bo_evicted_user(struct amdgpu_vm_bo_base *vm_bo)
245{
246 vm_bo->moved = true;
247 spin_lock(&vm_bo->vm->status_lock);
248 list_move(&vm_bo->vm_status, &vm_bo->vm->evicted_user);
249 spin_unlock(&vm_bo->vm->status_lock);
250}
251
252/**
253 * amdgpu_vm_bo_relocated - vm_bo is reloacted
254 *
255 * @vm_bo: vm_bo which is relocated
256 *
257 * State for PDs/PTs which needs to update their parent PD.
258 * For the root PD, just move to idle state.
259 */
260static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
261{
262 if (vm_bo->bo->parent) {
263 spin_lock(&vm_bo->vm->status_lock);
264 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
265 spin_unlock(&vm_bo->vm->status_lock);
266 } else {
267 amdgpu_vm_bo_idle(vm_bo);
268 }
269}
270
271/**
272 * amdgpu_vm_bo_done - vm_bo is done
273 *
274 * @vm_bo: vm_bo which is now done
275 *
276 * State for normal BOs which are invalidated and that change has been updated
277 * in the PTs.
278 */
279static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
280{
281 spin_lock(&vm_bo->vm->status_lock);
282 list_move(&vm_bo->vm_status, &vm_bo->vm->done);
283 spin_unlock(&vm_bo->vm->status_lock);
284}
285
286/**
287 * amdgpu_vm_bo_reset_state_machine - reset the vm_bo state machine
288 * @vm: the VM which state machine to reset
289 *
290 * Move all vm_bo object in the VM into a state where they will be updated
291 * again during validation.
292 */
293static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm)
294{
295 struct amdgpu_vm_bo_base *vm_bo, *tmp;
296
297 spin_lock(&vm->status_lock);
298 list_splice_init(&vm->done, &vm->invalidated);
299 list_for_each_entry(vm_bo, &vm->invalidated, vm_status)
300 vm_bo->moved = true;
301 list_for_each_entry_safe(vm_bo, tmp, &vm->idle, vm_status) {
302 struct amdgpu_bo *bo = vm_bo->bo;
303
304 vm_bo->moved = true;
305 if (!bo || bo->tbo.type != ttm_bo_type_kernel)
306 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
307 else if (bo->parent)
308 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
309 }
310 spin_unlock(&vm->status_lock);
311}
312
313/**
314 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
315 *
316 * @base: base structure for tracking BO usage in a VM
317 * @vm: vm to which bo is to be added
318 * @bo: amdgpu buffer object
319 *
320 * Initialize a bo_va_base structure and add it to the appropriate lists
321 *
322 */
323void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
324 struct amdgpu_vm *vm, struct amdgpu_bo *bo)
325{
326 base->vm = vm;
327 base->bo = bo;
328 base->next = NULL;
329 INIT_LIST_HEAD(&base->vm_status);
330
331 if (!bo)
332 return;
333 base->next = bo->vm_bo;
334 bo->vm_bo = base;
335
336 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
337 return;
338
339 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
340
341 ttm_bo_set_bulk_move(&bo->tbo, &vm->lru_bulk_move);
342 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
343 amdgpu_vm_bo_relocated(base);
344 else
345 amdgpu_vm_bo_idle(base);
346
347 if (bo->preferred_domains &
348 amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type))
349 return;
350
351 /*
352 * we checked all the prerequisites, but it looks like this per vm bo
353 * is currently evicted. add the bo to the evicted list to make sure it
354 * is validated on next vm use to avoid fault.
355 * */
356 amdgpu_vm_bo_evicted(base);
357}
358
359/**
360 * amdgpu_vm_lock_pd - lock PD in drm_exec
361 *
362 * @vm: vm providing the BOs
363 * @exec: drm execution context
364 * @num_fences: number of extra fences to reserve
365 *
366 * Lock the VM root PD in the DRM execution context.
367 */
368int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec,
369 unsigned int num_fences)
370{
371 /* We need at least two fences for the VM PD/PT updates */
372 return drm_exec_prepare_obj(exec, &vm->root.bo->tbo.base,
373 2 + num_fences);
374}
375
376/**
377 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
378 *
379 * @adev: amdgpu device pointer
380 * @vm: vm providing the BOs
381 *
382 * Move all BOs to the end of LRU and remember their positions to put them
383 * together.
384 */
385void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
386 struct amdgpu_vm *vm)
387{
388 spin_lock(&adev->mman.bdev.lru_lock);
389 ttm_lru_bulk_move_tail(&vm->lru_bulk_move);
390 spin_unlock(&adev->mman.bdev.lru_lock);
391}
392
393/* Create scheduler entities for page table updates */
394static int amdgpu_vm_init_entities(struct amdgpu_device *adev,
395 struct amdgpu_vm *vm)
396{
397 int r;
398
399 r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
400 adev->vm_manager.vm_pte_scheds,
401 adev->vm_manager.vm_pte_num_scheds, NULL);
402 if (r)
403 goto error;
404
405 return drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
406 adev->vm_manager.vm_pte_scheds,
407 adev->vm_manager.vm_pte_num_scheds, NULL);
408
409error:
410 drm_sched_entity_destroy(&vm->immediate);
411 return r;
412}
413
414/* Destroy the entities for page table updates again */
415static void amdgpu_vm_fini_entities(struct amdgpu_vm *vm)
416{
417 drm_sched_entity_destroy(&vm->immediate);
418 drm_sched_entity_destroy(&vm->delayed);
419}
420
421/**
422 * amdgpu_vm_generation - return the page table re-generation counter
423 * @adev: the amdgpu_device
424 * @vm: optional VM to check, might be NULL
425 *
426 * Returns a page table re-generation token to allow checking if submissions
427 * are still valid to use this VM. The VM parameter might be NULL in which case
428 * just the VRAM lost counter will be used.
429 */
430uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm)
431{
432 uint64_t result = (u64)atomic_read(&adev->vram_lost_counter) << 32;
433
434 if (!vm)
435 return result;
436
437 result += vm->generation;
438 /* Add one if the page tables will be re-generated on next CS */
439 if (drm_sched_entity_error(&vm->delayed))
440 ++result;
441
442 return result;
443}
444
445/**
446 * amdgpu_vm_validate - validate evicted BOs tracked in the VM
447 *
448 * @adev: amdgpu device pointer
449 * @vm: vm providing the BOs
450 * @ticket: optional reservation ticket used to reserve the VM
451 * @validate: callback to do the validation
452 * @param: parameter for the validation callback
453 *
454 * Validate the page table BOs and per-VM BOs on command submission if
455 * necessary. If a ticket is given, also try to validate evicted user queue
456 * BOs. They must already be reserved with the given ticket.
457 *
458 * Returns:
459 * Validation result.
460 */
461int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm,
462 struct ww_acquire_ctx *ticket,
463 int (*validate)(void *p, struct amdgpu_bo *bo),
464 void *param)
465{
466 struct amdgpu_vm_bo_base *bo_base;
467 struct amdgpu_bo *shadow;
468 struct amdgpu_bo *bo;
469 int r;
470
471 if (drm_sched_entity_error(&vm->delayed)) {
472 ++vm->generation;
473 amdgpu_vm_bo_reset_state_machine(vm);
474 amdgpu_vm_fini_entities(vm);
475 r = amdgpu_vm_init_entities(adev, vm);
476 if (r)
477 return r;
478 }
479
480 spin_lock(&vm->status_lock);
481 while (!list_empty(&vm->evicted)) {
482 bo_base = list_first_entry(&vm->evicted,
483 struct amdgpu_vm_bo_base,
484 vm_status);
485 spin_unlock(&vm->status_lock);
486
487 bo = bo_base->bo;
488 shadow = amdgpu_bo_shadowed(bo);
489
490 r = validate(param, bo);
491 if (r)
492 return r;
493 if (shadow) {
494 r = validate(param, shadow);
495 if (r)
496 return r;
497 }
498
499 if (bo->tbo.type != ttm_bo_type_kernel) {
500 amdgpu_vm_bo_moved(bo_base);
501 } else {
502 vm->update_funcs->map_table(to_amdgpu_bo_vm(bo));
503 amdgpu_vm_bo_relocated(bo_base);
504 }
505 spin_lock(&vm->status_lock);
506 }
507 while (ticket && !list_empty(&vm->evicted_user)) {
508 bo_base = list_first_entry(&vm->evicted_user,
509 struct amdgpu_vm_bo_base,
510 vm_status);
511 spin_unlock(&vm->status_lock);
512
513 bo = bo_base->bo;
514
515 if (dma_resv_locking_ctx(bo->tbo.base.resv) != ticket) {
516 struct amdgpu_task_info *ti = amdgpu_vm_get_task_info_vm(vm);
517
518 pr_warn_ratelimited("Evicted user BO is not reserved\n");
519 if (ti) {
520 pr_warn_ratelimited("pid %d\n", ti->pid);
521 amdgpu_vm_put_task_info(ti);
522 }
523
524 return -EINVAL;
525 }
526
527 r = validate(param, bo);
528 if (r)
529 return r;
530
531 amdgpu_vm_bo_invalidated(bo_base);
532
533 spin_lock(&vm->status_lock);
534 }
535 spin_unlock(&vm->status_lock);
536
537 amdgpu_vm_eviction_lock(vm);
538 vm->evicting = false;
539 amdgpu_vm_eviction_unlock(vm);
540
541 return 0;
542}
543
544/**
545 * amdgpu_vm_ready - check VM is ready for updates
546 *
547 * @vm: VM to check
548 *
549 * Check if all VM PDs/PTs are ready for updates
550 *
551 * Returns:
552 * True if VM is not evicting.
553 */
554bool amdgpu_vm_ready(struct amdgpu_vm *vm)
555{
556 bool empty;
557 bool ret;
558
559 amdgpu_vm_eviction_lock(vm);
560 ret = !vm->evicting;
561 amdgpu_vm_eviction_unlock(vm);
562
563 spin_lock(&vm->status_lock);
564 empty = list_empty(&vm->evicted);
565 spin_unlock(&vm->status_lock);
566
567 return ret && empty;
568}
569
570/**
571 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
572 *
573 * @adev: amdgpu_device pointer
574 */
575void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
576{
577 const struct amdgpu_ip_block *ip_block;
578 bool has_compute_vm_bug;
579 struct amdgpu_ring *ring;
580 int i;
581
582 has_compute_vm_bug = false;
583
584 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
585 if (ip_block) {
586 /* Compute has a VM bug for GFX version < 7.
587 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
588 if (ip_block->version->major <= 7)
589 has_compute_vm_bug = true;
590 else if (ip_block->version->major == 8)
591 if (adev->gfx.mec_fw_version < 673)
592 has_compute_vm_bug = true;
593 }
594
595 for (i = 0; i < adev->num_rings; i++) {
596 ring = adev->rings[i];
597 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
598 /* only compute rings */
599 ring->has_compute_vm_bug = has_compute_vm_bug;
600 else
601 ring->has_compute_vm_bug = false;
602 }
603}
604
605/**
606 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
607 *
608 * @ring: ring on which the job will be submitted
609 * @job: job to submit
610 *
611 * Returns:
612 * True if sync is needed.
613 */
614bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
615 struct amdgpu_job *job)
616{
617 struct amdgpu_device *adev = ring->adev;
618 unsigned vmhub = ring->vm_hub;
619 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
620
621 if (job->vmid == 0)
622 return false;
623
624 if (job->vm_needs_flush || ring->has_compute_vm_bug)
625 return true;
626
627 if (ring->funcs->emit_gds_switch && job->gds_switch_needed)
628 return true;
629
630 if (amdgpu_vmid_had_gpu_reset(adev, &id_mgr->ids[job->vmid]))
631 return true;
632
633 return false;
634}
635
636/**
637 * amdgpu_vm_flush - hardware flush the vm
638 *
639 * @ring: ring to use for flush
640 * @job: related job
641 * @need_pipe_sync: is pipe sync needed
642 *
643 * Emit a VM flush when it is necessary.
644 *
645 * Returns:
646 * 0 on success, errno otherwise.
647 */
648int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
649 bool need_pipe_sync)
650{
651 struct amdgpu_device *adev = ring->adev;
652 unsigned vmhub = ring->vm_hub;
653 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
654 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
655 bool spm_update_needed = job->spm_update_needed;
656 bool gds_switch_needed = ring->funcs->emit_gds_switch &&
657 job->gds_switch_needed;
658 bool vm_flush_needed = job->vm_needs_flush;
659 struct dma_fence *fence = NULL;
660 bool pasid_mapping_needed = false;
661 unsigned int patch;
662 int r;
663
664 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
665 gds_switch_needed = true;
666 vm_flush_needed = true;
667 pasid_mapping_needed = true;
668 spm_update_needed = true;
669 }
670
671 mutex_lock(&id_mgr->lock);
672 if (id->pasid != job->pasid || !id->pasid_mapping ||
673 !dma_fence_is_signaled(id->pasid_mapping))
674 pasid_mapping_needed = true;
675 mutex_unlock(&id_mgr->lock);
676
677 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
678 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
679 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
680 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
681 ring->funcs->emit_wreg;
682
683 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
684 return 0;
685
686 amdgpu_ring_ib_begin(ring);
687 if (ring->funcs->init_cond_exec)
688 patch = amdgpu_ring_init_cond_exec(ring,
689 ring->cond_exe_gpu_addr);
690
691 if (need_pipe_sync)
692 amdgpu_ring_emit_pipeline_sync(ring);
693
694 if (vm_flush_needed) {
695 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
696 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
697 }
698
699 if (pasid_mapping_needed)
700 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
701
702 if (spm_update_needed && adev->gfx.rlc.funcs->update_spm_vmid)
703 adev->gfx.rlc.funcs->update_spm_vmid(adev, ring, job->vmid);
704
705 if (!ring->is_mes_queue && ring->funcs->emit_gds_switch &&
706 gds_switch_needed) {
707 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
708 job->gds_size, job->gws_base,
709 job->gws_size, job->oa_base,
710 job->oa_size);
711 }
712
713 if (vm_flush_needed || pasid_mapping_needed) {
714 r = amdgpu_fence_emit(ring, &fence, NULL, 0);
715 if (r)
716 return r;
717 }
718
719 if (vm_flush_needed) {
720 mutex_lock(&id_mgr->lock);
721 dma_fence_put(id->last_flush);
722 id->last_flush = dma_fence_get(fence);
723 id->current_gpu_reset_count =
724 atomic_read(&adev->gpu_reset_counter);
725 mutex_unlock(&id_mgr->lock);
726 }
727
728 if (pasid_mapping_needed) {
729 mutex_lock(&id_mgr->lock);
730 id->pasid = job->pasid;
731 dma_fence_put(id->pasid_mapping);
732 id->pasid_mapping = dma_fence_get(fence);
733 mutex_unlock(&id_mgr->lock);
734 }
735 dma_fence_put(fence);
736
737 amdgpu_ring_patch_cond_exec(ring, patch);
738
739 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
740 if (ring->funcs->emit_switch_buffer) {
741 amdgpu_ring_emit_switch_buffer(ring);
742 amdgpu_ring_emit_switch_buffer(ring);
743 }
744 amdgpu_ring_ib_end(ring);
745 return 0;
746}
747
748/**
749 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
750 *
751 * @vm: requested vm
752 * @bo: requested buffer object
753 *
754 * Find @bo inside the requested vm.
755 * Search inside the @bos vm list for the requested vm
756 * Returns the found bo_va or NULL if none is found
757 *
758 * Object has to be reserved!
759 *
760 * Returns:
761 * Found bo_va or NULL.
762 */
763struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
764 struct amdgpu_bo *bo)
765{
766 struct amdgpu_vm_bo_base *base;
767
768 for (base = bo->vm_bo; base; base = base->next) {
769 if (base->vm != vm)
770 continue;
771
772 return container_of(base, struct amdgpu_bo_va, base);
773 }
774 return NULL;
775}
776
777/**
778 * amdgpu_vm_map_gart - Resolve gart mapping of addr
779 *
780 * @pages_addr: optional DMA address to use for lookup
781 * @addr: the unmapped addr
782 *
783 * Look up the physical address of the page that the pte resolves
784 * to.
785 *
786 * Returns:
787 * The pointer for the page table entry.
788 */
789uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
790{
791 uint64_t result;
792
793 /* page table offset */
794 result = pages_addr[addr >> PAGE_SHIFT];
795
796 /* in case cpu page size != gpu page size*/
797 result |= addr & (~PAGE_MASK);
798
799 result &= 0xFFFFFFFFFFFFF000ULL;
800
801 return result;
802}
803
804/**
805 * amdgpu_vm_update_pdes - make sure that all directories are valid
806 *
807 * @adev: amdgpu_device pointer
808 * @vm: requested vm
809 * @immediate: submit immediately to the paging queue
810 *
811 * Makes sure all directories are up to date.
812 *
813 * Returns:
814 * 0 for success, error for failure.
815 */
816int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
817 struct amdgpu_vm *vm, bool immediate)
818{
819 struct amdgpu_vm_update_params params;
820 struct amdgpu_vm_bo_base *entry;
821 bool flush_tlb_needed = false;
822 LIST_HEAD(relocated);
823 int r, idx;
824
825 spin_lock(&vm->status_lock);
826 list_splice_init(&vm->relocated, &relocated);
827 spin_unlock(&vm->status_lock);
828
829 if (list_empty(&relocated))
830 return 0;
831
832 if (!drm_dev_enter(adev_to_drm(adev), &idx))
833 return -ENODEV;
834
835 memset(¶ms, 0, sizeof(params));
836 params.adev = adev;
837 params.vm = vm;
838 params.immediate = immediate;
839
840 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
841 if (r)
842 goto error;
843
844 list_for_each_entry(entry, &relocated, vm_status) {
845 /* vm_flush_needed after updating moved PDEs */
846 flush_tlb_needed |= entry->moved;
847
848 r = amdgpu_vm_pde_update(¶ms, entry);
849 if (r)
850 goto error;
851 }
852
853 r = vm->update_funcs->commit(¶ms, &vm->last_update);
854 if (r)
855 goto error;
856
857 if (flush_tlb_needed)
858 atomic64_inc(&vm->tlb_seq);
859
860 while (!list_empty(&relocated)) {
861 entry = list_first_entry(&relocated, struct amdgpu_vm_bo_base,
862 vm_status);
863 amdgpu_vm_bo_idle(entry);
864 }
865
866error:
867 drm_dev_exit(idx);
868 return r;
869}
870
871/**
872 * amdgpu_vm_tlb_seq_cb - make sure to increment tlb sequence
873 * @fence: unused
874 * @cb: the callback structure
875 *
876 * Increments the tlb sequence to make sure that future CS execute a VM flush.
877 */
878static void amdgpu_vm_tlb_seq_cb(struct dma_fence *fence,
879 struct dma_fence_cb *cb)
880{
881 struct amdgpu_vm_tlb_seq_struct *tlb_cb;
882
883 tlb_cb = container_of(cb, typeof(*tlb_cb), cb);
884 atomic64_inc(&tlb_cb->vm->tlb_seq);
885 kfree(tlb_cb);
886}
887
888/**
889 * amdgpu_vm_update_range - update a range in the vm page table
890 *
891 * @adev: amdgpu_device pointer to use for commands
892 * @vm: the VM to update the range
893 * @immediate: immediate submission in a page fault
894 * @unlocked: unlocked invalidation during MM callback
895 * @flush_tlb: trigger tlb invalidation after update completed
896 * @allow_override: change MTYPE for local NUMA nodes
897 * @resv: fences we need to sync to
898 * @start: start of mapped range
899 * @last: last mapped entry
900 * @flags: flags for the entries
901 * @offset: offset into nodes and pages_addr
902 * @vram_base: base for vram mappings
903 * @res: ttm_resource to map
904 * @pages_addr: DMA addresses to use for mapping
905 * @fence: optional resulting fence
906 *
907 * Fill in the page table entries between @start and @last.
908 *
909 * Returns:
910 * 0 for success, negative erro code for failure.
911 */
912int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
913 bool immediate, bool unlocked, bool flush_tlb, bool allow_override,
914 struct dma_resv *resv, uint64_t start, uint64_t last,
915 uint64_t flags, uint64_t offset, uint64_t vram_base,
916 struct ttm_resource *res, dma_addr_t *pages_addr,
917 struct dma_fence **fence)
918{
919 struct amdgpu_vm_update_params params;
920 struct amdgpu_vm_tlb_seq_struct *tlb_cb;
921 struct amdgpu_res_cursor cursor;
922 enum amdgpu_sync_mode sync_mode;
923 int r, idx;
924
925 if (!drm_dev_enter(adev_to_drm(adev), &idx))
926 return -ENODEV;
927
928 tlb_cb = kmalloc(sizeof(*tlb_cb), GFP_KERNEL);
929 if (!tlb_cb) {
930 r = -ENOMEM;
931 goto error_unlock;
932 }
933
934 /* Vega20+XGMI where PTEs get inadvertently cached in L2 texture cache,
935 * heavy-weight flush TLB unconditionally.
936 */
937 flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
938 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0);
939
940 /*
941 * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
942 */
943 flush_tlb |= amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 0, 0);
944
945 memset(¶ms, 0, sizeof(params));
946 params.adev = adev;
947 params.vm = vm;
948 params.immediate = immediate;
949 params.pages_addr = pages_addr;
950 params.unlocked = unlocked;
951 params.allow_override = allow_override;
952
953 /* Implicitly sync to command submissions in the same VM before
954 * unmapping. Sync to moving fences before mapping.
955 */
956 if (!(flags & AMDGPU_PTE_VALID))
957 sync_mode = AMDGPU_SYNC_EQ_OWNER;
958 else
959 sync_mode = AMDGPU_SYNC_EXPLICIT;
960
961 amdgpu_vm_eviction_lock(vm);
962 if (vm->evicting) {
963 r = -EBUSY;
964 goto error_free;
965 }
966
967 if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
968 struct dma_fence *tmp = dma_fence_get_stub();
969
970 amdgpu_bo_fence(vm->root.bo, vm->last_unlocked, true);
971 swap(vm->last_unlocked, tmp);
972 dma_fence_put(tmp);
973 }
974
975 r = vm->update_funcs->prepare(¶ms, resv, sync_mode);
976 if (r)
977 goto error_free;
978
979 amdgpu_res_first(pages_addr ? NULL : res, offset,
980 (last - start + 1) * AMDGPU_GPU_PAGE_SIZE, &cursor);
981 while (cursor.remaining) {
982 uint64_t tmp, num_entries, addr;
983
984 num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT;
985 if (pages_addr) {
986 bool contiguous = true;
987
988 if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
989 uint64_t pfn = cursor.start >> PAGE_SHIFT;
990 uint64_t count;
991
992 contiguous = pages_addr[pfn + 1] ==
993 pages_addr[pfn] + PAGE_SIZE;
994
995 tmp = num_entries /
996 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
997 for (count = 2; count < tmp; ++count) {
998 uint64_t idx = pfn + count;
999
1000 if (contiguous != (pages_addr[idx] ==
1001 pages_addr[idx - 1] + PAGE_SIZE))
1002 break;
1003 }
1004 if (!contiguous)
1005 count--;
1006 num_entries = count *
1007 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1008 }
1009
1010 if (!contiguous) {
1011 addr = cursor.start;
1012 params.pages_addr = pages_addr;
1013 } else {
1014 addr = pages_addr[cursor.start >> PAGE_SHIFT];
1015 params.pages_addr = NULL;
1016 }
1017
1018 } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
1019 addr = vram_base + cursor.start;
1020 } else {
1021 addr = 0;
1022 }
1023
1024 tmp = start + num_entries;
1025 r = amdgpu_vm_ptes_update(¶ms, start, tmp, addr, flags);
1026 if (r)
1027 goto error_free;
1028
1029 amdgpu_res_next(&cursor, num_entries * AMDGPU_GPU_PAGE_SIZE);
1030 start = tmp;
1031 }
1032
1033 r = vm->update_funcs->commit(¶ms, fence);
1034
1035 if (flush_tlb || params.table_freed) {
1036 tlb_cb->vm = vm;
1037 if (fence && *fence &&
1038 !dma_fence_add_callback(*fence, &tlb_cb->cb,
1039 amdgpu_vm_tlb_seq_cb)) {
1040 dma_fence_put(vm->last_tlb_flush);
1041 vm->last_tlb_flush = dma_fence_get(*fence);
1042 } else {
1043 amdgpu_vm_tlb_seq_cb(NULL, &tlb_cb->cb);
1044 }
1045 tlb_cb = NULL;
1046 }
1047
1048error_free:
1049 kfree(tlb_cb);
1050
1051error_unlock:
1052 amdgpu_vm_eviction_unlock(vm);
1053 drm_dev_exit(idx);
1054 return r;
1055}
1056
1057static void amdgpu_vm_bo_get_memory(struct amdgpu_bo_va *bo_va,
1058 struct amdgpu_mem_stats *stats)
1059{
1060 struct amdgpu_vm *vm = bo_va->base.vm;
1061 struct amdgpu_bo *bo = bo_va->base.bo;
1062
1063 if (!bo)
1064 return;
1065
1066 /*
1067 * For now ignore BOs which are currently locked and potentially
1068 * changing their location.
1069 */
1070 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv &&
1071 !dma_resv_trylock(bo->tbo.base.resv))
1072 return;
1073
1074 amdgpu_bo_get_memory(bo, stats);
1075 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
1076 dma_resv_unlock(bo->tbo.base.resv);
1077}
1078
1079void amdgpu_vm_get_memory(struct amdgpu_vm *vm,
1080 struct amdgpu_mem_stats *stats)
1081{
1082 struct amdgpu_bo_va *bo_va, *tmp;
1083
1084 spin_lock(&vm->status_lock);
1085 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status)
1086 amdgpu_vm_bo_get_memory(bo_va, stats);
1087
1088 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status)
1089 amdgpu_vm_bo_get_memory(bo_va, stats);
1090
1091 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status)
1092 amdgpu_vm_bo_get_memory(bo_va, stats);
1093
1094 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status)
1095 amdgpu_vm_bo_get_memory(bo_va, stats);
1096
1097 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status)
1098 amdgpu_vm_bo_get_memory(bo_va, stats);
1099
1100 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status)
1101 amdgpu_vm_bo_get_memory(bo_va, stats);
1102 spin_unlock(&vm->status_lock);
1103}
1104
1105/**
1106 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1107 *
1108 * @adev: amdgpu_device pointer
1109 * @bo_va: requested BO and VM object
1110 * @clear: if true clear the entries
1111 *
1112 * Fill in the page table entries for @bo_va.
1113 *
1114 * Returns:
1115 * 0 for success, -EINVAL for failure.
1116 */
1117int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
1118 bool clear)
1119{
1120 struct amdgpu_bo *bo = bo_va->base.bo;
1121 struct amdgpu_vm *vm = bo_va->base.vm;
1122 struct amdgpu_bo_va_mapping *mapping;
1123 dma_addr_t *pages_addr = NULL;
1124 struct ttm_resource *mem;
1125 struct dma_fence **last_update;
1126 bool flush_tlb = clear;
1127 bool uncached;
1128 struct dma_resv *resv;
1129 uint64_t vram_base;
1130 uint64_t flags;
1131 int r;
1132
1133 if (clear || !bo) {
1134 mem = NULL;
1135 resv = vm->root.bo->tbo.base.resv;
1136 } else {
1137 struct drm_gem_object *obj = &bo->tbo.base;
1138
1139 resv = bo->tbo.base.resv;
1140 if (obj->import_attach && bo_va->is_xgmi) {
1141 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1142 struct drm_gem_object *gobj = dma_buf->priv;
1143 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
1144
1145 if (abo->tbo.resource &&
1146 abo->tbo.resource->mem_type == TTM_PL_VRAM)
1147 bo = gem_to_amdgpu_bo(gobj);
1148 }
1149 mem = bo->tbo.resource;
1150 if (mem && (mem->mem_type == TTM_PL_TT ||
1151 mem->mem_type == AMDGPU_PL_PREEMPT))
1152 pages_addr = bo->tbo.ttm->dma_address;
1153 }
1154
1155 if (bo) {
1156 struct amdgpu_device *bo_adev;
1157
1158 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1159
1160 if (amdgpu_bo_encrypted(bo))
1161 flags |= AMDGPU_PTE_TMZ;
1162
1163 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1164 vram_base = bo_adev->vm_manager.vram_base_offset;
1165 uncached = (bo->flags & AMDGPU_GEM_CREATE_UNCACHED) != 0;
1166 } else {
1167 flags = 0x0;
1168 vram_base = 0;
1169 uncached = false;
1170 }
1171
1172 if (clear || (bo && bo->tbo.base.resv ==
1173 vm->root.bo->tbo.base.resv))
1174 last_update = &vm->last_update;
1175 else
1176 last_update = &bo_va->last_pt_update;
1177
1178 if (!clear && bo_va->base.moved) {
1179 flush_tlb = true;
1180 list_splice_init(&bo_va->valids, &bo_va->invalids);
1181
1182 } else if (bo_va->cleared != clear) {
1183 list_splice_init(&bo_va->valids, &bo_va->invalids);
1184 }
1185
1186 list_for_each_entry(mapping, &bo_va->invalids, list) {
1187 uint64_t update_flags = flags;
1188
1189 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1190 * but in case of something, we filter the flags in first place
1191 */
1192 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1193 update_flags &= ~AMDGPU_PTE_READABLE;
1194 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1195 update_flags &= ~AMDGPU_PTE_WRITEABLE;
1196
1197 /* Apply ASIC specific mapping flags */
1198 amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags);
1199
1200 trace_amdgpu_vm_bo_update(mapping);
1201
1202 r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb,
1203 !uncached, resv, mapping->start, mapping->last,
1204 update_flags, mapping->offset,
1205 vram_base, mem, pages_addr,
1206 last_update);
1207 if (r)
1208 return r;
1209 }
1210
1211 /* If the BO is not in its preferred location add it back to
1212 * the evicted list so that it gets validated again on the
1213 * next command submission.
1214 */
1215 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
1216 uint32_t mem_type = bo->tbo.resource->mem_type;
1217
1218 if (!(bo->preferred_domains &
1219 amdgpu_mem_type_to_domain(mem_type)))
1220 amdgpu_vm_bo_evicted(&bo_va->base);
1221 else
1222 amdgpu_vm_bo_idle(&bo_va->base);
1223 } else {
1224 amdgpu_vm_bo_done(&bo_va->base);
1225 }
1226
1227 list_splice_init(&bo_va->invalids, &bo_va->valids);
1228 bo_va->cleared = clear;
1229 bo_va->base.moved = false;
1230
1231 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1232 list_for_each_entry(mapping, &bo_va->valids, list)
1233 trace_amdgpu_vm_bo_mapping(mapping);
1234 }
1235
1236 return 0;
1237}
1238
1239/**
1240 * amdgpu_vm_update_prt_state - update the global PRT state
1241 *
1242 * @adev: amdgpu_device pointer
1243 */
1244static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1245{
1246 unsigned long flags;
1247 bool enable;
1248
1249 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1250 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1251 adev->gmc.gmc_funcs->set_prt(adev, enable);
1252 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1253}
1254
1255/**
1256 * amdgpu_vm_prt_get - add a PRT user
1257 *
1258 * @adev: amdgpu_device pointer
1259 */
1260static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1261{
1262 if (!adev->gmc.gmc_funcs->set_prt)
1263 return;
1264
1265 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1266 amdgpu_vm_update_prt_state(adev);
1267}
1268
1269/**
1270 * amdgpu_vm_prt_put - drop a PRT user
1271 *
1272 * @adev: amdgpu_device pointer
1273 */
1274static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1275{
1276 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1277 amdgpu_vm_update_prt_state(adev);
1278}
1279
1280/**
1281 * amdgpu_vm_prt_cb - callback for updating the PRT status
1282 *
1283 * @fence: fence for the callback
1284 * @_cb: the callback function
1285 */
1286static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1287{
1288 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1289
1290 amdgpu_vm_prt_put(cb->adev);
1291 kfree(cb);
1292}
1293
1294/**
1295 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1296 *
1297 * @adev: amdgpu_device pointer
1298 * @fence: fence for the callback
1299 */
1300static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1301 struct dma_fence *fence)
1302{
1303 struct amdgpu_prt_cb *cb;
1304
1305 if (!adev->gmc.gmc_funcs->set_prt)
1306 return;
1307
1308 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1309 if (!cb) {
1310 /* Last resort when we are OOM */
1311 if (fence)
1312 dma_fence_wait(fence, false);
1313
1314 amdgpu_vm_prt_put(adev);
1315 } else {
1316 cb->adev = adev;
1317 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1318 amdgpu_vm_prt_cb))
1319 amdgpu_vm_prt_cb(fence, &cb->cb);
1320 }
1321}
1322
1323/**
1324 * amdgpu_vm_free_mapping - free a mapping
1325 *
1326 * @adev: amdgpu_device pointer
1327 * @vm: requested vm
1328 * @mapping: mapping to be freed
1329 * @fence: fence of the unmap operation
1330 *
1331 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1332 */
1333static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1334 struct amdgpu_vm *vm,
1335 struct amdgpu_bo_va_mapping *mapping,
1336 struct dma_fence *fence)
1337{
1338 if (mapping->flags & AMDGPU_PTE_PRT)
1339 amdgpu_vm_add_prt_cb(adev, fence);
1340 kfree(mapping);
1341}
1342
1343/**
1344 * amdgpu_vm_prt_fini - finish all prt mappings
1345 *
1346 * @adev: amdgpu_device pointer
1347 * @vm: requested vm
1348 *
1349 * Register a cleanup callback to disable PRT support after VM dies.
1350 */
1351static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1352{
1353 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1354 struct dma_resv_iter cursor;
1355 struct dma_fence *fence;
1356
1357 dma_resv_for_each_fence(&cursor, resv, DMA_RESV_USAGE_BOOKKEEP, fence) {
1358 /* Add a callback for each fence in the reservation object */
1359 amdgpu_vm_prt_get(adev);
1360 amdgpu_vm_add_prt_cb(adev, fence);
1361 }
1362}
1363
1364/**
1365 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1366 *
1367 * @adev: amdgpu_device pointer
1368 * @vm: requested vm
1369 * @fence: optional resulting fence (unchanged if no work needed to be done
1370 * or if an error occurred)
1371 *
1372 * Make sure all freed BOs are cleared in the PT.
1373 * PTs have to be reserved and mutex must be locked!
1374 *
1375 * Returns:
1376 * 0 for success.
1377 *
1378 */
1379int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1380 struct amdgpu_vm *vm,
1381 struct dma_fence **fence)
1382{
1383 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1384 struct amdgpu_bo_va_mapping *mapping;
1385 uint64_t init_pte_value = 0;
1386 struct dma_fence *f = NULL;
1387 int r;
1388
1389 while (!list_empty(&vm->freed)) {
1390 mapping = list_first_entry(&vm->freed,
1391 struct amdgpu_bo_va_mapping, list);
1392 list_del(&mapping->list);
1393
1394 r = amdgpu_vm_update_range(adev, vm, false, false, true, false,
1395 resv, mapping->start, mapping->last,
1396 init_pte_value, 0, 0, NULL, NULL,
1397 &f);
1398 amdgpu_vm_free_mapping(adev, vm, mapping, f);
1399 if (r) {
1400 dma_fence_put(f);
1401 return r;
1402 }
1403 }
1404
1405 if (fence && f) {
1406 dma_fence_put(*fence);
1407 *fence = f;
1408 } else {
1409 dma_fence_put(f);
1410 }
1411
1412 return 0;
1413
1414}
1415
1416/**
1417 * amdgpu_vm_handle_moved - handle moved BOs in the PT
1418 *
1419 * @adev: amdgpu_device pointer
1420 * @vm: requested vm
1421 * @ticket: optional reservation ticket used to reserve the VM
1422 *
1423 * Make sure all BOs which are moved are updated in the PTs.
1424 *
1425 * Returns:
1426 * 0 for success.
1427 *
1428 * PTs have to be reserved!
1429 */
1430int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
1431 struct amdgpu_vm *vm,
1432 struct ww_acquire_ctx *ticket)
1433{
1434 struct amdgpu_bo_va *bo_va;
1435 struct dma_resv *resv;
1436 bool clear, unlock;
1437 int r;
1438
1439 spin_lock(&vm->status_lock);
1440 while (!list_empty(&vm->moved)) {
1441 bo_va = list_first_entry(&vm->moved, struct amdgpu_bo_va,
1442 base.vm_status);
1443 spin_unlock(&vm->status_lock);
1444
1445 /* Per VM BOs never need to bo cleared in the page tables */
1446 r = amdgpu_vm_bo_update(adev, bo_va, false);
1447 if (r)
1448 return r;
1449 spin_lock(&vm->status_lock);
1450 }
1451
1452 while (!list_empty(&vm->invalidated)) {
1453 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
1454 base.vm_status);
1455 resv = bo_va->base.bo->tbo.base.resv;
1456 spin_unlock(&vm->status_lock);
1457
1458 /* Try to reserve the BO to avoid clearing its ptes */
1459 if (!adev->debug_vm && dma_resv_trylock(resv)) {
1460 clear = false;
1461 unlock = true;
1462 /* The caller is already holding the reservation lock */
1463 } else if (ticket && dma_resv_locking_ctx(resv) == ticket) {
1464 clear = false;
1465 unlock = false;
1466 /* Somebody else is using the BO right now */
1467 } else {
1468 clear = true;
1469 unlock = false;
1470 }
1471
1472 r = amdgpu_vm_bo_update(adev, bo_va, clear);
1473
1474 if (unlock)
1475 dma_resv_unlock(resv);
1476 if (r)
1477 return r;
1478
1479 /* Remember evicted DMABuf imports in compute VMs for later
1480 * validation
1481 */
1482 if (vm->is_compute_context &&
1483 bo_va->base.bo->tbo.base.import_attach &&
1484 (!bo_va->base.bo->tbo.resource ||
1485 bo_va->base.bo->tbo.resource->mem_type == TTM_PL_SYSTEM))
1486 amdgpu_vm_bo_evicted_user(&bo_va->base);
1487
1488 spin_lock(&vm->status_lock);
1489 }
1490 spin_unlock(&vm->status_lock);
1491
1492 return 0;
1493}
1494
1495/**
1496 * amdgpu_vm_flush_compute_tlb - Flush TLB on compute VM
1497 *
1498 * @adev: amdgpu_device pointer
1499 * @vm: requested vm
1500 * @flush_type: flush type
1501 * @xcc_mask: mask of XCCs that belong to the compute partition in need of a TLB flush.
1502 *
1503 * Flush TLB if needed for a compute VM.
1504 *
1505 * Returns:
1506 * 0 for success.
1507 */
1508int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev,
1509 struct amdgpu_vm *vm,
1510 uint32_t flush_type,
1511 uint32_t xcc_mask)
1512{
1513 uint64_t tlb_seq = amdgpu_vm_tlb_seq(vm);
1514 bool all_hub = false;
1515 int xcc = 0, r = 0;
1516
1517 WARN_ON_ONCE(!vm->is_compute_context);
1518
1519 /*
1520 * It can be that we race and lose here, but that is extremely unlikely
1521 * and the worst thing which could happen is that we flush the changes
1522 * into the TLB once more which is harmless.
1523 */
1524 if (atomic64_xchg(&vm->kfd_last_flushed_seq, tlb_seq) == tlb_seq)
1525 return 0;
1526
1527 if (adev->family == AMDGPU_FAMILY_AI ||
1528 adev->family == AMDGPU_FAMILY_RV)
1529 all_hub = true;
1530
1531 for_each_inst(xcc, xcc_mask) {
1532 r = amdgpu_gmc_flush_gpu_tlb_pasid(adev, vm->pasid, flush_type,
1533 all_hub, xcc);
1534 if (r)
1535 break;
1536 }
1537 return r;
1538}
1539
1540/**
1541 * amdgpu_vm_bo_add - add a bo to a specific vm
1542 *
1543 * @adev: amdgpu_device pointer
1544 * @vm: requested vm
1545 * @bo: amdgpu buffer object
1546 *
1547 * Add @bo into the requested vm.
1548 * Add @bo to the list of bos associated with the vm
1549 *
1550 * Returns:
1551 * Newly added bo_va or NULL for failure
1552 *
1553 * Object has to be reserved!
1554 */
1555struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1556 struct amdgpu_vm *vm,
1557 struct amdgpu_bo *bo)
1558{
1559 struct amdgpu_bo_va *bo_va;
1560
1561 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1562 if (bo_va == NULL) {
1563 return NULL;
1564 }
1565 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
1566
1567 bo_va->ref_count = 1;
1568 bo_va->last_pt_update = dma_fence_get_stub();
1569 INIT_LIST_HEAD(&bo_va->valids);
1570 INIT_LIST_HEAD(&bo_va->invalids);
1571
1572 if (!bo)
1573 return bo_va;
1574
1575 dma_resv_assert_held(bo->tbo.base.resv);
1576 if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) {
1577 bo_va->is_xgmi = true;
1578 /* Power up XGMI if it can be potentially used */
1579 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
1580 }
1581
1582 return bo_va;
1583}
1584
1585
1586/**
1587 * amdgpu_vm_bo_insert_map - insert a new mapping
1588 *
1589 * @adev: amdgpu_device pointer
1590 * @bo_va: bo_va to store the address
1591 * @mapping: the mapping to insert
1592 *
1593 * Insert a new mapping into all structures.
1594 */
1595static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
1596 struct amdgpu_bo_va *bo_va,
1597 struct amdgpu_bo_va_mapping *mapping)
1598{
1599 struct amdgpu_vm *vm = bo_va->base.vm;
1600 struct amdgpu_bo *bo = bo_va->base.bo;
1601
1602 mapping->bo_va = bo_va;
1603 list_add(&mapping->list, &bo_va->invalids);
1604 amdgpu_vm_it_insert(mapping, &vm->va);
1605
1606 if (mapping->flags & AMDGPU_PTE_PRT)
1607 amdgpu_vm_prt_get(adev);
1608
1609 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1610 !bo_va->base.moved) {
1611 amdgpu_vm_bo_moved(&bo_va->base);
1612 }
1613 trace_amdgpu_vm_bo_map(bo_va, mapping);
1614}
1615
1616/* Validate operation parameters to prevent potential abuse */
1617static int amdgpu_vm_verify_parameters(struct amdgpu_device *adev,
1618 struct amdgpu_bo *bo,
1619 uint64_t saddr,
1620 uint64_t offset,
1621 uint64_t size)
1622{
1623 uint64_t tmp, lpfn;
1624
1625 if (saddr & AMDGPU_GPU_PAGE_MASK
1626 || offset & AMDGPU_GPU_PAGE_MASK
1627 || size & AMDGPU_GPU_PAGE_MASK)
1628 return -EINVAL;
1629
1630 if (check_add_overflow(saddr, size, &tmp)
1631 || check_add_overflow(offset, size, &tmp)
1632 || size == 0 /* which also leads to end < begin */)
1633 return -EINVAL;
1634
1635 /* make sure object fit at this offset */
1636 if (bo && offset + size > amdgpu_bo_size(bo))
1637 return -EINVAL;
1638
1639 /* Ensure last pfn not exceed max_pfn */
1640 lpfn = (saddr + size - 1) >> AMDGPU_GPU_PAGE_SHIFT;
1641 if (lpfn >= adev->vm_manager.max_pfn)
1642 return -EINVAL;
1643
1644 return 0;
1645}
1646
1647/**
1648 * amdgpu_vm_bo_map - map bo inside a vm
1649 *
1650 * @adev: amdgpu_device pointer
1651 * @bo_va: bo_va to store the address
1652 * @saddr: where to map the BO
1653 * @offset: requested offset in the BO
1654 * @size: BO size in bytes
1655 * @flags: attributes of pages (read/write/valid/etc.)
1656 *
1657 * Add a mapping of the BO at the specefied addr into the VM.
1658 *
1659 * Returns:
1660 * 0 for success, error for failure.
1661 *
1662 * Object has to be reserved and unreserved outside!
1663 */
1664int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1665 struct amdgpu_bo_va *bo_va,
1666 uint64_t saddr, uint64_t offset,
1667 uint64_t size, uint64_t flags)
1668{
1669 struct amdgpu_bo_va_mapping *mapping, *tmp;
1670 struct amdgpu_bo *bo = bo_va->base.bo;
1671 struct amdgpu_vm *vm = bo_va->base.vm;
1672 uint64_t eaddr;
1673 int r;
1674
1675 r = amdgpu_vm_verify_parameters(adev, bo, saddr, offset, size);
1676 if (r)
1677 return r;
1678
1679 saddr /= AMDGPU_GPU_PAGE_SIZE;
1680 eaddr = saddr + (size - 1) / AMDGPU_GPU_PAGE_SIZE;
1681
1682 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1683 if (tmp) {
1684 /* bo and tmp overlap, invalid addr */
1685 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1686 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
1687 tmp->start, tmp->last + 1);
1688 return -EINVAL;
1689 }
1690
1691 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1692 if (!mapping)
1693 return -ENOMEM;
1694
1695 mapping->start = saddr;
1696 mapping->last = eaddr;
1697 mapping->offset = offset;
1698 mapping->flags = flags;
1699
1700 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1701
1702 return 0;
1703}
1704
1705/**
1706 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
1707 *
1708 * @adev: amdgpu_device pointer
1709 * @bo_va: bo_va to store the address
1710 * @saddr: where to map the BO
1711 * @offset: requested offset in the BO
1712 * @size: BO size in bytes
1713 * @flags: attributes of pages (read/write/valid/etc.)
1714 *
1715 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
1716 * mappings as we do so.
1717 *
1718 * Returns:
1719 * 0 for success, error for failure.
1720 *
1721 * Object has to be reserved and unreserved outside!
1722 */
1723int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
1724 struct amdgpu_bo_va *bo_va,
1725 uint64_t saddr, uint64_t offset,
1726 uint64_t size, uint64_t flags)
1727{
1728 struct amdgpu_bo_va_mapping *mapping;
1729 struct amdgpu_bo *bo = bo_va->base.bo;
1730 uint64_t eaddr;
1731 int r;
1732
1733 r = amdgpu_vm_verify_parameters(adev, bo, saddr, offset, size);
1734 if (r)
1735 return r;
1736
1737 /* Allocate all the needed memory */
1738 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1739 if (!mapping)
1740 return -ENOMEM;
1741
1742 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
1743 if (r) {
1744 kfree(mapping);
1745 return r;
1746 }
1747
1748 saddr /= AMDGPU_GPU_PAGE_SIZE;
1749 eaddr = saddr + (size - 1) / AMDGPU_GPU_PAGE_SIZE;
1750
1751 mapping->start = saddr;
1752 mapping->last = eaddr;
1753 mapping->offset = offset;
1754 mapping->flags = flags;
1755
1756 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1757
1758 return 0;
1759}
1760
1761/**
1762 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1763 *
1764 * @adev: amdgpu_device pointer
1765 * @bo_va: bo_va to remove the address from
1766 * @saddr: where to the BO is mapped
1767 *
1768 * Remove a mapping of the BO at the specefied addr from the VM.
1769 *
1770 * Returns:
1771 * 0 for success, error for failure.
1772 *
1773 * Object has to be reserved and unreserved outside!
1774 */
1775int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1776 struct amdgpu_bo_va *bo_va,
1777 uint64_t saddr)
1778{
1779 struct amdgpu_bo_va_mapping *mapping;
1780 struct amdgpu_vm *vm = bo_va->base.vm;
1781 bool valid = true;
1782
1783 saddr /= AMDGPU_GPU_PAGE_SIZE;
1784
1785 list_for_each_entry(mapping, &bo_va->valids, list) {
1786 if (mapping->start == saddr)
1787 break;
1788 }
1789
1790 if (&mapping->list == &bo_va->valids) {
1791 valid = false;
1792
1793 list_for_each_entry(mapping, &bo_va->invalids, list) {
1794 if (mapping->start == saddr)
1795 break;
1796 }
1797
1798 if (&mapping->list == &bo_va->invalids)
1799 return -ENOENT;
1800 }
1801
1802 list_del(&mapping->list);
1803 amdgpu_vm_it_remove(mapping, &vm->va);
1804 mapping->bo_va = NULL;
1805 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1806
1807 if (valid)
1808 list_add(&mapping->list, &vm->freed);
1809 else
1810 amdgpu_vm_free_mapping(adev, vm, mapping,
1811 bo_va->last_pt_update);
1812
1813 return 0;
1814}
1815
1816/**
1817 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
1818 *
1819 * @adev: amdgpu_device pointer
1820 * @vm: VM structure to use
1821 * @saddr: start of the range
1822 * @size: size of the range
1823 *
1824 * Remove all mappings in a range, split them as appropriate.
1825 *
1826 * Returns:
1827 * 0 for success, error for failure.
1828 */
1829int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
1830 struct amdgpu_vm *vm,
1831 uint64_t saddr, uint64_t size)
1832{
1833 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
1834 LIST_HEAD(removed);
1835 uint64_t eaddr;
1836 int r;
1837
1838 r = amdgpu_vm_verify_parameters(adev, NULL, saddr, 0, size);
1839 if (r)
1840 return r;
1841
1842 saddr /= AMDGPU_GPU_PAGE_SIZE;
1843 eaddr = saddr + (size - 1) / AMDGPU_GPU_PAGE_SIZE;
1844
1845 /* Allocate all the needed memory */
1846 before = kzalloc(sizeof(*before), GFP_KERNEL);
1847 if (!before)
1848 return -ENOMEM;
1849 INIT_LIST_HEAD(&before->list);
1850
1851 after = kzalloc(sizeof(*after), GFP_KERNEL);
1852 if (!after) {
1853 kfree(before);
1854 return -ENOMEM;
1855 }
1856 INIT_LIST_HEAD(&after->list);
1857
1858 /* Now gather all removed mappings */
1859 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1860 while (tmp) {
1861 /* Remember mapping split at the start */
1862 if (tmp->start < saddr) {
1863 before->start = tmp->start;
1864 before->last = saddr - 1;
1865 before->offset = tmp->offset;
1866 before->flags = tmp->flags;
1867 before->bo_va = tmp->bo_va;
1868 list_add(&before->list, &tmp->bo_va->invalids);
1869 }
1870
1871 /* Remember mapping split at the end */
1872 if (tmp->last > eaddr) {
1873 after->start = eaddr + 1;
1874 after->last = tmp->last;
1875 after->offset = tmp->offset;
1876 after->offset += (after->start - tmp->start) << PAGE_SHIFT;
1877 after->flags = tmp->flags;
1878 after->bo_va = tmp->bo_va;
1879 list_add(&after->list, &tmp->bo_va->invalids);
1880 }
1881
1882 list_del(&tmp->list);
1883 list_add(&tmp->list, &removed);
1884
1885 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
1886 }
1887
1888 /* And free them up */
1889 list_for_each_entry_safe(tmp, next, &removed, list) {
1890 amdgpu_vm_it_remove(tmp, &vm->va);
1891 list_del(&tmp->list);
1892
1893 if (tmp->start < saddr)
1894 tmp->start = saddr;
1895 if (tmp->last > eaddr)
1896 tmp->last = eaddr;
1897
1898 tmp->bo_va = NULL;
1899 list_add(&tmp->list, &vm->freed);
1900 trace_amdgpu_vm_bo_unmap(NULL, tmp);
1901 }
1902
1903 /* Insert partial mapping before the range */
1904 if (!list_empty(&before->list)) {
1905 struct amdgpu_bo *bo = before->bo_va->base.bo;
1906
1907 amdgpu_vm_it_insert(before, &vm->va);
1908 if (before->flags & AMDGPU_PTE_PRT)
1909 amdgpu_vm_prt_get(adev);
1910
1911 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1912 !before->bo_va->base.moved)
1913 amdgpu_vm_bo_moved(&before->bo_va->base);
1914 } else {
1915 kfree(before);
1916 }
1917
1918 /* Insert partial mapping after the range */
1919 if (!list_empty(&after->list)) {
1920 struct amdgpu_bo *bo = after->bo_va->base.bo;
1921
1922 amdgpu_vm_it_insert(after, &vm->va);
1923 if (after->flags & AMDGPU_PTE_PRT)
1924 amdgpu_vm_prt_get(adev);
1925
1926 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1927 !after->bo_va->base.moved)
1928 amdgpu_vm_bo_moved(&after->bo_va->base);
1929 } else {
1930 kfree(after);
1931 }
1932
1933 return 0;
1934}
1935
1936/**
1937 * amdgpu_vm_bo_lookup_mapping - find mapping by address
1938 *
1939 * @vm: the requested VM
1940 * @addr: the address
1941 *
1942 * Find a mapping by it's address.
1943 *
1944 * Returns:
1945 * The amdgpu_bo_va_mapping matching for addr or NULL
1946 *
1947 */
1948struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
1949 uint64_t addr)
1950{
1951 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
1952}
1953
1954/**
1955 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
1956 *
1957 * @vm: the requested vm
1958 * @ticket: CS ticket
1959 *
1960 * Trace all mappings of BOs reserved during a command submission.
1961 */
1962void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
1963{
1964 struct amdgpu_bo_va_mapping *mapping;
1965
1966 if (!trace_amdgpu_vm_bo_cs_enabled())
1967 return;
1968
1969 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
1970 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
1971 if (mapping->bo_va && mapping->bo_va->base.bo) {
1972 struct amdgpu_bo *bo;
1973
1974 bo = mapping->bo_va->base.bo;
1975 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
1976 ticket)
1977 continue;
1978 }
1979
1980 trace_amdgpu_vm_bo_cs(mapping);
1981 }
1982}
1983
1984/**
1985 * amdgpu_vm_bo_del - remove a bo from a specific vm
1986 *
1987 * @adev: amdgpu_device pointer
1988 * @bo_va: requested bo_va
1989 *
1990 * Remove @bo_va->bo from the requested vm.
1991 *
1992 * Object have to be reserved!
1993 */
1994void amdgpu_vm_bo_del(struct amdgpu_device *adev,
1995 struct amdgpu_bo_va *bo_va)
1996{
1997 struct amdgpu_bo_va_mapping *mapping, *next;
1998 struct amdgpu_bo *bo = bo_va->base.bo;
1999 struct amdgpu_vm *vm = bo_va->base.vm;
2000 struct amdgpu_vm_bo_base **base;
2001
2002 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
2003
2004 if (bo) {
2005 dma_resv_assert_held(bo->tbo.base.resv);
2006 if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
2007 ttm_bo_set_bulk_move(&bo->tbo, NULL);
2008
2009 for (base = &bo_va->base.bo->vm_bo; *base;
2010 base = &(*base)->next) {
2011 if (*base != &bo_va->base)
2012 continue;
2013
2014 *base = bo_va->base.next;
2015 break;
2016 }
2017 }
2018
2019 spin_lock(&vm->status_lock);
2020 list_del(&bo_va->base.vm_status);
2021 spin_unlock(&vm->status_lock);
2022
2023 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2024 list_del(&mapping->list);
2025 amdgpu_vm_it_remove(mapping, &vm->va);
2026 mapping->bo_va = NULL;
2027 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2028 list_add(&mapping->list, &vm->freed);
2029 }
2030 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2031 list_del(&mapping->list);
2032 amdgpu_vm_it_remove(mapping, &vm->va);
2033 amdgpu_vm_free_mapping(adev, vm, mapping,
2034 bo_va->last_pt_update);
2035 }
2036
2037 dma_fence_put(bo_va->last_pt_update);
2038
2039 if (bo && bo_va->is_xgmi)
2040 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
2041
2042 kfree(bo_va);
2043}
2044
2045/**
2046 * amdgpu_vm_evictable - check if we can evict a VM
2047 *
2048 * @bo: A page table of the VM.
2049 *
2050 * Check if it is possible to evict a VM.
2051 */
2052bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
2053{
2054 struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
2055
2056 /* Page tables of a destroyed VM can go away immediately */
2057 if (!bo_base || !bo_base->vm)
2058 return true;
2059
2060 /* Don't evict VM page tables while they are busy */
2061 if (!dma_resv_test_signaled(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP))
2062 return false;
2063
2064 /* Try to block ongoing updates */
2065 if (!amdgpu_vm_eviction_trylock(bo_base->vm))
2066 return false;
2067
2068 /* Don't evict VM page tables while they are updated */
2069 if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) {
2070 amdgpu_vm_eviction_unlock(bo_base->vm);
2071 return false;
2072 }
2073
2074 bo_base->vm->evicting = true;
2075 amdgpu_vm_eviction_unlock(bo_base->vm);
2076 return true;
2077}
2078
2079/**
2080 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2081 *
2082 * @adev: amdgpu_device pointer
2083 * @bo: amdgpu buffer object
2084 * @evicted: is the BO evicted
2085 *
2086 * Mark @bo as invalid.
2087 */
2088void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2089 struct amdgpu_bo *bo, bool evicted)
2090{
2091 struct amdgpu_vm_bo_base *bo_base;
2092
2093 /* shadow bo doesn't have bo base, its validation needs its parent */
2094 if (bo->parent && (amdgpu_bo_shadowed(bo->parent) == bo))
2095 bo = bo->parent;
2096
2097 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2098 struct amdgpu_vm *vm = bo_base->vm;
2099
2100 if (evicted && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
2101 amdgpu_vm_bo_evicted(bo_base);
2102 continue;
2103 }
2104
2105 if (bo_base->moved)
2106 continue;
2107 bo_base->moved = true;
2108
2109 if (bo->tbo.type == ttm_bo_type_kernel)
2110 amdgpu_vm_bo_relocated(bo_base);
2111 else if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
2112 amdgpu_vm_bo_moved(bo_base);
2113 else
2114 amdgpu_vm_bo_invalidated(bo_base);
2115 }
2116}
2117
2118/**
2119 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2120 *
2121 * @vm_size: VM size
2122 *
2123 * Returns:
2124 * VM page table as power of two
2125 */
2126static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2127{
2128 /* Total bits covered by PD + PTs */
2129 unsigned bits = ilog2(vm_size) + 18;
2130
2131 /* Make sure the PD is 4K in size up to 8GB address space.
2132 Above that split equal between PD and PTs */
2133 if (vm_size <= 8)
2134 return (bits - 9);
2135 else
2136 return ((bits + 3) / 2);
2137}
2138
2139/**
2140 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2141 *
2142 * @adev: amdgpu_device pointer
2143 * @min_vm_size: the minimum vm size in GB if it's set auto
2144 * @fragment_size_default: Default PTE fragment size
2145 * @max_level: max VMPT level
2146 * @max_bits: max address space size in bits
2147 *
2148 */
2149void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2150 uint32_t fragment_size_default, unsigned max_level,
2151 unsigned max_bits)
2152{
2153 unsigned int max_size = 1 << (max_bits - 30);
2154 unsigned int vm_size;
2155 uint64_t tmp;
2156
2157 /* adjust vm size first */
2158 if (amdgpu_vm_size != -1) {
2159 vm_size = amdgpu_vm_size;
2160 if (vm_size > max_size) {
2161 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2162 amdgpu_vm_size, max_size);
2163 vm_size = max_size;
2164 }
2165 } else {
2166 struct sysinfo si;
2167 unsigned int phys_ram_gb;
2168
2169 /* Optimal VM size depends on the amount of physical
2170 * RAM available. Underlying requirements and
2171 * assumptions:
2172 *
2173 * - Need to map system memory and VRAM from all GPUs
2174 * - VRAM from other GPUs not known here
2175 * - Assume VRAM <= system memory
2176 * - On GFX8 and older, VM space can be segmented for
2177 * different MTYPEs
2178 * - Need to allow room for fragmentation, guard pages etc.
2179 *
2180 * This adds up to a rough guess of system memory x3.
2181 * Round up to power of two to maximize the available
2182 * VM size with the given page table size.
2183 */
2184 si_meminfo(&si);
2185 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2186 (1 << 30) - 1) >> 30;
2187 vm_size = roundup_pow_of_two(
2188 min(max(phys_ram_gb * 3, min_vm_size), max_size));
2189 }
2190
2191 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2192
2193 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2194 if (amdgpu_vm_block_size != -1)
2195 tmp >>= amdgpu_vm_block_size - 9;
2196 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2197 adev->vm_manager.num_level = min_t(unsigned int, max_level, tmp);
2198 switch (adev->vm_manager.num_level) {
2199 case 3:
2200 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2201 break;
2202 case 2:
2203 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2204 break;
2205 case 1:
2206 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2207 break;
2208 default:
2209 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2210 }
2211 /* block size depends on vm size and hw setup*/
2212 if (amdgpu_vm_block_size != -1)
2213 adev->vm_manager.block_size =
2214 min((unsigned)amdgpu_vm_block_size, max_bits
2215 - AMDGPU_GPU_PAGE_SHIFT
2216 - 9 * adev->vm_manager.num_level);
2217 else if (adev->vm_manager.num_level > 1)
2218 adev->vm_manager.block_size = 9;
2219 else
2220 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2221
2222 if (amdgpu_vm_fragment_size == -1)
2223 adev->vm_manager.fragment_size = fragment_size_default;
2224 else
2225 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2226
2227 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2228 vm_size, adev->vm_manager.num_level + 1,
2229 adev->vm_manager.block_size,
2230 adev->vm_manager.fragment_size);
2231}
2232
2233/**
2234 * amdgpu_vm_wait_idle - wait for the VM to become idle
2235 *
2236 * @vm: VM object to wait for
2237 * @timeout: timeout to wait for VM to become idle
2238 */
2239long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2240{
2241 timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv,
2242 DMA_RESV_USAGE_BOOKKEEP,
2243 true, timeout);
2244 if (timeout <= 0)
2245 return timeout;
2246
2247 return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
2248}
2249
2250static void amdgpu_vm_destroy_task_info(struct kref *kref)
2251{
2252 struct amdgpu_task_info *ti = container_of(kref, struct amdgpu_task_info, refcount);
2253
2254 kfree(ti);
2255}
2256
2257static inline struct amdgpu_vm *
2258amdgpu_vm_get_vm_from_pasid(struct amdgpu_device *adev, u32 pasid)
2259{
2260 struct amdgpu_vm *vm;
2261 unsigned long flags;
2262
2263 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
2264 vm = xa_load(&adev->vm_manager.pasids, pasid);
2265 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
2266
2267 return vm;
2268}
2269
2270/**
2271 * amdgpu_vm_put_task_info - reference down the vm task_info ptr
2272 *
2273 * @task_info: task_info struct under discussion.
2274 *
2275 * frees the vm task_info ptr at the last put
2276 */
2277void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info)
2278{
2279 kref_put(&task_info->refcount, amdgpu_vm_destroy_task_info);
2280}
2281
2282/**
2283 * amdgpu_vm_get_task_info_vm - Extracts task info for a vm.
2284 *
2285 * @vm: VM to get info from
2286 *
2287 * Returns the reference counted task_info structure, which must be
2288 * referenced down with amdgpu_vm_put_task_info.
2289 */
2290struct amdgpu_task_info *
2291amdgpu_vm_get_task_info_vm(struct amdgpu_vm *vm)
2292{
2293 struct amdgpu_task_info *ti = NULL;
2294
2295 if (vm) {
2296 ti = vm->task_info;
2297 kref_get(&vm->task_info->refcount);
2298 }
2299
2300 return ti;
2301}
2302
2303/**
2304 * amdgpu_vm_get_task_info_pasid - Extracts task info for a PASID.
2305 *
2306 * @adev: drm device pointer
2307 * @pasid: PASID identifier for VM
2308 *
2309 * Returns the reference counted task_info structure, which must be
2310 * referenced down with amdgpu_vm_put_task_info.
2311 */
2312struct amdgpu_task_info *
2313amdgpu_vm_get_task_info_pasid(struct amdgpu_device *adev, u32 pasid)
2314{
2315 return amdgpu_vm_get_task_info_vm(
2316 amdgpu_vm_get_vm_from_pasid(adev, pasid));
2317}
2318
2319static int amdgpu_vm_create_task_info(struct amdgpu_vm *vm)
2320{
2321 vm->task_info = kzalloc(sizeof(struct amdgpu_task_info), GFP_KERNEL);
2322 if (!vm->task_info)
2323 return -ENOMEM;
2324
2325 kref_init(&vm->task_info->refcount);
2326 return 0;
2327}
2328
2329/**
2330 * amdgpu_vm_set_task_info - Sets VMs task info.
2331 *
2332 * @vm: vm for which to set the info
2333 */
2334void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
2335{
2336 if (!vm->task_info)
2337 return;
2338
2339 if (vm->task_info->pid == current->pid)
2340 return;
2341
2342 vm->task_info->pid = current->pid;
2343 get_task_comm(vm->task_info->task_name, current);
2344
2345 if (current->group_leader->mm != current->mm)
2346 return;
2347
2348 vm->task_info->tgid = current->group_leader->pid;
2349 get_task_comm(vm->task_info->process_name, current->group_leader);
2350}
2351
2352/**
2353 * amdgpu_vm_init - initialize a vm instance
2354 *
2355 * @adev: amdgpu_device pointer
2356 * @vm: requested vm
2357 * @xcp_id: GPU partition selection id
2358 *
2359 * Init @vm fields.
2360 *
2361 * Returns:
2362 * 0 for success, error for failure.
2363 */
2364int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2365 int32_t xcp_id)
2366{
2367 struct amdgpu_bo *root_bo;
2368 struct amdgpu_bo_vm *root;
2369 int r, i;
2370
2371 vm->va = RB_ROOT_CACHED;
2372 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2373 vm->reserved_vmid[i] = NULL;
2374 INIT_LIST_HEAD(&vm->evicted);
2375 INIT_LIST_HEAD(&vm->evicted_user);
2376 INIT_LIST_HEAD(&vm->relocated);
2377 INIT_LIST_HEAD(&vm->moved);
2378 INIT_LIST_HEAD(&vm->idle);
2379 INIT_LIST_HEAD(&vm->invalidated);
2380 spin_lock_init(&vm->status_lock);
2381 INIT_LIST_HEAD(&vm->freed);
2382 INIT_LIST_HEAD(&vm->done);
2383 INIT_LIST_HEAD(&vm->pt_freed);
2384 INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);
2385 INIT_KFIFO(vm->faults);
2386
2387 r = amdgpu_vm_init_entities(adev, vm);
2388 if (r)
2389 return r;
2390
2391 vm->is_compute_context = false;
2392
2393 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2394 AMDGPU_VM_USE_CPU_FOR_GFX);
2395
2396 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2397 vm->use_cpu_for_update ? "CPU" : "SDMA");
2398 WARN_ONCE((vm->use_cpu_for_update &&
2399 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2400 "CPU update of VM recommended only for large BAR system\n");
2401
2402 if (vm->use_cpu_for_update)
2403 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2404 else
2405 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2406
2407 vm->last_update = dma_fence_get_stub();
2408 vm->last_unlocked = dma_fence_get_stub();
2409 vm->last_tlb_flush = dma_fence_get_stub();
2410 vm->generation = 0;
2411
2412 mutex_init(&vm->eviction_lock);
2413 vm->evicting = false;
2414
2415 r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
2416 false, &root, xcp_id);
2417 if (r)
2418 goto error_free_delayed;
2419
2420 root_bo = amdgpu_bo_ref(&root->bo);
2421 r = amdgpu_bo_reserve(root_bo, true);
2422 if (r) {
2423 amdgpu_bo_unref(&root->shadow);
2424 amdgpu_bo_unref(&root_bo);
2425 goto error_free_delayed;
2426 }
2427
2428 amdgpu_vm_bo_base_init(&vm->root, vm, root_bo);
2429 r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1);
2430 if (r)
2431 goto error_free_root;
2432
2433 r = amdgpu_vm_pt_clear(adev, vm, root, false);
2434 if (r)
2435 goto error_free_root;
2436
2437 r = amdgpu_vm_create_task_info(vm);
2438 if (r)
2439 DRM_DEBUG("Failed to create task info for VM\n");
2440
2441 amdgpu_bo_unreserve(vm->root.bo);
2442 amdgpu_bo_unref(&root_bo);
2443
2444 return 0;
2445
2446error_free_root:
2447 amdgpu_vm_pt_free_root(adev, vm);
2448 amdgpu_bo_unreserve(vm->root.bo);
2449 amdgpu_bo_unref(&root_bo);
2450
2451error_free_delayed:
2452 dma_fence_put(vm->last_tlb_flush);
2453 dma_fence_put(vm->last_unlocked);
2454 amdgpu_vm_fini_entities(vm);
2455
2456 return r;
2457}
2458
2459/**
2460 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2461 *
2462 * @adev: amdgpu_device pointer
2463 * @vm: requested vm
2464 *
2465 * This only works on GFX VMs that don't have any BOs added and no
2466 * page tables allocated yet.
2467 *
2468 * Changes the following VM parameters:
2469 * - use_cpu_for_update
2470 * - pte_supports_ats
2471 *
2472 * Reinitializes the page directory to reflect the changed ATS
2473 * setting.
2474 *
2475 * Returns:
2476 * 0 for success, -errno for errors.
2477 */
2478int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2479{
2480 int r;
2481
2482 r = amdgpu_bo_reserve(vm->root.bo, true);
2483 if (r)
2484 return r;
2485
2486 /* Update VM state */
2487 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2488 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2489 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2490 vm->use_cpu_for_update ? "CPU" : "SDMA");
2491 WARN_ONCE((vm->use_cpu_for_update &&
2492 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2493 "CPU update of VM recommended only for large BAR system\n");
2494
2495 if (vm->use_cpu_for_update) {
2496 /* Sync with last SDMA update/clear before switching to CPU */
2497 r = amdgpu_bo_sync_wait(vm->root.bo,
2498 AMDGPU_FENCE_OWNER_UNDEFINED, true);
2499 if (r)
2500 goto unreserve_bo;
2501
2502 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2503 r = amdgpu_vm_pt_map_tables(adev, vm);
2504 if (r)
2505 goto unreserve_bo;
2506
2507 } else {
2508 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2509 }
2510
2511 dma_fence_put(vm->last_update);
2512 vm->last_update = dma_fence_get_stub();
2513 vm->is_compute_context = true;
2514
2515 /* Free the shadow bo for compute VM */
2516 amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.bo)->shadow);
2517
2518 goto unreserve_bo;
2519
2520unreserve_bo:
2521 amdgpu_bo_unreserve(vm->root.bo);
2522 return r;
2523}
2524
2525/**
2526 * amdgpu_vm_release_compute - release a compute vm
2527 * @adev: amdgpu_device pointer
2528 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
2529 *
2530 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
2531 * pasid from vm. Compute should stop use of vm after this call.
2532 */
2533void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2534{
2535 amdgpu_vm_set_pasid(adev, vm, 0);
2536 vm->is_compute_context = false;
2537}
2538
2539/**
2540 * amdgpu_vm_fini - tear down a vm instance
2541 *
2542 * @adev: amdgpu_device pointer
2543 * @vm: requested vm
2544 *
2545 * Tear down @vm.
2546 * Unbind the VM and remove all bos from the vm bo list
2547 */
2548void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2549{
2550 struct amdgpu_bo_va_mapping *mapping, *tmp;
2551 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
2552 struct amdgpu_bo *root;
2553 unsigned long flags;
2554 int i;
2555
2556 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
2557
2558 flush_work(&vm->pt_free_work);
2559
2560 root = amdgpu_bo_ref(vm->root.bo);
2561 amdgpu_bo_reserve(root, true);
2562 amdgpu_vm_put_task_info(vm->task_info);
2563 amdgpu_vm_set_pasid(adev, vm, 0);
2564 dma_fence_wait(vm->last_unlocked, false);
2565 dma_fence_put(vm->last_unlocked);
2566 dma_fence_wait(vm->last_tlb_flush, false);
2567 /* Make sure that all fence callbacks have completed */
2568 spin_lock_irqsave(vm->last_tlb_flush->lock, flags);
2569 spin_unlock_irqrestore(vm->last_tlb_flush->lock, flags);
2570 dma_fence_put(vm->last_tlb_flush);
2571
2572 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2573 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
2574 amdgpu_vm_prt_fini(adev, vm);
2575 prt_fini_needed = false;
2576 }
2577
2578 list_del(&mapping->list);
2579 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2580 }
2581
2582 amdgpu_vm_pt_free_root(adev, vm);
2583 amdgpu_bo_unreserve(root);
2584 amdgpu_bo_unref(&root);
2585 WARN_ON(vm->root.bo);
2586
2587 amdgpu_vm_fini_entities(vm);
2588
2589 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
2590 dev_err(adev->dev, "still active bo inside vm\n");
2591 }
2592 rbtree_postorder_for_each_entry_safe(mapping, tmp,
2593 &vm->va.rb_root, rb) {
2594 /* Don't remove the mapping here, we don't want to trigger a
2595 * rebalance and the tree is about to be destroyed anyway.
2596 */
2597 list_del(&mapping->list);
2598 kfree(mapping);
2599 }
2600
2601 dma_fence_put(vm->last_update);
2602
2603 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) {
2604 if (vm->reserved_vmid[i]) {
2605 amdgpu_vmid_free_reserved(adev, i);
2606 vm->reserved_vmid[i] = false;
2607 }
2608 }
2609
2610}
2611
2612/**
2613 * amdgpu_vm_manager_init - init the VM manager
2614 *
2615 * @adev: amdgpu_device pointer
2616 *
2617 * Initialize the VM manager structures
2618 */
2619void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2620{
2621 unsigned i;
2622
2623 /* Concurrent flushes are only possible starting with Vega10 and
2624 * are broken on Navi10 and Navi14.
2625 */
2626 adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
2627 adev->asic_type == CHIP_NAVI10 ||
2628 adev->asic_type == CHIP_NAVI14);
2629 amdgpu_vmid_mgr_init(adev);
2630
2631 adev->vm_manager.fence_context =
2632 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2633 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2634 adev->vm_manager.seqno[i] = 0;
2635
2636 spin_lock_init(&adev->vm_manager.prt_lock);
2637 atomic_set(&adev->vm_manager.num_prt_users, 0);
2638
2639 /* If not overridden by the user, by default, only in large BAR systems
2640 * Compute VM tables will be updated by CPU
2641 */
2642#ifdef CONFIG_X86_64
2643 if (amdgpu_vm_update_mode == -1) {
2644 /* For asic with VF MMIO access protection
2645 * avoid using CPU for VM table updates
2646 */
2647 if (amdgpu_gmc_vram_full_visible(&adev->gmc) &&
2648 !amdgpu_sriov_vf_mmio_access_protection(adev))
2649 adev->vm_manager.vm_update_mode =
2650 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
2651 else
2652 adev->vm_manager.vm_update_mode = 0;
2653 } else
2654 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
2655#else
2656 adev->vm_manager.vm_update_mode = 0;
2657#endif
2658
2659 xa_init_flags(&adev->vm_manager.pasids, XA_FLAGS_LOCK_IRQ);
2660}
2661
2662/**
2663 * amdgpu_vm_manager_fini - cleanup VM manager
2664 *
2665 * @adev: amdgpu_device pointer
2666 *
2667 * Cleanup the VM manager and free resources.
2668 */
2669void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2670{
2671 WARN_ON(!xa_empty(&adev->vm_manager.pasids));
2672 xa_destroy(&adev->vm_manager.pasids);
2673
2674 amdgpu_vmid_mgr_fini(adev);
2675}
2676
2677/**
2678 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
2679 *
2680 * @dev: drm device pointer
2681 * @data: drm_amdgpu_vm
2682 * @filp: drm file pointer
2683 *
2684 * Returns:
2685 * 0 for success, -errno for errors.
2686 */
2687int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
2688{
2689 union drm_amdgpu_vm *args = data;
2690 struct amdgpu_device *adev = drm_to_adev(dev);
2691 struct amdgpu_fpriv *fpriv = filp->driver_priv;
2692
2693 /* No valid flags defined yet */
2694 if (args->in.flags)
2695 return -EINVAL;
2696
2697 switch (args->in.op) {
2698 case AMDGPU_VM_OP_RESERVE_VMID:
2699 /* We only have requirement to reserve vmid from gfxhub */
2700 if (!fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {
2701 amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0));
2702 fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = true;
2703 }
2704
2705 break;
2706 case AMDGPU_VM_OP_UNRESERVE_VMID:
2707 if (fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {
2708 amdgpu_vmid_free_reserved(adev, AMDGPU_GFXHUB(0));
2709 fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = false;
2710 }
2711 break;
2712 default:
2713 return -EINVAL;
2714 }
2715
2716 return 0;
2717}
2718
2719/**
2720 * amdgpu_vm_handle_fault - graceful handling of VM faults.
2721 * @adev: amdgpu device pointer
2722 * @pasid: PASID of the VM
2723 * @vmid: VMID, only used for GFX 9.4.3.
2724 * @node_id: Node_id received in IH cookie. Only applicable for
2725 * GFX 9.4.3.
2726 * @addr: Address of the fault
2727 * @write_fault: true is write fault, false is read fault
2728 *
2729 * Try to gracefully handle a VM fault. Return true if the fault was handled and
2730 * shouldn't be reported any more.
2731 */
2732bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
2733 u32 vmid, u32 node_id, uint64_t addr,
2734 bool write_fault)
2735{
2736 bool is_compute_context = false;
2737 struct amdgpu_bo *root;
2738 unsigned long irqflags;
2739 uint64_t value, flags;
2740 struct amdgpu_vm *vm;
2741 int r;
2742
2743 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2744 vm = xa_load(&adev->vm_manager.pasids, pasid);
2745 if (vm) {
2746 root = amdgpu_bo_ref(vm->root.bo);
2747 is_compute_context = vm->is_compute_context;
2748 } else {
2749 root = NULL;
2750 }
2751 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2752
2753 if (!root)
2754 return false;
2755
2756 addr /= AMDGPU_GPU_PAGE_SIZE;
2757
2758 if (is_compute_context && !svm_range_restore_pages(adev, pasid, vmid,
2759 node_id, addr, write_fault)) {
2760 amdgpu_bo_unref(&root);
2761 return true;
2762 }
2763
2764 r = amdgpu_bo_reserve(root, true);
2765 if (r)
2766 goto error_unref;
2767
2768 /* Double check that the VM still exists */
2769 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2770 vm = xa_load(&adev->vm_manager.pasids, pasid);
2771 if (vm && vm->root.bo != root)
2772 vm = NULL;
2773 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2774 if (!vm)
2775 goto error_unlock;
2776
2777 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
2778 AMDGPU_PTE_SYSTEM;
2779
2780 if (is_compute_context) {
2781 /* Intentionally setting invalid PTE flag
2782 * combination to force a no-retry-fault
2783 */
2784 flags = AMDGPU_VM_NORETRY_FLAGS;
2785 value = 0;
2786 } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
2787 /* Redirect the access to the dummy page */
2788 value = adev->dummy_page_addr;
2789 flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
2790 AMDGPU_PTE_WRITEABLE;
2791
2792 } else {
2793 /* Let the hw retry silently on the PTE */
2794 value = 0;
2795 }
2796
2797 r = dma_resv_reserve_fences(root->tbo.base.resv, 1);
2798 if (r) {
2799 pr_debug("failed %d to reserve fence slot\n", r);
2800 goto error_unlock;
2801 }
2802
2803 r = amdgpu_vm_update_range(adev, vm, true, false, false, false,
2804 NULL, addr, addr, flags, value, 0, NULL, NULL, NULL);
2805 if (r)
2806 goto error_unlock;
2807
2808 r = amdgpu_vm_update_pdes(adev, vm, true);
2809
2810error_unlock:
2811 amdgpu_bo_unreserve(root);
2812 if (r < 0)
2813 DRM_ERROR("Can't handle page fault (%d)\n", r);
2814
2815error_unref:
2816 amdgpu_bo_unref(&root);
2817
2818 return false;
2819}
2820
2821#if defined(CONFIG_DEBUG_FS)
2822/**
2823 * amdgpu_debugfs_vm_bo_info - print BO info for the VM
2824 *
2825 * @vm: Requested VM for printing BO info
2826 * @m: debugfs file
2827 *
2828 * Print BO information in debugfs file for the VM
2829 */
2830void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)
2831{
2832 struct amdgpu_bo_va *bo_va, *tmp;
2833 u64 total_idle = 0;
2834 u64 total_evicted = 0;
2835 u64 total_relocated = 0;
2836 u64 total_moved = 0;
2837 u64 total_invalidated = 0;
2838 u64 total_done = 0;
2839 unsigned int total_idle_objs = 0;
2840 unsigned int total_evicted_objs = 0;
2841 unsigned int total_relocated_objs = 0;
2842 unsigned int total_moved_objs = 0;
2843 unsigned int total_invalidated_objs = 0;
2844 unsigned int total_done_objs = 0;
2845 unsigned int id = 0;
2846
2847 spin_lock(&vm->status_lock);
2848 seq_puts(m, "\tIdle BOs:\n");
2849 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
2850 if (!bo_va->base.bo)
2851 continue;
2852 total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2853 }
2854 total_idle_objs = id;
2855 id = 0;
2856
2857 seq_puts(m, "\tEvicted BOs:\n");
2858 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
2859 if (!bo_va->base.bo)
2860 continue;
2861 total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2862 }
2863 total_evicted_objs = id;
2864 id = 0;
2865
2866 seq_puts(m, "\tRelocated BOs:\n");
2867 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
2868 if (!bo_va->base.bo)
2869 continue;
2870 total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2871 }
2872 total_relocated_objs = id;
2873 id = 0;
2874
2875 seq_puts(m, "\tMoved BOs:\n");
2876 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2877 if (!bo_va->base.bo)
2878 continue;
2879 total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2880 }
2881 total_moved_objs = id;
2882 id = 0;
2883
2884 seq_puts(m, "\tInvalidated BOs:\n");
2885 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
2886 if (!bo_va->base.bo)
2887 continue;
2888 total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2889 }
2890 total_invalidated_objs = id;
2891 id = 0;
2892
2893 seq_puts(m, "\tDone BOs:\n");
2894 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
2895 if (!bo_va->base.bo)
2896 continue;
2897 total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2898 }
2899 spin_unlock(&vm->status_lock);
2900 total_done_objs = id;
2901
2902 seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle,
2903 total_idle_objs);
2904 seq_printf(m, "\tTotal evicted size: %12lld\tobjs:\t%d\n", total_evicted,
2905 total_evicted_objs);
2906 seq_printf(m, "\tTotal relocated size: %12lld\tobjs:\t%d\n", total_relocated,
2907 total_relocated_objs);
2908 seq_printf(m, "\tTotal moved size: %12lld\tobjs:\t%d\n", total_moved,
2909 total_moved_objs);
2910 seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated,
2911 total_invalidated_objs);
2912 seq_printf(m, "\tTotal done size: %12lld\tobjs:\t%d\n", total_done,
2913 total_done_objs);
2914}
2915#endif
2916
2917/**
2918 * amdgpu_vm_update_fault_cache - update cached fault into.
2919 * @adev: amdgpu device pointer
2920 * @pasid: PASID of the VM
2921 * @addr: Address of the fault
2922 * @status: GPUVM fault status register
2923 * @vmhub: which vmhub got the fault
2924 *
2925 * Cache the fault info for later use by userspace in debugging.
2926 */
2927void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev,
2928 unsigned int pasid,
2929 uint64_t addr,
2930 uint32_t status,
2931 unsigned int vmhub)
2932{
2933 struct amdgpu_vm *vm;
2934 unsigned long flags;
2935
2936 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
2937
2938 vm = xa_load(&adev->vm_manager.pasids, pasid);
2939 /* Don't update the fault cache if status is 0. In the multiple
2940 * fault case, subsequent faults will return a 0 status which is
2941 * useless for userspace and replaces the useful fault status, so
2942 * only update if status is non-0.
2943 */
2944 if (vm && status) {
2945 vm->fault_info.addr = addr;
2946 vm->fault_info.status = status;
2947 if (AMDGPU_IS_GFXHUB(vmhub)) {
2948 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_GFX;
2949 vm->fault_info.vmhub |=
2950 (vmhub - AMDGPU_GFXHUB_START) << AMDGPU_VMHUB_IDX_SHIFT;
2951 } else if (AMDGPU_IS_MMHUB0(vmhub)) {
2952 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_MM0;
2953 vm->fault_info.vmhub |=
2954 (vmhub - AMDGPU_MMHUB0_START) << AMDGPU_VMHUB_IDX_SHIFT;
2955 } else if (AMDGPU_IS_MMHUB1(vmhub)) {
2956 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_MM1;
2957 vm->fault_info.vmhub |=
2958 (vmhub - AMDGPU_MMHUB1_START) << AMDGPU_VMHUB_IDX_SHIFT;
2959 } else {
2960 WARN_ONCE(1, "Invalid vmhub %u\n", vmhub);
2961 }
2962 }
2963 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
2964}
2965
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/dma-fence-array.h>
30#include <linux/interval_tree_generic.h>
31#include <linux/idr.h>
32#include <linux/dma-buf.h>
33
34#include <drm/amdgpu_drm.h>
35#include <drm/drm_drv.h>
36#include <drm/ttm/ttm_tt.h>
37#include <drm/drm_exec.h>
38#include "amdgpu.h"
39#include "amdgpu_trace.h"
40#include "amdgpu_amdkfd.h"
41#include "amdgpu_gmc.h"
42#include "amdgpu_xgmi.h"
43#include "amdgpu_dma_buf.h"
44#include "amdgpu_res_cursor.h"
45#include "kfd_svm.h"
46
47/**
48 * DOC: GPUVM
49 *
50 * GPUVM is the MMU functionality provided on the GPU.
51 * GPUVM is similar to the legacy GART on older asics, however
52 * rather than there being a single global GART table
53 * for the entire GPU, there can be multiple GPUVM page tables active
54 * at any given time. The GPUVM page tables can contain a mix
55 * VRAM pages and system pages (both memory and MMIO) and system pages
56 * can be mapped as snooped (cached system pages) or unsnooped
57 * (uncached system pages).
58 *
59 * Each active GPUVM has an ID associated with it and there is a page table
60 * linked with each VMID. When executing a command buffer,
61 * the kernel tells the engine what VMID to use for that command
62 * buffer. VMIDs are allocated dynamically as commands are submitted.
63 * The userspace drivers maintain their own address space and the kernel
64 * sets up their pages tables accordingly when they submit their
65 * command buffers and a VMID is assigned.
66 * The hardware supports up to 16 active GPUVMs at any given time.
67 *
68 * Each GPUVM is represented by a 1-2 or 1-5 level page table, depending
69 * on the ASIC family. GPUVM supports RWX attributes on each page as well
70 * as other features such as encryption and caching attributes.
71 *
72 * VMID 0 is special. It is the GPUVM used for the kernel driver. In
73 * addition to an aperture managed by a page table, VMID 0 also has
74 * several other apertures. There is an aperture for direct access to VRAM
75 * and there is a legacy AGP aperture which just forwards accesses directly
76 * to the matching system physical addresses (or IOVAs when an IOMMU is
77 * present). These apertures provide direct access to these memories without
78 * incurring the overhead of a page table. VMID 0 is used by the kernel
79 * driver for tasks like memory management.
80 *
81 * GPU clients (i.e., engines on the GPU) use GPUVM VMIDs to access memory.
82 * For user applications, each application can have their own unique GPUVM
83 * address space. The application manages the address space and the kernel
84 * driver manages the GPUVM page tables for each process. If an GPU client
85 * accesses an invalid page, it will generate a GPU page fault, similar to
86 * accessing an invalid page on a CPU.
87 */
88
89#define START(node) ((node)->start)
90#define LAST(node) ((node)->last)
91
92INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
93 START, LAST, static, amdgpu_vm_it)
94
95#undef START
96#undef LAST
97
98/**
99 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
100 */
101struct amdgpu_prt_cb {
102
103 /**
104 * @adev: amdgpu device
105 */
106 struct amdgpu_device *adev;
107
108 /**
109 * @cb: callback
110 */
111 struct dma_fence_cb cb;
112};
113
114/**
115 * struct amdgpu_vm_tlb_seq_struct - Helper to increment the TLB flush sequence
116 */
117struct amdgpu_vm_tlb_seq_struct {
118 /**
119 * @vm: pointer to the amdgpu_vm structure to set the fence sequence on
120 */
121 struct amdgpu_vm *vm;
122
123 /**
124 * @cb: callback
125 */
126 struct dma_fence_cb cb;
127};
128
129/**
130 * amdgpu_vm_set_pasid - manage pasid and vm ptr mapping
131 *
132 * @adev: amdgpu_device pointer
133 * @vm: amdgpu_vm pointer
134 * @pasid: the pasid the VM is using on this GPU
135 *
136 * Set the pasid this VM is using on this GPU, can also be used to remove the
137 * pasid by passing in zero.
138 *
139 */
140int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm,
141 u32 pasid)
142{
143 int r;
144
145 if (vm->pasid == pasid)
146 return 0;
147
148 if (vm->pasid) {
149 r = xa_err(xa_erase_irq(&adev->vm_manager.pasids, vm->pasid));
150 if (r < 0)
151 return r;
152
153 vm->pasid = 0;
154 }
155
156 if (pasid) {
157 r = xa_err(xa_store_irq(&adev->vm_manager.pasids, pasid, vm,
158 GFP_KERNEL));
159 if (r < 0)
160 return r;
161
162 vm->pasid = pasid;
163 }
164
165
166 return 0;
167}
168
169/**
170 * amdgpu_vm_bo_evicted - vm_bo is evicted
171 *
172 * @vm_bo: vm_bo which is evicted
173 *
174 * State for PDs/PTs and per VM BOs which are not at the location they should
175 * be.
176 */
177static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
178{
179 struct amdgpu_vm *vm = vm_bo->vm;
180 struct amdgpu_bo *bo = vm_bo->bo;
181
182 vm_bo->moved = true;
183 spin_lock(&vm_bo->vm->status_lock);
184 if (bo->tbo.type == ttm_bo_type_kernel)
185 list_move(&vm_bo->vm_status, &vm->evicted);
186 else
187 list_move_tail(&vm_bo->vm_status, &vm->evicted);
188 spin_unlock(&vm_bo->vm->status_lock);
189}
190/**
191 * amdgpu_vm_bo_moved - vm_bo is moved
192 *
193 * @vm_bo: vm_bo which is moved
194 *
195 * State for per VM BOs which are moved, but that change is not yet reflected
196 * in the page tables.
197 */
198static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
199{
200 spin_lock(&vm_bo->vm->status_lock);
201 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
202 spin_unlock(&vm_bo->vm->status_lock);
203}
204
205/**
206 * amdgpu_vm_bo_idle - vm_bo is idle
207 *
208 * @vm_bo: vm_bo which is now idle
209 *
210 * State for PDs/PTs and per VM BOs which have gone through the state machine
211 * and are now idle.
212 */
213static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
214{
215 spin_lock(&vm_bo->vm->status_lock);
216 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
217 spin_unlock(&vm_bo->vm->status_lock);
218 vm_bo->moved = false;
219}
220
221/**
222 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
223 *
224 * @vm_bo: vm_bo which is now invalidated
225 *
226 * State for normal BOs which are invalidated and that change not yet reflected
227 * in the PTs.
228 */
229static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
230{
231 spin_lock(&vm_bo->vm->status_lock);
232 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
233 spin_unlock(&vm_bo->vm->status_lock);
234}
235
236/**
237 * amdgpu_vm_bo_relocated - vm_bo is reloacted
238 *
239 * @vm_bo: vm_bo which is relocated
240 *
241 * State for PDs/PTs which needs to update their parent PD.
242 * For the root PD, just move to idle state.
243 */
244static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
245{
246 if (vm_bo->bo->parent) {
247 spin_lock(&vm_bo->vm->status_lock);
248 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
249 spin_unlock(&vm_bo->vm->status_lock);
250 } else {
251 amdgpu_vm_bo_idle(vm_bo);
252 }
253}
254
255/**
256 * amdgpu_vm_bo_done - vm_bo is done
257 *
258 * @vm_bo: vm_bo which is now done
259 *
260 * State for normal BOs which are invalidated and that change has been updated
261 * in the PTs.
262 */
263static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
264{
265 spin_lock(&vm_bo->vm->status_lock);
266 list_move(&vm_bo->vm_status, &vm_bo->vm->done);
267 spin_unlock(&vm_bo->vm->status_lock);
268}
269
270/**
271 * amdgpu_vm_bo_reset_state_machine - reset the vm_bo state machine
272 * @vm: the VM which state machine to reset
273 *
274 * Move all vm_bo object in the VM into a state where they will be updated
275 * again during validation.
276 */
277static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm)
278{
279 struct amdgpu_vm_bo_base *vm_bo, *tmp;
280
281 spin_lock(&vm->status_lock);
282 list_splice_init(&vm->done, &vm->invalidated);
283 list_for_each_entry(vm_bo, &vm->invalidated, vm_status)
284 vm_bo->moved = true;
285 list_for_each_entry_safe(vm_bo, tmp, &vm->idle, vm_status) {
286 struct amdgpu_bo *bo = vm_bo->bo;
287
288 vm_bo->moved = true;
289 if (!bo || bo->tbo.type != ttm_bo_type_kernel)
290 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
291 else if (bo->parent)
292 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
293 }
294 spin_unlock(&vm->status_lock);
295}
296
297/**
298 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
299 *
300 * @base: base structure for tracking BO usage in a VM
301 * @vm: vm to which bo is to be added
302 * @bo: amdgpu buffer object
303 *
304 * Initialize a bo_va_base structure and add it to the appropriate lists
305 *
306 */
307void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
308 struct amdgpu_vm *vm, struct amdgpu_bo *bo)
309{
310 base->vm = vm;
311 base->bo = bo;
312 base->next = NULL;
313 INIT_LIST_HEAD(&base->vm_status);
314
315 if (!bo)
316 return;
317 base->next = bo->vm_bo;
318 bo->vm_bo = base;
319
320 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
321 return;
322
323 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
324
325 ttm_bo_set_bulk_move(&bo->tbo, &vm->lru_bulk_move);
326 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
327 amdgpu_vm_bo_relocated(base);
328 else
329 amdgpu_vm_bo_idle(base);
330
331 if (bo->preferred_domains &
332 amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type))
333 return;
334
335 /*
336 * we checked all the prerequisites, but it looks like this per vm bo
337 * is currently evicted. add the bo to the evicted list to make sure it
338 * is validated on next vm use to avoid fault.
339 * */
340 amdgpu_vm_bo_evicted(base);
341}
342
343/**
344 * amdgpu_vm_lock_pd - lock PD in drm_exec
345 *
346 * @vm: vm providing the BOs
347 * @exec: drm execution context
348 * @num_fences: number of extra fences to reserve
349 *
350 * Lock the VM root PD in the DRM execution context.
351 */
352int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec,
353 unsigned int num_fences)
354{
355 /* We need at least two fences for the VM PD/PT updates */
356 return drm_exec_prepare_obj(exec, &vm->root.bo->tbo.base,
357 2 + num_fences);
358}
359
360/**
361 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
362 *
363 * @adev: amdgpu device pointer
364 * @vm: vm providing the BOs
365 *
366 * Move all BOs to the end of LRU and remember their positions to put them
367 * together.
368 */
369void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
370 struct amdgpu_vm *vm)
371{
372 spin_lock(&adev->mman.bdev.lru_lock);
373 ttm_lru_bulk_move_tail(&vm->lru_bulk_move);
374 spin_unlock(&adev->mman.bdev.lru_lock);
375}
376
377/* Create scheduler entities for page table updates */
378static int amdgpu_vm_init_entities(struct amdgpu_device *adev,
379 struct amdgpu_vm *vm)
380{
381 int r;
382
383 r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
384 adev->vm_manager.vm_pte_scheds,
385 adev->vm_manager.vm_pte_num_scheds, NULL);
386 if (r)
387 goto error;
388
389 return drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
390 adev->vm_manager.vm_pte_scheds,
391 adev->vm_manager.vm_pte_num_scheds, NULL);
392
393error:
394 drm_sched_entity_destroy(&vm->immediate);
395 return r;
396}
397
398/* Destroy the entities for page table updates again */
399static void amdgpu_vm_fini_entities(struct amdgpu_vm *vm)
400{
401 drm_sched_entity_destroy(&vm->immediate);
402 drm_sched_entity_destroy(&vm->delayed);
403}
404
405/**
406 * amdgpu_vm_generation - return the page table re-generation counter
407 * @adev: the amdgpu_device
408 * @vm: optional VM to check, might be NULL
409 *
410 * Returns a page table re-generation token to allow checking if submissions
411 * are still valid to use this VM. The VM parameter might be NULL in which case
412 * just the VRAM lost counter will be used.
413 */
414uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm)
415{
416 uint64_t result = (u64)atomic_read(&adev->vram_lost_counter) << 32;
417
418 if (!vm)
419 return result;
420
421 result += vm->generation;
422 /* Add one if the page tables will be re-generated on next CS */
423 if (drm_sched_entity_error(&vm->delayed))
424 ++result;
425
426 return result;
427}
428
429/**
430 * amdgpu_vm_validate_pt_bos - validate the page table BOs
431 *
432 * @adev: amdgpu device pointer
433 * @vm: vm providing the BOs
434 * @validate: callback to do the validation
435 * @param: parameter for the validation callback
436 *
437 * Validate the page table BOs on command submission if neccessary.
438 *
439 * Returns:
440 * Validation result.
441 */
442int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
443 int (*validate)(void *p, struct amdgpu_bo *bo),
444 void *param)
445{
446 struct amdgpu_vm_bo_base *bo_base;
447 struct amdgpu_bo *shadow;
448 struct amdgpu_bo *bo;
449 int r;
450
451 if (drm_sched_entity_error(&vm->delayed)) {
452 ++vm->generation;
453 amdgpu_vm_bo_reset_state_machine(vm);
454 amdgpu_vm_fini_entities(vm);
455 r = amdgpu_vm_init_entities(adev, vm);
456 if (r)
457 return r;
458 }
459
460 spin_lock(&vm->status_lock);
461 while (!list_empty(&vm->evicted)) {
462 bo_base = list_first_entry(&vm->evicted,
463 struct amdgpu_vm_bo_base,
464 vm_status);
465 spin_unlock(&vm->status_lock);
466
467 bo = bo_base->bo;
468 shadow = amdgpu_bo_shadowed(bo);
469
470 r = validate(param, bo);
471 if (r)
472 return r;
473 if (shadow) {
474 r = validate(param, shadow);
475 if (r)
476 return r;
477 }
478
479 if (bo->tbo.type != ttm_bo_type_kernel) {
480 amdgpu_vm_bo_moved(bo_base);
481 } else {
482 vm->update_funcs->map_table(to_amdgpu_bo_vm(bo));
483 amdgpu_vm_bo_relocated(bo_base);
484 }
485 spin_lock(&vm->status_lock);
486 }
487 spin_unlock(&vm->status_lock);
488
489 amdgpu_vm_eviction_lock(vm);
490 vm->evicting = false;
491 amdgpu_vm_eviction_unlock(vm);
492
493 return 0;
494}
495
496/**
497 * amdgpu_vm_ready - check VM is ready for updates
498 *
499 * @vm: VM to check
500 *
501 * Check if all VM PDs/PTs are ready for updates
502 *
503 * Returns:
504 * True if VM is not evicting.
505 */
506bool amdgpu_vm_ready(struct amdgpu_vm *vm)
507{
508 bool empty;
509 bool ret;
510
511 amdgpu_vm_eviction_lock(vm);
512 ret = !vm->evicting;
513 amdgpu_vm_eviction_unlock(vm);
514
515 spin_lock(&vm->status_lock);
516 empty = list_empty(&vm->evicted);
517 spin_unlock(&vm->status_lock);
518
519 return ret && empty;
520}
521
522/**
523 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
524 *
525 * @adev: amdgpu_device pointer
526 */
527void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
528{
529 const struct amdgpu_ip_block *ip_block;
530 bool has_compute_vm_bug;
531 struct amdgpu_ring *ring;
532 int i;
533
534 has_compute_vm_bug = false;
535
536 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
537 if (ip_block) {
538 /* Compute has a VM bug for GFX version < 7.
539 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
540 if (ip_block->version->major <= 7)
541 has_compute_vm_bug = true;
542 else if (ip_block->version->major == 8)
543 if (adev->gfx.mec_fw_version < 673)
544 has_compute_vm_bug = true;
545 }
546
547 for (i = 0; i < adev->num_rings; i++) {
548 ring = adev->rings[i];
549 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
550 /* only compute rings */
551 ring->has_compute_vm_bug = has_compute_vm_bug;
552 else
553 ring->has_compute_vm_bug = false;
554 }
555}
556
557/**
558 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
559 *
560 * @ring: ring on which the job will be submitted
561 * @job: job to submit
562 *
563 * Returns:
564 * True if sync is needed.
565 */
566bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
567 struct amdgpu_job *job)
568{
569 struct amdgpu_device *adev = ring->adev;
570 unsigned vmhub = ring->vm_hub;
571 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
572
573 if (job->vmid == 0)
574 return false;
575
576 if (job->vm_needs_flush || ring->has_compute_vm_bug)
577 return true;
578
579 if (ring->funcs->emit_gds_switch && job->gds_switch_needed)
580 return true;
581
582 if (amdgpu_vmid_had_gpu_reset(adev, &id_mgr->ids[job->vmid]))
583 return true;
584
585 return false;
586}
587
588/**
589 * amdgpu_vm_flush - hardware flush the vm
590 *
591 * @ring: ring to use for flush
592 * @job: related job
593 * @need_pipe_sync: is pipe sync needed
594 *
595 * Emit a VM flush when it is necessary.
596 *
597 * Returns:
598 * 0 on success, errno otherwise.
599 */
600int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
601 bool need_pipe_sync)
602{
603 struct amdgpu_device *adev = ring->adev;
604 unsigned vmhub = ring->vm_hub;
605 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
606 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
607 bool spm_update_needed = job->spm_update_needed;
608 bool gds_switch_needed = ring->funcs->emit_gds_switch &&
609 job->gds_switch_needed;
610 bool vm_flush_needed = job->vm_needs_flush;
611 struct dma_fence *fence = NULL;
612 bool pasid_mapping_needed = false;
613 unsigned patch_offset = 0;
614 int r;
615
616 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
617 gds_switch_needed = true;
618 vm_flush_needed = true;
619 pasid_mapping_needed = true;
620 spm_update_needed = true;
621 }
622
623 mutex_lock(&id_mgr->lock);
624 if (id->pasid != job->pasid || !id->pasid_mapping ||
625 !dma_fence_is_signaled(id->pasid_mapping))
626 pasid_mapping_needed = true;
627 mutex_unlock(&id_mgr->lock);
628
629 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
630 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
631 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
632 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
633 ring->funcs->emit_wreg;
634
635 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
636 return 0;
637
638 amdgpu_ring_ib_begin(ring);
639 if (ring->funcs->init_cond_exec)
640 patch_offset = amdgpu_ring_init_cond_exec(ring);
641
642 if (need_pipe_sync)
643 amdgpu_ring_emit_pipeline_sync(ring);
644
645 if (vm_flush_needed) {
646 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
647 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
648 }
649
650 if (pasid_mapping_needed)
651 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
652
653 if (spm_update_needed && adev->gfx.rlc.funcs->update_spm_vmid)
654 adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid);
655
656 if (!ring->is_mes_queue && ring->funcs->emit_gds_switch &&
657 gds_switch_needed) {
658 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
659 job->gds_size, job->gws_base,
660 job->gws_size, job->oa_base,
661 job->oa_size);
662 }
663
664 if (vm_flush_needed || pasid_mapping_needed) {
665 r = amdgpu_fence_emit(ring, &fence, NULL, 0);
666 if (r)
667 return r;
668 }
669
670 if (vm_flush_needed) {
671 mutex_lock(&id_mgr->lock);
672 dma_fence_put(id->last_flush);
673 id->last_flush = dma_fence_get(fence);
674 id->current_gpu_reset_count =
675 atomic_read(&adev->gpu_reset_counter);
676 mutex_unlock(&id_mgr->lock);
677 }
678
679 if (pasid_mapping_needed) {
680 mutex_lock(&id_mgr->lock);
681 id->pasid = job->pasid;
682 dma_fence_put(id->pasid_mapping);
683 id->pasid_mapping = dma_fence_get(fence);
684 mutex_unlock(&id_mgr->lock);
685 }
686 dma_fence_put(fence);
687
688 if (ring->funcs->patch_cond_exec)
689 amdgpu_ring_patch_cond_exec(ring, patch_offset);
690
691 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
692 if (ring->funcs->emit_switch_buffer) {
693 amdgpu_ring_emit_switch_buffer(ring);
694 amdgpu_ring_emit_switch_buffer(ring);
695 }
696 amdgpu_ring_ib_end(ring);
697 return 0;
698}
699
700/**
701 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
702 *
703 * @vm: requested vm
704 * @bo: requested buffer object
705 *
706 * Find @bo inside the requested vm.
707 * Search inside the @bos vm list for the requested vm
708 * Returns the found bo_va or NULL if none is found
709 *
710 * Object has to be reserved!
711 *
712 * Returns:
713 * Found bo_va or NULL.
714 */
715struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
716 struct amdgpu_bo *bo)
717{
718 struct amdgpu_vm_bo_base *base;
719
720 for (base = bo->vm_bo; base; base = base->next) {
721 if (base->vm != vm)
722 continue;
723
724 return container_of(base, struct amdgpu_bo_va, base);
725 }
726 return NULL;
727}
728
729/**
730 * amdgpu_vm_map_gart - Resolve gart mapping of addr
731 *
732 * @pages_addr: optional DMA address to use for lookup
733 * @addr: the unmapped addr
734 *
735 * Look up the physical address of the page that the pte resolves
736 * to.
737 *
738 * Returns:
739 * The pointer for the page table entry.
740 */
741uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
742{
743 uint64_t result;
744
745 /* page table offset */
746 result = pages_addr[addr >> PAGE_SHIFT];
747
748 /* in case cpu page size != gpu page size*/
749 result |= addr & (~PAGE_MASK);
750
751 result &= 0xFFFFFFFFFFFFF000ULL;
752
753 return result;
754}
755
756/**
757 * amdgpu_vm_update_pdes - make sure that all directories are valid
758 *
759 * @adev: amdgpu_device pointer
760 * @vm: requested vm
761 * @immediate: submit immediately to the paging queue
762 *
763 * Makes sure all directories are up to date.
764 *
765 * Returns:
766 * 0 for success, error for failure.
767 */
768int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
769 struct amdgpu_vm *vm, bool immediate)
770{
771 struct amdgpu_vm_update_params params;
772 struct amdgpu_vm_bo_base *entry;
773 bool flush_tlb_needed = false;
774 LIST_HEAD(relocated);
775 int r, idx;
776
777 spin_lock(&vm->status_lock);
778 list_splice_init(&vm->relocated, &relocated);
779 spin_unlock(&vm->status_lock);
780
781 if (list_empty(&relocated))
782 return 0;
783
784 if (!drm_dev_enter(adev_to_drm(adev), &idx))
785 return -ENODEV;
786
787 memset(¶ms, 0, sizeof(params));
788 params.adev = adev;
789 params.vm = vm;
790 params.immediate = immediate;
791
792 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
793 if (r)
794 goto error;
795
796 list_for_each_entry(entry, &relocated, vm_status) {
797 /* vm_flush_needed after updating moved PDEs */
798 flush_tlb_needed |= entry->moved;
799
800 r = amdgpu_vm_pde_update(¶ms, entry);
801 if (r)
802 goto error;
803 }
804
805 r = vm->update_funcs->commit(¶ms, &vm->last_update);
806 if (r)
807 goto error;
808
809 if (flush_tlb_needed)
810 atomic64_inc(&vm->tlb_seq);
811
812 while (!list_empty(&relocated)) {
813 entry = list_first_entry(&relocated, struct amdgpu_vm_bo_base,
814 vm_status);
815 amdgpu_vm_bo_idle(entry);
816 }
817
818error:
819 drm_dev_exit(idx);
820 return r;
821}
822
823/**
824 * amdgpu_vm_tlb_seq_cb - make sure to increment tlb sequence
825 * @fence: unused
826 * @cb: the callback structure
827 *
828 * Increments the tlb sequence to make sure that future CS execute a VM flush.
829 */
830static void amdgpu_vm_tlb_seq_cb(struct dma_fence *fence,
831 struct dma_fence_cb *cb)
832{
833 struct amdgpu_vm_tlb_seq_struct *tlb_cb;
834
835 tlb_cb = container_of(cb, typeof(*tlb_cb), cb);
836 atomic64_inc(&tlb_cb->vm->tlb_seq);
837 kfree(tlb_cb);
838}
839
840/**
841 * amdgpu_vm_update_range - update a range in the vm page table
842 *
843 * @adev: amdgpu_device pointer to use for commands
844 * @vm: the VM to update the range
845 * @immediate: immediate submission in a page fault
846 * @unlocked: unlocked invalidation during MM callback
847 * @flush_tlb: trigger tlb invalidation after update completed
848 * @allow_override: change MTYPE for local NUMA nodes
849 * @resv: fences we need to sync to
850 * @start: start of mapped range
851 * @last: last mapped entry
852 * @flags: flags for the entries
853 * @offset: offset into nodes and pages_addr
854 * @vram_base: base for vram mappings
855 * @res: ttm_resource to map
856 * @pages_addr: DMA addresses to use for mapping
857 * @fence: optional resulting fence
858 *
859 * Fill in the page table entries between @start and @last.
860 *
861 * Returns:
862 * 0 for success, negative erro code for failure.
863 */
864int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
865 bool immediate, bool unlocked, bool flush_tlb, bool allow_override,
866 struct dma_resv *resv, uint64_t start, uint64_t last,
867 uint64_t flags, uint64_t offset, uint64_t vram_base,
868 struct ttm_resource *res, dma_addr_t *pages_addr,
869 struct dma_fence **fence)
870{
871 struct amdgpu_vm_update_params params;
872 struct amdgpu_vm_tlb_seq_struct *tlb_cb;
873 struct amdgpu_res_cursor cursor;
874 enum amdgpu_sync_mode sync_mode;
875 int r, idx;
876
877 if (!drm_dev_enter(adev_to_drm(adev), &idx))
878 return -ENODEV;
879
880 tlb_cb = kmalloc(sizeof(*tlb_cb), GFP_KERNEL);
881 if (!tlb_cb) {
882 r = -ENOMEM;
883 goto error_unlock;
884 }
885
886 /* Vega20+XGMI where PTEs get inadvertently cached in L2 texture cache,
887 * heavy-weight flush TLB unconditionally.
888 */
889 flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
890 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0);
891
892 /*
893 * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
894 */
895 flush_tlb |= amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 0, 0);
896
897 memset(¶ms, 0, sizeof(params));
898 params.adev = adev;
899 params.vm = vm;
900 params.immediate = immediate;
901 params.pages_addr = pages_addr;
902 params.unlocked = unlocked;
903 params.allow_override = allow_override;
904
905 /* Implicitly sync to command submissions in the same VM before
906 * unmapping. Sync to moving fences before mapping.
907 */
908 if (!(flags & AMDGPU_PTE_VALID))
909 sync_mode = AMDGPU_SYNC_EQ_OWNER;
910 else
911 sync_mode = AMDGPU_SYNC_EXPLICIT;
912
913 amdgpu_vm_eviction_lock(vm);
914 if (vm->evicting) {
915 r = -EBUSY;
916 goto error_free;
917 }
918
919 if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
920 struct dma_fence *tmp = dma_fence_get_stub();
921
922 amdgpu_bo_fence(vm->root.bo, vm->last_unlocked, true);
923 swap(vm->last_unlocked, tmp);
924 dma_fence_put(tmp);
925 }
926
927 r = vm->update_funcs->prepare(¶ms, resv, sync_mode);
928 if (r)
929 goto error_free;
930
931 amdgpu_res_first(pages_addr ? NULL : res, offset,
932 (last - start + 1) * AMDGPU_GPU_PAGE_SIZE, &cursor);
933 while (cursor.remaining) {
934 uint64_t tmp, num_entries, addr;
935
936 num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT;
937 if (pages_addr) {
938 bool contiguous = true;
939
940 if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
941 uint64_t pfn = cursor.start >> PAGE_SHIFT;
942 uint64_t count;
943
944 contiguous = pages_addr[pfn + 1] ==
945 pages_addr[pfn] + PAGE_SIZE;
946
947 tmp = num_entries /
948 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
949 for (count = 2; count < tmp; ++count) {
950 uint64_t idx = pfn + count;
951
952 if (contiguous != (pages_addr[idx] ==
953 pages_addr[idx - 1] + PAGE_SIZE))
954 break;
955 }
956 if (!contiguous)
957 count--;
958 num_entries = count *
959 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
960 }
961
962 if (!contiguous) {
963 addr = cursor.start;
964 params.pages_addr = pages_addr;
965 } else {
966 addr = pages_addr[cursor.start >> PAGE_SHIFT];
967 params.pages_addr = NULL;
968 }
969
970 } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
971 addr = vram_base + cursor.start;
972 } else {
973 addr = 0;
974 }
975
976 tmp = start + num_entries;
977 r = amdgpu_vm_ptes_update(¶ms, start, tmp, addr, flags);
978 if (r)
979 goto error_free;
980
981 amdgpu_res_next(&cursor, num_entries * AMDGPU_GPU_PAGE_SIZE);
982 start = tmp;
983 }
984
985 r = vm->update_funcs->commit(¶ms, fence);
986
987 if (flush_tlb || params.table_freed) {
988 tlb_cb->vm = vm;
989 if (fence && *fence &&
990 !dma_fence_add_callback(*fence, &tlb_cb->cb,
991 amdgpu_vm_tlb_seq_cb)) {
992 dma_fence_put(vm->last_tlb_flush);
993 vm->last_tlb_flush = dma_fence_get(*fence);
994 } else {
995 amdgpu_vm_tlb_seq_cb(NULL, &tlb_cb->cb);
996 }
997 tlb_cb = NULL;
998 }
999
1000error_free:
1001 kfree(tlb_cb);
1002
1003error_unlock:
1004 amdgpu_vm_eviction_unlock(vm);
1005 drm_dev_exit(idx);
1006 return r;
1007}
1008
1009static void amdgpu_vm_bo_get_memory(struct amdgpu_bo_va *bo_va,
1010 struct amdgpu_mem_stats *stats)
1011{
1012 struct amdgpu_vm *vm = bo_va->base.vm;
1013 struct amdgpu_bo *bo = bo_va->base.bo;
1014
1015 if (!bo)
1016 return;
1017
1018 /*
1019 * For now ignore BOs which are currently locked and potentially
1020 * changing their location.
1021 */
1022 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv &&
1023 !dma_resv_trylock(bo->tbo.base.resv))
1024 return;
1025
1026 amdgpu_bo_get_memory(bo, stats);
1027 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
1028 dma_resv_unlock(bo->tbo.base.resv);
1029}
1030
1031void amdgpu_vm_get_memory(struct amdgpu_vm *vm,
1032 struct amdgpu_mem_stats *stats)
1033{
1034 struct amdgpu_bo_va *bo_va, *tmp;
1035
1036 spin_lock(&vm->status_lock);
1037 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status)
1038 amdgpu_vm_bo_get_memory(bo_va, stats);
1039
1040 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status)
1041 amdgpu_vm_bo_get_memory(bo_va, stats);
1042
1043 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status)
1044 amdgpu_vm_bo_get_memory(bo_va, stats);
1045
1046 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status)
1047 amdgpu_vm_bo_get_memory(bo_va, stats);
1048
1049 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status)
1050 amdgpu_vm_bo_get_memory(bo_va, stats);
1051
1052 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status)
1053 amdgpu_vm_bo_get_memory(bo_va, stats);
1054 spin_unlock(&vm->status_lock);
1055}
1056
1057/**
1058 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1059 *
1060 * @adev: amdgpu_device pointer
1061 * @bo_va: requested BO and VM object
1062 * @clear: if true clear the entries
1063 *
1064 * Fill in the page table entries for @bo_va.
1065 *
1066 * Returns:
1067 * 0 for success, -EINVAL for failure.
1068 */
1069int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
1070 bool clear)
1071{
1072 struct amdgpu_bo *bo = bo_va->base.bo;
1073 struct amdgpu_vm *vm = bo_va->base.vm;
1074 struct amdgpu_bo_va_mapping *mapping;
1075 dma_addr_t *pages_addr = NULL;
1076 struct ttm_resource *mem;
1077 struct dma_fence **last_update;
1078 bool flush_tlb = clear;
1079 bool uncached;
1080 struct dma_resv *resv;
1081 uint64_t vram_base;
1082 uint64_t flags;
1083 int r;
1084
1085 if (clear || !bo) {
1086 mem = NULL;
1087 resv = vm->root.bo->tbo.base.resv;
1088 } else {
1089 struct drm_gem_object *obj = &bo->tbo.base;
1090
1091 resv = bo->tbo.base.resv;
1092 if (obj->import_attach && bo_va->is_xgmi) {
1093 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1094 struct drm_gem_object *gobj = dma_buf->priv;
1095 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
1096
1097 if (abo->tbo.resource &&
1098 abo->tbo.resource->mem_type == TTM_PL_VRAM)
1099 bo = gem_to_amdgpu_bo(gobj);
1100 }
1101 mem = bo->tbo.resource;
1102 if (mem && (mem->mem_type == TTM_PL_TT ||
1103 mem->mem_type == AMDGPU_PL_PREEMPT))
1104 pages_addr = bo->tbo.ttm->dma_address;
1105 }
1106
1107 if (bo) {
1108 struct amdgpu_device *bo_adev;
1109
1110 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1111
1112 if (amdgpu_bo_encrypted(bo))
1113 flags |= AMDGPU_PTE_TMZ;
1114
1115 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1116 vram_base = bo_adev->vm_manager.vram_base_offset;
1117 uncached = (bo->flags & AMDGPU_GEM_CREATE_UNCACHED) != 0;
1118 } else {
1119 flags = 0x0;
1120 vram_base = 0;
1121 uncached = false;
1122 }
1123
1124 if (clear || (bo && bo->tbo.base.resv ==
1125 vm->root.bo->tbo.base.resv))
1126 last_update = &vm->last_update;
1127 else
1128 last_update = &bo_va->last_pt_update;
1129
1130 if (!clear && bo_va->base.moved) {
1131 flush_tlb = true;
1132 list_splice_init(&bo_va->valids, &bo_va->invalids);
1133
1134 } else if (bo_va->cleared != clear) {
1135 list_splice_init(&bo_va->valids, &bo_va->invalids);
1136 }
1137
1138 list_for_each_entry(mapping, &bo_va->invalids, list) {
1139 uint64_t update_flags = flags;
1140
1141 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1142 * but in case of something, we filter the flags in first place
1143 */
1144 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1145 update_flags &= ~AMDGPU_PTE_READABLE;
1146 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1147 update_flags &= ~AMDGPU_PTE_WRITEABLE;
1148
1149 /* Apply ASIC specific mapping flags */
1150 amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags);
1151
1152 trace_amdgpu_vm_bo_update(mapping);
1153
1154 r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb,
1155 !uncached, resv, mapping->start, mapping->last,
1156 update_flags, mapping->offset,
1157 vram_base, mem, pages_addr,
1158 last_update);
1159 if (r)
1160 return r;
1161 }
1162
1163 /* If the BO is not in its preferred location add it back to
1164 * the evicted list so that it gets validated again on the
1165 * next command submission.
1166 */
1167 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
1168 uint32_t mem_type = bo->tbo.resource->mem_type;
1169
1170 if (!(bo->preferred_domains &
1171 amdgpu_mem_type_to_domain(mem_type)))
1172 amdgpu_vm_bo_evicted(&bo_va->base);
1173 else
1174 amdgpu_vm_bo_idle(&bo_va->base);
1175 } else {
1176 amdgpu_vm_bo_done(&bo_va->base);
1177 }
1178
1179 list_splice_init(&bo_va->invalids, &bo_va->valids);
1180 bo_va->cleared = clear;
1181 bo_va->base.moved = false;
1182
1183 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1184 list_for_each_entry(mapping, &bo_va->valids, list)
1185 trace_amdgpu_vm_bo_mapping(mapping);
1186 }
1187
1188 return 0;
1189}
1190
1191/**
1192 * amdgpu_vm_update_prt_state - update the global PRT state
1193 *
1194 * @adev: amdgpu_device pointer
1195 */
1196static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1197{
1198 unsigned long flags;
1199 bool enable;
1200
1201 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1202 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1203 adev->gmc.gmc_funcs->set_prt(adev, enable);
1204 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1205}
1206
1207/**
1208 * amdgpu_vm_prt_get - add a PRT user
1209 *
1210 * @adev: amdgpu_device pointer
1211 */
1212static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1213{
1214 if (!adev->gmc.gmc_funcs->set_prt)
1215 return;
1216
1217 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1218 amdgpu_vm_update_prt_state(adev);
1219}
1220
1221/**
1222 * amdgpu_vm_prt_put - drop a PRT user
1223 *
1224 * @adev: amdgpu_device pointer
1225 */
1226static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1227{
1228 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1229 amdgpu_vm_update_prt_state(adev);
1230}
1231
1232/**
1233 * amdgpu_vm_prt_cb - callback for updating the PRT status
1234 *
1235 * @fence: fence for the callback
1236 * @_cb: the callback function
1237 */
1238static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1239{
1240 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1241
1242 amdgpu_vm_prt_put(cb->adev);
1243 kfree(cb);
1244}
1245
1246/**
1247 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1248 *
1249 * @adev: amdgpu_device pointer
1250 * @fence: fence for the callback
1251 */
1252static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1253 struct dma_fence *fence)
1254{
1255 struct amdgpu_prt_cb *cb;
1256
1257 if (!adev->gmc.gmc_funcs->set_prt)
1258 return;
1259
1260 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1261 if (!cb) {
1262 /* Last resort when we are OOM */
1263 if (fence)
1264 dma_fence_wait(fence, false);
1265
1266 amdgpu_vm_prt_put(adev);
1267 } else {
1268 cb->adev = adev;
1269 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1270 amdgpu_vm_prt_cb))
1271 amdgpu_vm_prt_cb(fence, &cb->cb);
1272 }
1273}
1274
1275/**
1276 * amdgpu_vm_free_mapping - free a mapping
1277 *
1278 * @adev: amdgpu_device pointer
1279 * @vm: requested vm
1280 * @mapping: mapping to be freed
1281 * @fence: fence of the unmap operation
1282 *
1283 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1284 */
1285static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1286 struct amdgpu_vm *vm,
1287 struct amdgpu_bo_va_mapping *mapping,
1288 struct dma_fence *fence)
1289{
1290 if (mapping->flags & AMDGPU_PTE_PRT)
1291 amdgpu_vm_add_prt_cb(adev, fence);
1292 kfree(mapping);
1293}
1294
1295/**
1296 * amdgpu_vm_prt_fini - finish all prt mappings
1297 *
1298 * @adev: amdgpu_device pointer
1299 * @vm: requested vm
1300 *
1301 * Register a cleanup callback to disable PRT support after VM dies.
1302 */
1303static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1304{
1305 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1306 struct dma_resv_iter cursor;
1307 struct dma_fence *fence;
1308
1309 dma_resv_for_each_fence(&cursor, resv, DMA_RESV_USAGE_BOOKKEEP, fence) {
1310 /* Add a callback for each fence in the reservation object */
1311 amdgpu_vm_prt_get(adev);
1312 amdgpu_vm_add_prt_cb(adev, fence);
1313 }
1314}
1315
1316/**
1317 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1318 *
1319 * @adev: amdgpu_device pointer
1320 * @vm: requested vm
1321 * @fence: optional resulting fence (unchanged if no work needed to be done
1322 * or if an error occurred)
1323 *
1324 * Make sure all freed BOs are cleared in the PT.
1325 * PTs have to be reserved and mutex must be locked!
1326 *
1327 * Returns:
1328 * 0 for success.
1329 *
1330 */
1331int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1332 struct amdgpu_vm *vm,
1333 struct dma_fence **fence)
1334{
1335 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1336 struct amdgpu_bo_va_mapping *mapping;
1337 uint64_t init_pte_value = 0;
1338 struct dma_fence *f = NULL;
1339 int r;
1340
1341 while (!list_empty(&vm->freed)) {
1342 mapping = list_first_entry(&vm->freed,
1343 struct amdgpu_bo_va_mapping, list);
1344 list_del(&mapping->list);
1345
1346 if (vm->pte_support_ats &&
1347 mapping->start < AMDGPU_GMC_HOLE_START)
1348 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
1349
1350 r = amdgpu_vm_update_range(adev, vm, false, false, true, false,
1351 resv, mapping->start, mapping->last,
1352 init_pte_value, 0, 0, NULL, NULL,
1353 &f);
1354 amdgpu_vm_free_mapping(adev, vm, mapping, f);
1355 if (r) {
1356 dma_fence_put(f);
1357 return r;
1358 }
1359 }
1360
1361 if (fence && f) {
1362 dma_fence_put(*fence);
1363 *fence = f;
1364 } else {
1365 dma_fence_put(f);
1366 }
1367
1368 return 0;
1369
1370}
1371
1372/**
1373 * amdgpu_vm_handle_moved - handle moved BOs in the PT
1374 *
1375 * @adev: amdgpu_device pointer
1376 * @vm: requested vm
1377 * @ticket: optional reservation ticket used to reserve the VM
1378 *
1379 * Make sure all BOs which are moved are updated in the PTs.
1380 *
1381 * Returns:
1382 * 0 for success.
1383 *
1384 * PTs have to be reserved!
1385 */
1386int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
1387 struct amdgpu_vm *vm,
1388 struct ww_acquire_ctx *ticket)
1389{
1390 struct amdgpu_bo_va *bo_va;
1391 struct dma_resv *resv;
1392 bool clear, unlock;
1393 int r;
1394
1395 spin_lock(&vm->status_lock);
1396 while (!list_empty(&vm->moved)) {
1397 bo_va = list_first_entry(&vm->moved, struct amdgpu_bo_va,
1398 base.vm_status);
1399 spin_unlock(&vm->status_lock);
1400
1401 /* Per VM BOs never need to bo cleared in the page tables */
1402 r = amdgpu_vm_bo_update(adev, bo_va, false);
1403 if (r)
1404 return r;
1405 spin_lock(&vm->status_lock);
1406 }
1407
1408 while (!list_empty(&vm->invalidated)) {
1409 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
1410 base.vm_status);
1411 resv = bo_va->base.bo->tbo.base.resv;
1412 spin_unlock(&vm->status_lock);
1413
1414 /* Try to reserve the BO to avoid clearing its ptes */
1415 if (!adev->debug_vm && dma_resv_trylock(resv)) {
1416 clear = false;
1417 unlock = true;
1418 /* The caller is already holding the reservation lock */
1419 } else if (ticket && dma_resv_locking_ctx(resv) == ticket) {
1420 clear = false;
1421 unlock = false;
1422 /* Somebody else is using the BO right now */
1423 } else {
1424 clear = true;
1425 unlock = false;
1426 }
1427
1428 r = amdgpu_vm_bo_update(adev, bo_va, clear);
1429 if (r)
1430 return r;
1431
1432 if (unlock)
1433 dma_resv_unlock(resv);
1434 spin_lock(&vm->status_lock);
1435 }
1436 spin_unlock(&vm->status_lock);
1437
1438 return 0;
1439}
1440
1441/**
1442 * amdgpu_vm_flush_compute_tlb - Flush TLB on compute VM
1443 *
1444 * @adev: amdgpu_device pointer
1445 * @vm: requested vm
1446 * @flush_type: flush type
1447 * @xcc_mask: mask of XCCs that belong to the compute partition in need of a TLB flush.
1448 *
1449 * Flush TLB if needed for a compute VM.
1450 *
1451 * Returns:
1452 * 0 for success.
1453 */
1454int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev,
1455 struct amdgpu_vm *vm,
1456 uint32_t flush_type,
1457 uint32_t xcc_mask)
1458{
1459 uint64_t tlb_seq = amdgpu_vm_tlb_seq(vm);
1460 bool all_hub = false;
1461 int xcc = 0, r = 0;
1462
1463 WARN_ON_ONCE(!vm->is_compute_context);
1464
1465 /*
1466 * It can be that we race and lose here, but that is extremely unlikely
1467 * and the worst thing which could happen is that we flush the changes
1468 * into the TLB once more which is harmless.
1469 */
1470 if (atomic64_xchg(&vm->kfd_last_flushed_seq, tlb_seq) == tlb_seq)
1471 return 0;
1472
1473 if (adev->family == AMDGPU_FAMILY_AI ||
1474 adev->family == AMDGPU_FAMILY_RV)
1475 all_hub = true;
1476
1477 for_each_inst(xcc, xcc_mask) {
1478 r = amdgpu_gmc_flush_gpu_tlb_pasid(adev, vm->pasid, flush_type,
1479 all_hub, xcc);
1480 if (r)
1481 break;
1482 }
1483 return r;
1484}
1485
1486/**
1487 * amdgpu_vm_bo_add - add a bo to a specific vm
1488 *
1489 * @adev: amdgpu_device pointer
1490 * @vm: requested vm
1491 * @bo: amdgpu buffer object
1492 *
1493 * Add @bo into the requested vm.
1494 * Add @bo to the list of bos associated with the vm
1495 *
1496 * Returns:
1497 * Newly added bo_va or NULL for failure
1498 *
1499 * Object has to be reserved!
1500 */
1501struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1502 struct amdgpu_vm *vm,
1503 struct amdgpu_bo *bo)
1504{
1505 struct amdgpu_bo_va *bo_va;
1506
1507 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1508 if (bo_va == NULL) {
1509 return NULL;
1510 }
1511 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
1512
1513 bo_va->ref_count = 1;
1514 bo_va->last_pt_update = dma_fence_get_stub();
1515 INIT_LIST_HEAD(&bo_va->valids);
1516 INIT_LIST_HEAD(&bo_va->invalids);
1517
1518 if (!bo)
1519 return bo_va;
1520
1521 dma_resv_assert_held(bo->tbo.base.resv);
1522 if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) {
1523 bo_va->is_xgmi = true;
1524 /* Power up XGMI if it can be potentially used */
1525 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
1526 }
1527
1528 return bo_va;
1529}
1530
1531
1532/**
1533 * amdgpu_vm_bo_insert_map - insert a new mapping
1534 *
1535 * @adev: amdgpu_device pointer
1536 * @bo_va: bo_va to store the address
1537 * @mapping: the mapping to insert
1538 *
1539 * Insert a new mapping into all structures.
1540 */
1541static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
1542 struct amdgpu_bo_va *bo_va,
1543 struct amdgpu_bo_va_mapping *mapping)
1544{
1545 struct amdgpu_vm *vm = bo_va->base.vm;
1546 struct amdgpu_bo *bo = bo_va->base.bo;
1547
1548 mapping->bo_va = bo_va;
1549 list_add(&mapping->list, &bo_va->invalids);
1550 amdgpu_vm_it_insert(mapping, &vm->va);
1551
1552 if (mapping->flags & AMDGPU_PTE_PRT)
1553 amdgpu_vm_prt_get(adev);
1554
1555 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1556 !bo_va->base.moved) {
1557 amdgpu_vm_bo_moved(&bo_va->base);
1558 }
1559 trace_amdgpu_vm_bo_map(bo_va, mapping);
1560}
1561
1562/**
1563 * amdgpu_vm_bo_map - map bo inside a vm
1564 *
1565 * @adev: amdgpu_device pointer
1566 * @bo_va: bo_va to store the address
1567 * @saddr: where to map the BO
1568 * @offset: requested offset in the BO
1569 * @size: BO size in bytes
1570 * @flags: attributes of pages (read/write/valid/etc.)
1571 *
1572 * Add a mapping of the BO at the specefied addr into the VM.
1573 *
1574 * Returns:
1575 * 0 for success, error for failure.
1576 *
1577 * Object has to be reserved and unreserved outside!
1578 */
1579int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1580 struct amdgpu_bo_va *bo_va,
1581 uint64_t saddr, uint64_t offset,
1582 uint64_t size, uint64_t flags)
1583{
1584 struct amdgpu_bo_va_mapping *mapping, *tmp;
1585 struct amdgpu_bo *bo = bo_va->base.bo;
1586 struct amdgpu_vm *vm = bo_va->base.vm;
1587 uint64_t eaddr;
1588
1589 /* validate the parameters */
1590 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK || size & ~PAGE_MASK)
1591 return -EINVAL;
1592 if (saddr + size <= saddr || offset + size <= offset)
1593 return -EINVAL;
1594
1595 /* make sure object fit at this offset */
1596 eaddr = saddr + size - 1;
1597 if ((bo && offset + size > amdgpu_bo_size(bo)) ||
1598 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
1599 return -EINVAL;
1600
1601 saddr /= AMDGPU_GPU_PAGE_SIZE;
1602 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1603
1604 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1605 if (tmp) {
1606 /* bo and tmp overlap, invalid addr */
1607 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1608 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
1609 tmp->start, tmp->last + 1);
1610 return -EINVAL;
1611 }
1612
1613 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1614 if (!mapping)
1615 return -ENOMEM;
1616
1617 mapping->start = saddr;
1618 mapping->last = eaddr;
1619 mapping->offset = offset;
1620 mapping->flags = flags;
1621
1622 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1623
1624 return 0;
1625}
1626
1627/**
1628 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
1629 *
1630 * @adev: amdgpu_device pointer
1631 * @bo_va: bo_va to store the address
1632 * @saddr: where to map the BO
1633 * @offset: requested offset in the BO
1634 * @size: BO size in bytes
1635 * @flags: attributes of pages (read/write/valid/etc.)
1636 *
1637 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
1638 * mappings as we do so.
1639 *
1640 * Returns:
1641 * 0 for success, error for failure.
1642 *
1643 * Object has to be reserved and unreserved outside!
1644 */
1645int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
1646 struct amdgpu_bo_va *bo_va,
1647 uint64_t saddr, uint64_t offset,
1648 uint64_t size, uint64_t flags)
1649{
1650 struct amdgpu_bo_va_mapping *mapping;
1651 struct amdgpu_bo *bo = bo_va->base.bo;
1652 uint64_t eaddr;
1653 int r;
1654
1655 /* validate the parameters */
1656 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK || size & ~PAGE_MASK)
1657 return -EINVAL;
1658 if (saddr + size <= saddr || offset + size <= offset)
1659 return -EINVAL;
1660
1661 /* make sure object fit at this offset */
1662 eaddr = saddr + size - 1;
1663 if ((bo && offset + size > amdgpu_bo_size(bo)) ||
1664 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
1665 return -EINVAL;
1666
1667 /* Allocate all the needed memory */
1668 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1669 if (!mapping)
1670 return -ENOMEM;
1671
1672 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
1673 if (r) {
1674 kfree(mapping);
1675 return r;
1676 }
1677
1678 saddr /= AMDGPU_GPU_PAGE_SIZE;
1679 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1680
1681 mapping->start = saddr;
1682 mapping->last = eaddr;
1683 mapping->offset = offset;
1684 mapping->flags = flags;
1685
1686 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1687
1688 return 0;
1689}
1690
1691/**
1692 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1693 *
1694 * @adev: amdgpu_device pointer
1695 * @bo_va: bo_va to remove the address from
1696 * @saddr: where to the BO is mapped
1697 *
1698 * Remove a mapping of the BO at the specefied addr from the VM.
1699 *
1700 * Returns:
1701 * 0 for success, error for failure.
1702 *
1703 * Object has to be reserved and unreserved outside!
1704 */
1705int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1706 struct amdgpu_bo_va *bo_va,
1707 uint64_t saddr)
1708{
1709 struct amdgpu_bo_va_mapping *mapping;
1710 struct amdgpu_vm *vm = bo_va->base.vm;
1711 bool valid = true;
1712
1713 saddr /= AMDGPU_GPU_PAGE_SIZE;
1714
1715 list_for_each_entry(mapping, &bo_va->valids, list) {
1716 if (mapping->start == saddr)
1717 break;
1718 }
1719
1720 if (&mapping->list == &bo_va->valids) {
1721 valid = false;
1722
1723 list_for_each_entry(mapping, &bo_va->invalids, list) {
1724 if (mapping->start == saddr)
1725 break;
1726 }
1727
1728 if (&mapping->list == &bo_va->invalids)
1729 return -ENOENT;
1730 }
1731
1732 list_del(&mapping->list);
1733 amdgpu_vm_it_remove(mapping, &vm->va);
1734 mapping->bo_va = NULL;
1735 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1736
1737 if (valid)
1738 list_add(&mapping->list, &vm->freed);
1739 else
1740 amdgpu_vm_free_mapping(adev, vm, mapping,
1741 bo_va->last_pt_update);
1742
1743 return 0;
1744}
1745
1746/**
1747 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
1748 *
1749 * @adev: amdgpu_device pointer
1750 * @vm: VM structure to use
1751 * @saddr: start of the range
1752 * @size: size of the range
1753 *
1754 * Remove all mappings in a range, split them as appropriate.
1755 *
1756 * Returns:
1757 * 0 for success, error for failure.
1758 */
1759int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
1760 struct amdgpu_vm *vm,
1761 uint64_t saddr, uint64_t size)
1762{
1763 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
1764 LIST_HEAD(removed);
1765 uint64_t eaddr;
1766
1767 eaddr = saddr + size - 1;
1768 saddr /= AMDGPU_GPU_PAGE_SIZE;
1769 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1770
1771 /* Allocate all the needed memory */
1772 before = kzalloc(sizeof(*before), GFP_KERNEL);
1773 if (!before)
1774 return -ENOMEM;
1775 INIT_LIST_HEAD(&before->list);
1776
1777 after = kzalloc(sizeof(*after), GFP_KERNEL);
1778 if (!after) {
1779 kfree(before);
1780 return -ENOMEM;
1781 }
1782 INIT_LIST_HEAD(&after->list);
1783
1784 /* Now gather all removed mappings */
1785 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1786 while (tmp) {
1787 /* Remember mapping split at the start */
1788 if (tmp->start < saddr) {
1789 before->start = tmp->start;
1790 before->last = saddr - 1;
1791 before->offset = tmp->offset;
1792 before->flags = tmp->flags;
1793 before->bo_va = tmp->bo_va;
1794 list_add(&before->list, &tmp->bo_va->invalids);
1795 }
1796
1797 /* Remember mapping split at the end */
1798 if (tmp->last > eaddr) {
1799 after->start = eaddr + 1;
1800 after->last = tmp->last;
1801 after->offset = tmp->offset;
1802 after->offset += (after->start - tmp->start) << PAGE_SHIFT;
1803 after->flags = tmp->flags;
1804 after->bo_va = tmp->bo_va;
1805 list_add(&after->list, &tmp->bo_va->invalids);
1806 }
1807
1808 list_del(&tmp->list);
1809 list_add(&tmp->list, &removed);
1810
1811 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
1812 }
1813
1814 /* And free them up */
1815 list_for_each_entry_safe(tmp, next, &removed, list) {
1816 amdgpu_vm_it_remove(tmp, &vm->va);
1817 list_del(&tmp->list);
1818
1819 if (tmp->start < saddr)
1820 tmp->start = saddr;
1821 if (tmp->last > eaddr)
1822 tmp->last = eaddr;
1823
1824 tmp->bo_va = NULL;
1825 list_add(&tmp->list, &vm->freed);
1826 trace_amdgpu_vm_bo_unmap(NULL, tmp);
1827 }
1828
1829 /* Insert partial mapping before the range */
1830 if (!list_empty(&before->list)) {
1831 struct amdgpu_bo *bo = before->bo_va->base.bo;
1832
1833 amdgpu_vm_it_insert(before, &vm->va);
1834 if (before->flags & AMDGPU_PTE_PRT)
1835 amdgpu_vm_prt_get(adev);
1836
1837 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1838 !before->bo_va->base.moved)
1839 amdgpu_vm_bo_moved(&before->bo_va->base);
1840 } else {
1841 kfree(before);
1842 }
1843
1844 /* Insert partial mapping after the range */
1845 if (!list_empty(&after->list)) {
1846 struct amdgpu_bo *bo = after->bo_va->base.bo;
1847
1848 amdgpu_vm_it_insert(after, &vm->va);
1849 if (after->flags & AMDGPU_PTE_PRT)
1850 amdgpu_vm_prt_get(adev);
1851
1852 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1853 !after->bo_va->base.moved)
1854 amdgpu_vm_bo_moved(&after->bo_va->base);
1855 } else {
1856 kfree(after);
1857 }
1858
1859 return 0;
1860}
1861
1862/**
1863 * amdgpu_vm_bo_lookup_mapping - find mapping by address
1864 *
1865 * @vm: the requested VM
1866 * @addr: the address
1867 *
1868 * Find a mapping by it's address.
1869 *
1870 * Returns:
1871 * The amdgpu_bo_va_mapping matching for addr or NULL
1872 *
1873 */
1874struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
1875 uint64_t addr)
1876{
1877 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
1878}
1879
1880/**
1881 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
1882 *
1883 * @vm: the requested vm
1884 * @ticket: CS ticket
1885 *
1886 * Trace all mappings of BOs reserved during a command submission.
1887 */
1888void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
1889{
1890 struct amdgpu_bo_va_mapping *mapping;
1891
1892 if (!trace_amdgpu_vm_bo_cs_enabled())
1893 return;
1894
1895 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
1896 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
1897 if (mapping->bo_va && mapping->bo_va->base.bo) {
1898 struct amdgpu_bo *bo;
1899
1900 bo = mapping->bo_va->base.bo;
1901 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
1902 ticket)
1903 continue;
1904 }
1905
1906 trace_amdgpu_vm_bo_cs(mapping);
1907 }
1908}
1909
1910/**
1911 * amdgpu_vm_bo_del - remove a bo from a specific vm
1912 *
1913 * @adev: amdgpu_device pointer
1914 * @bo_va: requested bo_va
1915 *
1916 * Remove @bo_va->bo from the requested vm.
1917 *
1918 * Object have to be reserved!
1919 */
1920void amdgpu_vm_bo_del(struct amdgpu_device *adev,
1921 struct amdgpu_bo_va *bo_va)
1922{
1923 struct amdgpu_bo_va_mapping *mapping, *next;
1924 struct amdgpu_bo *bo = bo_va->base.bo;
1925 struct amdgpu_vm *vm = bo_va->base.vm;
1926 struct amdgpu_vm_bo_base **base;
1927
1928 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
1929
1930 if (bo) {
1931 dma_resv_assert_held(bo->tbo.base.resv);
1932 if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
1933 ttm_bo_set_bulk_move(&bo->tbo, NULL);
1934
1935 for (base = &bo_va->base.bo->vm_bo; *base;
1936 base = &(*base)->next) {
1937 if (*base != &bo_va->base)
1938 continue;
1939
1940 *base = bo_va->base.next;
1941 break;
1942 }
1943 }
1944
1945 spin_lock(&vm->status_lock);
1946 list_del(&bo_va->base.vm_status);
1947 spin_unlock(&vm->status_lock);
1948
1949 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
1950 list_del(&mapping->list);
1951 amdgpu_vm_it_remove(mapping, &vm->va);
1952 mapping->bo_va = NULL;
1953 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1954 list_add(&mapping->list, &vm->freed);
1955 }
1956 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
1957 list_del(&mapping->list);
1958 amdgpu_vm_it_remove(mapping, &vm->va);
1959 amdgpu_vm_free_mapping(adev, vm, mapping,
1960 bo_va->last_pt_update);
1961 }
1962
1963 dma_fence_put(bo_va->last_pt_update);
1964
1965 if (bo && bo_va->is_xgmi)
1966 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
1967
1968 kfree(bo_va);
1969}
1970
1971/**
1972 * amdgpu_vm_evictable - check if we can evict a VM
1973 *
1974 * @bo: A page table of the VM.
1975 *
1976 * Check if it is possible to evict a VM.
1977 */
1978bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
1979{
1980 struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
1981
1982 /* Page tables of a destroyed VM can go away immediately */
1983 if (!bo_base || !bo_base->vm)
1984 return true;
1985
1986 /* Don't evict VM page tables while they are busy */
1987 if (!dma_resv_test_signaled(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP))
1988 return false;
1989
1990 /* Try to block ongoing updates */
1991 if (!amdgpu_vm_eviction_trylock(bo_base->vm))
1992 return false;
1993
1994 /* Don't evict VM page tables while they are updated */
1995 if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) {
1996 amdgpu_vm_eviction_unlock(bo_base->vm);
1997 return false;
1998 }
1999
2000 bo_base->vm->evicting = true;
2001 amdgpu_vm_eviction_unlock(bo_base->vm);
2002 return true;
2003}
2004
2005/**
2006 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2007 *
2008 * @adev: amdgpu_device pointer
2009 * @bo: amdgpu buffer object
2010 * @evicted: is the BO evicted
2011 *
2012 * Mark @bo as invalid.
2013 */
2014void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2015 struct amdgpu_bo *bo, bool evicted)
2016{
2017 struct amdgpu_vm_bo_base *bo_base;
2018
2019 /* shadow bo doesn't have bo base, its validation needs its parent */
2020 if (bo->parent && (amdgpu_bo_shadowed(bo->parent) == bo))
2021 bo = bo->parent;
2022
2023 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2024 struct amdgpu_vm *vm = bo_base->vm;
2025
2026 if (evicted && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
2027 amdgpu_vm_bo_evicted(bo_base);
2028 continue;
2029 }
2030
2031 if (bo_base->moved)
2032 continue;
2033 bo_base->moved = true;
2034
2035 if (bo->tbo.type == ttm_bo_type_kernel)
2036 amdgpu_vm_bo_relocated(bo_base);
2037 else if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
2038 amdgpu_vm_bo_moved(bo_base);
2039 else
2040 amdgpu_vm_bo_invalidated(bo_base);
2041 }
2042}
2043
2044/**
2045 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2046 *
2047 * @vm_size: VM size
2048 *
2049 * Returns:
2050 * VM page table as power of two
2051 */
2052static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2053{
2054 /* Total bits covered by PD + PTs */
2055 unsigned bits = ilog2(vm_size) + 18;
2056
2057 /* Make sure the PD is 4K in size up to 8GB address space.
2058 Above that split equal between PD and PTs */
2059 if (vm_size <= 8)
2060 return (bits - 9);
2061 else
2062 return ((bits + 3) / 2);
2063}
2064
2065/**
2066 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2067 *
2068 * @adev: amdgpu_device pointer
2069 * @min_vm_size: the minimum vm size in GB if it's set auto
2070 * @fragment_size_default: Default PTE fragment size
2071 * @max_level: max VMPT level
2072 * @max_bits: max address space size in bits
2073 *
2074 */
2075void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2076 uint32_t fragment_size_default, unsigned max_level,
2077 unsigned max_bits)
2078{
2079 unsigned int max_size = 1 << (max_bits - 30);
2080 unsigned int vm_size;
2081 uint64_t tmp;
2082
2083 /* adjust vm size first */
2084 if (amdgpu_vm_size != -1) {
2085 vm_size = amdgpu_vm_size;
2086 if (vm_size > max_size) {
2087 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2088 amdgpu_vm_size, max_size);
2089 vm_size = max_size;
2090 }
2091 } else {
2092 struct sysinfo si;
2093 unsigned int phys_ram_gb;
2094
2095 /* Optimal VM size depends on the amount of physical
2096 * RAM available. Underlying requirements and
2097 * assumptions:
2098 *
2099 * - Need to map system memory and VRAM from all GPUs
2100 * - VRAM from other GPUs not known here
2101 * - Assume VRAM <= system memory
2102 * - On GFX8 and older, VM space can be segmented for
2103 * different MTYPEs
2104 * - Need to allow room for fragmentation, guard pages etc.
2105 *
2106 * This adds up to a rough guess of system memory x3.
2107 * Round up to power of two to maximize the available
2108 * VM size with the given page table size.
2109 */
2110 si_meminfo(&si);
2111 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2112 (1 << 30) - 1) >> 30;
2113 vm_size = roundup_pow_of_two(
2114 min(max(phys_ram_gb * 3, min_vm_size), max_size));
2115 }
2116
2117 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2118
2119 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2120 if (amdgpu_vm_block_size != -1)
2121 tmp >>= amdgpu_vm_block_size - 9;
2122 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2123 adev->vm_manager.num_level = min_t(unsigned int, max_level, tmp);
2124 switch (adev->vm_manager.num_level) {
2125 case 3:
2126 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2127 break;
2128 case 2:
2129 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2130 break;
2131 case 1:
2132 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2133 break;
2134 default:
2135 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2136 }
2137 /* block size depends on vm size and hw setup*/
2138 if (amdgpu_vm_block_size != -1)
2139 adev->vm_manager.block_size =
2140 min((unsigned)amdgpu_vm_block_size, max_bits
2141 - AMDGPU_GPU_PAGE_SHIFT
2142 - 9 * adev->vm_manager.num_level);
2143 else if (adev->vm_manager.num_level > 1)
2144 adev->vm_manager.block_size = 9;
2145 else
2146 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2147
2148 if (amdgpu_vm_fragment_size == -1)
2149 adev->vm_manager.fragment_size = fragment_size_default;
2150 else
2151 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2152
2153 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2154 vm_size, adev->vm_manager.num_level + 1,
2155 adev->vm_manager.block_size,
2156 adev->vm_manager.fragment_size);
2157}
2158
2159/**
2160 * amdgpu_vm_wait_idle - wait for the VM to become idle
2161 *
2162 * @vm: VM object to wait for
2163 * @timeout: timeout to wait for VM to become idle
2164 */
2165long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2166{
2167 timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv,
2168 DMA_RESV_USAGE_BOOKKEEP,
2169 true, timeout);
2170 if (timeout <= 0)
2171 return timeout;
2172
2173 return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
2174}
2175
2176/**
2177 * amdgpu_vm_init - initialize a vm instance
2178 *
2179 * @adev: amdgpu_device pointer
2180 * @vm: requested vm
2181 * @xcp_id: GPU partition selection id
2182 *
2183 * Init @vm fields.
2184 *
2185 * Returns:
2186 * 0 for success, error for failure.
2187 */
2188int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2189 int32_t xcp_id)
2190{
2191 struct amdgpu_bo *root_bo;
2192 struct amdgpu_bo_vm *root;
2193 int r, i;
2194
2195 vm->va = RB_ROOT_CACHED;
2196 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2197 vm->reserved_vmid[i] = NULL;
2198 INIT_LIST_HEAD(&vm->evicted);
2199 INIT_LIST_HEAD(&vm->relocated);
2200 INIT_LIST_HEAD(&vm->moved);
2201 INIT_LIST_HEAD(&vm->idle);
2202 INIT_LIST_HEAD(&vm->invalidated);
2203 spin_lock_init(&vm->status_lock);
2204 INIT_LIST_HEAD(&vm->freed);
2205 INIT_LIST_HEAD(&vm->done);
2206 INIT_LIST_HEAD(&vm->pt_freed);
2207 INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);
2208 INIT_KFIFO(vm->faults);
2209
2210 r = amdgpu_vm_init_entities(adev, vm);
2211 if (r)
2212 return r;
2213
2214 vm->pte_support_ats = false;
2215 vm->is_compute_context = false;
2216
2217 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2218 AMDGPU_VM_USE_CPU_FOR_GFX);
2219
2220 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2221 vm->use_cpu_for_update ? "CPU" : "SDMA");
2222 WARN_ONCE((vm->use_cpu_for_update &&
2223 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2224 "CPU update of VM recommended only for large BAR system\n");
2225
2226 if (vm->use_cpu_for_update)
2227 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2228 else
2229 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2230
2231 vm->last_update = dma_fence_get_stub();
2232 vm->last_unlocked = dma_fence_get_stub();
2233 vm->last_tlb_flush = dma_fence_get_stub();
2234 vm->generation = 0;
2235
2236 mutex_init(&vm->eviction_lock);
2237 vm->evicting = false;
2238
2239 r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
2240 false, &root, xcp_id);
2241 if (r)
2242 goto error_free_delayed;
2243
2244 root_bo = amdgpu_bo_ref(&root->bo);
2245 r = amdgpu_bo_reserve(root_bo, true);
2246 if (r) {
2247 amdgpu_bo_unref(&root->shadow);
2248 amdgpu_bo_unref(&root_bo);
2249 goto error_free_delayed;
2250 }
2251
2252 amdgpu_vm_bo_base_init(&vm->root, vm, root_bo);
2253 r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1);
2254 if (r)
2255 goto error_free_root;
2256
2257 r = amdgpu_vm_pt_clear(adev, vm, root, false);
2258 if (r)
2259 goto error_free_root;
2260
2261 amdgpu_bo_unreserve(vm->root.bo);
2262 amdgpu_bo_unref(&root_bo);
2263
2264 return 0;
2265
2266error_free_root:
2267 amdgpu_vm_pt_free_root(adev, vm);
2268 amdgpu_bo_unreserve(vm->root.bo);
2269 amdgpu_bo_unref(&root_bo);
2270
2271error_free_delayed:
2272 dma_fence_put(vm->last_tlb_flush);
2273 dma_fence_put(vm->last_unlocked);
2274 amdgpu_vm_fini_entities(vm);
2275
2276 return r;
2277}
2278
2279/**
2280 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2281 *
2282 * @adev: amdgpu_device pointer
2283 * @vm: requested vm
2284 *
2285 * This only works on GFX VMs that don't have any BOs added and no
2286 * page tables allocated yet.
2287 *
2288 * Changes the following VM parameters:
2289 * - use_cpu_for_update
2290 * - pte_supports_ats
2291 *
2292 * Reinitializes the page directory to reflect the changed ATS
2293 * setting.
2294 *
2295 * Returns:
2296 * 0 for success, -errno for errors.
2297 */
2298int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2299{
2300 bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
2301 int r;
2302
2303 r = amdgpu_bo_reserve(vm->root.bo, true);
2304 if (r)
2305 return r;
2306
2307 /* Check if PD needs to be reinitialized and do it before
2308 * changing any other state, in case it fails.
2309 */
2310 if (pte_support_ats != vm->pte_support_ats) {
2311 /* Sanity checks */
2312 if (!amdgpu_vm_pt_is_root_clean(adev, vm)) {
2313 r = -EINVAL;
2314 goto unreserve_bo;
2315 }
2316
2317 vm->pte_support_ats = pte_support_ats;
2318 r = amdgpu_vm_pt_clear(adev, vm, to_amdgpu_bo_vm(vm->root.bo),
2319 false);
2320 if (r)
2321 goto unreserve_bo;
2322 }
2323
2324 /* Update VM state */
2325 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2326 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2327 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2328 vm->use_cpu_for_update ? "CPU" : "SDMA");
2329 WARN_ONCE((vm->use_cpu_for_update &&
2330 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2331 "CPU update of VM recommended only for large BAR system\n");
2332
2333 if (vm->use_cpu_for_update) {
2334 /* Sync with last SDMA update/clear before switching to CPU */
2335 r = amdgpu_bo_sync_wait(vm->root.bo,
2336 AMDGPU_FENCE_OWNER_UNDEFINED, true);
2337 if (r)
2338 goto unreserve_bo;
2339
2340 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2341 r = amdgpu_vm_pt_map_tables(adev, vm);
2342 if (r)
2343 goto unreserve_bo;
2344
2345 } else {
2346 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2347 }
2348
2349 dma_fence_put(vm->last_update);
2350 vm->last_update = dma_fence_get_stub();
2351 vm->is_compute_context = true;
2352
2353 /* Free the shadow bo for compute VM */
2354 amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.bo)->shadow);
2355
2356 goto unreserve_bo;
2357
2358unreserve_bo:
2359 amdgpu_bo_unreserve(vm->root.bo);
2360 return r;
2361}
2362
2363/**
2364 * amdgpu_vm_release_compute - release a compute vm
2365 * @adev: amdgpu_device pointer
2366 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
2367 *
2368 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
2369 * pasid from vm. Compute should stop use of vm after this call.
2370 */
2371void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2372{
2373 amdgpu_vm_set_pasid(adev, vm, 0);
2374 vm->is_compute_context = false;
2375}
2376
2377/**
2378 * amdgpu_vm_fini - tear down a vm instance
2379 *
2380 * @adev: amdgpu_device pointer
2381 * @vm: requested vm
2382 *
2383 * Tear down @vm.
2384 * Unbind the VM and remove all bos from the vm bo list
2385 */
2386void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2387{
2388 struct amdgpu_bo_va_mapping *mapping, *tmp;
2389 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
2390 struct amdgpu_bo *root;
2391 unsigned long flags;
2392 int i;
2393
2394 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
2395
2396 flush_work(&vm->pt_free_work);
2397
2398 root = amdgpu_bo_ref(vm->root.bo);
2399 amdgpu_bo_reserve(root, true);
2400 amdgpu_vm_set_pasid(adev, vm, 0);
2401 dma_fence_wait(vm->last_unlocked, false);
2402 dma_fence_put(vm->last_unlocked);
2403 dma_fence_wait(vm->last_tlb_flush, false);
2404 /* Make sure that all fence callbacks have completed */
2405 spin_lock_irqsave(vm->last_tlb_flush->lock, flags);
2406 spin_unlock_irqrestore(vm->last_tlb_flush->lock, flags);
2407 dma_fence_put(vm->last_tlb_flush);
2408
2409 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2410 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
2411 amdgpu_vm_prt_fini(adev, vm);
2412 prt_fini_needed = false;
2413 }
2414
2415 list_del(&mapping->list);
2416 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2417 }
2418
2419 amdgpu_vm_pt_free_root(adev, vm);
2420 amdgpu_bo_unreserve(root);
2421 amdgpu_bo_unref(&root);
2422 WARN_ON(vm->root.bo);
2423
2424 amdgpu_vm_fini_entities(vm);
2425
2426 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
2427 dev_err(adev->dev, "still active bo inside vm\n");
2428 }
2429 rbtree_postorder_for_each_entry_safe(mapping, tmp,
2430 &vm->va.rb_root, rb) {
2431 /* Don't remove the mapping here, we don't want to trigger a
2432 * rebalance and the tree is about to be destroyed anyway.
2433 */
2434 list_del(&mapping->list);
2435 kfree(mapping);
2436 }
2437
2438 dma_fence_put(vm->last_update);
2439
2440 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) {
2441 if (vm->reserved_vmid[i]) {
2442 amdgpu_vmid_free_reserved(adev, i);
2443 vm->reserved_vmid[i] = false;
2444 }
2445 }
2446
2447}
2448
2449/**
2450 * amdgpu_vm_manager_init - init the VM manager
2451 *
2452 * @adev: amdgpu_device pointer
2453 *
2454 * Initialize the VM manager structures
2455 */
2456void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2457{
2458 unsigned i;
2459
2460 /* Concurrent flushes are only possible starting with Vega10 and
2461 * are broken on Navi10 and Navi14.
2462 */
2463 adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
2464 adev->asic_type == CHIP_NAVI10 ||
2465 adev->asic_type == CHIP_NAVI14);
2466 amdgpu_vmid_mgr_init(adev);
2467
2468 adev->vm_manager.fence_context =
2469 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2470 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2471 adev->vm_manager.seqno[i] = 0;
2472
2473 spin_lock_init(&adev->vm_manager.prt_lock);
2474 atomic_set(&adev->vm_manager.num_prt_users, 0);
2475
2476 /* If not overridden by the user, by default, only in large BAR systems
2477 * Compute VM tables will be updated by CPU
2478 */
2479#ifdef CONFIG_X86_64
2480 if (amdgpu_vm_update_mode == -1) {
2481 /* For asic with VF MMIO access protection
2482 * avoid using CPU for VM table updates
2483 */
2484 if (amdgpu_gmc_vram_full_visible(&adev->gmc) &&
2485 !amdgpu_sriov_vf_mmio_access_protection(adev))
2486 adev->vm_manager.vm_update_mode =
2487 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
2488 else
2489 adev->vm_manager.vm_update_mode = 0;
2490 } else
2491 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
2492#else
2493 adev->vm_manager.vm_update_mode = 0;
2494#endif
2495
2496 xa_init_flags(&adev->vm_manager.pasids, XA_FLAGS_LOCK_IRQ);
2497}
2498
2499/**
2500 * amdgpu_vm_manager_fini - cleanup VM manager
2501 *
2502 * @adev: amdgpu_device pointer
2503 *
2504 * Cleanup the VM manager and free resources.
2505 */
2506void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2507{
2508 WARN_ON(!xa_empty(&adev->vm_manager.pasids));
2509 xa_destroy(&adev->vm_manager.pasids);
2510
2511 amdgpu_vmid_mgr_fini(adev);
2512}
2513
2514/**
2515 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
2516 *
2517 * @dev: drm device pointer
2518 * @data: drm_amdgpu_vm
2519 * @filp: drm file pointer
2520 *
2521 * Returns:
2522 * 0 for success, -errno for errors.
2523 */
2524int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
2525{
2526 union drm_amdgpu_vm *args = data;
2527 struct amdgpu_device *adev = drm_to_adev(dev);
2528 struct amdgpu_fpriv *fpriv = filp->driver_priv;
2529
2530 /* No valid flags defined yet */
2531 if (args->in.flags)
2532 return -EINVAL;
2533
2534 switch (args->in.op) {
2535 case AMDGPU_VM_OP_RESERVE_VMID:
2536 /* We only have requirement to reserve vmid from gfxhub */
2537 if (!fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {
2538 amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0));
2539 fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = true;
2540 }
2541
2542 break;
2543 case AMDGPU_VM_OP_UNRESERVE_VMID:
2544 if (fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {
2545 amdgpu_vmid_free_reserved(adev, AMDGPU_GFXHUB(0));
2546 fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = false;
2547 }
2548 break;
2549 default:
2550 return -EINVAL;
2551 }
2552
2553 return 0;
2554}
2555
2556/**
2557 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
2558 *
2559 * @adev: drm device pointer
2560 * @pasid: PASID identifier for VM
2561 * @task_info: task_info to fill.
2562 */
2563void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid,
2564 struct amdgpu_task_info *task_info)
2565{
2566 struct amdgpu_vm *vm;
2567 unsigned long flags;
2568
2569 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
2570
2571 vm = xa_load(&adev->vm_manager.pasids, pasid);
2572 if (vm)
2573 *task_info = vm->task_info;
2574
2575 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
2576}
2577
2578/**
2579 * amdgpu_vm_set_task_info - Sets VMs task info.
2580 *
2581 * @vm: vm for which to set the info
2582 */
2583void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
2584{
2585 if (vm->task_info.pid)
2586 return;
2587
2588 vm->task_info.pid = current->pid;
2589 get_task_comm(vm->task_info.task_name, current);
2590
2591 if (current->group_leader->mm != current->mm)
2592 return;
2593
2594 vm->task_info.tgid = current->group_leader->pid;
2595 get_task_comm(vm->task_info.process_name, current->group_leader);
2596}
2597
2598/**
2599 * amdgpu_vm_handle_fault - graceful handling of VM faults.
2600 * @adev: amdgpu device pointer
2601 * @pasid: PASID of the VM
2602 * @vmid: VMID, only used for GFX 9.4.3.
2603 * @node_id: Node_id received in IH cookie. Only applicable for
2604 * GFX 9.4.3.
2605 * @addr: Address of the fault
2606 * @write_fault: true is write fault, false is read fault
2607 *
2608 * Try to gracefully handle a VM fault. Return true if the fault was handled and
2609 * shouldn't be reported any more.
2610 */
2611bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
2612 u32 vmid, u32 node_id, uint64_t addr,
2613 bool write_fault)
2614{
2615 bool is_compute_context = false;
2616 struct amdgpu_bo *root;
2617 unsigned long irqflags;
2618 uint64_t value, flags;
2619 struct amdgpu_vm *vm;
2620 int r;
2621
2622 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2623 vm = xa_load(&adev->vm_manager.pasids, pasid);
2624 if (vm) {
2625 root = amdgpu_bo_ref(vm->root.bo);
2626 is_compute_context = vm->is_compute_context;
2627 } else {
2628 root = NULL;
2629 }
2630 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2631
2632 if (!root)
2633 return false;
2634
2635 addr /= AMDGPU_GPU_PAGE_SIZE;
2636
2637 if (is_compute_context && !svm_range_restore_pages(adev, pasid, vmid,
2638 node_id, addr, write_fault)) {
2639 amdgpu_bo_unref(&root);
2640 return true;
2641 }
2642
2643 r = amdgpu_bo_reserve(root, true);
2644 if (r)
2645 goto error_unref;
2646
2647 /* Double check that the VM still exists */
2648 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2649 vm = xa_load(&adev->vm_manager.pasids, pasid);
2650 if (vm && vm->root.bo != root)
2651 vm = NULL;
2652 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2653 if (!vm)
2654 goto error_unlock;
2655
2656 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
2657 AMDGPU_PTE_SYSTEM;
2658
2659 if (is_compute_context) {
2660 /* Intentionally setting invalid PTE flag
2661 * combination to force a no-retry-fault
2662 */
2663 flags = AMDGPU_VM_NORETRY_FLAGS;
2664 value = 0;
2665 } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
2666 /* Redirect the access to the dummy page */
2667 value = adev->dummy_page_addr;
2668 flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
2669 AMDGPU_PTE_WRITEABLE;
2670
2671 } else {
2672 /* Let the hw retry silently on the PTE */
2673 value = 0;
2674 }
2675
2676 r = dma_resv_reserve_fences(root->tbo.base.resv, 1);
2677 if (r) {
2678 pr_debug("failed %d to reserve fence slot\n", r);
2679 goto error_unlock;
2680 }
2681
2682 r = amdgpu_vm_update_range(adev, vm, true, false, false, false,
2683 NULL, addr, addr, flags, value, 0, NULL, NULL, NULL);
2684 if (r)
2685 goto error_unlock;
2686
2687 r = amdgpu_vm_update_pdes(adev, vm, true);
2688
2689error_unlock:
2690 amdgpu_bo_unreserve(root);
2691 if (r < 0)
2692 DRM_ERROR("Can't handle page fault (%d)\n", r);
2693
2694error_unref:
2695 amdgpu_bo_unref(&root);
2696
2697 return false;
2698}
2699
2700#if defined(CONFIG_DEBUG_FS)
2701/**
2702 * amdgpu_debugfs_vm_bo_info - print BO info for the VM
2703 *
2704 * @vm: Requested VM for printing BO info
2705 * @m: debugfs file
2706 *
2707 * Print BO information in debugfs file for the VM
2708 */
2709void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)
2710{
2711 struct amdgpu_bo_va *bo_va, *tmp;
2712 u64 total_idle = 0;
2713 u64 total_evicted = 0;
2714 u64 total_relocated = 0;
2715 u64 total_moved = 0;
2716 u64 total_invalidated = 0;
2717 u64 total_done = 0;
2718 unsigned int total_idle_objs = 0;
2719 unsigned int total_evicted_objs = 0;
2720 unsigned int total_relocated_objs = 0;
2721 unsigned int total_moved_objs = 0;
2722 unsigned int total_invalidated_objs = 0;
2723 unsigned int total_done_objs = 0;
2724 unsigned int id = 0;
2725
2726 spin_lock(&vm->status_lock);
2727 seq_puts(m, "\tIdle BOs:\n");
2728 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
2729 if (!bo_va->base.bo)
2730 continue;
2731 total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2732 }
2733 total_idle_objs = id;
2734 id = 0;
2735
2736 seq_puts(m, "\tEvicted BOs:\n");
2737 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
2738 if (!bo_va->base.bo)
2739 continue;
2740 total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2741 }
2742 total_evicted_objs = id;
2743 id = 0;
2744
2745 seq_puts(m, "\tRelocated BOs:\n");
2746 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
2747 if (!bo_va->base.bo)
2748 continue;
2749 total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2750 }
2751 total_relocated_objs = id;
2752 id = 0;
2753
2754 seq_puts(m, "\tMoved BOs:\n");
2755 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2756 if (!bo_va->base.bo)
2757 continue;
2758 total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2759 }
2760 total_moved_objs = id;
2761 id = 0;
2762
2763 seq_puts(m, "\tInvalidated BOs:\n");
2764 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
2765 if (!bo_va->base.bo)
2766 continue;
2767 total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2768 }
2769 total_invalidated_objs = id;
2770 id = 0;
2771
2772 seq_puts(m, "\tDone BOs:\n");
2773 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
2774 if (!bo_va->base.bo)
2775 continue;
2776 total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2777 }
2778 spin_unlock(&vm->status_lock);
2779 total_done_objs = id;
2780
2781 seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle,
2782 total_idle_objs);
2783 seq_printf(m, "\tTotal evicted size: %12lld\tobjs:\t%d\n", total_evicted,
2784 total_evicted_objs);
2785 seq_printf(m, "\tTotal relocated size: %12lld\tobjs:\t%d\n", total_relocated,
2786 total_relocated_objs);
2787 seq_printf(m, "\tTotal moved size: %12lld\tobjs:\t%d\n", total_moved,
2788 total_moved_objs);
2789 seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated,
2790 total_invalidated_objs);
2791 seq_printf(m, "\tTotal done size: %12lld\tobjs:\t%d\n", total_done,
2792 total_done_objs);
2793}
2794#endif
2795
2796/**
2797 * amdgpu_vm_update_fault_cache - update cached fault into.
2798 * @adev: amdgpu device pointer
2799 * @pasid: PASID of the VM
2800 * @addr: Address of the fault
2801 * @status: GPUVM fault status register
2802 * @vmhub: which vmhub got the fault
2803 *
2804 * Cache the fault info for later use by userspace in debugging.
2805 */
2806void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev,
2807 unsigned int pasid,
2808 uint64_t addr,
2809 uint32_t status,
2810 unsigned int vmhub)
2811{
2812 struct amdgpu_vm *vm;
2813 unsigned long flags;
2814
2815 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
2816
2817 vm = xa_load(&adev->vm_manager.pasids, pasid);
2818 /* Don't update the fault cache if status is 0. In the multiple
2819 * fault case, subsequent faults will return a 0 status which is
2820 * useless for userspace and replaces the useful fault status, so
2821 * only update if status is non-0.
2822 */
2823 if (vm && status) {
2824 vm->fault_info.addr = addr;
2825 vm->fault_info.status = status;
2826 if (AMDGPU_IS_GFXHUB(vmhub)) {
2827 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_GFX;
2828 vm->fault_info.vmhub |=
2829 (vmhub - AMDGPU_GFXHUB_START) << AMDGPU_VMHUB_IDX_SHIFT;
2830 } else if (AMDGPU_IS_MMHUB0(vmhub)) {
2831 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_MM0;
2832 vm->fault_info.vmhub |=
2833 (vmhub - AMDGPU_MMHUB0_START) << AMDGPU_VMHUB_IDX_SHIFT;
2834 } else if (AMDGPU_IS_MMHUB1(vmhub)) {
2835 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_MM1;
2836 vm->fault_info.vmhub |=
2837 (vmhub - AMDGPU_MMHUB1_START) << AMDGPU_VMHUB_IDX_SHIFT;
2838 } else {
2839 WARN_ONCE(1, "Invalid vmhub %u\n", vmhub);
2840 }
2841 }
2842 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
2843}
2844