Loading...
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/power_supply.h>
29#include <linux/kthread.h>
30#include <linux/module.h>
31#include <linux/console.h>
32#include <linux/slab.h>
33#include <linux/iommu.h>
34#include <linux/pci.h>
35#include <linux/pci-p2pdma.h>
36#include <linux/apple-gmux.h>
37
38#include <drm/drm_aperture.h>
39#include <drm/drm_atomic_helper.h>
40#include <drm/drm_crtc_helper.h>
41#include <drm/drm_fb_helper.h>
42#include <drm/drm_probe_helper.h>
43#include <drm/amdgpu_drm.h>
44#include <linux/device.h>
45#include <linux/vgaarb.h>
46#include <linux/vga_switcheroo.h>
47#include <linux/efi.h>
48#include "amdgpu.h"
49#include "amdgpu_trace.h"
50#include "amdgpu_i2c.h"
51#include "atom.h"
52#include "amdgpu_atombios.h"
53#include "amdgpu_atomfirmware.h"
54#include "amd_pcie.h"
55#ifdef CONFIG_DRM_AMDGPU_SI
56#include "si.h"
57#endif
58#ifdef CONFIG_DRM_AMDGPU_CIK
59#include "cik.h"
60#endif
61#include "vi.h"
62#include "soc15.h"
63#include "nv.h"
64#include "bif/bif_4_1_d.h"
65#include <linux/firmware.h>
66#include "amdgpu_vf_error.h"
67
68#include "amdgpu_amdkfd.h"
69#include "amdgpu_pm.h"
70
71#include "amdgpu_xgmi.h"
72#include "amdgpu_ras.h"
73#include "amdgpu_pmu.h"
74#include "amdgpu_fru_eeprom.h"
75#include "amdgpu_reset.h"
76#include "amdgpu_virt.h"
77
78#include <linux/suspend.h>
79#include <drm/task_barrier.h>
80#include <linux/pm_runtime.h>
81
82#include <drm/drm_drv.h>
83
84#if IS_ENABLED(CONFIG_X86)
85#include <asm/intel-family.h>
86#endif
87
88MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
89MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
90MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
91MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
92MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
93MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
94MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
95
96#define AMDGPU_RESUME_MS 2000
97#define AMDGPU_MAX_RETRY_LIMIT 2
98#define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL)
99#define AMDGPU_PCIE_INDEX_FALLBACK (0x38 >> 2)
100#define AMDGPU_PCIE_INDEX_HI_FALLBACK (0x44 >> 2)
101#define AMDGPU_PCIE_DATA_FALLBACK (0x3C >> 2)
102
103static const struct drm_driver amdgpu_kms_driver;
104
105const char *amdgpu_asic_name[] = {
106 "TAHITI",
107 "PITCAIRN",
108 "VERDE",
109 "OLAND",
110 "HAINAN",
111 "BONAIRE",
112 "KAVERI",
113 "KABINI",
114 "HAWAII",
115 "MULLINS",
116 "TOPAZ",
117 "TONGA",
118 "FIJI",
119 "CARRIZO",
120 "STONEY",
121 "POLARIS10",
122 "POLARIS11",
123 "POLARIS12",
124 "VEGAM",
125 "VEGA10",
126 "VEGA12",
127 "VEGA20",
128 "RAVEN",
129 "ARCTURUS",
130 "RENOIR",
131 "ALDEBARAN",
132 "NAVI10",
133 "CYAN_SKILLFISH",
134 "NAVI14",
135 "NAVI12",
136 "SIENNA_CICHLID",
137 "NAVY_FLOUNDER",
138 "VANGOGH",
139 "DIMGREY_CAVEFISH",
140 "BEIGE_GOBY",
141 "YELLOW_CARP",
142 "IP DISCOVERY",
143 "LAST",
144};
145
146/**
147 * DOC: pcie_replay_count
148 *
149 * The amdgpu driver provides a sysfs API for reporting the total number
150 * of PCIe replays (NAKs)
151 * The file pcie_replay_count is used for this and returns the total
152 * number of replays as a sum of the NAKs generated and NAKs received
153 */
154
155static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
156 struct device_attribute *attr, char *buf)
157{
158 struct drm_device *ddev = dev_get_drvdata(dev);
159 struct amdgpu_device *adev = drm_to_adev(ddev);
160 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
161
162 return sysfs_emit(buf, "%llu\n", cnt);
163}
164
165static DEVICE_ATTR(pcie_replay_count, 0444,
166 amdgpu_device_get_pcie_replay_count, NULL);
167
168static ssize_t amdgpu_sysfs_reg_state_get(struct file *f, struct kobject *kobj,
169 struct bin_attribute *attr, char *buf,
170 loff_t ppos, size_t count)
171{
172 struct device *dev = kobj_to_dev(kobj);
173 struct drm_device *ddev = dev_get_drvdata(dev);
174 struct amdgpu_device *adev = drm_to_adev(ddev);
175 ssize_t bytes_read;
176
177 switch (ppos) {
178 case AMDGPU_SYS_REG_STATE_XGMI:
179 bytes_read = amdgpu_asic_get_reg_state(
180 adev, AMDGPU_REG_STATE_TYPE_XGMI, buf, count);
181 break;
182 case AMDGPU_SYS_REG_STATE_WAFL:
183 bytes_read = amdgpu_asic_get_reg_state(
184 adev, AMDGPU_REG_STATE_TYPE_WAFL, buf, count);
185 break;
186 case AMDGPU_SYS_REG_STATE_PCIE:
187 bytes_read = amdgpu_asic_get_reg_state(
188 adev, AMDGPU_REG_STATE_TYPE_PCIE, buf, count);
189 break;
190 case AMDGPU_SYS_REG_STATE_USR:
191 bytes_read = amdgpu_asic_get_reg_state(
192 adev, AMDGPU_REG_STATE_TYPE_USR, buf, count);
193 break;
194 case AMDGPU_SYS_REG_STATE_USR_1:
195 bytes_read = amdgpu_asic_get_reg_state(
196 adev, AMDGPU_REG_STATE_TYPE_USR_1, buf, count);
197 break;
198 default:
199 return -EINVAL;
200 }
201
202 return bytes_read;
203}
204
205BIN_ATTR(reg_state, 0444, amdgpu_sysfs_reg_state_get, NULL,
206 AMDGPU_SYS_REG_STATE_END);
207
208int amdgpu_reg_state_sysfs_init(struct amdgpu_device *adev)
209{
210 int ret;
211
212 if (!amdgpu_asic_get_reg_state_supported(adev))
213 return 0;
214
215 ret = sysfs_create_bin_file(&adev->dev->kobj, &bin_attr_reg_state);
216
217 return ret;
218}
219
220void amdgpu_reg_state_sysfs_fini(struct amdgpu_device *adev)
221{
222 if (!amdgpu_asic_get_reg_state_supported(adev))
223 return;
224 sysfs_remove_bin_file(&adev->dev->kobj, &bin_attr_reg_state);
225}
226
227/**
228 * DOC: board_info
229 *
230 * The amdgpu driver provides a sysfs API for giving board related information.
231 * It provides the form factor information in the format
232 *
233 * type : form factor
234 *
235 * Possible form factor values
236 *
237 * - "cem" - PCIE CEM card
238 * - "oam" - Open Compute Accelerator Module
239 * - "unknown" - Not known
240 *
241 */
242
243static ssize_t amdgpu_device_get_board_info(struct device *dev,
244 struct device_attribute *attr,
245 char *buf)
246{
247 struct drm_device *ddev = dev_get_drvdata(dev);
248 struct amdgpu_device *adev = drm_to_adev(ddev);
249 enum amdgpu_pkg_type pkg_type = AMDGPU_PKG_TYPE_CEM;
250 const char *pkg;
251
252 if (adev->smuio.funcs && adev->smuio.funcs->get_pkg_type)
253 pkg_type = adev->smuio.funcs->get_pkg_type(adev);
254
255 switch (pkg_type) {
256 case AMDGPU_PKG_TYPE_CEM:
257 pkg = "cem";
258 break;
259 case AMDGPU_PKG_TYPE_OAM:
260 pkg = "oam";
261 break;
262 default:
263 pkg = "unknown";
264 break;
265 }
266
267 return sysfs_emit(buf, "%s : %s\n", "type", pkg);
268}
269
270static DEVICE_ATTR(board_info, 0444, amdgpu_device_get_board_info, NULL);
271
272static struct attribute *amdgpu_board_attrs[] = {
273 &dev_attr_board_info.attr,
274 NULL,
275};
276
277static umode_t amdgpu_board_attrs_is_visible(struct kobject *kobj,
278 struct attribute *attr, int n)
279{
280 struct device *dev = kobj_to_dev(kobj);
281 struct drm_device *ddev = dev_get_drvdata(dev);
282 struct amdgpu_device *adev = drm_to_adev(ddev);
283
284 if (adev->flags & AMD_IS_APU)
285 return 0;
286
287 return attr->mode;
288}
289
290static const struct attribute_group amdgpu_board_attrs_group = {
291 .attrs = amdgpu_board_attrs,
292 .is_visible = amdgpu_board_attrs_is_visible
293};
294
295static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
296
297
298/**
299 * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control
300 *
301 * @dev: drm_device pointer
302 *
303 * Returns true if the device is a dGPU with ATPX power control,
304 * otherwise return false.
305 */
306bool amdgpu_device_supports_px(struct drm_device *dev)
307{
308 struct amdgpu_device *adev = drm_to_adev(dev);
309
310 if ((adev->flags & AMD_IS_PX) && !amdgpu_is_atpx_hybrid())
311 return true;
312 return false;
313}
314
315/**
316 * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources
317 *
318 * @dev: drm_device pointer
319 *
320 * Returns true if the device is a dGPU with ACPI power control,
321 * otherwise return false.
322 */
323bool amdgpu_device_supports_boco(struct drm_device *dev)
324{
325 struct amdgpu_device *adev = drm_to_adev(dev);
326
327 if (adev->has_pr3 ||
328 ((adev->flags & AMD_IS_PX) && amdgpu_is_atpx_hybrid()))
329 return true;
330 return false;
331}
332
333/**
334 * amdgpu_device_supports_baco - Does the device support BACO
335 *
336 * @dev: drm_device pointer
337 *
338 * Returns true if the device supporte BACO,
339 * otherwise return false.
340 */
341bool amdgpu_device_supports_baco(struct drm_device *dev)
342{
343 struct amdgpu_device *adev = drm_to_adev(dev);
344
345 return amdgpu_asic_supports_baco(adev);
346}
347
348/**
349 * amdgpu_device_supports_smart_shift - Is the device dGPU with
350 * smart shift support
351 *
352 * @dev: drm_device pointer
353 *
354 * Returns true if the device is a dGPU with Smart Shift support,
355 * otherwise returns false.
356 */
357bool amdgpu_device_supports_smart_shift(struct drm_device *dev)
358{
359 return (amdgpu_device_supports_boco(dev) &&
360 amdgpu_acpi_is_power_shift_control_supported());
361}
362
363/*
364 * VRAM access helper functions
365 */
366
367/**
368 * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA
369 *
370 * @adev: amdgpu_device pointer
371 * @pos: offset of the buffer in vram
372 * @buf: virtual address of the buffer in system memory
373 * @size: read/write size, sizeof(@buf) must > @size
374 * @write: true - write to vram, otherwise - read from vram
375 */
376void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
377 void *buf, size_t size, bool write)
378{
379 unsigned long flags;
380 uint32_t hi = ~0, tmp = 0;
381 uint32_t *data = buf;
382 uint64_t last;
383 int idx;
384
385 if (!drm_dev_enter(adev_to_drm(adev), &idx))
386 return;
387
388 BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4));
389
390 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
391 for (last = pos + size; pos < last; pos += 4) {
392 tmp = pos >> 31;
393
394 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
395 if (tmp != hi) {
396 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
397 hi = tmp;
398 }
399 if (write)
400 WREG32_NO_KIQ(mmMM_DATA, *data++);
401 else
402 *data++ = RREG32_NO_KIQ(mmMM_DATA);
403 }
404
405 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
406 drm_dev_exit(idx);
407}
408
409/**
410 * amdgpu_device_aper_access - access vram by vram aperature
411 *
412 * @adev: amdgpu_device pointer
413 * @pos: offset of the buffer in vram
414 * @buf: virtual address of the buffer in system memory
415 * @size: read/write size, sizeof(@buf) must > @size
416 * @write: true - write to vram, otherwise - read from vram
417 *
418 * The return value means how many bytes have been transferred.
419 */
420size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
421 void *buf, size_t size, bool write)
422{
423#ifdef CONFIG_64BIT
424 void __iomem *addr;
425 size_t count = 0;
426 uint64_t last;
427
428 if (!adev->mman.aper_base_kaddr)
429 return 0;
430
431 last = min(pos + size, adev->gmc.visible_vram_size);
432 if (last > pos) {
433 addr = adev->mman.aper_base_kaddr + pos;
434 count = last - pos;
435
436 if (write) {
437 memcpy_toio(addr, buf, count);
438 /* Make sure HDP write cache flush happens without any reordering
439 * after the system memory contents are sent over PCIe device
440 */
441 mb();
442 amdgpu_device_flush_hdp(adev, NULL);
443 } else {
444 amdgpu_device_invalidate_hdp(adev, NULL);
445 /* Make sure HDP read cache is invalidated before issuing a read
446 * to the PCIe device
447 */
448 mb();
449 memcpy_fromio(buf, addr, count);
450 }
451
452 }
453
454 return count;
455#else
456 return 0;
457#endif
458}
459
460/**
461 * amdgpu_device_vram_access - read/write a buffer in vram
462 *
463 * @adev: amdgpu_device pointer
464 * @pos: offset of the buffer in vram
465 * @buf: virtual address of the buffer in system memory
466 * @size: read/write size, sizeof(@buf) must > @size
467 * @write: true - write to vram, otherwise - read from vram
468 */
469void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
470 void *buf, size_t size, bool write)
471{
472 size_t count;
473
474 /* try to using vram apreature to access vram first */
475 count = amdgpu_device_aper_access(adev, pos, buf, size, write);
476 size -= count;
477 if (size) {
478 /* using MM to access rest vram */
479 pos += count;
480 buf += count;
481 amdgpu_device_mm_access(adev, pos, buf, size, write);
482 }
483}
484
485/*
486 * register access helper functions.
487 */
488
489/* Check if hw access should be skipped because of hotplug or device error */
490bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev)
491{
492 if (adev->no_hw_access)
493 return true;
494
495#ifdef CONFIG_LOCKDEP
496 /*
497 * This is a bit complicated to understand, so worth a comment. What we assert
498 * here is that the GPU reset is not running on another thread in parallel.
499 *
500 * For this we trylock the read side of the reset semaphore, if that succeeds
501 * we know that the reset is not running in paralell.
502 *
503 * If the trylock fails we assert that we are either already holding the read
504 * side of the lock or are the reset thread itself and hold the write side of
505 * the lock.
506 */
507 if (in_task()) {
508 if (down_read_trylock(&adev->reset_domain->sem))
509 up_read(&adev->reset_domain->sem);
510 else
511 lockdep_assert_held(&adev->reset_domain->sem);
512 }
513#endif
514 return false;
515}
516
517/**
518 * amdgpu_device_rreg - read a memory mapped IO or indirect register
519 *
520 * @adev: amdgpu_device pointer
521 * @reg: dword aligned register offset
522 * @acc_flags: access flags which require special behavior
523 *
524 * Returns the 32 bit value from the offset specified.
525 */
526uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
527 uint32_t reg, uint32_t acc_flags)
528{
529 uint32_t ret;
530
531 if (amdgpu_device_skip_hw_access(adev))
532 return 0;
533
534 if ((reg * 4) < adev->rmmio_size) {
535 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
536 amdgpu_sriov_runtime(adev) &&
537 down_read_trylock(&adev->reset_domain->sem)) {
538 ret = amdgpu_kiq_rreg(adev, reg, 0);
539 up_read(&adev->reset_domain->sem);
540 } else {
541 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
542 }
543 } else {
544 ret = adev->pcie_rreg(adev, reg * 4);
545 }
546
547 trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
548
549 return ret;
550}
551
552/*
553 * MMIO register read with bytes helper functions
554 * @offset:bytes offset from MMIO start
555 */
556
557/**
558 * amdgpu_mm_rreg8 - read a memory mapped IO register
559 *
560 * @adev: amdgpu_device pointer
561 * @offset: byte aligned register offset
562 *
563 * Returns the 8 bit value from the offset specified.
564 */
565uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)
566{
567 if (amdgpu_device_skip_hw_access(adev))
568 return 0;
569
570 if (offset < adev->rmmio_size)
571 return (readb(adev->rmmio + offset));
572 BUG();
573}
574
575
576/**
577 * amdgpu_device_xcc_rreg - read a memory mapped IO or indirect register with specific XCC
578 *
579 * @adev: amdgpu_device pointer
580 * @reg: dword aligned register offset
581 * @acc_flags: access flags which require special behavior
582 * @xcc_id: xcc accelerated compute core id
583 *
584 * Returns the 32 bit value from the offset specified.
585 */
586uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,
587 uint32_t reg, uint32_t acc_flags,
588 uint32_t xcc_id)
589{
590 uint32_t ret, rlcg_flag;
591
592 if (amdgpu_device_skip_hw_access(adev))
593 return 0;
594
595 if ((reg * 4) < adev->rmmio_size) {
596 if (amdgpu_sriov_vf(adev) &&
597 !amdgpu_sriov_runtime(adev) &&
598 adev->gfx.rlc.rlcg_reg_access_supported &&
599 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags,
600 GC_HWIP, false,
601 &rlcg_flag)) {
602 ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, xcc_id);
603 } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
604 amdgpu_sriov_runtime(adev) &&
605 down_read_trylock(&adev->reset_domain->sem)) {
606 ret = amdgpu_kiq_rreg(adev, reg, xcc_id);
607 up_read(&adev->reset_domain->sem);
608 } else {
609 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
610 }
611 } else {
612 ret = adev->pcie_rreg(adev, reg * 4);
613 }
614
615 return ret;
616}
617
618/*
619 * MMIO register write with bytes helper functions
620 * @offset:bytes offset from MMIO start
621 * @value: the value want to be written to the register
622 */
623
624/**
625 * amdgpu_mm_wreg8 - read a memory mapped IO register
626 *
627 * @adev: amdgpu_device pointer
628 * @offset: byte aligned register offset
629 * @value: 8 bit value to write
630 *
631 * Writes the value specified to the offset specified.
632 */
633void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
634{
635 if (amdgpu_device_skip_hw_access(adev))
636 return;
637
638 if (offset < adev->rmmio_size)
639 writeb(value, adev->rmmio + offset);
640 else
641 BUG();
642}
643
644/**
645 * amdgpu_device_wreg - write to a memory mapped IO or indirect register
646 *
647 * @adev: amdgpu_device pointer
648 * @reg: dword aligned register offset
649 * @v: 32 bit value to write to the register
650 * @acc_flags: access flags which require special behavior
651 *
652 * Writes the value specified to the offset specified.
653 */
654void amdgpu_device_wreg(struct amdgpu_device *adev,
655 uint32_t reg, uint32_t v,
656 uint32_t acc_flags)
657{
658 if (amdgpu_device_skip_hw_access(adev))
659 return;
660
661 if ((reg * 4) < adev->rmmio_size) {
662 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
663 amdgpu_sriov_runtime(adev) &&
664 down_read_trylock(&adev->reset_domain->sem)) {
665 amdgpu_kiq_wreg(adev, reg, v, 0);
666 up_read(&adev->reset_domain->sem);
667 } else {
668 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
669 }
670 } else {
671 adev->pcie_wreg(adev, reg * 4, v);
672 }
673
674 trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
675}
676
677/**
678 * amdgpu_mm_wreg_mmio_rlc - write register either with direct/indirect mmio or with RLC path if in range
679 *
680 * @adev: amdgpu_device pointer
681 * @reg: mmio/rlc register
682 * @v: value to write
683 * @xcc_id: xcc accelerated compute core id
684 *
685 * this function is invoked only for the debugfs register access
686 */
687void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
688 uint32_t reg, uint32_t v,
689 uint32_t xcc_id)
690{
691 if (amdgpu_device_skip_hw_access(adev))
692 return;
693
694 if (amdgpu_sriov_fullaccess(adev) &&
695 adev->gfx.rlc.funcs &&
696 adev->gfx.rlc.funcs->is_rlcg_access_range) {
697 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
698 return amdgpu_sriov_wreg(adev, reg, v, 0, 0, xcc_id);
699 } else if ((reg * 4) >= adev->rmmio_size) {
700 adev->pcie_wreg(adev, reg * 4, v);
701 } else {
702 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
703 }
704}
705
706/**
707 * amdgpu_device_xcc_wreg - write to a memory mapped IO or indirect register with specific XCC
708 *
709 * @adev: amdgpu_device pointer
710 * @reg: dword aligned register offset
711 * @v: 32 bit value to write to the register
712 * @acc_flags: access flags which require special behavior
713 * @xcc_id: xcc accelerated compute core id
714 *
715 * Writes the value specified to the offset specified.
716 */
717void amdgpu_device_xcc_wreg(struct amdgpu_device *adev,
718 uint32_t reg, uint32_t v,
719 uint32_t acc_flags, uint32_t xcc_id)
720{
721 uint32_t rlcg_flag;
722
723 if (amdgpu_device_skip_hw_access(adev))
724 return;
725
726 if ((reg * 4) < adev->rmmio_size) {
727 if (amdgpu_sriov_vf(adev) &&
728 !amdgpu_sriov_runtime(adev) &&
729 adev->gfx.rlc.rlcg_reg_access_supported &&
730 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags,
731 GC_HWIP, true,
732 &rlcg_flag)) {
733 amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, xcc_id);
734 } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
735 amdgpu_sriov_runtime(adev) &&
736 down_read_trylock(&adev->reset_domain->sem)) {
737 amdgpu_kiq_wreg(adev, reg, v, xcc_id);
738 up_read(&adev->reset_domain->sem);
739 } else {
740 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
741 }
742 } else {
743 adev->pcie_wreg(adev, reg * 4, v);
744 }
745}
746
747/**
748 * amdgpu_device_indirect_rreg - read an indirect register
749 *
750 * @adev: amdgpu_device pointer
751 * @reg_addr: indirect register address to read from
752 *
753 * Returns the value of indirect register @reg_addr
754 */
755u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
756 u32 reg_addr)
757{
758 unsigned long flags, pcie_index, pcie_data;
759 void __iomem *pcie_index_offset;
760 void __iomem *pcie_data_offset;
761 u32 r;
762
763 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
764 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
765
766 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
767 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
768 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
769
770 writel(reg_addr, pcie_index_offset);
771 readl(pcie_index_offset);
772 r = readl(pcie_data_offset);
773 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
774
775 return r;
776}
777
778u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
779 u64 reg_addr)
780{
781 unsigned long flags, pcie_index, pcie_index_hi, pcie_data;
782 u32 r;
783 void __iomem *pcie_index_offset;
784 void __iomem *pcie_index_hi_offset;
785 void __iomem *pcie_data_offset;
786
787 if (unlikely(!adev->nbio.funcs)) {
788 pcie_index = AMDGPU_PCIE_INDEX_FALLBACK;
789 pcie_data = AMDGPU_PCIE_DATA_FALLBACK;
790 } else {
791 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
792 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
793 }
794
795 if (reg_addr >> 32) {
796 if (unlikely(!adev->nbio.funcs))
797 pcie_index_hi = AMDGPU_PCIE_INDEX_HI_FALLBACK;
798 else
799 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
800 } else {
801 pcie_index_hi = 0;
802 }
803
804 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
805 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
806 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
807 if (pcie_index_hi != 0)
808 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
809 pcie_index_hi * 4;
810
811 writel(reg_addr, pcie_index_offset);
812 readl(pcie_index_offset);
813 if (pcie_index_hi != 0) {
814 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
815 readl(pcie_index_hi_offset);
816 }
817 r = readl(pcie_data_offset);
818
819 /* clear the high bits */
820 if (pcie_index_hi != 0) {
821 writel(0, pcie_index_hi_offset);
822 readl(pcie_index_hi_offset);
823 }
824
825 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
826
827 return r;
828}
829
830/**
831 * amdgpu_device_indirect_rreg64 - read a 64bits indirect register
832 *
833 * @adev: amdgpu_device pointer
834 * @reg_addr: indirect register address to read from
835 *
836 * Returns the value of indirect register @reg_addr
837 */
838u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
839 u32 reg_addr)
840{
841 unsigned long flags, pcie_index, pcie_data;
842 void __iomem *pcie_index_offset;
843 void __iomem *pcie_data_offset;
844 u64 r;
845
846 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
847 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
848
849 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
850 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
851 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
852
853 /* read low 32 bits */
854 writel(reg_addr, pcie_index_offset);
855 readl(pcie_index_offset);
856 r = readl(pcie_data_offset);
857 /* read high 32 bits */
858 writel(reg_addr + 4, pcie_index_offset);
859 readl(pcie_index_offset);
860 r |= ((u64)readl(pcie_data_offset) << 32);
861 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
862
863 return r;
864}
865
866u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev,
867 u64 reg_addr)
868{
869 unsigned long flags, pcie_index, pcie_data;
870 unsigned long pcie_index_hi = 0;
871 void __iomem *pcie_index_offset;
872 void __iomem *pcie_index_hi_offset;
873 void __iomem *pcie_data_offset;
874 u64 r;
875
876 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
877 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
878 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
879 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
880
881 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
882 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
883 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
884 if (pcie_index_hi != 0)
885 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
886 pcie_index_hi * 4;
887
888 /* read low 32 bits */
889 writel(reg_addr, pcie_index_offset);
890 readl(pcie_index_offset);
891 if (pcie_index_hi != 0) {
892 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
893 readl(pcie_index_hi_offset);
894 }
895 r = readl(pcie_data_offset);
896 /* read high 32 bits */
897 writel(reg_addr + 4, pcie_index_offset);
898 readl(pcie_index_offset);
899 if (pcie_index_hi != 0) {
900 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
901 readl(pcie_index_hi_offset);
902 }
903 r |= ((u64)readl(pcie_data_offset) << 32);
904
905 /* clear the high bits */
906 if (pcie_index_hi != 0) {
907 writel(0, pcie_index_hi_offset);
908 readl(pcie_index_hi_offset);
909 }
910
911 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
912
913 return r;
914}
915
916/**
917 * amdgpu_device_indirect_wreg - write an indirect register address
918 *
919 * @adev: amdgpu_device pointer
920 * @reg_addr: indirect register offset
921 * @reg_data: indirect register data
922 *
923 */
924void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
925 u32 reg_addr, u32 reg_data)
926{
927 unsigned long flags, pcie_index, pcie_data;
928 void __iomem *pcie_index_offset;
929 void __iomem *pcie_data_offset;
930
931 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
932 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
933
934 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
935 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
936 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
937
938 writel(reg_addr, pcie_index_offset);
939 readl(pcie_index_offset);
940 writel(reg_data, pcie_data_offset);
941 readl(pcie_data_offset);
942 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
943}
944
945void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
946 u64 reg_addr, u32 reg_data)
947{
948 unsigned long flags, pcie_index, pcie_index_hi, pcie_data;
949 void __iomem *pcie_index_offset;
950 void __iomem *pcie_index_hi_offset;
951 void __iomem *pcie_data_offset;
952
953 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
954 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
955 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
956 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
957 else
958 pcie_index_hi = 0;
959
960 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
961 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
962 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
963 if (pcie_index_hi != 0)
964 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
965 pcie_index_hi * 4;
966
967 writel(reg_addr, pcie_index_offset);
968 readl(pcie_index_offset);
969 if (pcie_index_hi != 0) {
970 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
971 readl(pcie_index_hi_offset);
972 }
973 writel(reg_data, pcie_data_offset);
974 readl(pcie_data_offset);
975
976 /* clear the high bits */
977 if (pcie_index_hi != 0) {
978 writel(0, pcie_index_hi_offset);
979 readl(pcie_index_hi_offset);
980 }
981
982 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
983}
984
985/**
986 * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address
987 *
988 * @adev: amdgpu_device pointer
989 * @reg_addr: indirect register offset
990 * @reg_data: indirect register data
991 *
992 */
993void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
994 u32 reg_addr, u64 reg_data)
995{
996 unsigned long flags, pcie_index, pcie_data;
997 void __iomem *pcie_index_offset;
998 void __iomem *pcie_data_offset;
999
1000 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
1001 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
1002
1003 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1004 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
1005 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
1006
1007 /* write low 32 bits */
1008 writel(reg_addr, pcie_index_offset);
1009 readl(pcie_index_offset);
1010 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
1011 readl(pcie_data_offset);
1012 /* write high 32 bits */
1013 writel(reg_addr + 4, pcie_index_offset);
1014 readl(pcie_index_offset);
1015 writel((u32)(reg_data >> 32), pcie_data_offset);
1016 readl(pcie_data_offset);
1017 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1018}
1019
1020void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev,
1021 u64 reg_addr, u64 reg_data)
1022{
1023 unsigned long flags, pcie_index, pcie_data;
1024 unsigned long pcie_index_hi = 0;
1025 void __iomem *pcie_index_offset;
1026 void __iomem *pcie_index_hi_offset;
1027 void __iomem *pcie_data_offset;
1028
1029 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev);
1030 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev);
1031 if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset))
1032 pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev);
1033
1034 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1035 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
1036 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
1037 if (pcie_index_hi != 0)
1038 pcie_index_hi_offset = (void __iomem *)adev->rmmio +
1039 pcie_index_hi * 4;
1040
1041 /* write low 32 bits */
1042 writel(reg_addr, pcie_index_offset);
1043 readl(pcie_index_offset);
1044 if (pcie_index_hi != 0) {
1045 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
1046 readl(pcie_index_hi_offset);
1047 }
1048 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
1049 readl(pcie_data_offset);
1050 /* write high 32 bits */
1051 writel(reg_addr + 4, pcie_index_offset);
1052 readl(pcie_index_offset);
1053 if (pcie_index_hi != 0) {
1054 writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
1055 readl(pcie_index_hi_offset);
1056 }
1057 writel((u32)(reg_data >> 32), pcie_data_offset);
1058 readl(pcie_data_offset);
1059
1060 /* clear the high bits */
1061 if (pcie_index_hi != 0) {
1062 writel(0, pcie_index_hi_offset);
1063 readl(pcie_index_hi_offset);
1064 }
1065
1066 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1067}
1068
1069/**
1070 * amdgpu_device_get_rev_id - query device rev_id
1071 *
1072 * @adev: amdgpu_device pointer
1073 *
1074 * Return device rev_id
1075 */
1076u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev)
1077{
1078 return adev->nbio.funcs->get_rev_id(adev);
1079}
1080
1081/**
1082 * amdgpu_invalid_rreg - dummy reg read function
1083 *
1084 * @adev: amdgpu_device pointer
1085 * @reg: offset of register
1086 *
1087 * Dummy register read function. Used for register blocks
1088 * that certain asics don't have (all asics).
1089 * Returns the value in the register.
1090 */
1091static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
1092{
1093 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
1094 BUG();
1095 return 0;
1096}
1097
1098static uint32_t amdgpu_invalid_rreg_ext(struct amdgpu_device *adev, uint64_t reg)
1099{
1100 DRM_ERROR("Invalid callback to read register 0x%llX\n", reg);
1101 BUG();
1102 return 0;
1103}
1104
1105/**
1106 * amdgpu_invalid_wreg - dummy reg write function
1107 *
1108 * @adev: amdgpu_device pointer
1109 * @reg: offset of register
1110 * @v: value to write to the register
1111 *
1112 * Dummy register read function. Used for register blocks
1113 * that certain asics don't have (all asics).
1114 */
1115static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
1116{
1117 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
1118 reg, v);
1119 BUG();
1120}
1121
1122static void amdgpu_invalid_wreg_ext(struct amdgpu_device *adev, uint64_t reg, uint32_t v)
1123{
1124 DRM_ERROR("Invalid callback to write register 0x%llX with 0x%08X\n",
1125 reg, v);
1126 BUG();
1127}
1128
1129/**
1130 * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
1131 *
1132 * @adev: amdgpu_device pointer
1133 * @reg: offset of register
1134 *
1135 * Dummy register read function. Used for register blocks
1136 * that certain asics don't have (all asics).
1137 * Returns the value in the register.
1138 */
1139static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
1140{
1141 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
1142 BUG();
1143 return 0;
1144}
1145
1146static uint64_t amdgpu_invalid_rreg64_ext(struct amdgpu_device *adev, uint64_t reg)
1147{
1148 DRM_ERROR("Invalid callback to read register 0x%llX\n", reg);
1149 BUG();
1150 return 0;
1151}
1152
1153/**
1154 * amdgpu_invalid_wreg64 - dummy reg write function
1155 *
1156 * @adev: amdgpu_device pointer
1157 * @reg: offset of register
1158 * @v: value to write to the register
1159 *
1160 * Dummy register read function. Used for register blocks
1161 * that certain asics don't have (all asics).
1162 */
1163static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
1164{
1165 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
1166 reg, v);
1167 BUG();
1168}
1169
1170static void amdgpu_invalid_wreg64_ext(struct amdgpu_device *adev, uint64_t reg, uint64_t v)
1171{
1172 DRM_ERROR("Invalid callback to write 64 bit register 0x%llX with 0x%08llX\n",
1173 reg, v);
1174 BUG();
1175}
1176
1177/**
1178 * amdgpu_block_invalid_rreg - dummy reg read function
1179 *
1180 * @adev: amdgpu_device pointer
1181 * @block: offset of instance
1182 * @reg: offset of register
1183 *
1184 * Dummy register read function. Used for register blocks
1185 * that certain asics don't have (all asics).
1186 * Returns the value in the register.
1187 */
1188static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
1189 uint32_t block, uint32_t reg)
1190{
1191 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
1192 reg, block);
1193 BUG();
1194 return 0;
1195}
1196
1197/**
1198 * amdgpu_block_invalid_wreg - dummy reg write function
1199 *
1200 * @adev: amdgpu_device pointer
1201 * @block: offset of instance
1202 * @reg: offset of register
1203 * @v: value to write to the register
1204 *
1205 * Dummy register read function. Used for register blocks
1206 * that certain asics don't have (all asics).
1207 */
1208static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
1209 uint32_t block,
1210 uint32_t reg, uint32_t v)
1211{
1212 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
1213 reg, block, v);
1214 BUG();
1215}
1216
1217/**
1218 * amdgpu_device_asic_init - Wrapper for atom asic_init
1219 *
1220 * @adev: amdgpu_device pointer
1221 *
1222 * Does any asic specific work and then calls atom asic init.
1223 */
1224static int amdgpu_device_asic_init(struct amdgpu_device *adev)
1225{
1226 int ret;
1227
1228 amdgpu_asic_pre_asic_init(adev);
1229
1230 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
1231 amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0)) {
1232 amdgpu_psp_wait_for_bootloader(adev);
1233 ret = amdgpu_atomfirmware_asic_init(adev, true);
1234 return ret;
1235 } else {
1236 return amdgpu_atom_asic_init(adev->mode_info.atom_context);
1237 }
1238
1239 return 0;
1240}
1241
1242/**
1243 * amdgpu_device_mem_scratch_init - allocate the VRAM scratch page
1244 *
1245 * @adev: amdgpu_device pointer
1246 *
1247 * Allocates a scratch page of VRAM for use by various things in the
1248 * driver.
1249 */
1250static int amdgpu_device_mem_scratch_init(struct amdgpu_device *adev)
1251{
1252 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE,
1253 AMDGPU_GEM_DOMAIN_VRAM |
1254 AMDGPU_GEM_DOMAIN_GTT,
1255 &adev->mem_scratch.robj,
1256 &adev->mem_scratch.gpu_addr,
1257 (void **)&adev->mem_scratch.ptr);
1258}
1259
1260/**
1261 * amdgpu_device_mem_scratch_fini - Free the VRAM scratch page
1262 *
1263 * @adev: amdgpu_device pointer
1264 *
1265 * Frees the VRAM scratch page.
1266 */
1267static void amdgpu_device_mem_scratch_fini(struct amdgpu_device *adev)
1268{
1269 amdgpu_bo_free_kernel(&adev->mem_scratch.robj, NULL, NULL);
1270}
1271
1272/**
1273 * amdgpu_device_program_register_sequence - program an array of registers.
1274 *
1275 * @adev: amdgpu_device pointer
1276 * @registers: pointer to the register array
1277 * @array_size: size of the register array
1278 *
1279 * Programs an array or registers with and or masks.
1280 * This is a helper for setting golden registers.
1281 */
1282void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1283 const u32 *registers,
1284 const u32 array_size)
1285{
1286 u32 tmp, reg, and_mask, or_mask;
1287 int i;
1288
1289 if (array_size % 3)
1290 return;
1291
1292 for (i = 0; i < array_size; i += 3) {
1293 reg = registers[i + 0];
1294 and_mask = registers[i + 1];
1295 or_mask = registers[i + 2];
1296
1297 if (and_mask == 0xffffffff) {
1298 tmp = or_mask;
1299 } else {
1300 tmp = RREG32(reg);
1301 tmp &= ~and_mask;
1302 if (adev->family >= AMDGPU_FAMILY_AI)
1303 tmp |= (or_mask & and_mask);
1304 else
1305 tmp |= or_mask;
1306 }
1307 WREG32(reg, tmp);
1308 }
1309}
1310
1311/**
1312 * amdgpu_device_pci_config_reset - reset the GPU
1313 *
1314 * @adev: amdgpu_device pointer
1315 *
1316 * Resets the GPU using the pci config reset sequence.
1317 * Only applicable to asics prior to vega10.
1318 */
1319void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
1320{
1321 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
1322}
1323
1324/**
1325 * amdgpu_device_pci_reset - reset the GPU using generic PCI means
1326 *
1327 * @adev: amdgpu_device pointer
1328 *
1329 * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.).
1330 */
1331int amdgpu_device_pci_reset(struct amdgpu_device *adev)
1332{
1333 return pci_reset_function(adev->pdev);
1334}
1335
1336/*
1337 * amdgpu_device_wb_*()
1338 * Writeback is the method by which the GPU updates special pages in memory
1339 * with the status of certain GPU events (fences, ring pointers,etc.).
1340 */
1341
1342/**
1343 * amdgpu_device_wb_fini - Disable Writeback and free memory
1344 *
1345 * @adev: amdgpu_device pointer
1346 *
1347 * Disables Writeback and frees the Writeback memory (all asics).
1348 * Used at driver shutdown.
1349 */
1350static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
1351{
1352 if (adev->wb.wb_obj) {
1353 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
1354 &adev->wb.gpu_addr,
1355 (void **)&adev->wb.wb);
1356 adev->wb.wb_obj = NULL;
1357 }
1358}
1359
1360/**
1361 * amdgpu_device_wb_init - Init Writeback driver info and allocate memory
1362 *
1363 * @adev: amdgpu_device pointer
1364 *
1365 * Initializes writeback and allocates writeback memory (all asics).
1366 * Used at driver startup.
1367 * Returns 0 on success or an -error on failure.
1368 */
1369static int amdgpu_device_wb_init(struct amdgpu_device *adev)
1370{
1371 int r;
1372
1373 if (adev->wb.wb_obj == NULL) {
1374 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
1375 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
1376 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1377 &adev->wb.wb_obj, &adev->wb.gpu_addr,
1378 (void **)&adev->wb.wb);
1379 if (r) {
1380 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
1381 return r;
1382 }
1383
1384 adev->wb.num_wb = AMDGPU_MAX_WB;
1385 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
1386
1387 /* clear wb memory */
1388 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
1389 }
1390
1391 return 0;
1392}
1393
1394/**
1395 * amdgpu_device_wb_get - Allocate a wb entry
1396 *
1397 * @adev: amdgpu_device pointer
1398 * @wb: wb index
1399 *
1400 * Allocate a wb slot for use by the driver (all asics).
1401 * Returns 0 on success or -EINVAL on failure.
1402 */
1403int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
1404{
1405 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
1406
1407 if (offset < adev->wb.num_wb) {
1408 __set_bit(offset, adev->wb.used);
1409 *wb = offset << 3; /* convert to dw offset */
1410 return 0;
1411 } else {
1412 return -EINVAL;
1413 }
1414}
1415
1416/**
1417 * amdgpu_device_wb_free - Free a wb entry
1418 *
1419 * @adev: amdgpu_device pointer
1420 * @wb: wb index
1421 *
1422 * Free a wb slot allocated for use by the driver (all asics)
1423 */
1424void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
1425{
1426 wb >>= 3;
1427 if (wb < adev->wb.num_wb)
1428 __clear_bit(wb, adev->wb.used);
1429}
1430
1431/**
1432 * amdgpu_device_resize_fb_bar - try to resize FB BAR
1433 *
1434 * @adev: amdgpu_device pointer
1435 *
1436 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
1437 * to fail, but if any of the BARs is not accessible after the size we abort
1438 * driver loading by returning -ENODEV.
1439 */
1440int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
1441{
1442 int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size);
1443 struct pci_bus *root;
1444 struct resource *res;
1445 unsigned int i;
1446 u16 cmd;
1447 int r;
1448
1449 if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT))
1450 return 0;
1451
1452 /* Bypass for VF */
1453 if (amdgpu_sriov_vf(adev))
1454 return 0;
1455
1456 /* PCI_EXT_CAP_ID_VNDR extended capability is located at 0x100 */
1457 if (!pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_VNDR))
1458 DRM_WARN("System can't access extended configuration space,please check!!\n");
1459
1460 /* skip if the bios has already enabled large BAR */
1461 if (adev->gmc.real_vram_size &&
1462 (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
1463 return 0;
1464
1465 /* Check if the root BUS has 64bit memory resources */
1466 root = adev->pdev->bus;
1467 while (root->parent)
1468 root = root->parent;
1469
1470 pci_bus_for_each_resource(root, res, i) {
1471 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
1472 res->start > 0x100000000ull)
1473 break;
1474 }
1475
1476 /* Trying to resize is pointless without a root hub window above 4GB */
1477 if (!res)
1478 return 0;
1479
1480 /* Limit the BAR size to what is available */
1481 rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1,
1482 rbar_size);
1483
1484 /* Disable memory decoding while we change the BAR addresses and size */
1485 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
1486 pci_write_config_word(adev->pdev, PCI_COMMAND,
1487 cmd & ~PCI_COMMAND_MEMORY);
1488
1489 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
1490 amdgpu_doorbell_fini(adev);
1491 if (adev->asic_type >= CHIP_BONAIRE)
1492 pci_release_resource(adev->pdev, 2);
1493
1494 pci_release_resource(adev->pdev, 0);
1495
1496 r = pci_resize_resource(adev->pdev, 0, rbar_size);
1497 if (r == -ENOSPC)
1498 DRM_INFO("Not enough PCI address space for a large BAR.");
1499 else if (r && r != -ENOTSUPP)
1500 DRM_ERROR("Problem resizing BAR0 (%d).", r);
1501
1502 pci_assign_unassigned_bus_resources(adev->pdev->bus);
1503
1504 /* When the doorbell or fb BAR isn't available we have no chance of
1505 * using the device.
1506 */
1507 r = amdgpu_doorbell_init(adev);
1508 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
1509 return -ENODEV;
1510
1511 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
1512
1513 return 0;
1514}
1515
1516static bool amdgpu_device_read_bios(struct amdgpu_device *adev)
1517{
1518 if (hweight32(adev->aid_mask) && (adev->flags & AMD_IS_APU))
1519 return false;
1520
1521 return true;
1522}
1523
1524/*
1525 * GPU helpers function.
1526 */
1527/**
1528 * amdgpu_device_need_post - check if the hw need post or not
1529 *
1530 * @adev: amdgpu_device pointer
1531 *
1532 * Check if the asic has been initialized (all asics) at driver startup
1533 * or post is needed if hw reset is performed.
1534 * Returns true if need or false if not.
1535 */
1536bool amdgpu_device_need_post(struct amdgpu_device *adev)
1537{
1538 uint32_t reg;
1539
1540 if (amdgpu_sriov_vf(adev))
1541 return false;
1542
1543 if (!amdgpu_device_read_bios(adev))
1544 return false;
1545
1546 if (amdgpu_passthrough(adev)) {
1547 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
1548 * some old smc fw still need driver do vPost otherwise gpu hang, while
1549 * those smc fw version above 22.15 doesn't have this flaw, so we force
1550 * vpost executed for smc version below 22.15
1551 */
1552 if (adev->asic_type == CHIP_FIJI) {
1553 int err;
1554 uint32_t fw_ver;
1555
1556 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
1557 /* force vPost if error occured */
1558 if (err)
1559 return true;
1560
1561 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
1562 release_firmware(adev->pm.fw);
1563 if (fw_ver < 0x00160e00)
1564 return true;
1565 }
1566 }
1567
1568 /* Don't post if we need to reset whole hive on init */
1569 if (adev->gmc.xgmi.pending_reset)
1570 return false;
1571
1572 if (adev->has_hw_reset) {
1573 adev->has_hw_reset = false;
1574 return true;
1575 }
1576
1577 /* bios scratch used on CIK+ */
1578 if (adev->asic_type >= CHIP_BONAIRE)
1579 return amdgpu_atombios_scratch_need_asic_init(adev);
1580
1581 /* check MEM_SIZE for older asics */
1582 reg = amdgpu_asic_get_config_memsize(adev);
1583
1584 if ((reg != 0) && (reg != 0xffffffff))
1585 return false;
1586
1587 return true;
1588}
1589
1590/*
1591 * Check whether seamless boot is supported.
1592 *
1593 * So far we only support seamless boot on DCE 3.0 or later.
1594 * If users report that it works on older ASICS as well, we may
1595 * loosen this.
1596 */
1597bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev)
1598{
1599 switch (amdgpu_seamless) {
1600 case -1:
1601 break;
1602 case 1:
1603 return true;
1604 case 0:
1605 return false;
1606 default:
1607 DRM_ERROR("Invalid value for amdgpu.seamless: %d\n",
1608 amdgpu_seamless);
1609 return false;
1610 }
1611
1612 if (!(adev->flags & AMD_IS_APU))
1613 return false;
1614
1615 if (adev->mman.keep_stolen_vga_memory)
1616 return false;
1617
1618 return amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0);
1619}
1620
1621/*
1622 * Intel hosts such as Rocket Lake, Alder Lake, Raptor Lake and Sapphire Rapids
1623 * don't support dynamic speed switching. Until we have confirmation from Intel
1624 * that a specific host supports it, it's safer that we keep it disabled for all.
1625 *
1626 * https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/
1627 * https://gitlab.freedesktop.org/drm/amd/-/issues/2663
1628 */
1629static bool amdgpu_device_pcie_dynamic_switching_supported(struct amdgpu_device *adev)
1630{
1631#if IS_ENABLED(CONFIG_X86)
1632 struct cpuinfo_x86 *c = &cpu_data(0);
1633
1634 /* eGPU change speeds based on USB4 fabric conditions */
1635 if (dev_is_removable(adev->dev))
1636 return true;
1637
1638 if (c->x86_vendor == X86_VENDOR_INTEL)
1639 return false;
1640#endif
1641 return true;
1642}
1643
1644/**
1645 * amdgpu_device_should_use_aspm - check if the device should program ASPM
1646 *
1647 * @adev: amdgpu_device pointer
1648 *
1649 * Confirm whether the module parameter and pcie bridge agree that ASPM should
1650 * be set for this device.
1651 *
1652 * Returns true if it should be used or false if not.
1653 */
1654bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev)
1655{
1656 switch (amdgpu_aspm) {
1657 case -1:
1658 break;
1659 case 0:
1660 return false;
1661 case 1:
1662 return true;
1663 default:
1664 return false;
1665 }
1666 if (adev->flags & AMD_IS_APU)
1667 return false;
1668 if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK))
1669 return false;
1670 return pcie_aspm_enabled(adev->pdev);
1671}
1672
1673/* if we get transitioned to only one device, take VGA back */
1674/**
1675 * amdgpu_device_vga_set_decode - enable/disable vga decode
1676 *
1677 * @pdev: PCI device pointer
1678 * @state: enable/disable vga decode
1679 *
1680 * Enable/disable vga decode (all asics).
1681 * Returns VGA resource flags.
1682 */
1683static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev,
1684 bool state)
1685{
1686 struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev));
1687
1688 amdgpu_asic_set_vga_state(adev, state);
1689 if (state)
1690 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1691 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1692 else
1693 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1694}
1695
1696/**
1697 * amdgpu_device_check_block_size - validate the vm block size
1698 *
1699 * @adev: amdgpu_device pointer
1700 *
1701 * Validates the vm block size specified via module parameter.
1702 * The vm block size defines number of bits in page table versus page directory,
1703 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1704 * page table and the remaining bits are in the page directory.
1705 */
1706static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
1707{
1708 /* defines number of bits in page table versus page directory,
1709 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1710 * page table and the remaining bits are in the page directory
1711 */
1712 if (amdgpu_vm_block_size == -1)
1713 return;
1714
1715 if (amdgpu_vm_block_size < 9) {
1716 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1717 amdgpu_vm_block_size);
1718 amdgpu_vm_block_size = -1;
1719 }
1720}
1721
1722/**
1723 * amdgpu_device_check_vm_size - validate the vm size
1724 *
1725 * @adev: amdgpu_device pointer
1726 *
1727 * Validates the vm size in GB specified via module parameter.
1728 * The VM size is the size of the GPU virtual memory space in GB.
1729 */
1730static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
1731{
1732 /* no need to check the default value */
1733 if (amdgpu_vm_size == -1)
1734 return;
1735
1736 if (amdgpu_vm_size < 1) {
1737 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1738 amdgpu_vm_size);
1739 amdgpu_vm_size = -1;
1740 }
1741}
1742
1743static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
1744{
1745 struct sysinfo si;
1746 bool is_os_64 = (sizeof(void *) == 8);
1747 uint64_t total_memory;
1748 uint64_t dram_size_seven_GB = 0x1B8000000;
1749 uint64_t dram_size_three_GB = 0xB8000000;
1750
1751 if (amdgpu_smu_memory_pool_size == 0)
1752 return;
1753
1754 if (!is_os_64) {
1755 DRM_WARN("Not 64-bit OS, feature not supported\n");
1756 goto def_value;
1757 }
1758 si_meminfo(&si);
1759 total_memory = (uint64_t)si.totalram * si.mem_unit;
1760
1761 if ((amdgpu_smu_memory_pool_size == 1) ||
1762 (amdgpu_smu_memory_pool_size == 2)) {
1763 if (total_memory < dram_size_three_GB)
1764 goto def_value1;
1765 } else if ((amdgpu_smu_memory_pool_size == 4) ||
1766 (amdgpu_smu_memory_pool_size == 8)) {
1767 if (total_memory < dram_size_seven_GB)
1768 goto def_value1;
1769 } else {
1770 DRM_WARN("Smu memory pool size not supported\n");
1771 goto def_value;
1772 }
1773 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
1774
1775 return;
1776
1777def_value1:
1778 DRM_WARN("No enough system memory\n");
1779def_value:
1780 adev->pm.smu_prv_buffer_size = 0;
1781}
1782
1783static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev)
1784{
1785 if (!(adev->flags & AMD_IS_APU) ||
1786 adev->asic_type < CHIP_RAVEN)
1787 return 0;
1788
1789 switch (adev->asic_type) {
1790 case CHIP_RAVEN:
1791 if (adev->pdev->device == 0x15dd)
1792 adev->apu_flags |= AMD_APU_IS_RAVEN;
1793 if (adev->pdev->device == 0x15d8)
1794 adev->apu_flags |= AMD_APU_IS_PICASSO;
1795 break;
1796 case CHIP_RENOIR:
1797 if ((adev->pdev->device == 0x1636) ||
1798 (adev->pdev->device == 0x164c))
1799 adev->apu_flags |= AMD_APU_IS_RENOIR;
1800 else
1801 adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
1802 break;
1803 case CHIP_VANGOGH:
1804 adev->apu_flags |= AMD_APU_IS_VANGOGH;
1805 break;
1806 case CHIP_YELLOW_CARP:
1807 break;
1808 case CHIP_CYAN_SKILLFISH:
1809 if ((adev->pdev->device == 0x13FE) ||
1810 (adev->pdev->device == 0x143F))
1811 adev->apu_flags |= AMD_APU_IS_CYAN_SKILLFISH2;
1812 break;
1813 default:
1814 break;
1815 }
1816
1817 return 0;
1818}
1819
1820/**
1821 * amdgpu_device_check_arguments - validate module params
1822 *
1823 * @adev: amdgpu_device pointer
1824 *
1825 * Validates certain module parameters and updates
1826 * the associated values used by the driver (all asics).
1827 */
1828static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
1829{
1830 if (amdgpu_sched_jobs < 4) {
1831 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1832 amdgpu_sched_jobs);
1833 amdgpu_sched_jobs = 4;
1834 } else if (!is_power_of_2(amdgpu_sched_jobs)) {
1835 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1836 amdgpu_sched_jobs);
1837 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1838 }
1839
1840 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1841 /* gart size must be greater or equal to 32M */
1842 dev_warn(adev->dev, "gart size (%d) too small\n",
1843 amdgpu_gart_size);
1844 amdgpu_gart_size = -1;
1845 }
1846
1847 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1848 /* gtt size must be greater or equal to 32M */
1849 dev_warn(adev->dev, "gtt size (%d) too small\n",
1850 amdgpu_gtt_size);
1851 amdgpu_gtt_size = -1;
1852 }
1853
1854 /* valid range is between 4 and 9 inclusive */
1855 if (amdgpu_vm_fragment_size != -1 &&
1856 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1857 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1858 amdgpu_vm_fragment_size = -1;
1859 }
1860
1861 if (amdgpu_sched_hw_submission < 2) {
1862 dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n",
1863 amdgpu_sched_hw_submission);
1864 amdgpu_sched_hw_submission = 2;
1865 } else if (!is_power_of_2(amdgpu_sched_hw_submission)) {
1866 dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n",
1867 amdgpu_sched_hw_submission);
1868 amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission);
1869 }
1870
1871 if (amdgpu_reset_method < -1 || amdgpu_reset_method > 4) {
1872 dev_warn(adev->dev, "invalid option for reset method, reverting to default\n");
1873 amdgpu_reset_method = -1;
1874 }
1875
1876 amdgpu_device_check_smu_prv_buffer_size(adev);
1877
1878 amdgpu_device_check_vm_size(adev);
1879
1880 amdgpu_device_check_block_size(adev);
1881
1882 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1883
1884 return 0;
1885}
1886
1887/**
1888 * amdgpu_switcheroo_set_state - set switcheroo state
1889 *
1890 * @pdev: pci dev pointer
1891 * @state: vga_switcheroo state
1892 *
1893 * Callback for the switcheroo driver. Suspends or resumes
1894 * the asics before or after it is powered up using ACPI methods.
1895 */
1896static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,
1897 enum vga_switcheroo_state state)
1898{
1899 struct drm_device *dev = pci_get_drvdata(pdev);
1900 int r;
1901
1902 if (amdgpu_device_supports_px(dev) && state == VGA_SWITCHEROO_OFF)
1903 return;
1904
1905 if (state == VGA_SWITCHEROO_ON) {
1906 pr_info("switched on\n");
1907 /* don't suspend or resume card normally */
1908 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1909
1910 pci_set_power_state(pdev, PCI_D0);
1911 amdgpu_device_load_pci_state(pdev);
1912 r = pci_enable_device(pdev);
1913 if (r)
1914 DRM_WARN("pci_enable_device failed (%d)\n", r);
1915 amdgpu_device_resume(dev, true);
1916
1917 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1918 } else {
1919 pr_info("switched off\n");
1920 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1921 amdgpu_device_prepare(dev);
1922 amdgpu_device_suspend(dev, true);
1923 amdgpu_device_cache_pci_state(pdev);
1924 /* Shut down the device */
1925 pci_disable_device(pdev);
1926 pci_set_power_state(pdev, PCI_D3cold);
1927 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1928 }
1929}
1930
1931/**
1932 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1933 *
1934 * @pdev: pci dev pointer
1935 *
1936 * Callback for the switcheroo driver. Check of the switcheroo
1937 * state can be changed.
1938 * Returns true if the state can be changed, false if not.
1939 */
1940static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1941{
1942 struct drm_device *dev = pci_get_drvdata(pdev);
1943
1944 /*
1945 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1946 * locking inversion with the driver load path. And the access here is
1947 * completely racy anyway. So don't bother with locking for now.
1948 */
1949 return atomic_read(&dev->open_count) == 0;
1950}
1951
1952static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1953 .set_gpu_state = amdgpu_switcheroo_set_state,
1954 .reprobe = NULL,
1955 .can_switch = amdgpu_switcheroo_can_switch,
1956};
1957
1958/**
1959 * amdgpu_device_ip_set_clockgating_state - set the CG state
1960 *
1961 * @dev: amdgpu_device pointer
1962 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1963 * @state: clockgating state (gate or ungate)
1964 *
1965 * Sets the requested clockgating state for all instances of
1966 * the hardware IP specified.
1967 * Returns the error code from the last instance.
1968 */
1969int amdgpu_device_ip_set_clockgating_state(void *dev,
1970 enum amd_ip_block_type block_type,
1971 enum amd_clockgating_state state)
1972{
1973 struct amdgpu_device *adev = dev;
1974 int i, r = 0;
1975
1976 for (i = 0; i < adev->num_ip_blocks; i++) {
1977 if (!adev->ip_blocks[i].status.valid)
1978 continue;
1979 if (adev->ip_blocks[i].version->type != block_type)
1980 continue;
1981 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1982 continue;
1983 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1984 (void *)adev, state);
1985 if (r)
1986 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1987 adev->ip_blocks[i].version->funcs->name, r);
1988 }
1989 return r;
1990}
1991
1992/**
1993 * amdgpu_device_ip_set_powergating_state - set the PG state
1994 *
1995 * @dev: amdgpu_device pointer
1996 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1997 * @state: powergating state (gate or ungate)
1998 *
1999 * Sets the requested powergating state for all instances of
2000 * the hardware IP specified.
2001 * Returns the error code from the last instance.
2002 */
2003int amdgpu_device_ip_set_powergating_state(void *dev,
2004 enum amd_ip_block_type block_type,
2005 enum amd_powergating_state state)
2006{
2007 struct amdgpu_device *adev = dev;
2008 int i, r = 0;
2009
2010 for (i = 0; i < adev->num_ip_blocks; i++) {
2011 if (!adev->ip_blocks[i].status.valid)
2012 continue;
2013 if (adev->ip_blocks[i].version->type != block_type)
2014 continue;
2015 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
2016 continue;
2017 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
2018 (void *)adev, state);
2019 if (r)
2020 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
2021 adev->ip_blocks[i].version->funcs->name, r);
2022 }
2023 return r;
2024}
2025
2026/**
2027 * amdgpu_device_ip_get_clockgating_state - get the CG state
2028 *
2029 * @adev: amdgpu_device pointer
2030 * @flags: clockgating feature flags
2031 *
2032 * Walks the list of IPs on the device and updates the clockgating
2033 * flags for each IP.
2034 * Updates @flags with the feature flags for each hardware IP where
2035 * clockgating is enabled.
2036 */
2037void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
2038 u64 *flags)
2039{
2040 int i;
2041
2042 for (i = 0; i < adev->num_ip_blocks; i++) {
2043 if (!adev->ip_blocks[i].status.valid)
2044 continue;
2045 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
2046 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
2047 }
2048}
2049
2050/**
2051 * amdgpu_device_ip_wait_for_idle - wait for idle
2052 *
2053 * @adev: amdgpu_device pointer
2054 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
2055 *
2056 * Waits for the request hardware IP to be idle.
2057 * Returns 0 for success or a negative error code on failure.
2058 */
2059int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
2060 enum amd_ip_block_type block_type)
2061{
2062 int i, r;
2063
2064 for (i = 0; i < adev->num_ip_blocks; i++) {
2065 if (!adev->ip_blocks[i].status.valid)
2066 continue;
2067 if (adev->ip_blocks[i].version->type == block_type) {
2068 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
2069 if (r)
2070 return r;
2071 break;
2072 }
2073 }
2074 return 0;
2075
2076}
2077
2078/**
2079 * amdgpu_device_ip_is_idle - is the hardware IP idle
2080 *
2081 * @adev: amdgpu_device pointer
2082 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
2083 *
2084 * Check if the hardware IP is idle or not.
2085 * Returns true if it the IP is idle, false if not.
2086 */
2087bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
2088 enum amd_ip_block_type block_type)
2089{
2090 int i;
2091
2092 for (i = 0; i < adev->num_ip_blocks; i++) {
2093 if (!adev->ip_blocks[i].status.valid)
2094 continue;
2095 if (adev->ip_blocks[i].version->type == block_type)
2096 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
2097 }
2098 return true;
2099
2100}
2101
2102/**
2103 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
2104 *
2105 * @adev: amdgpu_device pointer
2106 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
2107 *
2108 * Returns a pointer to the hardware IP block structure
2109 * if it exists for the asic, otherwise NULL.
2110 */
2111struct amdgpu_ip_block *
2112amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
2113 enum amd_ip_block_type type)
2114{
2115 int i;
2116
2117 for (i = 0; i < adev->num_ip_blocks; i++)
2118 if (adev->ip_blocks[i].version->type == type)
2119 return &adev->ip_blocks[i];
2120
2121 return NULL;
2122}
2123
2124/**
2125 * amdgpu_device_ip_block_version_cmp
2126 *
2127 * @adev: amdgpu_device pointer
2128 * @type: enum amd_ip_block_type
2129 * @major: major version
2130 * @minor: minor version
2131 *
2132 * return 0 if equal or greater
2133 * return 1 if smaller or the ip_block doesn't exist
2134 */
2135int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
2136 enum amd_ip_block_type type,
2137 u32 major, u32 minor)
2138{
2139 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
2140
2141 if (ip_block && ((ip_block->version->major > major) ||
2142 ((ip_block->version->major == major) &&
2143 (ip_block->version->minor >= minor))))
2144 return 0;
2145
2146 return 1;
2147}
2148
2149/**
2150 * amdgpu_device_ip_block_add
2151 *
2152 * @adev: amdgpu_device pointer
2153 * @ip_block_version: pointer to the IP to add
2154 *
2155 * Adds the IP block driver information to the collection of IPs
2156 * on the asic.
2157 */
2158int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
2159 const struct amdgpu_ip_block_version *ip_block_version)
2160{
2161 if (!ip_block_version)
2162 return -EINVAL;
2163
2164 switch (ip_block_version->type) {
2165 case AMD_IP_BLOCK_TYPE_VCN:
2166 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
2167 return 0;
2168 break;
2169 case AMD_IP_BLOCK_TYPE_JPEG:
2170 if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK)
2171 return 0;
2172 break;
2173 default:
2174 break;
2175 }
2176
2177 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
2178 ip_block_version->funcs->name);
2179
2180 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
2181
2182 return 0;
2183}
2184
2185/**
2186 * amdgpu_device_enable_virtual_display - enable virtual display feature
2187 *
2188 * @adev: amdgpu_device pointer
2189 *
2190 * Enabled the virtual display feature if the user has enabled it via
2191 * the module parameter virtual_display. This feature provides a virtual
2192 * display hardware on headless boards or in virtualized environments.
2193 * This function parses and validates the configuration string specified by
2194 * the user and configues the virtual display configuration (number of
2195 * virtual connectors, crtcs, etc.) specified.
2196 */
2197static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
2198{
2199 adev->enable_virtual_display = false;
2200
2201 if (amdgpu_virtual_display) {
2202 const char *pci_address_name = pci_name(adev->pdev);
2203 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
2204
2205 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
2206 pciaddstr_tmp = pciaddstr;
2207 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
2208 pciaddname = strsep(&pciaddname_tmp, ",");
2209 if (!strcmp("all", pciaddname)
2210 || !strcmp(pci_address_name, pciaddname)) {
2211 long num_crtc;
2212 int res = -1;
2213
2214 adev->enable_virtual_display = true;
2215
2216 if (pciaddname_tmp)
2217 res = kstrtol(pciaddname_tmp, 10,
2218 &num_crtc);
2219
2220 if (!res) {
2221 if (num_crtc < 1)
2222 num_crtc = 1;
2223 if (num_crtc > 6)
2224 num_crtc = 6;
2225 adev->mode_info.num_crtc = num_crtc;
2226 } else {
2227 adev->mode_info.num_crtc = 1;
2228 }
2229 break;
2230 }
2231 }
2232
2233 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
2234 amdgpu_virtual_display, pci_address_name,
2235 adev->enable_virtual_display, adev->mode_info.num_crtc);
2236
2237 kfree(pciaddstr);
2238 }
2239}
2240
2241void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev)
2242{
2243 if (amdgpu_sriov_vf(adev) && !adev->enable_virtual_display) {
2244 adev->mode_info.num_crtc = 1;
2245 adev->enable_virtual_display = true;
2246 DRM_INFO("virtual_display:%d, num_crtc:%d\n",
2247 adev->enable_virtual_display, adev->mode_info.num_crtc);
2248 }
2249}
2250
2251/**
2252 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
2253 *
2254 * @adev: amdgpu_device pointer
2255 *
2256 * Parses the asic configuration parameters specified in the gpu info
2257 * firmware and makes them availale to the driver for use in configuring
2258 * the asic.
2259 * Returns 0 on success, -EINVAL on failure.
2260 */
2261static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
2262{
2263 const char *chip_name;
2264 char fw_name[40];
2265 int err;
2266 const struct gpu_info_firmware_header_v1_0 *hdr;
2267
2268 adev->firmware.gpu_info_fw = NULL;
2269
2270 if (adev->mman.discovery_bin)
2271 return 0;
2272
2273 switch (adev->asic_type) {
2274 default:
2275 return 0;
2276 case CHIP_VEGA10:
2277 chip_name = "vega10";
2278 break;
2279 case CHIP_VEGA12:
2280 chip_name = "vega12";
2281 break;
2282 case CHIP_RAVEN:
2283 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
2284 chip_name = "raven2";
2285 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
2286 chip_name = "picasso";
2287 else
2288 chip_name = "raven";
2289 break;
2290 case CHIP_ARCTURUS:
2291 chip_name = "arcturus";
2292 break;
2293 case CHIP_NAVI12:
2294 chip_name = "navi12";
2295 break;
2296 }
2297
2298 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
2299 err = amdgpu_ucode_request(adev, &adev->firmware.gpu_info_fw, fw_name);
2300 if (err) {
2301 dev_err(adev->dev,
2302 "Failed to get gpu_info firmware \"%s\"\n",
2303 fw_name);
2304 goto out;
2305 }
2306
2307 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
2308 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
2309
2310 switch (hdr->version_major) {
2311 case 1:
2312 {
2313 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
2314 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
2315 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2316
2317 /*
2318 * Should be droped when DAL no longer needs it.
2319 */
2320 if (adev->asic_type == CHIP_NAVI12)
2321 goto parse_soc_bounding_box;
2322
2323 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
2324 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
2325 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
2326 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
2327 adev->gfx.config.max_texture_channel_caches =
2328 le32_to_cpu(gpu_info_fw->gc_num_tccs);
2329 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
2330 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
2331 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
2332 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
2333 adev->gfx.config.double_offchip_lds_buf =
2334 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
2335 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
2336 adev->gfx.cu_info.max_waves_per_simd =
2337 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
2338 adev->gfx.cu_info.max_scratch_slots_per_cu =
2339 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
2340 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
2341 if (hdr->version_minor >= 1) {
2342 const struct gpu_info_firmware_v1_1 *gpu_info_fw =
2343 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
2344 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2345 adev->gfx.config.num_sc_per_sh =
2346 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
2347 adev->gfx.config.num_packer_per_sc =
2348 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
2349 }
2350
2351parse_soc_bounding_box:
2352 /*
2353 * soc bounding box info is not integrated in disocovery table,
2354 * we always need to parse it from gpu info firmware if needed.
2355 */
2356 if (hdr->version_minor == 2) {
2357 const struct gpu_info_firmware_v1_2 *gpu_info_fw =
2358 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
2359 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2360 adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
2361 }
2362 break;
2363 }
2364 default:
2365 dev_err(adev->dev,
2366 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
2367 err = -EINVAL;
2368 goto out;
2369 }
2370out:
2371 return err;
2372}
2373
2374/**
2375 * amdgpu_device_ip_early_init - run early init for hardware IPs
2376 *
2377 * @adev: amdgpu_device pointer
2378 *
2379 * Early initialization pass for hardware IPs. The hardware IPs that make
2380 * up each asic are discovered each IP's early_init callback is run. This
2381 * is the first stage in initializing the asic.
2382 * Returns 0 on success, negative error code on failure.
2383 */
2384static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
2385{
2386 struct pci_dev *parent;
2387 int i, r;
2388 bool total;
2389
2390 amdgpu_device_enable_virtual_display(adev);
2391
2392 if (amdgpu_sriov_vf(adev)) {
2393 r = amdgpu_virt_request_full_gpu(adev, true);
2394 if (r)
2395 return r;
2396 }
2397
2398 switch (adev->asic_type) {
2399#ifdef CONFIG_DRM_AMDGPU_SI
2400 case CHIP_VERDE:
2401 case CHIP_TAHITI:
2402 case CHIP_PITCAIRN:
2403 case CHIP_OLAND:
2404 case CHIP_HAINAN:
2405 adev->family = AMDGPU_FAMILY_SI;
2406 r = si_set_ip_blocks(adev);
2407 if (r)
2408 return r;
2409 break;
2410#endif
2411#ifdef CONFIG_DRM_AMDGPU_CIK
2412 case CHIP_BONAIRE:
2413 case CHIP_HAWAII:
2414 case CHIP_KAVERI:
2415 case CHIP_KABINI:
2416 case CHIP_MULLINS:
2417 if (adev->flags & AMD_IS_APU)
2418 adev->family = AMDGPU_FAMILY_KV;
2419 else
2420 adev->family = AMDGPU_FAMILY_CI;
2421
2422 r = cik_set_ip_blocks(adev);
2423 if (r)
2424 return r;
2425 break;
2426#endif
2427 case CHIP_TOPAZ:
2428 case CHIP_TONGA:
2429 case CHIP_FIJI:
2430 case CHIP_POLARIS10:
2431 case CHIP_POLARIS11:
2432 case CHIP_POLARIS12:
2433 case CHIP_VEGAM:
2434 case CHIP_CARRIZO:
2435 case CHIP_STONEY:
2436 if (adev->flags & AMD_IS_APU)
2437 adev->family = AMDGPU_FAMILY_CZ;
2438 else
2439 adev->family = AMDGPU_FAMILY_VI;
2440
2441 r = vi_set_ip_blocks(adev);
2442 if (r)
2443 return r;
2444 break;
2445 default:
2446 r = amdgpu_discovery_set_ip_blocks(adev);
2447 if (r)
2448 return r;
2449 break;
2450 }
2451
2452 if (amdgpu_has_atpx() &&
2453 (amdgpu_is_atpx_hybrid() ||
2454 amdgpu_has_atpx_dgpu_power_cntl()) &&
2455 ((adev->flags & AMD_IS_APU) == 0) &&
2456 !dev_is_removable(&adev->pdev->dev))
2457 adev->flags |= AMD_IS_PX;
2458
2459 if (!(adev->flags & AMD_IS_APU)) {
2460 parent = pcie_find_root_port(adev->pdev);
2461 adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
2462 }
2463
2464
2465 adev->pm.pp_feature = amdgpu_pp_feature_mask;
2466 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
2467 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2468 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
2469 adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;
2470 if (!amdgpu_device_pcie_dynamic_switching_supported(adev))
2471 adev->pm.pp_feature &= ~PP_PCIE_DPM_MASK;
2472
2473 total = true;
2474 for (i = 0; i < adev->num_ip_blocks; i++) {
2475 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
2476 DRM_WARN("disabled ip block: %d <%s>\n",
2477 i, adev->ip_blocks[i].version->funcs->name);
2478 adev->ip_blocks[i].status.valid = false;
2479 } else {
2480 if (adev->ip_blocks[i].version->funcs->early_init) {
2481 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
2482 if (r == -ENOENT) {
2483 adev->ip_blocks[i].status.valid = false;
2484 } else if (r) {
2485 DRM_ERROR("early_init of IP block <%s> failed %d\n",
2486 adev->ip_blocks[i].version->funcs->name, r);
2487 total = false;
2488 } else {
2489 adev->ip_blocks[i].status.valid = true;
2490 }
2491 } else {
2492 adev->ip_blocks[i].status.valid = true;
2493 }
2494 }
2495 /* get the vbios after the asic_funcs are set up */
2496 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2497 r = amdgpu_device_parse_gpu_info_fw(adev);
2498 if (r)
2499 return r;
2500
2501 /* Read BIOS */
2502 if (amdgpu_device_read_bios(adev)) {
2503 if (!amdgpu_get_bios(adev))
2504 return -EINVAL;
2505
2506 r = amdgpu_atombios_init(adev);
2507 if (r) {
2508 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2509 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2510 return r;
2511 }
2512 }
2513
2514 /*get pf2vf msg info at it's earliest time*/
2515 if (amdgpu_sriov_vf(adev))
2516 amdgpu_virt_init_data_exchange(adev);
2517
2518 }
2519 }
2520 if (!total)
2521 return -ENODEV;
2522
2523 amdgpu_amdkfd_device_probe(adev);
2524 adev->cg_flags &= amdgpu_cg_mask;
2525 adev->pg_flags &= amdgpu_pg_mask;
2526
2527 return 0;
2528}
2529
2530static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
2531{
2532 int i, r;
2533
2534 for (i = 0; i < adev->num_ip_blocks; i++) {
2535 if (!adev->ip_blocks[i].status.sw)
2536 continue;
2537 if (adev->ip_blocks[i].status.hw)
2538 continue;
2539 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2540 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
2541 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2542 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2543 if (r) {
2544 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2545 adev->ip_blocks[i].version->funcs->name, r);
2546 return r;
2547 }
2548 adev->ip_blocks[i].status.hw = true;
2549 }
2550 }
2551
2552 return 0;
2553}
2554
2555static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
2556{
2557 int i, r;
2558
2559 for (i = 0; i < adev->num_ip_blocks; i++) {
2560 if (!adev->ip_blocks[i].status.sw)
2561 continue;
2562 if (adev->ip_blocks[i].status.hw)
2563 continue;
2564 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2565 if (r) {
2566 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2567 adev->ip_blocks[i].version->funcs->name, r);
2568 return r;
2569 }
2570 adev->ip_blocks[i].status.hw = true;
2571 }
2572
2573 return 0;
2574}
2575
2576static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
2577{
2578 int r = 0;
2579 int i;
2580 uint32_t smu_version;
2581
2582 if (adev->asic_type >= CHIP_VEGA10) {
2583 for (i = 0; i < adev->num_ip_blocks; i++) {
2584 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
2585 continue;
2586
2587 if (!adev->ip_blocks[i].status.sw)
2588 continue;
2589
2590 /* no need to do the fw loading again if already done*/
2591 if (adev->ip_blocks[i].status.hw == true)
2592 break;
2593
2594 if (amdgpu_in_reset(adev) || adev->in_suspend) {
2595 r = adev->ip_blocks[i].version->funcs->resume(adev);
2596 if (r) {
2597 DRM_ERROR("resume of IP block <%s> failed %d\n",
2598 adev->ip_blocks[i].version->funcs->name, r);
2599 return r;
2600 }
2601 } else {
2602 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2603 if (r) {
2604 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2605 adev->ip_blocks[i].version->funcs->name, r);
2606 return r;
2607 }
2608 }
2609
2610 adev->ip_blocks[i].status.hw = true;
2611 break;
2612 }
2613 }
2614
2615 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA)
2616 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
2617
2618 return r;
2619}
2620
2621static int amdgpu_device_init_schedulers(struct amdgpu_device *adev)
2622{
2623 long timeout;
2624 int r, i;
2625
2626 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2627 struct amdgpu_ring *ring = adev->rings[i];
2628
2629 /* No need to setup the GPU scheduler for rings that don't need it */
2630 if (!ring || ring->no_scheduler)
2631 continue;
2632
2633 switch (ring->funcs->type) {
2634 case AMDGPU_RING_TYPE_GFX:
2635 timeout = adev->gfx_timeout;
2636 break;
2637 case AMDGPU_RING_TYPE_COMPUTE:
2638 timeout = adev->compute_timeout;
2639 break;
2640 case AMDGPU_RING_TYPE_SDMA:
2641 timeout = adev->sdma_timeout;
2642 break;
2643 default:
2644 timeout = adev->video_timeout;
2645 break;
2646 }
2647
2648 r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, NULL,
2649 DRM_SCHED_PRIORITY_COUNT,
2650 ring->num_hw_submission, 0,
2651 timeout, adev->reset_domain->wq,
2652 ring->sched_score, ring->name,
2653 adev->dev);
2654 if (r) {
2655 DRM_ERROR("Failed to create scheduler on ring %s.\n",
2656 ring->name);
2657 return r;
2658 }
2659 r = amdgpu_uvd_entity_init(adev, ring);
2660 if (r) {
2661 DRM_ERROR("Failed to create UVD scheduling entity on ring %s.\n",
2662 ring->name);
2663 return r;
2664 }
2665 r = amdgpu_vce_entity_init(adev, ring);
2666 if (r) {
2667 DRM_ERROR("Failed to create VCE scheduling entity on ring %s.\n",
2668 ring->name);
2669 return r;
2670 }
2671 }
2672
2673 amdgpu_xcp_update_partition_sched_list(adev);
2674
2675 return 0;
2676}
2677
2678
2679/**
2680 * amdgpu_device_ip_init - run init for hardware IPs
2681 *
2682 * @adev: amdgpu_device pointer
2683 *
2684 * Main initialization pass for hardware IPs. The list of all the hardware
2685 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
2686 * are run. sw_init initializes the software state associated with each IP
2687 * and hw_init initializes the hardware associated with each IP.
2688 * Returns 0 on success, negative error code on failure.
2689 */
2690static int amdgpu_device_ip_init(struct amdgpu_device *adev)
2691{
2692 int i, r;
2693
2694 r = amdgpu_ras_init(adev);
2695 if (r)
2696 return r;
2697
2698 for (i = 0; i < adev->num_ip_blocks; i++) {
2699 if (!adev->ip_blocks[i].status.valid)
2700 continue;
2701 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
2702 if (r) {
2703 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
2704 adev->ip_blocks[i].version->funcs->name, r);
2705 goto init_failed;
2706 }
2707 adev->ip_blocks[i].status.sw = true;
2708
2709 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2710 /* need to do common hw init early so everything is set up for gmc */
2711 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2712 if (r) {
2713 DRM_ERROR("hw_init %d failed %d\n", i, r);
2714 goto init_failed;
2715 }
2716 adev->ip_blocks[i].status.hw = true;
2717 } else if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2718 /* need to do gmc hw init early so we can allocate gpu mem */
2719 /* Try to reserve bad pages early */
2720 if (amdgpu_sriov_vf(adev))
2721 amdgpu_virt_exchange_data(adev);
2722
2723 r = amdgpu_device_mem_scratch_init(adev);
2724 if (r) {
2725 DRM_ERROR("amdgpu_mem_scratch_init failed %d\n", r);
2726 goto init_failed;
2727 }
2728 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2729 if (r) {
2730 DRM_ERROR("hw_init %d failed %d\n", i, r);
2731 goto init_failed;
2732 }
2733 r = amdgpu_device_wb_init(adev);
2734 if (r) {
2735 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
2736 goto init_failed;
2737 }
2738 adev->ip_blocks[i].status.hw = true;
2739
2740 /* right after GMC hw init, we create CSA */
2741 if (adev->gfx.mcbp) {
2742 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
2743 AMDGPU_GEM_DOMAIN_VRAM |
2744 AMDGPU_GEM_DOMAIN_GTT,
2745 AMDGPU_CSA_SIZE);
2746 if (r) {
2747 DRM_ERROR("allocate CSA failed %d\n", r);
2748 goto init_failed;
2749 }
2750 }
2751
2752 r = amdgpu_seq64_init(adev);
2753 if (r) {
2754 DRM_ERROR("allocate seq64 failed %d\n", r);
2755 goto init_failed;
2756 }
2757 }
2758 }
2759
2760 if (amdgpu_sriov_vf(adev))
2761 amdgpu_virt_init_data_exchange(adev);
2762
2763 r = amdgpu_ib_pool_init(adev);
2764 if (r) {
2765 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2766 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2767 goto init_failed;
2768 }
2769
2770 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
2771 if (r)
2772 goto init_failed;
2773
2774 r = amdgpu_device_ip_hw_init_phase1(adev);
2775 if (r)
2776 goto init_failed;
2777
2778 r = amdgpu_device_fw_loading(adev);
2779 if (r)
2780 goto init_failed;
2781
2782 r = amdgpu_device_ip_hw_init_phase2(adev);
2783 if (r)
2784 goto init_failed;
2785
2786 /*
2787 * retired pages will be loaded from eeprom and reserved here,
2788 * it should be called after amdgpu_device_ip_hw_init_phase2 since
2789 * for some ASICs the RAS EEPROM code relies on SMU fully functioning
2790 * for I2C communication which only true at this point.
2791 *
2792 * amdgpu_ras_recovery_init may fail, but the upper only cares the
2793 * failure from bad gpu situation and stop amdgpu init process
2794 * accordingly. For other failed cases, it will still release all
2795 * the resource and print error message, rather than returning one
2796 * negative value to upper level.
2797 *
2798 * Note: theoretically, this should be called before all vram allocations
2799 * to protect retired page from abusing
2800 */
2801 r = amdgpu_ras_recovery_init(adev);
2802 if (r)
2803 goto init_failed;
2804
2805 /**
2806 * In case of XGMI grab extra reference for reset domain for this device
2807 */
2808 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2809 if (amdgpu_xgmi_add_device(adev) == 0) {
2810 if (!amdgpu_sriov_vf(adev)) {
2811 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2812
2813 if (WARN_ON(!hive)) {
2814 r = -ENOENT;
2815 goto init_failed;
2816 }
2817
2818 if (!hive->reset_domain ||
2819 !amdgpu_reset_get_reset_domain(hive->reset_domain)) {
2820 r = -ENOENT;
2821 amdgpu_put_xgmi_hive(hive);
2822 goto init_failed;
2823 }
2824
2825 /* Drop the early temporary reset domain we created for device */
2826 amdgpu_reset_put_reset_domain(adev->reset_domain);
2827 adev->reset_domain = hive->reset_domain;
2828 amdgpu_put_xgmi_hive(hive);
2829 }
2830 }
2831 }
2832
2833 r = amdgpu_device_init_schedulers(adev);
2834 if (r)
2835 goto init_failed;
2836
2837 if (adev->mman.buffer_funcs_ring->sched.ready)
2838 amdgpu_ttm_set_buffer_funcs_status(adev, true);
2839
2840 /* Don't init kfd if whole hive need to be reset during init */
2841 if (!adev->gmc.xgmi.pending_reset) {
2842 kgd2kfd_init_zone_device(adev);
2843 amdgpu_amdkfd_device_init(adev);
2844 }
2845
2846 amdgpu_fru_get_product_info(adev);
2847
2848init_failed:
2849
2850 return r;
2851}
2852
2853/**
2854 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
2855 *
2856 * @adev: amdgpu_device pointer
2857 *
2858 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
2859 * this function before a GPU reset. If the value is retained after a
2860 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
2861 */
2862static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
2863{
2864 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
2865}
2866
2867/**
2868 * amdgpu_device_check_vram_lost - check if vram is valid
2869 *
2870 * @adev: amdgpu_device pointer
2871 *
2872 * Checks the reset magic value written to the gart pointer in VRAM.
2873 * The driver calls this after a GPU reset to see if the contents of
2874 * VRAM is lost or now.
2875 * returns true if vram is lost, false if not.
2876 */
2877static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
2878{
2879 if (memcmp(adev->gart.ptr, adev->reset_magic,
2880 AMDGPU_RESET_MAGIC_NUM))
2881 return true;
2882
2883 if (!amdgpu_in_reset(adev))
2884 return false;
2885
2886 /*
2887 * For all ASICs with baco/mode1 reset, the VRAM is
2888 * always assumed to be lost.
2889 */
2890 switch (amdgpu_asic_reset_method(adev)) {
2891 case AMD_RESET_METHOD_BACO:
2892 case AMD_RESET_METHOD_MODE1:
2893 return true;
2894 default:
2895 return false;
2896 }
2897}
2898
2899/**
2900 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
2901 *
2902 * @adev: amdgpu_device pointer
2903 * @state: clockgating state (gate or ungate)
2904 *
2905 * The list of all the hardware IPs that make up the asic is walked and the
2906 * set_clockgating_state callbacks are run.
2907 * Late initialization pass enabling clockgating for hardware IPs.
2908 * Fini or suspend, pass disabling clockgating for hardware IPs.
2909 * Returns 0 on success, negative error code on failure.
2910 */
2911
2912int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
2913 enum amd_clockgating_state state)
2914{
2915 int i, j, r;
2916
2917 if (amdgpu_emu_mode == 1)
2918 return 0;
2919
2920 for (j = 0; j < adev->num_ip_blocks; j++) {
2921 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2922 if (!adev->ip_blocks[i].status.late_initialized)
2923 continue;
2924 /* skip CG for GFX, SDMA on S0ix */
2925 if (adev->in_s0ix &&
2926 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
2927 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
2928 continue;
2929 /* skip CG for VCE/UVD, it's handled specially */
2930 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2931 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2932 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2933 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2934 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
2935 /* enable clockgating to save power */
2936 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
2937 state);
2938 if (r) {
2939 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
2940 adev->ip_blocks[i].version->funcs->name, r);
2941 return r;
2942 }
2943 }
2944 }
2945
2946 return 0;
2947}
2948
2949int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
2950 enum amd_powergating_state state)
2951{
2952 int i, j, r;
2953
2954 if (amdgpu_emu_mode == 1)
2955 return 0;
2956
2957 for (j = 0; j < adev->num_ip_blocks; j++) {
2958 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2959 if (!adev->ip_blocks[i].status.late_initialized)
2960 continue;
2961 /* skip PG for GFX, SDMA on S0ix */
2962 if (adev->in_s0ix &&
2963 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
2964 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
2965 continue;
2966 /* skip CG for VCE/UVD, it's handled specially */
2967 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2968 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2969 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2970 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2971 adev->ip_blocks[i].version->funcs->set_powergating_state) {
2972 /* enable powergating to save power */
2973 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
2974 state);
2975 if (r) {
2976 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
2977 adev->ip_blocks[i].version->funcs->name, r);
2978 return r;
2979 }
2980 }
2981 }
2982 return 0;
2983}
2984
2985static int amdgpu_device_enable_mgpu_fan_boost(void)
2986{
2987 struct amdgpu_gpu_instance *gpu_ins;
2988 struct amdgpu_device *adev;
2989 int i, ret = 0;
2990
2991 mutex_lock(&mgpu_info.mutex);
2992
2993 /*
2994 * MGPU fan boost feature should be enabled
2995 * only when there are two or more dGPUs in
2996 * the system
2997 */
2998 if (mgpu_info.num_dgpu < 2)
2999 goto out;
3000
3001 for (i = 0; i < mgpu_info.num_dgpu; i++) {
3002 gpu_ins = &(mgpu_info.gpu_ins[i]);
3003 adev = gpu_ins->adev;
3004 if (!(adev->flags & AMD_IS_APU) &&
3005 !gpu_ins->mgpu_fan_enabled) {
3006 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
3007 if (ret)
3008 break;
3009
3010 gpu_ins->mgpu_fan_enabled = 1;
3011 }
3012 }
3013
3014out:
3015 mutex_unlock(&mgpu_info.mutex);
3016
3017 return ret;
3018}
3019
3020/**
3021 * amdgpu_device_ip_late_init - run late init for hardware IPs
3022 *
3023 * @adev: amdgpu_device pointer
3024 *
3025 * Late initialization pass for hardware IPs. The list of all the hardware
3026 * IPs that make up the asic is walked and the late_init callbacks are run.
3027 * late_init covers any special initialization that an IP requires
3028 * after all of the have been initialized or something that needs to happen
3029 * late in the init process.
3030 * Returns 0 on success, negative error code on failure.
3031 */
3032static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
3033{
3034 struct amdgpu_gpu_instance *gpu_instance;
3035 int i = 0, r;
3036
3037 for (i = 0; i < adev->num_ip_blocks; i++) {
3038 if (!adev->ip_blocks[i].status.hw)
3039 continue;
3040 if (adev->ip_blocks[i].version->funcs->late_init) {
3041 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
3042 if (r) {
3043 DRM_ERROR("late_init of IP block <%s> failed %d\n",
3044 adev->ip_blocks[i].version->funcs->name, r);
3045 return r;
3046 }
3047 }
3048 adev->ip_blocks[i].status.late_initialized = true;
3049 }
3050
3051 r = amdgpu_ras_late_init(adev);
3052 if (r) {
3053 DRM_ERROR("amdgpu_ras_late_init failed %d", r);
3054 return r;
3055 }
3056
3057 amdgpu_ras_set_error_query_ready(adev, true);
3058
3059 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
3060 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
3061
3062 amdgpu_device_fill_reset_magic(adev);
3063
3064 r = amdgpu_device_enable_mgpu_fan_boost();
3065 if (r)
3066 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
3067
3068 /* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */
3069 if (amdgpu_passthrough(adev) &&
3070 ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1) ||
3071 adev->asic_type == CHIP_ALDEBARAN))
3072 amdgpu_dpm_handle_passthrough_sbr(adev, true);
3073
3074 if (adev->gmc.xgmi.num_physical_nodes > 1) {
3075 mutex_lock(&mgpu_info.mutex);
3076
3077 /*
3078 * Reset device p-state to low as this was booted with high.
3079 *
3080 * This should be performed only after all devices from the same
3081 * hive get initialized.
3082 *
3083 * However, it's unknown how many device in the hive in advance.
3084 * As this is counted one by one during devices initializations.
3085 *
3086 * So, we wait for all XGMI interlinked devices initialized.
3087 * This may bring some delays as those devices may come from
3088 * different hives. But that should be OK.
3089 */
3090 if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
3091 for (i = 0; i < mgpu_info.num_gpu; i++) {
3092 gpu_instance = &(mgpu_info.gpu_ins[i]);
3093 if (gpu_instance->adev->flags & AMD_IS_APU)
3094 continue;
3095
3096 r = amdgpu_xgmi_set_pstate(gpu_instance->adev,
3097 AMDGPU_XGMI_PSTATE_MIN);
3098 if (r) {
3099 DRM_ERROR("pstate setting failed (%d).\n", r);
3100 break;
3101 }
3102 }
3103 }
3104
3105 mutex_unlock(&mgpu_info.mutex);
3106 }
3107
3108 return 0;
3109}
3110
3111/**
3112 * amdgpu_device_smu_fini_early - smu hw_fini wrapper
3113 *
3114 * @adev: amdgpu_device pointer
3115 *
3116 * For ASICs need to disable SMC first
3117 */
3118static void amdgpu_device_smu_fini_early(struct amdgpu_device *adev)
3119{
3120 int i, r;
3121
3122 if (amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(9, 0, 0))
3123 return;
3124
3125 for (i = 0; i < adev->num_ip_blocks; i++) {
3126 if (!adev->ip_blocks[i].status.hw)
3127 continue;
3128 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3129 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
3130 /* XXX handle errors */
3131 if (r) {
3132 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
3133 adev->ip_blocks[i].version->funcs->name, r);
3134 }
3135 adev->ip_blocks[i].status.hw = false;
3136 break;
3137 }
3138 }
3139}
3140
3141static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev)
3142{
3143 int i, r;
3144
3145 for (i = 0; i < adev->num_ip_blocks; i++) {
3146 if (!adev->ip_blocks[i].version->funcs->early_fini)
3147 continue;
3148
3149 r = adev->ip_blocks[i].version->funcs->early_fini((void *)adev);
3150 if (r) {
3151 DRM_DEBUG("early_fini of IP block <%s> failed %d\n",
3152 adev->ip_blocks[i].version->funcs->name, r);
3153 }
3154 }
3155
3156 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
3157 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
3158
3159 amdgpu_amdkfd_suspend(adev, false);
3160
3161 /* Workaroud for ASICs need to disable SMC first */
3162 amdgpu_device_smu_fini_early(adev);
3163
3164 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3165 if (!adev->ip_blocks[i].status.hw)
3166 continue;
3167
3168 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
3169 /* XXX handle errors */
3170 if (r) {
3171 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
3172 adev->ip_blocks[i].version->funcs->name, r);
3173 }
3174
3175 adev->ip_blocks[i].status.hw = false;
3176 }
3177
3178 if (amdgpu_sriov_vf(adev)) {
3179 if (amdgpu_virt_release_full_gpu(adev, false))
3180 DRM_ERROR("failed to release exclusive mode on fini\n");
3181 }
3182
3183 return 0;
3184}
3185
3186/**
3187 * amdgpu_device_ip_fini - run fini for hardware IPs
3188 *
3189 * @adev: amdgpu_device pointer
3190 *
3191 * Main teardown pass for hardware IPs. The list of all the hardware
3192 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
3193 * are run. hw_fini tears down the hardware associated with each IP
3194 * and sw_fini tears down any software state associated with each IP.
3195 * Returns 0 on success, negative error code on failure.
3196 */
3197static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
3198{
3199 int i, r;
3200
3201 if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
3202 amdgpu_virt_release_ras_err_handler_data(adev);
3203
3204 if (adev->gmc.xgmi.num_physical_nodes > 1)
3205 amdgpu_xgmi_remove_device(adev);
3206
3207 amdgpu_amdkfd_device_fini_sw(adev);
3208
3209 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3210 if (!adev->ip_blocks[i].status.sw)
3211 continue;
3212
3213 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
3214 amdgpu_ucode_free_bo(adev);
3215 amdgpu_free_static_csa(&adev->virt.csa_obj);
3216 amdgpu_device_wb_fini(adev);
3217 amdgpu_device_mem_scratch_fini(adev);
3218 amdgpu_ib_pool_fini(adev);
3219 amdgpu_seq64_fini(adev);
3220 }
3221
3222 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
3223 /* XXX handle errors */
3224 if (r) {
3225 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
3226 adev->ip_blocks[i].version->funcs->name, r);
3227 }
3228 adev->ip_blocks[i].status.sw = false;
3229 adev->ip_blocks[i].status.valid = false;
3230 }
3231
3232 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3233 if (!adev->ip_blocks[i].status.late_initialized)
3234 continue;
3235 if (adev->ip_blocks[i].version->funcs->late_fini)
3236 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
3237 adev->ip_blocks[i].status.late_initialized = false;
3238 }
3239
3240 amdgpu_ras_fini(adev);
3241
3242 return 0;
3243}
3244
3245/**
3246 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
3247 *
3248 * @work: work_struct.
3249 */
3250static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
3251{
3252 struct amdgpu_device *adev =
3253 container_of(work, struct amdgpu_device, delayed_init_work.work);
3254 int r;
3255
3256 r = amdgpu_ib_ring_tests(adev);
3257 if (r)
3258 DRM_ERROR("ib ring test failed (%d).\n", r);
3259}
3260
3261static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
3262{
3263 struct amdgpu_device *adev =
3264 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
3265
3266 WARN_ON_ONCE(adev->gfx.gfx_off_state);
3267 WARN_ON_ONCE(adev->gfx.gfx_off_req_count);
3268
3269 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
3270 adev->gfx.gfx_off_state = true;
3271}
3272
3273/**
3274 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
3275 *
3276 * @adev: amdgpu_device pointer
3277 *
3278 * Main suspend function for hardware IPs. The list of all the hardware
3279 * IPs that make up the asic is walked, clockgating is disabled and the
3280 * suspend callbacks are run. suspend puts the hardware and software state
3281 * in each IP into a state suitable for suspend.
3282 * Returns 0 on success, negative error code on failure.
3283 */
3284static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
3285{
3286 int i, r;
3287
3288 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
3289 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
3290
3291 /*
3292 * Per PMFW team's suggestion, driver needs to handle gfxoff
3293 * and df cstate features disablement for gpu reset(e.g. Mode1Reset)
3294 * scenario. Add the missing df cstate disablement here.
3295 */
3296 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
3297 dev_warn(adev->dev, "Failed to disallow df cstate");
3298
3299 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3300 if (!adev->ip_blocks[i].status.valid)
3301 continue;
3302
3303 /* displays are handled separately */
3304 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE)
3305 continue;
3306
3307 /* XXX handle errors */
3308 r = adev->ip_blocks[i].version->funcs->suspend(adev);
3309 /* XXX handle errors */
3310 if (r) {
3311 DRM_ERROR("suspend of IP block <%s> failed %d\n",
3312 adev->ip_blocks[i].version->funcs->name, r);
3313 return r;
3314 }
3315
3316 adev->ip_blocks[i].status.hw = false;
3317 }
3318
3319 return 0;
3320}
3321
3322/**
3323 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
3324 *
3325 * @adev: amdgpu_device pointer
3326 *
3327 * Main suspend function for hardware IPs. The list of all the hardware
3328 * IPs that make up the asic is walked, clockgating is disabled and the
3329 * suspend callbacks are run. suspend puts the hardware and software state
3330 * in each IP into a state suitable for suspend.
3331 * Returns 0 on success, negative error code on failure.
3332 */
3333static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
3334{
3335 int i, r;
3336
3337 if (adev->in_s0ix)
3338 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D3Entry);
3339
3340 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3341 if (!adev->ip_blocks[i].status.valid)
3342 continue;
3343 /* displays are handled in phase1 */
3344 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
3345 continue;
3346 /* PSP lost connection when err_event_athub occurs */
3347 if (amdgpu_ras_intr_triggered() &&
3348 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3349 adev->ip_blocks[i].status.hw = false;
3350 continue;
3351 }
3352
3353 /* skip unnecessary suspend if we do not initialize them yet */
3354 if (adev->gmc.xgmi.pending_reset &&
3355 !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3356 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC ||
3357 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3358 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) {
3359 adev->ip_blocks[i].status.hw = false;
3360 continue;
3361 }
3362
3363 /* skip suspend of gfx/mes and psp for S0ix
3364 * gfx is in gfxoff state, so on resume it will exit gfxoff just
3365 * like at runtime. PSP is also part of the always on hardware
3366 * so no need to suspend it.
3367 */
3368 if (adev->in_s0ix &&
3369 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP ||
3370 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
3371 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_MES))
3372 continue;
3373
3374 /* SDMA 5.x+ is part of GFX power domain so it's covered by GFXOFF */
3375 if (adev->in_s0ix &&
3376 (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >=
3377 IP_VERSION(5, 0, 0)) &&
3378 (adev->ip_blocks[i].version->type ==
3379 AMD_IP_BLOCK_TYPE_SDMA))
3380 continue;
3381
3382 /* Once swPSP provides the IMU, RLC FW binaries to TOS during cold-boot.
3383 * These are in TMR, hence are expected to be reused by PSP-TOS to reload
3384 * from this location and RLC Autoload automatically also gets loaded
3385 * from here based on PMFW -> PSP message during re-init sequence.
3386 * Therefore, the psp suspend & resume should be skipped to avoid destroy
3387 * the TMR and reload FWs again for IMU enabled APU ASICs.
3388 */
3389 if (amdgpu_in_reset(adev) &&
3390 (adev->flags & AMD_IS_APU) && adev->gfx.imu.funcs &&
3391 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3392 continue;
3393
3394 /* XXX handle errors */
3395 r = adev->ip_blocks[i].version->funcs->suspend(adev);
3396 /* XXX handle errors */
3397 if (r) {
3398 DRM_ERROR("suspend of IP block <%s> failed %d\n",
3399 adev->ip_blocks[i].version->funcs->name, r);
3400 }
3401 adev->ip_blocks[i].status.hw = false;
3402 /* handle putting the SMC in the appropriate state */
3403 if (!amdgpu_sriov_vf(adev)) {
3404 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3405 r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);
3406 if (r) {
3407 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
3408 adev->mp1_state, r);
3409 return r;
3410 }
3411 }
3412 }
3413 }
3414
3415 return 0;
3416}
3417
3418/**
3419 * amdgpu_device_ip_suspend - run suspend for hardware IPs
3420 *
3421 * @adev: amdgpu_device pointer
3422 *
3423 * Main suspend function for hardware IPs. The list of all the hardware
3424 * IPs that make up the asic is walked, clockgating is disabled and the
3425 * suspend callbacks are run. suspend puts the hardware and software state
3426 * in each IP into a state suitable for suspend.
3427 * Returns 0 on success, negative error code on failure.
3428 */
3429int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
3430{
3431 int r;
3432
3433 if (amdgpu_sriov_vf(adev)) {
3434 amdgpu_virt_fini_data_exchange(adev);
3435 amdgpu_virt_request_full_gpu(adev, false);
3436 }
3437
3438 amdgpu_ttm_set_buffer_funcs_status(adev, false);
3439
3440 r = amdgpu_device_ip_suspend_phase1(adev);
3441 if (r)
3442 return r;
3443 r = amdgpu_device_ip_suspend_phase2(adev);
3444
3445 if (amdgpu_sriov_vf(adev))
3446 amdgpu_virt_release_full_gpu(adev, false);
3447
3448 return r;
3449}
3450
3451static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
3452{
3453 int i, r;
3454
3455 static enum amd_ip_block_type ip_order[] = {
3456 AMD_IP_BLOCK_TYPE_COMMON,
3457 AMD_IP_BLOCK_TYPE_GMC,
3458 AMD_IP_BLOCK_TYPE_PSP,
3459 AMD_IP_BLOCK_TYPE_IH,
3460 };
3461
3462 for (i = 0; i < adev->num_ip_blocks; i++) {
3463 int j;
3464 struct amdgpu_ip_block *block;
3465
3466 block = &adev->ip_blocks[i];
3467 block->status.hw = false;
3468
3469 for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
3470
3471 if (block->version->type != ip_order[j] ||
3472 !block->status.valid)
3473 continue;
3474
3475 r = block->version->funcs->hw_init(adev);
3476 DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3477 if (r)
3478 return r;
3479 block->status.hw = true;
3480 }
3481 }
3482
3483 return 0;
3484}
3485
3486static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
3487{
3488 int i, r;
3489
3490 static enum amd_ip_block_type ip_order[] = {
3491 AMD_IP_BLOCK_TYPE_SMC,
3492 AMD_IP_BLOCK_TYPE_DCE,
3493 AMD_IP_BLOCK_TYPE_GFX,
3494 AMD_IP_BLOCK_TYPE_SDMA,
3495 AMD_IP_BLOCK_TYPE_MES,
3496 AMD_IP_BLOCK_TYPE_UVD,
3497 AMD_IP_BLOCK_TYPE_VCE,
3498 AMD_IP_BLOCK_TYPE_VCN,
3499 AMD_IP_BLOCK_TYPE_JPEG
3500 };
3501
3502 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
3503 int j;
3504 struct amdgpu_ip_block *block;
3505
3506 for (j = 0; j < adev->num_ip_blocks; j++) {
3507 block = &adev->ip_blocks[j];
3508
3509 if (block->version->type != ip_order[i] ||
3510 !block->status.valid ||
3511 block->status.hw)
3512 continue;
3513
3514 if (block->version->type == AMD_IP_BLOCK_TYPE_SMC)
3515 r = block->version->funcs->resume(adev);
3516 else
3517 r = block->version->funcs->hw_init(adev);
3518
3519 DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3520 if (r)
3521 return r;
3522 block->status.hw = true;
3523 }
3524 }
3525
3526 return 0;
3527}
3528
3529/**
3530 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
3531 *
3532 * @adev: amdgpu_device pointer
3533 *
3534 * First resume function for hardware IPs. The list of all the hardware
3535 * IPs that make up the asic is walked and the resume callbacks are run for
3536 * COMMON, GMC, and IH. resume puts the hardware into a functional state
3537 * after a suspend and updates the software state as necessary. This
3538 * function is also used for restoring the GPU after a GPU reset.
3539 * Returns 0 on success, negative error code on failure.
3540 */
3541static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
3542{
3543 int i, r;
3544
3545 for (i = 0; i < adev->num_ip_blocks; i++) {
3546 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3547 continue;
3548 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3549 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3550 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3551 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP && amdgpu_sriov_vf(adev))) {
3552
3553 r = adev->ip_blocks[i].version->funcs->resume(adev);
3554 if (r) {
3555 DRM_ERROR("resume of IP block <%s> failed %d\n",
3556 adev->ip_blocks[i].version->funcs->name, r);
3557 return r;
3558 }
3559 adev->ip_blocks[i].status.hw = true;
3560 }
3561 }
3562
3563 return 0;
3564}
3565
3566/**
3567 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
3568 *
3569 * @adev: amdgpu_device pointer
3570 *
3571 * First resume function for hardware IPs. The list of all the hardware
3572 * IPs that make up the asic is walked and the resume callbacks are run for
3573 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
3574 * functional state after a suspend and updates the software state as
3575 * necessary. This function is also used for restoring the GPU after a GPU
3576 * reset.
3577 * Returns 0 on success, negative error code on failure.
3578 */
3579static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
3580{
3581 int i, r;
3582
3583 for (i = 0; i < adev->num_ip_blocks; i++) {
3584 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3585 continue;
3586 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3587 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3588 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3589 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3590 continue;
3591 r = adev->ip_blocks[i].version->funcs->resume(adev);
3592 if (r) {
3593 DRM_ERROR("resume of IP block <%s> failed %d\n",
3594 adev->ip_blocks[i].version->funcs->name, r);
3595 return r;
3596 }
3597 adev->ip_blocks[i].status.hw = true;
3598 }
3599
3600 return 0;
3601}
3602
3603/**
3604 * amdgpu_device_ip_resume - run resume for hardware IPs
3605 *
3606 * @adev: amdgpu_device pointer
3607 *
3608 * Main resume function for hardware IPs. The hardware IPs
3609 * are split into two resume functions because they are
3610 * also used in recovering from a GPU reset and some additional
3611 * steps need to be take between them. In this case (S3/S4) they are
3612 * run sequentially.
3613 * Returns 0 on success, negative error code on failure.
3614 */
3615static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
3616{
3617 int r;
3618
3619 r = amdgpu_device_ip_resume_phase1(adev);
3620 if (r)
3621 return r;
3622
3623 r = amdgpu_device_fw_loading(adev);
3624 if (r)
3625 return r;
3626
3627 r = amdgpu_device_ip_resume_phase2(adev);
3628
3629 if (adev->mman.buffer_funcs_ring->sched.ready)
3630 amdgpu_ttm_set_buffer_funcs_status(adev, true);
3631
3632 return r;
3633}
3634
3635/**
3636 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
3637 *
3638 * @adev: amdgpu_device pointer
3639 *
3640 * Query the VBIOS data tables to determine if the board supports SR-IOV.
3641 */
3642static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
3643{
3644 if (amdgpu_sriov_vf(adev)) {
3645 if (adev->is_atom_fw) {
3646 if (amdgpu_atomfirmware_gpu_virtualization_supported(adev))
3647 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3648 } else {
3649 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
3650 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3651 }
3652
3653 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
3654 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
3655 }
3656}
3657
3658/**
3659 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
3660 *
3661 * @asic_type: AMD asic type
3662 *
3663 * Check if there is DC (new modesetting infrastructre) support for an asic.
3664 * returns true if DC has support, false if not.
3665 */
3666bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
3667{
3668 switch (asic_type) {
3669#ifdef CONFIG_DRM_AMDGPU_SI
3670 case CHIP_HAINAN:
3671#endif
3672 case CHIP_TOPAZ:
3673 /* chips with no display hardware */
3674 return false;
3675#if defined(CONFIG_DRM_AMD_DC)
3676 case CHIP_TAHITI:
3677 case CHIP_PITCAIRN:
3678 case CHIP_VERDE:
3679 case CHIP_OLAND:
3680 /*
3681 * We have systems in the wild with these ASICs that require
3682 * LVDS and VGA support which is not supported with DC.
3683 *
3684 * Fallback to the non-DC driver here by default so as not to
3685 * cause regressions.
3686 */
3687#if defined(CONFIG_DRM_AMD_DC_SI)
3688 return amdgpu_dc > 0;
3689#else
3690 return false;
3691#endif
3692 case CHIP_BONAIRE:
3693 case CHIP_KAVERI:
3694 case CHIP_KABINI:
3695 case CHIP_MULLINS:
3696 /*
3697 * We have systems in the wild with these ASICs that require
3698 * VGA support which is not supported with DC.
3699 *
3700 * Fallback to the non-DC driver here by default so as not to
3701 * cause regressions.
3702 */
3703 return amdgpu_dc > 0;
3704 default:
3705 return amdgpu_dc != 0;
3706#else
3707 default:
3708 if (amdgpu_dc > 0)
3709 DRM_INFO_ONCE("Display Core has been requested via kernel parameter but isn't supported by ASIC, ignoring\n");
3710 return false;
3711#endif
3712 }
3713}
3714
3715/**
3716 * amdgpu_device_has_dc_support - check if dc is supported
3717 *
3718 * @adev: amdgpu_device pointer
3719 *
3720 * Returns true for supported, false for not supported
3721 */
3722bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
3723{
3724 if (adev->enable_virtual_display ||
3725 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
3726 return false;
3727
3728 return amdgpu_device_asic_has_dc_support(adev->asic_type);
3729}
3730
3731static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
3732{
3733 struct amdgpu_device *adev =
3734 container_of(__work, struct amdgpu_device, xgmi_reset_work);
3735 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
3736
3737 /* It's a bug to not have a hive within this function */
3738 if (WARN_ON(!hive))
3739 return;
3740
3741 /*
3742 * Use task barrier to synchronize all xgmi reset works across the
3743 * hive. task_barrier_enter and task_barrier_exit will block
3744 * until all the threads running the xgmi reset works reach
3745 * those points. task_barrier_full will do both blocks.
3746 */
3747 if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
3748
3749 task_barrier_enter(&hive->tb);
3750 adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev));
3751
3752 if (adev->asic_reset_res)
3753 goto fail;
3754
3755 task_barrier_exit(&hive->tb);
3756 adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev));
3757
3758 if (adev->asic_reset_res)
3759 goto fail;
3760
3761 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB);
3762 } else {
3763
3764 task_barrier_full(&hive->tb);
3765 adev->asic_reset_res = amdgpu_asic_reset(adev);
3766 }
3767
3768fail:
3769 if (adev->asic_reset_res)
3770 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
3771 adev->asic_reset_res, adev_to_drm(adev)->unique);
3772 amdgpu_put_xgmi_hive(hive);
3773}
3774
3775static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
3776{
3777 char *input = amdgpu_lockup_timeout;
3778 char *timeout_setting = NULL;
3779 int index = 0;
3780 long timeout;
3781 int ret = 0;
3782
3783 /*
3784 * By default timeout for non compute jobs is 10000
3785 * and 60000 for compute jobs.
3786 * In SR-IOV or passthrough mode, timeout for compute
3787 * jobs are 60000 by default.
3788 */
3789 adev->gfx_timeout = msecs_to_jiffies(10000);
3790 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3791 if (amdgpu_sriov_vf(adev))
3792 adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ?
3793 msecs_to_jiffies(60000) : msecs_to_jiffies(10000);
3794 else
3795 adev->compute_timeout = msecs_to_jiffies(60000);
3796
3797 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3798 while ((timeout_setting = strsep(&input, ",")) &&
3799 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3800 ret = kstrtol(timeout_setting, 0, &timeout);
3801 if (ret)
3802 return ret;
3803
3804 if (timeout == 0) {
3805 index++;
3806 continue;
3807 } else if (timeout < 0) {
3808 timeout = MAX_SCHEDULE_TIMEOUT;
3809 dev_warn(adev->dev, "lockup timeout disabled");
3810 add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK);
3811 } else {
3812 timeout = msecs_to_jiffies(timeout);
3813 }
3814
3815 switch (index++) {
3816 case 0:
3817 adev->gfx_timeout = timeout;
3818 break;
3819 case 1:
3820 adev->compute_timeout = timeout;
3821 break;
3822 case 2:
3823 adev->sdma_timeout = timeout;
3824 break;
3825 case 3:
3826 adev->video_timeout = timeout;
3827 break;
3828 default:
3829 break;
3830 }
3831 }
3832 /*
3833 * There is only one value specified and
3834 * it should apply to all non-compute jobs.
3835 */
3836 if (index == 1) {
3837 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3838 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
3839 adev->compute_timeout = adev->gfx_timeout;
3840 }
3841 }
3842
3843 return ret;
3844}
3845
3846/**
3847 * amdgpu_device_check_iommu_direct_map - check if RAM direct mapped to GPU
3848 *
3849 * @adev: amdgpu_device pointer
3850 *
3851 * RAM direct mapped to GPU if IOMMU is not enabled or is pass through mode
3852 */
3853static void amdgpu_device_check_iommu_direct_map(struct amdgpu_device *adev)
3854{
3855 struct iommu_domain *domain;
3856
3857 domain = iommu_get_domain_for_dev(adev->dev);
3858 if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY)
3859 adev->ram_is_direct_mapped = true;
3860}
3861
3862static const struct attribute *amdgpu_dev_attributes[] = {
3863 &dev_attr_pcie_replay_count.attr,
3864 NULL
3865};
3866
3867static void amdgpu_device_set_mcbp(struct amdgpu_device *adev)
3868{
3869 if (amdgpu_mcbp == 1)
3870 adev->gfx.mcbp = true;
3871 else if (amdgpu_mcbp == 0)
3872 adev->gfx.mcbp = false;
3873
3874 if (amdgpu_sriov_vf(adev))
3875 adev->gfx.mcbp = true;
3876
3877 if (adev->gfx.mcbp)
3878 DRM_INFO("MCBP is enabled\n");
3879}
3880
3881/**
3882 * amdgpu_device_init - initialize the driver
3883 *
3884 * @adev: amdgpu_device pointer
3885 * @flags: driver flags
3886 *
3887 * Initializes the driver info and hw (all asics).
3888 * Returns 0 for success or an error on failure.
3889 * Called at driver startup.
3890 */
3891int amdgpu_device_init(struct amdgpu_device *adev,
3892 uint32_t flags)
3893{
3894 struct drm_device *ddev = adev_to_drm(adev);
3895 struct pci_dev *pdev = adev->pdev;
3896 int r, i;
3897 bool px = false;
3898 u32 max_MBps;
3899 int tmp;
3900
3901 adev->shutdown = false;
3902 adev->flags = flags;
3903
3904 if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
3905 adev->asic_type = amdgpu_force_asic_type;
3906 else
3907 adev->asic_type = flags & AMD_ASIC_MASK;
3908
3909 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
3910 if (amdgpu_emu_mode == 1)
3911 adev->usec_timeout *= 10;
3912 adev->gmc.gart_size = 512 * 1024 * 1024;
3913 adev->accel_working = false;
3914 adev->num_rings = 0;
3915 RCU_INIT_POINTER(adev->gang_submit, dma_fence_get_stub());
3916 adev->mman.buffer_funcs = NULL;
3917 adev->mman.buffer_funcs_ring = NULL;
3918 adev->vm_manager.vm_pte_funcs = NULL;
3919 adev->vm_manager.vm_pte_num_scheds = 0;
3920 adev->gmc.gmc_funcs = NULL;
3921 adev->harvest_ip_mask = 0x0;
3922 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3923 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
3924
3925 adev->smc_rreg = &amdgpu_invalid_rreg;
3926 adev->smc_wreg = &amdgpu_invalid_wreg;
3927 adev->pcie_rreg = &amdgpu_invalid_rreg;
3928 adev->pcie_wreg = &amdgpu_invalid_wreg;
3929 adev->pcie_rreg_ext = &amdgpu_invalid_rreg_ext;
3930 adev->pcie_wreg_ext = &amdgpu_invalid_wreg_ext;
3931 adev->pciep_rreg = &amdgpu_invalid_rreg;
3932 adev->pciep_wreg = &amdgpu_invalid_wreg;
3933 adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
3934 adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
3935 adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext;
3936 adev->pcie_wreg64_ext = &amdgpu_invalid_wreg64_ext;
3937 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
3938 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
3939 adev->didt_rreg = &amdgpu_invalid_rreg;
3940 adev->didt_wreg = &amdgpu_invalid_wreg;
3941 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
3942 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
3943 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
3944 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
3945
3946 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
3947 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
3948 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
3949
3950 /* mutex initialization are all done here so we
3951 * can recall function without having locking issues
3952 */
3953 mutex_init(&adev->firmware.mutex);
3954 mutex_init(&adev->pm.mutex);
3955 mutex_init(&adev->gfx.gpu_clock_mutex);
3956 mutex_init(&adev->srbm_mutex);
3957 mutex_init(&adev->gfx.pipe_reserve_mutex);
3958 mutex_init(&adev->gfx.gfx_off_mutex);
3959 mutex_init(&adev->gfx.partition_mutex);
3960 mutex_init(&adev->grbm_idx_mutex);
3961 mutex_init(&adev->mn_lock);
3962 mutex_init(&adev->virt.vf_errors.lock);
3963 hash_init(adev->mn_hash);
3964 mutex_init(&adev->psp.mutex);
3965 mutex_init(&adev->notifier_lock);
3966 mutex_init(&adev->pm.stable_pstate_ctx_lock);
3967 mutex_init(&adev->benchmark_mutex);
3968
3969 amdgpu_device_init_apu_flags(adev);
3970
3971 r = amdgpu_device_check_arguments(adev);
3972 if (r)
3973 return r;
3974
3975 spin_lock_init(&adev->mmio_idx_lock);
3976 spin_lock_init(&adev->smc_idx_lock);
3977 spin_lock_init(&adev->pcie_idx_lock);
3978 spin_lock_init(&adev->uvd_ctx_idx_lock);
3979 spin_lock_init(&adev->didt_idx_lock);
3980 spin_lock_init(&adev->gc_cac_idx_lock);
3981 spin_lock_init(&adev->se_cac_idx_lock);
3982 spin_lock_init(&adev->audio_endpt_idx_lock);
3983 spin_lock_init(&adev->mm_stats.lock);
3984
3985 INIT_LIST_HEAD(&adev->shadow_list);
3986 mutex_init(&adev->shadow_list_lock);
3987
3988 INIT_LIST_HEAD(&adev->reset_list);
3989
3990 INIT_LIST_HEAD(&adev->ras_list);
3991
3992 INIT_LIST_HEAD(&adev->pm.od_kobj_list);
3993
3994 INIT_DELAYED_WORK(&adev->delayed_init_work,
3995 amdgpu_device_delayed_init_work_handler);
3996 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
3997 amdgpu_device_delay_enable_gfx_off);
3998
3999 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
4000
4001 adev->gfx.gfx_off_req_count = 1;
4002 adev->gfx.gfx_off_residency = 0;
4003 adev->gfx.gfx_off_entrycount = 0;
4004 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
4005
4006 atomic_set(&adev->throttling_logging_enabled, 1);
4007 /*
4008 * If throttling continues, logging will be performed every minute
4009 * to avoid log flooding. "-1" is subtracted since the thermal
4010 * throttling interrupt comes every second. Thus, the total logging
4011 * interval is 59 seconds(retelimited printk interval) + 1(waiting
4012 * for throttling interrupt) = 60 seconds.
4013 */
4014 ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1);
4015 ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE);
4016
4017 /* Registers mapping */
4018 /* TODO: block userspace mapping of io register */
4019 if (adev->asic_type >= CHIP_BONAIRE) {
4020 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
4021 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
4022 } else {
4023 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
4024 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
4025 }
4026
4027 for (i = 0; i < AMD_IP_BLOCK_TYPE_NUM; i++)
4028 atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN);
4029
4030 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
4031 if (!adev->rmmio)
4032 return -ENOMEM;
4033
4034 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
4035 DRM_INFO("register mmio size: %u\n", (unsigned int)adev->rmmio_size);
4036
4037 /*
4038 * Reset domain needs to be present early, before XGMI hive discovered
4039 * (if any) and intitialized to use reset sem and in_gpu reset flag
4040 * early on during init and before calling to RREG32.
4041 */
4042 adev->reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE, "amdgpu-reset-dev");
4043 if (!adev->reset_domain)
4044 return -ENOMEM;
4045
4046 /* detect hw virtualization here */
4047 amdgpu_detect_virtualization(adev);
4048
4049 amdgpu_device_get_pcie_info(adev);
4050
4051 r = amdgpu_device_get_job_timeout_settings(adev);
4052 if (r) {
4053 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
4054 return r;
4055 }
4056
4057 amdgpu_device_set_mcbp(adev);
4058
4059 /* early init functions */
4060 r = amdgpu_device_ip_early_init(adev);
4061 if (r)
4062 return r;
4063
4064 /* Get rid of things like offb */
4065 r = drm_aperture_remove_conflicting_pci_framebuffers(adev->pdev, &amdgpu_kms_driver);
4066 if (r)
4067 return r;
4068
4069 /* Enable TMZ based on IP_VERSION */
4070 amdgpu_gmc_tmz_set(adev);
4071
4072 amdgpu_gmc_noretry_set(adev);
4073 /* Need to get xgmi info early to decide the reset behavior*/
4074 if (adev->gmc.xgmi.supported) {
4075 r = adev->gfxhub.funcs->get_xgmi_info(adev);
4076 if (r)
4077 return r;
4078 }
4079
4080 /* enable PCIE atomic ops */
4081 if (amdgpu_sriov_vf(adev)) {
4082 if (adev->virt.fw_reserve.p_pf2vf)
4083 adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)
4084 adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_support_flags ==
4085 (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64);
4086 /* APUs w/ gfx9 onwards doesn't reply on PCIe atomics, rather it is a
4087 * internal path natively support atomics, set have_atomics_support to true.
4088 */
4089 } else if ((adev->flags & AMD_IS_APU) &&
4090 (amdgpu_ip_version(adev, GC_HWIP, 0) >
4091 IP_VERSION(9, 0, 0))) {
4092 adev->have_atomics_support = true;
4093 } else {
4094 adev->have_atomics_support =
4095 !pci_enable_atomic_ops_to_root(adev->pdev,
4096 PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
4097 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
4098 }
4099
4100 if (!adev->have_atomics_support)
4101 dev_info(adev->dev, "PCIE atomic ops is not supported\n");
4102
4103 /* doorbell bar mapping and doorbell index init*/
4104 amdgpu_doorbell_init(adev);
4105
4106 if (amdgpu_emu_mode == 1) {
4107 /* post the asic on emulation mode */
4108 emu_soc_asic_init(adev);
4109 goto fence_driver_init;
4110 }
4111
4112 amdgpu_reset_init(adev);
4113
4114 /* detect if we are with an SRIOV vbios */
4115 if (adev->bios)
4116 amdgpu_device_detect_sriov_bios(adev);
4117
4118 /* check if we need to reset the asic
4119 * E.g., driver was not cleanly unloaded previously, etc.
4120 */
4121 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
4122 if (adev->gmc.xgmi.num_physical_nodes) {
4123 dev_info(adev->dev, "Pending hive reset.\n");
4124 adev->gmc.xgmi.pending_reset = true;
4125 /* Only need to init necessary block for SMU to handle the reset */
4126 for (i = 0; i < adev->num_ip_blocks; i++) {
4127 if (!adev->ip_blocks[i].status.valid)
4128 continue;
4129 if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
4130 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
4131 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
4132 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) {
4133 DRM_DEBUG("IP %s disabled for hw_init.\n",
4134 adev->ip_blocks[i].version->funcs->name);
4135 adev->ip_blocks[i].status.hw = true;
4136 }
4137 }
4138 } else if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) &&
4139 !amdgpu_device_has_display_hardware(adev)) {
4140 r = psp_gpu_reset(adev);
4141 } else {
4142 tmp = amdgpu_reset_method;
4143 /* It should do a default reset when loading or reloading the driver,
4144 * regardless of the module parameter reset_method.
4145 */
4146 amdgpu_reset_method = AMD_RESET_METHOD_NONE;
4147 r = amdgpu_asic_reset(adev);
4148 amdgpu_reset_method = tmp;
4149 }
4150
4151 if (r) {
4152 dev_err(adev->dev, "asic reset on init failed\n");
4153 goto failed;
4154 }
4155 }
4156
4157 /* Post card if necessary */
4158 if (amdgpu_device_need_post(adev)) {
4159 if (!adev->bios) {
4160 dev_err(adev->dev, "no vBIOS found\n");
4161 r = -EINVAL;
4162 goto failed;
4163 }
4164 DRM_INFO("GPU posting now...\n");
4165 r = amdgpu_device_asic_init(adev);
4166 if (r) {
4167 dev_err(adev->dev, "gpu post error!\n");
4168 goto failed;
4169 }
4170 }
4171
4172 if (adev->bios) {
4173 if (adev->is_atom_fw) {
4174 /* Initialize clocks */
4175 r = amdgpu_atomfirmware_get_clock_info(adev);
4176 if (r) {
4177 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
4178 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
4179 goto failed;
4180 }
4181 } else {
4182 /* Initialize clocks */
4183 r = amdgpu_atombios_get_clock_info(adev);
4184 if (r) {
4185 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
4186 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
4187 goto failed;
4188 }
4189 /* init i2c buses */
4190 if (!amdgpu_device_has_dc_support(adev))
4191 amdgpu_atombios_i2c_init(adev);
4192 }
4193 }
4194
4195fence_driver_init:
4196 /* Fence driver */
4197 r = amdgpu_fence_driver_sw_init(adev);
4198 if (r) {
4199 dev_err(adev->dev, "amdgpu_fence_driver_sw_init failed\n");
4200 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
4201 goto failed;
4202 }
4203
4204 /* init the mode config */
4205 drm_mode_config_init(adev_to_drm(adev));
4206
4207 r = amdgpu_device_ip_init(adev);
4208 if (r) {
4209 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
4210 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
4211 goto release_ras_con;
4212 }
4213
4214 amdgpu_fence_driver_hw_init(adev);
4215
4216 dev_info(adev->dev,
4217 "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n",
4218 adev->gfx.config.max_shader_engines,
4219 adev->gfx.config.max_sh_per_se,
4220 adev->gfx.config.max_cu_per_sh,
4221 adev->gfx.cu_info.number);
4222
4223 adev->accel_working = true;
4224
4225 amdgpu_vm_check_compute_bug(adev);
4226
4227 /* Initialize the buffer migration limit. */
4228 if (amdgpu_moverate >= 0)
4229 max_MBps = amdgpu_moverate;
4230 else
4231 max_MBps = 8; /* Allow 8 MB/s. */
4232 /* Get a log2 for easy divisions. */
4233 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
4234
4235 /*
4236 * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
4237 * Otherwise the mgpu fan boost feature will be skipped due to the
4238 * gpu instance is counted less.
4239 */
4240 amdgpu_register_gpu_instance(adev);
4241
4242 /* enable clockgating, etc. after ib tests, etc. since some blocks require
4243 * explicit gating rather than handling it automatically.
4244 */
4245 if (!adev->gmc.xgmi.pending_reset) {
4246 r = amdgpu_device_ip_late_init(adev);
4247 if (r) {
4248 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
4249 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
4250 goto release_ras_con;
4251 }
4252 /* must succeed. */
4253 amdgpu_ras_resume(adev);
4254 queue_delayed_work(system_wq, &adev->delayed_init_work,
4255 msecs_to_jiffies(AMDGPU_RESUME_MS));
4256 }
4257
4258 if (amdgpu_sriov_vf(adev)) {
4259 amdgpu_virt_release_full_gpu(adev, true);
4260 flush_delayed_work(&adev->delayed_init_work);
4261 }
4262
4263 /*
4264 * Place those sysfs registering after `late_init`. As some of those
4265 * operations performed in `late_init` might affect the sysfs
4266 * interfaces creating.
4267 */
4268 r = amdgpu_atombios_sysfs_init(adev);
4269 if (r)
4270 drm_err(&adev->ddev,
4271 "registering atombios sysfs failed (%d).\n", r);
4272
4273 r = amdgpu_pm_sysfs_init(adev);
4274 if (r)
4275 DRM_ERROR("registering pm sysfs failed (%d).\n", r);
4276
4277 r = amdgpu_ucode_sysfs_init(adev);
4278 if (r) {
4279 adev->ucode_sysfs_en = false;
4280 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
4281 } else
4282 adev->ucode_sysfs_en = true;
4283
4284 r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes);
4285 if (r)
4286 dev_err(adev->dev, "Could not create amdgpu device attr\n");
4287
4288 r = devm_device_add_group(adev->dev, &amdgpu_board_attrs_group);
4289 if (r)
4290 dev_err(adev->dev,
4291 "Could not create amdgpu board attributes\n");
4292
4293 amdgpu_fru_sysfs_init(adev);
4294 amdgpu_reg_state_sysfs_init(adev);
4295
4296 if (IS_ENABLED(CONFIG_PERF_EVENTS))
4297 r = amdgpu_pmu_init(adev);
4298 if (r)
4299 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
4300
4301 /* Have stored pci confspace at hand for restore in sudden PCI error */
4302 if (amdgpu_device_cache_pci_state(adev->pdev))
4303 pci_restore_state(pdev);
4304
4305 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
4306 /* this will fail for cards that aren't VGA class devices, just
4307 * ignore it
4308 */
4309 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
4310 vga_client_register(adev->pdev, amdgpu_device_vga_set_decode);
4311
4312 px = amdgpu_device_supports_px(ddev);
4313
4314 if (px || (!dev_is_removable(&adev->pdev->dev) &&
4315 apple_gmux_detect(NULL, NULL)))
4316 vga_switcheroo_register_client(adev->pdev,
4317 &amdgpu_switcheroo_ops, px);
4318
4319 if (px)
4320 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
4321
4322 if (adev->gmc.xgmi.pending_reset)
4323 queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work,
4324 msecs_to_jiffies(AMDGPU_RESUME_MS));
4325
4326 amdgpu_device_check_iommu_direct_map(adev);
4327
4328 return 0;
4329
4330release_ras_con:
4331 if (amdgpu_sriov_vf(adev))
4332 amdgpu_virt_release_full_gpu(adev, true);
4333
4334 /* failed in exclusive mode due to timeout */
4335 if (amdgpu_sriov_vf(adev) &&
4336 !amdgpu_sriov_runtime(adev) &&
4337 amdgpu_virt_mmio_blocked(adev) &&
4338 !amdgpu_virt_wait_reset(adev)) {
4339 dev_err(adev->dev, "VF exclusive mode timeout\n");
4340 /* Don't send request since VF is inactive. */
4341 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
4342 adev->virt.ops = NULL;
4343 r = -EAGAIN;
4344 }
4345 amdgpu_release_ras_context(adev);
4346
4347failed:
4348 amdgpu_vf_error_trans_all(adev);
4349
4350 return r;
4351}
4352
4353static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
4354{
4355
4356 /* Clear all CPU mappings pointing to this device */
4357 unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1);
4358
4359 /* Unmap all mapped bars - Doorbell, registers and VRAM */
4360 amdgpu_doorbell_fini(adev);
4361
4362 iounmap(adev->rmmio);
4363 adev->rmmio = NULL;
4364 if (adev->mman.aper_base_kaddr)
4365 iounmap(adev->mman.aper_base_kaddr);
4366 adev->mman.aper_base_kaddr = NULL;
4367
4368 /* Memory manager related */
4369 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
4370 arch_phys_wc_del(adev->gmc.vram_mtrr);
4371 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
4372 }
4373}
4374
4375/**
4376 * amdgpu_device_fini_hw - tear down the driver
4377 *
4378 * @adev: amdgpu_device pointer
4379 *
4380 * Tear down the driver info (all asics).
4381 * Called at driver shutdown.
4382 */
4383void amdgpu_device_fini_hw(struct amdgpu_device *adev)
4384{
4385 dev_info(adev->dev, "amdgpu: finishing device.\n");
4386 flush_delayed_work(&adev->delayed_init_work);
4387 adev->shutdown = true;
4388
4389 /* make sure IB test finished before entering exclusive mode
4390 * to avoid preemption on IB test
4391 */
4392 if (amdgpu_sriov_vf(adev)) {
4393 amdgpu_virt_request_full_gpu(adev, false);
4394 amdgpu_virt_fini_data_exchange(adev);
4395 }
4396
4397 /* disable all interrupts */
4398 amdgpu_irq_disable_all(adev);
4399 if (adev->mode_info.mode_config_initialized) {
4400 if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev)))
4401 drm_helper_force_disable_all(adev_to_drm(adev));
4402 else
4403 drm_atomic_helper_shutdown(adev_to_drm(adev));
4404 }
4405 amdgpu_fence_driver_hw_fini(adev);
4406
4407 if (adev->mman.initialized)
4408 drain_workqueue(adev->mman.bdev.wq);
4409
4410 if (adev->pm.sysfs_initialized)
4411 amdgpu_pm_sysfs_fini(adev);
4412 if (adev->ucode_sysfs_en)
4413 amdgpu_ucode_sysfs_fini(adev);
4414 sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
4415 amdgpu_fru_sysfs_fini(adev);
4416
4417 amdgpu_reg_state_sysfs_fini(adev);
4418
4419 /* disable ras feature must before hw fini */
4420 amdgpu_ras_pre_fini(adev);
4421
4422 amdgpu_ttm_set_buffer_funcs_status(adev, false);
4423
4424 amdgpu_device_ip_fini_early(adev);
4425
4426 amdgpu_irq_fini_hw(adev);
4427
4428 if (adev->mman.initialized)
4429 ttm_device_clear_dma_mappings(&adev->mman.bdev);
4430
4431 amdgpu_gart_dummy_page_fini(adev);
4432
4433 if (drm_dev_is_unplugged(adev_to_drm(adev)))
4434 amdgpu_device_unmap_mmio(adev);
4435
4436}
4437
4438void amdgpu_device_fini_sw(struct amdgpu_device *adev)
4439{
4440 int idx;
4441 bool px;
4442
4443 amdgpu_fence_driver_sw_fini(adev);
4444 amdgpu_device_ip_fini(adev);
4445 amdgpu_ucode_release(&adev->firmware.gpu_info_fw);
4446 adev->accel_working = false;
4447 dma_fence_put(rcu_dereference_protected(adev->gang_submit, true));
4448
4449 amdgpu_reset_fini(adev);
4450
4451 /* free i2c buses */
4452 if (!amdgpu_device_has_dc_support(adev))
4453 amdgpu_i2c_fini(adev);
4454
4455 if (amdgpu_emu_mode != 1)
4456 amdgpu_atombios_fini(adev);
4457
4458 kfree(adev->bios);
4459 adev->bios = NULL;
4460
4461 kfree(adev->fru_info);
4462 adev->fru_info = NULL;
4463
4464 px = amdgpu_device_supports_px(adev_to_drm(adev));
4465
4466 if (px || (!dev_is_removable(&adev->pdev->dev) &&
4467 apple_gmux_detect(NULL, NULL)))
4468 vga_switcheroo_unregister_client(adev->pdev);
4469
4470 if (px)
4471 vga_switcheroo_fini_domain_pm_ops(adev->dev);
4472
4473 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
4474 vga_client_unregister(adev->pdev);
4475
4476 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
4477
4478 iounmap(adev->rmmio);
4479 adev->rmmio = NULL;
4480 amdgpu_doorbell_fini(adev);
4481 drm_dev_exit(idx);
4482 }
4483
4484 if (IS_ENABLED(CONFIG_PERF_EVENTS))
4485 amdgpu_pmu_fini(adev);
4486 if (adev->mman.discovery_bin)
4487 amdgpu_discovery_fini(adev);
4488
4489 amdgpu_reset_put_reset_domain(adev->reset_domain);
4490 adev->reset_domain = NULL;
4491
4492 kfree(adev->pci_state);
4493
4494}
4495
4496/**
4497 * amdgpu_device_evict_resources - evict device resources
4498 * @adev: amdgpu device object
4499 *
4500 * Evicts all ttm device resources(vram BOs, gart table) from the lru list
4501 * of the vram memory type. Mainly used for evicting device resources
4502 * at suspend time.
4503 *
4504 */
4505static int amdgpu_device_evict_resources(struct amdgpu_device *adev)
4506{
4507 int ret;
4508
4509 /* No need to evict vram on APUs for suspend to ram or s2idle */
4510 if ((adev->in_s3 || adev->in_s0ix) && (adev->flags & AMD_IS_APU))
4511 return 0;
4512
4513 ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
4514 if (ret)
4515 DRM_WARN("evicting device resources failed\n");
4516 return ret;
4517}
4518
4519/*
4520 * Suspend & resume.
4521 */
4522/**
4523 * amdgpu_device_prepare - prepare for device suspend
4524 *
4525 * @dev: drm dev pointer
4526 *
4527 * Prepare to put the hw in the suspend state (all asics).
4528 * Returns 0 for success or an error on failure.
4529 * Called at driver suspend.
4530 */
4531int amdgpu_device_prepare(struct drm_device *dev)
4532{
4533 struct amdgpu_device *adev = drm_to_adev(dev);
4534 int i, r;
4535
4536 amdgpu_choose_low_power_state(adev);
4537
4538 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4539 return 0;
4540
4541 /* Evict the majority of BOs before starting suspend sequence */
4542 r = amdgpu_device_evict_resources(adev);
4543 if (r)
4544 goto unprepare;
4545
4546 flush_delayed_work(&adev->gfx.gfx_off_delay_work);
4547
4548 for (i = 0; i < adev->num_ip_blocks; i++) {
4549 if (!adev->ip_blocks[i].status.valid)
4550 continue;
4551 if (!adev->ip_blocks[i].version->funcs->prepare_suspend)
4552 continue;
4553 r = adev->ip_blocks[i].version->funcs->prepare_suspend((void *)adev);
4554 if (r)
4555 goto unprepare;
4556 }
4557
4558 return 0;
4559
4560unprepare:
4561 adev->in_s0ix = adev->in_s3 = false;
4562
4563 return r;
4564}
4565
4566/**
4567 * amdgpu_device_suspend - initiate device suspend
4568 *
4569 * @dev: drm dev pointer
4570 * @fbcon : notify the fbdev of suspend
4571 *
4572 * Puts the hw in the suspend state (all asics).
4573 * Returns 0 for success or an error on failure.
4574 * Called at driver suspend.
4575 */
4576int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
4577{
4578 struct amdgpu_device *adev = drm_to_adev(dev);
4579 int r = 0;
4580
4581 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4582 return 0;
4583
4584 adev->in_suspend = true;
4585
4586 if (amdgpu_sriov_vf(adev)) {
4587 amdgpu_virt_fini_data_exchange(adev);
4588 r = amdgpu_virt_request_full_gpu(adev, false);
4589 if (r)
4590 return r;
4591 }
4592
4593 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3))
4594 DRM_WARN("smart shift update failed\n");
4595
4596 if (fbcon)
4597 drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
4598
4599 cancel_delayed_work_sync(&adev->delayed_init_work);
4600
4601 amdgpu_ras_suspend(adev);
4602
4603 amdgpu_device_ip_suspend_phase1(adev);
4604
4605 if (!adev->in_s0ix)
4606 amdgpu_amdkfd_suspend(adev, adev->in_runpm);
4607
4608 r = amdgpu_device_evict_resources(adev);
4609 if (r)
4610 return r;
4611
4612 amdgpu_ttm_set_buffer_funcs_status(adev, false);
4613
4614 amdgpu_fence_driver_hw_fini(adev);
4615
4616 amdgpu_device_ip_suspend_phase2(adev);
4617
4618 if (amdgpu_sriov_vf(adev))
4619 amdgpu_virt_release_full_gpu(adev, false);
4620
4621 r = amdgpu_dpm_notify_rlc_state(adev, false);
4622 if (r)
4623 return r;
4624
4625 return 0;
4626}
4627
4628/**
4629 * amdgpu_device_resume - initiate device resume
4630 *
4631 * @dev: drm dev pointer
4632 * @fbcon : notify the fbdev of resume
4633 *
4634 * Bring the hw back to operating state (all asics).
4635 * Returns 0 for success or an error on failure.
4636 * Called at driver resume.
4637 */
4638int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
4639{
4640 struct amdgpu_device *adev = drm_to_adev(dev);
4641 int r = 0;
4642
4643 if (amdgpu_sriov_vf(adev)) {
4644 r = amdgpu_virt_request_full_gpu(adev, true);
4645 if (r)
4646 return r;
4647 }
4648
4649 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4650 return 0;
4651
4652 if (adev->in_s0ix)
4653 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D0Entry);
4654
4655 /* post card */
4656 if (amdgpu_device_need_post(adev)) {
4657 r = amdgpu_device_asic_init(adev);
4658 if (r)
4659 dev_err(adev->dev, "amdgpu asic init failed\n");
4660 }
4661
4662 r = amdgpu_device_ip_resume(adev);
4663
4664 if (r) {
4665 dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);
4666 goto exit;
4667 }
4668 amdgpu_fence_driver_hw_init(adev);
4669
4670 if (!adev->in_s0ix) {
4671 r = amdgpu_amdkfd_resume(adev, adev->in_runpm);
4672 if (r)
4673 goto exit;
4674 }
4675
4676 r = amdgpu_device_ip_late_init(adev);
4677 if (r)
4678 goto exit;
4679
4680 queue_delayed_work(system_wq, &adev->delayed_init_work,
4681 msecs_to_jiffies(AMDGPU_RESUME_MS));
4682exit:
4683 if (amdgpu_sriov_vf(adev)) {
4684 amdgpu_virt_init_data_exchange(adev);
4685 amdgpu_virt_release_full_gpu(adev, true);
4686 }
4687
4688 if (r)
4689 return r;
4690
4691 /* Make sure IB tests flushed */
4692 flush_delayed_work(&adev->delayed_init_work);
4693
4694 if (fbcon)
4695 drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false);
4696
4697 amdgpu_ras_resume(adev);
4698
4699 if (adev->mode_info.num_crtc) {
4700 /*
4701 * Most of the connector probing functions try to acquire runtime pm
4702 * refs to ensure that the GPU is powered on when connector polling is
4703 * performed. Since we're calling this from a runtime PM callback,
4704 * trying to acquire rpm refs will cause us to deadlock.
4705 *
4706 * Since we're guaranteed to be holding the rpm lock, it's safe to
4707 * temporarily disable the rpm helpers so this doesn't deadlock us.
4708 */
4709#ifdef CONFIG_PM
4710 dev->dev->power.disable_depth++;
4711#endif
4712 if (!adev->dc_enabled)
4713 drm_helper_hpd_irq_event(dev);
4714 else
4715 drm_kms_helper_hotplug_event(dev);
4716#ifdef CONFIG_PM
4717 dev->dev->power.disable_depth--;
4718#endif
4719 }
4720 adev->in_suspend = false;
4721
4722 if (adev->enable_mes)
4723 amdgpu_mes_self_test(adev);
4724
4725 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))
4726 DRM_WARN("smart shift update failed\n");
4727
4728 return 0;
4729}
4730
4731/**
4732 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
4733 *
4734 * @adev: amdgpu_device pointer
4735 *
4736 * The list of all the hardware IPs that make up the asic is walked and
4737 * the check_soft_reset callbacks are run. check_soft_reset determines
4738 * if the asic is still hung or not.
4739 * Returns true if any of the IPs are still in a hung state, false if not.
4740 */
4741static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
4742{
4743 int i;
4744 bool asic_hang = false;
4745
4746 if (amdgpu_sriov_vf(adev))
4747 return true;
4748
4749 if (amdgpu_asic_need_full_reset(adev))
4750 return true;
4751
4752 for (i = 0; i < adev->num_ip_blocks; i++) {
4753 if (!adev->ip_blocks[i].status.valid)
4754 continue;
4755 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
4756 adev->ip_blocks[i].status.hang =
4757 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
4758 if (adev->ip_blocks[i].status.hang) {
4759 dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
4760 asic_hang = true;
4761 }
4762 }
4763 return asic_hang;
4764}
4765
4766/**
4767 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
4768 *
4769 * @adev: amdgpu_device pointer
4770 *
4771 * The list of all the hardware IPs that make up the asic is walked and the
4772 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
4773 * handles any IP specific hardware or software state changes that are
4774 * necessary for a soft reset to succeed.
4775 * Returns 0 on success, negative error code on failure.
4776 */
4777static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
4778{
4779 int i, r = 0;
4780
4781 for (i = 0; i < adev->num_ip_blocks; i++) {
4782 if (!adev->ip_blocks[i].status.valid)
4783 continue;
4784 if (adev->ip_blocks[i].status.hang &&
4785 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
4786 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
4787 if (r)
4788 return r;
4789 }
4790 }
4791
4792 return 0;
4793}
4794
4795/**
4796 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
4797 *
4798 * @adev: amdgpu_device pointer
4799 *
4800 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
4801 * reset is necessary to recover.
4802 * Returns true if a full asic reset is required, false if not.
4803 */
4804static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
4805{
4806 int i;
4807
4808 if (amdgpu_asic_need_full_reset(adev))
4809 return true;
4810
4811 for (i = 0; i < adev->num_ip_blocks; i++) {
4812 if (!adev->ip_blocks[i].status.valid)
4813 continue;
4814 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
4815 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
4816 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
4817 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
4818 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
4819 if (adev->ip_blocks[i].status.hang) {
4820 dev_info(adev->dev, "Some block need full reset!\n");
4821 return true;
4822 }
4823 }
4824 }
4825 return false;
4826}
4827
4828/**
4829 * amdgpu_device_ip_soft_reset - do a soft reset
4830 *
4831 * @adev: amdgpu_device pointer
4832 *
4833 * The list of all the hardware IPs that make up the asic is walked and the
4834 * soft_reset callbacks are run if the block is hung. soft_reset handles any
4835 * IP specific hardware or software state changes that are necessary to soft
4836 * reset the IP.
4837 * Returns 0 on success, negative error code on failure.
4838 */
4839static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
4840{
4841 int i, r = 0;
4842
4843 for (i = 0; i < adev->num_ip_blocks; i++) {
4844 if (!adev->ip_blocks[i].status.valid)
4845 continue;
4846 if (adev->ip_blocks[i].status.hang &&
4847 adev->ip_blocks[i].version->funcs->soft_reset) {
4848 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
4849 if (r)
4850 return r;
4851 }
4852 }
4853
4854 return 0;
4855}
4856
4857/**
4858 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
4859 *
4860 * @adev: amdgpu_device pointer
4861 *
4862 * The list of all the hardware IPs that make up the asic is walked and the
4863 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
4864 * handles any IP specific hardware or software state changes that are
4865 * necessary after the IP has been soft reset.
4866 * Returns 0 on success, negative error code on failure.
4867 */
4868static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
4869{
4870 int i, r = 0;
4871
4872 for (i = 0; i < adev->num_ip_blocks; i++) {
4873 if (!adev->ip_blocks[i].status.valid)
4874 continue;
4875 if (adev->ip_blocks[i].status.hang &&
4876 adev->ip_blocks[i].version->funcs->post_soft_reset)
4877 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
4878 if (r)
4879 return r;
4880 }
4881
4882 return 0;
4883}
4884
4885/**
4886 * amdgpu_device_recover_vram - Recover some VRAM contents
4887 *
4888 * @adev: amdgpu_device pointer
4889 *
4890 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
4891 * restore things like GPUVM page tables after a GPU reset where
4892 * the contents of VRAM might be lost.
4893 *
4894 * Returns:
4895 * 0 on success, negative error code on failure.
4896 */
4897static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
4898{
4899 struct dma_fence *fence = NULL, *next = NULL;
4900 struct amdgpu_bo *shadow;
4901 struct amdgpu_bo_vm *vmbo;
4902 long r = 1, tmo;
4903
4904 if (amdgpu_sriov_runtime(adev))
4905 tmo = msecs_to_jiffies(8000);
4906 else
4907 tmo = msecs_to_jiffies(100);
4908
4909 dev_info(adev->dev, "recover vram bo from shadow start\n");
4910 mutex_lock(&adev->shadow_list_lock);
4911 list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) {
4912 /* If vm is compute context or adev is APU, shadow will be NULL */
4913 if (!vmbo->shadow)
4914 continue;
4915 shadow = vmbo->shadow;
4916
4917 /* No need to recover an evicted BO */
4918 if (shadow->tbo.resource->mem_type != TTM_PL_TT ||
4919 shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET ||
4920 shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM)
4921 continue;
4922
4923 r = amdgpu_bo_restore_shadow(shadow, &next);
4924 if (r)
4925 break;
4926
4927 if (fence) {
4928 tmo = dma_fence_wait_timeout(fence, false, tmo);
4929 dma_fence_put(fence);
4930 fence = next;
4931 if (tmo == 0) {
4932 r = -ETIMEDOUT;
4933 break;
4934 } else if (tmo < 0) {
4935 r = tmo;
4936 break;
4937 }
4938 } else {
4939 fence = next;
4940 }
4941 }
4942 mutex_unlock(&adev->shadow_list_lock);
4943
4944 if (fence)
4945 tmo = dma_fence_wait_timeout(fence, false, tmo);
4946 dma_fence_put(fence);
4947
4948 if (r < 0 || tmo <= 0) {
4949 dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
4950 return -EIO;
4951 }
4952
4953 dev_info(adev->dev, "recover vram bo from shadow done\n");
4954 return 0;
4955}
4956
4957
4958/**
4959 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
4960 *
4961 * @adev: amdgpu_device pointer
4962 * @from_hypervisor: request from hypervisor
4963 *
4964 * do VF FLR and reinitialize Asic
4965 * return 0 means succeeded otherwise failed
4966 */
4967static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
4968 bool from_hypervisor)
4969{
4970 int r;
4971 struct amdgpu_hive_info *hive = NULL;
4972 int retry_limit = 0;
4973
4974retry:
4975 amdgpu_amdkfd_pre_reset(adev);
4976
4977 if (from_hypervisor)
4978 r = amdgpu_virt_request_full_gpu(adev, true);
4979 else
4980 r = amdgpu_virt_reset_gpu(adev);
4981 if (r)
4982 return r;
4983 amdgpu_irq_gpu_reset_resume_helper(adev);
4984
4985 /* some sw clean up VF needs to do before recover */
4986 amdgpu_virt_post_reset(adev);
4987
4988 /* Resume IP prior to SMC */
4989 r = amdgpu_device_ip_reinit_early_sriov(adev);
4990 if (r)
4991 goto error;
4992
4993 amdgpu_virt_init_data_exchange(adev);
4994
4995 r = amdgpu_device_fw_loading(adev);
4996 if (r)
4997 return r;
4998
4999 /* now we are okay to resume SMC/CP/SDMA */
5000 r = amdgpu_device_ip_reinit_late_sriov(adev);
5001 if (r)
5002 goto error;
5003
5004 hive = amdgpu_get_xgmi_hive(adev);
5005 /* Update PSP FW topology after reset */
5006 if (hive && adev->gmc.xgmi.num_physical_nodes > 1)
5007 r = amdgpu_xgmi_update_topology(hive, adev);
5008
5009 if (hive)
5010 amdgpu_put_xgmi_hive(hive);
5011
5012 if (!r) {
5013 r = amdgpu_ib_ring_tests(adev);
5014
5015 amdgpu_amdkfd_post_reset(adev);
5016 }
5017
5018error:
5019 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
5020 amdgpu_inc_vram_lost(adev);
5021 r = amdgpu_device_recover_vram(adev);
5022 }
5023 amdgpu_virt_release_full_gpu(adev, true);
5024
5025 if (AMDGPU_RETRY_SRIOV_RESET(r)) {
5026 if (retry_limit < AMDGPU_MAX_RETRY_LIMIT) {
5027 retry_limit++;
5028 goto retry;
5029 } else
5030 DRM_ERROR("GPU reset retry is beyond the retry limit\n");
5031 }
5032
5033 return r;
5034}
5035
5036/**
5037 * amdgpu_device_has_job_running - check if there is any job in mirror list
5038 *
5039 * @adev: amdgpu_device pointer
5040 *
5041 * check if there is any job in mirror list
5042 */
5043bool amdgpu_device_has_job_running(struct amdgpu_device *adev)
5044{
5045 int i;
5046 struct drm_sched_job *job;
5047
5048 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5049 struct amdgpu_ring *ring = adev->rings[i];
5050
5051 if (!amdgpu_ring_sched_ready(ring))
5052 continue;
5053
5054 spin_lock(&ring->sched.job_list_lock);
5055 job = list_first_entry_or_null(&ring->sched.pending_list,
5056 struct drm_sched_job, list);
5057 spin_unlock(&ring->sched.job_list_lock);
5058 if (job)
5059 return true;
5060 }
5061 return false;
5062}
5063
5064/**
5065 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
5066 *
5067 * @adev: amdgpu_device pointer
5068 *
5069 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
5070 * a hung GPU.
5071 */
5072bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
5073{
5074
5075 if (amdgpu_gpu_recovery == 0)
5076 goto disabled;
5077
5078 /* Skip soft reset check in fatal error mode */
5079 if (!amdgpu_ras_is_poison_mode_supported(adev))
5080 return true;
5081
5082 if (amdgpu_sriov_vf(adev))
5083 return true;
5084
5085 if (amdgpu_gpu_recovery == -1) {
5086 switch (adev->asic_type) {
5087#ifdef CONFIG_DRM_AMDGPU_SI
5088 case CHIP_VERDE:
5089 case CHIP_TAHITI:
5090 case CHIP_PITCAIRN:
5091 case CHIP_OLAND:
5092 case CHIP_HAINAN:
5093#endif
5094#ifdef CONFIG_DRM_AMDGPU_CIK
5095 case CHIP_KAVERI:
5096 case CHIP_KABINI:
5097 case CHIP_MULLINS:
5098#endif
5099 case CHIP_CARRIZO:
5100 case CHIP_STONEY:
5101 case CHIP_CYAN_SKILLFISH:
5102 goto disabled;
5103 default:
5104 break;
5105 }
5106 }
5107
5108 return true;
5109
5110disabled:
5111 dev_info(adev->dev, "GPU recovery disabled.\n");
5112 return false;
5113}
5114
5115int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
5116{
5117 u32 i;
5118 int ret = 0;
5119
5120 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
5121
5122 dev_info(adev->dev, "GPU mode1 reset\n");
5123
5124 /* disable BM */
5125 pci_clear_master(adev->pdev);
5126
5127 amdgpu_device_cache_pci_state(adev->pdev);
5128
5129 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
5130 dev_info(adev->dev, "GPU smu mode1 reset\n");
5131 ret = amdgpu_dpm_mode1_reset(adev);
5132 } else {
5133 dev_info(adev->dev, "GPU psp mode1 reset\n");
5134 ret = psp_gpu_reset(adev);
5135 }
5136
5137 if (ret)
5138 goto mode1_reset_failed;
5139
5140 amdgpu_device_load_pci_state(adev->pdev);
5141 ret = amdgpu_psp_wait_for_bootloader(adev);
5142 if (ret)
5143 goto mode1_reset_failed;
5144
5145 /* wait for asic to come out of reset */
5146 for (i = 0; i < adev->usec_timeout; i++) {
5147 u32 memsize = adev->nbio.funcs->get_memsize(adev);
5148
5149 if (memsize != 0xffffffff)
5150 break;
5151 udelay(1);
5152 }
5153
5154 if (i >= adev->usec_timeout) {
5155 ret = -ETIMEDOUT;
5156 goto mode1_reset_failed;
5157 }
5158
5159 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
5160
5161 return 0;
5162
5163mode1_reset_failed:
5164 dev_err(adev->dev, "GPU mode1 reset failed\n");
5165 return ret;
5166}
5167
5168int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
5169 struct amdgpu_reset_context *reset_context)
5170{
5171 int i, r = 0;
5172 struct amdgpu_job *job = NULL;
5173 bool need_full_reset =
5174 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5175
5176 if (reset_context->reset_req_dev == adev)
5177 job = reset_context->job;
5178
5179 if (amdgpu_sriov_vf(adev)) {
5180 /* stop the data exchange thread */
5181 amdgpu_virt_fini_data_exchange(adev);
5182 }
5183
5184 amdgpu_fence_driver_isr_toggle(adev, true);
5185
5186 /* block all schedulers and reset given job's ring */
5187 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5188 struct amdgpu_ring *ring = adev->rings[i];
5189
5190 if (!amdgpu_ring_sched_ready(ring))
5191 continue;
5192
5193 /* Clear job fence from fence drv to avoid force_completion
5194 * leave NULL and vm flush fence in fence drv
5195 */
5196 amdgpu_fence_driver_clear_job_fences(ring);
5197
5198 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
5199 amdgpu_fence_driver_force_completion(ring);
5200 }
5201
5202 amdgpu_fence_driver_isr_toggle(adev, false);
5203
5204 if (job && job->vm)
5205 drm_sched_increase_karma(&job->base);
5206
5207 r = amdgpu_reset_prepare_hwcontext(adev, reset_context);
5208 /* If reset handler not implemented, continue; otherwise return */
5209 if (r == -EOPNOTSUPP)
5210 r = 0;
5211 else
5212 return r;
5213
5214 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
5215 if (!amdgpu_sriov_vf(adev)) {
5216
5217 if (!need_full_reset)
5218 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
5219
5220 if (!need_full_reset && amdgpu_gpu_recovery &&
5221 amdgpu_device_ip_check_soft_reset(adev)) {
5222 amdgpu_device_ip_pre_soft_reset(adev);
5223 r = amdgpu_device_ip_soft_reset(adev);
5224 amdgpu_device_ip_post_soft_reset(adev);
5225 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
5226 dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n");
5227 need_full_reset = true;
5228 }
5229 }
5230
5231 if (need_full_reset)
5232 r = amdgpu_device_ip_suspend(adev);
5233 if (need_full_reset)
5234 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5235 else
5236 clear_bit(AMDGPU_NEED_FULL_RESET,
5237 &reset_context->flags);
5238 }
5239
5240 return r;
5241}
5242
5243static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)
5244{
5245 int i;
5246
5247 lockdep_assert_held(&adev->reset_domain->sem);
5248
5249 for (i = 0; i < adev->reset_info.num_regs; i++) {
5250 adev->reset_info.reset_dump_reg_value[i] =
5251 RREG32(adev->reset_info.reset_dump_reg_list[i]);
5252
5253 trace_amdgpu_reset_reg_dumps(adev->reset_info.reset_dump_reg_list[i],
5254 adev->reset_info.reset_dump_reg_value[i]);
5255 }
5256
5257 return 0;
5258}
5259
5260int amdgpu_do_asic_reset(struct list_head *device_list_handle,
5261 struct amdgpu_reset_context *reset_context)
5262{
5263 struct amdgpu_device *tmp_adev = NULL;
5264 bool need_full_reset, skip_hw_reset, vram_lost = false;
5265 int r = 0;
5266
5267 /* Try reset handler method first */
5268 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5269 reset_list);
5270 amdgpu_reset_reg_dumps(tmp_adev);
5271
5272 reset_context->reset_device_list = device_list_handle;
5273 r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
5274 /* If reset handler not implemented, continue; otherwise return */
5275 if (r == -EOPNOTSUPP)
5276 r = 0;
5277 else
5278 return r;
5279
5280 /* Reset handler not implemented, use the default method */
5281 need_full_reset =
5282 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5283 skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags);
5284
5285 /*
5286 * ASIC reset has to be done on all XGMI hive nodes ASAP
5287 * to allow proper links negotiation in FW (within 1 sec)
5288 */
5289 if (!skip_hw_reset && need_full_reset) {
5290 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5291 /* For XGMI run all resets in parallel to speed up the process */
5292 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
5293 tmp_adev->gmc.xgmi.pending_reset = false;
5294 if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work))
5295 r = -EALREADY;
5296 } else
5297 r = amdgpu_asic_reset(tmp_adev);
5298
5299 if (r) {
5300 dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s",
5301 r, adev_to_drm(tmp_adev)->unique);
5302 goto out;
5303 }
5304 }
5305
5306 /* For XGMI wait for all resets to complete before proceed */
5307 if (!r) {
5308 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5309 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
5310 flush_work(&tmp_adev->xgmi_reset_work);
5311 r = tmp_adev->asic_reset_res;
5312 if (r)
5313 break;
5314 }
5315 }
5316 }
5317 }
5318
5319 if (!r && amdgpu_ras_intr_triggered()) {
5320 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5321 amdgpu_ras_reset_error_count(tmp_adev, AMDGPU_RAS_BLOCK__MMHUB);
5322 }
5323
5324 amdgpu_ras_intr_cleared();
5325 }
5326
5327 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5328 if (need_full_reset) {
5329 /* post card */
5330 amdgpu_ras_set_fed(tmp_adev, false);
5331 r = amdgpu_device_asic_init(tmp_adev);
5332 if (r) {
5333 dev_warn(tmp_adev->dev, "asic atom init failed!");
5334 } else {
5335 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
5336
5337 r = amdgpu_device_ip_resume_phase1(tmp_adev);
5338 if (r)
5339 goto out;
5340
5341 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
5342
5343 amdgpu_coredump(tmp_adev, vram_lost, reset_context);
5344
5345 if (vram_lost) {
5346 DRM_INFO("VRAM is lost due to GPU reset!\n");
5347 amdgpu_inc_vram_lost(tmp_adev);
5348 }
5349
5350 r = amdgpu_device_fw_loading(tmp_adev);
5351 if (r)
5352 return r;
5353
5354 r = amdgpu_xcp_restore_partition_mode(
5355 tmp_adev->xcp_mgr);
5356 if (r)
5357 goto out;
5358
5359 r = amdgpu_device_ip_resume_phase2(tmp_adev);
5360 if (r)
5361 goto out;
5362
5363 if (tmp_adev->mman.buffer_funcs_ring->sched.ready)
5364 amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true);
5365
5366 if (vram_lost)
5367 amdgpu_device_fill_reset_magic(tmp_adev);
5368
5369 /*
5370 * Add this ASIC as tracked as reset was already
5371 * complete successfully.
5372 */
5373 amdgpu_register_gpu_instance(tmp_adev);
5374
5375 if (!reset_context->hive &&
5376 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5377 amdgpu_xgmi_add_device(tmp_adev);
5378
5379 r = amdgpu_device_ip_late_init(tmp_adev);
5380 if (r)
5381 goto out;
5382
5383 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, false);
5384
5385 /*
5386 * The GPU enters bad state once faulty pages
5387 * by ECC has reached the threshold, and ras
5388 * recovery is scheduled next. So add one check
5389 * here to break recovery if it indeed exceeds
5390 * bad page threshold, and remind user to
5391 * retire this GPU or setting one bigger
5392 * bad_page_threshold value to fix this once
5393 * probing driver again.
5394 */
5395 if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) {
5396 /* must succeed. */
5397 amdgpu_ras_resume(tmp_adev);
5398 } else {
5399 r = -EINVAL;
5400 goto out;
5401 }
5402
5403 /* Update PSP FW topology after reset */
5404 if (reset_context->hive &&
5405 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5406 r = amdgpu_xgmi_update_topology(
5407 reset_context->hive, tmp_adev);
5408 }
5409 }
5410
5411out:
5412 if (!r) {
5413 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
5414 r = amdgpu_ib_ring_tests(tmp_adev);
5415 if (r) {
5416 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
5417 need_full_reset = true;
5418 r = -EAGAIN;
5419 goto end;
5420 }
5421 }
5422
5423 if (!r)
5424 r = amdgpu_device_recover_vram(tmp_adev);
5425 else
5426 tmp_adev->asic_reset_res = r;
5427 }
5428
5429end:
5430 if (need_full_reset)
5431 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5432 else
5433 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5434 return r;
5435}
5436
5437static void amdgpu_device_set_mp1_state(struct amdgpu_device *adev)
5438{
5439
5440 switch (amdgpu_asic_reset_method(adev)) {
5441 case AMD_RESET_METHOD_MODE1:
5442 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
5443 break;
5444 case AMD_RESET_METHOD_MODE2:
5445 adev->mp1_state = PP_MP1_STATE_RESET;
5446 break;
5447 default:
5448 adev->mp1_state = PP_MP1_STATE_NONE;
5449 break;
5450 }
5451}
5452
5453static void amdgpu_device_unset_mp1_state(struct amdgpu_device *adev)
5454{
5455 amdgpu_vf_error_trans_all(adev);
5456 adev->mp1_state = PP_MP1_STATE_NONE;
5457}
5458
5459static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev)
5460{
5461 struct pci_dev *p = NULL;
5462
5463 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5464 adev->pdev->bus->number, 1);
5465 if (p) {
5466 pm_runtime_enable(&(p->dev));
5467 pm_runtime_resume(&(p->dev));
5468 }
5469
5470 pci_dev_put(p);
5471}
5472
5473static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
5474{
5475 enum amd_reset_method reset_method;
5476 struct pci_dev *p = NULL;
5477 u64 expires;
5478
5479 /*
5480 * For now, only BACO and mode1 reset are confirmed
5481 * to suffer the audio issue without proper suspended.
5482 */
5483 reset_method = amdgpu_asic_reset_method(adev);
5484 if ((reset_method != AMD_RESET_METHOD_BACO) &&
5485 (reset_method != AMD_RESET_METHOD_MODE1))
5486 return -EINVAL;
5487
5488 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5489 adev->pdev->bus->number, 1);
5490 if (!p)
5491 return -ENODEV;
5492
5493 expires = pm_runtime_autosuspend_expiration(&(p->dev));
5494 if (!expires)
5495 /*
5496 * If we cannot get the audio device autosuspend delay,
5497 * a fixed 4S interval will be used. Considering 3S is
5498 * the audio controller default autosuspend delay setting.
5499 * 4S used here is guaranteed to cover that.
5500 */
5501 expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL;
5502
5503 while (!pm_runtime_status_suspended(&(p->dev))) {
5504 if (!pm_runtime_suspend(&(p->dev)))
5505 break;
5506
5507 if (expires < ktime_get_mono_fast_ns()) {
5508 dev_warn(adev->dev, "failed to suspend display audio\n");
5509 pci_dev_put(p);
5510 /* TODO: abort the succeeding gpu reset? */
5511 return -ETIMEDOUT;
5512 }
5513 }
5514
5515 pm_runtime_disable(&(p->dev));
5516
5517 pci_dev_put(p);
5518 return 0;
5519}
5520
5521static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev)
5522{
5523 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
5524
5525#if defined(CONFIG_DEBUG_FS)
5526 if (!amdgpu_sriov_vf(adev))
5527 cancel_work(&adev->reset_work);
5528#endif
5529
5530 if (adev->kfd.dev)
5531 cancel_work(&adev->kfd.reset_work);
5532
5533 if (amdgpu_sriov_vf(adev))
5534 cancel_work(&adev->virt.flr_work);
5535
5536 if (con && adev->ras_enabled)
5537 cancel_work(&con->recovery_work);
5538
5539}
5540
5541/**
5542 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
5543 *
5544 * @adev: amdgpu_device pointer
5545 * @job: which job trigger hang
5546 * @reset_context: amdgpu reset context pointer
5547 *
5548 * Attempt to reset the GPU if it has hung (all asics).
5549 * Attempt to do soft-reset or full-reset and reinitialize Asic
5550 * Returns 0 for success or an error on failure.
5551 */
5552
5553int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
5554 struct amdgpu_job *job,
5555 struct amdgpu_reset_context *reset_context)
5556{
5557 struct list_head device_list, *device_list_handle = NULL;
5558 bool job_signaled = false;
5559 struct amdgpu_hive_info *hive = NULL;
5560 struct amdgpu_device *tmp_adev = NULL;
5561 int i, r = 0;
5562 bool need_emergency_restart = false;
5563 bool audio_suspended = false;
5564
5565 /*
5566 * Special case: RAS triggered and full reset isn't supported
5567 */
5568 need_emergency_restart = amdgpu_ras_need_emergency_restart(adev);
5569
5570 /*
5571 * Flush RAM to disk so that after reboot
5572 * the user can read log and see why the system rebooted.
5573 */
5574 if (need_emergency_restart && amdgpu_ras_get_context(adev) &&
5575 amdgpu_ras_get_context(adev)->reboot) {
5576 DRM_WARN("Emergency reboot.");
5577
5578 ksys_sync_helper();
5579 emergency_restart();
5580 }
5581
5582 dev_info(adev->dev, "GPU %s begin!\n",
5583 need_emergency_restart ? "jobs stop":"reset");
5584
5585 if (!amdgpu_sriov_vf(adev))
5586 hive = amdgpu_get_xgmi_hive(adev);
5587 if (hive)
5588 mutex_lock(&hive->hive_lock);
5589
5590 reset_context->job = job;
5591 reset_context->hive = hive;
5592 /*
5593 * Build list of devices to reset.
5594 * In case we are in XGMI hive mode, resort the device list
5595 * to put adev in the 1st position.
5596 */
5597 INIT_LIST_HEAD(&device_list);
5598 if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1)) {
5599 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
5600 list_add_tail(&tmp_adev->reset_list, &device_list);
5601 if (adev->shutdown)
5602 tmp_adev->shutdown = true;
5603 }
5604 if (!list_is_first(&adev->reset_list, &device_list))
5605 list_rotate_to_front(&adev->reset_list, &device_list);
5606 device_list_handle = &device_list;
5607 } else {
5608 list_add_tail(&adev->reset_list, &device_list);
5609 device_list_handle = &device_list;
5610 }
5611
5612 /* We need to lock reset domain only once both for XGMI and single device */
5613 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5614 reset_list);
5615 amdgpu_device_lock_reset_domain(tmp_adev->reset_domain);
5616
5617 /* block all schedulers and reset given job's ring */
5618 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5619
5620 amdgpu_device_set_mp1_state(tmp_adev);
5621
5622 /*
5623 * Try to put the audio codec into suspend state
5624 * before gpu reset started.
5625 *
5626 * Due to the power domain of the graphics device
5627 * is shared with AZ power domain. Without this,
5628 * we may change the audio hardware from behind
5629 * the audio driver's back. That will trigger
5630 * some audio codec errors.
5631 */
5632 if (!amdgpu_device_suspend_display_audio(tmp_adev))
5633 audio_suspended = true;
5634
5635 amdgpu_ras_set_error_query_ready(tmp_adev, false);
5636
5637 cancel_delayed_work_sync(&tmp_adev->delayed_init_work);
5638
5639 if (!amdgpu_sriov_vf(tmp_adev))
5640 amdgpu_amdkfd_pre_reset(tmp_adev);
5641
5642 /*
5643 * Mark these ASICs to be reseted as untracked first
5644 * And add them back after reset completed
5645 */
5646 amdgpu_unregister_gpu_instance(tmp_adev);
5647
5648 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true);
5649
5650 /* disable ras on ALL IPs */
5651 if (!need_emergency_restart &&
5652 amdgpu_device_ip_need_full_reset(tmp_adev))
5653 amdgpu_ras_suspend(tmp_adev);
5654
5655 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5656 struct amdgpu_ring *ring = tmp_adev->rings[i];
5657
5658 if (!amdgpu_ring_sched_ready(ring))
5659 continue;
5660
5661 drm_sched_stop(&ring->sched, job ? &job->base : NULL);
5662
5663 if (need_emergency_restart)
5664 amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
5665 }
5666 atomic_inc(&tmp_adev->gpu_reset_counter);
5667 }
5668
5669 if (need_emergency_restart)
5670 goto skip_sched_resume;
5671
5672 /*
5673 * Must check guilty signal here since after this point all old
5674 * HW fences are force signaled.
5675 *
5676 * job->base holds a reference to parent fence
5677 */
5678 if (job && dma_fence_is_signaled(&job->hw_fence)) {
5679 job_signaled = true;
5680 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
5681 goto skip_hw_reset;
5682 }
5683
5684retry: /* Rest of adevs pre asic reset from XGMI hive. */
5685 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5686 r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context);
5687 /*TODO Should we stop ?*/
5688 if (r) {
5689 dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
5690 r, adev_to_drm(tmp_adev)->unique);
5691 tmp_adev->asic_reset_res = r;
5692 }
5693
5694 /*
5695 * Drop all pending non scheduler resets. Scheduler resets
5696 * were already dropped during drm_sched_stop
5697 */
5698 amdgpu_device_stop_pending_resets(tmp_adev);
5699 }
5700
5701 /* Actual ASIC resets if needed.*/
5702 /* Host driver will handle XGMI hive reset for SRIOV */
5703 if (amdgpu_sriov_vf(adev)) {
5704 r = amdgpu_device_reset_sriov(adev, job ? false : true);
5705 if (r)
5706 adev->asic_reset_res = r;
5707
5708 /* Aldebaran and gfx_11_0_3 support ras in SRIOV, so need resume ras during reset */
5709 if (amdgpu_ip_version(adev, GC_HWIP, 0) ==
5710 IP_VERSION(9, 4, 2) ||
5711 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
5712 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3))
5713 amdgpu_ras_resume(adev);
5714 } else {
5715 r = amdgpu_do_asic_reset(device_list_handle, reset_context);
5716 if (r && r == -EAGAIN)
5717 goto retry;
5718 }
5719
5720skip_hw_reset:
5721
5722 /* Post ASIC reset for all devs .*/
5723 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5724
5725 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5726 struct amdgpu_ring *ring = tmp_adev->rings[i];
5727
5728 if (!amdgpu_ring_sched_ready(ring))
5729 continue;
5730
5731 drm_sched_start(&ring->sched, true);
5732 }
5733
5734 if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled)
5735 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
5736
5737 if (tmp_adev->asic_reset_res)
5738 r = tmp_adev->asic_reset_res;
5739
5740 tmp_adev->asic_reset_res = 0;
5741
5742 if (r) {
5743 /* bad news, how to tell it to userspace ? */
5744 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
5745 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
5746 } else {
5747 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
5748 if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0))
5749 DRM_WARN("smart shift update failed\n");
5750 }
5751 }
5752
5753skip_sched_resume:
5754 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5755 /* unlock kfd: SRIOV would do it separately */
5756 if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev))
5757 amdgpu_amdkfd_post_reset(tmp_adev);
5758
5759 /* kfd_post_reset will do nothing if kfd device is not initialized,
5760 * need to bring up kfd here if it's not be initialized before
5761 */
5762 if (!adev->kfd.init_complete)
5763 amdgpu_amdkfd_device_init(adev);
5764
5765 if (audio_suspended)
5766 amdgpu_device_resume_display_audio(tmp_adev);
5767
5768 amdgpu_device_unset_mp1_state(tmp_adev);
5769
5770 amdgpu_ras_set_error_query_ready(tmp_adev, true);
5771 }
5772
5773 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5774 reset_list);
5775 amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain);
5776
5777 if (hive) {
5778 mutex_unlock(&hive->hive_lock);
5779 amdgpu_put_xgmi_hive(hive);
5780 }
5781
5782 if (r)
5783 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
5784
5785 atomic_set(&adev->reset_domain->reset_res, r);
5786 return r;
5787}
5788
5789/**
5790 * amdgpu_device_partner_bandwidth - find the bandwidth of appropriate partner
5791 *
5792 * @adev: amdgpu_device pointer
5793 * @speed: pointer to the speed of the link
5794 * @width: pointer to the width of the link
5795 *
5796 * Evaluate the hierarchy to find the speed and bandwidth capabilities of the
5797 * first physical partner to an AMD dGPU.
5798 * This will exclude any virtual switches and links.
5799 */
5800static void amdgpu_device_partner_bandwidth(struct amdgpu_device *adev,
5801 enum pci_bus_speed *speed,
5802 enum pcie_link_width *width)
5803{
5804 struct pci_dev *parent = adev->pdev;
5805
5806 if (!speed || !width)
5807 return;
5808
5809 *speed = PCI_SPEED_UNKNOWN;
5810 *width = PCIE_LNK_WIDTH_UNKNOWN;
5811
5812 if (amdgpu_device_pcie_dynamic_switching_supported(adev)) {
5813 while ((parent = pci_upstream_bridge(parent))) {
5814 /* skip upstream/downstream switches internal to dGPU*/
5815 if (parent->vendor == PCI_VENDOR_ID_ATI)
5816 continue;
5817 *speed = pcie_get_speed_cap(parent);
5818 *width = pcie_get_width_cap(parent);
5819 break;
5820 }
5821 } else {
5822 /* use the current speeds rather than max if switching is not supported */
5823 pcie_bandwidth_available(adev->pdev, NULL, speed, width);
5824 }
5825}
5826
5827/**
5828 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
5829 *
5830 * @adev: amdgpu_device pointer
5831 *
5832 * Fetchs and stores in the driver the PCIE capabilities (gen speed
5833 * and lanes) of the slot the device is in. Handles APUs and
5834 * virtualized environments where PCIE config space may not be available.
5835 */
5836static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
5837{
5838 struct pci_dev *pdev;
5839 enum pci_bus_speed speed_cap, platform_speed_cap;
5840 enum pcie_link_width platform_link_width;
5841
5842 if (amdgpu_pcie_gen_cap)
5843 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
5844
5845 if (amdgpu_pcie_lane_cap)
5846 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
5847
5848 /* covers APUs as well */
5849 if (pci_is_root_bus(adev->pdev->bus) && !amdgpu_passthrough(adev)) {
5850 if (adev->pm.pcie_gen_mask == 0)
5851 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
5852 if (adev->pm.pcie_mlw_mask == 0)
5853 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
5854 return;
5855 }
5856
5857 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
5858 return;
5859
5860 amdgpu_device_partner_bandwidth(adev, &platform_speed_cap,
5861 &platform_link_width);
5862
5863 if (adev->pm.pcie_gen_mask == 0) {
5864 /* asic caps */
5865 pdev = adev->pdev;
5866 speed_cap = pcie_get_speed_cap(pdev);
5867 if (speed_cap == PCI_SPEED_UNKNOWN) {
5868 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5869 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5870 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5871 } else {
5872 if (speed_cap == PCIE_SPEED_32_0GT)
5873 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5874 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5875 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5876 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5877 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5);
5878 else if (speed_cap == PCIE_SPEED_16_0GT)
5879 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5880 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5881 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5882 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
5883 else if (speed_cap == PCIE_SPEED_8_0GT)
5884 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5885 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5886 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5887 else if (speed_cap == PCIE_SPEED_5_0GT)
5888 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5889 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
5890 else
5891 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
5892 }
5893 /* platform caps */
5894 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
5895 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5896 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5897 } else {
5898 if (platform_speed_cap == PCIE_SPEED_32_0GT)
5899 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5900 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5901 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5902 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5903 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5);
5904 else if (platform_speed_cap == PCIE_SPEED_16_0GT)
5905 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5906 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5907 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5908 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
5909 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
5910 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5911 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5912 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
5913 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
5914 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5915 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5916 else
5917 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
5918
5919 }
5920 }
5921 if (adev->pm.pcie_mlw_mask == 0) {
5922 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
5923 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
5924 } else {
5925 switch (platform_link_width) {
5926 case PCIE_LNK_X32:
5927 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
5928 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5929 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5930 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5931 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5932 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5933 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5934 break;
5935 case PCIE_LNK_X16:
5936 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5937 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5938 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5939 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5940 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5941 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5942 break;
5943 case PCIE_LNK_X12:
5944 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5945 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5946 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5947 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5948 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5949 break;
5950 case PCIE_LNK_X8:
5951 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5952 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5953 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5954 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5955 break;
5956 case PCIE_LNK_X4:
5957 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5958 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5959 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5960 break;
5961 case PCIE_LNK_X2:
5962 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5963 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5964 break;
5965 case PCIE_LNK_X1:
5966 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
5967 break;
5968 default:
5969 break;
5970 }
5971 }
5972 }
5973}
5974
5975/**
5976 * amdgpu_device_is_peer_accessible - Check peer access through PCIe BAR
5977 *
5978 * @adev: amdgpu_device pointer
5979 * @peer_adev: amdgpu_device pointer for peer device trying to access @adev
5980 *
5981 * Return true if @peer_adev can access (DMA) @adev through the PCIe
5982 * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of
5983 * @peer_adev.
5984 */
5985bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
5986 struct amdgpu_device *peer_adev)
5987{
5988#ifdef CONFIG_HSA_AMD_P2P
5989 uint64_t address_mask = peer_adev->dev->dma_mask ?
5990 ~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1);
5991 resource_size_t aper_limit =
5992 adev->gmc.aper_base + adev->gmc.aper_size - 1;
5993 bool p2p_access =
5994 !adev->gmc.xgmi.connected_to_cpu &&
5995 !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0);
5996
5997 return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size &&
5998 adev->gmc.real_vram_size == adev->gmc.visible_vram_size &&
5999 !(adev->gmc.aper_base & address_mask ||
6000 aper_limit & address_mask));
6001#else
6002 return false;
6003#endif
6004}
6005
6006int amdgpu_device_baco_enter(struct drm_device *dev)
6007{
6008 struct amdgpu_device *adev = drm_to_adev(dev);
6009 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
6010
6011 if (!amdgpu_device_supports_baco(dev))
6012 return -ENOTSUPP;
6013
6014 if (ras && adev->ras_enabled &&
6015 adev->nbio.funcs->enable_doorbell_interrupt)
6016 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
6017
6018 return amdgpu_dpm_baco_enter(adev);
6019}
6020
6021int amdgpu_device_baco_exit(struct drm_device *dev)
6022{
6023 struct amdgpu_device *adev = drm_to_adev(dev);
6024 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
6025 int ret = 0;
6026
6027 if (!amdgpu_device_supports_baco(dev))
6028 return -ENOTSUPP;
6029
6030 ret = amdgpu_dpm_baco_exit(adev);
6031 if (ret)
6032 return ret;
6033
6034 if (ras && adev->ras_enabled &&
6035 adev->nbio.funcs->enable_doorbell_interrupt)
6036 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
6037
6038 if (amdgpu_passthrough(adev) &&
6039 adev->nbio.funcs->clear_doorbell_interrupt)
6040 adev->nbio.funcs->clear_doorbell_interrupt(adev);
6041
6042 return 0;
6043}
6044
6045/**
6046 * amdgpu_pci_error_detected - Called when a PCI error is detected.
6047 * @pdev: PCI device struct
6048 * @state: PCI channel state
6049 *
6050 * Description: Called when a PCI error is detected.
6051 *
6052 * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT.
6053 */
6054pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6055{
6056 struct drm_device *dev = pci_get_drvdata(pdev);
6057 struct amdgpu_device *adev = drm_to_adev(dev);
6058 int i;
6059
6060 DRM_INFO("PCI error: detected callback, state(%d)!!\n", state);
6061
6062 if (adev->gmc.xgmi.num_physical_nodes > 1) {
6063 DRM_WARN("No support for XGMI hive yet...");
6064 return PCI_ERS_RESULT_DISCONNECT;
6065 }
6066
6067 adev->pci_channel_state = state;
6068
6069 switch (state) {
6070 case pci_channel_io_normal:
6071 return PCI_ERS_RESULT_CAN_RECOVER;
6072 /* Fatal error, prepare for slot reset */
6073 case pci_channel_io_frozen:
6074 /*
6075 * Locking adev->reset_domain->sem will prevent any external access
6076 * to GPU during PCI error recovery
6077 */
6078 amdgpu_device_lock_reset_domain(adev->reset_domain);
6079 amdgpu_device_set_mp1_state(adev);
6080
6081 /*
6082 * Block any work scheduling as we do for regular GPU reset
6083 * for the duration of the recovery
6084 */
6085 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
6086 struct amdgpu_ring *ring = adev->rings[i];
6087
6088 if (!amdgpu_ring_sched_ready(ring))
6089 continue;
6090
6091 drm_sched_stop(&ring->sched, NULL);
6092 }
6093 atomic_inc(&adev->gpu_reset_counter);
6094 return PCI_ERS_RESULT_NEED_RESET;
6095 case pci_channel_io_perm_failure:
6096 /* Permanent error, prepare for device removal */
6097 return PCI_ERS_RESULT_DISCONNECT;
6098 }
6099
6100 return PCI_ERS_RESULT_NEED_RESET;
6101}
6102
6103/**
6104 * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers
6105 * @pdev: pointer to PCI device
6106 */
6107pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev)
6108{
6109
6110 DRM_INFO("PCI error: mmio enabled callback!!\n");
6111
6112 /* TODO - dump whatever for debugging purposes */
6113
6114 /* This called only if amdgpu_pci_error_detected returns
6115 * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still
6116 * works, no need to reset slot.
6117 */
6118
6119 return PCI_ERS_RESULT_RECOVERED;
6120}
6121
6122/**
6123 * amdgpu_pci_slot_reset - Called when PCI slot has been reset.
6124 * @pdev: PCI device struct
6125 *
6126 * Description: This routine is called by the pci error recovery
6127 * code after the PCI slot has been reset, just before we
6128 * should resume normal operations.
6129 */
6130pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
6131{
6132 struct drm_device *dev = pci_get_drvdata(pdev);
6133 struct amdgpu_device *adev = drm_to_adev(dev);
6134 int r, i;
6135 struct amdgpu_reset_context reset_context;
6136 u32 memsize;
6137 struct list_head device_list;
6138 struct amdgpu_hive_info *hive;
6139 int hive_ras_recovery = 0;
6140 struct amdgpu_ras *ras;
6141
6142 /* PCI error slot reset should be skipped During RAS recovery */
6143 hive = amdgpu_get_xgmi_hive(adev);
6144 if (hive) {
6145 hive_ras_recovery = atomic_read(&hive->ras_recovery);
6146 amdgpu_put_xgmi_hive(hive);
6147 }
6148 ras = amdgpu_ras_get_context(adev);
6149 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) &&
6150 ras && (atomic_read(&ras->in_recovery) || hive_ras_recovery))
6151 return PCI_ERS_RESULT_RECOVERED;
6152
6153 DRM_INFO("PCI error: slot reset callback!!\n");
6154
6155 memset(&reset_context, 0, sizeof(reset_context));
6156
6157 INIT_LIST_HEAD(&device_list);
6158 list_add_tail(&adev->reset_list, &device_list);
6159
6160 /* wait for asic to come out of reset */
6161 msleep(500);
6162
6163 /* Restore PCI confspace */
6164 amdgpu_device_load_pci_state(pdev);
6165
6166 /* confirm ASIC came out of reset */
6167 for (i = 0; i < adev->usec_timeout; i++) {
6168 memsize = amdgpu_asic_get_config_memsize(adev);
6169
6170 if (memsize != 0xffffffff)
6171 break;
6172 udelay(1);
6173 }
6174 if (memsize == 0xffffffff) {
6175 r = -ETIME;
6176 goto out;
6177 }
6178
6179 reset_context.method = AMD_RESET_METHOD_NONE;
6180 reset_context.reset_req_dev = adev;
6181 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
6182 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
6183
6184 adev->no_hw_access = true;
6185 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
6186 adev->no_hw_access = false;
6187 if (r)
6188 goto out;
6189
6190 r = amdgpu_do_asic_reset(&device_list, &reset_context);
6191
6192out:
6193 if (!r) {
6194 if (amdgpu_device_cache_pci_state(adev->pdev))
6195 pci_restore_state(adev->pdev);
6196
6197 DRM_INFO("PCIe error recovery succeeded\n");
6198 } else {
6199 DRM_ERROR("PCIe error recovery failed, err:%d", r);
6200 amdgpu_device_unset_mp1_state(adev);
6201 amdgpu_device_unlock_reset_domain(adev->reset_domain);
6202 }
6203
6204 return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
6205}
6206
6207/**
6208 * amdgpu_pci_resume() - resume normal ops after PCI reset
6209 * @pdev: pointer to PCI device
6210 *
6211 * Called when the error recovery driver tells us that its
6212 * OK to resume normal operation.
6213 */
6214void amdgpu_pci_resume(struct pci_dev *pdev)
6215{
6216 struct drm_device *dev = pci_get_drvdata(pdev);
6217 struct amdgpu_device *adev = drm_to_adev(dev);
6218 int i;
6219
6220
6221 DRM_INFO("PCI error: resume callback!!\n");
6222
6223 /* Only continue execution for the case of pci_channel_io_frozen */
6224 if (adev->pci_channel_state != pci_channel_io_frozen)
6225 return;
6226
6227 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
6228 struct amdgpu_ring *ring = adev->rings[i];
6229
6230 if (!amdgpu_ring_sched_ready(ring))
6231 continue;
6232
6233 drm_sched_start(&ring->sched, true);
6234 }
6235
6236 amdgpu_device_unset_mp1_state(adev);
6237 amdgpu_device_unlock_reset_domain(adev->reset_domain);
6238}
6239
6240bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)
6241{
6242 struct drm_device *dev = pci_get_drvdata(pdev);
6243 struct amdgpu_device *adev = drm_to_adev(dev);
6244 int r;
6245
6246 r = pci_save_state(pdev);
6247 if (!r) {
6248 kfree(adev->pci_state);
6249
6250 adev->pci_state = pci_store_saved_state(pdev);
6251
6252 if (!adev->pci_state) {
6253 DRM_ERROR("Failed to store PCI saved state");
6254 return false;
6255 }
6256 } else {
6257 DRM_WARN("Failed to save PCI state, err:%d\n", r);
6258 return false;
6259 }
6260
6261 return true;
6262}
6263
6264bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
6265{
6266 struct drm_device *dev = pci_get_drvdata(pdev);
6267 struct amdgpu_device *adev = drm_to_adev(dev);
6268 int r;
6269
6270 if (!adev->pci_state)
6271 return false;
6272
6273 r = pci_load_saved_state(pdev, adev->pci_state);
6274
6275 if (!r) {
6276 pci_restore_state(pdev);
6277 } else {
6278 DRM_WARN("Failed to load PCI state, err:%d\n", r);
6279 return false;
6280 }
6281
6282 return true;
6283}
6284
6285void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
6286 struct amdgpu_ring *ring)
6287{
6288#ifdef CONFIG_X86_64
6289 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
6290 return;
6291#endif
6292 if (adev->gmc.xgmi.connected_to_cpu)
6293 return;
6294
6295 if (ring && ring->funcs->emit_hdp_flush)
6296 amdgpu_ring_emit_hdp_flush(ring);
6297 else
6298 amdgpu_asic_flush_hdp(adev, ring);
6299}
6300
6301void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
6302 struct amdgpu_ring *ring)
6303{
6304#ifdef CONFIG_X86_64
6305 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
6306 return;
6307#endif
6308 if (adev->gmc.xgmi.connected_to_cpu)
6309 return;
6310
6311 amdgpu_asic_invalidate_hdp(adev, ring);
6312}
6313
6314int amdgpu_in_reset(struct amdgpu_device *adev)
6315{
6316 return atomic_read(&adev->reset_domain->in_gpu_reset);
6317}
6318
6319/**
6320 * amdgpu_device_halt() - bring hardware to some kind of halt state
6321 *
6322 * @adev: amdgpu_device pointer
6323 *
6324 * Bring hardware to some kind of halt state so that no one can touch it
6325 * any more. It will help to maintain error context when error occurred.
6326 * Compare to a simple hang, the system will keep stable at least for SSH
6327 * access. Then it should be trivial to inspect the hardware state and
6328 * see what's going on. Implemented as following:
6329 *
6330 * 1. drm_dev_unplug() makes device inaccessible to user space(IOCTLs, etc),
6331 * clears all CPU mappings to device, disallows remappings through page faults
6332 * 2. amdgpu_irq_disable_all() disables all interrupts
6333 * 3. amdgpu_fence_driver_hw_fini() signals all HW fences
6334 * 4. set adev->no_hw_access to avoid potential crashes after setp 5
6335 * 5. amdgpu_device_unmap_mmio() clears all MMIO mappings
6336 * 6. pci_disable_device() and pci_wait_for_pending_transaction()
6337 * flush any in flight DMA operations
6338 */
6339void amdgpu_device_halt(struct amdgpu_device *adev)
6340{
6341 struct pci_dev *pdev = adev->pdev;
6342 struct drm_device *ddev = adev_to_drm(adev);
6343
6344 amdgpu_xcp_dev_unplug(adev);
6345 drm_dev_unplug(ddev);
6346
6347 amdgpu_irq_disable_all(adev);
6348
6349 amdgpu_fence_driver_hw_fini(adev);
6350
6351 adev->no_hw_access = true;
6352
6353 amdgpu_device_unmap_mmio(adev);
6354
6355 pci_disable_device(pdev);
6356 pci_wait_for_pending_transaction(pdev);
6357}
6358
6359u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
6360 u32 reg)
6361{
6362 unsigned long flags, address, data;
6363 u32 r;
6364
6365 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
6366 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
6367
6368 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
6369 WREG32(address, reg * 4);
6370 (void)RREG32(address);
6371 r = RREG32(data);
6372 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
6373 return r;
6374}
6375
6376void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
6377 u32 reg, u32 v)
6378{
6379 unsigned long flags, address, data;
6380
6381 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
6382 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
6383
6384 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
6385 WREG32(address, reg * 4);
6386 (void)RREG32(address);
6387 WREG32(data, v);
6388 (void)RREG32(data);
6389 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
6390}
6391
6392/**
6393 * amdgpu_device_switch_gang - switch to a new gang
6394 * @adev: amdgpu_device pointer
6395 * @gang: the gang to switch to
6396 *
6397 * Try to switch to a new gang.
6398 * Returns: NULL if we switched to the new gang or a reference to the current
6399 * gang leader.
6400 */
6401struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
6402 struct dma_fence *gang)
6403{
6404 struct dma_fence *old = NULL;
6405
6406 do {
6407 dma_fence_put(old);
6408 rcu_read_lock();
6409 old = dma_fence_get_rcu_safe(&adev->gang_submit);
6410 rcu_read_unlock();
6411
6412 if (old == gang)
6413 break;
6414
6415 if (!dma_fence_is_signaled(old))
6416 return old;
6417
6418 } while (cmpxchg((struct dma_fence __force **)&adev->gang_submit,
6419 old, gang) != old);
6420
6421 dma_fence_put(old);
6422 return NULL;
6423}
6424
6425bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev)
6426{
6427 switch (adev->asic_type) {
6428#ifdef CONFIG_DRM_AMDGPU_SI
6429 case CHIP_HAINAN:
6430#endif
6431 case CHIP_TOPAZ:
6432 /* chips with no display hardware */
6433 return false;
6434#ifdef CONFIG_DRM_AMDGPU_SI
6435 case CHIP_TAHITI:
6436 case CHIP_PITCAIRN:
6437 case CHIP_VERDE:
6438 case CHIP_OLAND:
6439#endif
6440#ifdef CONFIG_DRM_AMDGPU_CIK
6441 case CHIP_BONAIRE:
6442 case CHIP_HAWAII:
6443 case CHIP_KAVERI:
6444 case CHIP_KABINI:
6445 case CHIP_MULLINS:
6446#endif
6447 case CHIP_TONGA:
6448 case CHIP_FIJI:
6449 case CHIP_POLARIS10:
6450 case CHIP_POLARIS11:
6451 case CHIP_POLARIS12:
6452 case CHIP_VEGAM:
6453 case CHIP_CARRIZO:
6454 case CHIP_STONEY:
6455 /* chips with display hardware */
6456 return true;
6457 default:
6458 /* IP discovery */
6459 if (!amdgpu_ip_version(adev, DCE_HWIP, 0) ||
6460 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
6461 return false;
6462 return true;
6463 }
6464}
6465
6466uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
6467 uint32_t inst, uint32_t reg_addr, char reg_name[],
6468 uint32_t expected_value, uint32_t mask)
6469{
6470 uint32_t ret = 0;
6471 uint32_t old_ = 0;
6472 uint32_t tmp_ = RREG32(reg_addr);
6473 uint32_t loop = adev->usec_timeout;
6474
6475 while ((tmp_ & (mask)) != (expected_value)) {
6476 if (old_ != tmp_) {
6477 loop = adev->usec_timeout;
6478 old_ = tmp_;
6479 } else
6480 udelay(1);
6481 tmp_ = RREG32(reg_addr);
6482 loop--;
6483 if (!loop) {
6484 DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08xn",
6485 inst, reg_name, (uint32_t)expected_value,
6486 (uint32_t)(tmp_ & (mask)));
6487 ret = -ETIMEDOUT;
6488 break;
6489 }
6490 }
6491 return ret;
6492}
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/power_supply.h>
29#include <linux/kthread.h>
30#include <linux/module.h>
31#include <linux/console.h>
32#include <linux/slab.h>
33#include <linux/iommu.h>
34#include <linux/pci.h>
35#include <linux/devcoredump.h>
36#include <generated/utsrelease.h>
37#include <linux/pci-p2pdma.h>
38
39#include <drm/drm_aperture.h>
40#include <drm/drm_atomic_helper.h>
41#include <drm/drm_fb_helper.h>
42#include <drm/drm_probe_helper.h>
43#include <drm/amdgpu_drm.h>
44#include <linux/vgaarb.h>
45#include <linux/vga_switcheroo.h>
46#include <linux/efi.h>
47#include "amdgpu.h"
48#include "amdgpu_trace.h"
49#include "amdgpu_i2c.h"
50#include "atom.h"
51#include "amdgpu_atombios.h"
52#include "amdgpu_atomfirmware.h"
53#include "amd_pcie.h"
54#ifdef CONFIG_DRM_AMDGPU_SI
55#include "si.h"
56#endif
57#ifdef CONFIG_DRM_AMDGPU_CIK
58#include "cik.h"
59#endif
60#include "vi.h"
61#include "soc15.h"
62#include "nv.h"
63#include "bif/bif_4_1_d.h"
64#include <linux/firmware.h>
65#include "amdgpu_vf_error.h"
66
67#include "amdgpu_amdkfd.h"
68#include "amdgpu_pm.h"
69
70#include "amdgpu_xgmi.h"
71#include "amdgpu_ras.h"
72#include "amdgpu_pmu.h"
73#include "amdgpu_fru_eeprom.h"
74#include "amdgpu_reset.h"
75
76#include <linux/suspend.h>
77#include <drm/task_barrier.h>
78#include <linux/pm_runtime.h>
79
80#include <drm/drm_drv.h>
81
82MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
83MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
84MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
85MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
86MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
87MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
88MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
89
90#define AMDGPU_RESUME_MS 2000
91#define AMDGPU_MAX_RETRY_LIMIT 2
92#define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL)
93
94static const struct drm_driver amdgpu_kms_driver;
95
96const char *amdgpu_asic_name[] = {
97 "TAHITI",
98 "PITCAIRN",
99 "VERDE",
100 "OLAND",
101 "HAINAN",
102 "BONAIRE",
103 "KAVERI",
104 "KABINI",
105 "HAWAII",
106 "MULLINS",
107 "TOPAZ",
108 "TONGA",
109 "FIJI",
110 "CARRIZO",
111 "STONEY",
112 "POLARIS10",
113 "POLARIS11",
114 "POLARIS12",
115 "VEGAM",
116 "VEGA10",
117 "VEGA12",
118 "VEGA20",
119 "RAVEN",
120 "ARCTURUS",
121 "RENOIR",
122 "ALDEBARAN",
123 "NAVI10",
124 "CYAN_SKILLFISH",
125 "NAVI14",
126 "NAVI12",
127 "SIENNA_CICHLID",
128 "NAVY_FLOUNDER",
129 "VANGOGH",
130 "DIMGREY_CAVEFISH",
131 "BEIGE_GOBY",
132 "YELLOW_CARP",
133 "IP DISCOVERY",
134 "LAST",
135};
136
137/**
138 * DOC: pcie_replay_count
139 *
140 * The amdgpu driver provides a sysfs API for reporting the total number
141 * of PCIe replays (NAKs)
142 * The file pcie_replay_count is used for this and returns the total
143 * number of replays as a sum of the NAKs generated and NAKs received
144 */
145
146static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
147 struct device_attribute *attr, char *buf)
148{
149 struct drm_device *ddev = dev_get_drvdata(dev);
150 struct amdgpu_device *adev = drm_to_adev(ddev);
151 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev);
152
153 return sysfs_emit(buf, "%llu\n", cnt);
154}
155
156static DEVICE_ATTR(pcie_replay_count, S_IRUGO,
157 amdgpu_device_get_pcie_replay_count, NULL);
158
159static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
160
161/**
162 * DOC: product_name
163 *
164 * The amdgpu driver provides a sysfs API for reporting the product name
165 * for the device
166 * The file serial_number is used for this and returns the product name
167 * as returned from the FRU.
168 * NOTE: This is only available for certain server cards
169 */
170
171static ssize_t amdgpu_device_get_product_name(struct device *dev,
172 struct device_attribute *attr, char *buf)
173{
174 struct drm_device *ddev = dev_get_drvdata(dev);
175 struct amdgpu_device *adev = drm_to_adev(ddev);
176
177 return sysfs_emit(buf, "%s\n", adev->product_name);
178}
179
180static DEVICE_ATTR(product_name, S_IRUGO,
181 amdgpu_device_get_product_name, NULL);
182
183/**
184 * DOC: product_number
185 *
186 * The amdgpu driver provides a sysfs API for reporting the part number
187 * for the device
188 * The file serial_number is used for this and returns the part number
189 * as returned from the FRU.
190 * NOTE: This is only available for certain server cards
191 */
192
193static ssize_t amdgpu_device_get_product_number(struct device *dev,
194 struct device_attribute *attr, char *buf)
195{
196 struct drm_device *ddev = dev_get_drvdata(dev);
197 struct amdgpu_device *adev = drm_to_adev(ddev);
198
199 return sysfs_emit(buf, "%s\n", adev->product_number);
200}
201
202static DEVICE_ATTR(product_number, S_IRUGO,
203 amdgpu_device_get_product_number, NULL);
204
205/**
206 * DOC: serial_number
207 *
208 * The amdgpu driver provides a sysfs API for reporting the serial number
209 * for the device
210 * The file serial_number is used for this and returns the serial number
211 * as returned from the FRU.
212 * NOTE: This is only available for certain server cards
213 */
214
215static ssize_t amdgpu_device_get_serial_number(struct device *dev,
216 struct device_attribute *attr, char *buf)
217{
218 struct drm_device *ddev = dev_get_drvdata(dev);
219 struct amdgpu_device *adev = drm_to_adev(ddev);
220
221 return sysfs_emit(buf, "%s\n", adev->serial);
222}
223
224static DEVICE_ATTR(serial_number, S_IRUGO,
225 amdgpu_device_get_serial_number, NULL);
226
227/**
228 * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control
229 *
230 * @dev: drm_device pointer
231 *
232 * Returns true if the device is a dGPU with ATPX power control,
233 * otherwise return false.
234 */
235bool amdgpu_device_supports_px(struct drm_device *dev)
236{
237 struct amdgpu_device *adev = drm_to_adev(dev);
238
239 if ((adev->flags & AMD_IS_PX) && !amdgpu_is_atpx_hybrid())
240 return true;
241 return false;
242}
243
244/**
245 * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources
246 *
247 * @dev: drm_device pointer
248 *
249 * Returns true if the device is a dGPU with ACPI power control,
250 * otherwise return false.
251 */
252bool amdgpu_device_supports_boco(struct drm_device *dev)
253{
254 struct amdgpu_device *adev = drm_to_adev(dev);
255
256 if (adev->has_pr3 ||
257 ((adev->flags & AMD_IS_PX) && amdgpu_is_atpx_hybrid()))
258 return true;
259 return false;
260}
261
262/**
263 * amdgpu_device_supports_baco - Does the device support BACO
264 *
265 * @dev: drm_device pointer
266 *
267 * Returns true if the device supporte BACO,
268 * otherwise return false.
269 */
270bool amdgpu_device_supports_baco(struct drm_device *dev)
271{
272 struct amdgpu_device *adev = drm_to_adev(dev);
273
274 return amdgpu_asic_supports_baco(adev);
275}
276
277/**
278 * amdgpu_device_supports_smart_shift - Is the device dGPU with
279 * smart shift support
280 *
281 * @dev: drm_device pointer
282 *
283 * Returns true if the device is a dGPU with Smart Shift support,
284 * otherwise returns false.
285 */
286bool amdgpu_device_supports_smart_shift(struct drm_device *dev)
287{
288 return (amdgpu_device_supports_boco(dev) &&
289 amdgpu_acpi_is_power_shift_control_supported());
290}
291
292/*
293 * VRAM access helper functions
294 */
295
296/**
297 * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA
298 *
299 * @adev: amdgpu_device pointer
300 * @pos: offset of the buffer in vram
301 * @buf: virtual address of the buffer in system memory
302 * @size: read/write size, sizeof(@buf) must > @size
303 * @write: true - write to vram, otherwise - read from vram
304 */
305void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
306 void *buf, size_t size, bool write)
307{
308 unsigned long flags;
309 uint32_t hi = ~0, tmp = 0;
310 uint32_t *data = buf;
311 uint64_t last;
312 int idx;
313
314 if (!drm_dev_enter(adev_to_drm(adev), &idx))
315 return;
316
317 BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4));
318
319 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
320 for (last = pos + size; pos < last; pos += 4) {
321 tmp = pos >> 31;
322
323 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
324 if (tmp != hi) {
325 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
326 hi = tmp;
327 }
328 if (write)
329 WREG32_NO_KIQ(mmMM_DATA, *data++);
330 else
331 *data++ = RREG32_NO_KIQ(mmMM_DATA);
332 }
333
334 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
335 drm_dev_exit(idx);
336}
337
338/**
339 * amdgpu_device_aper_access - access vram by vram aperature
340 *
341 * @adev: amdgpu_device pointer
342 * @pos: offset of the buffer in vram
343 * @buf: virtual address of the buffer in system memory
344 * @size: read/write size, sizeof(@buf) must > @size
345 * @write: true - write to vram, otherwise - read from vram
346 *
347 * The return value means how many bytes have been transferred.
348 */
349size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
350 void *buf, size_t size, bool write)
351{
352#ifdef CONFIG_64BIT
353 void __iomem *addr;
354 size_t count = 0;
355 uint64_t last;
356
357 if (!adev->mman.aper_base_kaddr)
358 return 0;
359
360 last = min(pos + size, adev->gmc.visible_vram_size);
361 if (last > pos) {
362 addr = adev->mman.aper_base_kaddr + pos;
363 count = last - pos;
364
365 if (write) {
366 memcpy_toio(addr, buf, count);
367 mb();
368 amdgpu_device_flush_hdp(adev, NULL);
369 } else {
370 amdgpu_device_invalidate_hdp(adev, NULL);
371 mb();
372 memcpy_fromio(buf, addr, count);
373 }
374
375 }
376
377 return count;
378#else
379 return 0;
380#endif
381}
382
383/**
384 * amdgpu_device_vram_access - read/write a buffer in vram
385 *
386 * @adev: amdgpu_device pointer
387 * @pos: offset of the buffer in vram
388 * @buf: virtual address of the buffer in system memory
389 * @size: read/write size, sizeof(@buf) must > @size
390 * @write: true - write to vram, otherwise - read from vram
391 */
392void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
393 void *buf, size_t size, bool write)
394{
395 size_t count;
396
397 /* try to using vram apreature to access vram first */
398 count = amdgpu_device_aper_access(adev, pos, buf, size, write);
399 size -= count;
400 if (size) {
401 /* using MM to access rest vram */
402 pos += count;
403 buf += count;
404 amdgpu_device_mm_access(adev, pos, buf, size, write);
405 }
406}
407
408/*
409 * register access helper functions.
410 */
411
412/* Check if hw access should be skipped because of hotplug or device error */
413bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev)
414{
415 if (adev->no_hw_access)
416 return true;
417
418#ifdef CONFIG_LOCKDEP
419 /*
420 * This is a bit complicated to understand, so worth a comment. What we assert
421 * here is that the GPU reset is not running on another thread in parallel.
422 *
423 * For this we trylock the read side of the reset semaphore, if that succeeds
424 * we know that the reset is not running in paralell.
425 *
426 * If the trylock fails we assert that we are either already holding the read
427 * side of the lock or are the reset thread itself and hold the write side of
428 * the lock.
429 */
430 if (in_task()) {
431 if (down_read_trylock(&adev->reset_domain->sem))
432 up_read(&adev->reset_domain->sem);
433 else
434 lockdep_assert_held(&adev->reset_domain->sem);
435 }
436#endif
437 return false;
438}
439
440/**
441 * amdgpu_device_rreg - read a memory mapped IO or indirect register
442 *
443 * @adev: amdgpu_device pointer
444 * @reg: dword aligned register offset
445 * @acc_flags: access flags which require special behavior
446 *
447 * Returns the 32 bit value from the offset specified.
448 */
449uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
450 uint32_t reg, uint32_t acc_flags)
451{
452 uint32_t ret;
453
454 if (amdgpu_device_skip_hw_access(adev))
455 return 0;
456
457 if ((reg * 4) < adev->rmmio_size) {
458 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
459 amdgpu_sriov_runtime(adev) &&
460 down_read_trylock(&adev->reset_domain->sem)) {
461 ret = amdgpu_kiq_rreg(adev, reg);
462 up_read(&adev->reset_domain->sem);
463 } else {
464 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
465 }
466 } else {
467 ret = adev->pcie_rreg(adev, reg * 4);
468 }
469
470 trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);
471
472 return ret;
473}
474
475/*
476 * MMIO register read with bytes helper functions
477 * @offset:bytes offset from MMIO start
478 *
479*/
480
481/**
482 * amdgpu_mm_rreg8 - read a memory mapped IO register
483 *
484 * @adev: amdgpu_device pointer
485 * @offset: byte aligned register offset
486 *
487 * Returns the 8 bit value from the offset specified.
488 */
489uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset)
490{
491 if (amdgpu_device_skip_hw_access(adev))
492 return 0;
493
494 if (offset < adev->rmmio_size)
495 return (readb(adev->rmmio + offset));
496 BUG();
497}
498
499/*
500 * MMIO register write with bytes helper functions
501 * @offset:bytes offset from MMIO start
502 * @value: the value want to be written to the register
503 *
504*/
505/**
506 * amdgpu_mm_wreg8 - read a memory mapped IO register
507 *
508 * @adev: amdgpu_device pointer
509 * @offset: byte aligned register offset
510 * @value: 8 bit value to write
511 *
512 * Writes the value specified to the offset specified.
513 */
514void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value)
515{
516 if (amdgpu_device_skip_hw_access(adev))
517 return;
518
519 if (offset < adev->rmmio_size)
520 writeb(value, adev->rmmio + offset);
521 else
522 BUG();
523}
524
525/**
526 * amdgpu_device_wreg - write to a memory mapped IO or indirect register
527 *
528 * @adev: amdgpu_device pointer
529 * @reg: dword aligned register offset
530 * @v: 32 bit value to write to the register
531 * @acc_flags: access flags which require special behavior
532 *
533 * Writes the value specified to the offset specified.
534 */
535void amdgpu_device_wreg(struct amdgpu_device *adev,
536 uint32_t reg, uint32_t v,
537 uint32_t acc_flags)
538{
539 if (amdgpu_device_skip_hw_access(adev))
540 return;
541
542 if ((reg * 4) < adev->rmmio_size) {
543 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
544 amdgpu_sriov_runtime(adev) &&
545 down_read_trylock(&adev->reset_domain->sem)) {
546 amdgpu_kiq_wreg(adev, reg, v);
547 up_read(&adev->reset_domain->sem);
548 } else {
549 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
550 }
551 } else {
552 adev->pcie_wreg(adev, reg * 4, v);
553 }
554
555 trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
556}
557
558/**
559 * amdgpu_mm_wreg_mmio_rlc - write register either with direct/indirect mmio or with RLC path if in range
560 *
561 * @adev: amdgpu_device pointer
562 * @reg: mmio/rlc register
563 * @v: value to write
564 *
565 * this function is invoked only for the debugfs register access
566 */
567void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
568 uint32_t reg, uint32_t v)
569{
570 if (amdgpu_device_skip_hw_access(adev))
571 return;
572
573 if (amdgpu_sriov_fullaccess(adev) &&
574 adev->gfx.rlc.funcs &&
575 adev->gfx.rlc.funcs->is_rlcg_access_range) {
576 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
577 return amdgpu_sriov_wreg(adev, reg, v, 0, 0);
578 } else if ((reg * 4) >= adev->rmmio_size) {
579 adev->pcie_wreg(adev, reg * 4, v);
580 } else {
581 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
582 }
583}
584
585/**
586 * amdgpu_mm_rdoorbell - read a doorbell dword
587 *
588 * @adev: amdgpu_device pointer
589 * @index: doorbell index
590 *
591 * Returns the value in the doorbell aperture at the
592 * requested doorbell index (CIK).
593 */
594u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
595{
596 if (amdgpu_device_skip_hw_access(adev))
597 return 0;
598
599 if (index < adev->doorbell.num_doorbells) {
600 return readl(adev->doorbell.ptr + index);
601 } else {
602 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
603 return 0;
604 }
605}
606
607/**
608 * amdgpu_mm_wdoorbell - write a doorbell dword
609 *
610 * @adev: amdgpu_device pointer
611 * @index: doorbell index
612 * @v: value to write
613 *
614 * Writes @v to the doorbell aperture at the
615 * requested doorbell index (CIK).
616 */
617void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
618{
619 if (amdgpu_device_skip_hw_access(adev))
620 return;
621
622 if (index < adev->doorbell.num_doorbells) {
623 writel(v, adev->doorbell.ptr + index);
624 } else {
625 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
626 }
627}
628
629/**
630 * amdgpu_mm_rdoorbell64 - read a doorbell Qword
631 *
632 * @adev: amdgpu_device pointer
633 * @index: doorbell index
634 *
635 * Returns the value in the doorbell aperture at the
636 * requested doorbell index (VEGA10+).
637 */
638u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
639{
640 if (amdgpu_device_skip_hw_access(adev))
641 return 0;
642
643 if (index < adev->doorbell.num_doorbells) {
644 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
645 } else {
646 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
647 return 0;
648 }
649}
650
651/**
652 * amdgpu_mm_wdoorbell64 - write a doorbell Qword
653 *
654 * @adev: amdgpu_device pointer
655 * @index: doorbell index
656 * @v: value to write
657 *
658 * Writes @v to the doorbell aperture at the
659 * requested doorbell index (VEGA10+).
660 */
661void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
662{
663 if (amdgpu_device_skip_hw_access(adev))
664 return;
665
666 if (index < adev->doorbell.num_doorbells) {
667 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
668 } else {
669 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
670 }
671}
672
673/**
674 * amdgpu_device_indirect_rreg - read an indirect register
675 *
676 * @adev: amdgpu_device pointer
677 * @pcie_index: mmio register offset
678 * @pcie_data: mmio register offset
679 * @reg_addr: indirect register address to read from
680 *
681 * Returns the value of indirect register @reg_addr
682 */
683u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
684 u32 pcie_index, u32 pcie_data,
685 u32 reg_addr)
686{
687 unsigned long flags;
688 u32 r;
689 void __iomem *pcie_index_offset;
690 void __iomem *pcie_data_offset;
691
692 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
693 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
694 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
695
696 writel(reg_addr, pcie_index_offset);
697 readl(pcie_index_offset);
698 r = readl(pcie_data_offset);
699 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
700
701 return r;
702}
703
704/**
705 * amdgpu_device_indirect_rreg64 - read a 64bits indirect register
706 *
707 * @adev: amdgpu_device pointer
708 * @pcie_index: mmio register offset
709 * @pcie_data: mmio register offset
710 * @reg_addr: indirect register address to read from
711 *
712 * Returns the value of indirect register @reg_addr
713 */
714u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
715 u32 pcie_index, u32 pcie_data,
716 u32 reg_addr)
717{
718 unsigned long flags;
719 u64 r;
720 void __iomem *pcie_index_offset;
721 void __iomem *pcie_data_offset;
722
723 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
724 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
725 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
726
727 /* read low 32 bits */
728 writel(reg_addr, pcie_index_offset);
729 readl(pcie_index_offset);
730 r = readl(pcie_data_offset);
731 /* read high 32 bits */
732 writel(reg_addr + 4, pcie_index_offset);
733 readl(pcie_index_offset);
734 r |= ((u64)readl(pcie_data_offset) << 32);
735 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
736
737 return r;
738}
739
740/**
741 * amdgpu_device_indirect_wreg - write an indirect register address
742 *
743 * @adev: amdgpu_device pointer
744 * @pcie_index: mmio register offset
745 * @pcie_data: mmio register offset
746 * @reg_addr: indirect register offset
747 * @reg_data: indirect register data
748 *
749 */
750void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
751 u32 pcie_index, u32 pcie_data,
752 u32 reg_addr, u32 reg_data)
753{
754 unsigned long flags;
755 void __iomem *pcie_index_offset;
756 void __iomem *pcie_data_offset;
757
758 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
759 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
760 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
761
762 writel(reg_addr, pcie_index_offset);
763 readl(pcie_index_offset);
764 writel(reg_data, pcie_data_offset);
765 readl(pcie_data_offset);
766 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
767}
768
769/**
770 * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address
771 *
772 * @adev: amdgpu_device pointer
773 * @pcie_index: mmio register offset
774 * @pcie_data: mmio register offset
775 * @reg_addr: indirect register offset
776 * @reg_data: indirect register data
777 *
778 */
779void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
780 u32 pcie_index, u32 pcie_data,
781 u32 reg_addr, u64 reg_data)
782{
783 unsigned long flags;
784 void __iomem *pcie_index_offset;
785 void __iomem *pcie_data_offset;
786
787 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
788 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4;
789 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4;
790
791 /* write low 32 bits */
792 writel(reg_addr, pcie_index_offset);
793 readl(pcie_index_offset);
794 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
795 readl(pcie_data_offset);
796 /* write high 32 bits */
797 writel(reg_addr + 4, pcie_index_offset);
798 readl(pcie_index_offset);
799 writel((u32)(reg_data >> 32), pcie_data_offset);
800 readl(pcie_data_offset);
801 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
802}
803
804/**
805 * amdgpu_invalid_rreg - dummy reg read function
806 *
807 * @adev: amdgpu_device pointer
808 * @reg: offset of register
809 *
810 * Dummy register read function. Used for register blocks
811 * that certain asics don't have (all asics).
812 * Returns the value in the register.
813 */
814static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
815{
816 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
817 BUG();
818 return 0;
819}
820
821/**
822 * amdgpu_invalid_wreg - dummy reg write function
823 *
824 * @adev: amdgpu_device pointer
825 * @reg: offset of register
826 * @v: value to write to the register
827 *
828 * Dummy register read function. Used for register blocks
829 * that certain asics don't have (all asics).
830 */
831static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
832{
833 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
834 reg, v);
835 BUG();
836}
837
838/**
839 * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
840 *
841 * @adev: amdgpu_device pointer
842 * @reg: offset of register
843 *
844 * Dummy register read function. Used for register blocks
845 * that certain asics don't have (all asics).
846 * Returns the value in the register.
847 */
848static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
849{
850 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
851 BUG();
852 return 0;
853}
854
855/**
856 * amdgpu_invalid_wreg64 - dummy reg write function
857 *
858 * @adev: amdgpu_device pointer
859 * @reg: offset of register
860 * @v: value to write to the register
861 *
862 * Dummy register read function. Used for register blocks
863 * that certain asics don't have (all asics).
864 */
865static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
866{
867 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
868 reg, v);
869 BUG();
870}
871
872/**
873 * amdgpu_block_invalid_rreg - dummy reg read function
874 *
875 * @adev: amdgpu_device pointer
876 * @block: offset of instance
877 * @reg: offset of register
878 *
879 * Dummy register read function. Used for register blocks
880 * that certain asics don't have (all asics).
881 * Returns the value in the register.
882 */
883static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
884 uint32_t block, uint32_t reg)
885{
886 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
887 reg, block);
888 BUG();
889 return 0;
890}
891
892/**
893 * amdgpu_block_invalid_wreg - dummy reg write function
894 *
895 * @adev: amdgpu_device pointer
896 * @block: offset of instance
897 * @reg: offset of register
898 * @v: value to write to the register
899 *
900 * Dummy register read function. Used for register blocks
901 * that certain asics don't have (all asics).
902 */
903static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
904 uint32_t block,
905 uint32_t reg, uint32_t v)
906{
907 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
908 reg, block, v);
909 BUG();
910}
911
912/**
913 * amdgpu_device_asic_init - Wrapper for atom asic_init
914 *
915 * @adev: amdgpu_device pointer
916 *
917 * Does any asic specific work and then calls atom asic init.
918 */
919static int amdgpu_device_asic_init(struct amdgpu_device *adev)
920{
921 amdgpu_asic_pre_asic_init(adev);
922
923 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0))
924 return amdgpu_atomfirmware_asic_init(adev, true);
925 else
926 return amdgpu_atom_asic_init(adev->mode_info.atom_context);
927}
928
929/**
930 * amdgpu_device_vram_scratch_init - allocate the VRAM scratch page
931 *
932 * @adev: amdgpu_device pointer
933 *
934 * Allocates a scratch page of VRAM for use by various things in the
935 * driver.
936 */
937static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
938{
939 return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
940 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
941 &adev->vram_scratch.robj,
942 &adev->vram_scratch.gpu_addr,
943 (void **)&adev->vram_scratch.ptr);
944}
945
946/**
947 * amdgpu_device_vram_scratch_fini - Free the VRAM scratch page
948 *
949 * @adev: amdgpu_device pointer
950 *
951 * Frees the VRAM scratch page.
952 */
953static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
954{
955 amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
956}
957
958/**
959 * amdgpu_device_program_register_sequence - program an array of registers.
960 *
961 * @adev: amdgpu_device pointer
962 * @registers: pointer to the register array
963 * @array_size: size of the register array
964 *
965 * Programs an array or registers with and and or masks.
966 * This is a helper for setting golden registers.
967 */
968void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
969 const u32 *registers,
970 const u32 array_size)
971{
972 u32 tmp, reg, and_mask, or_mask;
973 int i;
974
975 if (array_size % 3)
976 return;
977
978 for (i = 0; i < array_size; i +=3) {
979 reg = registers[i + 0];
980 and_mask = registers[i + 1];
981 or_mask = registers[i + 2];
982
983 if (and_mask == 0xffffffff) {
984 tmp = or_mask;
985 } else {
986 tmp = RREG32(reg);
987 tmp &= ~and_mask;
988 if (adev->family >= AMDGPU_FAMILY_AI)
989 tmp |= (or_mask & and_mask);
990 else
991 tmp |= or_mask;
992 }
993 WREG32(reg, tmp);
994 }
995}
996
997/**
998 * amdgpu_device_pci_config_reset - reset the GPU
999 *
1000 * @adev: amdgpu_device pointer
1001 *
1002 * Resets the GPU using the pci config reset sequence.
1003 * Only applicable to asics prior to vega10.
1004 */
1005void amdgpu_device_pci_config_reset(struct amdgpu_device *adev)
1006{
1007 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
1008}
1009
1010/**
1011 * amdgpu_device_pci_reset - reset the GPU using generic PCI means
1012 *
1013 * @adev: amdgpu_device pointer
1014 *
1015 * Resets the GPU using generic pci reset interfaces (FLR, SBR, etc.).
1016 */
1017int amdgpu_device_pci_reset(struct amdgpu_device *adev)
1018{
1019 return pci_reset_function(adev->pdev);
1020}
1021
1022/*
1023 * GPU doorbell aperture helpers function.
1024 */
1025/**
1026 * amdgpu_device_doorbell_init - Init doorbell driver information.
1027 *
1028 * @adev: amdgpu_device pointer
1029 *
1030 * Init doorbell driver information (CIK)
1031 * Returns 0 on success, error on failure.
1032 */
1033static int amdgpu_device_doorbell_init(struct amdgpu_device *adev)
1034{
1035
1036 /* No doorbell on SI hardware generation */
1037 if (adev->asic_type < CHIP_BONAIRE) {
1038 adev->doorbell.base = 0;
1039 adev->doorbell.size = 0;
1040 adev->doorbell.num_doorbells = 0;
1041 adev->doorbell.ptr = NULL;
1042 return 0;
1043 }
1044
1045 if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
1046 return -EINVAL;
1047
1048 amdgpu_asic_init_doorbell_index(adev);
1049
1050 /* doorbell bar mapping */
1051 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
1052 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
1053
1054 if (adev->enable_mes) {
1055 adev->doorbell.num_doorbells =
1056 adev->doorbell.size / sizeof(u32);
1057 } else {
1058 adev->doorbell.num_doorbells =
1059 min_t(u32, adev->doorbell.size / sizeof(u32),
1060 adev->doorbell_index.max_assignment+1);
1061 if (adev->doorbell.num_doorbells == 0)
1062 return -EINVAL;
1063
1064 /* For Vega, reserve and map two pages on doorbell BAR since SDMA
1065 * paging queue doorbell use the second page. The
1066 * AMDGPU_DOORBELL64_MAX_ASSIGNMENT definition assumes all the
1067 * doorbells are in the first page. So with paging queue enabled,
1068 * the max num_doorbells should + 1 page (0x400 in dword)
1069 */
1070 if (adev->asic_type >= CHIP_VEGA10)
1071 adev->doorbell.num_doorbells += 0x400;
1072 }
1073
1074 adev->doorbell.ptr = ioremap(adev->doorbell.base,
1075 adev->doorbell.num_doorbells *
1076 sizeof(u32));
1077 if (adev->doorbell.ptr == NULL)
1078 return -ENOMEM;
1079
1080 return 0;
1081}
1082
1083/**
1084 * amdgpu_device_doorbell_fini - Tear down doorbell driver information.
1085 *
1086 * @adev: amdgpu_device pointer
1087 *
1088 * Tear down doorbell driver information (CIK)
1089 */
1090static void amdgpu_device_doorbell_fini(struct amdgpu_device *adev)
1091{
1092 iounmap(adev->doorbell.ptr);
1093 adev->doorbell.ptr = NULL;
1094}
1095
1096
1097
1098/*
1099 * amdgpu_device_wb_*()
1100 * Writeback is the method by which the GPU updates special pages in memory
1101 * with the status of certain GPU events (fences, ring pointers,etc.).
1102 */
1103
1104/**
1105 * amdgpu_device_wb_fini - Disable Writeback and free memory
1106 *
1107 * @adev: amdgpu_device pointer
1108 *
1109 * Disables Writeback and frees the Writeback memory (all asics).
1110 * Used at driver shutdown.
1111 */
1112static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
1113{
1114 if (adev->wb.wb_obj) {
1115 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
1116 &adev->wb.gpu_addr,
1117 (void **)&adev->wb.wb);
1118 adev->wb.wb_obj = NULL;
1119 }
1120}
1121
1122/**
1123 * amdgpu_device_wb_init - Init Writeback driver info and allocate memory
1124 *
1125 * @adev: amdgpu_device pointer
1126 *
1127 * Initializes writeback and allocates writeback memory (all asics).
1128 * Used at driver startup.
1129 * Returns 0 on success or an -error on failure.
1130 */
1131static int amdgpu_device_wb_init(struct amdgpu_device *adev)
1132{
1133 int r;
1134
1135 if (adev->wb.wb_obj == NULL) {
1136 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
1137 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
1138 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1139 &adev->wb.wb_obj, &adev->wb.gpu_addr,
1140 (void **)&adev->wb.wb);
1141 if (r) {
1142 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
1143 return r;
1144 }
1145
1146 adev->wb.num_wb = AMDGPU_MAX_WB;
1147 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
1148
1149 /* clear wb memory */
1150 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
1151 }
1152
1153 return 0;
1154}
1155
1156/**
1157 * amdgpu_device_wb_get - Allocate a wb entry
1158 *
1159 * @adev: amdgpu_device pointer
1160 * @wb: wb index
1161 *
1162 * Allocate a wb slot for use by the driver (all asics).
1163 * Returns 0 on success or -EINVAL on failure.
1164 */
1165int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
1166{
1167 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
1168
1169 if (offset < adev->wb.num_wb) {
1170 __set_bit(offset, adev->wb.used);
1171 *wb = offset << 3; /* convert to dw offset */
1172 return 0;
1173 } else {
1174 return -EINVAL;
1175 }
1176}
1177
1178/**
1179 * amdgpu_device_wb_free - Free a wb entry
1180 *
1181 * @adev: amdgpu_device pointer
1182 * @wb: wb index
1183 *
1184 * Free a wb slot allocated for use by the driver (all asics)
1185 */
1186void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
1187{
1188 wb >>= 3;
1189 if (wb < adev->wb.num_wb)
1190 __clear_bit(wb, adev->wb.used);
1191}
1192
1193/**
1194 * amdgpu_device_resize_fb_bar - try to resize FB BAR
1195 *
1196 * @adev: amdgpu_device pointer
1197 *
1198 * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
1199 * to fail, but if any of the BARs is not accessible after the size we abort
1200 * driver loading by returning -ENODEV.
1201 */
1202int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
1203{
1204 int rbar_size = pci_rebar_bytes_to_size(adev->gmc.real_vram_size);
1205 struct pci_bus *root;
1206 struct resource *res;
1207 unsigned i;
1208 u16 cmd;
1209 int r;
1210
1211 /* Bypass for VF */
1212 if (amdgpu_sriov_vf(adev))
1213 return 0;
1214
1215 /* skip if the bios has already enabled large BAR */
1216 if (adev->gmc.real_vram_size &&
1217 (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
1218 return 0;
1219
1220 /* Check if the root BUS has 64bit memory resources */
1221 root = adev->pdev->bus;
1222 while (root->parent)
1223 root = root->parent;
1224
1225 pci_bus_for_each_resource(root, res, i) {
1226 if (res && res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
1227 res->start > 0x100000000ull)
1228 break;
1229 }
1230
1231 /* Trying to resize is pointless without a root hub window above 4GB */
1232 if (!res)
1233 return 0;
1234
1235 /* Limit the BAR size to what is available */
1236 rbar_size = min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1,
1237 rbar_size);
1238
1239 /* Disable memory decoding while we change the BAR addresses and size */
1240 pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
1241 pci_write_config_word(adev->pdev, PCI_COMMAND,
1242 cmd & ~PCI_COMMAND_MEMORY);
1243
1244 /* Free the VRAM and doorbell BAR, we most likely need to move both. */
1245 amdgpu_device_doorbell_fini(adev);
1246 if (adev->asic_type >= CHIP_BONAIRE)
1247 pci_release_resource(adev->pdev, 2);
1248
1249 pci_release_resource(adev->pdev, 0);
1250
1251 r = pci_resize_resource(adev->pdev, 0, rbar_size);
1252 if (r == -ENOSPC)
1253 DRM_INFO("Not enough PCI address space for a large BAR.");
1254 else if (r && r != -ENOTSUPP)
1255 DRM_ERROR("Problem resizing BAR0 (%d).", r);
1256
1257 pci_assign_unassigned_bus_resources(adev->pdev->bus);
1258
1259 /* When the doorbell or fb BAR isn't available we have no chance of
1260 * using the device.
1261 */
1262 r = amdgpu_device_doorbell_init(adev);
1263 if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
1264 return -ENODEV;
1265
1266 pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
1267
1268 return 0;
1269}
1270
1271/*
1272 * GPU helpers function.
1273 */
1274/**
1275 * amdgpu_device_need_post - check if the hw need post or not
1276 *
1277 * @adev: amdgpu_device pointer
1278 *
1279 * Check if the asic has been initialized (all asics) at driver startup
1280 * or post is needed if hw reset is performed.
1281 * Returns true if need or false if not.
1282 */
1283bool amdgpu_device_need_post(struct amdgpu_device *adev)
1284{
1285 uint32_t reg;
1286
1287 if (amdgpu_sriov_vf(adev))
1288 return false;
1289
1290 if (amdgpu_passthrough(adev)) {
1291 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
1292 * some old smc fw still need driver do vPost otherwise gpu hang, while
1293 * those smc fw version above 22.15 doesn't have this flaw, so we force
1294 * vpost executed for smc version below 22.15
1295 */
1296 if (adev->asic_type == CHIP_FIJI) {
1297 int err;
1298 uint32_t fw_ver;
1299 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
1300 /* force vPost if error occured */
1301 if (err)
1302 return true;
1303
1304 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
1305 if (fw_ver < 0x00160e00)
1306 return true;
1307 }
1308 }
1309
1310 /* Don't post if we need to reset whole hive on init */
1311 if (adev->gmc.xgmi.pending_reset)
1312 return false;
1313
1314 if (adev->has_hw_reset) {
1315 adev->has_hw_reset = false;
1316 return true;
1317 }
1318
1319 /* bios scratch used on CIK+ */
1320 if (adev->asic_type >= CHIP_BONAIRE)
1321 return amdgpu_atombios_scratch_need_asic_init(adev);
1322
1323 /* check MEM_SIZE for older asics */
1324 reg = amdgpu_asic_get_config_memsize(adev);
1325
1326 if ((reg != 0) && (reg != 0xffffffff))
1327 return false;
1328
1329 return true;
1330}
1331
1332/**
1333 * amdgpu_device_should_use_aspm - check if the device should program ASPM
1334 *
1335 * @adev: amdgpu_device pointer
1336 *
1337 * Confirm whether the module parameter and pcie bridge agree that ASPM should
1338 * be set for this device.
1339 *
1340 * Returns true if it should be used or false if not.
1341 */
1342bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev)
1343{
1344 switch (amdgpu_aspm) {
1345 case -1:
1346 break;
1347 case 0:
1348 return false;
1349 case 1:
1350 return true;
1351 default:
1352 return false;
1353 }
1354 return pcie_aspm_enabled(adev->pdev);
1355}
1356
1357/* if we get transitioned to only one device, take VGA back */
1358/**
1359 * amdgpu_device_vga_set_decode - enable/disable vga decode
1360 *
1361 * @pdev: PCI device pointer
1362 * @state: enable/disable vga decode
1363 *
1364 * Enable/disable vga decode (all asics).
1365 * Returns VGA resource flags.
1366 */
1367static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev,
1368 bool state)
1369{
1370 struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev));
1371 amdgpu_asic_set_vga_state(adev, state);
1372 if (state)
1373 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1374 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1375 else
1376 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1377}
1378
1379/**
1380 * amdgpu_device_check_block_size - validate the vm block size
1381 *
1382 * @adev: amdgpu_device pointer
1383 *
1384 * Validates the vm block size specified via module parameter.
1385 * The vm block size defines number of bits in page table versus page directory,
1386 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1387 * page table and the remaining bits are in the page directory.
1388 */
1389static void amdgpu_device_check_block_size(struct amdgpu_device *adev)
1390{
1391 /* defines number of bits in page table versus page directory,
1392 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1393 * page table and the remaining bits are in the page directory */
1394 if (amdgpu_vm_block_size == -1)
1395 return;
1396
1397 if (amdgpu_vm_block_size < 9) {
1398 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1399 amdgpu_vm_block_size);
1400 amdgpu_vm_block_size = -1;
1401 }
1402}
1403
1404/**
1405 * amdgpu_device_check_vm_size - validate the vm size
1406 *
1407 * @adev: amdgpu_device pointer
1408 *
1409 * Validates the vm size in GB specified via module parameter.
1410 * The VM size is the size of the GPU virtual memory space in GB.
1411 */
1412static void amdgpu_device_check_vm_size(struct amdgpu_device *adev)
1413{
1414 /* no need to check the default value */
1415 if (amdgpu_vm_size == -1)
1416 return;
1417
1418 if (amdgpu_vm_size < 1) {
1419 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1420 amdgpu_vm_size);
1421 amdgpu_vm_size = -1;
1422 }
1423}
1424
1425static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
1426{
1427 struct sysinfo si;
1428 bool is_os_64 = (sizeof(void *) == 8);
1429 uint64_t total_memory;
1430 uint64_t dram_size_seven_GB = 0x1B8000000;
1431 uint64_t dram_size_three_GB = 0xB8000000;
1432
1433 if (amdgpu_smu_memory_pool_size == 0)
1434 return;
1435
1436 if (!is_os_64) {
1437 DRM_WARN("Not 64-bit OS, feature not supported\n");
1438 goto def_value;
1439 }
1440 si_meminfo(&si);
1441 total_memory = (uint64_t)si.totalram * si.mem_unit;
1442
1443 if ((amdgpu_smu_memory_pool_size == 1) ||
1444 (amdgpu_smu_memory_pool_size == 2)) {
1445 if (total_memory < dram_size_three_GB)
1446 goto def_value1;
1447 } else if ((amdgpu_smu_memory_pool_size == 4) ||
1448 (amdgpu_smu_memory_pool_size == 8)) {
1449 if (total_memory < dram_size_seven_GB)
1450 goto def_value1;
1451 } else {
1452 DRM_WARN("Smu memory pool size not supported\n");
1453 goto def_value;
1454 }
1455 adev->pm.smu_prv_buffer_size = amdgpu_smu_memory_pool_size << 28;
1456
1457 return;
1458
1459def_value1:
1460 DRM_WARN("No enough system memory\n");
1461def_value:
1462 adev->pm.smu_prv_buffer_size = 0;
1463}
1464
1465static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev)
1466{
1467 if (!(adev->flags & AMD_IS_APU) ||
1468 adev->asic_type < CHIP_RAVEN)
1469 return 0;
1470
1471 switch (adev->asic_type) {
1472 case CHIP_RAVEN:
1473 if (adev->pdev->device == 0x15dd)
1474 adev->apu_flags |= AMD_APU_IS_RAVEN;
1475 if (adev->pdev->device == 0x15d8)
1476 adev->apu_flags |= AMD_APU_IS_PICASSO;
1477 break;
1478 case CHIP_RENOIR:
1479 if ((adev->pdev->device == 0x1636) ||
1480 (adev->pdev->device == 0x164c))
1481 adev->apu_flags |= AMD_APU_IS_RENOIR;
1482 else
1483 adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
1484 break;
1485 case CHIP_VANGOGH:
1486 adev->apu_flags |= AMD_APU_IS_VANGOGH;
1487 break;
1488 case CHIP_YELLOW_CARP:
1489 break;
1490 case CHIP_CYAN_SKILLFISH:
1491 if ((adev->pdev->device == 0x13FE) ||
1492 (adev->pdev->device == 0x143F))
1493 adev->apu_flags |= AMD_APU_IS_CYAN_SKILLFISH2;
1494 break;
1495 default:
1496 break;
1497 }
1498
1499 return 0;
1500}
1501
1502/**
1503 * amdgpu_device_check_arguments - validate module params
1504 *
1505 * @adev: amdgpu_device pointer
1506 *
1507 * Validates certain module parameters and updates
1508 * the associated values used by the driver (all asics).
1509 */
1510static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
1511{
1512 if (amdgpu_sched_jobs < 4) {
1513 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1514 amdgpu_sched_jobs);
1515 amdgpu_sched_jobs = 4;
1516 } else if (!is_power_of_2(amdgpu_sched_jobs)){
1517 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1518 amdgpu_sched_jobs);
1519 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1520 }
1521
1522 if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1523 /* gart size must be greater or equal to 32M */
1524 dev_warn(adev->dev, "gart size (%d) too small\n",
1525 amdgpu_gart_size);
1526 amdgpu_gart_size = -1;
1527 }
1528
1529 if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1530 /* gtt size must be greater or equal to 32M */
1531 dev_warn(adev->dev, "gtt size (%d) too small\n",
1532 amdgpu_gtt_size);
1533 amdgpu_gtt_size = -1;
1534 }
1535
1536 /* valid range is between 4 and 9 inclusive */
1537 if (amdgpu_vm_fragment_size != -1 &&
1538 (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1539 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1540 amdgpu_vm_fragment_size = -1;
1541 }
1542
1543 if (amdgpu_sched_hw_submission < 2) {
1544 dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n",
1545 amdgpu_sched_hw_submission);
1546 amdgpu_sched_hw_submission = 2;
1547 } else if (!is_power_of_2(amdgpu_sched_hw_submission)) {
1548 dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n",
1549 amdgpu_sched_hw_submission);
1550 amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission);
1551 }
1552
1553 if (amdgpu_reset_method < -1 || amdgpu_reset_method > 4) {
1554 dev_warn(adev->dev, "invalid option for reset method, reverting to default\n");
1555 amdgpu_reset_method = -1;
1556 }
1557
1558 amdgpu_device_check_smu_prv_buffer_size(adev);
1559
1560 amdgpu_device_check_vm_size(adev);
1561
1562 amdgpu_device_check_block_size(adev);
1563
1564 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1565
1566 return 0;
1567}
1568
1569/**
1570 * amdgpu_switcheroo_set_state - set switcheroo state
1571 *
1572 * @pdev: pci dev pointer
1573 * @state: vga_switcheroo state
1574 *
1575 * Callback for the switcheroo driver. Suspends or resumes
1576 * the asics before or after it is powered up using ACPI methods.
1577 */
1578static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,
1579 enum vga_switcheroo_state state)
1580{
1581 struct drm_device *dev = pci_get_drvdata(pdev);
1582 int r;
1583
1584 if (amdgpu_device_supports_px(dev) && state == VGA_SWITCHEROO_OFF)
1585 return;
1586
1587 if (state == VGA_SWITCHEROO_ON) {
1588 pr_info("switched on\n");
1589 /* don't suspend or resume card normally */
1590 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1591
1592 pci_set_power_state(pdev, PCI_D0);
1593 amdgpu_device_load_pci_state(pdev);
1594 r = pci_enable_device(pdev);
1595 if (r)
1596 DRM_WARN("pci_enable_device failed (%d)\n", r);
1597 amdgpu_device_resume(dev, true);
1598
1599 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1600 } else {
1601 pr_info("switched off\n");
1602 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1603 amdgpu_device_suspend(dev, true);
1604 amdgpu_device_cache_pci_state(pdev);
1605 /* Shut down the device */
1606 pci_disable_device(pdev);
1607 pci_set_power_state(pdev, PCI_D3cold);
1608 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1609 }
1610}
1611
1612/**
1613 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1614 *
1615 * @pdev: pci dev pointer
1616 *
1617 * Callback for the switcheroo driver. Check of the switcheroo
1618 * state can be changed.
1619 * Returns true if the state can be changed, false if not.
1620 */
1621static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1622{
1623 struct drm_device *dev = pci_get_drvdata(pdev);
1624
1625 /*
1626 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1627 * locking inversion with the driver load path. And the access here is
1628 * completely racy anyway. So don't bother with locking for now.
1629 */
1630 return atomic_read(&dev->open_count) == 0;
1631}
1632
1633static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1634 .set_gpu_state = amdgpu_switcheroo_set_state,
1635 .reprobe = NULL,
1636 .can_switch = amdgpu_switcheroo_can_switch,
1637};
1638
1639/**
1640 * amdgpu_device_ip_set_clockgating_state - set the CG state
1641 *
1642 * @dev: amdgpu_device pointer
1643 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1644 * @state: clockgating state (gate or ungate)
1645 *
1646 * Sets the requested clockgating state for all instances of
1647 * the hardware IP specified.
1648 * Returns the error code from the last instance.
1649 */
1650int amdgpu_device_ip_set_clockgating_state(void *dev,
1651 enum amd_ip_block_type block_type,
1652 enum amd_clockgating_state state)
1653{
1654 struct amdgpu_device *adev = dev;
1655 int i, r = 0;
1656
1657 for (i = 0; i < adev->num_ip_blocks; i++) {
1658 if (!adev->ip_blocks[i].status.valid)
1659 continue;
1660 if (adev->ip_blocks[i].version->type != block_type)
1661 continue;
1662 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1663 continue;
1664 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1665 (void *)adev, state);
1666 if (r)
1667 DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1668 adev->ip_blocks[i].version->funcs->name, r);
1669 }
1670 return r;
1671}
1672
1673/**
1674 * amdgpu_device_ip_set_powergating_state - set the PG state
1675 *
1676 * @dev: amdgpu_device pointer
1677 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1678 * @state: powergating state (gate or ungate)
1679 *
1680 * Sets the requested powergating state for all instances of
1681 * the hardware IP specified.
1682 * Returns the error code from the last instance.
1683 */
1684int amdgpu_device_ip_set_powergating_state(void *dev,
1685 enum amd_ip_block_type block_type,
1686 enum amd_powergating_state state)
1687{
1688 struct amdgpu_device *adev = dev;
1689 int i, r = 0;
1690
1691 for (i = 0; i < adev->num_ip_blocks; i++) {
1692 if (!adev->ip_blocks[i].status.valid)
1693 continue;
1694 if (adev->ip_blocks[i].version->type != block_type)
1695 continue;
1696 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1697 continue;
1698 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1699 (void *)adev, state);
1700 if (r)
1701 DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1702 adev->ip_blocks[i].version->funcs->name, r);
1703 }
1704 return r;
1705}
1706
1707/**
1708 * amdgpu_device_ip_get_clockgating_state - get the CG state
1709 *
1710 * @adev: amdgpu_device pointer
1711 * @flags: clockgating feature flags
1712 *
1713 * Walks the list of IPs on the device and updates the clockgating
1714 * flags for each IP.
1715 * Updates @flags with the feature flags for each hardware IP where
1716 * clockgating is enabled.
1717 */
1718void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
1719 u64 *flags)
1720{
1721 int i;
1722
1723 for (i = 0; i < adev->num_ip_blocks; i++) {
1724 if (!adev->ip_blocks[i].status.valid)
1725 continue;
1726 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1727 adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1728 }
1729}
1730
1731/**
1732 * amdgpu_device_ip_wait_for_idle - wait for idle
1733 *
1734 * @adev: amdgpu_device pointer
1735 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1736 *
1737 * Waits for the request hardware IP to be idle.
1738 * Returns 0 for success or a negative error code on failure.
1739 */
1740int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
1741 enum amd_ip_block_type block_type)
1742{
1743 int i, r;
1744
1745 for (i = 0; i < adev->num_ip_blocks; i++) {
1746 if (!adev->ip_blocks[i].status.valid)
1747 continue;
1748 if (adev->ip_blocks[i].version->type == block_type) {
1749 r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1750 if (r)
1751 return r;
1752 break;
1753 }
1754 }
1755 return 0;
1756
1757}
1758
1759/**
1760 * amdgpu_device_ip_is_idle - is the hardware IP idle
1761 *
1762 * @adev: amdgpu_device pointer
1763 * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
1764 *
1765 * Check if the hardware IP is idle or not.
1766 * Returns true if it the IP is idle, false if not.
1767 */
1768bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
1769 enum amd_ip_block_type block_type)
1770{
1771 int i;
1772
1773 for (i = 0; i < adev->num_ip_blocks; i++) {
1774 if (!adev->ip_blocks[i].status.valid)
1775 continue;
1776 if (adev->ip_blocks[i].version->type == block_type)
1777 return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1778 }
1779 return true;
1780
1781}
1782
1783/**
1784 * amdgpu_device_ip_get_ip_block - get a hw IP pointer
1785 *
1786 * @adev: amdgpu_device pointer
1787 * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
1788 *
1789 * Returns a pointer to the hardware IP block structure
1790 * if it exists for the asic, otherwise NULL.
1791 */
1792struct amdgpu_ip_block *
1793amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
1794 enum amd_ip_block_type type)
1795{
1796 int i;
1797
1798 for (i = 0; i < adev->num_ip_blocks; i++)
1799 if (adev->ip_blocks[i].version->type == type)
1800 return &adev->ip_blocks[i];
1801
1802 return NULL;
1803}
1804
1805/**
1806 * amdgpu_device_ip_block_version_cmp
1807 *
1808 * @adev: amdgpu_device pointer
1809 * @type: enum amd_ip_block_type
1810 * @major: major version
1811 * @minor: minor version
1812 *
1813 * return 0 if equal or greater
1814 * return 1 if smaller or the ip_block doesn't exist
1815 */
1816int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
1817 enum amd_ip_block_type type,
1818 u32 major, u32 minor)
1819{
1820 struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
1821
1822 if (ip_block && ((ip_block->version->major > major) ||
1823 ((ip_block->version->major == major) &&
1824 (ip_block->version->minor >= minor))))
1825 return 0;
1826
1827 return 1;
1828}
1829
1830/**
1831 * amdgpu_device_ip_block_add
1832 *
1833 * @adev: amdgpu_device pointer
1834 * @ip_block_version: pointer to the IP to add
1835 *
1836 * Adds the IP block driver information to the collection of IPs
1837 * on the asic.
1838 */
1839int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
1840 const struct amdgpu_ip_block_version *ip_block_version)
1841{
1842 if (!ip_block_version)
1843 return -EINVAL;
1844
1845 switch (ip_block_version->type) {
1846 case AMD_IP_BLOCK_TYPE_VCN:
1847 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
1848 return 0;
1849 break;
1850 case AMD_IP_BLOCK_TYPE_JPEG:
1851 if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK)
1852 return 0;
1853 break;
1854 default:
1855 break;
1856 }
1857
1858 DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
1859 ip_block_version->funcs->name);
1860
1861 adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1862
1863 return 0;
1864}
1865
1866/**
1867 * amdgpu_device_enable_virtual_display - enable virtual display feature
1868 *
1869 * @adev: amdgpu_device pointer
1870 *
1871 * Enabled the virtual display feature if the user has enabled it via
1872 * the module parameter virtual_display. This feature provides a virtual
1873 * display hardware on headless boards or in virtualized environments.
1874 * This function parses and validates the configuration string specified by
1875 * the user and configues the virtual display configuration (number of
1876 * virtual connectors, crtcs, etc.) specified.
1877 */
1878static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1879{
1880 adev->enable_virtual_display = false;
1881
1882 if (amdgpu_virtual_display) {
1883 const char *pci_address_name = pci_name(adev->pdev);
1884 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1885
1886 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1887 pciaddstr_tmp = pciaddstr;
1888 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1889 pciaddname = strsep(&pciaddname_tmp, ",");
1890 if (!strcmp("all", pciaddname)
1891 || !strcmp(pci_address_name, pciaddname)) {
1892 long num_crtc;
1893 int res = -1;
1894
1895 adev->enable_virtual_display = true;
1896
1897 if (pciaddname_tmp)
1898 res = kstrtol(pciaddname_tmp, 10,
1899 &num_crtc);
1900
1901 if (!res) {
1902 if (num_crtc < 1)
1903 num_crtc = 1;
1904 if (num_crtc > 6)
1905 num_crtc = 6;
1906 adev->mode_info.num_crtc = num_crtc;
1907 } else {
1908 adev->mode_info.num_crtc = 1;
1909 }
1910 break;
1911 }
1912 }
1913
1914 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1915 amdgpu_virtual_display, pci_address_name,
1916 adev->enable_virtual_display, adev->mode_info.num_crtc);
1917
1918 kfree(pciaddstr);
1919 }
1920}
1921
1922void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev)
1923{
1924 if (amdgpu_sriov_vf(adev) && !adev->enable_virtual_display) {
1925 adev->mode_info.num_crtc = 1;
1926 adev->enable_virtual_display = true;
1927 DRM_INFO("virtual_display:%d, num_crtc:%d\n",
1928 adev->enable_virtual_display, adev->mode_info.num_crtc);
1929 }
1930}
1931
1932/**
1933 * amdgpu_device_parse_gpu_info_fw - parse gpu info firmware
1934 *
1935 * @adev: amdgpu_device pointer
1936 *
1937 * Parses the asic configuration parameters specified in the gpu info
1938 * firmware and makes them availale to the driver for use in configuring
1939 * the asic.
1940 * Returns 0 on success, -EINVAL on failure.
1941 */
1942static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1943{
1944 const char *chip_name;
1945 char fw_name[40];
1946 int err;
1947 const struct gpu_info_firmware_header_v1_0 *hdr;
1948
1949 adev->firmware.gpu_info_fw = NULL;
1950
1951 if (adev->mman.discovery_bin) {
1952 /*
1953 * FIXME: The bounding box is still needed by Navi12, so
1954 * temporarily read it from gpu_info firmware. Should be dropped
1955 * when DAL no longer needs it.
1956 */
1957 if (adev->asic_type != CHIP_NAVI12)
1958 return 0;
1959 }
1960
1961 switch (adev->asic_type) {
1962 default:
1963 return 0;
1964 case CHIP_VEGA10:
1965 chip_name = "vega10";
1966 break;
1967 case CHIP_VEGA12:
1968 chip_name = "vega12";
1969 break;
1970 case CHIP_RAVEN:
1971 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1972 chip_name = "raven2";
1973 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1974 chip_name = "picasso";
1975 else
1976 chip_name = "raven";
1977 break;
1978 case CHIP_ARCTURUS:
1979 chip_name = "arcturus";
1980 break;
1981 case CHIP_NAVI12:
1982 chip_name = "navi12";
1983 break;
1984 }
1985
1986 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1987 err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1988 if (err) {
1989 dev_err(adev->dev,
1990 "Failed to load gpu_info firmware \"%s\"\n",
1991 fw_name);
1992 goto out;
1993 }
1994 err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1995 if (err) {
1996 dev_err(adev->dev,
1997 "Failed to validate gpu_info firmware \"%s\"\n",
1998 fw_name);
1999 goto out;
2000 }
2001
2002 hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
2003 amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
2004
2005 switch (hdr->version_major) {
2006 case 1:
2007 {
2008 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
2009 (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
2010 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2011
2012 /*
2013 * Should be droped when DAL no longer needs it.
2014 */
2015 if (adev->asic_type == CHIP_NAVI12)
2016 goto parse_soc_bounding_box;
2017
2018 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
2019 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
2020 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
2021 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
2022 adev->gfx.config.max_texture_channel_caches =
2023 le32_to_cpu(gpu_info_fw->gc_num_tccs);
2024 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
2025 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
2026 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
2027 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
2028 adev->gfx.config.double_offchip_lds_buf =
2029 le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
2030 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
2031 adev->gfx.cu_info.max_waves_per_simd =
2032 le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
2033 adev->gfx.cu_info.max_scratch_slots_per_cu =
2034 le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
2035 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
2036 if (hdr->version_minor >= 1) {
2037 const struct gpu_info_firmware_v1_1 *gpu_info_fw =
2038 (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +
2039 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2040 adev->gfx.config.num_sc_per_sh =
2041 le32_to_cpu(gpu_info_fw->num_sc_per_sh);
2042 adev->gfx.config.num_packer_per_sc =
2043 le32_to_cpu(gpu_info_fw->num_packer_per_sc);
2044 }
2045
2046parse_soc_bounding_box:
2047 /*
2048 * soc bounding box info is not integrated in disocovery table,
2049 * we always need to parse it from gpu info firmware if needed.
2050 */
2051 if (hdr->version_minor == 2) {
2052 const struct gpu_info_firmware_v1_2 *gpu_info_fw =
2053 (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +
2054 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2055 adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;
2056 }
2057 break;
2058 }
2059 default:
2060 dev_err(adev->dev,
2061 "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
2062 err = -EINVAL;
2063 goto out;
2064 }
2065out:
2066 return err;
2067}
2068
2069/**
2070 * amdgpu_device_ip_early_init - run early init for hardware IPs
2071 *
2072 * @adev: amdgpu_device pointer
2073 *
2074 * Early initialization pass for hardware IPs. The hardware IPs that make
2075 * up each asic are discovered each IP's early_init callback is run. This
2076 * is the first stage in initializing the asic.
2077 * Returns 0 on success, negative error code on failure.
2078 */
2079static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
2080{
2081 struct drm_device *dev = adev_to_drm(adev);
2082 struct pci_dev *parent;
2083 int i, r;
2084
2085 amdgpu_device_enable_virtual_display(adev);
2086
2087 if (amdgpu_sriov_vf(adev)) {
2088 r = amdgpu_virt_request_full_gpu(adev, true);
2089 if (r)
2090 return r;
2091 }
2092
2093 switch (adev->asic_type) {
2094#ifdef CONFIG_DRM_AMDGPU_SI
2095 case CHIP_VERDE:
2096 case CHIP_TAHITI:
2097 case CHIP_PITCAIRN:
2098 case CHIP_OLAND:
2099 case CHIP_HAINAN:
2100 adev->family = AMDGPU_FAMILY_SI;
2101 r = si_set_ip_blocks(adev);
2102 if (r)
2103 return r;
2104 break;
2105#endif
2106#ifdef CONFIG_DRM_AMDGPU_CIK
2107 case CHIP_BONAIRE:
2108 case CHIP_HAWAII:
2109 case CHIP_KAVERI:
2110 case CHIP_KABINI:
2111 case CHIP_MULLINS:
2112 if (adev->flags & AMD_IS_APU)
2113 adev->family = AMDGPU_FAMILY_KV;
2114 else
2115 adev->family = AMDGPU_FAMILY_CI;
2116
2117 r = cik_set_ip_blocks(adev);
2118 if (r)
2119 return r;
2120 break;
2121#endif
2122 case CHIP_TOPAZ:
2123 case CHIP_TONGA:
2124 case CHIP_FIJI:
2125 case CHIP_POLARIS10:
2126 case CHIP_POLARIS11:
2127 case CHIP_POLARIS12:
2128 case CHIP_VEGAM:
2129 case CHIP_CARRIZO:
2130 case CHIP_STONEY:
2131 if (adev->flags & AMD_IS_APU)
2132 adev->family = AMDGPU_FAMILY_CZ;
2133 else
2134 adev->family = AMDGPU_FAMILY_VI;
2135
2136 r = vi_set_ip_blocks(adev);
2137 if (r)
2138 return r;
2139 break;
2140 default:
2141 r = amdgpu_discovery_set_ip_blocks(adev);
2142 if (r)
2143 return r;
2144 break;
2145 }
2146
2147 if (amdgpu_has_atpx() &&
2148 (amdgpu_is_atpx_hybrid() ||
2149 amdgpu_has_atpx_dgpu_power_cntl()) &&
2150 ((adev->flags & AMD_IS_APU) == 0) &&
2151 !pci_is_thunderbolt_attached(to_pci_dev(dev->dev)))
2152 adev->flags |= AMD_IS_PX;
2153
2154 if (!(adev->flags & AMD_IS_APU)) {
2155 parent = pci_upstream_bridge(adev->pdev);
2156 adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
2157 }
2158
2159 amdgpu_amdkfd_device_probe(adev);
2160
2161 adev->pm.pp_feature = amdgpu_pp_feature_mask;
2162 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS)
2163 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2164 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
2165 adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;
2166
2167 for (i = 0; i < adev->num_ip_blocks; i++) {
2168 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
2169 DRM_ERROR("disabled ip block: %d <%s>\n",
2170 i, adev->ip_blocks[i].version->funcs->name);
2171 adev->ip_blocks[i].status.valid = false;
2172 } else {
2173 if (adev->ip_blocks[i].version->funcs->early_init) {
2174 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
2175 if (r == -ENOENT) {
2176 adev->ip_blocks[i].status.valid = false;
2177 } else if (r) {
2178 DRM_ERROR("early_init of IP block <%s> failed %d\n",
2179 adev->ip_blocks[i].version->funcs->name, r);
2180 return r;
2181 } else {
2182 adev->ip_blocks[i].status.valid = true;
2183 }
2184 } else {
2185 adev->ip_blocks[i].status.valid = true;
2186 }
2187 }
2188 /* get the vbios after the asic_funcs are set up */
2189 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2190 r = amdgpu_device_parse_gpu_info_fw(adev);
2191 if (r)
2192 return r;
2193
2194 /* Read BIOS */
2195 if (!amdgpu_get_bios(adev))
2196 return -EINVAL;
2197
2198 r = amdgpu_atombios_init(adev);
2199 if (r) {
2200 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2201 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2202 return r;
2203 }
2204
2205 /*get pf2vf msg info at it's earliest time*/
2206 if (amdgpu_sriov_vf(adev))
2207 amdgpu_virt_init_data_exchange(adev);
2208
2209 }
2210 }
2211
2212 adev->cg_flags &= amdgpu_cg_mask;
2213 adev->pg_flags &= amdgpu_pg_mask;
2214
2215 return 0;
2216}
2217
2218static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
2219{
2220 int i, r;
2221
2222 for (i = 0; i < adev->num_ip_blocks; i++) {
2223 if (!adev->ip_blocks[i].status.sw)
2224 continue;
2225 if (adev->ip_blocks[i].status.hw)
2226 continue;
2227 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2228 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) ||
2229 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
2230 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2231 if (r) {
2232 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2233 adev->ip_blocks[i].version->funcs->name, r);
2234 return r;
2235 }
2236 adev->ip_blocks[i].status.hw = true;
2237 }
2238 }
2239
2240 return 0;
2241}
2242
2243static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
2244{
2245 int i, r;
2246
2247 for (i = 0; i < adev->num_ip_blocks; i++) {
2248 if (!adev->ip_blocks[i].status.sw)
2249 continue;
2250 if (adev->ip_blocks[i].status.hw)
2251 continue;
2252 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2253 if (r) {
2254 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2255 adev->ip_blocks[i].version->funcs->name, r);
2256 return r;
2257 }
2258 adev->ip_blocks[i].status.hw = true;
2259 }
2260
2261 return 0;
2262}
2263
2264static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
2265{
2266 int r = 0;
2267 int i;
2268 uint32_t smu_version;
2269
2270 if (adev->asic_type >= CHIP_VEGA10) {
2271 for (i = 0; i < adev->num_ip_blocks; i++) {
2272 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
2273 continue;
2274
2275 if (!adev->ip_blocks[i].status.sw)
2276 continue;
2277
2278 /* no need to do the fw loading again if already done*/
2279 if (adev->ip_blocks[i].status.hw == true)
2280 break;
2281
2282 if (amdgpu_in_reset(adev) || adev->in_suspend) {
2283 r = adev->ip_blocks[i].version->funcs->resume(adev);
2284 if (r) {
2285 DRM_ERROR("resume of IP block <%s> failed %d\n",
2286 adev->ip_blocks[i].version->funcs->name, r);
2287 return r;
2288 }
2289 } else {
2290 r = adev->ip_blocks[i].version->funcs->hw_init(adev);
2291 if (r) {
2292 DRM_ERROR("hw_init of IP block <%s> failed %d\n",
2293 adev->ip_blocks[i].version->funcs->name, r);
2294 return r;
2295 }
2296 }
2297
2298 adev->ip_blocks[i].status.hw = true;
2299 break;
2300 }
2301 }
2302
2303 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA)
2304 r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
2305
2306 return r;
2307}
2308
2309static int amdgpu_device_init_schedulers(struct amdgpu_device *adev)
2310{
2311 long timeout;
2312 int r, i;
2313
2314 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2315 struct amdgpu_ring *ring = adev->rings[i];
2316
2317 /* No need to setup the GPU scheduler for rings that don't need it */
2318 if (!ring || ring->no_scheduler)
2319 continue;
2320
2321 switch (ring->funcs->type) {
2322 case AMDGPU_RING_TYPE_GFX:
2323 timeout = adev->gfx_timeout;
2324 break;
2325 case AMDGPU_RING_TYPE_COMPUTE:
2326 timeout = adev->compute_timeout;
2327 break;
2328 case AMDGPU_RING_TYPE_SDMA:
2329 timeout = adev->sdma_timeout;
2330 break;
2331 default:
2332 timeout = adev->video_timeout;
2333 break;
2334 }
2335
2336 r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
2337 ring->num_hw_submission, amdgpu_job_hang_limit,
2338 timeout, adev->reset_domain->wq,
2339 ring->sched_score, ring->name,
2340 adev->dev);
2341 if (r) {
2342 DRM_ERROR("Failed to create scheduler on ring %s.\n",
2343 ring->name);
2344 return r;
2345 }
2346 }
2347
2348 return 0;
2349}
2350
2351
2352/**
2353 * amdgpu_device_ip_init - run init for hardware IPs
2354 *
2355 * @adev: amdgpu_device pointer
2356 *
2357 * Main initialization pass for hardware IPs. The list of all the hardware
2358 * IPs that make up the asic is walked and the sw_init and hw_init callbacks
2359 * are run. sw_init initializes the software state associated with each IP
2360 * and hw_init initializes the hardware associated with each IP.
2361 * Returns 0 on success, negative error code on failure.
2362 */
2363static int amdgpu_device_ip_init(struct amdgpu_device *adev)
2364{
2365 int i, r;
2366
2367 r = amdgpu_ras_init(adev);
2368 if (r)
2369 return r;
2370
2371 for (i = 0; i < adev->num_ip_blocks; i++) {
2372 if (!adev->ip_blocks[i].status.valid)
2373 continue;
2374 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
2375 if (r) {
2376 DRM_ERROR("sw_init of IP block <%s> failed %d\n",
2377 adev->ip_blocks[i].version->funcs->name, r);
2378 goto init_failed;
2379 }
2380 adev->ip_blocks[i].status.sw = true;
2381
2382 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
2383 /* need to do common hw init early so everything is set up for gmc */
2384 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2385 if (r) {
2386 DRM_ERROR("hw_init %d failed %d\n", i, r);
2387 goto init_failed;
2388 }
2389 adev->ip_blocks[i].status.hw = true;
2390 } else if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2391 /* need to do gmc hw init early so we can allocate gpu mem */
2392 /* Try to reserve bad pages early */
2393 if (amdgpu_sriov_vf(adev))
2394 amdgpu_virt_exchange_data(adev);
2395
2396 r = amdgpu_device_vram_scratch_init(adev);
2397 if (r) {
2398 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
2399 goto init_failed;
2400 }
2401 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
2402 if (r) {
2403 DRM_ERROR("hw_init %d failed %d\n", i, r);
2404 goto init_failed;
2405 }
2406 r = amdgpu_device_wb_init(adev);
2407 if (r) {
2408 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
2409 goto init_failed;
2410 }
2411 adev->ip_blocks[i].status.hw = true;
2412
2413 /* right after GMC hw init, we create CSA */
2414 if (amdgpu_mcbp) {
2415 r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
2416 AMDGPU_GEM_DOMAIN_VRAM,
2417 AMDGPU_CSA_SIZE);
2418 if (r) {
2419 DRM_ERROR("allocate CSA failed %d\n", r);
2420 goto init_failed;
2421 }
2422 }
2423 }
2424 }
2425
2426 if (amdgpu_sriov_vf(adev))
2427 amdgpu_virt_init_data_exchange(adev);
2428
2429 r = amdgpu_ib_pool_init(adev);
2430 if (r) {
2431 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2432 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2433 goto init_failed;
2434 }
2435
2436 r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
2437 if (r)
2438 goto init_failed;
2439
2440 r = amdgpu_device_ip_hw_init_phase1(adev);
2441 if (r)
2442 goto init_failed;
2443
2444 r = amdgpu_device_fw_loading(adev);
2445 if (r)
2446 goto init_failed;
2447
2448 r = amdgpu_device_ip_hw_init_phase2(adev);
2449 if (r)
2450 goto init_failed;
2451
2452 /*
2453 * retired pages will be loaded from eeprom and reserved here,
2454 * it should be called after amdgpu_device_ip_hw_init_phase2 since
2455 * for some ASICs the RAS EEPROM code relies on SMU fully functioning
2456 * for I2C communication which only true at this point.
2457 *
2458 * amdgpu_ras_recovery_init may fail, but the upper only cares the
2459 * failure from bad gpu situation and stop amdgpu init process
2460 * accordingly. For other failed cases, it will still release all
2461 * the resource and print error message, rather than returning one
2462 * negative value to upper level.
2463 *
2464 * Note: theoretically, this should be called before all vram allocations
2465 * to protect retired page from abusing
2466 */
2467 r = amdgpu_ras_recovery_init(adev);
2468 if (r)
2469 goto init_failed;
2470
2471 /**
2472 * In case of XGMI grab extra reference for reset domain for this device
2473 */
2474 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2475 if (amdgpu_xgmi_add_device(adev) == 0) {
2476 if (!amdgpu_sriov_vf(adev)) {
2477 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2478
2479 if (WARN_ON(!hive)) {
2480 r = -ENOENT;
2481 goto init_failed;
2482 }
2483
2484 if (!hive->reset_domain ||
2485 !amdgpu_reset_get_reset_domain(hive->reset_domain)) {
2486 r = -ENOENT;
2487 amdgpu_put_xgmi_hive(hive);
2488 goto init_failed;
2489 }
2490
2491 /* Drop the early temporary reset domain we created for device */
2492 amdgpu_reset_put_reset_domain(adev->reset_domain);
2493 adev->reset_domain = hive->reset_domain;
2494 amdgpu_put_xgmi_hive(hive);
2495 }
2496 }
2497 }
2498
2499 r = amdgpu_device_init_schedulers(adev);
2500 if (r)
2501 goto init_failed;
2502
2503 /* Don't init kfd if whole hive need to be reset during init */
2504 if (!adev->gmc.xgmi.pending_reset)
2505 amdgpu_amdkfd_device_init(adev);
2506
2507 amdgpu_fru_get_product_info(adev);
2508
2509init_failed:
2510 if (amdgpu_sriov_vf(adev))
2511 amdgpu_virt_release_full_gpu(adev, true);
2512
2513 return r;
2514}
2515
2516/**
2517 * amdgpu_device_fill_reset_magic - writes reset magic to gart pointer
2518 *
2519 * @adev: amdgpu_device pointer
2520 *
2521 * Writes a reset magic value to the gart pointer in VRAM. The driver calls
2522 * this function before a GPU reset. If the value is retained after a
2523 * GPU reset, VRAM has not been lost. Some GPU resets may destry VRAM contents.
2524 */
2525static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
2526{
2527 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
2528}
2529
2530/**
2531 * amdgpu_device_check_vram_lost - check if vram is valid
2532 *
2533 * @adev: amdgpu_device pointer
2534 *
2535 * Checks the reset magic value written to the gart pointer in VRAM.
2536 * The driver calls this after a GPU reset to see if the contents of
2537 * VRAM is lost or now.
2538 * returns true if vram is lost, false if not.
2539 */
2540static bool amdgpu_device_check_vram_lost(struct amdgpu_device *adev)
2541{
2542 if (memcmp(adev->gart.ptr, adev->reset_magic,
2543 AMDGPU_RESET_MAGIC_NUM))
2544 return true;
2545
2546 if (!amdgpu_in_reset(adev))
2547 return false;
2548
2549 /*
2550 * For all ASICs with baco/mode1 reset, the VRAM is
2551 * always assumed to be lost.
2552 */
2553 switch (amdgpu_asic_reset_method(adev)) {
2554 case AMD_RESET_METHOD_BACO:
2555 case AMD_RESET_METHOD_MODE1:
2556 return true;
2557 default:
2558 return false;
2559 }
2560}
2561
2562/**
2563 * amdgpu_device_set_cg_state - set clockgating for amdgpu device
2564 *
2565 * @adev: amdgpu_device pointer
2566 * @state: clockgating state (gate or ungate)
2567 *
2568 * The list of all the hardware IPs that make up the asic is walked and the
2569 * set_clockgating_state callbacks are run.
2570 * Late initialization pass enabling clockgating for hardware IPs.
2571 * Fini or suspend, pass disabling clockgating for hardware IPs.
2572 * Returns 0 on success, negative error code on failure.
2573 */
2574
2575int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
2576 enum amd_clockgating_state state)
2577{
2578 int i, j, r;
2579
2580 if (amdgpu_emu_mode == 1)
2581 return 0;
2582
2583 for (j = 0; j < adev->num_ip_blocks; j++) {
2584 i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2585 if (!adev->ip_blocks[i].status.late_initialized)
2586 continue;
2587 /* skip CG for GFX on S0ix */
2588 if (adev->in_s0ix &&
2589 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX)
2590 continue;
2591 /* skip CG for VCE/UVD, it's handled specially */
2592 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2593 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2594 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2595 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2596 adev->ip_blocks[i].version->funcs->set_clockgating_state) {
2597 /* enable clockgating to save power */
2598 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
2599 state);
2600 if (r) {
2601 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
2602 adev->ip_blocks[i].version->funcs->name, r);
2603 return r;
2604 }
2605 }
2606 }
2607
2608 return 0;
2609}
2610
2611int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
2612 enum amd_powergating_state state)
2613{
2614 int i, j, r;
2615
2616 if (amdgpu_emu_mode == 1)
2617 return 0;
2618
2619 for (j = 0; j < adev->num_ip_blocks; j++) {
2620 i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1;
2621 if (!adev->ip_blocks[i].status.late_initialized)
2622 continue;
2623 /* skip PG for GFX on S0ix */
2624 if (adev->in_s0ix &&
2625 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX)
2626 continue;
2627 /* skip CG for VCE/UVD, it's handled specially */
2628 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
2629 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
2630 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
2631 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
2632 adev->ip_blocks[i].version->funcs->set_powergating_state) {
2633 /* enable powergating to save power */
2634 r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
2635 state);
2636 if (r) {
2637 DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
2638 adev->ip_blocks[i].version->funcs->name, r);
2639 return r;
2640 }
2641 }
2642 }
2643 return 0;
2644}
2645
2646static int amdgpu_device_enable_mgpu_fan_boost(void)
2647{
2648 struct amdgpu_gpu_instance *gpu_ins;
2649 struct amdgpu_device *adev;
2650 int i, ret = 0;
2651
2652 mutex_lock(&mgpu_info.mutex);
2653
2654 /*
2655 * MGPU fan boost feature should be enabled
2656 * only when there are two or more dGPUs in
2657 * the system
2658 */
2659 if (mgpu_info.num_dgpu < 2)
2660 goto out;
2661
2662 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2663 gpu_ins = &(mgpu_info.gpu_ins[i]);
2664 adev = gpu_ins->adev;
2665 if (!(adev->flags & AMD_IS_APU) &&
2666 !gpu_ins->mgpu_fan_enabled) {
2667 ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
2668 if (ret)
2669 break;
2670
2671 gpu_ins->mgpu_fan_enabled = 1;
2672 }
2673 }
2674
2675out:
2676 mutex_unlock(&mgpu_info.mutex);
2677
2678 return ret;
2679}
2680
2681/**
2682 * amdgpu_device_ip_late_init - run late init for hardware IPs
2683 *
2684 * @adev: amdgpu_device pointer
2685 *
2686 * Late initialization pass for hardware IPs. The list of all the hardware
2687 * IPs that make up the asic is walked and the late_init callbacks are run.
2688 * late_init covers any special initialization that an IP requires
2689 * after all of the have been initialized or something that needs to happen
2690 * late in the init process.
2691 * Returns 0 on success, negative error code on failure.
2692 */
2693static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
2694{
2695 struct amdgpu_gpu_instance *gpu_instance;
2696 int i = 0, r;
2697
2698 for (i = 0; i < adev->num_ip_blocks; i++) {
2699 if (!adev->ip_blocks[i].status.hw)
2700 continue;
2701 if (adev->ip_blocks[i].version->funcs->late_init) {
2702 r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
2703 if (r) {
2704 DRM_ERROR("late_init of IP block <%s> failed %d\n",
2705 adev->ip_blocks[i].version->funcs->name, r);
2706 return r;
2707 }
2708 }
2709 adev->ip_blocks[i].status.late_initialized = true;
2710 }
2711
2712 r = amdgpu_ras_late_init(adev);
2713 if (r) {
2714 DRM_ERROR("amdgpu_ras_late_init failed %d", r);
2715 return r;
2716 }
2717
2718 amdgpu_ras_set_error_query_ready(adev, true);
2719
2720 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
2721 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
2722
2723 amdgpu_device_fill_reset_magic(adev);
2724
2725 r = amdgpu_device_enable_mgpu_fan_boost();
2726 if (r)
2727 DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
2728
2729 /* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */
2730 if (amdgpu_passthrough(adev) && ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1)||
2731 adev->asic_type == CHIP_ALDEBARAN ))
2732 amdgpu_dpm_handle_passthrough_sbr(adev, true);
2733
2734 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2735 mutex_lock(&mgpu_info.mutex);
2736
2737 /*
2738 * Reset device p-state to low as this was booted with high.
2739 *
2740 * This should be performed only after all devices from the same
2741 * hive get initialized.
2742 *
2743 * However, it's unknown how many device in the hive in advance.
2744 * As this is counted one by one during devices initializations.
2745 *
2746 * So, we wait for all XGMI interlinked devices initialized.
2747 * This may bring some delays as those devices may come from
2748 * different hives. But that should be OK.
2749 */
2750 if (mgpu_info.num_dgpu == adev->gmc.xgmi.num_physical_nodes) {
2751 for (i = 0; i < mgpu_info.num_gpu; i++) {
2752 gpu_instance = &(mgpu_info.gpu_ins[i]);
2753 if (gpu_instance->adev->flags & AMD_IS_APU)
2754 continue;
2755
2756 r = amdgpu_xgmi_set_pstate(gpu_instance->adev,
2757 AMDGPU_XGMI_PSTATE_MIN);
2758 if (r) {
2759 DRM_ERROR("pstate setting failed (%d).\n", r);
2760 break;
2761 }
2762 }
2763 }
2764
2765 mutex_unlock(&mgpu_info.mutex);
2766 }
2767
2768 return 0;
2769}
2770
2771/**
2772 * amdgpu_device_smu_fini_early - smu hw_fini wrapper
2773 *
2774 * @adev: amdgpu_device pointer
2775 *
2776 * For ASICs need to disable SMC first
2777 */
2778static void amdgpu_device_smu_fini_early(struct amdgpu_device *adev)
2779{
2780 int i, r;
2781
2782 if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0))
2783 return;
2784
2785 for (i = 0; i < adev->num_ip_blocks; i++) {
2786 if (!adev->ip_blocks[i].status.hw)
2787 continue;
2788 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
2789 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2790 /* XXX handle errors */
2791 if (r) {
2792 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2793 adev->ip_blocks[i].version->funcs->name, r);
2794 }
2795 adev->ip_blocks[i].status.hw = false;
2796 break;
2797 }
2798 }
2799}
2800
2801static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev)
2802{
2803 int i, r;
2804
2805 for (i = 0; i < adev->num_ip_blocks; i++) {
2806 if (!adev->ip_blocks[i].version->funcs->early_fini)
2807 continue;
2808
2809 r = adev->ip_blocks[i].version->funcs->early_fini((void *)adev);
2810 if (r) {
2811 DRM_DEBUG("early_fini of IP block <%s> failed %d\n",
2812 adev->ip_blocks[i].version->funcs->name, r);
2813 }
2814 }
2815
2816 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2817 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2818
2819 amdgpu_amdkfd_suspend(adev, false);
2820
2821 /* Workaroud for ASICs need to disable SMC first */
2822 amdgpu_device_smu_fini_early(adev);
2823
2824 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2825 if (!adev->ip_blocks[i].status.hw)
2826 continue;
2827
2828 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
2829 /* XXX handle errors */
2830 if (r) {
2831 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
2832 adev->ip_blocks[i].version->funcs->name, r);
2833 }
2834
2835 adev->ip_blocks[i].status.hw = false;
2836 }
2837
2838 if (amdgpu_sriov_vf(adev)) {
2839 if (amdgpu_virt_release_full_gpu(adev, false))
2840 DRM_ERROR("failed to release exclusive mode on fini\n");
2841 }
2842
2843 return 0;
2844}
2845
2846/**
2847 * amdgpu_device_ip_fini - run fini for hardware IPs
2848 *
2849 * @adev: amdgpu_device pointer
2850 *
2851 * Main teardown pass for hardware IPs. The list of all the hardware
2852 * IPs that make up the asic is walked and the hw_fini and sw_fini callbacks
2853 * are run. hw_fini tears down the hardware associated with each IP
2854 * and sw_fini tears down any software state associated with each IP.
2855 * Returns 0 on success, negative error code on failure.
2856 */
2857static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
2858{
2859 int i, r;
2860
2861 if (amdgpu_sriov_vf(adev) && adev->virt.ras_init_done)
2862 amdgpu_virt_release_ras_err_handler_data(adev);
2863
2864 if (adev->gmc.xgmi.num_physical_nodes > 1)
2865 amdgpu_xgmi_remove_device(adev);
2866
2867 amdgpu_amdkfd_device_fini_sw(adev);
2868
2869 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2870 if (!adev->ip_blocks[i].status.sw)
2871 continue;
2872
2873 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
2874 amdgpu_ucode_free_bo(adev);
2875 amdgpu_free_static_csa(&adev->virt.csa_obj);
2876 amdgpu_device_wb_fini(adev);
2877 amdgpu_device_vram_scratch_fini(adev);
2878 amdgpu_ib_pool_fini(adev);
2879 }
2880
2881 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
2882 /* XXX handle errors */
2883 if (r) {
2884 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
2885 adev->ip_blocks[i].version->funcs->name, r);
2886 }
2887 adev->ip_blocks[i].status.sw = false;
2888 adev->ip_blocks[i].status.valid = false;
2889 }
2890
2891 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2892 if (!adev->ip_blocks[i].status.late_initialized)
2893 continue;
2894 if (adev->ip_blocks[i].version->funcs->late_fini)
2895 adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
2896 adev->ip_blocks[i].status.late_initialized = false;
2897 }
2898
2899 amdgpu_ras_fini(adev);
2900
2901 return 0;
2902}
2903
2904/**
2905 * amdgpu_device_delayed_init_work_handler - work handler for IB tests
2906 *
2907 * @work: work_struct.
2908 */
2909static void amdgpu_device_delayed_init_work_handler(struct work_struct *work)
2910{
2911 struct amdgpu_device *adev =
2912 container_of(work, struct amdgpu_device, delayed_init_work.work);
2913 int r;
2914
2915 r = amdgpu_ib_ring_tests(adev);
2916 if (r)
2917 DRM_ERROR("ib ring test failed (%d).\n", r);
2918}
2919
2920static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
2921{
2922 struct amdgpu_device *adev =
2923 container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work);
2924
2925 WARN_ON_ONCE(adev->gfx.gfx_off_state);
2926 WARN_ON_ONCE(adev->gfx.gfx_off_req_count);
2927
2928 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
2929 adev->gfx.gfx_off_state = true;
2930}
2931
2932/**
2933 * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1)
2934 *
2935 * @adev: amdgpu_device pointer
2936 *
2937 * Main suspend function for hardware IPs. The list of all the hardware
2938 * IPs that make up the asic is walked, clockgating is disabled and the
2939 * suspend callbacks are run. suspend puts the hardware and software state
2940 * in each IP into a state suitable for suspend.
2941 * Returns 0 on success, negative error code on failure.
2942 */
2943static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
2944{
2945 int i, r;
2946
2947 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
2948 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
2949
2950 /*
2951 * Per PMFW team's suggestion, driver needs to handle gfxoff
2952 * and df cstate features disablement for gpu reset(e.g. Mode1Reset)
2953 * scenario. Add the missing df cstate disablement here.
2954 */
2955 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
2956 dev_warn(adev->dev, "Failed to disallow df cstate");
2957
2958 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
2959 if (!adev->ip_blocks[i].status.valid)
2960 continue;
2961
2962 /* displays are handled separately */
2963 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE)
2964 continue;
2965
2966 /* XXX handle errors */
2967 r = adev->ip_blocks[i].version->funcs->suspend(adev);
2968 /* XXX handle errors */
2969 if (r) {
2970 DRM_ERROR("suspend of IP block <%s> failed %d\n",
2971 adev->ip_blocks[i].version->funcs->name, r);
2972 return r;
2973 }
2974
2975 adev->ip_blocks[i].status.hw = false;
2976 }
2977
2978 return 0;
2979}
2980
2981/**
2982 * amdgpu_device_ip_suspend_phase2 - run suspend for hardware IPs (phase 2)
2983 *
2984 * @adev: amdgpu_device pointer
2985 *
2986 * Main suspend function for hardware IPs. The list of all the hardware
2987 * IPs that make up the asic is walked, clockgating is disabled and the
2988 * suspend callbacks are run. suspend puts the hardware and software state
2989 * in each IP into a state suitable for suspend.
2990 * Returns 0 on success, negative error code on failure.
2991 */
2992static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
2993{
2994 int i, r;
2995
2996 if (adev->in_s0ix)
2997 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D3Entry);
2998
2999 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
3000 if (!adev->ip_blocks[i].status.valid)
3001 continue;
3002 /* displays are handled in phase1 */
3003 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)
3004 continue;
3005 /* PSP lost connection when err_event_athub occurs */
3006 if (amdgpu_ras_intr_triggered() &&
3007 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
3008 adev->ip_blocks[i].status.hw = false;
3009 continue;
3010 }
3011
3012 /* skip unnecessary suspend if we do not initialize them yet */
3013 if (adev->gmc.xgmi.pending_reset &&
3014 !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3015 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC ||
3016 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3017 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) {
3018 adev->ip_blocks[i].status.hw = false;
3019 continue;
3020 }
3021
3022 /* skip suspend of gfx/mes and psp for S0ix
3023 * gfx is in gfxoff state, so on resume it will exit gfxoff just
3024 * like at runtime. PSP is also part of the always on hardware
3025 * so no need to suspend it.
3026 */
3027 if (adev->in_s0ix &&
3028 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP ||
3029 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
3030 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_MES))
3031 continue;
3032
3033 /* XXX handle errors */
3034 r = adev->ip_blocks[i].version->funcs->suspend(adev);
3035 /* XXX handle errors */
3036 if (r) {
3037 DRM_ERROR("suspend of IP block <%s> failed %d\n",
3038 adev->ip_blocks[i].version->funcs->name, r);
3039 }
3040 adev->ip_blocks[i].status.hw = false;
3041 /* handle putting the SMC in the appropriate state */
3042 if(!amdgpu_sriov_vf(adev)){
3043 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3044 r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);
3045 if (r) {
3046 DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
3047 adev->mp1_state, r);
3048 return r;
3049 }
3050 }
3051 }
3052 }
3053
3054 return 0;
3055}
3056
3057/**
3058 * amdgpu_device_ip_suspend - run suspend for hardware IPs
3059 *
3060 * @adev: amdgpu_device pointer
3061 *
3062 * Main suspend function for hardware IPs. The list of all the hardware
3063 * IPs that make up the asic is walked, clockgating is disabled and the
3064 * suspend callbacks are run. suspend puts the hardware and software state
3065 * in each IP into a state suitable for suspend.
3066 * Returns 0 on success, negative error code on failure.
3067 */
3068int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
3069{
3070 int r;
3071
3072 if (amdgpu_sriov_vf(adev)) {
3073 amdgpu_virt_fini_data_exchange(adev);
3074 amdgpu_virt_request_full_gpu(adev, false);
3075 }
3076
3077 r = amdgpu_device_ip_suspend_phase1(adev);
3078 if (r)
3079 return r;
3080 r = amdgpu_device_ip_suspend_phase2(adev);
3081
3082 if (amdgpu_sriov_vf(adev))
3083 amdgpu_virt_release_full_gpu(adev, false);
3084
3085 return r;
3086}
3087
3088static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
3089{
3090 int i, r;
3091
3092 static enum amd_ip_block_type ip_order[] = {
3093 AMD_IP_BLOCK_TYPE_COMMON,
3094 AMD_IP_BLOCK_TYPE_GMC,
3095 AMD_IP_BLOCK_TYPE_PSP,
3096 AMD_IP_BLOCK_TYPE_IH,
3097 };
3098
3099 for (i = 0; i < adev->num_ip_blocks; i++) {
3100 int j;
3101 struct amdgpu_ip_block *block;
3102
3103 block = &adev->ip_blocks[i];
3104 block->status.hw = false;
3105
3106 for (j = 0; j < ARRAY_SIZE(ip_order); j++) {
3107
3108 if (block->version->type != ip_order[j] ||
3109 !block->status.valid)
3110 continue;
3111
3112 r = block->version->funcs->hw_init(adev);
3113 DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3114 if (r)
3115 return r;
3116 block->status.hw = true;
3117 }
3118 }
3119
3120 return 0;
3121}
3122
3123static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
3124{
3125 int i, r;
3126
3127 static enum amd_ip_block_type ip_order[] = {
3128 AMD_IP_BLOCK_TYPE_SMC,
3129 AMD_IP_BLOCK_TYPE_DCE,
3130 AMD_IP_BLOCK_TYPE_GFX,
3131 AMD_IP_BLOCK_TYPE_SDMA,
3132 AMD_IP_BLOCK_TYPE_UVD,
3133 AMD_IP_BLOCK_TYPE_VCE,
3134 AMD_IP_BLOCK_TYPE_VCN
3135 };
3136
3137 for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
3138 int j;
3139 struct amdgpu_ip_block *block;
3140
3141 for (j = 0; j < adev->num_ip_blocks; j++) {
3142 block = &adev->ip_blocks[j];
3143
3144 if (block->version->type != ip_order[i] ||
3145 !block->status.valid ||
3146 block->status.hw)
3147 continue;
3148
3149 if (block->version->type == AMD_IP_BLOCK_TYPE_SMC)
3150 r = block->version->funcs->resume(adev);
3151 else
3152 r = block->version->funcs->hw_init(adev);
3153
3154 DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
3155 if (r)
3156 return r;
3157 block->status.hw = true;
3158 }
3159 }
3160
3161 return 0;
3162}
3163
3164/**
3165 * amdgpu_device_ip_resume_phase1 - run resume for hardware IPs
3166 *
3167 * @adev: amdgpu_device pointer
3168 *
3169 * First resume function for hardware IPs. The list of all the hardware
3170 * IPs that make up the asic is walked and the resume callbacks are run for
3171 * COMMON, GMC, and IH. resume puts the hardware into a functional state
3172 * after a suspend and updates the software state as necessary. This
3173 * function is also used for restoring the GPU after a GPU reset.
3174 * Returns 0 on success, negative error code on failure.
3175 */
3176static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev)
3177{
3178 int i, r;
3179
3180 for (i = 0; i < adev->num_ip_blocks; i++) {
3181 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3182 continue;
3183 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3184 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3185 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3186 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP && amdgpu_sriov_vf(adev))) {
3187
3188 r = adev->ip_blocks[i].version->funcs->resume(adev);
3189 if (r) {
3190 DRM_ERROR("resume of IP block <%s> failed %d\n",
3191 adev->ip_blocks[i].version->funcs->name, r);
3192 return r;
3193 }
3194 adev->ip_blocks[i].status.hw = true;
3195 }
3196 }
3197
3198 return 0;
3199}
3200
3201/**
3202 * amdgpu_device_ip_resume_phase2 - run resume for hardware IPs
3203 *
3204 * @adev: amdgpu_device pointer
3205 *
3206 * First resume function for hardware IPs. The list of all the hardware
3207 * IPs that make up the asic is walked and the resume callbacks are run for
3208 * all blocks except COMMON, GMC, and IH. resume puts the hardware into a
3209 * functional state after a suspend and updates the software state as
3210 * necessary. This function is also used for restoring the GPU after a GPU
3211 * reset.
3212 * Returns 0 on success, negative error code on failure.
3213 */
3214static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev)
3215{
3216 int i, r;
3217
3218 for (i = 0; i < adev->num_ip_blocks; i++) {
3219 if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
3220 continue;
3221 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3222 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3223 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3224 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)
3225 continue;
3226 r = adev->ip_blocks[i].version->funcs->resume(adev);
3227 if (r) {
3228 DRM_ERROR("resume of IP block <%s> failed %d\n",
3229 adev->ip_blocks[i].version->funcs->name, r);
3230 return r;
3231 }
3232 adev->ip_blocks[i].status.hw = true;
3233
3234 if (adev->in_s0ix && adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
3235 /* disable gfxoff for IP resume. The gfxoff will be re-enabled in
3236 * amdgpu_device_resume() after IP resume.
3237 */
3238 amdgpu_gfx_off_ctrl(adev, false);
3239 DRM_DEBUG("will disable gfxoff for re-initializing other blocks\n");
3240 }
3241
3242 }
3243
3244 return 0;
3245}
3246
3247/**
3248 * amdgpu_device_ip_resume - run resume for hardware IPs
3249 *
3250 * @adev: amdgpu_device pointer
3251 *
3252 * Main resume function for hardware IPs. The hardware IPs
3253 * are split into two resume functions because they are
3254 * are also used in in recovering from a GPU reset and some additional
3255 * steps need to be take between them. In this case (S3/S4) they are
3256 * run sequentially.
3257 * Returns 0 on success, negative error code on failure.
3258 */
3259static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
3260{
3261 int r;
3262
3263 r = amdgpu_amdkfd_resume_iommu(adev);
3264 if (r)
3265 return r;
3266
3267 r = amdgpu_device_ip_resume_phase1(adev);
3268 if (r)
3269 return r;
3270
3271 r = amdgpu_device_fw_loading(adev);
3272 if (r)
3273 return r;
3274
3275 r = amdgpu_device_ip_resume_phase2(adev);
3276
3277 return r;
3278}
3279
3280/**
3281 * amdgpu_device_detect_sriov_bios - determine if the board supports SR-IOV
3282 *
3283 * @adev: amdgpu_device pointer
3284 *
3285 * Query the VBIOS data tables to determine if the board supports SR-IOV.
3286 */
3287static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
3288{
3289 if (amdgpu_sriov_vf(adev)) {
3290 if (adev->is_atom_fw) {
3291 if (amdgpu_atomfirmware_gpu_virtualization_supported(adev))
3292 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3293 } else {
3294 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
3295 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
3296 }
3297
3298 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
3299 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
3300 }
3301}
3302
3303/**
3304 * amdgpu_device_asic_has_dc_support - determine if DC supports the asic
3305 *
3306 * @asic_type: AMD asic type
3307 *
3308 * Check if there is DC (new modesetting infrastructre) support for an asic.
3309 * returns true if DC has support, false if not.
3310 */
3311bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
3312{
3313 switch (asic_type) {
3314#ifdef CONFIG_DRM_AMDGPU_SI
3315 case CHIP_HAINAN:
3316#endif
3317 case CHIP_TOPAZ:
3318 /* chips with no display hardware */
3319 return false;
3320#if defined(CONFIG_DRM_AMD_DC)
3321 case CHIP_TAHITI:
3322 case CHIP_PITCAIRN:
3323 case CHIP_VERDE:
3324 case CHIP_OLAND:
3325 /*
3326 * We have systems in the wild with these ASICs that require
3327 * LVDS and VGA support which is not supported with DC.
3328 *
3329 * Fallback to the non-DC driver here by default so as not to
3330 * cause regressions.
3331 */
3332#if defined(CONFIG_DRM_AMD_DC_SI)
3333 return amdgpu_dc > 0;
3334#else
3335 return false;
3336#endif
3337 case CHIP_BONAIRE:
3338 case CHIP_KAVERI:
3339 case CHIP_KABINI:
3340 case CHIP_MULLINS:
3341 /*
3342 * We have systems in the wild with these ASICs that require
3343 * VGA support which is not supported with DC.
3344 *
3345 * Fallback to the non-DC driver here by default so as not to
3346 * cause regressions.
3347 */
3348 return amdgpu_dc > 0;
3349 default:
3350 return amdgpu_dc != 0;
3351#else
3352 default:
3353 if (amdgpu_dc > 0)
3354 DRM_INFO_ONCE("Display Core has been requested via kernel parameter "
3355 "but isn't supported by ASIC, ignoring\n");
3356 return false;
3357#endif
3358 }
3359}
3360
3361/**
3362 * amdgpu_device_has_dc_support - check if dc is supported
3363 *
3364 * @adev: amdgpu_device pointer
3365 *
3366 * Returns true for supported, false for not supported
3367 */
3368bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
3369{
3370 if (adev->enable_virtual_display ||
3371 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
3372 return false;
3373
3374 return amdgpu_device_asic_has_dc_support(adev->asic_type);
3375}
3376
3377static void amdgpu_device_xgmi_reset_func(struct work_struct *__work)
3378{
3379 struct amdgpu_device *adev =
3380 container_of(__work, struct amdgpu_device, xgmi_reset_work);
3381 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
3382
3383 /* It's a bug to not have a hive within this function */
3384 if (WARN_ON(!hive))
3385 return;
3386
3387 /*
3388 * Use task barrier to synchronize all xgmi reset works across the
3389 * hive. task_barrier_enter and task_barrier_exit will block
3390 * until all the threads running the xgmi reset works reach
3391 * those points. task_barrier_full will do both blocks.
3392 */
3393 if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
3394
3395 task_barrier_enter(&hive->tb);
3396 adev->asic_reset_res = amdgpu_device_baco_enter(adev_to_drm(adev));
3397
3398 if (adev->asic_reset_res)
3399 goto fail;
3400
3401 task_barrier_exit(&hive->tb);
3402 adev->asic_reset_res = amdgpu_device_baco_exit(adev_to_drm(adev));
3403
3404 if (adev->asic_reset_res)
3405 goto fail;
3406
3407 if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops &&
3408 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
3409 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev);
3410 } else {
3411
3412 task_barrier_full(&hive->tb);
3413 adev->asic_reset_res = amdgpu_asic_reset(adev);
3414 }
3415
3416fail:
3417 if (adev->asic_reset_res)
3418 DRM_WARN("ASIC reset failed with error, %d for drm dev, %s",
3419 adev->asic_reset_res, adev_to_drm(adev)->unique);
3420 amdgpu_put_xgmi_hive(hive);
3421}
3422
3423static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
3424{
3425 char *input = amdgpu_lockup_timeout;
3426 char *timeout_setting = NULL;
3427 int index = 0;
3428 long timeout;
3429 int ret = 0;
3430
3431 /*
3432 * By default timeout for non compute jobs is 10000
3433 * and 60000 for compute jobs.
3434 * In SR-IOV or passthrough mode, timeout for compute
3435 * jobs are 60000 by default.
3436 */
3437 adev->gfx_timeout = msecs_to_jiffies(10000);
3438 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3439 if (amdgpu_sriov_vf(adev))
3440 adev->compute_timeout = amdgpu_sriov_is_pp_one_vf(adev) ?
3441 msecs_to_jiffies(60000) : msecs_to_jiffies(10000);
3442 else
3443 adev->compute_timeout = msecs_to_jiffies(60000);
3444
3445 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3446 while ((timeout_setting = strsep(&input, ",")) &&
3447 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) {
3448 ret = kstrtol(timeout_setting, 0, &timeout);
3449 if (ret)
3450 return ret;
3451
3452 if (timeout == 0) {
3453 index++;
3454 continue;
3455 } else if (timeout < 0) {
3456 timeout = MAX_SCHEDULE_TIMEOUT;
3457 dev_warn(adev->dev, "lockup timeout disabled");
3458 add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK);
3459 } else {
3460 timeout = msecs_to_jiffies(timeout);
3461 }
3462
3463 switch (index++) {
3464 case 0:
3465 adev->gfx_timeout = timeout;
3466 break;
3467 case 1:
3468 adev->compute_timeout = timeout;
3469 break;
3470 case 2:
3471 adev->sdma_timeout = timeout;
3472 break;
3473 case 3:
3474 adev->video_timeout = timeout;
3475 break;
3476 default:
3477 break;
3478 }
3479 }
3480 /*
3481 * There is only one value specified and
3482 * it should apply to all non-compute jobs.
3483 */
3484 if (index == 1) {
3485 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
3486 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
3487 adev->compute_timeout = adev->gfx_timeout;
3488 }
3489 }
3490
3491 return ret;
3492}
3493
3494/**
3495 * amdgpu_device_check_iommu_direct_map - check if RAM direct mapped to GPU
3496 *
3497 * @adev: amdgpu_device pointer
3498 *
3499 * RAM direct mapped to GPU if IOMMU is not enabled or is pass through mode
3500 */
3501static void amdgpu_device_check_iommu_direct_map(struct amdgpu_device *adev)
3502{
3503 struct iommu_domain *domain;
3504
3505 domain = iommu_get_domain_for_dev(adev->dev);
3506 if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY)
3507 adev->ram_is_direct_mapped = true;
3508}
3509
3510static const struct attribute *amdgpu_dev_attributes[] = {
3511 &dev_attr_product_name.attr,
3512 &dev_attr_product_number.attr,
3513 &dev_attr_serial_number.attr,
3514 &dev_attr_pcie_replay_count.attr,
3515 NULL
3516};
3517
3518/**
3519 * amdgpu_device_init - initialize the driver
3520 *
3521 * @adev: amdgpu_device pointer
3522 * @flags: driver flags
3523 *
3524 * Initializes the driver info and hw (all asics).
3525 * Returns 0 for success or an error on failure.
3526 * Called at driver startup.
3527 */
3528int amdgpu_device_init(struct amdgpu_device *adev,
3529 uint32_t flags)
3530{
3531 struct drm_device *ddev = adev_to_drm(adev);
3532 struct pci_dev *pdev = adev->pdev;
3533 int r, i;
3534 bool px = false;
3535 u32 max_MBps;
3536
3537 adev->shutdown = false;
3538 adev->flags = flags;
3539
3540 if (amdgpu_force_asic_type >= 0 && amdgpu_force_asic_type < CHIP_LAST)
3541 adev->asic_type = amdgpu_force_asic_type;
3542 else
3543 adev->asic_type = flags & AMD_ASIC_MASK;
3544
3545 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
3546 if (amdgpu_emu_mode == 1)
3547 adev->usec_timeout *= 10;
3548 adev->gmc.gart_size = 512 * 1024 * 1024;
3549 adev->accel_working = false;
3550 adev->num_rings = 0;
3551 RCU_INIT_POINTER(adev->gang_submit, dma_fence_get_stub());
3552 adev->mman.buffer_funcs = NULL;
3553 adev->mman.buffer_funcs_ring = NULL;
3554 adev->vm_manager.vm_pte_funcs = NULL;
3555 adev->vm_manager.vm_pte_num_scheds = 0;
3556 adev->gmc.gmc_funcs = NULL;
3557 adev->harvest_ip_mask = 0x0;
3558 adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3559 bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
3560
3561 adev->smc_rreg = &amdgpu_invalid_rreg;
3562 adev->smc_wreg = &amdgpu_invalid_wreg;
3563 adev->pcie_rreg = &amdgpu_invalid_rreg;
3564 adev->pcie_wreg = &amdgpu_invalid_wreg;
3565 adev->pciep_rreg = &amdgpu_invalid_rreg;
3566 adev->pciep_wreg = &amdgpu_invalid_wreg;
3567 adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
3568 adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
3569 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
3570 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
3571 adev->didt_rreg = &amdgpu_invalid_rreg;
3572 adev->didt_wreg = &amdgpu_invalid_wreg;
3573 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
3574 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
3575 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
3576 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
3577
3578 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
3579 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
3580 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
3581
3582 /* mutex initialization are all done here so we
3583 * can recall function without having locking issues */
3584 mutex_init(&adev->firmware.mutex);
3585 mutex_init(&adev->pm.mutex);
3586 mutex_init(&adev->gfx.gpu_clock_mutex);
3587 mutex_init(&adev->srbm_mutex);
3588 mutex_init(&adev->gfx.pipe_reserve_mutex);
3589 mutex_init(&adev->gfx.gfx_off_mutex);
3590 mutex_init(&adev->grbm_idx_mutex);
3591 mutex_init(&adev->mn_lock);
3592 mutex_init(&adev->virt.vf_errors.lock);
3593 hash_init(adev->mn_hash);
3594 mutex_init(&adev->psp.mutex);
3595 mutex_init(&adev->notifier_lock);
3596 mutex_init(&adev->pm.stable_pstate_ctx_lock);
3597 mutex_init(&adev->benchmark_mutex);
3598
3599 amdgpu_device_init_apu_flags(adev);
3600
3601 r = amdgpu_device_check_arguments(adev);
3602 if (r)
3603 return r;
3604
3605 spin_lock_init(&adev->mmio_idx_lock);
3606 spin_lock_init(&adev->smc_idx_lock);
3607 spin_lock_init(&adev->pcie_idx_lock);
3608 spin_lock_init(&adev->uvd_ctx_idx_lock);
3609 spin_lock_init(&adev->didt_idx_lock);
3610 spin_lock_init(&adev->gc_cac_idx_lock);
3611 spin_lock_init(&adev->se_cac_idx_lock);
3612 spin_lock_init(&adev->audio_endpt_idx_lock);
3613 spin_lock_init(&adev->mm_stats.lock);
3614
3615 INIT_LIST_HEAD(&adev->shadow_list);
3616 mutex_init(&adev->shadow_list_lock);
3617
3618 INIT_LIST_HEAD(&adev->reset_list);
3619
3620 INIT_LIST_HEAD(&adev->ras_list);
3621
3622 INIT_DELAYED_WORK(&adev->delayed_init_work,
3623 amdgpu_device_delayed_init_work_handler);
3624 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
3625 amdgpu_device_delay_enable_gfx_off);
3626
3627 INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func);
3628
3629 adev->gfx.gfx_off_req_count = 1;
3630 adev->gfx.gfx_off_residency = 0;
3631 adev->gfx.gfx_off_entrycount = 0;
3632 adev->pm.ac_power = power_supply_is_system_supplied() > 0;
3633
3634 atomic_set(&adev->throttling_logging_enabled, 1);
3635 /*
3636 * If throttling continues, logging will be performed every minute
3637 * to avoid log flooding. "-1" is subtracted since the thermal
3638 * throttling interrupt comes every second. Thus, the total logging
3639 * interval is 59 seconds(retelimited printk interval) + 1(waiting
3640 * for throttling interrupt) = 60 seconds.
3641 */
3642 ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1);
3643 ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE);
3644
3645 /* Registers mapping */
3646 /* TODO: block userspace mapping of io register */
3647 if (adev->asic_type >= CHIP_BONAIRE) {
3648 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
3649 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
3650 } else {
3651 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
3652 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
3653 }
3654
3655 for (i = 0; i < AMD_IP_BLOCK_TYPE_NUM; i++)
3656 atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN);
3657
3658 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
3659 if (adev->rmmio == NULL) {
3660 return -ENOMEM;
3661 }
3662 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
3663 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
3664
3665 amdgpu_device_get_pcie_info(adev);
3666
3667 if (amdgpu_mcbp)
3668 DRM_INFO("MCBP is enabled\n");
3669
3670 /*
3671 * Reset domain needs to be present early, before XGMI hive discovered
3672 * (if any) and intitialized to use reset sem and in_gpu reset flag
3673 * early on during init and before calling to RREG32.
3674 */
3675 adev->reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE, "amdgpu-reset-dev");
3676 if (!adev->reset_domain)
3677 return -ENOMEM;
3678
3679 /* detect hw virtualization here */
3680 amdgpu_detect_virtualization(adev);
3681
3682 r = amdgpu_device_get_job_timeout_settings(adev);
3683 if (r) {
3684 dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
3685 return r;
3686 }
3687
3688 /* early init functions */
3689 r = amdgpu_device_ip_early_init(adev);
3690 if (r)
3691 return r;
3692
3693 /* Get rid of things like offb */
3694 r = drm_aperture_remove_conflicting_pci_framebuffers(adev->pdev, &amdgpu_kms_driver);
3695 if (r)
3696 return r;
3697
3698 /* Enable TMZ based on IP_VERSION */
3699 amdgpu_gmc_tmz_set(adev);
3700
3701 amdgpu_gmc_noretry_set(adev);
3702 /* Need to get xgmi info early to decide the reset behavior*/
3703 if (adev->gmc.xgmi.supported) {
3704 r = adev->gfxhub.funcs->get_xgmi_info(adev);
3705 if (r)
3706 return r;
3707 }
3708
3709 /* enable PCIE atomic ops */
3710 if (amdgpu_sriov_vf(adev))
3711 adev->have_atomics_support = ((struct amd_sriov_msg_pf2vf_info *)
3712 adev->virt.fw_reserve.p_pf2vf)->pcie_atomic_ops_support_flags ==
3713 (PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCAP2_ATOMIC_COMP64);
3714 else
3715 adev->have_atomics_support =
3716 !pci_enable_atomic_ops_to_root(adev->pdev,
3717 PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
3718 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
3719 if (!adev->have_atomics_support)
3720 dev_info(adev->dev, "PCIE atomic ops is not supported\n");
3721
3722 /* doorbell bar mapping and doorbell index init*/
3723 amdgpu_device_doorbell_init(adev);
3724
3725 if (amdgpu_emu_mode == 1) {
3726 /* post the asic on emulation mode */
3727 emu_soc_asic_init(adev);
3728 goto fence_driver_init;
3729 }
3730
3731 amdgpu_reset_init(adev);
3732
3733 /* detect if we are with an SRIOV vbios */
3734 amdgpu_device_detect_sriov_bios(adev);
3735
3736 /* check if we need to reset the asic
3737 * E.g., driver was not cleanly unloaded previously, etc.
3738 */
3739 if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
3740 if (adev->gmc.xgmi.num_physical_nodes) {
3741 dev_info(adev->dev, "Pending hive reset.\n");
3742 adev->gmc.xgmi.pending_reset = true;
3743 /* Only need to init necessary block for SMU to handle the reset */
3744 for (i = 0; i < adev->num_ip_blocks; i++) {
3745 if (!adev->ip_blocks[i].status.valid)
3746 continue;
3747 if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
3748 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
3749 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH ||
3750 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) {
3751 DRM_DEBUG("IP %s disabled for hw_init.\n",
3752 adev->ip_blocks[i].version->funcs->name);
3753 adev->ip_blocks[i].status.hw = true;
3754 }
3755 }
3756 } else {
3757 r = amdgpu_asic_reset(adev);
3758 if (r) {
3759 dev_err(adev->dev, "asic reset on init failed\n");
3760 goto failed;
3761 }
3762 }
3763 }
3764
3765 pci_enable_pcie_error_reporting(adev->pdev);
3766
3767 /* Post card if necessary */
3768 if (amdgpu_device_need_post(adev)) {
3769 if (!adev->bios) {
3770 dev_err(adev->dev, "no vBIOS found\n");
3771 r = -EINVAL;
3772 goto failed;
3773 }
3774 DRM_INFO("GPU posting now...\n");
3775 r = amdgpu_device_asic_init(adev);
3776 if (r) {
3777 dev_err(adev->dev, "gpu post error!\n");
3778 goto failed;
3779 }
3780 }
3781
3782 if (adev->is_atom_fw) {
3783 /* Initialize clocks */
3784 r = amdgpu_atomfirmware_get_clock_info(adev);
3785 if (r) {
3786 dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
3787 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3788 goto failed;
3789 }
3790 } else {
3791 /* Initialize clocks */
3792 r = amdgpu_atombios_get_clock_info(adev);
3793 if (r) {
3794 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
3795 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
3796 goto failed;
3797 }
3798 /* init i2c buses */
3799 if (!amdgpu_device_has_dc_support(adev))
3800 amdgpu_atombios_i2c_init(adev);
3801 }
3802
3803fence_driver_init:
3804 /* Fence driver */
3805 r = amdgpu_fence_driver_sw_init(adev);
3806 if (r) {
3807 dev_err(adev->dev, "amdgpu_fence_driver_sw_init failed\n");
3808 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
3809 goto failed;
3810 }
3811
3812 /* init the mode config */
3813 drm_mode_config_init(adev_to_drm(adev));
3814
3815 r = amdgpu_device_ip_init(adev);
3816 if (r) {
3817 /* failed in exclusive mode due to timeout */
3818 if (amdgpu_sriov_vf(adev) &&
3819 !amdgpu_sriov_runtime(adev) &&
3820 amdgpu_virt_mmio_blocked(adev) &&
3821 !amdgpu_virt_wait_reset(adev)) {
3822 dev_err(adev->dev, "VF exclusive mode timeout\n");
3823 /* Don't send request since VF is inactive. */
3824 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
3825 adev->virt.ops = NULL;
3826 r = -EAGAIN;
3827 goto release_ras_con;
3828 }
3829 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
3830 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
3831 goto release_ras_con;
3832 }
3833
3834 amdgpu_fence_driver_hw_init(adev);
3835
3836 dev_info(adev->dev,
3837 "SE %d, SH per SE %d, CU per SH %d, active_cu_number %d\n",
3838 adev->gfx.config.max_shader_engines,
3839 adev->gfx.config.max_sh_per_se,
3840 adev->gfx.config.max_cu_per_sh,
3841 adev->gfx.cu_info.number);
3842
3843 adev->accel_working = true;
3844
3845 amdgpu_vm_check_compute_bug(adev);
3846
3847 /* Initialize the buffer migration limit. */
3848 if (amdgpu_moverate >= 0)
3849 max_MBps = amdgpu_moverate;
3850 else
3851 max_MBps = 8; /* Allow 8 MB/s. */
3852 /* Get a log2 for easy divisions. */
3853 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
3854
3855 r = amdgpu_pm_sysfs_init(adev);
3856 if (r) {
3857 adev->pm_sysfs_en = false;
3858 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
3859 } else
3860 adev->pm_sysfs_en = true;
3861
3862 r = amdgpu_ucode_sysfs_init(adev);
3863 if (r) {
3864 adev->ucode_sysfs_en = false;
3865 DRM_ERROR("Creating firmware sysfs failed (%d).\n", r);
3866 } else
3867 adev->ucode_sysfs_en = true;
3868
3869 r = amdgpu_psp_sysfs_init(adev);
3870 if (r) {
3871 adev->psp_sysfs_en = false;
3872 if (!amdgpu_sriov_vf(adev))
3873 DRM_ERROR("Creating psp sysfs failed\n");
3874 } else
3875 adev->psp_sysfs_en = true;
3876
3877 /*
3878 * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
3879 * Otherwise the mgpu fan boost feature will be skipped due to the
3880 * gpu instance is counted less.
3881 */
3882 amdgpu_register_gpu_instance(adev);
3883
3884 /* enable clockgating, etc. after ib tests, etc. since some blocks require
3885 * explicit gating rather than handling it automatically.
3886 */
3887 if (!adev->gmc.xgmi.pending_reset) {
3888 r = amdgpu_device_ip_late_init(adev);
3889 if (r) {
3890 dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n");
3891 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
3892 goto release_ras_con;
3893 }
3894 /* must succeed. */
3895 amdgpu_ras_resume(adev);
3896 queue_delayed_work(system_wq, &adev->delayed_init_work,
3897 msecs_to_jiffies(AMDGPU_RESUME_MS));
3898 }
3899
3900 if (amdgpu_sriov_vf(adev))
3901 flush_delayed_work(&adev->delayed_init_work);
3902
3903 r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes);
3904 if (r)
3905 dev_err(adev->dev, "Could not create amdgpu device attr\n");
3906
3907 if (IS_ENABLED(CONFIG_PERF_EVENTS))
3908 r = amdgpu_pmu_init(adev);
3909 if (r)
3910 dev_err(adev->dev, "amdgpu_pmu_init failed\n");
3911
3912 /* Have stored pci confspace at hand for restore in sudden PCI error */
3913 if (amdgpu_device_cache_pci_state(adev->pdev))
3914 pci_restore_state(pdev);
3915
3916 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
3917 /* this will fail for cards that aren't VGA class devices, just
3918 * ignore it */
3919 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3920 vga_client_register(adev->pdev, amdgpu_device_vga_set_decode);
3921
3922 if (amdgpu_device_supports_px(ddev)) {
3923 px = true;
3924 vga_switcheroo_register_client(adev->pdev,
3925 &amdgpu_switcheroo_ops, px);
3926 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
3927 }
3928
3929 if (adev->gmc.xgmi.pending_reset)
3930 queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work,
3931 msecs_to_jiffies(AMDGPU_RESUME_MS));
3932
3933 amdgpu_device_check_iommu_direct_map(adev);
3934
3935 return 0;
3936
3937release_ras_con:
3938 amdgpu_release_ras_context(adev);
3939
3940failed:
3941 amdgpu_vf_error_trans_all(adev);
3942
3943 return r;
3944}
3945
3946static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
3947{
3948
3949 /* Clear all CPU mappings pointing to this device */
3950 unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1);
3951
3952 /* Unmap all mapped bars - Doorbell, registers and VRAM */
3953 amdgpu_device_doorbell_fini(adev);
3954
3955 iounmap(adev->rmmio);
3956 adev->rmmio = NULL;
3957 if (adev->mman.aper_base_kaddr)
3958 iounmap(adev->mman.aper_base_kaddr);
3959 adev->mman.aper_base_kaddr = NULL;
3960
3961 /* Memory manager related */
3962 if (!adev->gmc.xgmi.connected_to_cpu) {
3963 arch_phys_wc_del(adev->gmc.vram_mtrr);
3964 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
3965 }
3966}
3967
3968/**
3969 * amdgpu_device_fini_hw - tear down the driver
3970 *
3971 * @adev: amdgpu_device pointer
3972 *
3973 * Tear down the driver info (all asics).
3974 * Called at driver shutdown.
3975 */
3976void amdgpu_device_fini_hw(struct amdgpu_device *adev)
3977{
3978 dev_info(adev->dev, "amdgpu: finishing device.\n");
3979 flush_delayed_work(&adev->delayed_init_work);
3980 adev->shutdown = true;
3981
3982 /* make sure IB test finished before entering exclusive mode
3983 * to avoid preemption on IB test
3984 * */
3985 if (amdgpu_sriov_vf(adev)) {
3986 amdgpu_virt_request_full_gpu(adev, false);
3987 amdgpu_virt_fini_data_exchange(adev);
3988 }
3989
3990 /* disable all interrupts */
3991 amdgpu_irq_disable_all(adev);
3992 if (adev->mode_info.mode_config_initialized){
3993 if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev)))
3994 drm_helper_force_disable_all(adev_to_drm(adev));
3995 else
3996 drm_atomic_helper_shutdown(adev_to_drm(adev));
3997 }
3998 amdgpu_fence_driver_hw_fini(adev);
3999
4000 if (adev->mman.initialized) {
4001 flush_delayed_work(&adev->mman.bdev.wq);
4002 ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
4003 }
4004
4005 if (adev->pm_sysfs_en)
4006 amdgpu_pm_sysfs_fini(adev);
4007 if (adev->ucode_sysfs_en)
4008 amdgpu_ucode_sysfs_fini(adev);
4009 if (adev->psp_sysfs_en)
4010 amdgpu_psp_sysfs_fini(adev);
4011 sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
4012
4013 /* disable ras feature must before hw fini */
4014 amdgpu_ras_pre_fini(adev);
4015
4016 amdgpu_device_ip_fini_early(adev);
4017
4018 amdgpu_irq_fini_hw(adev);
4019
4020 if (adev->mman.initialized)
4021 ttm_device_clear_dma_mappings(&adev->mman.bdev);
4022
4023 amdgpu_gart_dummy_page_fini(adev);
4024
4025 amdgpu_device_unmap_mmio(adev);
4026
4027}
4028
4029void amdgpu_device_fini_sw(struct amdgpu_device *adev)
4030{
4031 int idx;
4032
4033 amdgpu_fence_driver_sw_fini(adev);
4034 amdgpu_device_ip_fini(adev);
4035 release_firmware(adev->firmware.gpu_info_fw);
4036 adev->firmware.gpu_info_fw = NULL;
4037 adev->accel_working = false;
4038 dma_fence_put(rcu_dereference_protected(adev->gang_submit, true));
4039
4040 amdgpu_reset_fini(adev);
4041
4042 /* free i2c buses */
4043 if (!amdgpu_device_has_dc_support(adev))
4044 amdgpu_i2c_fini(adev);
4045
4046 if (amdgpu_emu_mode != 1)
4047 amdgpu_atombios_fini(adev);
4048
4049 kfree(adev->bios);
4050 adev->bios = NULL;
4051 if (amdgpu_device_supports_px(adev_to_drm(adev))) {
4052 vga_switcheroo_unregister_client(adev->pdev);
4053 vga_switcheroo_fini_domain_pm_ops(adev->dev);
4054 }
4055 if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
4056 vga_client_unregister(adev->pdev);
4057
4058 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
4059
4060 iounmap(adev->rmmio);
4061 adev->rmmio = NULL;
4062 amdgpu_device_doorbell_fini(adev);
4063 drm_dev_exit(idx);
4064 }
4065
4066 if (IS_ENABLED(CONFIG_PERF_EVENTS))
4067 amdgpu_pmu_fini(adev);
4068 if (adev->mman.discovery_bin)
4069 amdgpu_discovery_fini(adev);
4070
4071 amdgpu_reset_put_reset_domain(adev->reset_domain);
4072 adev->reset_domain = NULL;
4073
4074 kfree(adev->pci_state);
4075
4076}
4077
4078/**
4079 * amdgpu_device_evict_resources - evict device resources
4080 * @adev: amdgpu device object
4081 *
4082 * Evicts all ttm device resources(vram BOs, gart table) from the lru list
4083 * of the vram memory type. Mainly used for evicting device resources
4084 * at suspend time.
4085 *
4086 */
4087static int amdgpu_device_evict_resources(struct amdgpu_device *adev)
4088{
4089 int ret;
4090
4091 /* No need to evict vram on APUs for suspend to ram or s2idle */
4092 if ((adev->in_s3 || adev->in_s0ix) && (adev->flags & AMD_IS_APU))
4093 return 0;
4094
4095 ret = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
4096 if (ret)
4097 DRM_WARN("evicting device resources failed\n");
4098 return ret;
4099}
4100
4101/*
4102 * Suspend & resume.
4103 */
4104/**
4105 * amdgpu_device_suspend - initiate device suspend
4106 *
4107 * @dev: drm dev pointer
4108 * @fbcon : notify the fbdev of suspend
4109 *
4110 * Puts the hw in the suspend state (all asics).
4111 * Returns 0 for success or an error on failure.
4112 * Called at driver suspend.
4113 */
4114int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
4115{
4116 struct amdgpu_device *adev = drm_to_adev(dev);
4117 int r = 0;
4118
4119 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4120 return 0;
4121
4122 adev->in_suspend = true;
4123
4124 /* Evict the majority of BOs before grabbing the full access */
4125 r = amdgpu_device_evict_resources(adev);
4126 if (r)
4127 return r;
4128
4129 if (amdgpu_sriov_vf(adev)) {
4130 amdgpu_virt_fini_data_exchange(adev);
4131 r = amdgpu_virt_request_full_gpu(adev, false);
4132 if (r)
4133 return r;
4134 }
4135
4136 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D3))
4137 DRM_WARN("smart shift update failed\n");
4138
4139 drm_kms_helper_poll_disable(dev);
4140
4141 if (fbcon)
4142 drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
4143
4144 cancel_delayed_work_sync(&adev->delayed_init_work);
4145
4146 amdgpu_ras_suspend(adev);
4147
4148 amdgpu_device_ip_suspend_phase1(adev);
4149
4150 if (!adev->in_s0ix)
4151 amdgpu_amdkfd_suspend(adev, adev->in_runpm);
4152
4153 r = amdgpu_device_evict_resources(adev);
4154 if (r)
4155 return r;
4156
4157 amdgpu_fence_driver_hw_fini(adev);
4158
4159 amdgpu_device_ip_suspend_phase2(adev);
4160
4161 if (amdgpu_sriov_vf(adev))
4162 amdgpu_virt_release_full_gpu(adev, false);
4163
4164 return 0;
4165}
4166
4167/**
4168 * amdgpu_device_resume - initiate device resume
4169 *
4170 * @dev: drm dev pointer
4171 * @fbcon : notify the fbdev of resume
4172 *
4173 * Bring the hw back to operating state (all asics).
4174 * Returns 0 for success or an error on failure.
4175 * Called at driver resume.
4176 */
4177int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
4178{
4179 struct amdgpu_device *adev = drm_to_adev(dev);
4180 int r = 0;
4181
4182 if (amdgpu_sriov_vf(adev)) {
4183 r = amdgpu_virt_request_full_gpu(adev, true);
4184 if (r)
4185 return r;
4186 }
4187
4188 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
4189 return 0;
4190
4191 if (adev->in_s0ix)
4192 amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D0Entry);
4193
4194 /* post card */
4195 if (amdgpu_device_need_post(adev)) {
4196 r = amdgpu_device_asic_init(adev);
4197 if (r)
4198 dev_err(adev->dev, "amdgpu asic init failed\n");
4199 }
4200
4201 r = amdgpu_device_ip_resume(adev);
4202
4203 if (r) {
4204 dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r);
4205 goto exit;
4206 }
4207 amdgpu_fence_driver_hw_init(adev);
4208
4209 r = amdgpu_device_ip_late_init(adev);
4210 if (r)
4211 goto exit;
4212
4213 queue_delayed_work(system_wq, &adev->delayed_init_work,
4214 msecs_to_jiffies(AMDGPU_RESUME_MS));
4215
4216 if (!adev->in_s0ix) {
4217 r = amdgpu_amdkfd_resume(adev, adev->in_runpm);
4218 if (r)
4219 goto exit;
4220 }
4221
4222exit:
4223 if (amdgpu_sriov_vf(adev)) {
4224 amdgpu_virt_init_data_exchange(adev);
4225 amdgpu_virt_release_full_gpu(adev, true);
4226 }
4227
4228 if (r)
4229 return r;
4230
4231 /* Make sure IB tests flushed */
4232 flush_delayed_work(&adev->delayed_init_work);
4233
4234 if (adev->in_s0ix) {
4235 /* re-enable gfxoff after IP resume. This re-enables gfxoff after
4236 * it was disabled for IP resume in amdgpu_device_ip_resume_phase2().
4237 */
4238 amdgpu_gfx_off_ctrl(adev, true);
4239 DRM_DEBUG("will enable gfxoff for the mission mode\n");
4240 }
4241 if (fbcon)
4242 drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false);
4243
4244 drm_kms_helper_poll_enable(dev);
4245
4246 amdgpu_ras_resume(adev);
4247
4248 if (adev->mode_info.num_crtc) {
4249 /*
4250 * Most of the connector probing functions try to acquire runtime pm
4251 * refs to ensure that the GPU is powered on when connector polling is
4252 * performed. Since we're calling this from a runtime PM callback,
4253 * trying to acquire rpm refs will cause us to deadlock.
4254 *
4255 * Since we're guaranteed to be holding the rpm lock, it's safe to
4256 * temporarily disable the rpm helpers so this doesn't deadlock us.
4257 */
4258#ifdef CONFIG_PM
4259 dev->dev->power.disable_depth++;
4260#endif
4261 if (!adev->dc_enabled)
4262 drm_helper_hpd_irq_event(dev);
4263 else
4264 drm_kms_helper_hotplug_event(dev);
4265#ifdef CONFIG_PM
4266 dev->dev->power.disable_depth--;
4267#endif
4268 }
4269 adev->in_suspend = false;
4270
4271 if (adev->enable_mes)
4272 amdgpu_mes_self_test(adev);
4273
4274 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DEV_D0))
4275 DRM_WARN("smart shift update failed\n");
4276
4277 return 0;
4278}
4279
4280/**
4281 * amdgpu_device_ip_check_soft_reset - did soft reset succeed
4282 *
4283 * @adev: amdgpu_device pointer
4284 *
4285 * The list of all the hardware IPs that make up the asic is walked and
4286 * the check_soft_reset callbacks are run. check_soft_reset determines
4287 * if the asic is still hung or not.
4288 * Returns true if any of the IPs are still in a hung state, false if not.
4289 */
4290static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
4291{
4292 int i;
4293 bool asic_hang = false;
4294
4295 if (amdgpu_sriov_vf(adev))
4296 return true;
4297
4298 if (amdgpu_asic_need_full_reset(adev))
4299 return true;
4300
4301 for (i = 0; i < adev->num_ip_blocks; i++) {
4302 if (!adev->ip_blocks[i].status.valid)
4303 continue;
4304 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
4305 adev->ip_blocks[i].status.hang =
4306 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
4307 if (adev->ip_blocks[i].status.hang) {
4308 dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
4309 asic_hang = true;
4310 }
4311 }
4312 return asic_hang;
4313}
4314
4315/**
4316 * amdgpu_device_ip_pre_soft_reset - prepare for soft reset
4317 *
4318 * @adev: amdgpu_device pointer
4319 *
4320 * The list of all the hardware IPs that make up the asic is walked and the
4321 * pre_soft_reset callbacks are run if the block is hung. pre_soft_reset
4322 * handles any IP specific hardware or software state changes that are
4323 * necessary for a soft reset to succeed.
4324 * Returns 0 on success, negative error code on failure.
4325 */
4326static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev)
4327{
4328 int i, r = 0;
4329
4330 for (i = 0; i < adev->num_ip_blocks; i++) {
4331 if (!adev->ip_blocks[i].status.valid)
4332 continue;
4333 if (adev->ip_blocks[i].status.hang &&
4334 adev->ip_blocks[i].version->funcs->pre_soft_reset) {
4335 r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
4336 if (r)
4337 return r;
4338 }
4339 }
4340
4341 return 0;
4342}
4343
4344/**
4345 * amdgpu_device_ip_need_full_reset - check if a full asic reset is needed
4346 *
4347 * @adev: amdgpu_device pointer
4348 *
4349 * Some hardware IPs cannot be soft reset. If they are hung, a full gpu
4350 * reset is necessary to recover.
4351 * Returns true if a full asic reset is required, false if not.
4352 */
4353static bool amdgpu_device_ip_need_full_reset(struct amdgpu_device *adev)
4354{
4355 int i;
4356
4357 if (amdgpu_asic_need_full_reset(adev))
4358 return true;
4359
4360 for (i = 0; i < adev->num_ip_blocks; i++) {
4361 if (!adev->ip_blocks[i].status.valid)
4362 continue;
4363 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
4364 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
4365 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
4366 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
4367 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
4368 if (adev->ip_blocks[i].status.hang) {
4369 dev_info(adev->dev, "Some block need full reset!\n");
4370 return true;
4371 }
4372 }
4373 }
4374 return false;
4375}
4376
4377/**
4378 * amdgpu_device_ip_soft_reset - do a soft reset
4379 *
4380 * @adev: amdgpu_device pointer
4381 *
4382 * The list of all the hardware IPs that make up the asic is walked and the
4383 * soft_reset callbacks are run if the block is hung. soft_reset handles any
4384 * IP specific hardware or software state changes that are necessary to soft
4385 * reset the IP.
4386 * Returns 0 on success, negative error code on failure.
4387 */
4388static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev)
4389{
4390 int i, r = 0;
4391
4392 for (i = 0; i < adev->num_ip_blocks; i++) {
4393 if (!adev->ip_blocks[i].status.valid)
4394 continue;
4395 if (adev->ip_blocks[i].status.hang &&
4396 adev->ip_blocks[i].version->funcs->soft_reset) {
4397 r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
4398 if (r)
4399 return r;
4400 }
4401 }
4402
4403 return 0;
4404}
4405
4406/**
4407 * amdgpu_device_ip_post_soft_reset - clean up from soft reset
4408 *
4409 * @adev: amdgpu_device pointer
4410 *
4411 * The list of all the hardware IPs that make up the asic is walked and the
4412 * post_soft_reset callbacks are run if the asic was hung. post_soft_reset
4413 * handles any IP specific hardware or software state changes that are
4414 * necessary after the IP has been soft reset.
4415 * Returns 0 on success, negative error code on failure.
4416 */
4417static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev)
4418{
4419 int i, r = 0;
4420
4421 for (i = 0; i < adev->num_ip_blocks; i++) {
4422 if (!adev->ip_blocks[i].status.valid)
4423 continue;
4424 if (adev->ip_blocks[i].status.hang &&
4425 adev->ip_blocks[i].version->funcs->post_soft_reset)
4426 r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
4427 if (r)
4428 return r;
4429 }
4430
4431 return 0;
4432}
4433
4434/**
4435 * amdgpu_device_recover_vram - Recover some VRAM contents
4436 *
4437 * @adev: amdgpu_device pointer
4438 *
4439 * Restores the contents of VRAM buffers from the shadows in GTT. Used to
4440 * restore things like GPUVM page tables after a GPU reset where
4441 * the contents of VRAM might be lost.
4442 *
4443 * Returns:
4444 * 0 on success, negative error code on failure.
4445 */
4446static int amdgpu_device_recover_vram(struct amdgpu_device *adev)
4447{
4448 struct dma_fence *fence = NULL, *next = NULL;
4449 struct amdgpu_bo *shadow;
4450 struct amdgpu_bo_vm *vmbo;
4451 long r = 1, tmo;
4452
4453 if (amdgpu_sriov_runtime(adev))
4454 tmo = msecs_to_jiffies(8000);
4455 else
4456 tmo = msecs_to_jiffies(100);
4457
4458 dev_info(adev->dev, "recover vram bo from shadow start\n");
4459 mutex_lock(&adev->shadow_list_lock);
4460 list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) {
4461 shadow = &vmbo->bo;
4462 /* No need to recover an evicted BO */
4463 if (shadow->tbo.resource->mem_type != TTM_PL_TT ||
4464 shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET ||
4465 shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM)
4466 continue;
4467
4468 r = amdgpu_bo_restore_shadow(shadow, &next);
4469 if (r)
4470 break;
4471
4472 if (fence) {
4473 tmo = dma_fence_wait_timeout(fence, false, tmo);
4474 dma_fence_put(fence);
4475 fence = next;
4476 if (tmo == 0) {
4477 r = -ETIMEDOUT;
4478 break;
4479 } else if (tmo < 0) {
4480 r = tmo;
4481 break;
4482 }
4483 } else {
4484 fence = next;
4485 }
4486 }
4487 mutex_unlock(&adev->shadow_list_lock);
4488
4489 if (fence)
4490 tmo = dma_fence_wait_timeout(fence, false, tmo);
4491 dma_fence_put(fence);
4492
4493 if (r < 0 || tmo <= 0) {
4494 dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo);
4495 return -EIO;
4496 }
4497
4498 dev_info(adev->dev, "recover vram bo from shadow done\n");
4499 return 0;
4500}
4501
4502
4503/**
4504 * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
4505 *
4506 * @adev: amdgpu_device pointer
4507 * @from_hypervisor: request from hypervisor
4508 *
4509 * do VF FLR and reinitialize Asic
4510 * return 0 means succeeded otherwise failed
4511 */
4512static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
4513 bool from_hypervisor)
4514{
4515 int r;
4516 struct amdgpu_hive_info *hive = NULL;
4517 int retry_limit = 0;
4518
4519retry:
4520 amdgpu_amdkfd_pre_reset(adev);
4521
4522 if (from_hypervisor)
4523 r = amdgpu_virt_request_full_gpu(adev, true);
4524 else
4525 r = amdgpu_virt_reset_gpu(adev);
4526 if (r)
4527 return r;
4528
4529 /* Resume IP prior to SMC */
4530 r = amdgpu_device_ip_reinit_early_sriov(adev);
4531 if (r)
4532 goto error;
4533
4534 amdgpu_virt_init_data_exchange(adev);
4535
4536 r = amdgpu_device_fw_loading(adev);
4537 if (r)
4538 return r;
4539
4540 /* now we are okay to resume SMC/CP/SDMA */
4541 r = amdgpu_device_ip_reinit_late_sriov(adev);
4542 if (r)
4543 goto error;
4544
4545 hive = amdgpu_get_xgmi_hive(adev);
4546 /* Update PSP FW topology after reset */
4547 if (hive && adev->gmc.xgmi.num_physical_nodes > 1)
4548 r = amdgpu_xgmi_update_topology(hive, adev);
4549
4550 if (hive)
4551 amdgpu_put_xgmi_hive(hive);
4552
4553 if (!r) {
4554 amdgpu_irq_gpu_reset_resume_helper(adev);
4555 r = amdgpu_ib_ring_tests(adev);
4556
4557 amdgpu_amdkfd_post_reset(adev);
4558 }
4559
4560error:
4561 if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
4562 amdgpu_inc_vram_lost(adev);
4563 r = amdgpu_device_recover_vram(adev);
4564 }
4565 amdgpu_virt_release_full_gpu(adev, true);
4566
4567 if (AMDGPU_RETRY_SRIOV_RESET(r)) {
4568 if (retry_limit < AMDGPU_MAX_RETRY_LIMIT) {
4569 retry_limit++;
4570 goto retry;
4571 } else
4572 DRM_ERROR("GPU reset retry is beyond the retry limit\n");
4573 }
4574
4575 return r;
4576}
4577
4578/**
4579 * amdgpu_device_has_job_running - check if there is any job in mirror list
4580 *
4581 * @adev: amdgpu_device pointer
4582 *
4583 * check if there is any job in mirror list
4584 */
4585bool amdgpu_device_has_job_running(struct amdgpu_device *adev)
4586{
4587 int i;
4588 struct drm_sched_job *job;
4589
4590 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4591 struct amdgpu_ring *ring = adev->rings[i];
4592
4593 if (!ring || !ring->sched.thread)
4594 continue;
4595
4596 spin_lock(&ring->sched.job_list_lock);
4597 job = list_first_entry_or_null(&ring->sched.pending_list,
4598 struct drm_sched_job, list);
4599 spin_unlock(&ring->sched.job_list_lock);
4600 if (job)
4601 return true;
4602 }
4603 return false;
4604}
4605
4606/**
4607 * amdgpu_device_should_recover_gpu - check if we should try GPU recovery
4608 *
4609 * @adev: amdgpu_device pointer
4610 *
4611 * Check amdgpu_gpu_recovery and SRIOV status to see if we should try to recover
4612 * a hung GPU.
4613 */
4614bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
4615{
4616
4617 if (amdgpu_gpu_recovery == 0)
4618 goto disabled;
4619
4620 /* Skip soft reset check in fatal error mode */
4621 if (!amdgpu_ras_is_poison_mode_supported(adev))
4622 return true;
4623
4624 if (!amdgpu_device_ip_check_soft_reset(adev)) {
4625 dev_info(adev->dev,"Timeout, but no hardware hang detected.\n");
4626 return false;
4627 }
4628
4629 if (amdgpu_sriov_vf(adev))
4630 return true;
4631
4632 if (amdgpu_gpu_recovery == -1) {
4633 switch (adev->asic_type) {
4634#ifdef CONFIG_DRM_AMDGPU_SI
4635 case CHIP_VERDE:
4636 case CHIP_TAHITI:
4637 case CHIP_PITCAIRN:
4638 case CHIP_OLAND:
4639 case CHIP_HAINAN:
4640#endif
4641#ifdef CONFIG_DRM_AMDGPU_CIK
4642 case CHIP_KAVERI:
4643 case CHIP_KABINI:
4644 case CHIP_MULLINS:
4645#endif
4646 case CHIP_CARRIZO:
4647 case CHIP_STONEY:
4648 case CHIP_CYAN_SKILLFISH:
4649 goto disabled;
4650 default:
4651 break;
4652 }
4653 }
4654
4655 return true;
4656
4657disabled:
4658 dev_info(adev->dev, "GPU recovery disabled.\n");
4659 return false;
4660}
4661
4662int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
4663{
4664 u32 i;
4665 int ret = 0;
4666
4667 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
4668
4669 dev_info(adev->dev, "GPU mode1 reset\n");
4670
4671 /* disable BM */
4672 pci_clear_master(adev->pdev);
4673
4674 amdgpu_device_cache_pci_state(adev->pdev);
4675
4676 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
4677 dev_info(adev->dev, "GPU smu mode1 reset\n");
4678 ret = amdgpu_dpm_mode1_reset(adev);
4679 } else {
4680 dev_info(adev->dev, "GPU psp mode1 reset\n");
4681 ret = psp_gpu_reset(adev);
4682 }
4683
4684 if (ret)
4685 dev_err(adev->dev, "GPU mode1 reset failed\n");
4686
4687 amdgpu_device_load_pci_state(adev->pdev);
4688
4689 /* wait for asic to come out of reset */
4690 for (i = 0; i < adev->usec_timeout; i++) {
4691 u32 memsize = adev->nbio.funcs->get_memsize(adev);
4692
4693 if (memsize != 0xffffffff)
4694 break;
4695 udelay(1);
4696 }
4697
4698 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
4699 return ret;
4700}
4701
4702int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
4703 struct amdgpu_reset_context *reset_context)
4704{
4705 int i, r = 0;
4706 struct amdgpu_job *job = NULL;
4707 bool need_full_reset =
4708 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4709
4710 if (reset_context->reset_req_dev == adev)
4711 job = reset_context->job;
4712
4713 if (amdgpu_sriov_vf(adev)) {
4714 /* stop the data exchange thread */
4715 amdgpu_virt_fini_data_exchange(adev);
4716 }
4717
4718 amdgpu_fence_driver_isr_toggle(adev, true);
4719
4720 /* block all schedulers and reset given job's ring */
4721 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
4722 struct amdgpu_ring *ring = adev->rings[i];
4723
4724 if (!ring || !ring->sched.thread)
4725 continue;
4726
4727 /*clear job fence from fence drv to avoid force_completion
4728 *leave NULL and vm flush fence in fence drv */
4729 amdgpu_fence_driver_clear_job_fences(ring);
4730
4731 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
4732 amdgpu_fence_driver_force_completion(ring);
4733 }
4734
4735 amdgpu_fence_driver_isr_toggle(adev, false);
4736
4737 if (job && job->vm)
4738 drm_sched_increase_karma(&job->base);
4739
4740 r = amdgpu_reset_prepare_hwcontext(adev, reset_context);
4741 /* If reset handler not implemented, continue; otherwise return */
4742 if (r == -ENOSYS)
4743 r = 0;
4744 else
4745 return r;
4746
4747 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
4748 if (!amdgpu_sriov_vf(adev)) {
4749
4750 if (!need_full_reset)
4751 need_full_reset = amdgpu_device_ip_need_full_reset(adev);
4752
4753 if (!need_full_reset && amdgpu_gpu_recovery) {
4754 amdgpu_device_ip_pre_soft_reset(adev);
4755 r = amdgpu_device_ip_soft_reset(adev);
4756 amdgpu_device_ip_post_soft_reset(adev);
4757 if (r || amdgpu_device_ip_check_soft_reset(adev)) {
4758 dev_info(adev->dev, "soft reset failed, will fallback to full reset!\n");
4759 need_full_reset = true;
4760 }
4761 }
4762
4763 if (need_full_reset)
4764 r = amdgpu_device_ip_suspend(adev);
4765 if (need_full_reset)
4766 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4767 else
4768 clear_bit(AMDGPU_NEED_FULL_RESET,
4769 &reset_context->flags);
4770 }
4771
4772 return r;
4773}
4774
4775static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)
4776{
4777 int i;
4778
4779 lockdep_assert_held(&adev->reset_domain->sem);
4780
4781 for (i = 0; i < adev->num_regs; i++) {
4782 adev->reset_dump_reg_value[i] = RREG32(adev->reset_dump_reg_list[i]);
4783 trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i],
4784 adev->reset_dump_reg_value[i]);
4785 }
4786
4787 return 0;
4788}
4789
4790#ifdef CONFIG_DEV_COREDUMP
4791static ssize_t amdgpu_devcoredump_read(char *buffer, loff_t offset,
4792 size_t count, void *data, size_t datalen)
4793{
4794 struct drm_printer p;
4795 struct amdgpu_device *adev = data;
4796 struct drm_print_iterator iter;
4797 int i;
4798
4799 iter.data = buffer;
4800 iter.offset = 0;
4801 iter.start = offset;
4802 iter.remain = count;
4803
4804 p = drm_coredump_printer(&iter);
4805
4806 drm_printf(&p, "**** AMDGPU Device Coredump ****\n");
4807 drm_printf(&p, "kernel: " UTS_RELEASE "\n");
4808 drm_printf(&p, "module: " KBUILD_MODNAME "\n");
4809 drm_printf(&p, "time: %lld.%09ld\n", adev->reset_time.tv_sec, adev->reset_time.tv_nsec);
4810 if (adev->reset_task_info.pid)
4811 drm_printf(&p, "process_name: %s PID: %d\n",
4812 adev->reset_task_info.process_name,
4813 adev->reset_task_info.pid);
4814
4815 if (adev->reset_vram_lost)
4816 drm_printf(&p, "VRAM is lost due to GPU reset!\n");
4817 if (adev->num_regs) {
4818 drm_printf(&p, "AMDGPU register dumps:\nOffset: Value:\n");
4819
4820 for (i = 0; i < adev->num_regs; i++)
4821 drm_printf(&p, "0x%08x: 0x%08x\n",
4822 adev->reset_dump_reg_list[i],
4823 adev->reset_dump_reg_value[i]);
4824 }
4825
4826 return count - iter.remain;
4827}
4828
4829static void amdgpu_devcoredump_free(void *data)
4830{
4831}
4832
4833static void amdgpu_reset_capture_coredumpm(struct amdgpu_device *adev)
4834{
4835 struct drm_device *dev = adev_to_drm(adev);
4836
4837 ktime_get_ts64(&adev->reset_time);
4838 dev_coredumpm(dev->dev, THIS_MODULE, adev, 0, GFP_KERNEL,
4839 amdgpu_devcoredump_read, amdgpu_devcoredump_free);
4840}
4841#endif
4842
4843int amdgpu_do_asic_reset(struct list_head *device_list_handle,
4844 struct amdgpu_reset_context *reset_context)
4845{
4846 struct amdgpu_device *tmp_adev = NULL;
4847 bool need_full_reset, skip_hw_reset, vram_lost = false;
4848 int r = 0;
4849 bool gpu_reset_for_dev_remove = 0;
4850
4851 /* Try reset handler method first */
4852 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
4853 reset_list);
4854 amdgpu_reset_reg_dumps(tmp_adev);
4855
4856 reset_context->reset_device_list = device_list_handle;
4857 r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
4858 /* If reset handler not implemented, continue; otherwise return */
4859 if (r == -ENOSYS)
4860 r = 0;
4861 else
4862 return r;
4863
4864 /* Reset handler not implemented, use the default method */
4865 need_full_reset =
4866 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4867 skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags);
4868
4869 gpu_reset_for_dev_remove =
4870 test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) &&
4871 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
4872
4873 /*
4874 * ASIC reset has to be done on all XGMI hive nodes ASAP
4875 * to allow proper links negotiation in FW (within 1 sec)
4876 */
4877 if (!skip_hw_reset && need_full_reset) {
4878 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4879 /* For XGMI run all resets in parallel to speed up the process */
4880 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4881 tmp_adev->gmc.xgmi.pending_reset = false;
4882 if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work))
4883 r = -EALREADY;
4884 } else
4885 r = amdgpu_asic_reset(tmp_adev);
4886
4887 if (r) {
4888 dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s",
4889 r, adev_to_drm(tmp_adev)->unique);
4890 break;
4891 }
4892 }
4893
4894 /* For XGMI wait for all resets to complete before proceed */
4895 if (!r) {
4896 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4897 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
4898 flush_work(&tmp_adev->xgmi_reset_work);
4899 r = tmp_adev->asic_reset_res;
4900 if (r)
4901 break;
4902 }
4903 }
4904 }
4905 }
4906
4907 if (!r && amdgpu_ras_intr_triggered()) {
4908 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4909 if (tmp_adev->mmhub.ras && tmp_adev->mmhub.ras->ras_block.hw_ops &&
4910 tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
4911 tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(tmp_adev);
4912 }
4913
4914 amdgpu_ras_intr_cleared();
4915 }
4916
4917 /* Since the mode1 reset affects base ip blocks, the
4918 * phase1 ip blocks need to be resumed. Otherwise there
4919 * will be a BIOS signature error and the psp bootloader
4920 * can't load kdb on the next amdgpu install.
4921 */
4922 if (gpu_reset_for_dev_remove) {
4923 list_for_each_entry(tmp_adev, device_list_handle, reset_list)
4924 amdgpu_device_ip_resume_phase1(tmp_adev);
4925
4926 goto end;
4927 }
4928
4929 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4930 if (need_full_reset) {
4931 /* post card */
4932 r = amdgpu_device_asic_init(tmp_adev);
4933 if (r) {
4934 dev_warn(tmp_adev->dev, "asic atom init failed!");
4935 } else {
4936 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
4937 r = amdgpu_amdkfd_resume_iommu(tmp_adev);
4938 if (r)
4939 goto out;
4940
4941 r = amdgpu_device_ip_resume_phase1(tmp_adev);
4942 if (r)
4943 goto out;
4944
4945 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
4946#ifdef CONFIG_DEV_COREDUMP
4947 tmp_adev->reset_vram_lost = vram_lost;
4948 memset(&tmp_adev->reset_task_info, 0,
4949 sizeof(tmp_adev->reset_task_info));
4950 if (reset_context->job && reset_context->job->vm)
4951 tmp_adev->reset_task_info =
4952 reset_context->job->vm->task_info;
4953 amdgpu_reset_capture_coredumpm(tmp_adev);
4954#endif
4955 if (vram_lost) {
4956 DRM_INFO("VRAM is lost due to GPU reset!\n");
4957 amdgpu_inc_vram_lost(tmp_adev);
4958 }
4959
4960 r = amdgpu_device_fw_loading(tmp_adev);
4961 if (r)
4962 return r;
4963
4964 r = amdgpu_device_ip_resume_phase2(tmp_adev);
4965 if (r)
4966 goto out;
4967
4968 if (vram_lost)
4969 amdgpu_device_fill_reset_magic(tmp_adev);
4970
4971 /*
4972 * Add this ASIC as tracked as reset was already
4973 * complete successfully.
4974 */
4975 amdgpu_register_gpu_instance(tmp_adev);
4976
4977 if (!reset_context->hive &&
4978 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
4979 amdgpu_xgmi_add_device(tmp_adev);
4980
4981 r = amdgpu_device_ip_late_init(tmp_adev);
4982 if (r)
4983 goto out;
4984
4985 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, false);
4986
4987 /*
4988 * The GPU enters bad state once faulty pages
4989 * by ECC has reached the threshold, and ras
4990 * recovery is scheduled next. So add one check
4991 * here to break recovery if it indeed exceeds
4992 * bad page threshold, and remind user to
4993 * retire this GPU or setting one bigger
4994 * bad_page_threshold value to fix this once
4995 * probing driver again.
4996 */
4997 if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) {
4998 /* must succeed. */
4999 amdgpu_ras_resume(tmp_adev);
5000 } else {
5001 r = -EINVAL;
5002 goto out;
5003 }
5004
5005 /* Update PSP FW topology after reset */
5006 if (reset_context->hive &&
5007 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5008 r = amdgpu_xgmi_update_topology(
5009 reset_context->hive, tmp_adev);
5010 }
5011 }
5012
5013out:
5014 if (!r) {
5015 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
5016 r = amdgpu_ib_ring_tests(tmp_adev);
5017 if (r) {
5018 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
5019 need_full_reset = true;
5020 r = -EAGAIN;
5021 goto end;
5022 }
5023 }
5024
5025 if (!r)
5026 r = amdgpu_device_recover_vram(tmp_adev);
5027 else
5028 tmp_adev->asic_reset_res = r;
5029 }
5030
5031end:
5032 if (need_full_reset)
5033 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5034 else
5035 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5036 return r;
5037}
5038
5039static void amdgpu_device_set_mp1_state(struct amdgpu_device *adev)
5040{
5041
5042 switch (amdgpu_asic_reset_method(adev)) {
5043 case AMD_RESET_METHOD_MODE1:
5044 adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
5045 break;
5046 case AMD_RESET_METHOD_MODE2:
5047 adev->mp1_state = PP_MP1_STATE_RESET;
5048 break;
5049 default:
5050 adev->mp1_state = PP_MP1_STATE_NONE;
5051 break;
5052 }
5053}
5054
5055static void amdgpu_device_unset_mp1_state(struct amdgpu_device *adev)
5056{
5057 amdgpu_vf_error_trans_all(adev);
5058 adev->mp1_state = PP_MP1_STATE_NONE;
5059}
5060
5061static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev)
5062{
5063 struct pci_dev *p = NULL;
5064
5065 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5066 adev->pdev->bus->number, 1);
5067 if (p) {
5068 pm_runtime_enable(&(p->dev));
5069 pm_runtime_resume(&(p->dev));
5070 }
5071
5072 pci_dev_put(p);
5073}
5074
5075static int amdgpu_device_suspend_display_audio(struct amdgpu_device *adev)
5076{
5077 enum amd_reset_method reset_method;
5078 struct pci_dev *p = NULL;
5079 u64 expires;
5080
5081 /*
5082 * For now, only BACO and mode1 reset are confirmed
5083 * to suffer the audio issue without proper suspended.
5084 */
5085 reset_method = amdgpu_asic_reset_method(adev);
5086 if ((reset_method != AMD_RESET_METHOD_BACO) &&
5087 (reset_method != AMD_RESET_METHOD_MODE1))
5088 return -EINVAL;
5089
5090 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
5091 adev->pdev->bus->number, 1);
5092 if (!p)
5093 return -ENODEV;
5094
5095 expires = pm_runtime_autosuspend_expiration(&(p->dev));
5096 if (!expires)
5097 /*
5098 * If we cannot get the audio device autosuspend delay,
5099 * a fixed 4S interval will be used. Considering 3S is
5100 * the audio controller default autosuspend delay setting.
5101 * 4S used here is guaranteed to cover that.
5102 */
5103 expires = ktime_get_mono_fast_ns() + NSEC_PER_SEC * 4ULL;
5104
5105 while (!pm_runtime_status_suspended(&(p->dev))) {
5106 if (!pm_runtime_suspend(&(p->dev)))
5107 break;
5108
5109 if (expires < ktime_get_mono_fast_ns()) {
5110 dev_warn(adev->dev, "failed to suspend display audio\n");
5111 pci_dev_put(p);
5112 /* TODO: abort the succeeding gpu reset? */
5113 return -ETIMEDOUT;
5114 }
5115 }
5116
5117 pm_runtime_disable(&(p->dev));
5118
5119 pci_dev_put(p);
5120 return 0;
5121}
5122
5123static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev)
5124{
5125 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
5126
5127#if defined(CONFIG_DEBUG_FS)
5128 if (!amdgpu_sriov_vf(adev))
5129 cancel_work(&adev->reset_work);
5130#endif
5131
5132 if (adev->kfd.dev)
5133 cancel_work(&adev->kfd.reset_work);
5134
5135 if (amdgpu_sriov_vf(adev))
5136 cancel_work(&adev->virt.flr_work);
5137
5138 if (con && adev->ras_enabled)
5139 cancel_work(&con->recovery_work);
5140
5141}
5142
5143/**
5144 * amdgpu_device_gpu_recover - reset the asic and recover scheduler
5145 *
5146 * @adev: amdgpu_device pointer
5147 * @job: which job trigger hang
5148 *
5149 * Attempt to reset the GPU if it has hung (all asics).
5150 * Attempt to do soft-reset or full-reset and reinitialize Asic
5151 * Returns 0 for success or an error on failure.
5152 */
5153
5154int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
5155 struct amdgpu_job *job,
5156 struct amdgpu_reset_context *reset_context)
5157{
5158 struct list_head device_list, *device_list_handle = NULL;
5159 bool job_signaled = false;
5160 struct amdgpu_hive_info *hive = NULL;
5161 struct amdgpu_device *tmp_adev = NULL;
5162 int i, r = 0;
5163 bool need_emergency_restart = false;
5164 bool audio_suspended = false;
5165 bool gpu_reset_for_dev_remove = false;
5166
5167 gpu_reset_for_dev_remove =
5168 test_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context->flags) &&
5169 test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
5170
5171 /*
5172 * Special case: RAS triggered and full reset isn't supported
5173 */
5174 need_emergency_restart = amdgpu_ras_need_emergency_restart(adev);
5175
5176 /*
5177 * Flush RAM to disk so that after reboot
5178 * the user can read log and see why the system rebooted.
5179 */
5180 if (need_emergency_restart && amdgpu_ras_get_context(adev)->reboot) {
5181 DRM_WARN("Emergency reboot.");
5182
5183 ksys_sync_helper();
5184 emergency_restart();
5185 }
5186
5187 dev_info(adev->dev, "GPU %s begin!\n",
5188 need_emergency_restart ? "jobs stop":"reset");
5189
5190 if (!amdgpu_sriov_vf(adev))
5191 hive = amdgpu_get_xgmi_hive(adev);
5192 if (hive)
5193 mutex_lock(&hive->hive_lock);
5194
5195 reset_context->job = job;
5196 reset_context->hive = hive;
5197 /*
5198 * Build list of devices to reset.
5199 * In case we are in XGMI hive mode, resort the device list
5200 * to put adev in the 1st position.
5201 */
5202 INIT_LIST_HEAD(&device_list);
5203 if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1)) {
5204 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
5205 list_add_tail(&tmp_adev->reset_list, &device_list);
5206 if (gpu_reset_for_dev_remove && adev->shutdown)
5207 tmp_adev->shutdown = true;
5208 }
5209 if (!list_is_first(&adev->reset_list, &device_list))
5210 list_rotate_to_front(&adev->reset_list, &device_list);
5211 device_list_handle = &device_list;
5212 } else {
5213 list_add_tail(&adev->reset_list, &device_list);
5214 device_list_handle = &device_list;
5215 }
5216
5217 /* We need to lock reset domain only once both for XGMI and single device */
5218 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5219 reset_list);
5220 amdgpu_device_lock_reset_domain(tmp_adev->reset_domain);
5221
5222 /* block all schedulers and reset given job's ring */
5223 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5224
5225 amdgpu_device_set_mp1_state(tmp_adev);
5226
5227 /*
5228 * Try to put the audio codec into suspend state
5229 * before gpu reset started.
5230 *
5231 * Due to the power domain of the graphics device
5232 * is shared with AZ power domain. Without this,
5233 * we may change the audio hardware from behind
5234 * the audio driver's back. That will trigger
5235 * some audio codec errors.
5236 */
5237 if (!amdgpu_device_suspend_display_audio(tmp_adev))
5238 audio_suspended = true;
5239
5240 amdgpu_ras_set_error_query_ready(tmp_adev, false);
5241
5242 cancel_delayed_work_sync(&tmp_adev->delayed_init_work);
5243
5244 if (!amdgpu_sriov_vf(tmp_adev))
5245 amdgpu_amdkfd_pre_reset(tmp_adev);
5246
5247 /*
5248 * Mark these ASICs to be reseted as untracked first
5249 * And add them back after reset completed
5250 */
5251 amdgpu_unregister_gpu_instance(tmp_adev);
5252
5253 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true);
5254
5255 /* disable ras on ALL IPs */
5256 if (!need_emergency_restart &&
5257 amdgpu_device_ip_need_full_reset(tmp_adev))
5258 amdgpu_ras_suspend(tmp_adev);
5259
5260 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5261 struct amdgpu_ring *ring = tmp_adev->rings[i];
5262
5263 if (!ring || !ring->sched.thread)
5264 continue;
5265
5266 drm_sched_stop(&ring->sched, job ? &job->base : NULL);
5267
5268 if (need_emergency_restart)
5269 amdgpu_job_stop_all_jobs_on_sched(&ring->sched);
5270 }
5271 atomic_inc(&tmp_adev->gpu_reset_counter);
5272 }
5273
5274 if (need_emergency_restart)
5275 goto skip_sched_resume;
5276
5277 /*
5278 * Must check guilty signal here since after this point all old
5279 * HW fences are force signaled.
5280 *
5281 * job->base holds a reference to parent fence
5282 */
5283 if (job && dma_fence_is_signaled(&job->hw_fence)) {
5284 job_signaled = true;
5285 dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
5286 goto skip_hw_reset;
5287 }
5288
5289retry: /* Rest of adevs pre asic reset from XGMI hive. */
5290 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5291 if (gpu_reset_for_dev_remove) {
5292 /* Workaroud for ASICs need to disable SMC first */
5293 amdgpu_device_smu_fini_early(tmp_adev);
5294 }
5295 r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context);
5296 /*TODO Should we stop ?*/
5297 if (r) {
5298 dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
5299 r, adev_to_drm(tmp_adev)->unique);
5300 tmp_adev->asic_reset_res = r;
5301 }
5302
5303 /*
5304 * Drop all pending non scheduler resets. Scheduler resets
5305 * were already dropped during drm_sched_stop
5306 */
5307 amdgpu_device_stop_pending_resets(tmp_adev);
5308 }
5309
5310 /* Actual ASIC resets if needed.*/
5311 /* Host driver will handle XGMI hive reset for SRIOV */
5312 if (amdgpu_sriov_vf(adev)) {
5313 r = amdgpu_device_reset_sriov(adev, job ? false : true);
5314 if (r)
5315 adev->asic_reset_res = r;
5316
5317 /* Aldebaran supports ras in SRIOV, so need resume ras during reset */
5318 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
5319 amdgpu_ras_resume(adev);
5320 } else {
5321 r = amdgpu_do_asic_reset(device_list_handle, reset_context);
5322 if (r && r == -EAGAIN)
5323 goto retry;
5324
5325 if (!r && gpu_reset_for_dev_remove)
5326 goto recover_end;
5327 }
5328
5329skip_hw_reset:
5330
5331 /* Post ASIC reset for all devs .*/
5332 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5333
5334 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5335 struct amdgpu_ring *ring = tmp_adev->rings[i];
5336
5337 if (!ring || !ring->sched.thread)
5338 continue;
5339
5340 drm_sched_start(&ring->sched, true);
5341 }
5342
5343 if (adev->enable_mes && adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3))
5344 amdgpu_mes_self_test(tmp_adev);
5345
5346 if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled) {
5347 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
5348 }
5349
5350 if (tmp_adev->asic_reset_res)
5351 r = tmp_adev->asic_reset_res;
5352
5353 tmp_adev->asic_reset_res = 0;
5354
5355 if (r) {
5356 /* bad news, how to tell it to userspace ? */
5357 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
5358 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
5359 } else {
5360 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
5361 if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0))
5362 DRM_WARN("smart shift update failed\n");
5363 }
5364 }
5365
5366skip_sched_resume:
5367 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5368 /* unlock kfd: SRIOV would do it separately */
5369 if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev))
5370 amdgpu_amdkfd_post_reset(tmp_adev);
5371
5372 /* kfd_post_reset will do nothing if kfd device is not initialized,
5373 * need to bring up kfd here if it's not be initialized before
5374 */
5375 if (!adev->kfd.init_complete)
5376 amdgpu_amdkfd_device_init(adev);
5377
5378 if (audio_suspended)
5379 amdgpu_device_resume_display_audio(tmp_adev);
5380
5381 amdgpu_device_unset_mp1_state(tmp_adev);
5382
5383 amdgpu_ras_set_error_query_ready(tmp_adev, true);
5384 }
5385
5386recover_end:
5387 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5388 reset_list);
5389 amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain);
5390
5391 if (hive) {
5392 mutex_unlock(&hive->hive_lock);
5393 amdgpu_put_xgmi_hive(hive);
5394 }
5395
5396 if (r)
5397 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
5398
5399 atomic_set(&adev->reset_domain->reset_res, r);
5400 return r;
5401}
5402
5403/**
5404 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
5405 *
5406 * @adev: amdgpu_device pointer
5407 *
5408 * Fetchs and stores in the driver the PCIE capabilities (gen speed
5409 * and lanes) of the slot the device is in. Handles APUs and
5410 * virtualized environments where PCIE config space may not be available.
5411 */
5412static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
5413{
5414 struct pci_dev *pdev;
5415 enum pci_bus_speed speed_cap, platform_speed_cap;
5416 enum pcie_link_width platform_link_width;
5417
5418 if (amdgpu_pcie_gen_cap)
5419 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
5420
5421 if (amdgpu_pcie_lane_cap)
5422 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
5423
5424 /* covers APUs as well */
5425 if (pci_is_root_bus(adev->pdev->bus)) {
5426 if (adev->pm.pcie_gen_mask == 0)
5427 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
5428 if (adev->pm.pcie_mlw_mask == 0)
5429 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
5430 return;
5431 }
5432
5433 if (adev->pm.pcie_gen_mask && adev->pm.pcie_mlw_mask)
5434 return;
5435
5436 pcie_bandwidth_available(adev->pdev, NULL,
5437 &platform_speed_cap, &platform_link_width);
5438
5439 if (adev->pm.pcie_gen_mask == 0) {
5440 /* asic caps */
5441 pdev = adev->pdev;
5442 speed_cap = pcie_get_speed_cap(pdev);
5443 if (speed_cap == PCI_SPEED_UNKNOWN) {
5444 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5445 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5446 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5447 } else {
5448 if (speed_cap == PCIE_SPEED_32_0GT)
5449 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5450 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5451 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5452 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5453 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN5);
5454 else if (speed_cap == PCIE_SPEED_16_0GT)
5455 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5456 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5457 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5458 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
5459 else if (speed_cap == PCIE_SPEED_8_0GT)
5460 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5461 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5462 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
5463 else if (speed_cap == PCIE_SPEED_5_0GT)
5464 adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5465 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
5466 else
5467 adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
5468 }
5469 /* platform caps */
5470 if (platform_speed_cap == PCI_SPEED_UNKNOWN) {
5471 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5472 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5473 } else {
5474 if (platform_speed_cap == PCIE_SPEED_32_0GT)
5475 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5476 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5477 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5478 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 |
5479 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5);
5480 else if (platform_speed_cap == PCIE_SPEED_16_0GT)
5481 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5482 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5483 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
5484 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
5485 else if (platform_speed_cap == PCIE_SPEED_8_0GT)
5486 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5487 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
5488 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
5489 else if (platform_speed_cap == PCIE_SPEED_5_0GT)
5490 adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
5491 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
5492 else
5493 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
5494
5495 }
5496 }
5497 if (adev->pm.pcie_mlw_mask == 0) {
5498 if (platform_link_width == PCIE_LNK_WIDTH_UNKNOWN) {
5499 adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
5500 } else {
5501 switch (platform_link_width) {
5502 case PCIE_LNK_X32:
5503 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
5504 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5505 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5506 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5507 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5508 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5509 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5510 break;
5511 case PCIE_LNK_X16:
5512 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
5513 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5514 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5515 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5516 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5517 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5518 break;
5519 case PCIE_LNK_X12:
5520 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
5521 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5522 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5523 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5524 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5525 break;
5526 case PCIE_LNK_X8:
5527 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
5528 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5529 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5530 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5531 break;
5532 case PCIE_LNK_X4:
5533 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
5534 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5535 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5536 break;
5537 case PCIE_LNK_X2:
5538 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
5539 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
5540 break;
5541 case PCIE_LNK_X1:
5542 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
5543 break;
5544 default:
5545 break;
5546 }
5547 }
5548 }
5549}
5550
5551/**
5552 * amdgpu_device_is_peer_accessible - Check peer access through PCIe BAR
5553 *
5554 * @adev: amdgpu_device pointer
5555 * @peer_adev: amdgpu_device pointer for peer device trying to access @adev
5556 *
5557 * Return true if @peer_adev can access (DMA) @adev through the PCIe
5558 * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of
5559 * @peer_adev.
5560 */
5561bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
5562 struct amdgpu_device *peer_adev)
5563{
5564#ifdef CONFIG_HSA_AMD_P2P
5565 uint64_t address_mask = peer_adev->dev->dma_mask ?
5566 ~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1);
5567 resource_size_t aper_limit =
5568 adev->gmc.aper_base + adev->gmc.aper_size - 1;
5569 bool p2p_access =
5570 !adev->gmc.xgmi.connected_to_cpu &&
5571 !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0);
5572
5573 return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size &&
5574 adev->gmc.real_vram_size == adev->gmc.visible_vram_size &&
5575 !(adev->gmc.aper_base & address_mask ||
5576 aper_limit & address_mask));
5577#else
5578 return false;
5579#endif
5580}
5581
5582int amdgpu_device_baco_enter(struct drm_device *dev)
5583{
5584 struct amdgpu_device *adev = drm_to_adev(dev);
5585 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5586
5587 if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
5588 return -ENOTSUPP;
5589
5590 if (ras && adev->ras_enabled &&
5591 adev->nbio.funcs->enable_doorbell_interrupt)
5592 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
5593
5594 return amdgpu_dpm_baco_enter(adev);
5595}
5596
5597int amdgpu_device_baco_exit(struct drm_device *dev)
5598{
5599 struct amdgpu_device *adev = drm_to_adev(dev);
5600 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
5601 int ret = 0;
5602
5603 if (!amdgpu_device_supports_baco(adev_to_drm(adev)))
5604 return -ENOTSUPP;
5605
5606 ret = amdgpu_dpm_baco_exit(adev);
5607 if (ret)
5608 return ret;
5609
5610 if (ras && adev->ras_enabled &&
5611 adev->nbio.funcs->enable_doorbell_interrupt)
5612 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
5613
5614 if (amdgpu_passthrough(adev) &&
5615 adev->nbio.funcs->clear_doorbell_interrupt)
5616 adev->nbio.funcs->clear_doorbell_interrupt(adev);
5617
5618 return 0;
5619}
5620
5621/**
5622 * amdgpu_pci_error_detected - Called when a PCI error is detected.
5623 * @pdev: PCI device struct
5624 * @state: PCI channel state
5625 *
5626 * Description: Called when a PCI error is detected.
5627 *
5628 * Return: PCI_ERS_RESULT_NEED_RESET or PCI_ERS_RESULT_DISCONNECT.
5629 */
5630pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5631{
5632 struct drm_device *dev = pci_get_drvdata(pdev);
5633 struct amdgpu_device *adev = drm_to_adev(dev);
5634 int i;
5635
5636 DRM_INFO("PCI error: detected callback, state(%d)!!\n", state);
5637
5638 if (adev->gmc.xgmi.num_physical_nodes > 1) {
5639 DRM_WARN("No support for XGMI hive yet...");
5640 return PCI_ERS_RESULT_DISCONNECT;
5641 }
5642
5643 adev->pci_channel_state = state;
5644
5645 switch (state) {
5646 case pci_channel_io_normal:
5647 return PCI_ERS_RESULT_CAN_RECOVER;
5648 /* Fatal error, prepare for slot reset */
5649 case pci_channel_io_frozen:
5650 /*
5651 * Locking adev->reset_domain->sem will prevent any external access
5652 * to GPU during PCI error recovery
5653 */
5654 amdgpu_device_lock_reset_domain(adev->reset_domain);
5655 amdgpu_device_set_mp1_state(adev);
5656
5657 /*
5658 * Block any work scheduling as we do for regular GPU reset
5659 * for the duration of the recovery
5660 */
5661 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5662 struct amdgpu_ring *ring = adev->rings[i];
5663
5664 if (!ring || !ring->sched.thread)
5665 continue;
5666
5667 drm_sched_stop(&ring->sched, NULL);
5668 }
5669 atomic_inc(&adev->gpu_reset_counter);
5670 return PCI_ERS_RESULT_NEED_RESET;
5671 case pci_channel_io_perm_failure:
5672 /* Permanent error, prepare for device removal */
5673 return PCI_ERS_RESULT_DISCONNECT;
5674 }
5675
5676 return PCI_ERS_RESULT_NEED_RESET;
5677}
5678
5679/**
5680 * amdgpu_pci_mmio_enabled - Enable MMIO and dump debug registers
5681 * @pdev: pointer to PCI device
5682 */
5683pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev)
5684{
5685
5686 DRM_INFO("PCI error: mmio enabled callback!!\n");
5687
5688 /* TODO - dump whatever for debugging purposes */
5689
5690 /* This called only if amdgpu_pci_error_detected returns
5691 * PCI_ERS_RESULT_CAN_RECOVER. Read/write to the device still
5692 * works, no need to reset slot.
5693 */
5694
5695 return PCI_ERS_RESULT_RECOVERED;
5696}
5697
5698/**
5699 * amdgpu_pci_slot_reset - Called when PCI slot has been reset.
5700 * @pdev: PCI device struct
5701 *
5702 * Description: This routine is called by the pci error recovery
5703 * code after the PCI slot has been reset, just before we
5704 * should resume normal operations.
5705 */
5706pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev)
5707{
5708 struct drm_device *dev = pci_get_drvdata(pdev);
5709 struct amdgpu_device *adev = drm_to_adev(dev);
5710 int r, i;
5711 struct amdgpu_reset_context reset_context;
5712 u32 memsize;
5713 struct list_head device_list;
5714
5715 DRM_INFO("PCI error: slot reset callback!!\n");
5716
5717 memset(&reset_context, 0, sizeof(reset_context));
5718
5719 INIT_LIST_HEAD(&device_list);
5720 list_add_tail(&adev->reset_list, &device_list);
5721
5722 /* wait for asic to come out of reset */
5723 msleep(500);
5724
5725 /* Restore PCI confspace */
5726 amdgpu_device_load_pci_state(pdev);
5727
5728 /* confirm ASIC came out of reset */
5729 for (i = 0; i < adev->usec_timeout; i++) {
5730 memsize = amdgpu_asic_get_config_memsize(adev);
5731
5732 if (memsize != 0xffffffff)
5733 break;
5734 udelay(1);
5735 }
5736 if (memsize == 0xffffffff) {
5737 r = -ETIME;
5738 goto out;
5739 }
5740
5741 reset_context.method = AMD_RESET_METHOD_NONE;
5742 reset_context.reset_req_dev = adev;
5743 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
5744 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
5745
5746 adev->no_hw_access = true;
5747 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
5748 adev->no_hw_access = false;
5749 if (r)
5750 goto out;
5751
5752 r = amdgpu_do_asic_reset(&device_list, &reset_context);
5753
5754out:
5755 if (!r) {
5756 if (amdgpu_device_cache_pci_state(adev->pdev))
5757 pci_restore_state(adev->pdev);
5758
5759 DRM_INFO("PCIe error recovery succeeded\n");
5760 } else {
5761 DRM_ERROR("PCIe error recovery failed, err:%d", r);
5762 amdgpu_device_unset_mp1_state(adev);
5763 amdgpu_device_unlock_reset_domain(adev->reset_domain);
5764 }
5765
5766 return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
5767}
5768
5769/**
5770 * amdgpu_pci_resume() - resume normal ops after PCI reset
5771 * @pdev: pointer to PCI device
5772 *
5773 * Called when the error recovery driver tells us that its
5774 * OK to resume normal operation.
5775 */
5776void amdgpu_pci_resume(struct pci_dev *pdev)
5777{
5778 struct drm_device *dev = pci_get_drvdata(pdev);
5779 struct amdgpu_device *adev = drm_to_adev(dev);
5780 int i;
5781
5782
5783 DRM_INFO("PCI error: resume callback!!\n");
5784
5785 /* Only continue execution for the case of pci_channel_io_frozen */
5786 if (adev->pci_channel_state != pci_channel_io_frozen)
5787 return;
5788
5789 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5790 struct amdgpu_ring *ring = adev->rings[i];
5791
5792 if (!ring || !ring->sched.thread)
5793 continue;
5794
5795 drm_sched_start(&ring->sched, true);
5796 }
5797
5798 amdgpu_device_unset_mp1_state(adev);
5799 amdgpu_device_unlock_reset_domain(adev->reset_domain);
5800}
5801
5802bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)
5803{
5804 struct drm_device *dev = pci_get_drvdata(pdev);
5805 struct amdgpu_device *adev = drm_to_adev(dev);
5806 int r;
5807
5808 r = pci_save_state(pdev);
5809 if (!r) {
5810 kfree(adev->pci_state);
5811
5812 adev->pci_state = pci_store_saved_state(pdev);
5813
5814 if (!adev->pci_state) {
5815 DRM_ERROR("Failed to store PCI saved state");
5816 return false;
5817 }
5818 } else {
5819 DRM_WARN("Failed to save PCI state, err:%d\n", r);
5820 return false;
5821 }
5822
5823 return true;
5824}
5825
5826bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
5827{
5828 struct drm_device *dev = pci_get_drvdata(pdev);
5829 struct amdgpu_device *adev = drm_to_adev(dev);
5830 int r;
5831
5832 if (!adev->pci_state)
5833 return false;
5834
5835 r = pci_load_saved_state(pdev, adev->pci_state);
5836
5837 if (!r) {
5838 pci_restore_state(pdev);
5839 } else {
5840 DRM_WARN("Failed to load PCI state, err:%d\n", r);
5841 return false;
5842 }
5843
5844 return true;
5845}
5846
5847void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
5848 struct amdgpu_ring *ring)
5849{
5850#ifdef CONFIG_X86_64
5851 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
5852 return;
5853#endif
5854 if (adev->gmc.xgmi.connected_to_cpu)
5855 return;
5856
5857 if (ring && ring->funcs->emit_hdp_flush)
5858 amdgpu_ring_emit_hdp_flush(ring);
5859 else
5860 amdgpu_asic_flush_hdp(adev, ring);
5861}
5862
5863void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
5864 struct amdgpu_ring *ring)
5865{
5866#ifdef CONFIG_X86_64
5867 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev))
5868 return;
5869#endif
5870 if (adev->gmc.xgmi.connected_to_cpu)
5871 return;
5872
5873 amdgpu_asic_invalidate_hdp(adev, ring);
5874}
5875
5876int amdgpu_in_reset(struct amdgpu_device *adev)
5877{
5878 return atomic_read(&adev->reset_domain->in_gpu_reset);
5879 }
5880
5881/**
5882 * amdgpu_device_halt() - bring hardware to some kind of halt state
5883 *
5884 * @adev: amdgpu_device pointer
5885 *
5886 * Bring hardware to some kind of halt state so that no one can touch it
5887 * any more. It will help to maintain error context when error occurred.
5888 * Compare to a simple hang, the system will keep stable at least for SSH
5889 * access. Then it should be trivial to inspect the hardware state and
5890 * see what's going on. Implemented as following:
5891 *
5892 * 1. drm_dev_unplug() makes device inaccessible to user space(IOCTLs, etc),
5893 * clears all CPU mappings to device, disallows remappings through page faults
5894 * 2. amdgpu_irq_disable_all() disables all interrupts
5895 * 3. amdgpu_fence_driver_hw_fini() signals all HW fences
5896 * 4. set adev->no_hw_access to avoid potential crashes after setp 5
5897 * 5. amdgpu_device_unmap_mmio() clears all MMIO mappings
5898 * 6. pci_disable_device() and pci_wait_for_pending_transaction()
5899 * flush any in flight DMA operations
5900 */
5901void amdgpu_device_halt(struct amdgpu_device *adev)
5902{
5903 struct pci_dev *pdev = adev->pdev;
5904 struct drm_device *ddev = adev_to_drm(adev);
5905
5906 drm_dev_unplug(ddev);
5907
5908 amdgpu_irq_disable_all(adev);
5909
5910 amdgpu_fence_driver_hw_fini(adev);
5911
5912 adev->no_hw_access = true;
5913
5914 amdgpu_device_unmap_mmio(adev);
5915
5916 pci_disable_device(pdev);
5917 pci_wait_for_pending_transaction(pdev);
5918}
5919
5920u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
5921 u32 reg)
5922{
5923 unsigned long flags, address, data;
5924 u32 r;
5925
5926 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
5927 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
5928
5929 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
5930 WREG32(address, reg * 4);
5931 (void)RREG32(address);
5932 r = RREG32(data);
5933 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
5934 return r;
5935}
5936
5937void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
5938 u32 reg, u32 v)
5939{
5940 unsigned long flags, address, data;
5941
5942 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
5943 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
5944
5945 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
5946 WREG32(address, reg * 4);
5947 (void)RREG32(address);
5948 WREG32(data, v);
5949 (void)RREG32(data);
5950 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
5951}
5952
5953/**
5954 * amdgpu_device_switch_gang - switch to a new gang
5955 * @adev: amdgpu_device pointer
5956 * @gang: the gang to switch to
5957 *
5958 * Try to switch to a new gang.
5959 * Returns: NULL if we switched to the new gang or a reference to the current
5960 * gang leader.
5961 */
5962struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
5963 struct dma_fence *gang)
5964{
5965 struct dma_fence *old = NULL;
5966
5967 do {
5968 dma_fence_put(old);
5969 rcu_read_lock();
5970 old = dma_fence_get_rcu_safe(&adev->gang_submit);
5971 rcu_read_unlock();
5972
5973 if (old == gang)
5974 break;
5975
5976 if (!dma_fence_is_signaled(old))
5977 return old;
5978
5979 } while (cmpxchg((struct dma_fence __force **)&adev->gang_submit,
5980 old, gang) != old);
5981
5982 dma_fence_put(old);
5983 return NULL;
5984}
5985
5986bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev)
5987{
5988 switch (adev->asic_type) {
5989#ifdef CONFIG_DRM_AMDGPU_SI
5990 case CHIP_HAINAN:
5991#endif
5992 case CHIP_TOPAZ:
5993 /* chips with no display hardware */
5994 return false;
5995#ifdef CONFIG_DRM_AMDGPU_SI
5996 case CHIP_TAHITI:
5997 case CHIP_PITCAIRN:
5998 case CHIP_VERDE:
5999 case CHIP_OLAND:
6000#endif
6001#ifdef CONFIG_DRM_AMDGPU_CIK
6002 case CHIP_BONAIRE:
6003 case CHIP_HAWAII:
6004 case CHIP_KAVERI:
6005 case CHIP_KABINI:
6006 case CHIP_MULLINS:
6007#endif
6008 case CHIP_TONGA:
6009 case CHIP_FIJI:
6010 case CHIP_POLARIS10:
6011 case CHIP_POLARIS11:
6012 case CHIP_POLARIS12:
6013 case CHIP_VEGAM:
6014 case CHIP_CARRIZO:
6015 case CHIP_STONEY:
6016 /* chips with display hardware */
6017 return true;
6018 default:
6019 /* IP discovery */
6020 if (!adev->ip_versions[DCE_HWIP][0] ||
6021 (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
6022 return false;
6023 return true;
6024 }
6025}