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1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "aldebaran.h"
25#include "amdgpu_reset.h"
26#include "amdgpu_amdkfd.h"
27#include "amdgpu_dpm.h"
28#include "amdgpu_job.h"
29#include "amdgpu_ring.h"
30#include "amdgpu_ras.h"
31#include "amdgpu_psp.h"
32#include "amdgpu_xgmi.h"
33
34static bool aldebaran_is_mode2_default(struct amdgpu_reset_control *reset_ctl)
35{
36 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
37
38 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2) &&
39 adev->gmc.xgmi.connected_to_cpu))
40 return true;
41
42 return false;
43}
44
45static struct amdgpu_reset_handler *
46aldebaran_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
47 struct amdgpu_reset_context *reset_context)
48{
49 struct amdgpu_reset_handler *handler;
50 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
51 int i;
52
53 if (reset_context->method == AMD_RESET_METHOD_NONE) {
54 if (aldebaran_is_mode2_default(reset_ctl))
55 reset_context->method = AMD_RESET_METHOD_MODE2;
56 else
57 reset_context->method = amdgpu_asic_reset_method(adev);
58 }
59
60 if (reset_context->method != AMD_RESET_METHOD_NONE) {
61 dev_dbg(adev->dev, "Getting reset handler for method %d\n",
62 reset_context->method);
63 for_each_handler(i, handler, reset_ctl) {
64 if (handler->reset_method == reset_context->method)
65 return handler;
66 }
67 }
68
69 dev_dbg(adev->dev, "Reset handler not found!\n");
70
71 return NULL;
72}
73
74static int aldebaran_mode2_suspend_ip(struct amdgpu_device *adev)
75{
76 int r, i;
77
78 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
79 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
80
81 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
82 if (!(adev->ip_blocks[i].version->type ==
83 AMD_IP_BLOCK_TYPE_GFX ||
84 adev->ip_blocks[i].version->type ==
85 AMD_IP_BLOCK_TYPE_SDMA))
86 continue;
87
88 r = adev->ip_blocks[i].version->funcs->suspend(adev);
89
90 if (r) {
91 dev_err(adev->dev,
92 "suspend of IP block <%s> failed %d\n",
93 adev->ip_blocks[i].version->funcs->name, r);
94 return r;
95 }
96
97 adev->ip_blocks[i].status.hw = false;
98 }
99
100 return r;
101}
102
103static int
104aldebaran_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,
105 struct amdgpu_reset_context *reset_context)
106{
107 int r = 0;
108 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
109
110 dev_dbg(adev->dev, "Aldebaran prepare hw context\n");
111 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
112 if (!amdgpu_sriov_vf(adev))
113 r = aldebaran_mode2_suspend_ip(adev);
114
115 return r;
116}
117
118static void aldebaran_async_reset(struct work_struct *work)
119{
120 struct amdgpu_reset_handler *handler;
121 struct amdgpu_reset_control *reset_ctl =
122 container_of(work, struct amdgpu_reset_control, reset_work);
123 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
124 int i;
125
126 for_each_handler(i, handler, reset_ctl) {
127 if (handler->reset_method == reset_ctl->active_reset) {
128 dev_dbg(adev->dev, "Resetting device\n");
129 handler->do_reset(adev);
130 break;
131 }
132 }
133}
134
135static int aldebaran_mode2_reset(struct amdgpu_device *adev)
136{
137 /* disable BM */
138 pci_clear_master(adev->pdev);
139 adev->asic_reset_res = amdgpu_dpm_mode2_reset(adev);
140 return adev->asic_reset_res;
141}
142
143static int
144aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,
145 struct amdgpu_reset_context *reset_context)
146{
147 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
148 struct list_head *reset_device_list = reset_context->reset_device_list;
149 struct amdgpu_device *tmp_adev = NULL;
150 int r = 0;
151
152 dev_dbg(adev->dev, "aldebaran perform hw reset\n");
153
154 if (reset_device_list == NULL)
155 return -EINVAL;
156
157 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2) &&
158 reset_context->hive == NULL) {
159 /* Wrong context, return error */
160 return -EINVAL;
161 }
162
163 list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
164 mutex_lock(&tmp_adev->reset_cntl->reset_lock);
165 tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_MODE2;
166 }
167 /*
168 * Mode2 reset doesn't need any sync between nodes in XGMI hive, instead launch
169 * them together so that they can be completed asynchronously on multiple nodes
170 */
171 list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
172 /* For XGMI run all resets in parallel to speed up the process */
173 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
174 if (!queue_work(system_unbound_wq,
175 &tmp_adev->reset_cntl->reset_work))
176 r = -EALREADY;
177 } else
178 r = aldebaran_mode2_reset(tmp_adev);
179 if (r) {
180 dev_err(tmp_adev->dev,
181 "ASIC reset failed with error, %d for drm dev, %s",
182 r, adev_to_drm(tmp_adev)->unique);
183 break;
184 }
185 }
186
187 /* For XGMI wait for all resets to complete before proceed */
188 if (!r) {
189 list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
190 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
191 flush_work(&tmp_adev->reset_cntl->reset_work);
192 r = tmp_adev->asic_reset_res;
193 if (r)
194 break;
195 }
196 }
197 }
198
199 list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
200 mutex_unlock(&tmp_adev->reset_cntl->reset_lock);
201 tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_NONE;
202 }
203
204 return r;
205}
206
207static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev)
208{
209 struct amdgpu_firmware_info *ucode_list[AMDGPU_UCODE_ID_MAXIMUM];
210 struct amdgpu_firmware_info *ucode;
211 struct amdgpu_ip_block *cmn_block;
212 int ucode_count = 0;
213 int i, r;
214
215 dev_dbg(adev->dev, "Reloading ucodes after reset\n");
216 for (i = 0; i < adev->firmware.max_ucodes; i++) {
217 ucode = &adev->firmware.ucode[i];
218 if (!ucode->fw)
219 continue;
220 switch (ucode->ucode_id) {
221 case AMDGPU_UCODE_ID_SDMA0:
222 case AMDGPU_UCODE_ID_SDMA1:
223 case AMDGPU_UCODE_ID_SDMA2:
224 case AMDGPU_UCODE_ID_SDMA3:
225 case AMDGPU_UCODE_ID_SDMA4:
226 case AMDGPU_UCODE_ID_SDMA5:
227 case AMDGPU_UCODE_ID_SDMA6:
228 case AMDGPU_UCODE_ID_SDMA7:
229 case AMDGPU_UCODE_ID_CP_MEC1:
230 case AMDGPU_UCODE_ID_CP_MEC1_JT:
231 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
232 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
233 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
234 case AMDGPU_UCODE_ID_RLC_G:
235 ucode_list[ucode_count++] = ucode;
236 break;
237 default:
238 break;
239 }
240 }
241
242 /* Reinit NBIF block */
243 cmn_block =
244 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_COMMON);
245 if (unlikely(!cmn_block)) {
246 dev_err(adev->dev, "Failed to get BIF handle\n");
247 return -EINVAL;
248 }
249 r = cmn_block->version->funcs->resume(adev);
250 if (r)
251 return r;
252
253 /* Reinit GFXHUB */
254 adev->gfxhub.funcs->init(adev);
255 r = adev->gfxhub.funcs->gart_enable(adev);
256 if (r) {
257 dev_err(adev->dev, "GFXHUB gart reenable failed after reset\n");
258 return r;
259 }
260
261 /* Reload GFX firmware */
262 r = psp_load_fw_list(&adev->psp, ucode_list, ucode_count);
263 if (r) {
264 dev_err(adev->dev, "GFX ucode load failed after reset\n");
265 return r;
266 }
267
268 /* Resume RLC, FW needs RLC alive to complete reset process */
269 adev->gfx.rlc.funcs->resume(adev);
270
271 /* Wait for FW reset event complete */
272 r = amdgpu_dpm_wait_for_event(adev, SMU_EVENT_RESET_COMPLETE, 0);
273 if (r) {
274 dev_err(adev->dev,
275 "Failed to get response from firmware after reset\n");
276 return r;
277 }
278
279 for (i = 0; i < adev->num_ip_blocks; i++) {
280 if (!(adev->ip_blocks[i].version->type ==
281 AMD_IP_BLOCK_TYPE_GFX ||
282 adev->ip_blocks[i].version->type ==
283 AMD_IP_BLOCK_TYPE_SDMA))
284 continue;
285 r = adev->ip_blocks[i].version->funcs->resume(adev);
286 if (r) {
287 dev_err(adev->dev,
288 "resume of IP block <%s> failed %d\n",
289 adev->ip_blocks[i].version->funcs->name, r);
290 return r;
291 }
292
293 adev->ip_blocks[i].status.hw = true;
294 }
295
296 for (i = 0; i < adev->num_ip_blocks; i++) {
297 if (!(adev->ip_blocks[i].version->type ==
298 AMD_IP_BLOCK_TYPE_GFX ||
299 adev->ip_blocks[i].version->type ==
300 AMD_IP_BLOCK_TYPE_SDMA ||
301 adev->ip_blocks[i].version->type ==
302 AMD_IP_BLOCK_TYPE_COMMON))
303 continue;
304
305 if (adev->ip_blocks[i].version->funcs->late_init) {
306 r = adev->ip_blocks[i].version->funcs->late_init(
307 (void *)adev);
308 if (r) {
309 dev_err(adev->dev,
310 "late_init of IP block <%s> failed %d after reset\n",
311 adev->ip_blocks[i].version->funcs->name,
312 r);
313 return r;
314 }
315 }
316 adev->ip_blocks[i].status.late_initialized = true;
317 }
318
319 amdgpu_ras_set_error_query_ready(adev, true);
320
321 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
322 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
323
324 return r;
325}
326
327static int
328aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,
329 struct amdgpu_reset_context *reset_context)
330{
331 struct list_head *reset_device_list = reset_context->reset_device_list;
332 struct amdgpu_device *tmp_adev = NULL;
333 struct amdgpu_ras *con;
334 int r;
335
336 if (reset_device_list == NULL)
337 return -EINVAL;
338
339 if (amdgpu_ip_version(reset_context->reset_req_dev, MP1_HWIP, 0) ==
340 IP_VERSION(13, 0, 2) &&
341 reset_context->hive == NULL) {
342 /* Wrong context, return error */
343 return -EINVAL;
344 }
345
346 list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
347 dev_info(tmp_adev->dev,
348 "GPU reset succeeded, trying to resume\n");
349 r = aldebaran_mode2_restore_ip(tmp_adev);
350 if (r)
351 goto end;
352
353 /*
354 * Add this ASIC as tracked as reset was already
355 * complete successfully.
356 */
357 amdgpu_register_gpu_instance(tmp_adev);
358
359 /* Resume RAS, ecc_irq */
360 con = amdgpu_ras_get_context(tmp_adev);
361 if (!amdgpu_sriov_vf(tmp_adev) && con) {
362 if (tmp_adev->sdma.ras &&
363 tmp_adev->sdma.ras->ras_block.ras_late_init) {
364 r = tmp_adev->sdma.ras->ras_block.ras_late_init(tmp_adev,
365 &tmp_adev->sdma.ras->ras_block.ras_comm);
366 if (r) {
367 dev_err(tmp_adev->dev, "SDMA failed to execute ras_late_init! ret:%d\n", r);
368 goto end;
369 }
370 }
371
372 if (tmp_adev->gfx.ras &&
373 tmp_adev->gfx.ras->ras_block.ras_late_init) {
374 r = tmp_adev->gfx.ras->ras_block.ras_late_init(tmp_adev,
375 &tmp_adev->gfx.ras->ras_block.ras_comm);
376 if (r) {
377 dev_err(tmp_adev->dev, "GFX failed to execute ras_late_init! ret:%d\n", r);
378 goto end;
379 }
380 }
381 }
382
383 amdgpu_ras_resume(tmp_adev);
384
385 /* Update PSP FW topology after reset */
386 if (reset_context->hive &&
387 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
388 r = amdgpu_xgmi_update_topology(reset_context->hive,
389 tmp_adev);
390
391 if (!r) {
392 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
393
394 r = amdgpu_ib_ring_tests(tmp_adev);
395 if (r) {
396 dev_err(tmp_adev->dev,
397 "ib ring test failed (%d).\n", r);
398 r = -EAGAIN;
399 tmp_adev->asic_reset_res = r;
400 goto end;
401 }
402 }
403 }
404
405end:
406 return r;
407}
408
409static struct amdgpu_reset_handler aldebaran_mode2_handler = {
410 .reset_method = AMD_RESET_METHOD_MODE2,
411 .prepare_env = NULL,
412 .prepare_hwcontext = aldebaran_mode2_prepare_hwcontext,
413 .perform_reset = aldebaran_mode2_perform_reset,
414 .restore_hwcontext = aldebaran_mode2_restore_hwcontext,
415 .restore_env = NULL,
416 .do_reset = aldebaran_mode2_reset,
417};
418
419static struct amdgpu_reset_handler
420 *aldebaran_rst_handlers[AMDGPU_RESET_MAX_HANDLERS] = {
421 &aldebaran_mode2_handler,
422 };
423
424int aldebaran_reset_init(struct amdgpu_device *adev)
425{
426 struct amdgpu_reset_control *reset_ctl;
427
428 reset_ctl = kzalloc(sizeof(*reset_ctl), GFP_KERNEL);
429 if (!reset_ctl)
430 return -ENOMEM;
431
432 reset_ctl->handle = adev;
433 reset_ctl->async_reset = aldebaran_async_reset;
434 reset_ctl->active_reset = AMD_RESET_METHOD_NONE;
435 reset_ctl->get_reset_handler = aldebaran_get_reset_handler;
436
437 INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset);
438 /* Only mode2 is handled through reset control now */
439 reset_ctl->reset_handlers = &aldebaran_rst_handlers;
440
441 adev->reset_cntl = reset_ctl;
442
443 return 0;
444}
445
446int aldebaran_reset_fini(struct amdgpu_device *adev)
447{
448 kfree(adev->reset_cntl);
449 adev->reset_cntl = NULL;
450 return 0;
451}
1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "aldebaran.h"
25#include "amdgpu_reset.h"
26#include "amdgpu_amdkfd.h"
27#include "amdgpu_dpm.h"
28#include "amdgpu_job.h"
29#include "amdgpu_ring.h"
30#include "amdgpu_ras.h"
31#include "amdgpu_psp.h"
32#include "amdgpu_xgmi.h"
33
34static bool aldebaran_is_mode2_default(struct amdgpu_reset_control *reset_ctl)
35{
36 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
37
38 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) &&
39 adev->gmc.xgmi.connected_to_cpu))
40 return true;
41
42 return false;
43}
44
45static struct amdgpu_reset_handler *
46aldebaran_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
47 struct amdgpu_reset_context *reset_context)
48{
49 struct amdgpu_reset_handler *handler;
50 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
51
52 if (reset_context->method != AMD_RESET_METHOD_NONE) {
53 dev_dbg(adev->dev, "Getting reset handler for method %d\n",
54 reset_context->method);
55 list_for_each_entry(handler, &reset_ctl->reset_handlers,
56 handler_list) {
57 if (handler->reset_method == reset_context->method)
58 return handler;
59 }
60 }
61
62 if (aldebaran_is_mode2_default(reset_ctl)) {
63 list_for_each_entry(handler, &reset_ctl->reset_handlers,
64 handler_list) {
65 if (handler->reset_method == AMD_RESET_METHOD_MODE2) {
66 reset_context->method = AMD_RESET_METHOD_MODE2;
67 return handler;
68 }
69 }
70 }
71
72 dev_dbg(adev->dev, "Reset handler not found!\n");
73
74 return NULL;
75}
76
77static int aldebaran_mode2_suspend_ip(struct amdgpu_device *adev)
78{
79 int r, i;
80
81 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
82 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
83
84 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
85 if (!(adev->ip_blocks[i].version->type ==
86 AMD_IP_BLOCK_TYPE_GFX ||
87 adev->ip_blocks[i].version->type ==
88 AMD_IP_BLOCK_TYPE_SDMA))
89 continue;
90
91 r = adev->ip_blocks[i].version->funcs->suspend(adev);
92
93 if (r) {
94 dev_err(adev->dev,
95 "suspend of IP block <%s> failed %d\n",
96 adev->ip_blocks[i].version->funcs->name, r);
97 return r;
98 }
99
100 adev->ip_blocks[i].status.hw = false;
101 }
102
103 return r;
104}
105
106static int
107aldebaran_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,
108 struct amdgpu_reset_context *reset_context)
109{
110 int r = 0;
111 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
112
113 dev_dbg(adev->dev, "Aldebaran prepare hw context\n");
114 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */
115 if (!amdgpu_sriov_vf(adev))
116 r = aldebaran_mode2_suspend_ip(adev);
117
118 return r;
119}
120
121static void aldebaran_async_reset(struct work_struct *work)
122{
123 struct amdgpu_reset_handler *handler;
124 struct amdgpu_reset_control *reset_ctl =
125 container_of(work, struct amdgpu_reset_control, reset_work);
126 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
127
128 list_for_each_entry(handler, &reset_ctl->reset_handlers,
129 handler_list) {
130 if (handler->reset_method == reset_ctl->active_reset) {
131 dev_dbg(adev->dev, "Resetting device\n");
132 handler->do_reset(adev);
133 break;
134 }
135 }
136}
137
138static int aldebaran_mode2_reset(struct amdgpu_device *adev)
139{
140 /* disable BM */
141 pci_clear_master(adev->pdev);
142 adev->asic_reset_res = amdgpu_dpm_mode2_reset(adev);
143 return adev->asic_reset_res;
144}
145
146static int
147aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,
148 struct amdgpu_reset_context *reset_context)
149{
150 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
151 struct list_head *reset_device_list = reset_context->reset_device_list;
152 struct amdgpu_device *tmp_adev = NULL;
153 int r = 0;
154
155 dev_dbg(adev->dev, "aldebaran perform hw reset\n");
156
157 if (reset_device_list == NULL)
158 return -EINVAL;
159
160 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) &&
161 reset_context->hive == NULL) {
162 /* Wrong context, return error */
163 return -EINVAL;
164 }
165
166 list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
167 mutex_lock(&tmp_adev->reset_cntl->reset_lock);
168 tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_MODE2;
169 }
170 /*
171 * Mode2 reset doesn't need any sync between nodes in XGMI hive, instead launch
172 * them together so that they can be completed asynchronously on multiple nodes
173 */
174 list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
175 /* For XGMI run all resets in parallel to speed up the process */
176 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
177 if (!queue_work(system_unbound_wq,
178 &tmp_adev->reset_cntl->reset_work))
179 r = -EALREADY;
180 } else
181 r = aldebaran_mode2_reset(tmp_adev);
182 if (r) {
183 dev_err(tmp_adev->dev,
184 "ASIC reset failed with error, %d for drm dev, %s",
185 r, adev_to_drm(tmp_adev)->unique);
186 break;
187 }
188 }
189
190 /* For XGMI wait for all resets to complete before proceed */
191 if (!r) {
192 list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
193 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
194 flush_work(&tmp_adev->reset_cntl->reset_work);
195 r = tmp_adev->asic_reset_res;
196 if (r)
197 break;
198 }
199 }
200 }
201
202 list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
203 mutex_unlock(&tmp_adev->reset_cntl->reset_lock);
204 tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_NONE;
205 }
206
207 return r;
208}
209
210static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev)
211{
212 struct amdgpu_firmware_info *ucode_list[AMDGPU_UCODE_ID_MAXIMUM];
213 struct amdgpu_firmware_info *ucode;
214 struct amdgpu_ip_block *cmn_block;
215 int ucode_count = 0;
216 int i, r;
217
218 dev_dbg(adev->dev, "Reloading ucodes after reset\n");
219 for (i = 0; i < adev->firmware.max_ucodes; i++) {
220 ucode = &adev->firmware.ucode[i];
221 if (!ucode->fw)
222 continue;
223 switch (ucode->ucode_id) {
224 case AMDGPU_UCODE_ID_SDMA0:
225 case AMDGPU_UCODE_ID_SDMA1:
226 case AMDGPU_UCODE_ID_SDMA2:
227 case AMDGPU_UCODE_ID_SDMA3:
228 case AMDGPU_UCODE_ID_SDMA4:
229 case AMDGPU_UCODE_ID_SDMA5:
230 case AMDGPU_UCODE_ID_SDMA6:
231 case AMDGPU_UCODE_ID_SDMA7:
232 case AMDGPU_UCODE_ID_CP_MEC1:
233 case AMDGPU_UCODE_ID_CP_MEC1_JT:
234 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
235 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
236 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
237 case AMDGPU_UCODE_ID_RLC_G:
238 ucode_list[ucode_count++] = ucode;
239 break;
240 default:
241 break;
242 }
243 }
244
245 /* Reinit NBIF block */
246 cmn_block =
247 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_COMMON);
248 if (unlikely(!cmn_block)) {
249 dev_err(adev->dev, "Failed to get BIF handle\n");
250 return -EINVAL;
251 }
252 r = cmn_block->version->funcs->resume(adev);
253 if (r)
254 return r;
255
256 /* Reinit GFXHUB */
257 adev->gfxhub.funcs->init(adev);
258 r = adev->gfxhub.funcs->gart_enable(adev);
259 if (r) {
260 dev_err(adev->dev, "GFXHUB gart reenable failed after reset\n");
261 return r;
262 }
263
264 /* Reload GFX firmware */
265 r = psp_load_fw_list(&adev->psp, ucode_list, ucode_count);
266 if (r) {
267 dev_err(adev->dev, "GFX ucode load failed after reset\n");
268 return r;
269 }
270
271 /* Resume RLC, FW needs RLC alive to complete reset process */
272 adev->gfx.rlc.funcs->resume(adev);
273
274 /* Wait for FW reset event complete */
275 r = amdgpu_dpm_wait_for_event(adev, SMU_EVENT_RESET_COMPLETE, 0);
276 if (r) {
277 dev_err(adev->dev,
278 "Failed to get response from firmware after reset\n");
279 return r;
280 }
281
282 for (i = 0; i < adev->num_ip_blocks; i++) {
283 if (!(adev->ip_blocks[i].version->type ==
284 AMD_IP_BLOCK_TYPE_GFX ||
285 adev->ip_blocks[i].version->type ==
286 AMD_IP_BLOCK_TYPE_SDMA))
287 continue;
288 r = adev->ip_blocks[i].version->funcs->resume(adev);
289 if (r) {
290 dev_err(adev->dev,
291 "resume of IP block <%s> failed %d\n",
292 adev->ip_blocks[i].version->funcs->name, r);
293 return r;
294 }
295
296 adev->ip_blocks[i].status.hw = true;
297 }
298
299 for (i = 0; i < adev->num_ip_blocks; i++) {
300 if (!(adev->ip_blocks[i].version->type ==
301 AMD_IP_BLOCK_TYPE_GFX ||
302 adev->ip_blocks[i].version->type ==
303 AMD_IP_BLOCK_TYPE_SDMA ||
304 adev->ip_blocks[i].version->type ==
305 AMD_IP_BLOCK_TYPE_COMMON))
306 continue;
307
308 if (adev->ip_blocks[i].version->funcs->late_init) {
309 r = adev->ip_blocks[i].version->funcs->late_init(
310 (void *)adev);
311 if (r) {
312 dev_err(adev->dev,
313 "late_init of IP block <%s> failed %d after reset\n",
314 adev->ip_blocks[i].version->funcs->name,
315 r);
316 return r;
317 }
318 }
319 adev->ip_blocks[i].status.late_initialized = true;
320 }
321
322 amdgpu_ras_set_error_query_ready(adev, true);
323
324 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
325 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
326
327 return r;
328}
329
330static int
331aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,
332 struct amdgpu_reset_context *reset_context)
333{
334 struct list_head *reset_device_list = reset_context->reset_device_list;
335 struct amdgpu_device *tmp_adev = NULL;
336 int r;
337
338 if (reset_device_list == NULL)
339 return -EINVAL;
340
341 if (reset_context->reset_req_dev->ip_versions[MP1_HWIP][0] ==
342 IP_VERSION(13, 0, 2) &&
343 reset_context->hive == NULL) {
344 /* Wrong context, return error */
345 return -EINVAL;
346 }
347
348 list_for_each_entry(tmp_adev, reset_device_list, reset_list) {
349 dev_info(tmp_adev->dev,
350 "GPU reset succeeded, trying to resume\n");
351 r = aldebaran_mode2_restore_ip(tmp_adev);
352 if (r)
353 goto end;
354
355 /*
356 * Add this ASIC as tracked as reset was already
357 * complete successfully.
358 */
359 amdgpu_register_gpu_instance(tmp_adev);
360
361 /* Resume RAS */
362 amdgpu_ras_resume(tmp_adev);
363
364 /* Update PSP FW topology after reset */
365 if (reset_context->hive &&
366 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
367 r = amdgpu_xgmi_update_topology(reset_context->hive,
368 tmp_adev);
369
370 if (!r) {
371 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
372
373 r = amdgpu_ib_ring_tests(tmp_adev);
374 if (r) {
375 dev_err(tmp_adev->dev,
376 "ib ring test failed (%d).\n", r);
377 r = -EAGAIN;
378 tmp_adev->asic_reset_res = r;
379 goto end;
380 }
381 }
382 }
383
384end:
385 return r;
386}
387
388static struct amdgpu_reset_handler aldebaran_mode2_handler = {
389 .reset_method = AMD_RESET_METHOD_MODE2,
390 .prepare_env = NULL,
391 .prepare_hwcontext = aldebaran_mode2_prepare_hwcontext,
392 .perform_reset = aldebaran_mode2_perform_reset,
393 .restore_hwcontext = aldebaran_mode2_restore_hwcontext,
394 .restore_env = NULL,
395 .do_reset = aldebaran_mode2_reset,
396};
397
398int aldebaran_reset_init(struct amdgpu_device *adev)
399{
400 struct amdgpu_reset_control *reset_ctl;
401
402 reset_ctl = kzalloc(sizeof(*reset_ctl), GFP_KERNEL);
403 if (!reset_ctl)
404 return -ENOMEM;
405
406 reset_ctl->handle = adev;
407 reset_ctl->async_reset = aldebaran_async_reset;
408 reset_ctl->active_reset = AMD_RESET_METHOD_NONE;
409 reset_ctl->get_reset_handler = aldebaran_get_reset_handler;
410
411 INIT_LIST_HEAD(&reset_ctl->reset_handlers);
412 INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset);
413 /* Only mode2 is handled through reset control now */
414 amdgpu_reset_add_handler(reset_ctl, &aldebaran_mode2_handler);
415
416 adev->reset_cntl = reset_ctl;
417
418 return 0;
419}
420
421int aldebaran_reset_fini(struct amdgpu_device *adev)
422{
423 kfree(adev->reset_cntl);
424 adev->reset_cntl = NULL;
425 return 0;
426}