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1/*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/pci.h>
25
26#include "amdgpu.h"
27#include "amdgpu_ih.h"
28
29#include "oss/osssys_6_1_0_offset.h"
30#include "oss/osssys_6_1_0_sh_mask.h"
31
32#include "soc15_common.h"
33#include "ih_v6_1.h"
34
35#define MAX_REARM_RETRY 10
36
37static void ih_v6_1_set_interrupt_funcs(struct amdgpu_device *adev);
38
39/**
40 * ih_v6_1_init_register_offset - Initialize register offset for ih rings
41 *
42 * @adev: amdgpu_device pointer
43 *
44 * Initialize register offset ih rings (IH_V6_0).
45 */
46static void ih_v6_1_init_register_offset(struct amdgpu_device *adev)
47{
48 struct amdgpu_ih_regs *ih_regs;
49
50 /* ih ring 2 is removed
51 * ih ring and ih ring 1 are available */
52 if (adev->irq.ih.ring_size) {
53 ih_regs = &adev->irq.ih.ih_regs;
54 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE);
55 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI);
56 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL);
57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR);
58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR);
59 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR);
60 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_LO);
61 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_HI);
62 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
63 }
64
65 if (adev->irq.ih1.ring_size) {
66 ih_regs = &adev->irq.ih1.ih_regs;
67 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_RING1);
68 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI_RING1);
69 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL_RING1);
70 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_RING1);
71 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR_RING1);
72 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR_RING1);
73 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
74 }
75}
76
77/**
78 * force_update_wptr_for_self_int - Force update the wptr for self interrupt
79 *
80 * @adev: amdgpu_device pointer
81 * @threshold: threshold to trigger the wptr reporting
82 * @timeout: timeout to trigger the wptr reporting
83 * @enabled: Enable/disable timeout flush mechanism
84 *
85 * threshold input range: 0 ~ 15, default 0,
86 * real_threshold = 2^threshold
87 * timeout input range: 0 ~ 20, default 8,
88 * real_timeout = (2^timeout) * 1024 / (socclk_freq)
89 *
90 * Force update wptr for self interrupt ( >= SIENNA_CICHLID).
91 */
92static void
93force_update_wptr_for_self_int(struct amdgpu_device *adev,
94 u32 threshold, u32 timeout, bool enabled)
95{
96 u32 ih_cntl, ih_rb_cntl;
97
98 ih_cntl = RREG32_SOC15(OSSSYS, 0, regIH_CNTL2);
99 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1);
100
101 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,
102 SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout);
103 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,
104 SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled);
105 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
106 RB_USED_INT_THRESHOLD, threshold);
107
108 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
109 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl))
110 return;
111 } else {
112 WREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1, ih_rb_cntl);
113 }
114
115 WREG32_SOC15(OSSSYS, 0, regIH_CNTL2, ih_cntl);
116}
117
118/**
119 * ih_v6_1_toggle_ring_interrupts - toggle the interrupt ring buffer
120 *
121 * @adev: amdgpu_device pointer
122 * @ih: amdgpu_ih_ring pointer
123 * @enable: true - enable the interrupts, false - disable the interrupts
124 *
125 * Toggle the interrupt ring buffer (IH_V6_0)
126 */
127static int ih_v6_1_toggle_ring_interrupts(struct amdgpu_device *adev,
128 struct amdgpu_ih_ring *ih,
129 bool enable)
130{
131 struct amdgpu_ih_regs *ih_regs;
132 uint32_t tmp;
133
134 ih_regs = &ih->ih_regs;
135
136 tmp = RREG32(ih_regs->ih_rb_cntl);
137 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
138 /* enable_intr field is only valid in ring0 */
139 if (ih == &adev->irq.ih)
140 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
141
142 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
143 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
144 return -ETIMEDOUT;
145 } else {
146 WREG32(ih_regs->ih_rb_cntl, tmp);
147 }
148
149 if (enable) {
150 ih->enabled = true;
151 } else {
152 /* set rptr, wptr to 0 */
153 WREG32(ih_regs->ih_rb_rptr, 0);
154 WREG32(ih_regs->ih_rb_wptr, 0);
155 ih->enabled = false;
156 ih->rptr = 0;
157 }
158
159 return 0;
160}
161
162/**
163 * ih_v6_1_toggle_interrupts - Toggle all the available interrupt ring buffers
164 *
165 * @adev: amdgpu_device pointer
166 * @enable: enable or disable interrupt ring buffers
167 *
168 * Toggle all the available interrupt ring buffers (IH_V6_0).
169 */
170static int ih_v6_1_toggle_interrupts(struct amdgpu_device *adev, bool enable)
171{
172 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1};
173 int i;
174 int r;
175
176 for (i = 0; i < ARRAY_SIZE(ih); i++) {
177 if (ih[i]->ring_size) {
178 r = ih_v6_1_toggle_ring_interrupts(adev, ih[i], enable);
179 if (r)
180 return r;
181 }
182 }
183
184 return 0;
185}
186
187static uint32_t ih_v6_1_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
188{
189 int rb_bufsz = order_base_2(ih->ring_size / 4);
190
191 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
192 MC_SPACE, ih->use_bus_addr ? 2 : 4);
193 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
194 WPTR_OVERFLOW_CLEAR, 1);
195 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
196 WPTR_OVERFLOW_ENABLE, 1);
197 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
198 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
199 * value is written to memory
200 */
201 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
202 WPTR_WRITEBACK_ENABLE, 1);
203 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
204 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
205 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
206
207 return ih_rb_cntl;
208}
209
210static uint32_t ih_v6_1_doorbell_rptr(struct amdgpu_ih_ring *ih)
211{
212 u32 ih_doorbell_rtpr = 0;
213
214 if (ih->use_doorbell) {
215 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
216 IH_DOORBELL_RPTR, OFFSET,
217 ih->doorbell_index);
218 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
219 IH_DOORBELL_RPTR,
220 ENABLE, 1);
221 } else {
222 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
223 IH_DOORBELL_RPTR,
224 ENABLE, 0);
225 }
226 return ih_doorbell_rtpr;
227}
228
229/**
230 * ih_v6_1_enable_ring - enable an ih ring buffer
231 *
232 * @adev: amdgpu_device pointer
233 * @ih: amdgpu_ih_ring pointer
234 *
235 * Enable an ih ring buffer (IH_V6_0)
236 */
237static int ih_v6_1_enable_ring(struct amdgpu_device *adev,
238 struct amdgpu_ih_ring *ih)
239{
240 struct amdgpu_ih_regs *ih_regs;
241 uint32_t tmp;
242
243 ih_regs = &ih->ih_regs;
244
245 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
246 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
247 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
248
249 tmp = RREG32(ih_regs->ih_rb_cntl);
250 tmp = ih_v6_1_rb_cntl(ih, tmp);
251 if (ih == &adev->irq.ih)
252 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
253 if (ih == &adev->irq.ih1) {
254 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
255 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
256 }
257
258 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
259 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
260 DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
261 return -ETIMEDOUT;
262 }
263 } else {
264 WREG32(ih_regs->ih_rb_cntl, tmp);
265 }
266
267 if (ih == &adev->irq.ih) {
268 /* set the ih ring 0 writeback address whether it's enabled or not */
269 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
270 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
271 }
272
273 /* set rptr, wptr to 0 */
274 WREG32(ih_regs->ih_rb_wptr, 0);
275 WREG32(ih_regs->ih_rb_rptr, 0);
276
277 WREG32(ih_regs->ih_doorbell_rptr, ih_v6_1_doorbell_rptr(ih));
278
279 return 0;
280}
281
282/**
283 * ih_v6_1_irq_init - init and enable the interrupt ring
284 *
285 * @adev: amdgpu_device pointer
286 *
287 * Allocate a ring buffer for the interrupt controller,
288 * enable the RLC, disable interrupts, enable the IH
289 * ring buffer and enable it.
290 * Called at device load and reume.
291 * Returns 0 for success, errors for failure.
292 */
293static int ih_v6_1_irq_init(struct amdgpu_device *adev)
294{
295 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1};
296 u32 ih_chicken;
297 u32 tmp;
298 int ret;
299 int i;
300
301 /* disable irqs */
302 ret = ih_v6_1_toggle_interrupts(adev, false);
303 if (ret)
304 return ret;
305
306 adev->nbio.funcs->ih_control(adev);
307
308 if (unlikely((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) ||
309 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO))) {
310 if (ih[0]->use_bus_addr) {
311 ih_chicken = RREG32_SOC15(OSSSYS, 0, regIH_CHICKEN);
312 ih_chicken = REG_SET_FIELD(ih_chicken,
313 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
314 WREG32_SOC15(OSSSYS, 0, regIH_CHICKEN, ih_chicken);
315 }
316 }
317
318 for (i = 0; i < ARRAY_SIZE(ih); i++) {
319 if (ih[i]->ring_size) {
320 ret = ih_v6_1_enable_ring(adev, ih[i]);
321 if (ret)
322 return ret;
323 }
324 }
325
326 /* update doorbell range for ih ring 0 */
327 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell,
328 ih[0]->doorbell_index);
329
330 tmp = RREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL);
331 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
332 CLIENT18_IS_STORM_CLIENT, 1);
333 WREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL, tmp);
334
335 tmp = RREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL);
336 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);
337 WREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL, tmp);
338
339 /* GC/MMHUB UTCL2 page fault interrupts are configured as
340 * MSI storm capable interrupts by deafult. The delay is
341 * used to avoid ISR being called too frequently
342 * when page fault happens on several continuous page
343 * and thus avoid MSI storm */
344 tmp = RREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL);
345 tmp = REG_SET_FIELD(tmp, IH_MSI_STORM_CTRL,
346 DELAY, 3);
347 WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp);
348
349 pci_set_master(adev->pdev);
350
351 /* enable interrupts */
352 ret = ih_v6_1_toggle_interrupts(adev, true);
353 if (ret)
354 return ret;
355 /* enable wptr force update for self int */
356 force_update_wptr_for_self_int(adev, 0, 8, true);
357
358 if (adev->irq.ih_soft.ring_size)
359 adev->irq.ih_soft.enabled = true;
360
361 return 0;
362}
363
364/**
365 * ih_v6_1_irq_disable - disable interrupts
366 *
367 * @adev: amdgpu_device pointer
368 *
369 * Disable interrupts on the hw.
370 */
371static void ih_v6_1_irq_disable(struct amdgpu_device *adev)
372{
373 force_update_wptr_for_self_int(adev, 0, 8, false);
374 ih_v6_1_toggle_interrupts(adev, false);
375
376 /* Wait and acknowledge irq */
377 mdelay(1);
378}
379
380/**
381 * ih_v6_1_get_wptr - get the IH ring buffer wptr
382 *
383 * @adev: amdgpu_device pointer
384 * @ih: amdgpu_ih_ring pointer
385 *
386 * Get the IH ring buffer wptr from either the register
387 * or the writeback memory buffer. Also check for
388 * ring buffer overflow and deal with it.
389 * Returns the value of the wptr.
390 */
391static u32 ih_v6_1_get_wptr(struct amdgpu_device *adev,
392 struct amdgpu_ih_ring *ih)
393{
394 u32 wptr, tmp;
395 struct amdgpu_ih_regs *ih_regs;
396
397 wptr = le32_to_cpu(*ih->wptr_cpu);
398 ih_regs = &ih->ih_regs;
399
400 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
401 goto out;
402
403 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
404 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
405 goto out;
406 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
407
408 /* When a ring buffer overflow happen start parsing interrupt
409 * from the last not overwritten vector (wptr + 32). Hopefully
410 * this should allow us to catch up.
411 */
412 tmp = (wptr + 32) & ih->ptr_mask;
413 dev_warn(adev->dev, "IH ring buffer overflow "
414 "(0x%08X, 0x%08X, 0x%08X)\n",
415 wptr, ih->rptr, tmp);
416 ih->rptr = tmp;
417
418 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
419 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
420 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
421
422 /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
423 * can be detected.
424 */
425 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
426 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
427
428out:
429 return (wptr & ih->ptr_mask);
430}
431
432/**
433 * ih_v6_1_irq_rearm - rearm IRQ if lost
434 *
435 * @adev: amdgpu_device pointer
436 * @ih: amdgpu_ih_ring pointer
437 *
438 */
439static void ih_v6_1_irq_rearm(struct amdgpu_device *adev,
440 struct amdgpu_ih_ring *ih)
441{
442 uint32_t v = 0;
443 uint32_t i = 0;
444 struct amdgpu_ih_regs *ih_regs;
445
446 ih_regs = &ih->ih_regs;
447
448 /* Rearm IRQ / re-write doorbell if doorbell write is lost */
449 for (i = 0; i < MAX_REARM_RETRY; i++) {
450 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
451 if ((v < ih->ring_size) && (v != ih->rptr))
452 WDOORBELL32(ih->doorbell_index, ih->rptr);
453 else
454 break;
455 }
456}
457
458/**
459 * ih_v6_1_set_rptr - set the IH ring buffer rptr
460 *
461 * @adev: amdgpu_device pointer
462 * @ih: amdgpu_ih_ring pointer
463 *
464 * Set the IH ring buffer rptr.
465 */
466static void ih_v6_1_set_rptr(struct amdgpu_device *adev,
467 struct amdgpu_ih_ring *ih)
468{
469 struct amdgpu_ih_regs *ih_regs;
470
471 if (ih->use_doorbell) {
472 /* XXX check if swapping is necessary on BE */
473 *ih->rptr_cpu = ih->rptr;
474 WDOORBELL32(ih->doorbell_index, ih->rptr);
475
476 if (amdgpu_sriov_vf(adev))
477 ih_v6_1_irq_rearm(adev, ih);
478 } else {
479 ih_regs = &ih->ih_regs;
480 WREG32(ih_regs->ih_rb_rptr, ih->rptr);
481 }
482}
483
484/**
485 * ih_v6_1_self_irq - dispatch work for ring 1
486 *
487 * @adev: amdgpu_device pointer
488 * @source: irq source
489 * @entry: IV with WPTR update
490 *
491 * Update the WPTR from the IV and schedule work to handle the entries.
492 */
493static int ih_v6_1_self_irq(struct amdgpu_device *adev,
494 struct amdgpu_irq_src *source,
495 struct amdgpu_iv_entry *entry)
496{
497 uint32_t wptr = cpu_to_le32(entry->src_data[0]);
498
499 switch (entry->ring_id) {
500 case 1:
501 *adev->irq.ih1.wptr_cpu = wptr;
502 schedule_work(&adev->irq.ih1_work);
503 break;
504 default:
505 break;
506 }
507 return 0;
508}
509
510static const struct amdgpu_irq_src_funcs ih_v6_1_self_irq_funcs = {
511 .process = ih_v6_1_self_irq,
512};
513
514static void ih_v6_1_set_self_irq_funcs(struct amdgpu_device *adev)
515{
516 adev->irq.self_irq.num_types = 0;
517 adev->irq.self_irq.funcs = &ih_v6_1_self_irq_funcs;
518}
519
520static int ih_v6_1_early_init(void *handle)
521{
522 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
523
524 ih_v6_1_set_interrupt_funcs(adev);
525 ih_v6_1_set_self_irq_funcs(adev);
526 return 0;
527}
528
529static int ih_v6_1_sw_init(void *handle)
530{
531 int r;
532 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
533 bool use_bus_addr;
534
535 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_IH, 0,
536 &adev->irq.self_irq);
537
538 if (r)
539 return r;
540
541 /* use gpu virtual address for ih ring
542 * until ih_checken is programmed to allow
543 * use bus address for ih ring by psp bl */
544 use_bus_addr =
545 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true;
546 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr);
547 if (r)
548 return r;
549
550 adev->irq.ih.use_doorbell = true;
551 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
552
553 adev->irq.ih1.ring_size = 0;
554 adev->irq.ih2.ring_size = 0;
555
556 /* initialize ih control register offset */
557 ih_v6_1_init_register_offset(adev);
558
559 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true);
560 if (r)
561 return r;
562
563 r = amdgpu_irq_init(adev);
564
565 return r;
566}
567
568static int ih_v6_1_sw_fini(void *handle)
569{
570 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
571
572 amdgpu_irq_fini_sw(adev);
573
574 return 0;
575}
576
577static int ih_v6_1_hw_init(void *handle)
578{
579 int r;
580 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
581
582 r = ih_v6_1_irq_init(adev);
583 if (r)
584 return r;
585
586 return 0;
587}
588
589static int ih_v6_1_hw_fini(void *handle)
590{
591 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
592
593 ih_v6_1_irq_disable(adev);
594
595 return 0;
596}
597
598static int ih_v6_1_suspend(void *handle)
599{
600 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
601
602 return ih_v6_1_hw_fini(adev);
603}
604
605static int ih_v6_1_resume(void *handle)
606{
607 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
608
609 return ih_v6_1_hw_init(adev);
610}
611
612static bool ih_v6_1_is_idle(void *handle)
613{
614 /* todo */
615 return true;
616}
617
618static int ih_v6_1_wait_for_idle(void *handle)
619{
620 /* todo */
621 return -ETIMEDOUT;
622}
623
624static int ih_v6_1_soft_reset(void *handle)
625{
626 /* todo */
627 return 0;
628}
629
630static void ih_v6_1_update_clockgating_state(struct amdgpu_device *adev,
631 bool enable)
632{
633 uint32_t data, def, field_val;
634
635 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
636 def = data = RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL);
637 field_val = enable ? 0 : 1;
638 data = REG_SET_FIELD(data, IH_CLK_CTRL,
639 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
640 data = REG_SET_FIELD(data, IH_CLK_CTRL,
641 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
642 data = REG_SET_FIELD(data, IH_CLK_CTRL,
643 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
644 data = REG_SET_FIELD(data, IH_CLK_CTRL,
645 DYN_CLK_SOFT_OVERRIDE, field_val);
646 data = REG_SET_FIELD(data, IH_CLK_CTRL,
647 REG_CLK_SOFT_OVERRIDE, field_val);
648 if (def != data)
649 WREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL, data);
650 }
651
652 return;
653}
654
655static int ih_v6_1_set_clockgating_state(void *handle,
656 enum amd_clockgating_state state)
657{
658 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
659
660 ih_v6_1_update_clockgating_state(adev,
661 state == AMD_CG_STATE_GATE);
662 return 0;
663}
664
665static void ih_v6_1_update_ih_mem_power_gating(struct amdgpu_device *adev,
666 bool enable)
667{
668 uint32_t ih_mem_pwr_cntl;
669
670 /* Disable ih sram power cntl before switch powergating mode */
671 ih_mem_pwr_cntl = RREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL);
672 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
673 IH_BUFFER_MEM_POWER_CTRL_EN, 0);
674 WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
675
676 /* It is recommended to set mem powergating mode to DS mode */
677 if (enable) {
678 /* mem power mode */
679 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
680 IH_BUFFER_MEM_POWER_LS_EN, 0);
681 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
682 IH_BUFFER_MEM_POWER_DS_EN, 1);
683 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
684 IH_BUFFER_MEM_POWER_SD_EN, 0);
685 /* cam mem power mode */
686 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
687 IH_RETRY_INT_CAM_MEM_POWER_LS_EN, 0);
688 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
689 IH_RETRY_INT_CAM_MEM_POWER_DS_EN, 1);
690 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
691 IH_RETRY_INT_CAM_MEM_POWER_SD_EN, 0);
692 /* re-enable power cntl */
693 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
694 IH_BUFFER_MEM_POWER_CTRL_EN, 1);
695 } else {
696 /* mem power mode */
697 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
698 IH_BUFFER_MEM_POWER_LS_EN, 0);
699 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
700 IH_BUFFER_MEM_POWER_DS_EN, 0);
701 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
702 IH_BUFFER_MEM_POWER_SD_EN, 0);
703 /* cam mem power mode */
704 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
705 IH_RETRY_INT_CAM_MEM_POWER_LS_EN, 0);
706 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
707 IH_RETRY_INT_CAM_MEM_POWER_DS_EN, 0);
708 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
709 IH_RETRY_INT_CAM_MEM_POWER_SD_EN, 0);
710 /* re-enable power cntl*/
711 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
712 IH_BUFFER_MEM_POWER_CTRL_EN, 1);
713 }
714
715 WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
716}
717
718static int ih_v6_1_set_powergating_state(void *handle,
719 enum amd_powergating_state state)
720{
721 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
722 bool enable = (state == AMD_PG_STATE_GATE);
723
724 if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
725 ih_v6_1_update_ih_mem_power_gating(adev, enable);
726
727 return 0;
728}
729
730static void ih_v6_1_get_clockgating_state(void *handle, u64 *flags)
731{
732 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
733
734 if (!RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL))
735 *flags |= AMD_CG_SUPPORT_IH_CG;
736
737 return;
738}
739
740static const struct amd_ip_funcs ih_v6_1_ip_funcs = {
741 .name = "ih_v6_1",
742 .early_init = ih_v6_1_early_init,
743 .late_init = NULL,
744 .sw_init = ih_v6_1_sw_init,
745 .sw_fini = ih_v6_1_sw_fini,
746 .hw_init = ih_v6_1_hw_init,
747 .hw_fini = ih_v6_1_hw_fini,
748 .suspend = ih_v6_1_suspend,
749 .resume = ih_v6_1_resume,
750 .is_idle = ih_v6_1_is_idle,
751 .wait_for_idle = ih_v6_1_wait_for_idle,
752 .soft_reset = ih_v6_1_soft_reset,
753 .set_clockgating_state = ih_v6_1_set_clockgating_state,
754 .set_powergating_state = ih_v6_1_set_powergating_state,
755 .get_clockgating_state = ih_v6_1_get_clockgating_state,
756};
757
758static const struct amdgpu_ih_funcs ih_v6_1_funcs = {
759 .get_wptr = ih_v6_1_get_wptr,
760 .decode_iv = amdgpu_ih_decode_iv_helper,
761 .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper,
762 .set_rptr = ih_v6_1_set_rptr
763};
764
765static void ih_v6_1_set_interrupt_funcs(struct amdgpu_device *adev)
766{
767 adev->irq.ih_funcs = &ih_v6_1_funcs;
768}
769
770const struct amdgpu_ip_block_version ih_v6_1_ip_block = {
771 .type = AMD_IP_BLOCK_TYPE_IH,
772 .major = 6,
773 .minor = 0,
774 .rev = 0,
775 .funcs = &ih_v6_1_ip_funcs,
776};
1/*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/pci.h>
25
26#include "amdgpu.h"
27#include "amdgpu_ih.h"
28
29#include "oss/osssys_6_1_0_offset.h"
30#include "oss/osssys_6_1_0_sh_mask.h"
31
32#include "soc15_common.h"
33#include "ih_v6_1.h"
34
35#define MAX_REARM_RETRY 10
36
37static void ih_v6_1_set_interrupt_funcs(struct amdgpu_device *adev);
38
39/**
40 * ih_v6_1_init_register_offset - Initialize register offset for ih rings
41 *
42 * @adev: amdgpu_device pointer
43 *
44 * Initialize register offset ih rings (IH_V6_0).
45 */
46static void ih_v6_1_init_register_offset(struct amdgpu_device *adev)
47{
48 struct amdgpu_ih_regs *ih_regs;
49
50 /* ih ring 2 is removed
51 * ih ring and ih ring 1 are available */
52 if (adev->irq.ih.ring_size) {
53 ih_regs = &adev->irq.ih.ih_regs;
54 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE);
55 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI);
56 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL);
57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR);
58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR);
59 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR);
60 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_LO);
61 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_HI);
62 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
63 }
64
65 if (adev->irq.ih1.ring_size) {
66 ih_regs = &adev->irq.ih1.ih_regs;
67 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_RING1);
68 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI_RING1);
69 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL_RING1);
70 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_RING1);
71 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR_RING1);
72 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR_RING1);
73 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
74 }
75}
76
77/**
78 * force_update_wptr_for_self_int - Force update the wptr for self interrupt
79 *
80 * @adev: amdgpu_device pointer
81 * @threshold: threshold to trigger the wptr reporting
82 * @timeout: timeout to trigger the wptr reporting
83 * @enabled: Enable/disable timeout flush mechanism
84 *
85 * threshold input range: 0 ~ 15, default 0,
86 * real_threshold = 2^threshold
87 * timeout input range: 0 ~ 20, default 8,
88 * real_timeout = (2^timeout) * 1024 / (socclk_freq)
89 *
90 * Force update wptr for self interrupt ( >= SIENNA_CICHLID).
91 */
92static void
93force_update_wptr_for_self_int(struct amdgpu_device *adev,
94 u32 threshold, u32 timeout, bool enabled)
95{
96 u32 ih_cntl, ih_rb_cntl;
97
98 ih_cntl = RREG32_SOC15(OSSSYS, 0, regIH_CNTL2);
99 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1);
100
101 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,
102 SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout);
103 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,
104 SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled);
105 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
106 RB_USED_INT_THRESHOLD, threshold);
107
108 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
109 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl))
110 return;
111 } else {
112 WREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1, ih_rb_cntl);
113 }
114
115 WREG32_SOC15(OSSSYS, 0, regIH_CNTL2, ih_cntl);
116}
117
118/**
119 * ih_v6_1_toggle_ring_interrupts - toggle the interrupt ring buffer
120 *
121 * @adev: amdgpu_device pointer
122 * @ih: amdgpu_ih_ring pointer
123 * @enable: true - enable the interrupts, false - disable the interrupts
124 *
125 * Toggle the interrupt ring buffer (IH_V6_0)
126 */
127static int ih_v6_1_toggle_ring_interrupts(struct amdgpu_device *adev,
128 struct amdgpu_ih_ring *ih,
129 bool enable)
130{
131 struct amdgpu_ih_regs *ih_regs;
132 uint32_t tmp;
133
134 ih_regs = &ih->ih_regs;
135
136 tmp = RREG32(ih_regs->ih_rb_cntl);
137 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
138 /* enable_intr field is only valid in ring0 */
139 if (ih == &adev->irq.ih)
140 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
141
142 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
143 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
144 return -ETIMEDOUT;
145 } else {
146 WREG32(ih_regs->ih_rb_cntl, tmp);
147 }
148
149 if (enable) {
150 ih->enabled = true;
151 } else {
152 /* set rptr, wptr to 0 */
153 WREG32(ih_regs->ih_rb_rptr, 0);
154 WREG32(ih_regs->ih_rb_wptr, 0);
155 ih->enabled = false;
156 ih->rptr = 0;
157 }
158
159 return 0;
160}
161
162/**
163 * ih_v6_1_toggle_interrupts - Toggle all the available interrupt ring buffers
164 *
165 * @adev: amdgpu_device pointer
166 * @enable: enable or disable interrupt ring buffers
167 *
168 * Toggle all the available interrupt ring buffers (IH_V6_0).
169 */
170static int ih_v6_1_toggle_interrupts(struct amdgpu_device *adev, bool enable)
171{
172 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1};
173 int i;
174 int r;
175
176 for (i = 0; i < ARRAY_SIZE(ih); i++) {
177 if (ih[i]->ring_size) {
178 r = ih_v6_1_toggle_ring_interrupts(adev, ih[i], enable);
179 if (r)
180 return r;
181 }
182 }
183
184 return 0;
185}
186
187static uint32_t ih_v6_1_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
188{
189 int rb_bufsz = order_base_2(ih->ring_size / 4);
190
191 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
192 MC_SPACE, ih->use_bus_addr ? 2 : 4);
193 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
194 WPTR_OVERFLOW_CLEAR, 1);
195 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
196 WPTR_OVERFLOW_ENABLE, 1);
197 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
198 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
199 * value is written to memory
200 */
201 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
202 WPTR_WRITEBACK_ENABLE, 1);
203 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
204 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
205 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
206
207 return ih_rb_cntl;
208}
209
210static uint32_t ih_v6_1_doorbell_rptr(struct amdgpu_ih_ring *ih)
211{
212 u32 ih_doorbell_rtpr = 0;
213
214 if (ih->use_doorbell) {
215 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
216 IH_DOORBELL_RPTR, OFFSET,
217 ih->doorbell_index);
218 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
219 IH_DOORBELL_RPTR,
220 ENABLE, 1);
221 } else {
222 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
223 IH_DOORBELL_RPTR,
224 ENABLE, 0);
225 }
226 return ih_doorbell_rtpr;
227}
228
229/**
230 * ih_v6_1_enable_ring - enable an ih ring buffer
231 *
232 * @adev: amdgpu_device pointer
233 * @ih: amdgpu_ih_ring pointer
234 *
235 * Enable an ih ring buffer (IH_V6_0)
236 */
237static int ih_v6_1_enable_ring(struct amdgpu_device *adev,
238 struct amdgpu_ih_ring *ih)
239{
240 struct amdgpu_ih_regs *ih_regs;
241 uint32_t tmp;
242
243 ih_regs = &ih->ih_regs;
244
245 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
246 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
247 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
248
249 tmp = RREG32(ih_regs->ih_rb_cntl);
250 tmp = ih_v6_1_rb_cntl(ih, tmp);
251 if (ih == &adev->irq.ih)
252 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
253 if (ih == &adev->irq.ih1) {
254 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
255 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
256 }
257
258 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
259 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
260 DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
261 return -ETIMEDOUT;
262 }
263 } else {
264 WREG32(ih_regs->ih_rb_cntl, tmp);
265 }
266
267 if (ih == &adev->irq.ih) {
268 /* set the ih ring 0 writeback address whether it's enabled or not */
269 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
270 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
271 }
272
273 /* set rptr, wptr to 0 */
274 WREG32(ih_regs->ih_rb_wptr, 0);
275 WREG32(ih_regs->ih_rb_rptr, 0);
276
277 WREG32(ih_regs->ih_doorbell_rptr, ih_v6_1_doorbell_rptr(ih));
278
279 return 0;
280}
281
282/**
283 * ih_v6_1_irq_init - init and enable the interrupt ring
284 *
285 * @adev: amdgpu_device pointer
286 *
287 * Allocate a ring buffer for the interrupt controller,
288 * enable the RLC, disable interrupts, enable the IH
289 * ring buffer and enable it.
290 * Called at device load and reume.
291 * Returns 0 for success, errors for failure.
292 */
293static int ih_v6_1_irq_init(struct amdgpu_device *adev)
294{
295 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1};
296 u32 ih_chicken;
297 u32 tmp;
298 int ret;
299 int i;
300
301 /* disable irqs */
302 ret = ih_v6_1_toggle_interrupts(adev, false);
303 if (ret)
304 return ret;
305
306 adev->nbio.funcs->ih_control(adev);
307
308 if (unlikely((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) ||
309 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO))) {
310 if (ih[0]->use_bus_addr) {
311 ih_chicken = RREG32_SOC15(OSSSYS, 0, regIH_CHICKEN);
312 ih_chicken = REG_SET_FIELD(ih_chicken,
313 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
314 WREG32_SOC15(OSSSYS, 0, regIH_CHICKEN, ih_chicken);
315 }
316 }
317
318 for (i = 0; i < ARRAY_SIZE(ih); i++) {
319 if (ih[i]->ring_size) {
320 ret = ih_v6_1_enable_ring(adev, ih[i]);
321 if (ret)
322 return ret;
323 }
324 }
325
326 /* update doorbell range for ih ring 0 */
327 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell,
328 ih[0]->doorbell_index);
329
330 tmp = RREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL);
331 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
332 CLIENT18_IS_STORM_CLIENT, 1);
333 WREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL, tmp);
334
335 tmp = RREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL);
336 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);
337 WREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL, tmp);
338
339 /* GC/MMHUB UTCL2 page fault interrupts are configured as
340 * MSI storm capable interrupts by deafult. The delay is
341 * used to avoid ISR being called too frequently
342 * when page fault happens on several continuous page
343 * and thus avoid MSI storm */
344 tmp = RREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL);
345 tmp = REG_SET_FIELD(tmp, IH_MSI_STORM_CTRL,
346 DELAY, 3);
347 WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp);
348
349 /* Redirect the interrupts to IH RB1 for dGPU */
350 if (adev->irq.ih1.ring_size) {
351 tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);
352 tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);
353 WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp);
354
355 tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);
356 tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa);
357 tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0);
358 tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,
359 SOURCE_ID_MATCH_ENABLE, 0x1);
360
361 WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp);
362 }
363
364 pci_set_master(adev->pdev);
365
366 /* enable interrupts */
367 ret = ih_v6_1_toggle_interrupts(adev, true);
368 if (ret)
369 return ret;
370 /* enable wptr force update for self int */
371 force_update_wptr_for_self_int(adev, 0, 8, true);
372
373 if (adev->irq.ih_soft.ring_size)
374 adev->irq.ih_soft.enabled = true;
375
376 return 0;
377}
378
379/**
380 * ih_v6_1_irq_disable - disable interrupts
381 *
382 * @adev: amdgpu_device pointer
383 *
384 * Disable interrupts on the hw.
385 */
386static void ih_v6_1_irq_disable(struct amdgpu_device *adev)
387{
388 force_update_wptr_for_self_int(adev, 0, 8, false);
389 ih_v6_1_toggle_interrupts(adev, false);
390
391 /* Wait and acknowledge irq */
392 mdelay(1);
393}
394
395/**
396 * ih_v6_1_get_wptr - get the IH ring buffer wptr
397 *
398 * @adev: amdgpu_device pointer
399 * @ih: amdgpu_ih_ring pointer
400 *
401 * Get the IH ring buffer wptr from either the register
402 * or the writeback memory buffer. Also check for
403 * ring buffer overflow and deal with it.
404 * Returns the value of the wptr.
405 */
406static u32 ih_v6_1_get_wptr(struct amdgpu_device *adev,
407 struct amdgpu_ih_ring *ih)
408{
409 u32 wptr, tmp;
410 struct amdgpu_ih_regs *ih_regs;
411
412 wptr = le32_to_cpu(*ih->wptr_cpu);
413 ih_regs = &ih->ih_regs;
414
415 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
416 goto out;
417
418 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
419 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
420 goto out;
421 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
422
423 /* When a ring buffer overflow happen start parsing interrupt
424 * from the last not overwritten vector (wptr + 32). Hopefully
425 * this should allow us to catch up.
426 */
427 tmp = (wptr + 32) & ih->ptr_mask;
428 dev_warn(adev->dev, "IH ring buffer overflow "
429 "(0x%08X, 0x%08X, 0x%08X)\n",
430 wptr, ih->rptr, tmp);
431 ih->rptr = tmp;
432
433 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
434 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
435 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
436
437 /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
438 * can be detected.
439 */
440 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
441 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
442
443out:
444 return (wptr & ih->ptr_mask);
445}
446
447/**
448 * ih_v6_1_irq_rearm - rearm IRQ if lost
449 *
450 * @adev: amdgpu_device pointer
451 * @ih: amdgpu_ih_ring pointer
452 *
453 */
454static void ih_v6_1_irq_rearm(struct amdgpu_device *adev,
455 struct amdgpu_ih_ring *ih)
456{
457 uint32_t v = 0;
458 uint32_t i = 0;
459 struct amdgpu_ih_regs *ih_regs;
460
461 ih_regs = &ih->ih_regs;
462
463 /* Rearm IRQ / re-write doorbell if doorbell write is lost */
464 for (i = 0; i < MAX_REARM_RETRY; i++) {
465 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
466 if ((v < ih->ring_size) && (v != ih->rptr))
467 WDOORBELL32(ih->doorbell_index, ih->rptr);
468 else
469 break;
470 }
471}
472
473/**
474 * ih_v6_1_set_rptr - set the IH ring buffer rptr
475 *
476 * @adev: amdgpu_device pointer
477 * @ih: amdgpu_ih_ring pointer
478 *
479 * Set the IH ring buffer rptr.
480 */
481static void ih_v6_1_set_rptr(struct amdgpu_device *adev,
482 struct amdgpu_ih_ring *ih)
483{
484 struct amdgpu_ih_regs *ih_regs;
485
486 if (ih->use_doorbell) {
487 /* XXX check if swapping is necessary on BE */
488 *ih->rptr_cpu = ih->rptr;
489 WDOORBELL32(ih->doorbell_index, ih->rptr);
490
491 if (amdgpu_sriov_vf(adev))
492 ih_v6_1_irq_rearm(adev, ih);
493 } else {
494 ih_regs = &ih->ih_regs;
495 WREG32(ih_regs->ih_rb_rptr, ih->rptr);
496 }
497}
498
499/**
500 * ih_v6_1_self_irq - dispatch work for ring 1
501 *
502 * @adev: amdgpu_device pointer
503 * @source: irq source
504 * @entry: IV with WPTR update
505 *
506 * Update the WPTR from the IV and schedule work to handle the entries.
507 */
508static int ih_v6_1_self_irq(struct amdgpu_device *adev,
509 struct amdgpu_irq_src *source,
510 struct amdgpu_iv_entry *entry)
511{
512 uint32_t wptr = cpu_to_le32(entry->src_data[0]);
513
514 switch (entry->ring_id) {
515 case 1:
516 *adev->irq.ih1.wptr_cpu = wptr;
517 schedule_work(&adev->irq.ih1_work);
518 break;
519 default:
520 break;
521 }
522 return 0;
523}
524
525static const struct amdgpu_irq_src_funcs ih_v6_1_self_irq_funcs = {
526 .process = ih_v6_1_self_irq,
527};
528
529static void ih_v6_1_set_self_irq_funcs(struct amdgpu_device *adev)
530{
531 adev->irq.self_irq.num_types = 0;
532 adev->irq.self_irq.funcs = &ih_v6_1_self_irq_funcs;
533}
534
535static int ih_v6_1_early_init(struct amdgpu_ip_block *ip_block)
536{
537 struct amdgpu_device *adev = ip_block->adev;
538 int ret;
539
540 ret = amdgpu_irq_add_domain(adev);
541 if (ret) {
542 return ret;
543 }
544
545 ih_v6_1_set_interrupt_funcs(adev);
546 ih_v6_1_set_self_irq_funcs(adev);
547 return 0;
548}
549
550static int ih_v6_1_sw_init(struct amdgpu_ip_block *ip_block)
551{
552 int r;
553 struct amdgpu_device *adev = ip_block->adev;
554 bool use_bus_addr;
555
556 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_IH, 0,
557 &adev->irq.self_irq);
558
559 if (r)
560 return r;
561
562 /* use gpu virtual address for ih ring
563 * until ih_checken is programmed to allow
564 * use bus address for ih ring by psp bl */
565 use_bus_addr =
566 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true;
567 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr);
568 if (r)
569 return r;
570
571 adev->irq.ih.use_doorbell = true;
572 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
573
574 if (!(adev->flags & AMD_IS_APU)) {
575 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, IH_RING_SIZE,
576 use_bus_addr);
577 if (r)
578 return r;
579
580 adev->irq.ih1.use_doorbell = true;
581 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
582 }
583
584 /* initialize ih control register offset */
585 ih_v6_1_init_register_offset(adev);
586
587 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true);
588 if (r)
589 return r;
590
591 r = amdgpu_irq_init(adev);
592
593 return r;
594}
595
596static int ih_v6_1_sw_fini(struct amdgpu_ip_block *ip_block)
597{
598 struct amdgpu_device *adev = ip_block->adev;
599
600 amdgpu_irq_fini_sw(adev);
601
602 return 0;
603}
604
605static int ih_v6_1_hw_init(struct amdgpu_ip_block *ip_block)
606{
607 int r;
608 struct amdgpu_device *adev = ip_block->adev;
609
610 r = ih_v6_1_irq_init(adev);
611 if (r)
612 return r;
613
614 return 0;
615}
616
617static int ih_v6_1_hw_fini(struct amdgpu_ip_block *ip_block)
618{
619 ih_v6_1_irq_disable(ip_block->adev);
620
621 return 0;
622}
623
624static int ih_v6_1_suspend(struct amdgpu_ip_block *ip_block)
625{
626 return ih_v6_1_hw_fini(ip_block);
627}
628
629static int ih_v6_1_resume(struct amdgpu_ip_block *ip_block)
630{
631 return ih_v6_1_hw_init(ip_block);
632}
633
634static bool ih_v6_1_is_idle(void *handle)
635{
636 /* todo */
637 return true;
638}
639
640static int ih_v6_1_wait_for_idle(struct amdgpu_ip_block *ip_block)
641{
642 /* todo */
643 return -ETIMEDOUT;
644}
645
646static int ih_v6_1_soft_reset(struct amdgpu_ip_block *ip_block)
647{
648 /* todo */
649 return 0;
650}
651
652static void ih_v6_1_update_clockgating_state(struct amdgpu_device *adev,
653 bool enable)
654{
655 uint32_t data, def, field_val;
656
657 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
658 def = data = RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL);
659 field_val = enable ? 0 : 1;
660 data = REG_SET_FIELD(data, IH_CLK_CTRL,
661 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
662 data = REG_SET_FIELD(data, IH_CLK_CTRL,
663 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
664 data = REG_SET_FIELD(data, IH_CLK_CTRL,
665 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
666 data = REG_SET_FIELD(data, IH_CLK_CTRL,
667 DYN_CLK_SOFT_OVERRIDE, field_val);
668 data = REG_SET_FIELD(data, IH_CLK_CTRL,
669 REG_CLK_SOFT_OVERRIDE, field_val);
670 if (def != data)
671 WREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL, data);
672 }
673
674 return;
675}
676
677static int ih_v6_1_set_clockgating_state(void *handle,
678 enum amd_clockgating_state state)
679{
680 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
681
682 ih_v6_1_update_clockgating_state(adev,
683 state == AMD_CG_STATE_GATE);
684 return 0;
685}
686
687static void ih_v6_1_update_ih_mem_power_gating(struct amdgpu_device *adev,
688 bool enable)
689{
690 uint32_t ih_mem_pwr_cntl;
691
692 /* Disable ih sram power cntl before switch powergating mode */
693 ih_mem_pwr_cntl = RREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL);
694 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
695 IH_BUFFER_MEM_POWER_CTRL_EN, 0);
696 WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
697
698 /* It is recommended to set mem powergating mode to DS mode */
699 if (enable) {
700 /* mem power mode */
701 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
702 IH_BUFFER_MEM_POWER_LS_EN, 0);
703 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
704 IH_BUFFER_MEM_POWER_DS_EN, 1);
705 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
706 IH_BUFFER_MEM_POWER_SD_EN, 0);
707 /* cam mem power mode */
708 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
709 IH_RETRY_INT_CAM_MEM_POWER_LS_EN, 0);
710 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
711 IH_RETRY_INT_CAM_MEM_POWER_DS_EN, 1);
712 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
713 IH_RETRY_INT_CAM_MEM_POWER_SD_EN, 0);
714 /* re-enable power cntl */
715 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
716 IH_BUFFER_MEM_POWER_CTRL_EN, 1);
717 } else {
718 /* mem power mode */
719 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
720 IH_BUFFER_MEM_POWER_LS_EN, 0);
721 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
722 IH_BUFFER_MEM_POWER_DS_EN, 0);
723 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
724 IH_BUFFER_MEM_POWER_SD_EN, 0);
725 /* cam mem power mode */
726 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
727 IH_RETRY_INT_CAM_MEM_POWER_LS_EN, 0);
728 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
729 IH_RETRY_INT_CAM_MEM_POWER_DS_EN, 0);
730 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
731 IH_RETRY_INT_CAM_MEM_POWER_SD_EN, 0);
732 /* re-enable power cntl*/
733 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
734 IH_BUFFER_MEM_POWER_CTRL_EN, 1);
735 }
736
737 WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
738}
739
740static int ih_v6_1_set_powergating_state(void *handle,
741 enum amd_powergating_state state)
742{
743 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
744 bool enable = (state == AMD_PG_STATE_GATE);
745
746 if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
747 ih_v6_1_update_ih_mem_power_gating(adev, enable);
748
749 return 0;
750}
751
752static void ih_v6_1_get_clockgating_state(void *handle, u64 *flags)
753{
754 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
755
756 if (!RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL))
757 *flags |= AMD_CG_SUPPORT_IH_CG;
758
759 return;
760}
761
762static const struct amd_ip_funcs ih_v6_1_ip_funcs = {
763 .name = "ih_v6_1",
764 .early_init = ih_v6_1_early_init,
765 .sw_init = ih_v6_1_sw_init,
766 .sw_fini = ih_v6_1_sw_fini,
767 .hw_init = ih_v6_1_hw_init,
768 .hw_fini = ih_v6_1_hw_fini,
769 .suspend = ih_v6_1_suspend,
770 .resume = ih_v6_1_resume,
771 .is_idle = ih_v6_1_is_idle,
772 .wait_for_idle = ih_v6_1_wait_for_idle,
773 .soft_reset = ih_v6_1_soft_reset,
774 .set_clockgating_state = ih_v6_1_set_clockgating_state,
775 .set_powergating_state = ih_v6_1_set_powergating_state,
776 .get_clockgating_state = ih_v6_1_get_clockgating_state,
777};
778
779static const struct amdgpu_ih_funcs ih_v6_1_funcs = {
780 .get_wptr = ih_v6_1_get_wptr,
781 .decode_iv = amdgpu_ih_decode_iv_helper,
782 .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper,
783 .set_rptr = ih_v6_1_set_rptr
784};
785
786static void ih_v6_1_set_interrupt_funcs(struct amdgpu_device *adev)
787{
788 adev->irq.ih_funcs = &ih_v6_1_funcs;
789}
790
791const struct amdgpu_ip_block_version ih_v6_1_ip_block = {
792 .type = AMD_IP_BLOCK_TYPE_IH,
793 .major = 6,
794 .minor = 0,
795 .rev = 0,
796 .funcs = &ih_v6_1_ip_funcs,
797};