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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27
28#include <drm/amdgpu_drm.h>
29
30#include "amdgpu.h"
31#include "amdgpu_atombios.h"
32#include "amdgpu_ih.h"
33#include "amdgpu_uvd.h"
34#include "amdgpu_vce.h"
35#include "amdgpu_ucode.h"
36#include "amdgpu_psp.h"
37#include "atom.h"
38#include "amd_pcie.h"
39
40#include "uvd/uvd_7_0_offset.h"
41#include "gc/gc_9_0_offset.h"
42#include "gc/gc_9_0_sh_mask.h"
43#include "sdma0/sdma0_4_0_offset.h"
44#include "sdma1/sdma1_4_0_offset.h"
45#include "nbio/nbio_7_0_default.h"
46#include "nbio/nbio_7_0_offset.h"
47#include "nbio/nbio_7_0_sh_mask.h"
48#include "nbio/nbio_7_0_smn.h"
49#include "mp/mp_9_0_offset.h"
50
51#include "soc15.h"
52#include "soc15_common.h"
53#include "gfx_v9_0.h"
54#include "gmc_v9_0.h"
55#include "gfxhub_v1_0.h"
56#include "mmhub_v1_0.h"
57#include "df_v1_7.h"
58#include "df_v3_6.h"
59#include "nbio_v6_1.h"
60#include "nbio_v7_0.h"
61#include "nbio_v7_4.h"
62#include "hdp_v4_0.h"
63#include "vega10_ih.h"
64#include "vega20_ih.h"
65#include "navi10_ih.h"
66#include "sdma_v4_0.h"
67#include "uvd_v7_0.h"
68#include "vce_v4_0.h"
69#include "vcn_v1_0.h"
70#include "vcn_v2_0.h"
71#include "jpeg_v2_0.h"
72#include "vcn_v2_5.h"
73#include "jpeg_v2_5.h"
74#include "smuio_v9_0.h"
75#include "smuio_v11_0.h"
76#include "smuio_v13_0.h"
77#include "amdgpu_vkms.h"
78#include "mxgpu_ai.h"
79#include "amdgpu_ras.h"
80#include "amdgpu_xgmi.h"
81#include <uapi/linux/kfd_ioctl.h>
82
83#define mmMP0_MISC_CGTT_CTRL0 0x01b9
84#define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
85#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
86#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
87
88static const struct amd_ip_funcs soc15_common_ip_funcs;
89
90/* Vega, Raven, Arcturus */
91static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] =
92{
93 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
94 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
95};
96
97static const struct amdgpu_video_codecs vega_video_codecs_encode =
98{
99 .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array),
100 .codec_array = vega_video_codecs_encode_array,
101};
102
103/* Vega */
104static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] =
105{
106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
111 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
112};
113
114static const struct amdgpu_video_codecs vega_video_codecs_decode =
115{
116 .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array),
117 .codec_array = vega_video_codecs_decode_array,
118};
119
120/* Raven */
121static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] =
122{
123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
126 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
127 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)},
130};
131
132static const struct amdgpu_video_codecs rv_video_codecs_decode =
133{
134 .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array),
135 .codec_array = rv_video_codecs_decode_array,
136};
137
138/* Renoir, Arcturus */
139static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] =
140{
141 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
142 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
143 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
144 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
148};
149
150static const struct amdgpu_video_codecs rn_video_codecs_decode =
151{
152 .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array),
153 .codec_array = rn_video_codecs_decode_array,
154};
155
156static const struct amdgpu_video_codec_info vcn_4_0_3_video_codecs_decode_array[] = {
157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
161 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
162};
163
164static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_decode = {
165 .codec_count = ARRAY_SIZE(vcn_4_0_3_video_codecs_decode_array),
166 .codec_array = vcn_4_0_3_video_codecs_decode_array,
167};
168
169static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_encode = {
170 .codec_count = 0,
171 .codec_array = NULL,
172};
173
174static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
175 const struct amdgpu_video_codecs **codecs)
176{
177 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
178 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
179 case IP_VERSION(4, 0, 0):
180 case IP_VERSION(4, 1, 0):
181 if (encode)
182 *codecs = &vega_video_codecs_encode;
183 else
184 *codecs = &vega_video_codecs_decode;
185 return 0;
186 default:
187 return -EINVAL;
188 }
189 } else {
190 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
191 case IP_VERSION(1, 0, 0):
192 case IP_VERSION(1, 0, 1):
193 if (encode)
194 *codecs = &vega_video_codecs_encode;
195 else
196 *codecs = &rv_video_codecs_decode;
197 return 0;
198 case IP_VERSION(2, 5, 0):
199 case IP_VERSION(2, 6, 0):
200 case IP_VERSION(2, 2, 0):
201 if (encode)
202 *codecs = &vega_video_codecs_encode;
203 else
204 *codecs = &rn_video_codecs_decode;
205 return 0;
206 case IP_VERSION(4, 0, 3):
207 if (encode)
208 *codecs = &vcn_4_0_3_video_codecs_encode;
209 else
210 *codecs = &vcn_4_0_3_video_codecs_decode;
211 return 0;
212 default:
213 return -EINVAL;
214 }
215 }
216}
217
218static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
219{
220 unsigned long flags, address, data;
221 u32 r;
222
223 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
224 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
225
226 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
227 WREG32(address, ((reg) & 0x1ff));
228 r = RREG32(data);
229 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
230 return r;
231}
232
233static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
234{
235 unsigned long flags, address, data;
236
237 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
238 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
239
240 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
241 WREG32(address, ((reg) & 0x1ff));
242 WREG32(data, (v));
243 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
244}
245
246static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
247{
248 unsigned long flags, address, data;
249 u32 r;
250
251 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
252 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
253
254 spin_lock_irqsave(&adev->didt_idx_lock, flags);
255 WREG32(address, (reg));
256 r = RREG32(data);
257 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
258 return r;
259}
260
261static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
262{
263 unsigned long flags, address, data;
264
265 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
266 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
267
268 spin_lock_irqsave(&adev->didt_idx_lock, flags);
269 WREG32(address, (reg));
270 WREG32(data, (v));
271 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
272}
273
274static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
275{
276 unsigned long flags;
277 u32 r;
278
279 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
280 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
281 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
282 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
283 return r;
284}
285
286static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
287{
288 unsigned long flags;
289
290 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
291 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
292 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
293 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
294}
295
296static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
297{
298 unsigned long flags;
299 u32 r;
300
301 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
302 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
303 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
304 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
305 return r;
306}
307
308static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
309{
310 unsigned long flags;
311
312 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
313 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
314 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
315 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
316}
317
318static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
319{
320 return adev->nbio.funcs->get_memsize(adev);
321}
322
323static u32 soc15_get_xclk(struct amdgpu_device *adev)
324{
325 u32 reference_clock = adev->clock.spll.reference_freq;
326
327 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 0) ||
328 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 1) ||
329 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6))
330 return 10000;
331 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 0) ||
332 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 1))
333 return reference_clock / 4;
334
335 return reference_clock;
336}
337
338
339void soc15_grbm_select(struct amdgpu_device *adev,
340 u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id)
341{
342 u32 grbm_gfx_cntl = 0;
343 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
344 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
345 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
346 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
347
348 WREG32_SOC15_RLC_SHADOW(GC, xcc_id, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
349}
350
351static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
352{
353 /* todo */
354 return false;
355}
356
357static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
358 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
359 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
360 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
361 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
362 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
363 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
364 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
365 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
366 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
367 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
368 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
369 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
370 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
371 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
372 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
373 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
374 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
375 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
376 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
377 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
378};
379
380static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
381 u32 sh_num, u32 reg_offset)
382{
383 uint32_t val;
384
385 mutex_lock(&adev->grbm_idx_mutex);
386 if (se_num != 0xffffffff || sh_num != 0xffffffff)
387 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
388
389 val = RREG32(reg_offset);
390
391 if (se_num != 0xffffffff || sh_num != 0xffffffff)
392 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
393 mutex_unlock(&adev->grbm_idx_mutex);
394 return val;
395}
396
397static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
398 bool indexed, u32 se_num,
399 u32 sh_num, u32 reg_offset)
400{
401 if (indexed) {
402 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
403 } else {
404 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
405 return adev->gfx.config.gb_addr_config;
406 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
407 return adev->gfx.config.db_debug2;
408 return RREG32(reg_offset);
409 }
410}
411
412static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
413 u32 sh_num, u32 reg_offset, u32 *value)
414{
415 uint32_t i;
416 struct soc15_allowed_register_entry *en;
417
418 *value = 0;
419 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
420 en = &soc15_allowed_read_registers[i];
421 if (!adev->reg_offset[en->hwip][en->inst])
422 continue;
423 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
424 + en->reg_offset))
425 continue;
426
427 *value = soc15_get_register_value(adev,
428 soc15_allowed_read_registers[i].grbm_indexed,
429 se_num, sh_num, reg_offset);
430 return 0;
431 }
432 return -EINVAL;
433}
434
435
436/**
437 * soc15_program_register_sequence - program an array of registers.
438 *
439 * @adev: amdgpu_device pointer
440 * @regs: pointer to the register array
441 * @array_size: size of the register array
442 *
443 * Programs an array or registers with and and or masks.
444 * This is a helper for setting golden registers.
445 */
446
447void soc15_program_register_sequence(struct amdgpu_device *adev,
448 const struct soc15_reg_golden *regs,
449 const u32 array_size)
450{
451 const struct soc15_reg_golden *entry;
452 u32 tmp, reg;
453 int i;
454
455 for (i = 0; i < array_size; ++i) {
456 entry = ®s[i];
457 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
458
459 if (entry->and_mask == 0xffffffff) {
460 tmp = entry->or_mask;
461 } else {
462 tmp = (entry->hwip == GC_HWIP) ?
463 RREG32_SOC15_IP(GC, reg) : RREG32(reg);
464
465 tmp &= ~(entry->and_mask);
466 tmp |= (entry->or_mask & entry->and_mask);
467 }
468
469 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
470 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
471 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
472 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
473 WREG32_RLC(reg, tmp);
474 else
475 (entry->hwip == GC_HWIP) ?
476 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp);
477
478 }
479
480}
481
482static int soc15_asic_baco_reset(struct amdgpu_device *adev)
483{
484 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
485 int ret = 0;
486
487 /* avoid NBIF got stuck when do RAS recovery in BACO reset */
488 if (ras && adev->ras_enabled)
489 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
490
491 ret = amdgpu_dpm_baco_reset(adev);
492 if (ret)
493 return ret;
494
495 /* re-enable doorbell interrupt after BACO exit */
496 if (ras && adev->ras_enabled)
497 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
498
499 return 0;
500}
501
502static enum amd_reset_method
503soc15_asic_reset_method(struct amdgpu_device *adev)
504{
505 bool baco_reset = false;
506 bool connected_to_cpu = false;
507 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
508
509 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu)
510 connected_to_cpu = true;
511
512 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
513 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
514 amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
515 amdgpu_reset_method == AMD_RESET_METHOD_PCI) {
516 /* If connected to cpu, driver only support mode2 */
517 if (connected_to_cpu)
518 return AMD_RESET_METHOD_MODE2;
519 return amdgpu_reset_method;
520 }
521
522 if (amdgpu_reset_method != -1)
523 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
524 amdgpu_reset_method);
525
526 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
527 case IP_VERSION(10, 0, 0):
528 case IP_VERSION(10, 0, 1):
529 case IP_VERSION(12, 0, 0):
530 case IP_VERSION(12, 0, 1):
531 return AMD_RESET_METHOD_MODE2;
532 case IP_VERSION(9, 0, 0):
533 case IP_VERSION(11, 0, 2):
534 if (adev->asic_type == CHIP_VEGA20) {
535 if (adev->psp.sos.fw_version >= 0x80067)
536 baco_reset = amdgpu_dpm_is_baco_supported(adev);
537 /*
538 * 1. PMFW version > 0x284300: all cases use baco
539 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
540 */
541 if (ras && adev->ras_enabled &&
542 adev->pm.fw_version <= 0x283400)
543 baco_reset = false;
544 } else {
545 baco_reset = amdgpu_dpm_is_baco_supported(adev);
546 }
547 break;
548 case IP_VERSION(13, 0, 2):
549 /*
550 * 1.connected to cpu: driver issue mode2 reset
551 * 2.discret gpu: driver issue mode1 reset
552 */
553 if (connected_to_cpu)
554 return AMD_RESET_METHOD_MODE2;
555 break;
556 case IP_VERSION(13, 0, 6):
557 /* Use gpu_recovery param to target a reset method.
558 * Enable triggering of GPU reset only if specified
559 * by module parameter.
560 */
561 if (amdgpu_gpu_recovery == 4 || amdgpu_gpu_recovery == 5)
562 return AMD_RESET_METHOD_MODE2;
563 else if (!(adev->flags & AMD_IS_APU))
564 return AMD_RESET_METHOD_MODE1;
565 else
566 return AMD_RESET_METHOD_MODE2;
567 default:
568 break;
569 }
570
571 if (baco_reset)
572 return AMD_RESET_METHOD_BACO;
573 else
574 return AMD_RESET_METHOD_MODE1;
575}
576
577static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)
578{
579 u32 sol_reg;
580
581 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
582
583 /* Will reset for the following suspend abort cases.
584 * 1) Only reset limit on APU side, dGPU hasn't checked yet.
585 * 2) S3 suspend abort and TOS already launched.
586 */
587 if (adev->flags & AMD_IS_APU && adev->in_s3 &&
588 !adev->suspend_complete &&
589 sol_reg)
590 return true;
591
592 return false;
593}
594
595static int soc15_asic_reset(struct amdgpu_device *adev)
596{
597 /* original raven doesn't have full asic reset */
598 /* On the latest Raven, the GPU reset can be performed
599 * successfully. So now, temporarily enable it for the
600 * S3 suspend abort case.
601 */
602 if (((adev->apu_flags & AMD_APU_IS_RAVEN) ||
603 (adev->apu_flags & AMD_APU_IS_RAVEN2)) &&
604 !soc15_need_reset_on_resume(adev))
605 return 0;
606
607 switch (soc15_asic_reset_method(adev)) {
608 case AMD_RESET_METHOD_PCI:
609 dev_info(adev->dev, "PCI reset\n");
610 return amdgpu_device_pci_reset(adev);
611 case AMD_RESET_METHOD_BACO:
612 dev_info(adev->dev, "BACO reset\n");
613 return soc15_asic_baco_reset(adev);
614 case AMD_RESET_METHOD_MODE2:
615 dev_info(adev->dev, "MODE2 reset\n");
616 return amdgpu_dpm_mode2_reset(adev);
617 default:
618 dev_info(adev->dev, "MODE1 reset\n");
619 return amdgpu_device_mode1_reset(adev);
620 }
621}
622
623static bool soc15_supports_baco(struct amdgpu_device *adev)
624{
625 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
626 case IP_VERSION(9, 0, 0):
627 case IP_VERSION(11, 0, 2):
628 if (adev->asic_type == CHIP_VEGA20) {
629 if (adev->psp.sos.fw_version >= 0x80067)
630 return amdgpu_dpm_is_baco_supported(adev);
631 return false;
632 } else {
633 return amdgpu_dpm_is_baco_supported(adev);
634 }
635 break;
636 default:
637 return false;
638 }
639}
640
641/*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
642 u32 cntl_reg, u32 status_reg)
643{
644 return 0;
645}*/
646
647static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
648{
649 /*int r;
650
651 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
652 if (r)
653 return r;
654
655 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
656 */
657 return 0;
658}
659
660static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
661{
662 /* todo */
663
664 return 0;
665}
666
667static void soc15_program_aspm(struct amdgpu_device *adev)
668{
669 if (!amdgpu_device_should_use_aspm(adev))
670 return;
671
672 if (adev->nbio.funcs->program_aspm)
673 adev->nbio.funcs->program_aspm(adev);
674}
675
676const struct amdgpu_ip_block_version vega10_common_ip_block =
677{
678 .type = AMD_IP_BLOCK_TYPE_COMMON,
679 .major = 2,
680 .minor = 0,
681 .rev = 0,
682 .funcs = &soc15_common_ip_funcs,
683};
684
685static void soc15_reg_base_init(struct amdgpu_device *adev)
686{
687 /* Set IP register base before any HW register access */
688 switch (adev->asic_type) {
689 case CHIP_VEGA10:
690 case CHIP_VEGA12:
691 case CHIP_RAVEN:
692 case CHIP_RENOIR:
693 vega10_reg_base_init(adev);
694 break;
695 case CHIP_VEGA20:
696 vega20_reg_base_init(adev);
697 break;
698 case CHIP_ARCTURUS:
699 arct_reg_base_init(adev);
700 break;
701 case CHIP_ALDEBARAN:
702 aldebaran_reg_base_init(adev);
703 break;
704 default:
705 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type);
706 break;
707 }
708}
709
710void soc15_set_virt_ops(struct amdgpu_device *adev)
711{
712 adev->virt.ops = &xgpu_ai_virt_ops;
713
714 /* init soc15 reg base early enough so we can
715 * request request full access for sriov before
716 * set_ip_blocks. */
717 soc15_reg_base_init(adev);
718}
719
720static bool soc15_need_full_reset(struct amdgpu_device *adev)
721{
722 /* change this when we implement soft reset */
723 return true;
724}
725
726static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
727 uint64_t *count1)
728{
729 uint32_t perfctr = 0;
730 uint64_t cnt0_of, cnt1_of;
731 int tmp;
732
733 /* This reports 0 on APUs, so return to avoid writing/reading registers
734 * that may or may not be different from their GPU counterparts
735 */
736 if (adev->flags & AMD_IS_APU)
737 return;
738
739 /* Set the 2 events that we wish to watch, defined above */
740 /* Reg 40 is # received msgs */
741 /* Reg 104 is # of posted requests sent */
742 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
743 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
744
745 /* Write to enable desired perf counters */
746 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
747 /* Zero out and enable the perf counters
748 * Write 0x5:
749 * Bit 0 = Start all counters(1)
750 * Bit 2 = Global counter reset enable(1)
751 */
752 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
753
754 msleep(1000);
755
756 /* Load the shadow and disable the perf counters
757 * Write 0x2:
758 * Bit 0 = Stop counters(0)
759 * Bit 1 = Load the shadow counters(1)
760 */
761 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
762
763 /* Read register values to get any >32bit overflow */
764 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
765 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
766 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
767
768 /* Get the values and add the overflow */
769 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
770 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
771}
772
773static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
774 uint64_t *count1)
775{
776 uint32_t perfctr = 0;
777 uint64_t cnt0_of, cnt1_of;
778 int tmp;
779
780 /* This reports 0 on APUs, so return to avoid writing/reading registers
781 * that may or may not be different from their GPU counterparts
782 */
783 if (adev->flags & AMD_IS_APU)
784 return;
785
786 /* Set the 2 events that we wish to watch, defined above */
787 /* Reg 40 is # received msgs */
788 /* Reg 108 is # of posted requests sent on VG20 */
789 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
790 EVENT0_SEL, 40);
791 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
792 EVENT1_SEL, 108);
793
794 /* Write to enable desired perf counters */
795 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
796 /* Zero out and enable the perf counters
797 * Write 0x5:
798 * Bit 0 = Start all counters(1)
799 * Bit 2 = Global counter reset enable(1)
800 */
801 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
802
803 msleep(1000);
804
805 /* Load the shadow and disable the perf counters
806 * Write 0x2:
807 * Bit 0 = Stop counters(0)
808 * Bit 1 = Load the shadow counters(1)
809 */
810 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
811
812 /* Read register values to get any >32bit overflow */
813 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
814 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
815 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
816
817 /* Get the values and add the overflow */
818 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
819 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
820}
821
822static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
823{
824 u32 sol_reg;
825
826 /* CP hangs in IGT reloading test on RN, reset to WA */
827 if (adev->asic_type == CHIP_RENOIR)
828 return true;
829
830 /* Just return false for soc15 GPUs. Reset does not seem to
831 * be necessary.
832 */
833 if (!amdgpu_passthrough(adev))
834 return false;
835
836 if (adev->flags & AMD_IS_APU)
837 return false;
838
839 /* Check sOS sign of life register to confirm sys driver and sOS
840 * are already been loaded.
841 */
842 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
843 if (sol_reg)
844 return true;
845
846 return false;
847}
848
849static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
850{
851 uint64_t nak_r, nak_g;
852
853 /* Get the number of NAKs received and generated */
854 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
855 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
856
857 /* Add the total number of NAKs, i.e the number of replays */
858 return (nak_r + nak_g);
859}
860
861static void soc15_pre_asic_init(struct amdgpu_device *adev)
862{
863 gmc_v9_0_restore_registers(adev);
864}
865
866static const struct amdgpu_asic_funcs soc15_asic_funcs =
867{
868 .read_disabled_bios = &soc15_read_disabled_bios,
869 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
870 .read_register = &soc15_read_register,
871 .reset = &soc15_asic_reset,
872 .reset_method = &soc15_asic_reset_method,
873 .get_xclk = &soc15_get_xclk,
874 .set_uvd_clocks = &soc15_set_uvd_clocks,
875 .set_vce_clocks = &soc15_set_vce_clocks,
876 .get_config_memsize = &soc15_get_config_memsize,
877 .need_full_reset = &soc15_need_full_reset,
878 .init_doorbell_index = &vega10_doorbell_index_init,
879 .get_pcie_usage = &soc15_get_pcie_usage,
880 .need_reset_on_init = &soc15_need_reset_on_init,
881 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
882 .supports_baco = &soc15_supports_baco,
883 .pre_asic_init = &soc15_pre_asic_init,
884 .query_video_codecs = &soc15_query_video_codecs,
885};
886
887static const struct amdgpu_asic_funcs vega20_asic_funcs =
888{
889 .read_disabled_bios = &soc15_read_disabled_bios,
890 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
891 .read_register = &soc15_read_register,
892 .reset = &soc15_asic_reset,
893 .reset_method = &soc15_asic_reset_method,
894 .get_xclk = &soc15_get_xclk,
895 .set_uvd_clocks = &soc15_set_uvd_clocks,
896 .set_vce_clocks = &soc15_set_vce_clocks,
897 .get_config_memsize = &soc15_get_config_memsize,
898 .need_full_reset = &soc15_need_full_reset,
899 .init_doorbell_index = &vega20_doorbell_index_init,
900 .get_pcie_usage = &vega20_get_pcie_usage,
901 .need_reset_on_init = &soc15_need_reset_on_init,
902 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
903 .supports_baco = &soc15_supports_baco,
904 .pre_asic_init = &soc15_pre_asic_init,
905 .query_video_codecs = &soc15_query_video_codecs,
906};
907
908static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs =
909{
910 .read_disabled_bios = &soc15_read_disabled_bios,
911 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
912 .read_register = &soc15_read_register,
913 .reset = &soc15_asic_reset,
914 .reset_method = &soc15_asic_reset_method,
915 .get_xclk = &soc15_get_xclk,
916 .set_uvd_clocks = &soc15_set_uvd_clocks,
917 .set_vce_clocks = &soc15_set_vce_clocks,
918 .get_config_memsize = &soc15_get_config_memsize,
919 .need_full_reset = &soc15_need_full_reset,
920 .init_doorbell_index = &aqua_vanjaram_doorbell_index_init,
921 .need_reset_on_init = &soc15_need_reset_on_init,
922 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
923 .supports_baco = &soc15_supports_baco,
924 .pre_asic_init = &soc15_pre_asic_init,
925 .query_video_codecs = &soc15_query_video_codecs,
926 .encode_ext_smn_addressing = &aqua_vanjaram_encode_ext_smn_addressing,
927 .get_reg_state = &aqua_vanjaram_get_reg_state,
928};
929
930static int soc15_common_early_init(void *handle)
931{
932#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
933 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
934
935 if (!amdgpu_sriov_vf(adev)) {
936 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
937 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
938 }
939 adev->smc_rreg = NULL;
940 adev->smc_wreg = NULL;
941 adev->pcie_rreg = &amdgpu_device_indirect_rreg;
942 adev->pcie_wreg = &amdgpu_device_indirect_wreg;
943 adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext;
944 adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext;
945 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
946 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
947 adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext;
948 adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext;
949 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
950 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
951 adev->didt_rreg = &soc15_didt_rreg;
952 adev->didt_wreg = &soc15_didt_wreg;
953 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
954 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
955 adev->se_cac_rreg = &soc15_se_cac_rreg;
956 adev->se_cac_wreg = &soc15_se_cac_wreg;
957
958 adev->rev_id = amdgpu_device_get_rev_id(adev);
959 adev->external_rev_id = 0xFF;
960 /* TODO: split the GC and PG flags based on the relevant IP version for which
961 * they are relevant.
962 */
963 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
964 case IP_VERSION(9, 0, 1):
965 adev->asic_funcs = &soc15_asic_funcs;
966 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
967 AMD_CG_SUPPORT_GFX_MGLS |
968 AMD_CG_SUPPORT_GFX_RLC_LS |
969 AMD_CG_SUPPORT_GFX_CP_LS |
970 AMD_CG_SUPPORT_GFX_3D_CGCG |
971 AMD_CG_SUPPORT_GFX_3D_CGLS |
972 AMD_CG_SUPPORT_GFX_CGCG |
973 AMD_CG_SUPPORT_GFX_CGLS |
974 AMD_CG_SUPPORT_BIF_MGCG |
975 AMD_CG_SUPPORT_BIF_LS |
976 AMD_CG_SUPPORT_HDP_LS |
977 AMD_CG_SUPPORT_DRM_MGCG |
978 AMD_CG_SUPPORT_DRM_LS |
979 AMD_CG_SUPPORT_ROM_MGCG |
980 AMD_CG_SUPPORT_DF_MGCG |
981 AMD_CG_SUPPORT_SDMA_MGCG |
982 AMD_CG_SUPPORT_SDMA_LS |
983 AMD_CG_SUPPORT_MC_MGCG |
984 AMD_CG_SUPPORT_MC_LS;
985 adev->pg_flags = 0;
986 adev->external_rev_id = 0x1;
987 break;
988 case IP_VERSION(9, 2, 1):
989 adev->asic_funcs = &soc15_asic_funcs;
990 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
991 AMD_CG_SUPPORT_GFX_MGLS |
992 AMD_CG_SUPPORT_GFX_CGCG |
993 AMD_CG_SUPPORT_GFX_CGLS |
994 AMD_CG_SUPPORT_GFX_3D_CGCG |
995 AMD_CG_SUPPORT_GFX_3D_CGLS |
996 AMD_CG_SUPPORT_GFX_CP_LS |
997 AMD_CG_SUPPORT_MC_LS |
998 AMD_CG_SUPPORT_MC_MGCG |
999 AMD_CG_SUPPORT_SDMA_MGCG |
1000 AMD_CG_SUPPORT_SDMA_LS |
1001 AMD_CG_SUPPORT_BIF_MGCG |
1002 AMD_CG_SUPPORT_BIF_LS |
1003 AMD_CG_SUPPORT_HDP_MGCG |
1004 AMD_CG_SUPPORT_HDP_LS |
1005 AMD_CG_SUPPORT_ROM_MGCG |
1006 AMD_CG_SUPPORT_VCE_MGCG |
1007 AMD_CG_SUPPORT_UVD_MGCG;
1008 adev->pg_flags = 0;
1009 adev->external_rev_id = adev->rev_id + 0x14;
1010 break;
1011 case IP_VERSION(9, 4, 0):
1012 adev->asic_funcs = &vega20_asic_funcs;
1013 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1014 AMD_CG_SUPPORT_GFX_MGLS |
1015 AMD_CG_SUPPORT_GFX_CGCG |
1016 AMD_CG_SUPPORT_GFX_CGLS |
1017 AMD_CG_SUPPORT_GFX_3D_CGCG |
1018 AMD_CG_SUPPORT_GFX_3D_CGLS |
1019 AMD_CG_SUPPORT_GFX_CP_LS |
1020 AMD_CG_SUPPORT_MC_LS |
1021 AMD_CG_SUPPORT_MC_MGCG |
1022 AMD_CG_SUPPORT_SDMA_MGCG |
1023 AMD_CG_SUPPORT_SDMA_LS |
1024 AMD_CG_SUPPORT_BIF_MGCG |
1025 AMD_CG_SUPPORT_BIF_LS |
1026 AMD_CG_SUPPORT_HDP_MGCG |
1027 AMD_CG_SUPPORT_HDP_LS |
1028 AMD_CG_SUPPORT_ROM_MGCG |
1029 AMD_CG_SUPPORT_VCE_MGCG |
1030 AMD_CG_SUPPORT_UVD_MGCG;
1031 adev->pg_flags = 0;
1032 adev->external_rev_id = adev->rev_id + 0x28;
1033 break;
1034 case IP_VERSION(9, 1, 0):
1035 case IP_VERSION(9, 2, 2):
1036 adev->asic_funcs = &soc15_asic_funcs;
1037
1038 if (adev->rev_id >= 0x8)
1039 adev->apu_flags |= AMD_APU_IS_RAVEN2;
1040
1041 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1042 adev->external_rev_id = adev->rev_id + 0x79;
1043 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1044 adev->external_rev_id = adev->rev_id + 0x41;
1045 else if (adev->rev_id == 1)
1046 adev->external_rev_id = adev->rev_id + 0x20;
1047 else
1048 adev->external_rev_id = adev->rev_id + 0x01;
1049
1050 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1051 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1052 AMD_CG_SUPPORT_GFX_MGLS |
1053 AMD_CG_SUPPORT_GFX_CP_LS |
1054 AMD_CG_SUPPORT_GFX_3D_CGCG |
1055 AMD_CG_SUPPORT_GFX_3D_CGLS |
1056 AMD_CG_SUPPORT_GFX_CGCG |
1057 AMD_CG_SUPPORT_GFX_CGLS |
1058 AMD_CG_SUPPORT_BIF_LS |
1059 AMD_CG_SUPPORT_HDP_LS |
1060 AMD_CG_SUPPORT_MC_MGCG |
1061 AMD_CG_SUPPORT_MC_LS |
1062 AMD_CG_SUPPORT_SDMA_MGCG |
1063 AMD_CG_SUPPORT_SDMA_LS |
1064 AMD_CG_SUPPORT_VCN_MGCG;
1065
1066 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1067 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
1068 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1069 AMD_CG_SUPPORT_GFX_MGLS |
1070 AMD_CG_SUPPORT_GFX_CP_LS |
1071 AMD_CG_SUPPORT_GFX_3D_CGLS |
1072 AMD_CG_SUPPORT_GFX_CGCG |
1073 AMD_CG_SUPPORT_GFX_CGLS |
1074 AMD_CG_SUPPORT_BIF_LS |
1075 AMD_CG_SUPPORT_HDP_LS |
1076 AMD_CG_SUPPORT_MC_MGCG |
1077 AMD_CG_SUPPORT_MC_LS |
1078 AMD_CG_SUPPORT_SDMA_MGCG |
1079 AMD_CG_SUPPORT_SDMA_LS |
1080 AMD_CG_SUPPORT_VCN_MGCG;
1081
1082 /*
1083 * MMHUB PG needs to be disabled for Picasso for
1084 * stability reasons.
1085 */
1086 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1087 AMD_PG_SUPPORT_VCN;
1088 } else {
1089 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1090 AMD_CG_SUPPORT_GFX_MGLS |
1091 AMD_CG_SUPPORT_GFX_RLC_LS |
1092 AMD_CG_SUPPORT_GFX_CP_LS |
1093 AMD_CG_SUPPORT_GFX_3D_CGLS |
1094 AMD_CG_SUPPORT_GFX_CGCG |
1095 AMD_CG_SUPPORT_GFX_CGLS |
1096 AMD_CG_SUPPORT_BIF_MGCG |
1097 AMD_CG_SUPPORT_BIF_LS |
1098 AMD_CG_SUPPORT_HDP_MGCG |
1099 AMD_CG_SUPPORT_HDP_LS |
1100 AMD_CG_SUPPORT_DRM_MGCG |
1101 AMD_CG_SUPPORT_DRM_LS |
1102 AMD_CG_SUPPORT_MC_MGCG |
1103 AMD_CG_SUPPORT_MC_LS |
1104 AMD_CG_SUPPORT_SDMA_MGCG |
1105 AMD_CG_SUPPORT_SDMA_LS |
1106 AMD_CG_SUPPORT_VCN_MGCG;
1107
1108 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1109 }
1110 break;
1111 case IP_VERSION(9, 4, 1):
1112 adev->asic_funcs = &vega20_asic_funcs;
1113 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1114 AMD_CG_SUPPORT_GFX_MGLS |
1115 AMD_CG_SUPPORT_GFX_CGCG |
1116 AMD_CG_SUPPORT_GFX_CGLS |
1117 AMD_CG_SUPPORT_GFX_CP_LS |
1118 AMD_CG_SUPPORT_HDP_MGCG |
1119 AMD_CG_SUPPORT_HDP_LS |
1120 AMD_CG_SUPPORT_SDMA_MGCG |
1121 AMD_CG_SUPPORT_SDMA_LS |
1122 AMD_CG_SUPPORT_MC_MGCG |
1123 AMD_CG_SUPPORT_MC_LS |
1124 AMD_CG_SUPPORT_IH_CG |
1125 AMD_CG_SUPPORT_VCN_MGCG |
1126 AMD_CG_SUPPORT_JPEG_MGCG;
1127 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
1128 adev->external_rev_id = adev->rev_id + 0x32;
1129 break;
1130 case IP_VERSION(9, 3, 0):
1131 adev->asic_funcs = &soc15_asic_funcs;
1132
1133 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1134 adev->external_rev_id = adev->rev_id + 0x91;
1135 else
1136 adev->external_rev_id = adev->rev_id + 0xa1;
1137 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1138 AMD_CG_SUPPORT_GFX_MGLS |
1139 AMD_CG_SUPPORT_GFX_3D_CGCG |
1140 AMD_CG_SUPPORT_GFX_3D_CGLS |
1141 AMD_CG_SUPPORT_GFX_CGCG |
1142 AMD_CG_SUPPORT_GFX_CGLS |
1143 AMD_CG_SUPPORT_GFX_CP_LS |
1144 AMD_CG_SUPPORT_MC_MGCG |
1145 AMD_CG_SUPPORT_MC_LS |
1146 AMD_CG_SUPPORT_SDMA_MGCG |
1147 AMD_CG_SUPPORT_SDMA_LS |
1148 AMD_CG_SUPPORT_BIF_LS |
1149 AMD_CG_SUPPORT_HDP_LS |
1150 AMD_CG_SUPPORT_VCN_MGCG |
1151 AMD_CG_SUPPORT_JPEG_MGCG |
1152 AMD_CG_SUPPORT_IH_CG |
1153 AMD_CG_SUPPORT_ATHUB_LS |
1154 AMD_CG_SUPPORT_ATHUB_MGCG |
1155 AMD_CG_SUPPORT_DF_MGCG;
1156 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1157 AMD_PG_SUPPORT_VCN |
1158 AMD_PG_SUPPORT_JPEG |
1159 AMD_PG_SUPPORT_VCN_DPG;
1160 break;
1161 case IP_VERSION(9, 4, 2):
1162 adev->asic_funcs = &vega20_asic_funcs;
1163 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1164 AMD_CG_SUPPORT_GFX_MGLS |
1165 AMD_CG_SUPPORT_GFX_CP_LS |
1166 AMD_CG_SUPPORT_HDP_LS |
1167 AMD_CG_SUPPORT_SDMA_MGCG |
1168 AMD_CG_SUPPORT_SDMA_LS |
1169 AMD_CG_SUPPORT_IH_CG |
1170 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG;
1171 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
1172 adev->external_rev_id = adev->rev_id + 0x3c;
1173 break;
1174 case IP_VERSION(9, 4, 3):
1175 adev->asic_funcs = &aqua_vanjaram_asic_funcs;
1176 adev->cg_flags =
1177 AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGCG |
1178 AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_SDMA_MGCG |
1179 AMD_CG_SUPPORT_GFX_FGCG | AMD_CG_SUPPORT_REPEATER_FGCG |
1180 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG |
1181 AMD_CG_SUPPORT_IH_CG;
1182 adev->pg_flags =
1183 AMD_PG_SUPPORT_VCN |
1184 AMD_PG_SUPPORT_VCN_DPG |
1185 AMD_PG_SUPPORT_JPEG;
1186 adev->external_rev_id = adev->rev_id + 0x46;
1187 /* GC 9.4.3 uses MMIO register region hole at a different offset */
1188 if (!amdgpu_sriov_vf(adev)) {
1189 adev->rmmio_remap.reg_offset = 0x1A000;
1190 adev->rmmio_remap.bus_addr = adev->rmmio_base + 0x1A000;
1191 }
1192 break;
1193 default:
1194 /* FIXME: not supported yet */
1195 return -EINVAL;
1196 }
1197
1198 if (amdgpu_sriov_vf(adev)) {
1199 amdgpu_virt_init_setting(adev);
1200 xgpu_ai_mailbox_set_irq_funcs(adev);
1201 }
1202
1203 return 0;
1204}
1205
1206static int soc15_common_late_init(void *handle)
1207{
1208 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1209
1210 if (amdgpu_sriov_vf(adev))
1211 xgpu_ai_mailbox_get_irq(adev);
1212
1213 /* Enable selfring doorbell aperture late because doorbell BAR
1214 * aperture will change if resize BAR successfully in gmc sw_init.
1215 */
1216 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);
1217
1218 return 0;
1219}
1220
1221static int soc15_common_sw_init(void *handle)
1222{
1223 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1224
1225 if (amdgpu_sriov_vf(adev))
1226 xgpu_ai_mailbox_add_irq_id(adev);
1227
1228 if (adev->df.funcs &&
1229 adev->df.funcs->sw_init)
1230 adev->df.funcs->sw_init(adev);
1231
1232 return 0;
1233}
1234
1235static int soc15_common_sw_fini(void *handle)
1236{
1237 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1238
1239 if (adev->df.funcs &&
1240 adev->df.funcs->sw_fini)
1241 adev->df.funcs->sw_fini(adev);
1242 return 0;
1243}
1244
1245static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev)
1246{
1247 int i;
1248
1249 /* sdma doorbell range is programed by hypervisor */
1250 if (!amdgpu_sriov_vf(adev)) {
1251 for (i = 0; i < adev->sdma.num_instances; i++) {
1252 adev->nbio.funcs->sdma_doorbell_range(adev, i,
1253 true, adev->doorbell_index.sdma_engine[i] << 1,
1254 adev->doorbell_index.sdma_doorbell_range);
1255 }
1256 }
1257}
1258
1259static int soc15_common_hw_init(void *handle)
1260{
1261 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1262
1263 /* enable aspm */
1264 soc15_program_aspm(adev);
1265 /* setup nbio registers */
1266 adev->nbio.funcs->init_registers(adev);
1267 /* remap HDP registers to a hole in mmio space,
1268 * for the purpose of expose those registers
1269 * to process space
1270 */
1271 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
1272 adev->nbio.funcs->remap_hdp_registers(adev);
1273
1274 /* enable the doorbell aperture */
1275 adev->nbio.funcs->enable_doorbell_aperture(adev, true);
1276
1277 /* HW doorbell routing policy: doorbell writing not
1278 * in SDMA/IH/MM/ACV range will be routed to CP. So
1279 * we need to init SDMA doorbell range prior
1280 * to CP ip block init and ring test. IH already
1281 * happens before CP.
1282 */
1283 soc15_sdma_doorbell_range_init(adev);
1284
1285 return 0;
1286}
1287
1288static int soc15_common_hw_fini(void *handle)
1289{
1290 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1291
1292 /* Disable the doorbell aperture and selfring doorbell aperture
1293 * separately in hw_fini because soc15_enable_doorbell_aperture
1294 * has been removed and there is no need to delay disabling
1295 * selfring doorbell.
1296 */
1297 adev->nbio.funcs->enable_doorbell_aperture(adev, false);
1298 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
1299
1300 if (amdgpu_sriov_vf(adev))
1301 xgpu_ai_mailbox_put_irq(adev);
1302
1303 if ((!amdgpu_sriov_vf(adev)) &&
1304 adev->nbio.ras_if &&
1305 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1306 if (adev->nbio.ras &&
1307 adev->nbio.ras->init_ras_controller_interrupt)
1308 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1309 if (adev->nbio.ras &&
1310 adev->nbio.ras->init_ras_err_event_athub_interrupt)
1311 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1312 }
1313
1314 return 0;
1315}
1316
1317static int soc15_common_suspend(void *handle)
1318{
1319 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1320
1321 return soc15_common_hw_fini(adev);
1322}
1323
1324static int soc15_common_resume(void *handle)
1325{
1326 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1327
1328 if (soc15_need_reset_on_resume(adev)) {
1329 dev_info(adev->dev, "S3 suspend abort case, let's reset ASIC.\n");
1330 soc15_asic_reset(adev);
1331 }
1332 return soc15_common_hw_init(adev);
1333}
1334
1335static bool soc15_common_is_idle(void *handle)
1336{
1337 return true;
1338}
1339
1340static int soc15_common_wait_for_idle(void *handle)
1341{
1342 return 0;
1343}
1344
1345static int soc15_common_soft_reset(void *handle)
1346{
1347 return 0;
1348}
1349
1350static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1351{
1352 uint32_t def, data;
1353
1354 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1355
1356 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1357 data &= ~(0x01000000 |
1358 0x02000000 |
1359 0x04000000 |
1360 0x08000000 |
1361 0x10000000 |
1362 0x20000000 |
1363 0x40000000 |
1364 0x80000000);
1365 else
1366 data |= (0x01000000 |
1367 0x02000000 |
1368 0x04000000 |
1369 0x08000000 |
1370 0x10000000 |
1371 0x20000000 |
1372 0x40000000 |
1373 0x80000000);
1374
1375 if (def != data)
1376 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1377}
1378
1379static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1380{
1381 uint32_t def, data;
1382
1383 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1384
1385 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1386 data |= 1;
1387 else
1388 data &= ~1;
1389
1390 if (def != data)
1391 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1392}
1393
1394static int soc15_common_set_clockgating_state(void *handle,
1395 enum amd_clockgating_state state)
1396{
1397 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1398
1399 if (amdgpu_sriov_vf(adev))
1400 return 0;
1401
1402 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
1403 case IP_VERSION(6, 1, 0):
1404 case IP_VERSION(6, 2, 0):
1405 case IP_VERSION(7, 4, 0):
1406 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1407 state == AMD_CG_STATE_GATE);
1408 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1409 state == AMD_CG_STATE_GATE);
1410 adev->hdp.funcs->update_clock_gating(adev,
1411 state == AMD_CG_STATE_GATE);
1412 soc15_update_drm_clock_gating(adev,
1413 state == AMD_CG_STATE_GATE);
1414 soc15_update_drm_light_sleep(adev,
1415 state == AMD_CG_STATE_GATE);
1416 adev->smuio.funcs->update_rom_clock_gating(adev,
1417 state == AMD_CG_STATE_GATE);
1418 adev->df.funcs->update_medium_grain_clock_gating(adev,
1419 state == AMD_CG_STATE_GATE);
1420 break;
1421 case IP_VERSION(7, 0, 0):
1422 case IP_VERSION(7, 0, 1):
1423 case IP_VERSION(2, 5, 0):
1424 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1425 state == AMD_CG_STATE_GATE);
1426 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1427 state == AMD_CG_STATE_GATE);
1428 adev->hdp.funcs->update_clock_gating(adev,
1429 state == AMD_CG_STATE_GATE);
1430 soc15_update_drm_clock_gating(adev,
1431 state == AMD_CG_STATE_GATE);
1432 soc15_update_drm_light_sleep(adev,
1433 state == AMD_CG_STATE_GATE);
1434 break;
1435 case IP_VERSION(7, 4, 1):
1436 case IP_VERSION(7, 4, 4):
1437 adev->hdp.funcs->update_clock_gating(adev,
1438 state == AMD_CG_STATE_GATE);
1439 break;
1440 default:
1441 break;
1442 }
1443 return 0;
1444}
1445
1446static void soc15_common_get_clockgating_state(void *handle, u64 *flags)
1447{
1448 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1449 int data;
1450
1451 if (amdgpu_sriov_vf(adev))
1452 *flags = 0;
1453
1454 if (adev->nbio.funcs && adev->nbio.funcs->get_clockgating_state)
1455 adev->nbio.funcs->get_clockgating_state(adev, flags);
1456
1457 if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state)
1458 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1459
1460 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) &&
1461 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6))) {
1462 /* AMD_CG_SUPPORT_DRM_MGCG */
1463 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1464 if (!(data & 0x01000000))
1465 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1466
1467 /* AMD_CG_SUPPORT_DRM_LS */
1468 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1469 if (data & 0x1)
1470 *flags |= AMD_CG_SUPPORT_DRM_LS;
1471 }
1472
1473 /* AMD_CG_SUPPORT_ROM_MGCG */
1474 if (adev->smuio.funcs && adev->smuio.funcs->get_clock_gating_state)
1475 adev->smuio.funcs->get_clock_gating_state(adev, flags);
1476
1477 if (adev->df.funcs && adev->df.funcs->get_clockgating_state)
1478 adev->df.funcs->get_clockgating_state(adev, flags);
1479}
1480
1481static int soc15_common_set_powergating_state(void *handle,
1482 enum amd_powergating_state state)
1483{
1484 /* todo */
1485 return 0;
1486}
1487
1488static const struct amd_ip_funcs soc15_common_ip_funcs = {
1489 .name = "soc15_common",
1490 .early_init = soc15_common_early_init,
1491 .late_init = soc15_common_late_init,
1492 .sw_init = soc15_common_sw_init,
1493 .sw_fini = soc15_common_sw_fini,
1494 .hw_init = soc15_common_hw_init,
1495 .hw_fini = soc15_common_hw_fini,
1496 .suspend = soc15_common_suspend,
1497 .resume = soc15_common_resume,
1498 .is_idle = soc15_common_is_idle,
1499 .wait_for_idle = soc15_common_wait_for_idle,
1500 .soft_reset = soc15_common_soft_reset,
1501 .set_clockgating_state = soc15_common_set_clockgating_state,
1502 .set_powergating_state = soc15_common_set_powergating_state,
1503 .get_clockgating_state= soc15_common_get_clockgating_state,
1504};
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27
28#include "amdgpu.h"
29#include "amdgpu_atombios.h"
30#include "amdgpu_ih.h"
31#include "amdgpu_uvd.h"
32#include "amdgpu_vce.h"
33#include "amdgpu_ucode.h"
34#include "amdgpu_psp.h"
35#include "atom.h"
36#include "amd_pcie.h"
37
38#include "uvd/uvd_7_0_offset.h"
39#include "gc/gc_9_0_offset.h"
40#include "gc/gc_9_0_sh_mask.h"
41#include "sdma0/sdma0_4_0_offset.h"
42#include "sdma1/sdma1_4_0_offset.h"
43#include "hdp/hdp_4_0_offset.h"
44#include "hdp/hdp_4_0_sh_mask.h"
45#include "smuio/smuio_9_0_offset.h"
46#include "smuio/smuio_9_0_sh_mask.h"
47#include "nbio/nbio_7_0_default.h"
48#include "nbio/nbio_7_0_offset.h"
49#include "nbio/nbio_7_0_sh_mask.h"
50#include "nbio/nbio_7_0_smn.h"
51#include "mp/mp_9_0_offset.h"
52
53#include "soc15.h"
54#include "soc15_common.h"
55#include "gfx_v9_0.h"
56#include "gmc_v9_0.h"
57#include "gfxhub_v1_0.h"
58#include "mmhub_v1_0.h"
59#include "df_v1_7.h"
60#include "df_v3_6.h"
61#include "nbio_v6_1.h"
62#include "nbio_v7_0.h"
63#include "nbio_v7_4.h"
64#include "vega10_ih.h"
65#include "sdma_v4_0.h"
66#include "uvd_v7_0.h"
67#include "vce_v4_0.h"
68#include "vcn_v1_0.h"
69#include "vcn_v2_0.h"
70#include "jpeg_v2_0.h"
71#include "vcn_v2_5.h"
72#include "jpeg_v2_5.h"
73#include "dce_virtual.h"
74#include "mxgpu_ai.h"
75#include "amdgpu_smu.h"
76#include "amdgpu_ras.h"
77#include "amdgpu_xgmi.h"
78#include <uapi/linux/kfd_ioctl.h>
79
80#define mmMP0_MISC_CGTT_CTRL0 0x01b9
81#define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
82#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
83#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
84
85/* for Vega20 register name change */
86#define mmHDP_MEM_POWER_CTRL 0x00d4
87#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
88#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
89#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
90#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
91#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
92
93/* for Vega20/arcturus regiter offset change */
94#define mmROM_INDEX_VG20 0x00e4
95#define mmROM_INDEX_VG20_BASE_IDX 0
96#define mmROM_DATA_VG20 0x00e5
97#define mmROM_DATA_VG20_BASE_IDX 0
98
99/*
100 * Indirect registers accessor
101 */
102static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
103{
104 unsigned long flags, address, data;
105 u32 r;
106 address = adev->nbio.funcs->get_pcie_index_offset(adev);
107 data = adev->nbio.funcs->get_pcie_data_offset(adev);
108
109 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
110 WREG32(address, reg);
111 (void)RREG32(address);
112 r = RREG32(data);
113 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
114 return r;
115}
116
117static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
118{
119 unsigned long flags, address, data;
120
121 address = adev->nbio.funcs->get_pcie_index_offset(adev);
122 data = adev->nbio.funcs->get_pcie_data_offset(adev);
123
124 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
125 WREG32(address, reg);
126 (void)RREG32(address);
127 WREG32(data, v);
128 (void)RREG32(data);
129 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
130}
131
132static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
133{
134 unsigned long flags, address, data;
135 u64 r;
136 address = adev->nbio.funcs->get_pcie_index_offset(adev);
137 data = adev->nbio.funcs->get_pcie_data_offset(adev);
138
139 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
140 /* read low 32 bit */
141 WREG32(address, reg);
142 (void)RREG32(address);
143 r = RREG32(data);
144
145 /* read high 32 bit*/
146 WREG32(address, reg + 4);
147 (void)RREG32(address);
148 r |= ((u64)RREG32(data) << 32);
149 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
150 return r;
151}
152
153static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
154{
155 unsigned long flags, address, data;
156
157 address = adev->nbio.funcs->get_pcie_index_offset(adev);
158 data = adev->nbio.funcs->get_pcie_data_offset(adev);
159
160 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
161 /* write low 32 bit */
162 WREG32(address, reg);
163 (void)RREG32(address);
164 WREG32(data, (u32)(v & 0xffffffffULL));
165 (void)RREG32(data);
166
167 /* write high 32 bit */
168 WREG32(address, reg + 4);
169 (void)RREG32(address);
170 WREG32(data, (u32)(v >> 32));
171 (void)RREG32(data);
172 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
173}
174
175static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
176{
177 unsigned long flags, address, data;
178 u32 r;
179
180 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
181 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
182
183 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
184 WREG32(address, ((reg) & 0x1ff));
185 r = RREG32(data);
186 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
187 return r;
188}
189
190static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
191{
192 unsigned long flags, address, data;
193
194 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
195 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
196
197 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
198 WREG32(address, ((reg) & 0x1ff));
199 WREG32(data, (v));
200 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
201}
202
203static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
204{
205 unsigned long flags, address, data;
206 u32 r;
207
208 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
209 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
210
211 spin_lock_irqsave(&adev->didt_idx_lock, flags);
212 WREG32(address, (reg));
213 r = RREG32(data);
214 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
215 return r;
216}
217
218static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
219{
220 unsigned long flags, address, data;
221
222 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
223 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
224
225 spin_lock_irqsave(&adev->didt_idx_lock, flags);
226 WREG32(address, (reg));
227 WREG32(data, (v));
228 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
229}
230
231static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
232{
233 unsigned long flags;
234 u32 r;
235
236 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
237 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
238 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
239 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
240 return r;
241}
242
243static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
244{
245 unsigned long flags;
246
247 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
248 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
249 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
250 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
251}
252
253static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
254{
255 unsigned long flags;
256 u32 r;
257
258 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
259 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
260 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
261 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
262 return r;
263}
264
265static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
266{
267 unsigned long flags;
268
269 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
270 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
271 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
272 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
273}
274
275static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
276{
277 return adev->nbio.funcs->get_memsize(adev);
278}
279
280static u32 soc15_get_xclk(struct amdgpu_device *adev)
281{
282 u32 reference_clock = adev->clock.spll.reference_freq;
283
284 if (adev->asic_type == CHIP_RAVEN)
285 return reference_clock / 4;
286
287 return reference_clock;
288}
289
290
291void soc15_grbm_select(struct amdgpu_device *adev,
292 u32 me, u32 pipe, u32 queue, u32 vmid)
293{
294 u32 grbm_gfx_cntl = 0;
295 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
296 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
297 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
298 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
299
300 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
301}
302
303static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
304{
305 /* todo */
306}
307
308static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
309{
310 /* todo */
311 return false;
312}
313
314static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
315 u8 *bios, u32 length_bytes)
316{
317 u32 *dw_ptr;
318 u32 i, length_dw;
319 uint32_t rom_index_offset;
320 uint32_t rom_data_offset;
321
322 if (bios == NULL)
323 return false;
324 if (length_bytes == 0)
325 return false;
326 /* APU vbios image is part of sbios image */
327 if (adev->flags & AMD_IS_APU)
328 return false;
329
330 dw_ptr = (u32 *)bios;
331 length_dw = ALIGN(length_bytes, 4) / 4;
332
333 switch (adev->asic_type) {
334 case CHIP_VEGA20:
335 case CHIP_ARCTURUS:
336 rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX_VG20);
337 rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA_VG20);
338 break;
339 default:
340 rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);
341 rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);
342 break;
343 }
344
345 /* set rom index to 0 */
346 WREG32(rom_index_offset, 0);
347 /* read out the rom data */
348 for (i = 0; i < length_dw; i++)
349 dw_ptr[i] = RREG32(rom_data_offset);
350
351 return true;
352}
353
354static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
355 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
356 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
357 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
358 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
359 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
360 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
361 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
362 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
363 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
364 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
365 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
366 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
367 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
368 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
369 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
370 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
371 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
372 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
373 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
374 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
375};
376
377static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
378 u32 sh_num, u32 reg_offset)
379{
380 uint32_t val;
381
382 mutex_lock(&adev->grbm_idx_mutex);
383 if (se_num != 0xffffffff || sh_num != 0xffffffff)
384 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
385
386 val = RREG32(reg_offset);
387
388 if (se_num != 0xffffffff || sh_num != 0xffffffff)
389 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
390 mutex_unlock(&adev->grbm_idx_mutex);
391 return val;
392}
393
394static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
395 bool indexed, u32 se_num,
396 u32 sh_num, u32 reg_offset)
397{
398 if (indexed) {
399 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
400 } else {
401 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
402 return adev->gfx.config.gb_addr_config;
403 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
404 return adev->gfx.config.db_debug2;
405 return RREG32(reg_offset);
406 }
407}
408
409static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
410 u32 sh_num, u32 reg_offset, u32 *value)
411{
412 uint32_t i;
413 struct soc15_allowed_register_entry *en;
414
415 *value = 0;
416 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
417 en = &soc15_allowed_read_registers[i];
418 if (adev->reg_offset[en->hwip][en->inst] &&
419 reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
420 + en->reg_offset))
421 continue;
422
423 *value = soc15_get_register_value(adev,
424 soc15_allowed_read_registers[i].grbm_indexed,
425 se_num, sh_num, reg_offset);
426 return 0;
427 }
428 return -EINVAL;
429}
430
431
432/**
433 * soc15_program_register_sequence - program an array of registers.
434 *
435 * @adev: amdgpu_device pointer
436 * @regs: pointer to the register array
437 * @array_size: size of the register array
438 *
439 * Programs an array or registers with and and or masks.
440 * This is a helper for setting golden registers.
441 */
442
443void soc15_program_register_sequence(struct amdgpu_device *adev,
444 const struct soc15_reg_golden *regs,
445 const u32 array_size)
446{
447 const struct soc15_reg_golden *entry;
448 u32 tmp, reg;
449 int i;
450
451 for (i = 0; i < array_size; ++i) {
452 entry = ®s[i];
453 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
454
455 if (entry->and_mask == 0xffffffff) {
456 tmp = entry->or_mask;
457 } else {
458 tmp = RREG32(reg);
459 tmp &= ~(entry->and_mask);
460 tmp |= (entry->or_mask & entry->and_mask);
461 }
462
463 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
464 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
465 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
466 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
467 WREG32_RLC(reg, tmp);
468 else
469 WREG32(reg, tmp);
470
471 }
472
473}
474
475static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
476{
477 u32 i;
478 int ret = 0;
479
480 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
481
482 dev_info(adev->dev, "GPU mode1 reset\n");
483
484 /* disable BM */
485 pci_clear_master(adev->pdev);
486
487 pci_save_state(adev->pdev);
488
489 ret = psp_gpu_reset(adev);
490 if (ret)
491 dev_err(adev->dev, "GPU mode1 reset failed\n");
492
493 pci_restore_state(adev->pdev);
494
495 /* wait for asic to come out of reset */
496 for (i = 0; i < adev->usec_timeout; i++) {
497 u32 memsize = adev->nbio.funcs->get_memsize(adev);
498
499 if (memsize != 0xffffffff)
500 break;
501 udelay(1);
502 }
503
504 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
505
506 return ret;
507}
508
509static int soc15_asic_baco_reset(struct amdgpu_device *adev)
510{
511 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
512 int ret = 0;
513
514 /* avoid NBIF got stuck when do RAS recovery in BACO reset */
515 if (ras && ras->supported)
516 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
517
518 ret = amdgpu_dpm_baco_reset(adev);
519 if (ret)
520 return ret;
521
522 /* re-enable doorbell interrupt after BACO exit */
523 if (ras && ras->supported)
524 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
525
526 return 0;
527}
528
529static enum amd_reset_method
530soc15_asic_reset_method(struct amdgpu_device *adev)
531{
532 bool baco_reset = false;
533 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
534
535 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
536 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
537 amdgpu_reset_method == AMD_RESET_METHOD_BACO)
538 return amdgpu_reset_method;
539
540 if (amdgpu_reset_method != -1)
541 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
542 amdgpu_reset_method);
543
544 switch (adev->asic_type) {
545 case CHIP_RAVEN:
546 case CHIP_RENOIR:
547 return AMD_RESET_METHOD_MODE2;
548 case CHIP_VEGA10:
549 case CHIP_VEGA12:
550 case CHIP_ARCTURUS:
551 baco_reset = amdgpu_dpm_is_baco_supported(adev);
552 break;
553 case CHIP_VEGA20:
554 if (adev->psp.sos_fw_version >= 0x80067)
555 baco_reset = amdgpu_dpm_is_baco_supported(adev);
556
557 /*
558 * 1. PMFW version > 0x284300: all cases use baco
559 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
560 */
561 if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400)
562 baco_reset = false;
563 break;
564 default:
565 break;
566 }
567
568 if (baco_reset)
569 return AMD_RESET_METHOD_BACO;
570 else
571 return AMD_RESET_METHOD_MODE1;
572}
573
574static int soc15_asic_reset(struct amdgpu_device *adev)
575{
576 /* original raven doesn't have full asic reset */
577 if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
578 !(adev->apu_flags & AMD_APU_IS_RAVEN2))
579 return 0;
580
581 switch (soc15_asic_reset_method(adev)) {
582 case AMD_RESET_METHOD_BACO:
583 return soc15_asic_baco_reset(adev);
584 case AMD_RESET_METHOD_MODE2:
585 return amdgpu_dpm_mode2_reset(adev);
586 default:
587 return soc15_asic_mode1_reset(adev);
588 }
589}
590
591static bool soc15_supports_baco(struct amdgpu_device *adev)
592{
593 switch (adev->asic_type) {
594 case CHIP_VEGA10:
595 case CHIP_VEGA12:
596 case CHIP_ARCTURUS:
597 return amdgpu_dpm_is_baco_supported(adev);
598 case CHIP_VEGA20:
599 if (adev->psp.sos_fw_version >= 0x80067)
600 return amdgpu_dpm_is_baco_supported(adev);
601 return false;
602 default:
603 return false;
604 }
605}
606
607/*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
608 u32 cntl_reg, u32 status_reg)
609{
610 return 0;
611}*/
612
613static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
614{
615 /*int r;
616
617 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
618 if (r)
619 return r;
620
621 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
622 */
623 return 0;
624}
625
626static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
627{
628 /* todo */
629
630 return 0;
631}
632
633static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
634{
635 if (pci_is_root_bus(adev->pdev->bus))
636 return;
637
638 if (amdgpu_pcie_gen2 == 0)
639 return;
640
641 if (adev->flags & AMD_IS_APU)
642 return;
643
644 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
645 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
646 return;
647
648 /* todo */
649}
650
651static void soc15_program_aspm(struct amdgpu_device *adev)
652{
653
654 if (amdgpu_aspm == 0)
655 return;
656
657 /* todo */
658}
659
660static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
661 bool enable)
662{
663 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
664 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
665}
666
667static const struct amdgpu_ip_block_version vega10_common_ip_block =
668{
669 .type = AMD_IP_BLOCK_TYPE_COMMON,
670 .major = 2,
671 .minor = 0,
672 .rev = 0,
673 .funcs = &soc15_common_ip_funcs,
674};
675
676static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
677{
678 return adev->nbio.funcs->get_rev_id(adev);
679}
680
681static void soc15_reg_base_init(struct amdgpu_device *adev)
682{
683 int r;
684
685 /* Set IP register base before any HW register access */
686 switch (adev->asic_type) {
687 case CHIP_VEGA10:
688 case CHIP_VEGA12:
689 case CHIP_RAVEN:
690 vega10_reg_base_init(adev);
691 break;
692 case CHIP_RENOIR:
693 /* It's safe to do ip discovery here for Renior,
694 * it doesn't support SRIOV. */
695 if (amdgpu_discovery) {
696 r = amdgpu_discovery_reg_base_init(adev);
697 if (r == 0)
698 break;
699 DRM_WARN("failed to init reg base from ip discovery table, "
700 "fallback to legacy init method\n");
701 }
702 vega10_reg_base_init(adev);
703 break;
704 case CHIP_VEGA20:
705 vega20_reg_base_init(adev);
706 break;
707 case CHIP_ARCTURUS:
708 arct_reg_base_init(adev);
709 break;
710 default:
711 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type);
712 break;
713 }
714}
715
716void soc15_set_virt_ops(struct amdgpu_device *adev)
717{
718 adev->virt.ops = &xgpu_ai_virt_ops;
719
720 /* init soc15 reg base early enough so we can
721 * request request full access for sriov before
722 * set_ip_blocks. */
723 soc15_reg_base_init(adev);
724}
725
726int soc15_set_ip_blocks(struct amdgpu_device *adev)
727{
728 /* for bare metal case */
729 if (!amdgpu_sriov_vf(adev))
730 soc15_reg_base_init(adev);
731
732 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
733 adev->gmc.xgmi.supported = true;
734
735 if (adev->flags & AMD_IS_APU) {
736 adev->nbio.funcs = &nbio_v7_0_funcs;
737 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
738 } else if (adev->asic_type == CHIP_VEGA20 ||
739 adev->asic_type == CHIP_ARCTURUS) {
740 adev->nbio.funcs = &nbio_v7_4_funcs;
741 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
742 } else {
743 adev->nbio.funcs = &nbio_v6_1_funcs;
744 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
745 }
746
747 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
748 adev->df.funcs = &df_v3_6_funcs;
749 else
750 adev->df.funcs = &df_v1_7_funcs;
751
752 adev->rev_id = soc15_get_rev_id(adev);
753
754 switch (adev->asic_type) {
755 case CHIP_VEGA10:
756 case CHIP_VEGA12:
757 case CHIP_VEGA20:
758 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
759 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
760
761 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
762 if (amdgpu_sriov_vf(adev)) {
763 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
764 if (adev->asic_type == CHIP_VEGA20)
765 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
766 else
767 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
768 }
769 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
770 } else {
771 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
772 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
773 if (adev->asic_type == CHIP_VEGA20)
774 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
775 else
776 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
777 }
778 }
779 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
780 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
781 if (is_support_sw_smu(adev)) {
782 if (!amdgpu_sriov_vf(adev))
783 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
784 } else {
785 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
786 }
787 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
788 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
789#if defined(CONFIG_DRM_AMD_DC)
790 else if (amdgpu_device_has_dc_support(adev))
791 amdgpu_device_ip_block_add(adev, &dm_ip_block);
792#endif
793 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
794 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
795 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
796 }
797 break;
798 case CHIP_RAVEN:
799 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
800 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
801 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
802 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
803 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
804 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
805 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
806 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
807 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
808 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
809#if defined(CONFIG_DRM_AMD_DC)
810 else if (amdgpu_device_has_dc_support(adev))
811 amdgpu_device_ip_block_add(adev, &dm_ip_block);
812#endif
813 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
814 break;
815 case CHIP_ARCTURUS:
816 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
817 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
818
819 if (amdgpu_sriov_vf(adev)) {
820 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
821 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
822 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
823 } else {
824 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
825 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
826 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
827 }
828
829 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
830 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
831 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
832 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
833 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
834
835 if (amdgpu_sriov_vf(adev)) {
836 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
837 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
838 } else {
839 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
840 }
841 if (!amdgpu_sriov_vf(adev))
842 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
843 break;
844 case CHIP_RENOIR:
845 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
846 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
847 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
848 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
849 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
850 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
851 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
852 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
853 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
854 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
855#if defined(CONFIG_DRM_AMD_DC)
856 else if (amdgpu_device_has_dc_support(adev))
857 amdgpu_device_ip_block_add(adev, &dm_ip_block);
858#endif
859 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
860 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
861 break;
862 default:
863 return -EINVAL;
864 }
865
866 return 0;
867}
868
869static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
870{
871 adev->nbio.funcs->hdp_flush(adev, ring);
872}
873
874static void soc15_invalidate_hdp(struct amdgpu_device *adev,
875 struct amdgpu_ring *ring)
876{
877 if (!ring || !ring->funcs->emit_wreg)
878 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
879 else
880 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
881 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
882}
883
884static bool soc15_need_full_reset(struct amdgpu_device *adev)
885{
886 /* change this when we implement soft reset */
887 return true;
888}
889
890static void vega20_reset_hdp_ras_error_count(struct amdgpu_device *adev)
891{
892 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
893 return;
894 /*read back hdp ras counter to reset it to 0 */
895 RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
896}
897
898static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
899 uint64_t *count1)
900{
901 uint32_t perfctr = 0;
902 uint64_t cnt0_of, cnt1_of;
903 int tmp;
904
905 /* This reports 0 on APUs, so return to avoid writing/reading registers
906 * that may or may not be different from their GPU counterparts
907 */
908 if (adev->flags & AMD_IS_APU)
909 return;
910
911 /* Set the 2 events that we wish to watch, defined above */
912 /* Reg 40 is # received msgs */
913 /* Reg 104 is # of posted requests sent */
914 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
915 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
916
917 /* Write to enable desired perf counters */
918 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
919 /* Zero out and enable the perf counters
920 * Write 0x5:
921 * Bit 0 = Start all counters(1)
922 * Bit 2 = Global counter reset enable(1)
923 */
924 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
925
926 msleep(1000);
927
928 /* Load the shadow and disable the perf counters
929 * Write 0x2:
930 * Bit 0 = Stop counters(0)
931 * Bit 1 = Load the shadow counters(1)
932 */
933 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
934
935 /* Read register values to get any >32bit overflow */
936 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
937 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
938 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
939
940 /* Get the values and add the overflow */
941 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
942 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
943}
944
945static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
946 uint64_t *count1)
947{
948 uint32_t perfctr = 0;
949 uint64_t cnt0_of, cnt1_of;
950 int tmp;
951
952 /* This reports 0 on APUs, so return to avoid writing/reading registers
953 * that may or may not be different from their GPU counterparts
954 */
955 if (adev->flags & AMD_IS_APU)
956 return;
957
958 /* Set the 2 events that we wish to watch, defined above */
959 /* Reg 40 is # received msgs */
960 /* Reg 108 is # of posted requests sent on VG20 */
961 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
962 EVENT0_SEL, 40);
963 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
964 EVENT1_SEL, 108);
965
966 /* Write to enable desired perf counters */
967 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
968 /* Zero out and enable the perf counters
969 * Write 0x5:
970 * Bit 0 = Start all counters(1)
971 * Bit 2 = Global counter reset enable(1)
972 */
973 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
974
975 msleep(1000);
976
977 /* Load the shadow and disable the perf counters
978 * Write 0x2:
979 * Bit 0 = Stop counters(0)
980 * Bit 1 = Load the shadow counters(1)
981 */
982 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
983
984 /* Read register values to get any >32bit overflow */
985 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
986 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
987 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
988
989 /* Get the values and add the overflow */
990 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
991 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
992}
993
994static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
995{
996 u32 sol_reg;
997
998 /* Just return false for soc15 GPUs. Reset does not seem to
999 * be necessary.
1000 */
1001 if (!amdgpu_passthrough(adev))
1002 return false;
1003
1004 if (adev->flags & AMD_IS_APU)
1005 return false;
1006
1007 /* Check sOS sign of life register to confirm sys driver and sOS
1008 * are already been loaded.
1009 */
1010 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
1011 if (sol_reg)
1012 return true;
1013
1014 return false;
1015}
1016
1017static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
1018{
1019 uint64_t nak_r, nak_g;
1020
1021 /* Get the number of NAKs received and generated */
1022 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
1023 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
1024
1025 /* Add the total number of NAKs, i.e the number of replays */
1026 return (nak_r + nak_g);
1027}
1028
1029static const struct amdgpu_asic_funcs soc15_asic_funcs =
1030{
1031 .read_disabled_bios = &soc15_read_disabled_bios,
1032 .read_bios_from_rom = &soc15_read_bios_from_rom,
1033 .read_register = &soc15_read_register,
1034 .reset = &soc15_asic_reset,
1035 .reset_method = &soc15_asic_reset_method,
1036 .set_vga_state = &soc15_vga_set_state,
1037 .get_xclk = &soc15_get_xclk,
1038 .set_uvd_clocks = &soc15_set_uvd_clocks,
1039 .set_vce_clocks = &soc15_set_vce_clocks,
1040 .get_config_memsize = &soc15_get_config_memsize,
1041 .flush_hdp = &soc15_flush_hdp,
1042 .invalidate_hdp = &soc15_invalidate_hdp,
1043 .need_full_reset = &soc15_need_full_reset,
1044 .init_doorbell_index = &vega10_doorbell_index_init,
1045 .get_pcie_usage = &soc15_get_pcie_usage,
1046 .need_reset_on_init = &soc15_need_reset_on_init,
1047 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1048 .supports_baco = &soc15_supports_baco,
1049};
1050
1051static const struct amdgpu_asic_funcs vega20_asic_funcs =
1052{
1053 .read_disabled_bios = &soc15_read_disabled_bios,
1054 .read_bios_from_rom = &soc15_read_bios_from_rom,
1055 .read_register = &soc15_read_register,
1056 .reset = &soc15_asic_reset,
1057 .reset_method = &soc15_asic_reset_method,
1058 .set_vga_state = &soc15_vga_set_state,
1059 .get_xclk = &soc15_get_xclk,
1060 .set_uvd_clocks = &soc15_set_uvd_clocks,
1061 .set_vce_clocks = &soc15_set_vce_clocks,
1062 .get_config_memsize = &soc15_get_config_memsize,
1063 .flush_hdp = &soc15_flush_hdp,
1064 .invalidate_hdp = &soc15_invalidate_hdp,
1065 .reset_hdp_ras_error_count = &vega20_reset_hdp_ras_error_count,
1066 .need_full_reset = &soc15_need_full_reset,
1067 .init_doorbell_index = &vega20_doorbell_index_init,
1068 .get_pcie_usage = &vega20_get_pcie_usage,
1069 .need_reset_on_init = &soc15_need_reset_on_init,
1070 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1071 .supports_baco = &soc15_supports_baco,
1072};
1073
1074static int soc15_common_early_init(void *handle)
1075{
1076#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
1077 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1078
1079 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1080 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1081 adev->smc_rreg = NULL;
1082 adev->smc_wreg = NULL;
1083 adev->pcie_rreg = &soc15_pcie_rreg;
1084 adev->pcie_wreg = &soc15_pcie_wreg;
1085 adev->pcie_rreg64 = &soc15_pcie_rreg64;
1086 adev->pcie_wreg64 = &soc15_pcie_wreg64;
1087 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
1088 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
1089 adev->didt_rreg = &soc15_didt_rreg;
1090 adev->didt_wreg = &soc15_didt_wreg;
1091 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
1092 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
1093 adev->se_cac_rreg = &soc15_se_cac_rreg;
1094 adev->se_cac_wreg = &soc15_se_cac_wreg;
1095
1096
1097 adev->external_rev_id = 0xFF;
1098 switch (adev->asic_type) {
1099 case CHIP_VEGA10:
1100 adev->asic_funcs = &soc15_asic_funcs;
1101 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1102 AMD_CG_SUPPORT_GFX_MGLS |
1103 AMD_CG_SUPPORT_GFX_RLC_LS |
1104 AMD_CG_SUPPORT_GFX_CP_LS |
1105 AMD_CG_SUPPORT_GFX_3D_CGCG |
1106 AMD_CG_SUPPORT_GFX_3D_CGLS |
1107 AMD_CG_SUPPORT_GFX_CGCG |
1108 AMD_CG_SUPPORT_GFX_CGLS |
1109 AMD_CG_SUPPORT_BIF_MGCG |
1110 AMD_CG_SUPPORT_BIF_LS |
1111 AMD_CG_SUPPORT_HDP_LS |
1112 AMD_CG_SUPPORT_DRM_MGCG |
1113 AMD_CG_SUPPORT_DRM_LS |
1114 AMD_CG_SUPPORT_ROM_MGCG |
1115 AMD_CG_SUPPORT_DF_MGCG |
1116 AMD_CG_SUPPORT_SDMA_MGCG |
1117 AMD_CG_SUPPORT_SDMA_LS |
1118 AMD_CG_SUPPORT_MC_MGCG |
1119 AMD_CG_SUPPORT_MC_LS;
1120 adev->pg_flags = 0;
1121 adev->external_rev_id = 0x1;
1122 break;
1123 case CHIP_VEGA12:
1124 adev->asic_funcs = &soc15_asic_funcs;
1125 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1126 AMD_CG_SUPPORT_GFX_MGLS |
1127 AMD_CG_SUPPORT_GFX_CGCG |
1128 AMD_CG_SUPPORT_GFX_CGLS |
1129 AMD_CG_SUPPORT_GFX_3D_CGCG |
1130 AMD_CG_SUPPORT_GFX_3D_CGLS |
1131 AMD_CG_SUPPORT_GFX_CP_LS |
1132 AMD_CG_SUPPORT_MC_LS |
1133 AMD_CG_SUPPORT_MC_MGCG |
1134 AMD_CG_SUPPORT_SDMA_MGCG |
1135 AMD_CG_SUPPORT_SDMA_LS |
1136 AMD_CG_SUPPORT_BIF_MGCG |
1137 AMD_CG_SUPPORT_BIF_LS |
1138 AMD_CG_SUPPORT_HDP_MGCG |
1139 AMD_CG_SUPPORT_HDP_LS |
1140 AMD_CG_SUPPORT_ROM_MGCG |
1141 AMD_CG_SUPPORT_VCE_MGCG |
1142 AMD_CG_SUPPORT_UVD_MGCG;
1143 adev->pg_flags = 0;
1144 adev->external_rev_id = adev->rev_id + 0x14;
1145 break;
1146 case CHIP_VEGA20:
1147 adev->asic_funcs = &vega20_asic_funcs;
1148 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1149 AMD_CG_SUPPORT_GFX_MGLS |
1150 AMD_CG_SUPPORT_GFX_CGCG |
1151 AMD_CG_SUPPORT_GFX_CGLS |
1152 AMD_CG_SUPPORT_GFX_3D_CGCG |
1153 AMD_CG_SUPPORT_GFX_3D_CGLS |
1154 AMD_CG_SUPPORT_GFX_CP_LS |
1155 AMD_CG_SUPPORT_MC_LS |
1156 AMD_CG_SUPPORT_MC_MGCG |
1157 AMD_CG_SUPPORT_SDMA_MGCG |
1158 AMD_CG_SUPPORT_SDMA_LS |
1159 AMD_CG_SUPPORT_BIF_MGCG |
1160 AMD_CG_SUPPORT_BIF_LS |
1161 AMD_CG_SUPPORT_HDP_MGCG |
1162 AMD_CG_SUPPORT_HDP_LS |
1163 AMD_CG_SUPPORT_ROM_MGCG |
1164 AMD_CG_SUPPORT_VCE_MGCG |
1165 AMD_CG_SUPPORT_UVD_MGCG;
1166 adev->pg_flags = 0;
1167 adev->external_rev_id = adev->rev_id + 0x28;
1168 break;
1169 case CHIP_RAVEN:
1170 adev->asic_funcs = &soc15_asic_funcs;
1171 if (adev->pdev->device == 0x15dd)
1172 adev->apu_flags |= AMD_APU_IS_RAVEN;
1173 if (adev->pdev->device == 0x15d8)
1174 adev->apu_flags |= AMD_APU_IS_PICASSO;
1175 if (adev->rev_id >= 0x8)
1176 adev->apu_flags |= AMD_APU_IS_RAVEN2;
1177
1178 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1179 adev->external_rev_id = adev->rev_id + 0x79;
1180 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1181 adev->external_rev_id = adev->rev_id + 0x41;
1182 else if (adev->rev_id == 1)
1183 adev->external_rev_id = adev->rev_id + 0x20;
1184 else
1185 adev->external_rev_id = adev->rev_id + 0x01;
1186
1187 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1188 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1189 AMD_CG_SUPPORT_GFX_MGLS |
1190 AMD_CG_SUPPORT_GFX_CP_LS |
1191 AMD_CG_SUPPORT_GFX_3D_CGCG |
1192 AMD_CG_SUPPORT_GFX_3D_CGLS |
1193 AMD_CG_SUPPORT_GFX_CGCG |
1194 AMD_CG_SUPPORT_GFX_CGLS |
1195 AMD_CG_SUPPORT_BIF_LS |
1196 AMD_CG_SUPPORT_HDP_LS |
1197 AMD_CG_SUPPORT_ROM_MGCG |
1198 AMD_CG_SUPPORT_MC_MGCG |
1199 AMD_CG_SUPPORT_MC_LS |
1200 AMD_CG_SUPPORT_SDMA_MGCG |
1201 AMD_CG_SUPPORT_SDMA_LS |
1202 AMD_CG_SUPPORT_VCN_MGCG;
1203
1204 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1205 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
1206 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1207 AMD_CG_SUPPORT_GFX_MGLS |
1208 AMD_CG_SUPPORT_GFX_CP_LS |
1209 AMD_CG_SUPPORT_GFX_3D_CGCG |
1210 AMD_CG_SUPPORT_GFX_3D_CGLS |
1211 AMD_CG_SUPPORT_GFX_CGCG |
1212 AMD_CG_SUPPORT_GFX_CGLS |
1213 AMD_CG_SUPPORT_BIF_LS |
1214 AMD_CG_SUPPORT_HDP_LS |
1215 AMD_CG_SUPPORT_ROM_MGCG |
1216 AMD_CG_SUPPORT_MC_MGCG |
1217 AMD_CG_SUPPORT_MC_LS |
1218 AMD_CG_SUPPORT_SDMA_MGCG |
1219 AMD_CG_SUPPORT_SDMA_LS;
1220
1221 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1222 AMD_PG_SUPPORT_MMHUB |
1223 AMD_PG_SUPPORT_VCN |
1224 AMD_PG_SUPPORT_VCN_DPG;
1225 } else {
1226 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1227 AMD_CG_SUPPORT_GFX_MGLS |
1228 AMD_CG_SUPPORT_GFX_RLC_LS |
1229 AMD_CG_SUPPORT_GFX_CP_LS |
1230 AMD_CG_SUPPORT_GFX_3D_CGCG |
1231 AMD_CG_SUPPORT_GFX_3D_CGLS |
1232 AMD_CG_SUPPORT_GFX_CGCG |
1233 AMD_CG_SUPPORT_GFX_CGLS |
1234 AMD_CG_SUPPORT_BIF_MGCG |
1235 AMD_CG_SUPPORT_BIF_LS |
1236 AMD_CG_SUPPORT_HDP_MGCG |
1237 AMD_CG_SUPPORT_HDP_LS |
1238 AMD_CG_SUPPORT_DRM_MGCG |
1239 AMD_CG_SUPPORT_DRM_LS |
1240 AMD_CG_SUPPORT_ROM_MGCG |
1241 AMD_CG_SUPPORT_MC_MGCG |
1242 AMD_CG_SUPPORT_MC_LS |
1243 AMD_CG_SUPPORT_SDMA_MGCG |
1244 AMD_CG_SUPPORT_SDMA_LS |
1245 AMD_CG_SUPPORT_VCN_MGCG;
1246
1247 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1248 }
1249 break;
1250 case CHIP_ARCTURUS:
1251 adev->asic_funcs = &vega20_asic_funcs;
1252 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1253 AMD_CG_SUPPORT_GFX_MGLS |
1254 AMD_CG_SUPPORT_GFX_CGCG |
1255 AMD_CG_SUPPORT_GFX_CGLS |
1256 AMD_CG_SUPPORT_GFX_CP_LS |
1257 AMD_CG_SUPPORT_HDP_MGCG |
1258 AMD_CG_SUPPORT_HDP_LS |
1259 AMD_CG_SUPPORT_SDMA_MGCG |
1260 AMD_CG_SUPPORT_SDMA_LS |
1261 AMD_CG_SUPPORT_MC_MGCG |
1262 AMD_CG_SUPPORT_MC_LS |
1263 AMD_CG_SUPPORT_IH_CG |
1264 AMD_CG_SUPPORT_VCN_MGCG |
1265 AMD_CG_SUPPORT_JPEG_MGCG;
1266 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
1267 adev->external_rev_id = adev->rev_id + 0x32;
1268 break;
1269 case CHIP_RENOIR:
1270 adev->asic_funcs = &soc15_asic_funcs;
1271 adev->apu_flags |= AMD_APU_IS_RENOIR;
1272 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1273 AMD_CG_SUPPORT_GFX_MGLS |
1274 AMD_CG_SUPPORT_GFX_3D_CGCG |
1275 AMD_CG_SUPPORT_GFX_3D_CGLS |
1276 AMD_CG_SUPPORT_GFX_CGCG |
1277 AMD_CG_SUPPORT_GFX_CGLS |
1278 AMD_CG_SUPPORT_GFX_CP_LS |
1279 AMD_CG_SUPPORT_MC_MGCG |
1280 AMD_CG_SUPPORT_MC_LS |
1281 AMD_CG_SUPPORT_SDMA_MGCG |
1282 AMD_CG_SUPPORT_SDMA_LS |
1283 AMD_CG_SUPPORT_BIF_LS |
1284 AMD_CG_SUPPORT_HDP_LS |
1285 AMD_CG_SUPPORT_ROM_MGCG |
1286 AMD_CG_SUPPORT_VCN_MGCG |
1287 AMD_CG_SUPPORT_JPEG_MGCG |
1288 AMD_CG_SUPPORT_IH_CG |
1289 AMD_CG_SUPPORT_ATHUB_LS |
1290 AMD_CG_SUPPORT_ATHUB_MGCG |
1291 AMD_CG_SUPPORT_DF_MGCG;
1292 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1293 AMD_PG_SUPPORT_VCN |
1294 AMD_PG_SUPPORT_JPEG |
1295 AMD_PG_SUPPORT_VCN_DPG;
1296 adev->external_rev_id = adev->rev_id + 0x91;
1297 break;
1298 default:
1299 /* FIXME: not supported yet */
1300 return -EINVAL;
1301 }
1302
1303 if (amdgpu_sriov_vf(adev)) {
1304 amdgpu_virt_init_setting(adev);
1305 xgpu_ai_mailbox_set_irq_funcs(adev);
1306 }
1307
1308 return 0;
1309}
1310
1311static int soc15_common_late_init(void *handle)
1312{
1313 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1314 int r = 0;
1315
1316 if (amdgpu_sriov_vf(adev))
1317 xgpu_ai_mailbox_get_irq(adev);
1318
1319 if (adev->asic_funcs &&
1320 adev->asic_funcs->reset_hdp_ras_error_count)
1321 adev->asic_funcs->reset_hdp_ras_error_count(adev);
1322
1323 if (adev->nbio.funcs->ras_late_init)
1324 r = adev->nbio.funcs->ras_late_init(adev);
1325
1326 return r;
1327}
1328
1329static int soc15_common_sw_init(void *handle)
1330{
1331 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1332
1333 if (amdgpu_sriov_vf(adev))
1334 xgpu_ai_mailbox_add_irq_id(adev);
1335
1336 adev->df.funcs->sw_init(adev);
1337
1338 return 0;
1339}
1340
1341static int soc15_common_sw_fini(void *handle)
1342{
1343 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1344
1345 amdgpu_nbio_ras_fini(adev);
1346 adev->df.funcs->sw_fini(adev);
1347 return 0;
1348}
1349
1350static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1351{
1352 int i;
1353 struct amdgpu_ring *ring;
1354
1355 /* sdma/ih doorbell range are programed by hypervisor */
1356 if (!amdgpu_sriov_vf(adev)) {
1357 for (i = 0; i < adev->sdma.num_instances; i++) {
1358 ring = &adev->sdma.instance[i].ring;
1359 adev->nbio.funcs->sdma_doorbell_range(adev, i,
1360 ring->use_doorbell, ring->doorbell_index,
1361 adev->doorbell_index.sdma_doorbell_range);
1362 }
1363
1364 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1365 adev->irq.ih.doorbell_index);
1366 }
1367}
1368
1369static int soc15_common_hw_init(void *handle)
1370{
1371 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1372
1373 /* enable pcie gen2/3 link */
1374 soc15_pcie_gen3_enable(adev);
1375 /* enable aspm */
1376 soc15_program_aspm(adev);
1377 /* setup nbio registers */
1378 adev->nbio.funcs->init_registers(adev);
1379 /* remap HDP registers to a hole in mmio space,
1380 * for the purpose of expose those registers
1381 * to process space
1382 */
1383 if (adev->nbio.funcs->remap_hdp_registers)
1384 adev->nbio.funcs->remap_hdp_registers(adev);
1385
1386 /* enable the doorbell aperture */
1387 soc15_enable_doorbell_aperture(adev, true);
1388 /* HW doorbell routing policy: doorbell writing not
1389 * in SDMA/IH/MM/ACV range will be routed to CP. So
1390 * we need to init SDMA/IH/MM/ACV doorbell range prior
1391 * to CP ip block init and ring test.
1392 */
1393 soc15_doorbell_range_init(adev);
1394
1395 return 0;
1396}
1397
1398static int soc15_common_hw_fini(void *handle)
1399{
1400 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1401
1402 /* disable the doorbell aperture */
1403 soc15_enable_doorbell_aperture(adev, false);
1404 if (amdgpu_sriov_vf(adev))
1405 xgpu_ai_mailbox_put_irq(adev);
1406
1407 if (adev->nbio.ras_if &&
1408 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1409 if (adev->nbio.funcs->init_ras_controller_interrupt)
1410 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1411 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt)
1412 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1413 }
1414
1415 return 0;
1416}
1417
1418static int soc15_common_suspend(void *handle)
1419{
1420 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1421
1422 return soc15_common_hw_fini(adev);
1423}
1424
1425static int soc15_common_resume(void *handle)
1426{
1427 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1428
1429 return soc15_common_hw_init(adev);
1430}
1431
1432static bool soc15_common_is_idle(void *handle)
1433{
1434 return true;
1435}
1436
1437static int soc15_common_wait_for_idle(void *handle)
1438{
1439 return 0;
1440}
1441
1442static int soc15_common_soft_reset(void *handle)
1443{
1444 return 0;
1445}
1446
1447static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1448{
1449 uint32_t def, data;
1450
1451 if (adev->asic_type == CHIP_VEGA20 ||
1452 adev->asic_type == CHIP_ARCTURUS) {
1453 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
1454
1455 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1456 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1457 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1458 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1459 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1460 else
1461 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1462 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1463 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1464 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
1465
1466 if (def != data)
1467 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1468 } else {
1469 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1470
1471 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1472 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1473 else
1474 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1475
1476 if (def != data)
1477 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1478 }
1479}
1480
1481static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1482{
1483 uint32_t def, data;
1484
1485 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1486
1487 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1488 data &= ~(0x01000000 |
1489 0x02000000 |
1490 0x04000000 |
1491 0x08000000 |
1492 0x10000000 |
1493 0x20000000 |
1494 0x40000000 |
1495 0x80000000);
1496 else
1497 data |= (0x01000000 |
1498 0x02000000 |
1499 0x04000000 |
1500 0x08000000 |
1501 0x10000000 |
1502 0x20000000 |
1503 0x40000000 |
1504 0x80000000);
1505
1506 if (def != data)
1507 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1508}
1509
1510static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1511{
1512 uint32_t def, data;
1513
1514 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1515
1516 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1517 data |= 1;
1518 else
1519 data &= ~1;
1520
1521 if (def != data)
1522 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1523}
1524
1525static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1526 bool enable)
1527{
1528 uint32_t def, data;
1529
1530 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1531
1532 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1533 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1534 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1535 else
1536 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1537 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1538
1539 if (def != data)
1540 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1541}
1542
1543static int soc15_common_set_clockgating_state(void *handle,
1544 enum amd_clockgating_state state)
1545{
1546 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1547
1548 if (amdgpu_sriov_vf(adev))
1549 return 0;
1550
1551 switch (adev->asic_type) {
1552 case CHIP_VEGA10:
1553 case CHIP_VEGA12:
1554 case CHIP_VEGA20:
1555 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1556 state == AMD_CG_STATE_GATE);
1557 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1558 state == AMD_CG_STATE_GATE);
1559 soc15_update_hdp_light_sleep(adev,
1560 state == AMD_CG_STATE_GATE);
1561 soc15_update_drm_clock_gating(adev,
1562 state == AMD_CG_STATE_GATE);
1563 soc15_update_drm_light_sleep(adev,
1564 state == AMD_CG_STATE_GATE);
1565 soc15_update_rom_medium_grain_clock_gating(adev,
1566 state == AMD_CG_STATE_GATE);
1567 adev->df.funcs->update_medium_grain_clock_gating(adev,
1568 state == AMD_CG_STATE_GATE);
1569 break;
1570 case CHIP_RAVEN:
1571 case CHIP_RENOIR:
1572 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1573 state == AMD_CG_STATE_GATE);
1574 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1575 state == AMD_CG_STATE_GATE);
1576 soc15_update_hdp_light_sleep(adev,
1577 state == AMD_CG_STATE_GATE);
1578 soc15_update_drm_clock_gating(adev,
1579 state == AMD_CG_STATE_GATE);
1580 soc15_update_drm_light_sleep(adev,
1581 state == AMD_CG_STATE_GATE);
1582 soc15_update_rom_medium_grain_clock_gating(adev,
1583 state == AMD_CG_STATE_GATE);
1584 break;
1585 case CHIP_ARCTURUS:
1586 soc15_update_hdp_light_sleep(adev,
1587 state == AMD_CG_STATE_GATE);
1588 break;
1589 default:
1590 break;
1591 }
1592 return 0;
1593}
1594
1595static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1596{
1597 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1598 int data;
1599
1600 if (amdgpu_sriov_vf(adev))
1601 *flags = 0;
1602
1603 adev->nbio.funcs->get_clockgating_state(adev, flags);
1604
1605 /* AMD_CG_SUPPORT_HDP_LS */
1606 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1607 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1608 *flags |= AMD_CG_SUPPORT_HDP_LS;
1609
1610 /* AMD_CG_SUPPORT_DRM_MGCG */
1611 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1612 if (!(data & 0x01000000))
1613 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1614
1615 /* AMD_CG_SUPPORT_DRM_LS */
1616 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1617 if (data & 0x1)
1618 *flags |= AMD_CG_SUPPORT_DRM_LS;
1619
1620 /* AMD_CG_SUPPORT_ROM_MGCG */
1621 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1622 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1623 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1624
1625 adev->df.funcs->get_clockgating_state(adev, flags);
1626}
1627
1628static int soc15_common_set_powergating_state(void *handle,
1629 enum amd_powergating_state state)
1630{
1631 /* todo */
1632 return 0;
1633}
1634
1635const struct amd_ip_funcs soc15_common_ip_funcs = {
1636 .name = "soc15_common",
1637 .early_init = soc15_common_early_init,
1638 .late_init = soc15_common_late_init,
1639 .sw_init = soc15_common_sw_init,
1640 .sw_fini = soc15_common_sw_fini,
1641 .hw_init = soc15_common_hw_init,
1642 .hw_fini = soc15_common_hw_fini,
1643 .suspend = soc15_common_suspend,
1644 .resume = soc15_common_resume,
1645 .is_idle = soc15_common_is_idle,
1646 .wait_for_idle = soc15_common_wait_for_idle,
1647 .soft_reset = soc15_common_soft_reset,
1648 .set_clockgating_state = soc15_common_set_clockgating_state,
1649 .set_powergating_state = soc15_common_set_powergating_state,
1650 .get_clockgating_state= soc15_common_get_clockgating_state,
1651};