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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/pci.h>
25
26#include "amdgpu.h"
27#include "amdgpu_ih.h"
28
29#include "oss/osssys_5_0_0_offset.h"
30#include "oss/osssys_5_0_0_sh_mask.h"
31
32#include "soc15_common.h"
33#include "navi10_ih.h"
34
35#define MAX_REARM_RETRY 10
36
37#define mmIH_CHICKEN_Sienna_Cichlid 0x018d
38#define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0
39
40static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
41
42/**
43 * navi10_ih_init_register_offset - Initialize register offset for ih rings
44 *
45 * @adev: amdgpu_device pointer
46 *
47 * Initialize register offset ih rings (NAVI10).
48 */
49static void navi10_ih_init_register_offset(struct amdgpu_device *adev)
50{
51 struct amdgpu_ih_regs *ih_regs;
52
53 if (adev->irq.ih.ring_size) {
54 ih_regs = &adev->irq.ih.ih_regs;
55 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
56 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);
57 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
59 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
60 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);
61 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
62 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);
63 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
64 }
65
66 if (adev->irq.ih1.ring_size) {
67 ih_regs = &adev->irq.ih1.ih_regs;
68 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);
69 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);
70 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
71 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
72 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
73 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);
74 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
75 }
76
77 if (adev->irq.ih2.ring_size) {
78 ih_regs = &adev->irq.ih2.ih_regs;
79 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);
80 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);
81 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
82 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
83 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
84 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);
85 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2;
86 }
87}
88
89/**
90 * force_update_wptr_for_self_int - Force update the wptr for self interrupt
91 *
92 * @adev: amdgpu_device pointer
93 * @threshold: threshold to trigger the wptr reporting
94 * @timeout: timeout to trigger the wptr reporting
95 * @enabled: Enable/disable timeout flush mechanism
96 *
97 * threshold input range: 0 ~ 15, default 0,
98 * real_threshold = 2^threshold
99 * timeout input range: 0 ~ 20, default 8,
100 * real_timeout = (2^timeout) * 1024 / (socclk_freq)
101 *
102 * Force update wptr for self interrupt ( >= SIENNA_CICHLID).
103 */
104static void
105force_update_wptr_for_self_int(struct amdgpu_device *adev,
106 u32 threshold, u32 timeout, bool enabled)
107{
108 u32 ih_cntl, ih_rb_cntl;
109
110 if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) < IP_VERSION(5, 0, 3))
111 return;
112
113 ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2);
114 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
115
116 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,
117 SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout);
118 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,
119 SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled);
120 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
121 RB_USED_INT_THRESHOLD, threshold);
122
123 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
124 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl))
125 return;
126 } else {
127 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
128 }
129
130 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
132 RB_USED_INT_THRESHOLD, threshold);
133 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
134 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, ih_rb_cntl))
135 return;
136 } else {
137 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
138 }
139
140 WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
141}
142
143/**
144 * navi10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer
145 *
146 * @adev: amdgpu_device pointer
147 * @ih: amdgpu_ih_ring pointet
148 * @enable: true - enable the interrupts, false - disable the interrupts
149 *
150 * Toggle the interrupt ring buffer (NAVI10)
151 */
152static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
153 struct amdgpu_ih_ring *ih,
154 bool enable)
155{
156 struct amdgpu_ih_regs *ih_regs;
157 uint32_t tmp;
158
159 ih_regs = &ih->ih_regs;
160
161 tmp = RREG32(ih_regs->ih_rb_cntl);
162 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
163 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);
164 /* enable_intr field is only valid in ring0 */
165 if (ih == &adev->irq.ih)
166 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
167
168 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
169 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
170 return -ETIMEDOUT;
171 } else {
172 WREG32(ih_regs->ih_rb_cntl, tmp);
173 }
174
175 if (enable) {
176 ih->enabled = true;
177 } else {
178 /* set rptr, wptr to 0 */
179 WREG32(ih_regs->ih_rb_rptr, 0);
180 WREG32(ih_regs->ih_rb_wptr, 0);
181 ih->enabled = false;
182 ih->rptr = 0;
183 }
184
185 return 0;
186}
187
188/**
189 * navi10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers
190 *
191 * @adev: amdgpu_device pointer
192 * @enable: enable or disable interrupt ring buffers
193 *
194 * Toggle all the available interrupt ring buffers (NAVI10).
195 */
196static int navi10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)
197{
198 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
199 int i;
200 int r;
201
202 for (i = 0; i < ARRAY_SIZE(ih); i++) {
203 if (ih[i]->ring_size) {
204 r = navi10_ih_toggle_ring_interrupts(adev, ih[i], enable);
205 if (r)
206 return r;
207 }
208 }
209
210 return 0;
211}
212
213static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
214{
215 int rb_bufsz = order_base_2(ih->ring_size / 4);
216
217 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
218 MC_SPACE, ih->use_bus_addr ? 1 : 4);
219 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
220 WPTR_OVERFLOW_CLEAR, 1);
221 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
222 WPTR_OVERFLOW_ENABLE, 1);
223 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
224 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
225 * value is written to memory
226 */
227 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
228 WPTR_WRITEBACK_ENABLE, 1);
229 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
230 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
231 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
232
233 return ih_rb_cntl;
234}
235
236static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
237{
238 u32 ih_doorbell_rtpr = 0;
239
240 if (ih->use_doorbell) {
241 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
242 IH_DOORBELL_RPTR, OFFSET,
243 ih->doorbell_index);
244 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
245 IH_DOORBELL_RPTR,
246 ENABLE, 1);
247 } else {
248 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
249 IH_DOORBELL_RPTR,
250 ENABLE, 0);
251 }
252 return ih_doorbell_rtpr;
253}
254
255/**
256 * navi10_ih_enable_ring - enable an ih ring buffer
257 *
258 * @adev: amdgpu_device pointer
259 * @ih: amdgpu_ih_ring pointer
260 *
261 * Enable an ih ring buffer (NAVI10)
262 */
263static int navi10_ih_enable_ring(struct amdgpu_device *adev,
264 struct amdgpu_ih_ring *ih)
265{
266 struct amdgpu_ih_regs *ih_regs;
267 uint32_t tmp;
268
269 ih_regs = &ih->ih_regs;
270
271 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
272 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
273 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
274
275 tmp = RREG32(ih_regs->ih_rb_cntl);
276 tmp = navi10_ih_rb_cntl(ih, tmp);
277 if (ih == &adev->irq.ih)
278 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
279 if (ih == &adev->irq.ih1)
280 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
281
282 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
283 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
284 DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
285 return -ETIMEDOUT;
286 }
287 } else {
288 WREG32(ih_regs->ih_rb_cntl, tmp);
289 }
290
291 if (ih == &adev->irq.ih) {
292 /* set the ih ring 0 writeback address whether it's enabled or not */
293 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
294 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
295 }
296
297 /* set rptr, wptr to 0 */
298 WREG32(ih_regs->ih_rb_wptr, 0);
299 WREG32(ih_regs->ih_rb_rptr, 0);
300
301 WREG32(ih_regs->ih_doorbell_rptr, navi10_ih_doorbell_rptr(ih));
302
303 return 0;
304}
305
306/**
307 * navi10_ih_irq_init - init and enable the interrupt ring
308 *
309 * @adev: amdgpu_device pointer
310 *
311 * Allocate a ring buffer for the interrupt controller,
312 * enable the RLC, disable interrupts, enable the IH
313 * ring buffer and enable it (NAVI).
314 * Called at device load and reume.
315 * Returns 0 for success, errors for failure.
316 */
317static int navi10_ih_irq_init(struct amdgpu_device *adev)
318{
319 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
320 u32 ih_chicken;
321 int ret;
322 int i;
323
324 /* disable irqs */
325 ret = navi10_ih_toggle_interrupts(adev, false);
326 if (ret)
327 return ret;
328
329 adev->nbio.funcs->ih_control(adev);
330
331 if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) {
332 if (ih[0]->use_bus_addr) {
333 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) {
334 case IP_VERSION(5, 0, 3):
335 case IP_VERSION(5, 2, 0):
336 case IP_VERSION(5, 2, 1):
337 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid);
338 ih_chicken = REG_SET_FIELD(ih_chicken,
339 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
340 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken);
341 break;
342 default:
343 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
344 ih_chicken = REG_SET_FIELD(ih_chicken,
345 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
346 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
347 break;
348 }
349 }
350 }
351
352 for (i = 0; i < ARRAY_SIZE(ih); i++) {
353 if (ih[i]->ring_size) {
354 ret = navi10_ih_enable_ring(adev, ih[i]);
355 if (ret)
356 return ret;
357 }
358 }
359
360 /* update doorbell range for ih ring 0*/
361 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell,
362 ih[0]->doorbell_index);
363
364 pci_set_master(adev->pdev);
365
366 /* enable interrupts */
367 ret = navi10_ih_toggle_interrupts(adev, true);
368 if (ret)
369 return ret;
370 /* enable wptr force update for self int */
371 force_update_wptr_for_self_int(adev, 0, 8, true);
372
373 if (adev->irq.ih_soft.ring_size)
374 adev->irq.ih_soft.enabled = true;
375
376 return 0;
377}
378
379/**
380 * navi10_ih_irq_disable - disable interrupts
381 *
382 * @adev: amdgpu_device pointer
383 *
384 * Disable interrupts on the hw (NAVI10).
385 */
386static void navi10_ih_irq_disable(struct amdgpu_device *adev)
387{
388 force_update_wptr_for_self_int(adev, 0, 8, false);
389 navi10_ih_toggle_interrupts(adev, false);
390
391 /* Wait and acknowledge irq */
392 mdelay(1);
393}
394
395/**
396 * navi10_ih_get_wptr - get the IH ring buffer wptr
397 *
398 * @adev: amdgpu_device pointer
399 * @ih: IH ring buffer to fetch wptr
400 *
401 * Get the IH ring buffer wptr from either the register
402 * or the writeback memory buffer (NAVI10). Also check for
403 * ring buffer overflow and deal with it.
404 * Returns the value of the wptr.
405 */
406static u32 navi10_ih_get_wptr(struct amdgpu_device *adev,
407 struct amdgpu_ih_ring *ih)
408{
409 u32 wptr, tmp;
410 struct amdgpu_ih_regs *ih_regs;
411
412 if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) {
413 /* Only ring0 supports writeback. On other rings fall back
414 * to register-based code with overflow checking below.
415 * ih_soft ring doesn't have any backing hardware registers,
416 * update wptr and return.
417 */
418 wptr = le32_to_cpu(*ih->wptr_cpu);
419
420 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
421 goto out;
422 }
423
424 ih_regs = &ih->ih_regs;
425
426 /* Double check that the overflow wasn't already cleared. */
427 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
428 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
429 goto out;
430 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
431
432 /* When a ring buffer overflow happen start parsing interrupt
433 * from the last not overwritten vector (wptr + 32). Hopefully
434 * this should allow us to catch up.
435 */
436 tmp = (wptr + 32) & ih->ptr_mask;
437 dev_warn(adev->dev, "IH ring buffer overflow "
438 "(0x%08X, 0x%08X, 0x%08X)\n",
439 wptr, ih->rptr, tmp);
440 ih->rptr = tmp;
441
442 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
443 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
444 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
445
446 /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
447 * can be detected.
448 */
449 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
450 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
451out:
452 return (wptr & ih->ptr_mask);
453}
454
455/**
456 * navi10_ih_irq_rearm - rearm IRQ if lost
457 *
458 * @adev: amdgpu_device pointer
459 * @ih: IH ring to match
460 *
461 */
462static void navi10_ih_irq_rearm(struct amdgpu_device *adev,
463 struct amdgpu_ih_ring *ih)
464{
465 uint32_t v = 0;
466 uint32_t i = 0;
467 struct amdgpu_ih_regs *ih_regs;
468
469 ih_regs = &ih->ih_regs;
470
471 /* Rearm IRQ / re-write doorbell if doorbell write is lost */
472 for (i = 0; i < MAX_REARM_RETRY; i++) {
473 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
474 if ((v < ih->ring_size) && (v != ih->rptr))
475 WDOORBELL32(ih->doorbell_index, ih->rptr);
476 else
477 break;
478 }
479}
480
481/**
482 * navi10_ih_set_rptr - set the IH ring buffer rptr
483 *
484 * @adev: amdgpu_device pointer
485 *
486 * @ih: IH ring buffer to set rptr
487 * Set the IH ring buffer rptr.
488 */
489static void navi10_ih_set_rptr(struct amdgpu_device *adev,
490 struct amdgpu_ih_ring *ih)
491{
492 struct amdgpu_ih_regs *ih_regs;
493
494 if (ih == &adev->irq.ih_soft)
495 return;
496
497 if (ih->use_doorbell) {
498 /* XXX check if swapping is necessary on BE */
499 *ih->rptr_cpu = ih->rptr;
500 WDOORBELL32(ih->doorbell_index, ih->rptr);
501
502 if (amdgpu_sriov_vf(adev))
503 navi10_ih_irq_rearm(adev, ih);
504 } else {
505 ih_regs = &ih->ih_regs;
506 WREG32(ih_regs->ih_rb_rptr, ih->rptr);
507 }
508}
509
510/**
511 * navi10_ih_self_irq - dispatch work for ring 1 and 2
512 *
513 * @adev: amdgpu_device pointer
514 * @source: irq source
515 * @entry: IV with WPTR update
516 *
517 * Update the WPTR from the IV and schedule work to handle the entries.
518 */
519static int navi10_ih_self_irq(struct amdgpu_device *adev,
520 struct amdgpu_irq_src *source,
521 struct amdgpu_iv_entry *entry)
522{
523 switch (entry->ring_id) {
524 case 1:
525 schedule_work(&adev->irq.ih1_work);
526 break;
527 case 2:
528 schedule_work(&adev->irq.ih2_work);
529 break;
530 default: break;
531 }
532 return 0;
533}
534
535static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = {
536 .process = navi10_ih_self_irq,
537};
538
539static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev)
540{
541 adev->irq.self_irq.num_types = 0;
542 adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs;
543}
544
545static int navi10_ih_early_init(void *handle)
546{
547 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
548
549 navi10_ih_set_interrupt_funcs(adev);
550 navi10_ih_set_self_irq_funcs(adev);
551 return 0;
552}
553
554static int navi10_ih_sw_init(void *handle)
555{
556 int r;
557 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
558 bool use_bus_addr;
559
560 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,
561 &adev->irq.self_irq);
562
563 if (r)
564 return r;
565
566 /* use gpu virtual address for ih ring
567 * until ih_checken is programmed to allow
568 * use bus address for ih ring by psp bl */
569 if ((adev->flags & AMD_IS_APU) ||
570 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
571 use_bus_addr = false;
572 else
573 use_bus_addr = true;
574 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr);
575 if (r)
576 return r;
577
578 adev->irq.ih.use_doorbell = true;
579 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
580
581 adev->irq.ih1.ring_size = 0;
582 adev->irq.ih2.ring_size = 0;
583
584 /* initialize ih control registers offset */
585 navi10_ih_init_register_offset(adev);
586
587 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true);
588 if (r)
589 return r;
590
591 r = amdgpu_irq_init(adev);
592
593 return r;
594}
595
596static int navi10_ih_sw_fini(void *handle)
597{
598 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
599
600 amdgpu_irq_fini_sw(adev);
601
602 return 0;
603}
604
605static int navi10_ih_hw_init(void *handle)
606{
607 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
608
609 return navi10_ih_irq_init(adev);
610}
611
612static int navi10_ih_hw_fini(void *handle)
613{
614 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
615
616 navi10_ih_irq_disable(adev);
617
618 return 0;
619}
620
621static int navi10_ih_suspend(void *handle)
622{
623 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
624
625 return navi10_ih_hw_fini(adev);
626}
627
628static int navi10_ih_resume(void *handle)
629{
630 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
631
632 return navi10_ih_hw_init(adev);
633}
634
635static bool navi10_ih_is_idle(void *handle)
636{
637 /* todo */
638 return true;
639}
640
641static int navi10_ih_wait_for_idle(void *handle)
642{
643 /* todo */
644 return -ETIMEDOUT;
645}
646
647static int navi10_ih_soft_reset(void *handle)
648{
649 /* todo */
650 return 0;
651}
652
653static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev,
654 bool enable)
655{
656 uint32_t data, def, field_val;
657
658 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
659 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
660 field_val = enable ? 0 : 1;
661 data = REG_SET_FIELD(data, IH_CLK_CTRL,
662 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
663 data = REG_SET_FIELD(data, IH_CLK_CTRL,
664 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
665 data = REG_SET_FIELD(data, IH_CLK_CTRL,
666 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
667 data = REG_SET_FIELD(data, IH_CLK_CTRL,
668 DYN_CLK_SOFT_OVERRIDE, field_val);
669 data = REG_SET_FIELD(data, IH_CLK_CTRL,
670 REG_CLK_SOFT_OVERRIDE, field_val);
671 if (def != data)
672 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);
673 }
674}
675
676static int navi10_ih_set_clockgating_state(void *handle,
677 enum amd_clockgating_state state)
678{
679 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
680
681 navi10_ih_update_clockgating_state(adev,
682 state == AMD_CG_STATE_GATE);
683 return 0;
684}
685
686static int navi10_ih_set_powergating_state(void *handle,
687 enum amd_powergating_state state)
688{
689 return 0;
690}
691
692static void navi10_ih_get_clockgating_state(void *handle, u64 *flags)
693{
694 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
695
696 if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL))
697 *flags |= AMD_CG_SUPPORT_IH_CG;
698}
699
700static const struct amd_ip_funcs navi10_ih_ip_funcs = {
701 .name = "navi10_ih",
702 .early_init = navi10_ih_early_init,
703 .late_init = NULL,
704 .sw_init = navi10_ih_sw_init,
705 .sw_fini = navi10_ih_sw_fini,
706 .hw_init = navi10_ih_hw_init,
707 .hw_fini = navi10_ih_hw_fini,
708 .suspend = navi10_ih_suspend,
709 .resume = navi10_ih_resume,
710 .is_idle = navi10_ih_is_idle,
711 .wait_for_idle = navi10_ih_wait_for_idle,
712 .soft_reset = navi10_ih_soft_reset,
713 .set_clockgating_state = navi10_ih_set_clockgating_state,
714 .set_powergating_state = navi10_ih_set_powergating_state,
715 .get_clockgating_state = navi10_ih_get_clockgating_state,
716};
717
718static const struct amdgpu_ih_funcs navi10_ih_funcs = {
719 .get_wptr = navi10_ih_get_wptr,
720 .decode_iv = amdgpu_ih_decode_iv_helper,
721 .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper,
722 .set_rptr = navi10_ih_set_rptr
723};
724
725static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev)
726{
727 if (adev->irq.ih_funcs == NULL)
728 adev->irq.ih_funcs = &navi10_ih_funcs;
729}
730
731const struct amdgpu_ip_block_version navi10_ih_ip_block = {
732 .type = AMD_IP_BLOCK_TYPE_IH,
733 .major = 5,
734 .minor = 0,
735 .rev = 0,
736 .funcs = &navi10_ih_ip_funcs,
737};
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/pci.h>
25
26#include "amdgpu.h"
27#include "amdgpu_ih.h"
28
29#include "oss/osssys_5_0_0_offset.h"
30#include "oss/osssys_5_0_0_sh_mask.h"
31
32#include "soc15_common.h"
33#include "navi10_ih.h"
34
35#define MAX_REARM_RETRY 10
36
37#define mmIH_CHICKEN_Sienna_Cichlid 0x018d
38#define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0
39
40static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
41
42/**
43 * force_update_wptr_for_self_int - Force update the wptr for self interrupt
44 *
45 * @adev: amdgpu_device pointer
46 * @threshold: threshold to trigger the wptr reporting
47 * @timeout: timeout to trigger the wptr reporting
48 * @enabled: Enable/disable timeout flush mechanism
49 *
50 * threshold input range: 0 ~ 15, default 0,
51 * real_threshold = 2^threshold
52 * timeout input range: 0 ~ 20, default 8,
53 * real_timeout = (2^timeout) * 1024 / (socclk_freq)
54 *
55 * Force update wptr for self interrupt ( >= SIENNA_CICHLID).
56 */
57static void
58force_update_wptr_for_self_int(struct amdgpu_device *adev,
59 u32 threshold, u32 timeout, bool enabled)
60{
61 u32 ih_cntl, ih_rb_cntl;
62
63 if (adev->asic_type < CHIP_SIENNA_CICHLID)
64 return;
65
66 ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2);
67 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
68
69 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,
70 SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout);
71 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,
72 SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled);
73 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
74 RB_USED_INT_THRESHOLD, threshold);
75
76 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
77 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
78 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
79 RB_USED_INT_THRESHOLD, threshold);
80 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
81 WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
82}
83
84/**
85 * navi10_ih_enable_interrupts - Enable the interrupt ring buffer
86 *
87 * @adev: amdgpu_device pointer
88 *
89 * Enable the interrupt ring buffer (NAVI10).
90 */
91static void navi10_ih_enable_interrupts(struct amdgpu_device *adev)
92{
93 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
94
95 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
96 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
97 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
98 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
99 DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
100 return;
101 }
102 } else {
103 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
104 }
105
106 adev->irq.ih.enabled = true;
107
108 if (adev->irq.ih1.ring_size) {
109 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
110 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
111 RB_ENABLE, 1);
112 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
113 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
114 ih_rb_cntl)) {
115 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
116 return;
117 }
118 } else {
119 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
120 }
121 adev->irq.ih1.enabled = true;
122 }
123
124 if (adev->irq.ih2.ring_size) {
125 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
126 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
127 RB_ENABLE, 1);
128 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
129 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
130 ih_rb_cntl)) {
131 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
132 return;
133 }
134 } else {
135 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
136 }
137 adev->irq.ih2.enabled = true;
138 }
139}
140
141/**
142 * navi10_ih_disable_interrupts - Disable the interrupt ring buffer
143 *
144 * @adev: amdgpu_device pointer
145 *
146 * Disable the interrupt ring buffer (NAVI10).
147 */
148static void navi10_ih_disable_interrupts(struct amdgpu_device *adev)
149{
150 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
151
152 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
153 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
154 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
155 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
156 DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
157 return;
158 }
159 } else {
160 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
161 }
162
163 /* set rptr, wptr to 0 */
164 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
165 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
166 adev->irq.ih.enabled = false;
167 adev->irq.ih.rptr = 0;
168
169 if (adev->irq.ih1.ring_size) {
170 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
171 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
172 RB_ENABLE, 0);
173 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
174 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
175 ih_rb_cntl)) {
176 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
177 return;
178 }
179 } else {
180 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
181 }
182 /* set rptr, wptr to 0 */
183 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
184 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
185 adev->irq.ih1.enabled = false;
186 adev->irq.ih1.rptr = 0;
187 }
188
189 if (adev->irq.ih2.ring_size) {
190 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
191 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
192 RB_ENABLE, 0);
193 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
194 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
195 ih_rb_cntl)) {
196 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
197 return;
198 }
199 } else {
200 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
201 }
202 /* set rptr, wptr to 0 */
203 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);
204 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);
205 adev->irq.ih2.enabled = false;
206 adev->irq.ih2.rptr = 0;
207 }
208
209}
210
211static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
212{
213 int rb_bufsz = order_base_2(ih->ring_size / 4);
214
215 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
216 MC_SPACE, ih->use_bus_addr ? 1 : 4);
217 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
218 WPTR_OVERFLOW_CLEAR, 1);
219 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
220 WPTR_OVERFLOW_ENABLE, 1);
221 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
222 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
223 * value is written to memory
224 */
225 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
226 WPTR_WRITEBACK_ENABLE, 1);
227 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
228 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
229 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
230
231 return ih_rb_cntl;
232}
233
234static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
235{
236 u32 ih_doorbell_rtpr = 0;
237
238 if (ih->use_doorbell) {
239 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
240 IH_DOORBELL_RPTR, OFFSET,
241 ih->doorbell_index);
242 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
243 IH_DOORBELL_RPTR,
244 ENABLE, 1);
245 } else {
246 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
247 IH_DOORBELL_RPTR,
248 ENABLE, 0);
249 }
250 return ih_doorbell_rtpr;
251}
252
253static void navi10_ih_reroute_ih(struct amdgpu_device *adev)
254{
255 uint32_t tmp;
256
257 /* Reroute to IH ring 1 for VMC */
258 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12);
259 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);
260 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
261 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
262 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);
263
264 /* Reroute IH ring 1 for UMC */
265 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B);
266 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);
267 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
268 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);
269}
270
271/**
272 * navi10_ih_irq_init - init and enable the interrupt ring
273 *
274 * @adev: amdgpu_device pointer
275 *
276 * Allocate a ring buffer for the interrupt controller,
277 * enable the RLC, disable interrupts, enable the IH
278 * ring buffer and enable it (NAVI).
279 * Called at device load and reume.
280 * Returns 0 for success, errors for failure.
281 */
282static int navi10_ih_irq_init(struct amdgpu_device *adev)
283{
284 struct amdgpu_ih_ring *ih = &adev->irq.ih;
285 u32 ih_rb_cntl, ih_chicken;
286 u32 tmp;
287
288 /* disable irqs */
289 navi10_ih_disable_interrupts(adev);
290
291 adev->nbio.funcs->ih_control(adev);
292
293 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
294 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8);
295 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff);
296
297 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
298 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl);
299 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM,
300 !!adev->irq.msi_enabled);
301 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
302 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
303 DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
304 return -ETIMEDOUT;
305 }
306 } else {
307 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
308 }
309 navi10_ih_reroute_ih(adev);
310
311 if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) {
312 if (ih->use_bus_addr) {
313 switch (adev->asic_type) {
314 case CHIP_SIENNA_CICHLID:
315 case CHIP_NAVY_FLOUNDER:
316 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid);
317 ih_chicken = REG_SET_FIELD(ih_chicken,
318 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
319 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken);
320 break;
321 default:
322 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
323 ih_chicken = REG_SET_FIELD(ih_chicken,
324 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
325 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
326 break;
327 }
328 }
329 }
330
331 /* set the writeback address whether it's enabled or not */
332 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO,
333 lower_32_bits(ih->wptr_addr));
334 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI,
335 upper_32_bits(ih->wptr_addr) & 0xFFFF);
336
337 /* set rptr, wptr to 0 */
338 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
339 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
340
341 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR,
342 navi10_ih_doorbell_rptr(ih));
343
344 adev->nbio.funcs->ih_doorbell_range(adev, ih->use_doorbell,
345 ih->doorbell_index);
346
347 ih = &adev->irq.ih1;
348 if (ih->ring_size) {
349 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8);
350 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1,
351 (ih->gpu_addr >> 40) & 0xff);
352
353 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
354 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl);
355 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
356 WPTR_OVERFLOW_ENABLE, 0);
357 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
358 RB_FULL_DRAIN_ENABLE, 1);
359 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
360 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
361 ih_rb_cntl)) {
362 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
363 return -ETIMEDOUT;
364 }
365 } else {
366 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
367 }
368 /* set rptr, wptr to 0 */
369 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
370 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
371
372 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1,
373 navi10_ih_doorbell_rptr(ih));
374 }
375
376 ih = &adev->irq.ih2;
377 if (ih->ring_size) {
378 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8);
379 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2,
380 (ih->gpu_addr >> 40) & 0xff);
381
382 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
383 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl);
384
385 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) {
386 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
387 ih_rb_cntl)) {
388 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
389 return -ETIMEDOUT;
390 }
391 } else {
392 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
393 }
394 /* set rptr, wptr to 0 */
395 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);
396 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);
397
398 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2,
399 navi10_ih_doorbell_rptr(ih));
400 }
401
402
403 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);
404 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
405 CLIENT18_IS_STORM_CLIENT, 1);
406 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp);
407
408 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL);
409 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);
410 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp);
411
412 pci_set_master(adev->pdev);
413
414 /* enable interrupts */
415 navi10_ih_enable_interrupts(adev);
416 /* enable wptr force update for self int */
417 force_update_wptr_for_self_int(adev, 0, 8, true);
418
419 return 0;
420}
421
422/**
423 * navi10_ih_irq_disable - disable interrupts
424 *
425 * @adev: amdgpu_device pointer
426 *
427 * Disable interrupts on the hw (NAVI10).
428 */
429static void navi10_ih_irq_disable(struct amdgpu_device *adev)
430{
431 force_update_wptr_for_self_int(adev, 0, 8, false);
432 navi10_ih_disable_interrupts(adev);
433
434 /* Wait and acknowledge irq */
435 mdelay(1);
436}
437
438/**
439 * navi10_ih_get_wptr - get the IH ring buffer wptr
440 *
441 * @adev: amdgpu_device pointer
442 *
443 * Get the IH ring buffer wptr from either the register
444 * or the writeback memory buffer (NAVI10). Also check for
445 * ring buffer overflow and deal with it.
446 * Returns the value of the wptr.
447 */
448static u32 navi10_ih_get_wptr(struct amdgpu_device *adev,
449 struct amdgpu_ih_ring *ih)
450{
451 u32 wptr, reg, tmp;
452
453 wptr = le32_to_cpu(*ih->wptr_cpu);
454
455 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
456 goto out;
457
458 if (ih == &adev->irq.ih)
459 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
460 else if (ih == &adev->irq.ih1)
461 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
462 else if (ih == &adev->irq.ih2)
463 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
464 else
465 BUG();
466
467 wptr = RREG32_NO_KIQ(reg);
468 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
469 goto out;
470 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
471
472 /* When a ring buffer overflow happen start parsing interrupt
473 * from the last not overwritten vector (wptr + 32). Hopefully
474 * this should allow us to catch up.
475 */
476 tmp = (wptr + 32) & ih->ptr_mask;
477 dev_warn(adev->dev, "IH ring buffer overflow "
478 "(0x%08X, 0x%08X, 0x%08X)\n",
479 wptr, ih->rptr, tmp);
480 ih->rptr = tmp;
481
482 if (ih == &adev->irq.ih)
483 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
484 else if (ih == &adev->irq.ih1)
485 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
486 else if (ih == &adev->irq.ih2)
487 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
488 else
489 BUG();
490
491 tmp = RREG32_NO_KIQ(reg);
492 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
493 WREG32_NO_KIQ(reg, tmp);
494out:
495 return (wptr & ih->ptr_mask);
496}
497
498/**
499 * navi10_ih_decode_iv - decode an interrupt vector
500 *
501 * @adev: amdgpu_device pointer
502 *
503 * Decodes the interrupt vector at the current rptr
504 * position and also advance the position.
505 */
506static void navi10_ih_decode_iv(struct amdgpu_device *adev,
507 struct amdgpu_ih_ring *ih,
508 struct amdgpu_iv_entry *entry)
509{
510 /* wptr/rptr are in bytes! */
511 u32 ring_index = ih->rptr >> 2;
512 uint32_t dw[8];
513
514 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
515 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
516 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
517 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
518 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]);
519 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]);
520 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]);
521 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]);
522
523 entry->client_id = dw[0] & 0xff;
524 entry->src_id = (dw[0] >> 8) & 0xff;
525 entry->ring_id = (dw[0] >> 16) & 0xff;
526 entry->vmid = (dw[0] >> 24) & 0xf;
527 entry->vmid_src = (dw[0] >> 31);
528 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32);
529 entry->timestamp_src = dw[2] >> 31;
530 entry->pasid = dw[3] & 0xffff;
531 entry->pasid_src = dw[3] >> 31;
532 entry->src_data[0] = dw[4];
533 entry->src_data[1] = dw[5];
534 entry->src_data[2] = dw[6];
535 entry->src_data[3] = dw[7];
536
537 /* wptr/rptr are in bytes! */
538 ih->rptr += 32;
539}
540
541/**
542 * navi10_ih_irq_rearm - rearm IRQ if lost
543 *
544 * @adev: amdgpu_device pointer
545 *
546 */
547static void navi10_ih_irq_rearm(struct amdgpu_device *adev,
548 struct amdgpu_ih_ring *ih)
549{
550 uint32_t reg_rptr = 0;
551 uint32_t v = 0;
552 uint32_t i = 0;
553
554 if (ih == &adev->irq.ih)
555 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
556 else if (ih == &adev->irq.ih1)
557 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
558 else if (ih == &adev->irq.ih2)
559 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
560 else
561 return;
562
563 /* Rearm IRQ / re-write doorbell if doorbell write is lost */
564 for (i = 0; i < MAX_REARM_RETRY; i++) {
565 v = RREG32_NO_KIQ(reg_rptr);
566 if ((v < ih->ring_size) && (v != ih->rptr))
567 WDOORBELL32(ih->doorbell_index, ih->rptr);
568 else
569 break;
570 }
571}
572
573/**
574 * navi10_ih_set_rptr - set the IH ring buffer rptr
575 *
576 * @adev: amdgpu_device pointer
577 *
578 * Set the IH ring buffer rptr.
579 */
580static void navi10_ih_set_rptr(struct amdgpu_device *adev,
581 struct amdgpu_ih_ring *ih)
582{
583 if (ih->use_doorbell) {
584 /* XXX check if swapping is necessary on BE */
585 *ih->rptr_cpu = ih->rptr;
586 WDOORBELL32(ih->doorbell_index, ih->rptr);
587
588 if (amdgpu_sriov_vf(adev))
589 navi10_ih_irq_rearm(adev, ih);
590 } else if (ih == &adev->irq.ih) {
591 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr);
592 } else if (ih == &adev->irq.ih1) {
593 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr);
594 } else if (ih == &adev->irq.ih2) {
595 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr);
596 }
597}
598
599/**
600 * navi10_ih_self_irq - dispatch work for ring 1 and 2
601 *
602 * @adev: amdgpu_device pointer
603 * @source: irq source
604 * @entry: IV with WPTR update
605 *
606 * Update the WPTR from the IV and schedule work to handle the entries.
607 */
608static int navi10_ih_self_irq(struct amdgpu_device *adev,
609 struct amdgpu_irq_src *source,
610 struct amdgpu_iv_entry *entry)
611{
612 uint32_t wptr = cpu_to_le32(entry->src_data[0]);
613
614 switch (entry->ring_id) {
615 case 1:
616 *adev->irq.ih1.wptr_cpu = wptr;
617 schedule_work(&adev->irq.ih1_work);
618 break;
619 case 2:
620 *adev->irq.ih2.wptr_cpu = wptr;
621 schedule_work(&adev->irq.ih2_work);
622 break;
623 default: break;
624 }
625 return 0;
626}
627
628static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = {
629 .process = navi10_ih_self_irq,
630};
631
632static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev)
633{
634 adev->irq.self_irq.num_types = 0;
635 adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs;
636}
637
638static int navi10_ih_early_init(void *handle)
639{
640 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
641
642 navi10_ih_set_interrupt_funcs(adev);
643 navi10_ih_set_self_irq_funcs(adev);
644 return 0;
645}
646
647static int navi10_ih_sw_init(void *handle)
648{
649 int r;
650 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
651 bool use_bus_addr;
652
653 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,
654 &adev->irq.self_irq);
655
656 if (r)
657 return r;
658
659 /* use gpu virtual address for ih ring
660 * until ih_checken is programmed to allow
661 * use bus address for ih ring by psp bl */
662 use_bus_addr =
663 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true;
664 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr);
665 if (r)
666 return r;
667
668 adev->irq.ih.use_doorbell = true;
669 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
670
671 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true);
672 if (r)
673 return r;
674
675 adev->irq.ih1.use_doorbell = true;
676 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
677
678 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
679 if (r)
680 return r;
681
682 adev->irq.ih2.use_doorbell = true;
683 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;
684
685 r = amdgpu_irq_init(adev);
686
687 return r;
688}
689
690static int navi10_ih_sw_fini(void *handle)
691{
692 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
693
694 amdgpu_irq_fini(adev);
695 amdgpu_ih_ring_fini(adev, &adev->irq.ih2);
696 amdgpu_ih_ring_fini(adev, &adev->irq.ih1);
697 amdgpu_ih_ring_fini(adev, &adev->irq.ih);
698
699 return 0;
700}
701
702static int navi10_ih_hw_init(void *handle)
703{
704 int r;
705 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
706
707 r = navi10_ih_irq_init(adev);
708 if (r)
709 return r;
710
711 return 0;
712}
713
714static int navi10_ih_hw_fini(void *handle)
715{
716 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
717
718 navi10_ih_irq_disable(adev);
719
720 return 0;
721}
722
723static int navi10_ih_suspend(void *handle)
724{
725 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
726
727 return navi10_ih_hw_fini(adev);
728}
729
730static int navi10_ih_resume(void *handle)
731{
732 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
733
734 return navi10_ih_hw_init(adev);
735}
736
737static bool navi10_ih_is_idle(void *handle)
738{
739 /* todo */
740 return true;
741}
742
743static int navi10_ih_wait_for_idle(void *handle)
744{
745 /* todo */
746 return -ETIMEDOUT;
747}
748
749static int navi10_ih_soft_reset(void *handle)
750{
751 /* todo */
752 return 0;
753}
754
755static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev,
756 bool enable)
757{
758 uint32_t data, def, field_val;
759
760 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
761 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
762 field_val = enable ? 0 : 1;
763 data = REG_SET_FIELD(data, IH_CLK_CTRL,
764 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
765 data = REG_SET_FIELD(data, IH_CLK_CTRL,
766 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
767 data = REG_SET_FIELD(data, IH_CLK_CTRL,
768 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
769 data = REG_SET_FIELD(data, IH_CLK_CTRL,
770 DYN_CLK_SOFT_OVERRIDE, field_val);
771 data = REG_SET_FIELD(data, IH_CLK_CTRL,
772 REG_CLK_SOFT_OVERRIDE, field_val);
773 if (def != data)
774 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);
775 }
776
777 return;
778}
779
780static int navi10_ih_set_clockgating_state(void *handle,
781 enum amd_clockgating_state state)
782{
783 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
784
785 navi10_ih_update_clockgating_state(adev,
786 state == AMD_CG_STATE_GATE);
787 return 0;
788}
789
790static int navi10_ih_set_powergating_state(void *handle,
791 enum amd_powergating_state state)
792{
793 return 0;
794}
795
796static void navi10_ih_get_clockgating_state(void *handle, u32 *flags)
797{
798 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
799
800 if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL))
801 *flags |= AMD_CG_SUPPORT_IH_CG;
802
803 return;
804}
805
806static const struct amd_ip_funcs navi10_ih_ip_funcs = {
807 .name = "navi10_ih",
808 .early_init = navi10_ih_early_init,
809 .late_init = NULL,
810 .sw_init = navi10_ih_sw_init,
811 .sw_fini = navi10_ih_sw_fini,
812 .hw_init = navi10_ih_hw_init,
813 .hw_fini = navi10_ih_hw_fini,
814 .suspend = navi10_ih_suspend,
815 .resume = navi10_ih_resume,
816 .is_idle = navi10_ih_is_idle,
817 .wait_for_idle = navi10_ih_wait_for_idle,
818 .soft_reset = navi10_ih_soft_reset,
819 .set_clockgating_state = navi10_ih_set_clockgating_state,
820 .set_powergating_state = navi10_ih_set_powergating_state,
821 .get_clockgating_state = navi10_ih_get_clockgating_state,
822};
823
824static const struct amdgpu_ih_funcs navi10_ih_funcs = {
825 .get_wptr = navi10_ih_get_wptr,
826 .decode_iv = navi10_ih_decode_iv,
827 .set_rptr = navi10_ih_set_rptr
828};
829
830static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev)
831{
832 if (adev->irq.ih_funcs == NULL)
833 adev->irq.ih_funcs = &navi10_ih_funcs;
834}
835
836const struct amdgpu_ip_block_version navi10_ih_ip_block =
837{
838 .type = AMD_IP_BLOCK_TYPE_IH,
839 .major = 5,
840 .minor = 0,
841 .rev = 0,
842 .funcs = &navi10_ih_ip_funcs,
843};