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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __AMDGPU_DPM_H__
24#define __AMDGPU_DPM_H__
25
26enum amdgpu_int_thermal_type {
27 THERMAL_TYPE_NONE,
28 THERMAL_TYPE_EXTERNAL,
29 THERMAL_TYPE_EXTERNAL_GPIO,
30 THERMAL_TYPE_RV6XX,
31 THERMAL_TYPE_RV770,
32 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
33 THERMAL_TYPE_EVERGREEN,
34 THERMAL_TYPE_SUMO,
35 THERMAL_TYPE_NI,
36 THERMAL_TYPE_SI,
37 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
38 THERMAL_TYPE_CI,
39 THERMAL_TYPE_KV,
40};
41
42enum amdgpu_dpm_auto_throttle_src {
43 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
44 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
45};
46
47enum amdgpu_dpm_event_src {
48 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
49 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
50 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
51 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
52 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
53};
54
55struct amdgpu_ps {
56 u32 caps; /* vbios flags */
57 u32 class; /* vbios flags */
58 u32 class2; /* vbios flags */
59 /* UVD clocks */
60 u32 vclk;
61 u32 dclk;
62 /* VCE clocks */
63 u32 evclk;
64 u32 ecclk;
65 bool vce_active;
66 enum amd_vce_level vce_level;
67 /* asic priv */
68 void *ps_priv;
69};
70
71struct amdgpu_dpm_thermal {
72 /* thermal interrupt work */
73 struct work_struct work;
74 /* low temperature threshold */
75 int min_temp;
76 /* high temperature threshold */
77 int max_temp;
78 /* edge max emergency(shutdown) temp */
79 int max_edge_emergency_temp;
80 /* hotspot low temperature threshold */
81 int min_hotspot_temp;
82 /* hotspot high temperature critical threshold */
83 int max_hotspot_crit_temp;
84 /* hotspot max emergency(shutdown) temp */
85 int max_hotspot_emergency_temp;
86 /* memory low temperature threshold */
87 int min_mem_temp;
88 /* memory high temperature critical threshold */
89 int max_mem_crit_temp;
90 /* memory max emergency(shutdown) temp */
91 int max_mem_emergency_temp;
92 /* was last interrupt low to high or high to low */
93 bool high_to_low;
94 /* interrupt source */
95 struct amdgpu_irq_src irq;
96};
97
98enum amdgpu_clk_action
99{
100 AMDGPU_SCLK_UP = 1,
101 AMDGPU_SCLK_DOWN
102};
103
104struct amdgpu_blacklist_clocks
105{
106 u32 sclk;
107 u32 mclk;
108 enum amdgpu_clk_action action;
109};
110
111struct amdgpu_clock_and_voltage_limits {
112 u32 sclk;
113 u32 mclk;
114 u16 vddc;
115 u16 vddci;
116};
117
118struct amdgpu_clock_array {
119 u32 count;
120 u32 *values;
121};
122
123struct amdgpu_clock_voltage_dependency_entry {
124 u32 clk;
125 u16 v;
126};
127
128struct amdgpu_clock_voltage_dependency_table {
129 u32 count;
130 struct amdgpu_clock_voltage_dependency_entry *entries;
131};
132
133union amdgpu_cac_leakage_entry {
134 struct {
135 u16 vddc;
136 u32 leakage;
137 };
138 struct {
139 u16 vddc1;
140 u16 vddc2;
141 u16 vddc3;
142 };
143};
144
145struct amdgpu_cac_leakage_table {
146 u32 count;
147 union amdgpu_cac_leakage_entry *entries;
148};
149
150struct amdgpu_phase_shedding_limits_entry {
151 u16 voltage;
152 u32 sclk;
153 u32 mclk;
154};
155
156struct amdgpu_phase_shedding_limits_table {
157 u32 count;
158 struct amdgpu_phase_shedding_limits_entry *entries;
159};
160
161struct amdgpu_uvd_clock_voltage_dependency_entry {
162 u32 vclk;
163 u32 dclk;
164 u16 v;
165};
166
167struct amdgpu_uvd_clock_voltage_dependency_table {
168 u8 count;
169 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
170};
171
172struct amdgpu_vce_clock_voltage_dependency_entry {
173 u32 ecclk;
174 u32 evclk;
175 u16 v;
176};
177
178struct amdgpu_vce_clock_voltage_dependency_table {
179 u8 count;
180 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
181};
182
183struct amdgpu_ppm_table {
184 u8 ppm_design;
185 u16 cpu_core_number;
186 u32 platform_tdp;
187 u32 small_ac_platform_tdp;
188 u32 platform_tdc;
189 u32 small_ac_platform_tdc;
190 u32 apu_tdp;
191 u32 dgpu_tdp;
192 u32 dgpu_ulv_power;
193 u32 tj_max;
194};
195
196struct amdgpu_cac_tdp_table {
197 u16 tdp;
198 u16 configurable_tdp;
199 u16 tdc;
200 u16 battery_power_limit;
201 u16 small_power_limit;
202 u16 low_cac_leakage;
203 u16 high_cac_leakage;
204 u16 maximum_power_delivery_limit;
205};
206
207struct amdgpu_dpm_dynamic_state {
208 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
209 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
210 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
211 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
212 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
213 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
214 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
215 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
216 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
217 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
218 struct amdgpu_clock_array valid_sclk_values;
219 struct amdgpu_clock_array valid_mclk_values;
220 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
221 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
222 u32 mclk_sclk_ratio;
223 u32 sclk_mclk_delta;
224 u16 vddc_vddci_delta;
225 u16 min_vddc_for_pcie_gen2;
226 struct amdgpu_cac_leakage_table cac_leakage_table;
227 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
228 struct amdgpu_ppm_table *ppm_table;
229 struct amdgpu_cac_tdp_table *cac_tdp_table;
230};
231
232struct amdgpu_dpm_fan {
233 u16 t_min;
234 u16 t_med;
235 u16 t_high;
236 u16 pwm_min;
237 u16 pwm_med;
238 u16 pwm_high;
239 u8 t_hyst;
240 u32 cycle_delay;
241 u16 t_max;
242 u8 control_mode;
243 u16 default_max_fan_pwm;
244 u16 default_fan_output_sensitivity;
245 u16 fan_output_sensitivity;
246 bool ucode_fan_control;
247};
248
249enum amdgpu_pcie_gen {
250 AMDGPU_PCIE_GEN1 = 0,
251 AMDGPU_PCIE_GEN2 = 1,
252 AMDGPU_PCIE_GEN3 = 2,
253 AMDGPU_PCIE_GEN_INVALID = 0xffff
254};
255
256#define amdgpu_dpm_pre_set_power_state(adev) \
257 ((adev)->powerplay.pp_funcs->pre_set_power_state((adev)->powerplay.pp_handle))
258
259#define amdgpu_dpm_set_power_state(adev) \
260 ((adev)->powerplay.pp_funcs->set_power_state((adev)->powerplay.pp_handle))
261
262#define amdgpu_dpm_post_set_power_state(adev) \
263 ((adev)->powerplay.pp_funcs->post_set_power_state((adev)->powerplay.pp_handle))
264
265#define amdgpu_dpm_display_configuration_changed(adev) \
266 ((adev)->powerplay.pp_funcs->display_configuration_changed((adev)->powerplay.pp_handle))
267
268#define amdgpu_dpm_print_power_state(adev, ps) \
269 ((adev)->powerplay.pp_funcs->print_power_state((adev)->powerplay.pp_handle, (ps)))
270
271#define amdgpu_dpm_vblank_too_short(adev) \
272 ((adev)->powerplay.pp_funcs->vblank_too_short((adev)->powerplay.pp_handle))
273
274#define amdgpu_dpm_enable_bapm(adev, e) \
275 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
276
277#define amdgpu_dpm_set_fan_control_mode(adev, m) \
278 ((adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)))
279
280#define amdgpu_dpm_get_fan_control_mode(adev) \
281 ((adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle))
282
283#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
284 ((adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)))
285
286#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
287 ((adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)))
288
289#define amdgpu_dpm_get_fan_speed_rpm(adev, s) \
290 ((adev)->powerplay.pp_funcs->get_fan_speed_rpm)((adev)->powerplay.pp_handle, (s))
291
292#define amdgpu_dpm_set_fan_speed_rpm(adev, s) \
293 ((adev)->powerplay.pp_funcs->set_fan_speed_rpm)((adev)->powerplay.pp_handle, (s))
294
295#define amdgpu_dpm_force_performance_level(adev, l) \
296 ((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)))
297
298#define amdgpu_dpm_get_current_power_state(adev) \
299 ((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
300
301#define amdgpu_dpm_get_pp_num_states(adev, data) \
302 ((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data))
303
304#define amdgpu_dpm_get_pp_table(adev, table) \
305 ((adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table))
306
307#define amdgpu_dpm_set_pp_table(adev, buf, size) \
308 ((adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size))
309
310#define amdgpu_dpm_print_clock_levels(adev, type, buf) \
311 ((adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf))
312
313#define amdgpu_dpm_force_clock_level(adev, type, level) \
314 ((adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level))
315
316#define amdgpu_dpm_get_sclk_od(adev) \
317 ((adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle))
318
319#define amdgpu_dpm_set_sclk_od(adev, value) \
320 ((adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value))
321
322#define amdgpu_dpm_get_mclk_od(adev) \
323 ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
324
325#define amdgpu_dpm_set_mclk_od(adev, value) \
326 ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
327
328#define amdgpu_dpm_dispatch_task(adev, task_id, user_state) \
329 ((adev)->powerplay.pp_funcs->dispatch_tasks)((adev)->powerplay.pp_handle, (task_id), (user_state))
330
331#define amdgpu_dpm_check_state_equal(adev, cps, rps, equal) \
332 ((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal)))
333
334#define amdgpu_dpm_get_vce_clock_state(adev, i) \
335 ((adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i)))
336
337#define amdgpu_dpm_get_performance_level(adev) \
338 ((adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle))
339
340#define amdgpu_dpm_reset_power_profile_state(adev, request) \
341 ((adev)->powerplay.pp_funcs->reset_power_profile_state(\
342 (adev)->powerplay.pp_handle, request))
343
344#define amdgpu_dpm_set_clockgating_by_smu(adev, msg_id) \
345 ((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
346 (adev)->powerplay.pp_handle, msg_id))
347
348#define amdgpu_dpm_get_power_profile_mode(adev, buf) \
349 ((adev)->powerplay.pp_funcs->get_power_profile_mode(\
350 (adev)->powerplay.pp_handle, buf))
351
352#define amdgpu_dpm_set_power_profile_mode(adev, parameter, size) \
353 ((adev)->powerplay.pp_funcs->set_power_profile_mode(\
354 (adev)->powerplay.pp_handle, parameter, size))
355
356#define amdgpu_dpm_odn_edit_dpm_table(adev, type, parameter, size) \
357 ((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
358 (adev)->powerplay.pp_handle, type, parameter, size))
359
360#define amdgpu_dpm_enable_mgpu_fan_boost(adev) \
361 ((adev)->powerplay.pp_funcs->enable_mgpu_fan_boost(\
362 (adev)->powerplay.pp_handle))
363
364#define amdgpu_dpm_get_ppfeature_status(adev, buf) \
365 ((adev)->powerplay.pp_funcs->get_ppfeature_status(\
366 (adev)->powerplay.pp_handle, (buf)))
367
368#define amdgpu_dpm_set_ppfeature_status(adev, ppfeatures) \
369 ((adev)->powerplay.pp_funcs->set_ppfeature_status(\
370 (adev)->powerplay.pp_handle, (ppfeatures)))
371
372struct amdgpu_dpm {
373 struct amdgpu_ps *ps;
374 /* number of valid power states */
375 int num_ps;
376 /* current power state that is active */
377 struct amdgpu_ps *current_ps;
378 /* requested power state */
379 struct amdgpu_ps *requested_ps;
380 /* boot up power state */
381 struct amdgpu_ps *boot_ps;
382 /* default uvd power state */
383 struct amdgpu_ps *uvd_ps;
384 /* vce requirements */
385 u32 num_of_vce_states;
386 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
387 enum amd_vce_level vce_level;
388 enum amd_pm_state_type state;
389 enum amd_pm_state_type user_state;
390 enum amd_pm_state_type last_state;
391 enum amd_pm_state_type last_user_state;
392 u32 platform_caps;
393 u32 voltage_response_time;
394 u32 backbias_response_time;
395 void *priv;
396 u32 new_active_crtcs;
397 int new_active_crtc_count;
398 u32 current_active_crtcs;
399 int current_active_crtc_count;
400 struct amdgpu_dpm_dynamic_state dyn_state;
401 struct amdgpu_dpm_fan fan;
402 u32 tdp_limit;
403 u32 near_tdp_limit;
404 u32 near_tdp_limit_adjusted;
405 u32 sq_ramping_threshold;
406 u32 cac_leakage;
407 u16 tdp_od_limit;
408 u32 tdp_adjustment;
409 u16 load_line_slope;
410 bool power_control;
411 /* special states active */
412 bool thermal_active;
413 bool uvd_active;
414 bool vce_active;
415 /* thermal handling */
416 struct amdgpu_dpm_thermal thermal;
417 /* forced levels */
418 enum amd_dpm_forced_level forced_level;
419};
420
421struct amdgpu_pm {
422 struct mutex mutex;
423 u32 current_sclk;
424 u32 current_mclk;
425 u32 default_sclk;
426 u32 default_mclk;
427 struct amdgpu_i2c_chan *i2c_bus;
428 bool bus_locked;
429 /* internal thermal controller on rv6xx+ */
430 enum amdgpu_int_thermal_type int_thermal_type;
431 struct device *int_hwmon_dev;
432 /* fan control parameters */
433 bool no_fan;
434 u8 fan_pulses_per_revolution;
435 u8 fan_min_rpm;
436 u8 fan_max_rpm;
437 /* dpm */
438 bool dpm_enabled;
439 bool sysfs_initialized;
440 struct amdgpu_dpm dpm;
441 const struct firmware *fw; /* SMC firmware */
442 uint32_t fw_version;
443 uint32_t pcie_gen_mask;
444 uint32_t pcie_mlw_mask;
445 struct amd_pp_display_configuration pm_display_cfg;/* set by dc */
446 uint32_t smu_prv_buffer_size;
447 struct amdgpu_bo *smu_prv_buffer;
448 bool ac_power;
449 /* powerplay feature */
450 uint32_t pp_feature;
451
452 /* Used for I2C access to various EEPROMs on relevant ASICs */
453 struct i2c_adapter smu_i2c;
454 struct list_head pm_attr_list;
455};
456
457#define R600_SSTU_DFLT 0
458#define R600_SST_DFLT 0x00C8
459
460/* XXX are these ok? */
461#define R600_TEMP_RANGE_MIN (90 * 1000)
462#define R600_TEMP_RANGE_MAX (120 * 1000)
463
464#define FDO_PWM_MODE_STATIC 1
465#define FDO_PWM_MODE_STATIC_RPM 5
466
467enum amdgpu_td {
468 AMDGPU_TD_AUTO,
469 AMDGPU_TD_UP,
470 AMDGPU_TD_DOWN,
471};
472
473enum amdgpu_display_watermark {
474 AMDGPU_DISPLAY_WATERMARK_LOW = 0,
475 AMDGPU_DISPLAY_WATERMARK_HIGH = 1,
476};
477
478enum amdgpu_display_gap
479{
480 AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM = 0,
481 AMDGPU_PM_DISPLAY_GAP_VBLANK = 1,
482 AMDGPU_PM_DISPLAY_GAP_WATERMARK = 2,
483 AMDGPU_PM_DISPLAY_GAP_IGNORE = 3,
484};
485
486void amdgpu_dpm_print_class_info(u32 class, u32 class2);
487void amdgpu_dpm_print_cap_info(u32 caps);
488void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev,
489 struct amdgpu_ps *rps);
490u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev);
491u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev);
492void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev);
493int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
494 void *data, uint32_t *size);
495
496bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor);
497
498int amdgpu_get_platform_caps(struct amdgpu_device *adev);
499
500int amdgpu_parse_extended_power_table(struct amdgpu_device *adev);
501void amdgpu_free_extended_power_table(struct amdgpu_device *adev);
502
503void amdgpu_add_thermal_controller(struct amdgpu_device *adev);
504
505enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev,
506 u32 sys_mask,
507 enum amdgpu_pcie_gen asic_gen,
508 enum amdgpu_pcie_gen default_gen);
509
510struct amd_vce_state*
511amdgpu_get_vce_clock_state(void *handle, u32 idx);
512
513int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev,
514 uint32_t block_type, bool gate);
515
516extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low);
517
518extern int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low);
519
520int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev,
521 uint32_t pstate);
522
523int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev,
524 enum PP_SMC_POWER_PROFILE type,
525 bool en);
526
527int amdgpu_dpm_baco_reset(struct amdgpu_device *adev);
528
529int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev);
530
531bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev);
532
533bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev);
534int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev);
535
536int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev,
537 enum pp_mp1_state mp1_state);
538
539int amdgpu_dpm_baco_exit(struct amdgpu_device *adev);
540
541int amdgpu_dpm_baco_enter(struct amdgpu_device *adev);
542
543int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev,
544 uint32_t cstate);
545
546int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device *adev, bool en);
547
548#endif