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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __AMDGPU_DPM_H__
24#define __AMDGPU_DPM_H__
25
26enum amdgpu_int_thermal_type {
27 THERMAL_TYPE_NONE,
28 THERMAL_TYPE_EXTERNAL,
29 THERMAL_TYPE_EXTERNAL_GPIO,
30 THERMAL_TYPE_RV6XX,
31 THERMAL_TYPE_RV770,
32 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
33 THERMAL_TYPE_EVERGREEN,
34 THERMAL_TYPE_SUMO,
35 THERMAL_TYPE_NI,
36 THERMAL_TYPE_SI,
37 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
38 THERMAL_TYPE_CI,
39 THERMAL_TYPE_KV,
40};
41
42enum amdgpu_dpm_auto_throttle_src {
43 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
44 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
45};
46
47enum amdgpu_dpm_event_src {
48 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
49 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
50 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
51 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
52 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
53};
54
55#define SCLK_DEEP_SLEEP_MASK 0x8
56
57struct amdgpu_ps {
58 u32 caps; /* vbios flags */
59 u32 class; /* vbios flags */
60 u32 class2; /* vbios flags */
61 /* UVD clocks */
62 u32 vclk;
63 u32 dclk;
64 /* VCE clocks */
65 u32 evclk;
66 u32 ecclk;
67 bool vce_active;
68 enum amd_vce_level vce_level;
69 /* asic priv */
70 void *ps_priv;
71};
72
73struct amdgpu_dpm_thermal {
74 /* thermal interrupt work */
75 struct work_struct work;
76 /* low temperature threshold */
77 int min_temp;
78 /* high temperature threshold */
79 int max_temp;
80 /* was last interrupt low to high or high to low */
81 bool high_to_low;
82 /* interrupt source */
83 struct amdgpu_irq_src irq;
84};
85
86enum amdgpu_clk_action
87{
88 AMDGPU_SCLK_UP = 1,
89 AMDGPU_SCLK_DOWN
90};
91
92struct amdgpu_blacklist_clocks
93{
94 u32 sclk;
95 u32 mclk;
96 enum amdgpu_clk_action action;
97};
98
99struct amdgpu_clock_and_voltage_limits {
100 u32 sclk;
101 u32 mclk;
102 u16 vddc;
103 u16 vddci;
104};
105
106struct amdgpu_clock_array {
107 u32 count;
108 u32 *values;
109};
110
111struct amdgpu_clock_voltage_dependency_entry {
112 u32 clk;
113 u16 v;
114};
115
116struct amdgpu_clock_voltage_dependency_table {
117 u32 count;
118 struct amdgpu_clock_voltage_dependency_entry *entries;
119};
120
121union amdgpu_cac_leakage_entry {
122 struct {
123 u16 vddc;
124 u32 leakage;
125 };
126 struct {
127 u16 vddc1;
128 u16 vddc2;
129 u16 vddc3;
130 };
131};
132
133struct amdgpu_cac_leakage_table {
134 u32 count;
135 union amdgpu_cac_leakage_entry *entries;
136};
137
138struct amdgpu_phase_shedding_limits_entry {
139 u16 voltage;
140 u32 sclk;
141 u32 mclk;
142};
143
144struct amdgpu_phase_shedding_limits_table {
145 u32 count;
146 struct amdgpu_phase_shedding_limits_entry *entries;
147};
148
149struct amdgpu_uvd_clock_voltage_dependency_entry {
150 u32 vclk;
151 u32 dclk;
152 u16 v;
153};
154
155struct amdgpu_uvd_clock_voltage_dependency_table {
156 u8 count;
157 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
158};
159
160struct amdgpu_vce_clock_voltage_dependency_entry {
161 u32 ecclk;
162 u32 evclk;
163 u16 v;
164};
165
166struct amdgpu_vce_clock_voltage_dependency_table {
167 u8 count;
168 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
169};
170
171struct amdgpu_ppm_table {
172 u8 ppm_design;
173 u16 cpu_core_number;
174 u32 platform_tdp;
175 u32 small_ac_platform_tdp;
176 u32 platform_tdc;
177 u32 small_ac_platform_tdc;
178 u32 apu_tdp;
179 u32 dgpu_tdp;
180 u32 dgpu_ulv_power;
181 u32 tj_max;
182};
183
184struct amdgpu_cac_tdp_table {
185 u16 tdp;
186 u16 configurable_tdp;
187 u16 tdc;
188 u16 battery_power_limit;
189 u16 small_power_limit;
190 u16 low_cac_leakage;
191 u16 high_cac_leakage;
192 u16 maximum_power_delivery_limit;
193};
194
195struct amdgpu_dpm_dynamic_state {
196 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
197 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
198 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
199 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
200 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
201 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
202 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
203 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
204 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
205 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
206 struct amdgpu_clock_array valid_sclk_values;
207 struct amdgpu_clock_array valid_mclk_values;
208 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
209 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
210 u32 mclk_sclk_ratio;
211 u32 sclk_mclk_delta;
212 u16 vddc_vddci_delta;
213 u16 min_vddc_for_pcie_gen2;
214 struct amdgpu_cac_leakage_table cac_leakage_table;
215 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
216 struct amdgpu_ppm_table *ppm_table;
217 struct amdgpu_cac_tdp_table *cac_tdp_table;
218};
219
220struct amdgpu_dpm_fan {
221 u16 t_min;
222 u16 t_med;
223 u16 t_high;
224 u16 pwm_min;
225 u16 pwm_med;
226 u16 pwm_high;
227 u8 t_hyst;
228 u32 cycle_delay;
229 u16 t_max;
230 u8 control_mode;
231 u16 default_max_fan_pwm;
232 u16 default_fan_output_sensitivity;
233 u16 fan_output_sensitivity;
234 bool ucode_fan_control;
235};
236
237enum amdgpu_pcie_gen {
238 AMDGPU_PCIE_GEN1 = 0,
239 AMDGPU_PCIE_GEN2 = 1,
240 AMDGPU_PCIE_GEN3 = 2,
241 AMDGPU_PCIE_GEN_INVALID = 0xffff
242};
243
244enum amdgpu_dpm_forced_level {
245 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
246 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
247 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
248 AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
249};
250
251struct amdgpu_dpm_funcs {
252 int (*get_temperature)(struct amdgpu_device *adev);
253 int (*pre_set_power_state)(struct amdgpu_device *adev);
254 int (*set_power_state)(struct amdgpu_device *adev);
255 void (*post_set_power_state)(struct amdgpu_device *adev);
256 void (*display_configuration_changed)(struct amdgpu_device *adev);
257 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
258 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
259 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
260 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
261 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
262 bool (*vblank_too_short)(struct amdgpu_device *adev);
263 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
264 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
265 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
266 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
267 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
268 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
269 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
270 int (*force_clock_level)(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t mask);
271 int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf);
272 int (*get_sclk_od)(struct amdgpu_device *adev);
273 int (*set_sclk_od)(struct amdgpu_device *adev, uint32_t value);
274 int (*get_mclk_od)(struct amdgpu_device *adev);
275 int (*set_mclk_od)(struct amdgpu_device *adev, uint32_t value);
276 int (*check_state_equal)(struct amdgpu_device *adev,
277 struct amdgpu_ps *cps,
278 struct amdgpu_ps *rps,
279 bool *equal);
280
281 struct amd_vce_state* (*get_vce_clock_state)(struct amdgpu_device *adev, unsigned idx);
282};
283
284#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
285#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
286#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
287#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
288#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
289#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
290#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
291
292#define amdgpu_dpm_read_sensor(adev, idx, value) \
293 ((adev)->pp_enabled ? \
294 (adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), (value)) : \
295 -EINVAL)
296
297#define amdgpu_dpm_get_temperature(adev) \
298 ((adev)->pp_enabled ? \
299 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
300 (adev)->pm.funcs->get_temperature((adev)))
301
302#define amdgpu_dpm_set_fan_control_mode(adev, m) \
303 ((adev)->pp_enabled ? \
304 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
305 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
306
307#define amdgpu_dpm_get_fan_control_mode(adev) \
308 ((adev)->pp_enabled ? \
309 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
310 (adev)->pm.funcs->get_fan_control_mode((adev)))
311
312#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
313 ((adev)->pp_enabled ? \
314 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
315 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
316
317#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
318 ((adev)->pp_enabled ? \
319 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
320 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
321
322#define amdgpu_dpm_get_fan_speed_rpm(adev, s) \
323 ((adev)->pp_enabled ? \
324 (adev)->powerplay.pp_funcs->get_fan_speed_rpm((adev)->powerplay.pp_handle, (s)) : \
325 -EINVAL)
326
327#define amdgpu_dpm_get_sclk(adev, l) \
328 ((adev)->pp_enabled ? \
329 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
330 (adev)->pm.funcs->get_sclk((adev), (l)))
331
332#define amdgpu_dpm_get_mclk(adev, l) \
333 ((adev)->pp_enabled ? \
334 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
335 (adev)->pm.funcs->get_mclk((adev), (l)))
336
337
338#define amdgpu_dpm_force_performance_level(adev, l) \
339 ((adev)->pp_enabled ? \
340 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
341 (adev)->pm.funcs->force_performance_level((adev), (l)))
342
343#define amdgpu_dpm_powergate_uvd(adev, g) \
344 ((adev)->pp_enabled ? \
345 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
346 (adev)->pm.funcs->powergate_uvd((adev), (g)))
347
348#define amdgpu_dpm_powergate_vce(adev, g) \
349 ((adev)->pp_enabled ? \
350 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
351 (adev)->pm.funcs->powergate_vce((adev), (g)))
352
353#define amdgpu_dpm_get_current_power_state(adev) \
354 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
355
356#define amdgpu_dpm_get_performance_level(adev) \
357 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
358
359#define amdgpu_dpm_get_pp_num_states(adev, data) \
360 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
361
362#define amdgpu_dpm_get_pp_table(adev, table) \
363 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
364
365#define amdgpu_dpm_set_pp_table(adev, buf, size) \
366 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
367
368#define amdgpu_dpm_print_clock_levels(adev, type, buf) \
369 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
370
371#define amdgpu_dpm_force_clock_level(adev, type, level) \
372 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
373
374#define amdgpu_dpm_get_sclk_od(adev) \
375 (adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)
376
377#define amdgpu_dpm_set_sclk_od(adev, value) \
378 (adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)
379
380#define amdgpu_dpm_get_mclk_od(adev) \
381 ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
382
383#define amdgpu_dpm_set_mclk_od(adev, value) \
384 ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
385
386#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
387 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
388
389#define amgdpu_dpm_check_state_equal(adev, cps, rps, equal) (adev)->pm.funcs->check_state_equal((adev), (cps),(rps),(equal))
390
391#define amdgpu_dpm_get_vce_clock_state(adev, i) \
392 ((adev)->pp_enabled ? \
393 (adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i)) : \
394 (adev)->pm.funcs->get_vce_clock_state((adev), (i)))
395
396struct amdgpu_dpm {
397 struct amdgpu_ps *ps;
398 /* number of valid power states */
399 int num_ps;
400 /* current power state that is active */
401 struct amdgpu_ps *current_ps;
402 /* requested power state */
403 struct amdgpu_ps *requested_ps;
404 /* boot up power state */
405 struct amdgpu_ps *boot_ps;
406 /* default uvd power state */
407 struct amdgpu_ps *uvd_ps;
408 /* vce requirements */
409 u32 num_of_vce_states;
410 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
411 enum amd_vce_level vce_level;
412 enum amd_pm_state_type state;
413 enum amd_pm_state_type user_state;
414 enum amd_pm_state_type last_state;
415 enum amd_pm_state_type last_user_state;
416 u32 platform_caps;
417 u32 voltage_response_time;
418 u32 backbias_response_time;
419 void *priv;
420 u32 new_active_crtcs;
421 int new_active_crtc_count;
422 u32 current_active_crtcs;
423 int current_active_crtc_count;
424 struct amdgpu_dpm_dynamic_state dyn_state;
425 struct amdgpu_dpm_fan fan;
426 u32 tdp_limit;
427 u32 near_tdp_limit;
428 u32 near_tdp_limit_adjusted;
429 u32 sq_ramping_threshold;
430 u32 cac_leakage;
431 u16 tdp_od_limit;
432 u32 tdp_adjustment;
433 u16 load_line_slope;
434 bool power_control;
435 bool ac_power;
436 /* special states active */
437 bool thermal_active;
438 bool uvd_active;
439 bool vce_active;
440 /* thermal handling */
441 struct amdgpu_dpm_thermal thermal;
442 /* forced levels */
443 enum amdgpu_dpm_forced_level forced_level;
444};
445
446struct amdgpu_pm {
447 struct mutex mutex;
448 u32 current_sclk;
449 u32 current_mclk;
450 u32 default_sclk;
451 u32 default_mclk;
452 struct amdgpu_i2c_chan *i2c_bus;
453 /* internal thermal controller on rv6xx+ */
454 enum amdgpu_int_thermal_type int_thermal_type;
455 struct device *int_hwmon_dev;
456 /* fan control parameters */
457 bool no_fan;
458 u8 fan_pulses_per_revolution;
459 u8 fan_min_rpm;
460 u8 fan_max_rpm;
461 /* dpm */
462 bool dpm_enabled;
463 bool sysfs_initialized;
464 struct amdgpu_dpm dpm;
465 const struct firmware *fw; /* SMC firmware */
466 uint32_t fw_version;
467 const struct amdgpu_dpm_funcs *funcs;
468 uint32_t pcie_gen_mask;
469 uint32_t pcie_mlw_mask;
470 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
471};
472
473#define R600_SSTU_DFLT 0
474#define R600_SST_DFLT 0x00C8
475
476/* XXX are these ok? */
477#define R600_TEMP_RANGE_MIN (90 * 1000)
478#define R600_TEMP_RANGE_MAX (120 * 1000)
479
480#define FDO_PWM_MODE_STATIC 1
481#define FDO_PWM_MODE_STATIC_RPM 5
482
483enum amdgpu_td {
484 AMDGPU_TD_AUTO,
485 AMDGPU_TD_UP,
486 AMDGPU_TD_DOWN,
487};
488
489enum amdgpu_display_watermark {
490 AMDGPU_DISPLAY_WATERMARK_LOW = 0,
491 AMDGPU_DISPLAY_WATERMARK_HIGH = 1,
492};
493
494enum amdgpu_display_gap
495{
496 AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM = 0,
497 AMDGPU_PM_DISPLAY_GAP_VBLANK = 1,
498 AMDGPU_PM_DISPLAY_GAP_WATERMARK = 2,
499 AMDGPU_PM_DISPLAY_GAP_IGNORE = 3,
500};
501
502void amdgpu_dpm_print_class_info(u32 class, u32 class2);
503void amdgpu_dpm_print_cap_info(u32 caps);
504void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev,
505 struct amdgpu_ps *rps);
506u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev);
507u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev);
508bool amdgpu_is_uvd_state(u32 class, u32 class2);
509void amdgpu_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
510 u32 *p, u32 *u);
511int amdgpu_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th);
512
513bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor);
514
515int amdgpu_get_platform_caps(struct amdgpu_device *adev);
516
517int amdgpu_parse_extended_power_table(struct amdgpu_device *adev);
518void amdgpu_free_extended_power_table(struct amdgpu_device *adev);
519
520void amdgpu_add_thermal_controller(struct amdgpu_device *adev);
521
522enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev,
523 u32 sys_mask,
524 enum amdgpu_pcie_gen asic_gen,
525 enum amdgpu_pcie_gen default_gen);
526
527u16 amdgpu_get_pcie_lane_support(struct amdgpu_device *adev,
528 u16 asic_lanes,
529 u16 default_lanes);
530u8 amdgpu_encode_pci_lane_width(u32 lanes);
531
532struct amd_vce_state*
533amdgpu_get_vce_clock_state(struct amdgpu_device *adev, unsigned idx);
534
535#endif