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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include "amdgpu.h"
24#include "amdgpu_amdkfd.h"
25#include "cikd.h"
26#include "cik_sdma.h"
27#include "gfx_v7_0.h"
28#include "gca/gfx_7_2_d.h"
29#include "gca/gfx_7_2_enum.h"
30#include "gca/gfx_7_2_sh_mask.h"
31#include "oss/oss_2_0_d.h"
32#include "oss/oss_2_0_sh_mask.h"
33#include "gmc/gmc_7_1_d.h"
34#include "gmc/gmc_7_1_sh_mask.h"
35#include "cik_structs.h"
36
37enum hqd_dequeue_request_type {
38 NO_ACTION = 0,
39 DRAIN_PIPE,
40 RESET_WAVES
41};
42
43enum {
44 MAX_TRAPID = 8, /* 3 bits in the bitfield. */
45 MAX_WATCH_ADDRESSES = 4
46};
47
48static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,
49 uint32_t queue, uint32_t vmid)
50{
51 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
52
53 mutex_lock(&adev->srbm_mutex);
54 WREG32(mmSRBM_GFX_CNTL, value);
55}
56
57static void unlock_srbm(struct amdgpu_device *adev)
58{
59 WREG32(mmSRBM_GFX_CNTL, 0);
60 mutex_unlock(&adev->srbm_mutex);
61}
62
63static void acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,
64 uint32_t queue_id)
65{
66 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
67 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
68
69 lock_srbm(adev, mec, pipe, queue_id, 0);
70}
71
72static void release_queue(struct amdgpu_device *adev)
73{
74 unlock_srbm(adev);
75}
76
77static void kgd_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid,
78 uint32_t sh_mem_config,
79 uint32_t sh_mem_ape1_base,
80 uint32_t sh_mem_ape1_limit,
81 uint32_t sh_mem_bases, uint32_t inst)
82{
83 lock_srbm(adev, 0, 0, 0, vmid);
84
85 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
86 WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
87 WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
88 WREG32(mmSH_MEM_BASES, sh_mem_bases);
89
90 unlock_srbm(adev);
91}
92
93static int kgd_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid,
94 unsigned int vmid, uint32_t inst)
95{
96 /*
97 * We have to assume that there is no outstanding mapping.
98 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
99 * a mapping is in progress or because a mapping finished and the
100 * SW cleared it. So the protocol is to always wait & clear.
101 */
102 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
103 ATC_VMID0_PASID_MAPPING__VALID_MASK;
104
105 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
106
107 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
108 cpu_relax();
109 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
110
111 /* Mapping vmid to pasid also for IH block */
112 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
113
114 return 0;
115}
116
117static int kgd_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id,
118 uint32_t inst)
119{
120 uint32_t mec;
121 uint32_t pipe;
122
123 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
124 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
125
126 lock_srbm(adev, mec, pipe, 0, 0);
127
128 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
129 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
130
131 unlock_srbm(adev);
132
133 return 0;
134}
135
136static inline uint32_t get_sdma_rlc_reg_offset(struct cik_sdma_rlc_registers *m)
137{
138 uint32_t retval;
139
140 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
141 m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
142
143 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n",
144 m->sdma_engine_id, m->sdma_queue_id, retval);
145
146 return retval;
147}
148
149static inline struct cik_mqd *get_mqd(void *mqd)
150{
151 return (struct cik_mqd *)mqd;
152}
153
154static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
155{
156 return (struct cik_sdma_rlc_registers *)mqd;
157}
158
159static int kgd_hqd_load(struct amdgpu_device *adev, void *mqd,
160 uint32_t pipe_id, uint32_t queue_id,
161 uint32_t __user *wptr, uint32_t wptr_shift,
162 uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst)
163{
164 struct cik_mqd *m;
165 uint32_t *mqd_hqd;
166 uint32_t reg, wptr_val, data;
167 bool valid_wptr = false;
168
169 m = get_mqd(mqd);
170
171 acquire_queue(adev, pipe_id, queue_id);
172
173 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_MQD_CONTROL. */
174 mqd_hqd = &m->cp_mqd_base_addr_lo;
175
176 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++)
177 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
178
179 /* Copy userspace write pointer value to register.
180 * Activate doorbell logic to monitor subsequent changes.
181 */
182 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
183 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
184 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
185
186 /* read_user_ptr may take the mm->mmap_lock.
187 * release srbm_mutex to avoid circular dependency between
188 * srbm_mutex->mmap_lock->reservation_ww_class_mutex->srbm_mutex.
189 */
190 release_queue(adev);
191 valid_wptr = read_user_wptr(mm, wptr, wptr_val);
192 acquire_queue(adev, pipe_id, queue_id);
193 if (valid_wptr)
194 WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask);
195
196 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
197 WREG32(mmCP_HQD_ACTIVE, data);
198
199 release_queue(adev);
200
201 return 0;
202}
203
204static int kgd_hqd_dump(struct amdgpu_device *adev,
205 uint32_t pipe_id, uint32_t queue_id,
206 uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)
207{
208 uint32_t i = 0, reg;
209#define HQD_N_REGS (35+4)
210#define DUMP_REG(addr) do { \
211 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \
212 break; \
213 (*dump)[i][0] = (addr) << 2; \
214 (*dump)[i++][1] = RREG32(addr); \
215 } while (0)
216
217 *dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL);
218 if (*dump == NULL)
219 return -ENOMEM;
220
221 acquire_queue(adev, pipe_id, queue_id);
222
223 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0);
224 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1);
225 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2);
226 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3);
227
228 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++)
229 DUMP_REG(reg);
230
231 release_queue(adev);
232
233 WARN_ON_ONCE(i != HQD_N_REGS);
234 *n_regs = i;
235
236 return 0;
237}
238
239static int kgd_hqd_sdma_load(struct amdgpu_device *adev, void *mqd,
240 uint32_t __user *wptr, struct mm_struct *mm)
241{
242 struct cik_sdma_rlc_registers *m;
243 unsigned long end_jiffies;
244 uint32_t sdma_rlc_reg_offset;
245 uint32_t data;
246
247 m = get_sdma_mqd(mqd);
248 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
249
250 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
251 m->sdma_rlc_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
252
253 end_jiffies = msecs_to_jiffies(2000) + jiffies;
254 while (true) {
255 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
256 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
257 break;
258 if (time_after(jiffies, end_jiffies)) {
259 pr_err("SDMA RLC not idle in %s\n", __func__);
260 return -ETIME;
261 }
262 usleep_range(500, 1000);
263 }
264
265 data = REG_SET_FIELD(m->sdma_rlc_doorbell, SDMA0_RLC0_DOORBELL,
266 ENABLE, 1);
267 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
268 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
269 m->sdma_rlc_rb_rptr);
270
271 if (read_user_wptr(mm, wptr, data))
272 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data);
273 else
274 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
275 m->sdma_rlc_rb_rptr);
276
277 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR,
278 m->sdma_rlc_virtual_addr);
279 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
280 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
281 m->sdma_rlc_rb_base_hi);
282 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
283 m->sdma_rlc_rb_rptr_addr_lo);
284 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
285 m->sdma_rlc_rb_rptr_addr_hi);
286
287 data = REG_SET_FIELD(m->sdma_rlc_rb_cntl, SDMA0_RLC0_RB_CNTL,
288 RB_ENABLE, 1);
289 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
290
291 return 0;
292}
293
294static int kgd_hqd_sdma_dump(struct amdgpu_device *adev,
295 uint32_t engine_id, uint32_t queue_id,
296 uint32_t (**dump)[2], uint32_t *n_regs)
297{
298 uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET +
299 queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
300 uint32_t i = 0, reg;
301#undef HQD_N_REGS
302#define HQD_N_REGS (19+4)
303
304 *dump = kmalloc_array(HQD_N_REGS, sizeof(**dump), GFP_KERNEL);
305 if (*dump == NULL)
306 return -ENOMEM;
307
308 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
309 DUMP_REG(sdma_offset + reg);
310 for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK;
311 reg++)
312 DUMP_REG(sdma_offset + reg);
313
314 WARN_ON_ONCE(i != HQD_N_REGS);
315 *n_regs = i;
316
317 return 0;
318}
319
320static bool kgd_hqd_is_occupied(struct amdgpu_device *adev,
321 uint64_t queue_address, uint32_t pipe_id,
322 uint32_t queue_id, uint32_t inst)
323{
324 uint32_t act;
325 bool retval = false;
326 uint32_t low, high;
327
328 acquire_queue(adev, pipe_id, queue_id);
329 act = RREG32(mmCP_HQD_ACTIVE);
330 if (act) {
331 low = lower_32_bits(queue_address >> 8);
332 high = upper_32_bits(queue_address >> 8);
333
334 if (low == RREG32(mmCP_HQD_PQ_BASE) &&
335 high == RREG32(mmCP_HQD_PQ_BASE_HI))
336 retval = true;
337 }
338 release_queue(adev);
339 return retval;
340}
341
342static bool kgd_hqd_sdma_is_occupied(struct amdgpu_device *adev, void *mqd)
343{
344 struct cik_sdma_rlc_registers *m;
345 uint32_t sdma_rlc_reg_offset;
346 uint32_t sdma_rlc_rb_cntl;
347
348 m = get_sdma_mqd(mqd);
349 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
350
351 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
352
353 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
354 return true;
355
356 return false;
357}
358
359static int kgd_hqd_destroy(struct amdgpu_device *adev, void *mqd,
360 enum kfd_preempt_type reset_type,
361 unsigned int utimeout, uint32_t pipe_id,
362 uint32_t queue_id, uint32_t inst)
363{
364 uint32_t temp;
365 enum hqd_dequeue_request_type type;
366 unsigned long flags, end_jiffies;
367 int retry;
368
369 if (amdgpu_in_reset(adev))
370 return -EIO;
371
372 acquire_queue(adev, pipe_id, queue_id);
373 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
374
375 switch (reset_type) {
376 case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
377 type = DRAIN_PIPE;
378 break;
379 case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
380 type = RESET_WAVES;
381 break;
382 default:
383 type = DRAIN_PIPE;
384 break;
385 }
386
387 /* Workaround: If IQ timer is active and the wait time is close to or
388 * equal to 0, dequeueing is not safe. Wait until either the wait time
389 * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is
390 * cleared before continuing. Also, ensure wait times are set to at
391 * least 0x3.
392 */
393 local_irq_save(flags);
394 preempt_disable();
395 retry = 5000; /* wait for 500 usecs at maximum */
396 while (true) {
397 temp = RREG32(mmCP_HQD_IQ_TIMER);
398 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
399 pr_debug("HW is processing IQ\n");
400 goto loop;
401 }
402 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
403 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
404 == 3) /* SEM-rearm is safe */
405 break;
406 /* Wait time 3 is safe for CP, but our MMIO read/write
407 * time is close to 1 microsecond, so check for 10 to
408 * leave more buffer room
409 */
410 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
411 >= 10)
412 break;
413 pr_debug("IQ timer is active\n");
414 } else
415 break;
416loop:
417 if (!retry) {
418 pr_err("CP HQD IQ timer status time out\n");
419 break;
420 }
421 ndelay(100);
422 --retry;
423 }
424 retry = 1000;
425 while (true) {
426 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
427 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK))
428 break;
429 pr_debug("Dequeue request is pending\n");
430
431 if (!retry) {
432 pr_err("CP HQD dequeue request time out\n");
433 break;
434 }
435 ndelay(100);
436 --retry;
437 }
438 local_irq_restore(flags);
439 preempt_enable();
440
441 WREG32(mmCP_HQD_DEQUEUE_REQUEST, type);
442
443 end_jiffies = (utimeout * HZ / 1000) + jiffies;
444 while (true) {
445 temp = RREG32(mmCP_HQD_ACTIVE);
446 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
447 break;
448 if (time_after(jiffies, end_jiffies)) {
449 pr_err("cp queue preemption time out\n");
450 release_queue(adev);
451 return -ETIME;
452 }
453 usleep_range(500, 1000);
454 }
455
456 release_queue(adev);
457 return 0;
458}
459
460static int kgd_hqd_sdma_destroy(struct amdgpu_device *adev, void *mqd,
461 unsigned int utimeout)
462{
463 struct cik_sdma_rlc_registers *m;
464 uint32_t sdma_rlc_reg_offset;
465 uint32_t temp;
466 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
467
468 m = get_sdma_mqd(mqd);
469 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
470
471 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
472 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
473 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
474
475 while (true) {
476 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
477 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
478 break;
479 if (time_after(jiffies, end_jiffies)) {
480 pr_err("SDMA RLC not idle in %s\n", __func__);
481 return -ETIME;
482 }
483 usleep_range(500, 1000);
484 }
485
486 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
487 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
488 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
489 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
490
491 m->sdma_rlc_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
492
493 return 0;
494}
495
496static int kgd_wave_control_execute(struct amdgpu_device *adev,
497 uint32_t gfx_index_val,
498 uint32_t sq_cmd, uint32_t inst)
499{
500 uint32_t data;
501
502 mutex_lock(&adev->grbm_idx_mutex);
503
504 WREG32(mmGRBM_GFX_INDEX, gfx_index_val);
505 WREG32(mmSQ_CMD, sq_cmd);
506
507 /* Restore the GRBM_GFX_INDEX register */
508
509 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK |
510 GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
511 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
512
513 WREG32(mmGRBM_GFX_INDEX, data);
514
515 mutex_unlock(&adev->grbm_idx_mutex);
516
517 return 0;
518}
519
520static bool get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
521 uint8_t vmid, uint16_t *p_pasid)
522{
523 uint32_t value;
524
525 value = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
526 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
527
528 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
529}
530
531static void set_scratch_backing_va(struct amdgpu_device *adev,
532 uint64_t va, uint32_t vmid)
533{
534 lock_srbm(adev, 0, 0, 0, vmid);
535 WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va);
536 unlock_srbm(adev);
537}
538
539static void set_vm_context_page_table_base(struct amdgpu_device *adev,
540 uint32_t vmid, uint64_t page_table_base)
541{
542 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
543 pr_err("trying to set page table base for wrong VMID\n");
544 return;
545 }
546 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8,
547 lower_32_bits(page_table_base));
548}
549
550 /**
551 * read_vmid_from_vmfault_reg - read vmid from register
552 *
553 * adev: amdgpu_device pointer
554 * @vmid: vmid pointer
555 * read vmid from register (CIK).
556 */
557static uint32_t read_vmid_from_vmfault_reg(struct amdgpu_device *adev)
558{
559 uint32_t status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
560
561 return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
562}
563
564const struct kfd2kgd_calls gfx_v7_kfd2kgd = {
565 .program_sh_mem_settings = kgd_program_sh_mem_settings,
566 .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
567 .init_interrupts = kgd_init_interrupts,
568 .hqd_load = kgd_hqd_load,
569 .hqd_sdma_load = kgd_hqd_sdma_load,
570 .hqd_dump = kgd_hqd_dump,
571 .hqd_sdma_dump = kgd_hqd_sdma_dump,
572 .hqd_is_occupied = kgd_hqd_is_occupied,
573 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
574 .hqd_destroy = kgd_hqd_destroy,
575 .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
576 .wave_control_execute = kgd_wave_control_execute,
577 .get_atc_vmid_pasid_mapping_info = get_atc_vmid_pasid_mapping_info,
578 .set_scratch_backing_va = set_scratch_backing_va,
579 .set_vm_context_page_table_base = set_vm_context_page_table_base,
580 .read_vmid_from_vmfault_reg = read_vmid_from_vmfault_reg,
581};
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include "amdgpu.h"
24#include "amdgpu_amdkfd.h"
25#include "cikd.h"
26#include "cik_sdma.h"
27#include "gfx_v7_0.h"
28#include "gca/gfx_7_2_d.h"
29#include "gca/gfx_7_2_enum.h"
30#include "gca/gfx_7_2_sh_mask.h"
31#include "oss/oss_2_0_d.h"
32#include "oss/oss_2_0_sh_mask.h"
33#include "gmc/gmc_7_1_d.h"
34#include "gmc/gmc_7_1_sh_mask.h"
35#include "cik_structs.h"
36
37enum hqd_dequeue_request_type {
38 NO_ACTION = 0,
39 DRAIN_PIPE,
40 RESET_WAVES
41};
42
43enum {
44 MAX_TRAPID = 8, /* 3 bits in the bitfield. */
45 MAX_WATCH_ADDRESSES = 4
46};
47
48enum {
49 ADDRESS_WATCH_REG_ADDR_HI = 0,
50 ADDRESS_WATCH_REG_ADDR_LO,
51 ADDRESS_WATCH_REG_CNTL,
52 ADDRESS_WATCH_REG_MAX
53};
54
55/* not defined in the CI/KV reg file */
56enum {
57 ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL,
58 ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF,
59 ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000,
60 /* extend the mask to 26 bits to match the low address field */
61 ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6,
62 ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF
63};
64
65static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = {
66 mmTCP_WATCH0_ADDR_H, mmTCP_WATCH0_ADDR_L, mmTCP_WATCH0_CNTL,
67 mmTCP_WATCH1_ADDR_H, mmTCP_WATCH1_ADDR_L, mmTCP_WATCH1_CNTL,
68 mmTCP_WATCH2_ADDR_H, mmTCP_WATCH2_ADDR_L, mmTCP_WATCH2_CNTL,
69 mmTCP_WATCH3_ADDR_H, mmTCP_WATCH3_ADDR_L, mmTCP_WATCH3_CNTL
70};
71
72union TCP_WATCH_CNTL_BITS {
73 struct {
74 uint32_t mask:24;
75 uint32_t vmid:4;
76 uint32_t atc:1;
77 uint32_t mode:2;
78 uint32_t valid:1;
79 } bitfields, bits;
80 uint32_t u32All;
81 signed int i32All;
82 float f32All;
83};
84
85static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
86{
87 return (struct amdgpu_device *)kgd;
88}
89
90static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
91 uint32_t queue, uint32_t vmid)
92{
93 struct amdgpu_device *adev = get_amdgpu_device(kgd);
94 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
95
96 mutex_lock(&adev->srbm_mutex);
97 WREG32(mmSRBM_GFX_CNTL, value);
98}
99
100static void unlock_srbm(struct kgd_dev *kgd)
101{
102 struct amdgpu_device *adev = get_amdgpu_device(kgd);
103
104 WREG32(mmSRBM_GFX_CNTL, 0);
105 mutex_unlock(&adev->srbm_mutex);
106}
107
108static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
109 uint32_t queue_id)
110{
111 struct amdgpu_device *adev = get_amdgpu_device(kgd);
112
113 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
114 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
115
116 lock_srbm(kgd, mec, pipe, queue_id, 0);
117}
118
119static void release_queue(struct kgd_dev *kgd)
120{
121 unlock_srbm(kgd);
122}
123
124static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
125 uint32_t sh_mem_config,
126 uint32_t sh_mem_ape1_base,
127 uint32_t sh_mem_ape1_limit,
128 uint32_t sh_mem_bases)
129{
130 struct amdgpu_device *adev = get_amdgpu_device(kgd);
131
132 lock_srbm(kgd, 0, 0, 0, vmid);
133
134 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
135 WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
136 WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
137 WREG32(mmSH_MEM_BASES, sh_mem_bases);
138
139 unlock_srbm(kgd);
140}
141
142static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, u32 pasid,
143 unsigned int vmid)
144{
145 struct amdgpu_device *adev = get_amdgpu_device(kgd);
146
147 /*
148 * We have to assume that there is no outstanding mapping.
149 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
150 * a mapping is in progress or because a mapping finished and the
151 * SW cleared it. So the protocol is to always wait & clear.
152 */
153 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
154 ATC_VMID0_PASID_MAPPING__VALID_MASK;
155
156 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
157
158 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
159 cpu_relax();
160 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
161
162 /* Mapping vmid to pasid also for IH block */
163 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
164
165 return 0;
166}
167
168static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
169{
170 struct amdgpu_device *adev = get_amdgpu_device(kgd);
171 uint32_t mec;
172 uint32_t pipe;
173
174 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
175 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
176
177 lock_srbm(kgd, mec, pipe, 0, 0);
178
179 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
180 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
181
182 unlock_srbm(kgd);
183
184 return 0;
185}
186
187static inline uint32_t get_sdma_rlc_reg_offset(struct cik_sdma_rlc_registers *m)
188{
189 uint32_t retval;
190
191 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
192 m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
193
194 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n",
195 m->sdma_engine_id, m->sdma_queue_id, retval);
196
197 return retval;
198}
199
200static inline struct cik_mqd *get_mqd(void *mqd)
201{
202 return (struct cik_mqd *)mqd;
203}
204
205static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
206{
207 return (struct cik_sdma_rlc_registers *)mqd;
208}
209
210static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
211 uint32_t queue_id, uint32_t __user *wptr,
212 uint32_t wptr_shift, uint32_t wptr_mask,
213 struct mm_struct *mm)
214{
215 struct amdgpu_device *adev = get_amdgpu_device(kgd);
216 struct cik_mqd *m;
217 uint32_t *mqd_hqd;
218 uint32_t reg, wptr_val, data;
219 bool valid_wptr = false;
220
221 m = get_mqd(mqd);
222
223 acquire_queue(kgd, pipe_id, queue_id);
224
225 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_MQD_CONTROL. */
226 mqd_hqd = &m->cp_mqd_base_addr_lo;
227
228 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++)
229 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
230
231 /* Copy userspace write pointer value to register.
232 * Activate doorbell logic to monitor subsequent changes.
233 */
234 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
235 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
236 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
237
238 /* read_user_ptr may take the mm->mmap_lock.
239 * release srbm_mutex to avoid circular dependency between
240 * srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex.
241 */
242 release_queue(kgd);
243 valid_wptr = read_user_wptr(mm, wptr, wptr_val);
244 acquire_queue(kgd, pipe_id, queue_id);
245 if (valid_wptr)
246 WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask);
247
248 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
249 WREG32(mmCP_HQD_ACTIVE, data);
250
251 release_queue(kgd);
252
253 return 0;
254}
255
256static int kgd_hqd_dump(struct kgd_dev *kgd,
257 uint32_t pipe_id, uint32_t queue_id,
258 uint32_t (**dump)[2], uint32_t *n_regs)
259{
260 struct amdgpu_device *adev = get_amdgpu_device(kgd);
261 uint32_t i = 0, reg;
262#define HQD_N_REGS (35+4)
263#define DUMP_REG(addr) do { \
264 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \
265 break; \
266 (*dump)[i][0] = (addr) << 2; \
267 (*dump)[i++][1] = RREG32(addr); \
268 } while (0)
269
270 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
271 if (*dump == NULL)
272 return -ENOMEM;
273
274 acquire_queue(kgd, pipe_id, queue_id);
275
276 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0);
277 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1);
278 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2);
279 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3);
280
281 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++)
282 DUMP_REG(reg);
283
284 release_queue(kgd);
285
286 WARN_ON_ONCE(i != HQD_N_REGS);
287 *n_regs = i;
288
289 return 0;
290}
291
292static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
293 uint32_t __user *wptr, struct mm_struct *mm)
294{
295 struct amdgpu_device *adev = get_amdgpu_device(kgd);
296 struct cik_sdma_rlc_registers *m;
297 unsigned long end_jiffies;
298 uint32_t sdma_rlc_reg_offset;
299 uint32_t data;
300
301 m = get_sdma_mqd(mqd);
302 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
303
304 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
305 m->sdma_rlc_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
306
307 end_jiffies = msecs_to_jiffies(2000) + jiffies;
308 while (true) {
309 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
310 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
311 break;
312 if (time_after(jiffies, end_jiffies)) {
313 pr_err("SDMA RLC not idle in %s\n", __func__);
314 return -ETIME;
315 }
316 usleep_range(500, 1000);
317 }
318
319 data = REG_SET_FIELD(m->sdma_rlc_doorbell, SDMA0_RLC0_DOORBELL,
320 ENABLE, 1);
321 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
322 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
323 m->sdma_rlc_rb_rptr);
324
325 if (read_user_wptr(mm, wptr, data))
326 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data);
327 else
328 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
329 m->sdma_rlc_rb_rptr);
330
331 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR,
332 m->sdma_rlc_virtual_addr);
333 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
334 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
335 m->sdma_rlc_rb_base_hi);
336 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
337 m->sdma_rlc_rb_rptr_addr_lo);
338 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
339 m->sdma_rlc_rb_rptr_addr_hi);
340
341 data = REG_SET_FIELD(m->sdma_rlc_rb_cntl, SDMA0_RLC0_RB_CNTL,
342 RB_ENABLE, 1);
343 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
344
345 return 0;
346}
347
348static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
349 uint32_t engine_id, uint32_t queue_id,
350 uint32_t (**dump)[2], uint32_t *n_regs)
351{
352 struct amdgpu_device *adev = get_amdgpu_device(kgd);
353 uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET +
354 queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
355 uint32_t i = 0, reg;
356#undef HQD_N_REGS
357#define HQD_N_REGS (19+4)
358
359 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
360 if (*dump == NULL)
361 return -ENOMEM;
362
363 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
364 DUMP_REG(sdma_offset + reg);
365 for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK;
366 reg++)
367 DUMP_REG(sdma_offset + reg);
368
369 WARN_ON_ONCE(i != HQD_N_REGS);
370 *n_regs = i;
371
372 return 0;
373}
374
375static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
376 uint32_t pipe_id, uint32_t queue_id)
377{
378 struct amdgpu_device *adev = get_amdgpu_device(kgd);
379 uint32_t act;
380 bool retval = false;
381 uint32_t low, high;
382
383 acquire_queue(kgd, pipe_id, queue_id);
384 act = RREG32(mmCP_HQD_ACTIVE);
385 if (act) {
386 low = lower_32_bits(queue_address >> 8);
387 high = upper_32_bits(queue_address >> 8);
388
389 if (low == RREG32(mmCP_HQD_PQ_BASE) &&
390 high == RREG32(mmCP_HQD_PQ_BASE_HI))
391 retval = true;
392 }
393 release_queue(kgd);
394 return retval;
395}
396
397static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
398{
399 struct amdgpu_device *adev = get_amdgpu_device(kgd);
400 struct cik_sdma_rlc_registers *m;
401 uint32_t sdma_rlc_reg_offset;
402 uint32_t sdma_rlc_rb_cntl;
403
404 m = get_sdma_mqd(mqd);
405 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
406
407 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
408
409 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
410 return true;
411
412 return false;
413}
414
415static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
416 enum kfd_preempt_type reset_type,
417 unsigned int utimeout, uint32_t pipe_id,
418 uint32_t queue_id)
419{
420 struct amdgpu_device *adev = get_amdgpu_device(kgd);
421 uint32_t temp;
422 enum hqd_dequeue_request_type type;
423 unsigned long flags, end_jiffies;
424 int retry;
425
426 if (amdgpu_in_reset(adev))
427 return -EIO;
428
429 acquire_queue(kgd, pipe_id, queue_id);
430 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
431
432 switch (reset_type) {
433 case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
434 type = DRAIN_PIPE;
435 break;
436 case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
437 type = RESET_WAVES;
438 break;
439 default:
440 type = DRAIN_PIPE;
441 break;
442 }
443
444 /* Workaround: If IQ timer is active and the wait time is close to or
445 * equal to 0, dequeueing is not safe. Wait until either the wait time
446 * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is
447 * cleared before continuing. Also, ensure wait times are set to at
448 * least 0x3.
449 */
450 local_irq_save(flags);
451 preempt_disable();
452 retry = 5000; /* wait for 500 usecs at maximum */
453 while (true) {
454 temp = RREG32(mmCP_HQD_IQ_TIMER);
455 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
456 pr_debug("HW is processing IQ\n");
457 goto loop;
458 }
459 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
460 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
461 == 3) /* SEM-rearm is safe */
462 break;
463 /* Wait time 3 is safe for CP, but our MMIO read/write
464 * time is close to 1 microsecond, so check for 10 to
465 * leave more buffer room
466 */
467 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
468 >= 10)
469 break;
470 pr_debug("IQ timer is active\n");
471 } else
472 break;
473loop:
474 if (!retry) {
475 pr_err("CP HQD IQ timer status time out\n");
476 break;
477 }
478 ndelay(100);
479 --retry;
480 }
481 retry = 1000;
482 while (true) {
483 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
484 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK))
485 break;
486 pr_debug("Dequeue request is pending\n");
487
488 if (!retry) {
489 pr_err("CP HQD dequeue request time out\n");
490 break;
491 }
492 ndelay(100);
493 --retry;
494 }
495 local_irq_restore(flags);
496 preempt_enable();
497
498 WREG32(mmCP_HQD_DEQUEUE_REQUEST, type);
499
500 end_jiffies = (utimeout * HZ / 1000) + jiffies;
501 while (true) {
502 temp = RREG32(mmCP_HQD_ACTIVE);
503 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
504 break;
505 if (time_after(jiffies, end_jiffies)) {
506 pr_err("cp queue preemption time out\n");
507 release_queue(kgd);
508 return -ETIME;
509 }
510 usleep_range(500, 1000);
511 }
512
513 release_queue(kgd);
514 return 0;
515}
516
517static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
518 unsigned int utimeout)
519{
520 struct amdgpu_device *adev = get_amdgpu_device(kgd);
521 struct cik_sdma_rlc_registers *m;
522 uint32_t sdma_rlc_reg_offset;
523 uint32_t temp;
524 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
525
526 m = get_sdma_mqd(mqd);
527 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m);
528
529 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
530 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
531 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
532
533 while (true) {
534 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
535 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
536 break;
537 if (time_after(jiffies, end_jiffies)) {
538 pr_err("SDMA RLC not idle in %s\n", __func__);
539 return -ETIME;
540 }
541 usleep_range(500, 1000);
542 }
543
544 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
545 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
546 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
547 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
548
549 m->sdma_rlc_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
550
551 return 0;
552}
553
554static int kgd_address_watch_disable(struct kgd_dev *kgd)
555{
556 struct amdgpu_device *adev = get_amdgpu_device(kgd);
557 union TCP_WATCH_CNTL_BITS cntl;
558 unsigned int i;
559
560 cntl.u32All = 0;
561
562 cntl.bitfields.valid = 0;
563 cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
564 cntl.bitfields.atc = 1;
565
566 /* Turning off this address until we set all the registers */
567 for (i = 0; i < MAX_WATCH_ADDRESSES; i++)
568 WREG32(watchRegs[i * ADDRESS_WATCH_REG_MAX +
569 ADDRESS_WATCH_REG_CNTL], cntl.u32All);
570
571 return 0;
572}
573
574static int kgd_address_watch_execute(struct kgd_dev *kgd,
575 unsigned int watch_point_id,
576 uint32_t cntl_val,
577 uint32_t addr_hi,
578 uint32_t addr_lo)
579{
580 struct amdgpu_device *adev = get_amdgpu_device(kgd);
581 union TCP_WATCH_CNTL_BITS cntl;
582
583 cntl.u32All = cntl_val;
584
585 /* Turning off this watch point until we set all the registers */
586 cntl.bitfields.valid = 0;
587 WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
588 ADDRESS_WATCH_REG_CNTL], cntl.u32All);
589
590 WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
591 ADDRESS_WATCH_REG_ADDR_HI], addr_hi);
592
593 WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
594 ADDRESS_WATCH_REG_ADDR_LO], addr_lo);
595
596 /* Enable the watch point */
597 cntl.bitfields.valid = 1;
598
599 WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
600 ADDRESS_WATCH_REG_CNTL], cntl.u32All);
601
602 return 0;
603}
604
605static int kgd_wave_control_execute(struct kgd_dev *kgd,
606 uint32_t gfx_index_val,
607 uint32_t sq_cmd)
608{
609 struct amdgpu_device *adev = get_amdgpu_device(kgd);
610 uint32_t data;
611
612 mutex_lock(&adev->grbm_idx_mutex);
613
614 WREG32(mmGRBM_GFX_INDEX, gfx_index_val);
615 WREG32(mmSQ_CMD, sq_cmd);
616
617 /* Restore the GRBM_GFX_INDEX register */
618
619 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK |
620 GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
621 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
622
623 WREG32(mmGRBM_GFX_INDEX, data);
624
625 mutex_unlock(&adev->grbm_idx_mutex);
626
627 return 0;
628}
629
630static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
631 unsigned int watch_point_id,
632 unsigned int reg_offset)
633{
634 return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset];
635}
636
637static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
638 uint8_t vmid, uint16_t *p_pasid)
639{
640 uint32_t value;
641 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
642
643 value = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
644 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
645
646 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
647}
648
649static void set_scratch_backing_va(struct kgd_dev *kgd,
650 uint64_t va, uint32_t vmid)
651{
652 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
653
654 lock_srbm(kgd, 0, 0, 0, vmid);
655 WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va);
656 unlock_srbm(kgd);
657}
658
659static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
660 uint64_t page_table_base)
661{
662 struct amdgpu_device *adev = get_amdgpu_device(kgd);
663
664 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
665 pr_err("trying to set page table base for wrong VMID\n");
666 return;
667 }
668 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8,
669 lower_32_bits(page_table_base));
670}
671
672 /**
673 * read_vmid_from_vmfault_reg - read vmid from register
674 *
675 * adev: amdgpu_device pointer
676 * @vmid: vmid pointer
677 * read vmid from register (CIK).
678 */
679static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd)
680{
681 struct amdgpu_device *adev = get_amdgpu_device(kgd);
682
683 uint32_t status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
684
685 return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
686}
687
688const struct kfd2kgd_calls gfx_v7_kfd2kgd = {
689 .program_sh_mem_settings = kgd_program_sh_mem_settings,
690 .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
691 .init_interrupts = kgd_init_interrupts,
692 .hqd_load = kgd_hqd_load,
693 .hqd_sdma_load = kgd_hqd_sdma_load,
694 .hqd_dump = kgd_hqd_dump,
695 .hqd_sdma_dump = kgd_hqd_sdma_dump,
696 .hqd_is_occupied = kgd_hqd_is_occupied,
697 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
698 .hqd_destroy = kgd_hqd_destroy,
699 .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
700 .address_watch_disable = kgd_address_watch_disable,
701 .address_watch_execute = kgd_address_watch_execute,
702 .wave_control_execute = kgd_wave_control_execute,
703 .address_watch_get_offset = kgd_address_watch_get_offset,
704 .get_atc_vmid_pasid_mapping_info = get_atc_vmid_pasid_mapping_info,
705 .set_scratch_backing_va = set_scratch_backing_va,
706 .set_vm_context_page_table_base = set_vm_context_page_table_base,
707 .read_vmid_from_vmfault_reg = read_vmid_from_vmfault_reg,
708};