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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22#include <linux/mmu_context.h>
23#include "amdgpu.h"
24#include "amdgpu_amdkfd.h"
25#include "amdgpu_amdkfd_gfx_v10.h"
26#include "gc/gc_10_3_0_offset.h"
27#include "gc/gc_10_3_0_sh_mask.h"
28#include "oss/osssys_5_0_0_offset.h"
29#include "oss/osssys_5_0_0_sh_mask.h"
30#include "athub/athub_2_1_0_offset.h"
31#include "athub/athub_2_1_0_sh_mask.h"
32#include "soc15_common.h"
33#include "v10_structs.h"
34#include "nv.h"
35#include "nvd.h"
36
37enum hqd_dequeue_request_type {
38 NO_ACTION = 0,
39 DRAIN_PIPE,
40 RESET_WAVES,
41 SAVE_WAVES
42};
43
44static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,
45 uint32_t queue, uint32_t vmid)
46{
47 mutex_lock(&adev->srbm_mutex);
48 nv_grbm_select(adev, mec, pipe, queue, vmid);
49}
50
51static void unlock_srbm(struct amdgpu_device *adev)
52{
53 nv_grbm_select(adev, 0, 0, 0, 0);
54 mutex_unlock(&adev->srbm_mutex);
55}
56
57static void acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,
58 uint32_t queue_id)
59{
60 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
61 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
62
63 lock_srbm(adev, mec, pipe, queue_id, 0);
64}
65
66static uint64_t get_queue_mask(struct amdgpu_device *adev,
67 uint32_t pipe_id, uint32_t queue_id)
68{
69 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe +
70 queue_id;
71
72 return 1ull << bit;
73}
74
75static void release_queue(struct amdgpu_device *adev)
76{
77 unlock_srbm(adev);
78}
79
80static void program_sh_mem_settings_v10_3(struct amdgpu_device *adev, uint32_t vmid,
81 uint32_t sh_mem_config,
82 uint32_t sh_mem_ape1_base,
83 uint32_t sh_mem_ape1_limit,
84 uint32_t sh_mem_bases, uint32_t inst)
85{
86 lock_srbm(adev, 0, 0, 0, vmid);
87
88 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
89 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
90 /* APE1 no longer exists on GFX9 */
91
92 unlock_srbm(adev);
93}
94
95/* ATC is defeatured on Sienna_Cichlid */
96static int set_pasid_vmid_mapping_v10_3(struct amdgpu_device *adev, unsigned int pasid,
97 unsigned int vmid, uint32_t inst)
98{
99 uint32_t value = pasid << IH_VMID_0_LUT__PASID__SHIFT;
100
101 /* Mapping vmid to pasid also for IH block */
102 pr_debug("mapping vmid %d -> pasid %d in IH block for GFX client\n",
103 vmid, pasid);
104 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, value);
105
106 return 0;
107}
108
109static int init_interrupts_v10_3(struct amdgpu_device *adev, uint32_t pipe_id,
110 uint32_t inst)
111{
112 uint32_t mec;
113 uint32_t pipe;
114
115 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
116 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
117
118 lock_srbm(adev, mec, pipe, 0, 0);
119
120 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL,
121 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
122 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
123
124 unlock_srbm(adev);
125
126 return 0;
127}
128
129static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
130 unsigned int engine_id,
131 unsigned int queue_id)
132{
133 uint32_t sdma_engine_reg_base = 0;
134 uint32_t sdma_rlc_reg_offset;
135
136 switch (engine_id) {
137 default:
138 dev_warn(adev->dev,
139 "Invalid sdma engine id (%d), using engine id 0\n",
140 engine_id);
141 fallthrough;
142 case 0:
143 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
144 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
145 break;
146 case 1:
147 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
148 mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
149 break;
150 case 2:
151 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
152 mmSDMA2_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
153 break;
154 case 3:
155 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
156 mmSDMA3_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
157 break;
158 }
159
160 sdma_rlc_reg_offset = sdma_engine_reg_base
161 + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
162
163 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
164 queue_id, sdma_rlc_reg_offset);
165
166 return sdma_rlc_reg_offset;
167}
168
169static inline struct v10_compute_mqd *get_mqd(void *mqd)
170{
171 return (struct v10_compute_mqd *)mqd;
172}
173
174static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd)
175{
176 return (struct v10_sdma_mqd *)mqd;
177}
178
179static int hqd_load_v10_3(struct amdgpu_device *adev, void *mqd,
180 uint32_t pipe_id, uint32_t queue_id,
181 uint32_t __user *wptr, uint32_t wptr_shift,
182 uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst)
183{
184 struct v10_compute_mqd *m;
185 uint32_t *mqd_hqd;
186 uint32_t reg, hqd_base, data;
187
188 m = get_mqd(mqd);
189
190 pr_debug("Load hqd of pipe %d queue %d\n", pipe_id, queue_id);
191 acquire_queue(adev, pipe_id, queue_id);
192
193 /* HIQ is set during driver init period with vmid set to 0*/
194 if (m->cp_hqd_vmid == 0) {
195 uint32_t value, mec, pipe;
196
197 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
198 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
199
200 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
201 mec, pipe, queue_id);
202 value = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
203 value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,
204 ((mec << 5) | (pipe << 3) | queue_id | 0x80));
205 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, value);
206 }
207
208 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */
209 mqd_hqd = &m->cp_mqd_base_addr_lo;
210 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
211
212 for (reg = hqd_base;
213 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
214 WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]);
215
216
217 /* Activate doorbell logic before triggering WPTR poll. */
218 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
219 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
220 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data);
221
222 if (wptr) {
223 /* Don't read wptr with get_user because the user
224 * context may not be accessible (if this function
225 * runs in a work queue). Instead trigger a one-shot
226 * polling read from memory in the CP. This assumes
227 * that wptr is GPU-accessible in the queue's VMID via
228 * ATC or SVM. WPTR==RPTR before starting the poll so
229 * the CP starts fetching new commands from the right
230 * place.
231 *
232 * Guessing a 64-bit WPTR from a 32-bit RPTR is a bit
233 * tricky. Assume that the queue didn't overflow. The
234 * number of valid bits in the 32-bit RPTR depends on
235 * the queue size. The remaining bits are taken from
236 * the saved 64-bit WPTR. If the WPTR wrapped, add the
237 * queue size.
238 */
239 uint32_t queue_size =
240 2 << REG_GET_FIELD(m->cp_hqd_pq_control,
241 CP_HQD_PQ_CONTROL, QUEUE_SIZE);
242 uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1);
243
244 if ((m->cp_hqd_pq_wptr_lo & (queue_size - 1)) < guessed_wptr)
245 guessed_wptr += queue_size;
246 guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);
247 guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
248
249 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
250 lower_32_bits(guessed_wptr));
251 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
252 upper_32_bits(guessed_wptr));
253 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
254 lower_32_bits((uint64_t)wptr));
255 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
256 upper_32_bits((uint64_t)wptr));
257 pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__,
258 (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
259 WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1,
260 (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
261 }
262
263 /* Start the EOP fetcher */
264 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),
265 REG_SET_FIELD(m->cp_hqd_eop_rptr,
266 CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
267
268 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
269 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data);
270
271 release_queue(adev);
272
273 return 0;
274}
275
276static int hiq_mqd_load_v10_3(struct amdgpu_device *adev, void *mqd,
277 uint32_t pipe_id, uint32_t queue_id,
278 uint32_t doorbell_off, uint32_t inst)
279{
280 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
281 struct v10_compute_mqd *m;
282 uint32_t mec, pipe;
283 int r;
284
285 m = get_mqd(mqd);
286
287 acquire_queue(adev, pipe_id, queue_id);
288
289 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
290 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
291
292 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
293 mec, pipe, queue_id);
294
295 spin_lock(&adev->gfx.kiq[0].ring_lock);
296 r = amdgpu_ring_alloc(kiq_ring, 7);
297 if (r) {
298 pr_err("Failed to alloc KIQ (%d).\n", r);
299 goto out_unlock;
300 }
301
302 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
303 amdgpu_ring_write(kiq_ring,
304 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
305 PACKET3_MAP_QUEUES_VMID(m->cp_hqd_vmid) | /* VMID */
306 PACKET3_MAP_QUEUES_QUEUE(queue_id) |
307 PACKET3_MAP_QUEUES_PIPE(pipe) |
308 PACKET3_MAP_QUEUES_ME((mec - 1)) |
309 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
310 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
311 PACKET3_MAP_QUEUES_ENGINE_SEL(1) | /* engine_sel: hiq */
312 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
313 amdgpu_ring_write(kiq_ring,
314 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(doorbell_off));
315 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo);
316 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi);
317 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo);
318 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi);
319 amdgpu_ring_commit(kiq_ring);
320
321out_unlock:
322 spin_unlock(&adev->gfx.kiq[0].ring_lock);
323 release_queue(adev);
324
325 return r;
326}
327
328static int hqd_dump_v10_3(struct amdgpu_device *adev,
329 uint32_t pipe_id, uint32_t queue_id,
330 uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst)
331{
332 uint32_t i = 0, reg;
333#define HQD_N_REGS 56
334#define DUMP_REG(addr) do { \
335 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \
336 break; \
337 (*dump)[i][0] = (addr) << 2; \
338 (*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \
339 } while (0)
340
341 *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
342 if (*dump == NULL)
343 return -ENOMEM;
344
345 acquire_queue(adev, pipe_id, queue_id);
346
347 for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
348 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
349 DUMP_REG(reg);
350
351 release_queue(adev);
352
353 WARN_ON_ONCE(i != HQD_N_REGS);
354 *n_regs = i;
355
356 return 0;
357}
358
359static int hqd_sdma_load_v10_3(struct amdgpu_device *adev, void *mqd,
360 uint32_t __user *wptr, struct mm_struct *mm)
361{
362 struct v10_sdma_mqd *m;
363 uint32_t sdma_rlc_reg_offset;
364 unsigned long end_jiffies;
365 uint32_t data;
366 uint64_t data64;
367 uint64_t __user *wptr64 = (uint64_t __user *)wptr;
368
369 m = get_sdma_mqd(mqd);
370 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
371 m->sdma_queue_id);
372
373 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
374 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
375
376 end_jiffies = msecs_to_jiffies(2000) + jiffies;
377 while (true) {
378 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
379 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
380 break;
381 if (time_after(jiffies, end_jiffies)) {
382 pr_err("SDMA RLC not idle in %s\n", __func__);
383 return -ETIME;
384 }
385 usleep_range(500, 1000);
386 }
387
388 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
389 m->sdmax_rlcx_doorbell_offset);
390
391 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
392 ENABLE, 1);
393 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
394 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
395 m->sdmax_rlcx_rb_rptr);
396 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
397 m->sdmax_rlcx_rb_rptr_hi);
398
399 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
400 if (read_user_wptr(mm, wptr64, data64)) {
401 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
402 lower_32_bits(data64));
403 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
404 upper_32_bits(data64));
405 } else {
406 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
407 m->sdmax_rlcx_rb_rptr);
408 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
409 m->sdmax_rlcx_rb_rptr_hi);
410 }
411 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
412
413 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
414 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
415 m->sdmax_rlcx_rb_base_hi);
416 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
417 m->sdmax_rlcx_rb_rptr_addr_lo);
418 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
419 m->sdmax_rlcx_rb_rptr_addr_hi);
420
421 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
422 RB_ENABLE, 1);
423 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
424
425 return 0;
426}
427
428static int hqd_sdma_dump_v10_3(struct amdgpu_device *adev,
429 uint32_t engine_id, uint32_t queue_id,
430 uint32_t (**dump)[2], uint32_t *n_regs)
431{
432 uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
433 engine_id, queue_id);
434 uint32_t i = 0, reg;
435#undef HQD_N_REGS
436#define HQD_N_REGS (19+6+7+12)
437
438 *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
439 if (*dump == NULL)
440 return -ENOMEM;
441
442 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
443 DUMP_REG(sdma_rlc_reg_offset + reg);
444 for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
445 DUMP_REG(sdma_rlc_reg_offset + reg);
446 for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
447 reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
448 DUMP_REG(sdma_rlc_reg_offset + reg);
449 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
450 reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
451 DUMP_REG(sdma_rlc_reg_offset + reg);
452
453 WARN_ON_ONCE(i != HQD_N_REGS);
454 *n_regs = i;
455
456 return 0;
457}
458
459static bool hqd_is_occupied_v10_3(struct amdgpu_device *adev,
460 uint64_t queue_address, uint32_t pipe_id,
461 uint32_t queue_id, uint32_t inst)
462{
463 uint32_t act;
464 bool retval = false;
465 uint32_t low, high;
466
467 acquire_queue(adev, pipe_id, queue_id);
468 act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
469 if (act) {
470 low = lower_32_bits(queue_address >> 8);
471 high = upper_32_bits(queue_address >> 8);
472
473 if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&
474 high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))
475 retval = true;
476 }
477 release_queue(adev);
478 return retval;
479}
480
481static bool hqd_sdma_is_occupied_v10_3(struct amdgpu_device *adev,
482 void *mqd)
483{
484 struct v10_sdma_mqd *m;
485 uint32_t sdma_rlc_reg_offset;
486 uint32_t sdma_rlc_rb_cntl;
487
488 m = get_sdma_mqd(mqd);
489 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
490 m->sdma_queue_id);
491
492 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
493
494 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
495 return true;
496
497 return false;
498}
499
500static int hqd_destroy_v10_3(struct amdgpu_device *adev, void *mqd,
501 enum kfd_preempt_type reset_type,
502 unsigned int utimeout, uint32_t pipe_id,
503 uint32_t queue_id, uint32_t inst)
504{
505 enum hqd_dequeue_request_type type;
506 unsigned long end_jiffies;
507 uint32_t temp;
508 struct v10_compute_mqd *m = get_mqd(mqd);
509
510 acquire_queue(adev, pipe_id, queue_id);
511
512 if (m->cp_hqd_vmid == 0)
513 WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0);
514
515 switch (reset_type) {
516 case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
517 type = DRAIN_PIPE;
518 break;
519 case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
520 type = RESET_WAVES;
521 break;
522 case KFD_PREEMPT_TYPE_WAVEFRONT_SAVE:
523 type = SAVE_WAVES;
524 break;
525 default:
526 type = DRAIN_PIPE;
527 break;
528 }
529
530 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, type);
531
532 end_jiffies = (utimeout * HZ / 1000) + jiffies;
533 while (true) {
534 temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
535 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
536 break;
537 if (time_after(jiffies, end_jiffies)) {
538 pr_err("cp queue pipe %d queue %d preemption failed\n",
539 pipe_id, queue_id);
540 release_queue(adev);
541 return -ETIME;
542 }
543 usleep_range(500, 1000);
544 }
545
546 release_queue(adev);
547 return 0;
548}
549
550static int hqd_sdma_destroy_v10_3(struct amdgpu_device *adev, void *mqd,
551 unsigned int utimeout)
552{
553 struct v10_sdma_mqd *m;
554 uint32_t sdma_rlc_reg_offset;
555 uint32_t temp;
556 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
557
558 m = get_sdma_mqd(mqd);
559 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
560 m->sdma_queue_id);
561
562 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
563 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
564 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
565
566 while (true) {
567 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
568 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
569 break;
570 if (time_after(jiffies, end_jiffies)) {
571 pr_err("SDMA RLC not idle in %s\n", __func__);
572 return -ETIME;
573 }
574 usleep_range(500, 1000);
575 }
576
577 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
578 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
579 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
580 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
581
582 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
583 m->sdmax_rlcx_rb_rptr_hi =
584 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);
585
586 return 0;
587}
588
589static int wave_control_execute_v10_3(struct amdgpu_device *adev,
590 uint32_t gfx_index_val,
591 uint32_t sq_cmd, uint32_t inst)
592{
593 uint32_t data = 0;
594
595 mutex_lock(&adev->grbm_idx_mutex);
596
597 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val);
598 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);
599
600 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
601 INSTANCE_BROADCAST_WRITES, 1);
602 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
603 SA_BROADCAST_WRITES, 1);
604 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
605 SE_BROADCAST_WRITES, 1);
606
607 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
608 mutex_unlock(&adev->grbm_idx_mutex);
609
610 return 0;
611}
612
613static bool get_atc_vmid_pasid_mapping_info_v10_3(struct amdgpu_device *adev,
614 uint8_t vmid, uint16_t *p_pasid)
615{
616 uint32_t value;
617
618 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
619 + vmid);
620 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
621
622 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
623}
624
625static void set_vm_context_page_table_base_v10_3(struct amdgpu_device *adev,
626 uint32_t vmid, uint64_t page_table_base)
627{
628 /* SDMA is on gfxhub as well for Navi1* series */
629 adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base);
630}
631
632static void program_trap_handler_settings_v10_3(struct amdgpu_device *adev,
633 uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr,
634 uint32_t inst)
635{
636 lock_srbm(adev, 0, 0, 0, vmid);
637
638 /*
639 * Program TBA registers
640 */
641 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO),
642 lower_32_bits(tba_addr >> 8));
643 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI),
644 upper_32_bits(tba_addr >> 8) |
645 (1 << SQ_SHADER_TBA_HI__TRAP_EN__SHIFT));
646
647 /*
648 * Program TMA registers
649 */
650 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO),
651 lower_32_bits(tma_addr >> 8));
652 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_HI),
653 upper_32_bits(tma_addr >> 8));
654
655 unlock_srbm(adev);
656}
657
658const struct kfd2kgd_calls gfx_v10_3_kfd2kgd = {
659 .program_sh_mem_settings = program_sh_mem_settings_v10_3,
660 .set_pasid_vmid_mapping = set_pasid_vmid_mapping_v10_3,
661 .init_interrupts = init_interrupts_v10_3,
662 .hqd_load = hqd_load_v10_3,
663 .hiq_mqd_load = hiq_mqd_load_v10_3,
664 .hqd_sdma_load = hqd_sdma_load_v10_3,
665 .hqd_dump = hqd_dump_v10_3,
666 .hqd_sdma_dump = hqd_sdma_dump_v10_3,
667 .hqd_is_occupied = hqd_is_occupied_v10_3,
668 .hqd_sdma_is_occupied = hqd_sdma_is_occupied_v10_3,
669 .hqd_destroy = hqd_destroy_v10_3,
670 .hqd_sdma_destroy = hqd_sdma_destroy_v10_3,
671 .wave_control_execute = wave_control_execute_v10_3,
672 .get_atc_vmid_pasid_mapping_info = get_atc_vmid_pasid_mapping_info_v10_3,
673 .set_vm_context_page_table_base = set_vm_context_page_table_base_v10_3,
674 .program_trap_handler_settings = program_trap_handler_settings_v10_3,
675 .get_iq_wait_times = kgd_gfx_v10_get_iq_wait_times,
676 .build_grace_period_packet_info = kgd_gfx_v10_build_grace_period_packet_info,
677 .enable_debug_trap = kgd_gfx_v10_enable_debug_trap,
678 .disable_debug_trap = kgd_gfx_v10_disable_debug_trap,
679 .validate_trap_override_request = kgd_gfx_v10_validate_trap_override_request,
680 .set_wave_launch_trap_override = kgd_gfx_v10_set_wave_launch_trap_override,
681 .set_wave_launch_mode = kgd_gfx_v10_set_wave_launch_mode,
682 .set_address_watch = kgd_gfx_v10_set_address_watch,
683 .clear_address_watch = kgd_gfx_v10_clear_address_watch
684};
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22#include <linux/mmu_context.h>
23#include "amdgpu.h"
24#include "amdgpu_amdkfd.h"
25#include "gc/gc_10_3_0_offset.h"
26#include "gc/gc_10_3_0_sh_mask.h"
27#include "oss/osssys_5_0_0_offset.h"
28#include "oss/osssys_5_0_0_sh_mask.h"
29#include "soc15_common.h"
30#include "v10_structs.h"
31#include "nv.h"
32#include "nvd.h"
33
34enum hqd_dequeue_request_type {
35 NO_ACTION = 0,
36 DRAIN_PIPE,
37 RESET_WAVES,
38 SAVE_WAVES
39};
40
41static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
42{
43 return (struct amdgpu_device *)kgd;
44}
45
46static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
47 uint32_t queue, uint32_t vmid)
48{
49 struct amdgpu_device *adev = get_amdgpu_device(kgd);
50
51 mutex_lock(&adev->srbm_mutex);
52 nv_grbm_select(adev, mec, pipe, queue, vmid);
53}
54
55static void unlock_srbm(struct kgd_dev *kgd)
56{
57 struct amdgpu_device *adev = get_amdgpu_device(kgd);
58
59 nv_grbm_select(adev, 0, 0, 0, 0);
60 mutex_unlock(&adev->srbm_mutex);
61}
62
63static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
64 uint32_t queue_id)
65{
66 struct amdgpu_device *adev = get_amdgpu_device(kgd);
67
68 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
69 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
70
71 lock_srbm(kgd, mec, pipe, queue_id, 0);
72}
73
74static uint64_t get_queue_mask(struct amdgpu_device *adev,
75 uint32_t pipe_id, uint32_t queue_id)
76{
77 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe +
78 queue_id;
79
80 return 1ull << bit;
81}
82
83static void release_queue(struct kgd_dev *kgd)
84{
85 unlock_srbm(kgd);
86}
87
88static void program_sh_mem_settings_v10_3(struct kgd_dev *kgd, uint32_t vmid,
89 uint32_t sh_mem_config,
90 uint32_t sh_mem_ape1_base,
91 uint32_t sh_mem_ape1_limit,
92 uint32_t sh_mem_bases)
93{
94 struct amdgpu_device *adev = get_amdgpu_device(kgd);
95
96 lock_srbm(kgd, 0, 0, 0, vmid);
97
98 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
99 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
100 /* APE1 no longer exists on GFX9 */
101
102 unlock_srbm(kgd);
103}
104
105/* ATC is defeatured on Sienna_Cichlid */
106static int set_pasid_vmid_mapping_v10_3(struct kgd_dev *kgd, unsigned int pasid,
107 unsigned int vmid)
108{
109 struct amdgpu_device *adev = get_amdgpu_device(kgd);
110
111 uint32_t value = pasid << IH_VMID_0_LUT__PASID__SHIFT;
112
113 /* Mapping vmid to pasid also for IH block */
114 pr_debug("mapping vmid %d -> pasid %d in IH block for GFX client\n",
115 vmid, pasid);
116 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, value);
117
118 return 0;
119}
120
121static int init_interrupts_v10_3(struct kgd_dev *kgd, uint32_t pipe_id)
122{
123 struct amdgpu_device *adev = get_amdgpu_device(kgd);
124 uint32_t mec;
125 uint32_t pipe;
126
127 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
128 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
129
130 lock_srbm(kgd, mec, pipe, 0, 0);
131
132 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL,
133 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
134 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
135
136 unlock_srbm(kgd);
137
138 return 0;
139}
140
141static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
142 unsigned int engine_id,
143 unsigned int queue_id)
144{
145 uint32_t sdma_engine_reg_base = 0;
146 uint32_t sdma_rlc_reg_offset;
147
148 switch (engine_id) {
149 default:
150 dev_warn(adev->dev,
151 "Invalid sdma engine id (%d), using engine id 0\n",
152 engine_id);
153 fallthrough;
154 case 0:
155 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
156 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
157 break;
158 case 1:
159 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
160 mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
161 break;
162 case 2:
163 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
164 mmSDMA2_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
165 break;
166 case 3:
167 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
168 mmSDMA3_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
169 break;
170 }
171
172 sdma_rlc_reg_offset = sdma_engine_reg_base
173 + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
174
175 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
176 queue_id, sdma_rlc_reg_offset);
177
178 return sdma_rlc_reg_offset;
179}
180
181static inline struct v10_compute_mqd *get_mqd(void *mqd)
182{
183 return (struct v10_compute_mqd *)mqd;
184}
185
186static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd)
187{
188 return (struct v10_sdma_mqd *)mqd;
189}
190
191static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
192 uint32_t queue_id, uint32_t __user *wptr,
193 uint32_t wptr_shift, uint32_t wptr_mask,
194 struct mm_struct *mm)
195{
196 struct amdgpu_device *adev = get_amdgpu_device(kgd);
197 struct v10_compute_mqd *m;
198 uint32_t *mqd_hqd;
199 uint32_t reg, hqd_base, data;
200
201 m = get_mqd(mqd);
202
203 pr_debug("Load hqd of pipe %d queue %d\n", pipe_id, queue_id);
204 acquire_queue(kgd, pipe_id, queue_id);
205
206 /* HIQ is set during driver init period with vmid set to 0*/
207 if (m->cp_hqd_vmid == 0) {
208 uint32_t value, mec, pipe;
209
210 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
211 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
212
213 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
214 mec, pipe, queue_id);
215 value = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
216 value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,
217 ((mec << 5) | (pipe << 3) | queue_id | 0x80));
218 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, value);
219 }
220
221 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */
222 mqd_hqd = &m->cp_mqd_base_addr_lo;
223 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
224
225 for (reg = hqd_base;
226 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
227 WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]);
228
229
230 /* Activate doorbell logic before triggering WPTR poll. */
231 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
232 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
233 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data);
234
235 if (wptr) {
236 /* Don't read wptr with get_user because the user
237 * context may not be accessible (if this function
238 * runs in a work queue). Instead trigger a one-shot
239 * polling read from memory in the CP. This assumes
240 * that wptr is GPU-accessible in the queue's VMID via
241 * ATC or SVM. WPTR==RPTR before starting the poll so
242 * the CP starts fetching new commands from the right
243 * place.
244 *
245 * Guessing a 64-bit WPTR from a 32-bit RPTR is a bit
246 * tricky. Assume that the queue didn't overflow. The
247 * number of valid bits in the 32-bit RPTR depends on
248 * the queue size. The remaining bits are taken from
249 * the saved 64-bit WPTR. If the WPTR wrapped, add the
250 * queue size.
251 */
252 uint32_t queue_size =
253 2 << REG_GET_FIELD(m->cp_hqd_pq_control,
254 CP_HQD_PQ_CONTROL, QUEUE_SIZE);
255 uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1);
256
257 if ((m->cp_hqd_pq_wptr_lo & (queue_size - 1)) < guessed_wptr)
258 guessed_wptr += queue_size;
259 guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);
260 guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
261
262 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
263 lower_32_bits(guessed_wptr));
264 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
265 upper_32_bits(guessed_wptr));
266 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
267 lower_32_bits((uint64_t)wptr));
268 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
269 upper_32_bits((uint64_t)wptr));
270 pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__,
271 (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
272 WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1,
273 (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
274 }
275
276 /* Start the EOP fetcher */
277 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),
278 REG_SET_FIELD(m->cp_hqd_eop_rptr,
279 CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
280
281 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
282 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data);
283
284 release_queue(kgd);
285
286 return 0;
287}
288
289static int hiq_mqd_load_v10_3(struct kgd_dev *kgd, void *mqd,
290 uint32_t pipe_id, uint32_t queue_id,
291 uint32_t doorbell_off)
292{
293 struct amdgpu_device *adev = get_amdgpu_device(kgd);
294 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
295 struct v10_compute_mqd *m;
296 uint32_t mec, pipe;
297 int r;
298
299 m = get_mqd(mqd);
300
301 acquire_queue(kgd, pipe_id, queue_id);
302
303 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
304 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
305
306 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
307 mec, pipe, queue_id);
308
309 spin_lock(&adev->gfx.kiq.ring_lock);
310 r = amdgpu_ring_alloc(kiq_ring, 7);
311 if (r) {
312 pr_err("Failed to alloc KIQ (%d).\n", r);
313 goto out_unlock;
314 }
315
316 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
317 amdgpu_ring_write(kiq_ring,
318 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
319 PACKET3_MAP_QUEUES_VMID(m->cp_hqd_vmid) | /* VMID */
320 PACKET3_MAP_QUEUES_QUEUE(queue_id) |
321 PACKET3_MAP_QUEUES_PIPE(pipe) |
322 PACKET3_MAP_QUEUES_ME((mec - 1)) |
323 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
324 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
325 PACKET3_MAP_QUEUES_ENGINE_SEL(1) | /* engine_sel: hiq */
326 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
327 amdgpu_ring_write(kiq_ring,
328 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(doorbell_off));
329 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo);
330 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi);
331 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo);
332 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi);
333 amdgpu_ring_commit(kiq_ring);
334
335out_unlock:
336 spin_unlock(&adev->gfx.kiq.ring_lock);
337 release_queue(kgd);
338
339 return r;
340}
341
342static int hqd_dump_v10_3(struct kgd_dev *kgd,
343 uint32_t pipe_id, uint32_t queue_id,
344 uint32_t (**dump)[2], uint32_t *n_regs)
345{
346 struct amdgpu_device *adev = get_amdgpu_device(kgd);
347 uint32_t i = 0, reg;
348#define HQD_N_REGS 56
349#define DUMP_REG(addr) do { \
350 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \
351 break; \
352 (*dump)[i][0] = (addr) << 2; \
353 (*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \
354 } while (0)
355
356 *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
357 if (*dump == NULL)
358 return -ENOMEM;
359
360 acquire_queue(kgd, pipe_id, queue_id);
361
362 for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
363 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
364 DUMP_REG(reg);
365
366 release_queue(kgd);
367
368 WARN_ON_ONCE(i != HQD_N_REGS);
369 *n_regs = i;
370
371 return 0;
372}
373
374static int hqd_sdma_load_v10_3(struct kgd_dev *kgd, void *mqd,
375 uint32_t __user *wptr, struct mm_struct *mm)
376{
377 struct amdgpu_device *adev = get_amdgpu_device(kgd);
378 struct v10_sdma_mqd *m;
379 uint32_t sdma_rlc_reg_offset;
380 unsigned long end_jiffies;
381 uint32_t data;
382 uint64_t data64;
383 uint64_t __user *wptr64 = (uint64_t __user *)wptr;
384
385 m = get_sdma_mqd(mqd);
386 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
387 m->sdma_queue_id);
388
389 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
390 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
391
392 end_jiffies = msecs_to_jiffies(2000) + jiffies;
393 while (true) {
394 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
395 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
396 break;
397 if (time_after(jiffies, end_jiffies)) {
398 pr_err("SDMA RLC not idle in %s\n", __func__);
399 return -ETIME;
400 }
401 usleep_range(500, 1000);
402 }
403
404 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
405 m->sdmax_rlcx_doorbell_offset);
406
407 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
408 ENABLE, 1);
409 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
410 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
411 m->sdmax_rlcx_rb_rptr);
412 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
413 m->sdmax_rlcx_rb_rptr_hi);
414
415 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
416 if (read_user_wptr(mm, wptr64, data64)) {
417 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
418 lower_32_bits(data64));
419 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
420 upper_32_bits(data64));
421 } else {
422 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
423 m->sdmax_rlcx_rb_rptr);
424 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
425 m->sdmax_rlcx_rb_rptr_hi);
426 }
427 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
428
429 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
430 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
431 m->sdmax_rlcx_rb_base_hi);
432 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
433 m->sdmax_rlcx_rb_rptr_addr_lo);
434 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
435 m->sdmax_rlcx_rb_rptr_addr_hi);
436
437 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
438 RB_ENABLE, 1);
439 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
440
441 return 0;
442}
443
444static int hqd_sdma_dump_v10_3(struct kgd_dev *kgd,
445 uint32_t engine_id, uint32_t queue_id,
446 uint32_t (**dump)[2], uint32_t *n_regs)
447{
448 struct amdgpu_device *adev = get_amdgpu_device(kgd);
449 uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
450 engine_id, queue_id);
451 uint32_t i = 0, reg;
452#undef HQD_N_REGS
453#define HQD_N_REGS (19+6+7+12)
454
455 *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
456 if (*dump == NULL)
457 return -ENOMEM;
458
459 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
460 DUMP_REG(sdma_rlc_reg_offset + reg);
461 for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
462 DUMP_REG(sdma_rlc_reg_offset + reg);
463 for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
464 reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
465 DUMP_REG(sdma_rlc_reg_offset + reg);
466 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
467 reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
468 DUMP_REG(sdma_rlc_reg_offset + reg);
469
470 WARN_ON_ONCE(i != HQD_N_REGS);
471 *n_regs = i;
472
473 return 0;
474}
475
476static bool hqd_is_occupied_v10_3(struct kgd_dev *kgd, uint64_t queue_address,
477 uint32_t pipe_id, uint32_t queue_id)
478{
479 struct amdgpu_device *adev = get_amdgpu_device(kgd);
480 uint32_t act;
481 bool retval = false;
482 uint32_t low, high;
483
484 acquire_queue(kgd, pipe_id, queue_id);
485 act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
486 if (act) {
487 low = lower_32_bits(queue_address >> 8);
488 high = upper_32_bits(queue_address >> 8);
489
490 if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&
491 high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))
492 retval = true;
493 }
494 release_queue(kgd);
495 return retval;
496}
497
498static bool hqd_sdma_is_occupied_v10_3(struct kgd_dev *kgd, void *mqd)
499{
500 struct amdgpu_device *adev = get_amdgpu_device(kgd);
501 struct v10_sdma_mqd *m;
502 uint32_t sdma_rlc_reg_offset;
503 uint32_t sdma_rlc_rb_cntl;
504
505 m = get_sdma_mqd(mqd);
506 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
507 m->sdma_queue_id);
508
509 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
510
511 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
512 return true;
513
514 return false;
515}
516
517static int hqd_destroy_v10_3(struct kgd_dev *kgd, void *mqd,
518 enum kfd_preempt_type reset_type,
519 unsigned int utimeout, uint32_t pipe_id,
520 uint32_t queue_id)
521{
522 struct amdgpu_device *adev = get_amdgpu_device(kgd);
523 enum hqd_dequeue_request_type type;
524 unsigned long end_jiffies;
525 uint32_t temp;
526 struct v10_compute_mqd *m = get_mqd(mqd);
527
528 acquire_queue(kgd, pipe_id, queue_id);
529
530 if (m->cp_hqd_vmid == 0)
531 WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0);
532
533 switch (reset_type) {
534 case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
535 type = DRAIN_PIPE;
536 break;
537 case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
538 type = RESET_WAVES;
539 break;
540 default:
541 type = DRAIN_PIPE;
542 break;
543 }
544
545 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, type);
546
547 end_jiffies = (utimeout * HZ / 1000) + jiffies;
548 while (true) {
549 temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
550 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
551 break;
552 if (time_after(jiffies, end_jiffies)) {
553 pr_err("cp queue pipe %d queue %d preemption failed\n",
554 pipe_id, queue_id);
555 release_queue(kgd);
556 return -ETIME;
557 }
558 usleep_range(500, 1000);
559 }
560
561 release_queue(kgd);
562 return 0;
563}
564
565static int hqd_sdma_destroy_v10_3(struct kgd_dev *kgd, void *mqd,
566 unsigned int utimeout)
567{
568 struct amdgpu_device *adev = get_amdgpu_device(kgd);
569 struct v10_sdma_mqd *m;
570 uint32_t sdma_rlc_reg_offset;
571 uint32_t temp;
572 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
573
574 m = get_sdma_mqd(mqd);
575 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
576 m->sdma_queue_id);
577
578 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
579 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
580 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
581
582 while (true) {
583 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
584 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
585 break;
586 if (time_after(jiffies, end_jiffies)) {
587 pr_err("SDMA RLC not idle in %s\n", __func__);
588 return -ETIME;
589 }
590 usleep_range(500, 1000);
591 }
592
593 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
594 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
595 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
596 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
597
598 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
599 m->sdmax_rlcx_rb_rptr_hi =
600 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);
601
602 return 0;
603}
604
605
606static int address_watch_disable_v10_3(struct kgd_dev *kgd)
607{
608 return 0;
609}
610
611static int address_watch_execute_v10_3(struct kgd_dev *kgd,
612 unsigned int watch_point_id,
613 uint32_t cntl_val,
614 uint32_t addr_hi,
615 uint32_t addr_lo)
616{
617 return 0;
618}
619
620static int wave_control_execute_v10_3(struct kgd_dev *kgd,
621 uint32_t gfx_index_val,
622 uint32_t sq_cmd)
623{
624 struct amdgpu_device *adev = get_amdgpu_device(kgd);
625 uint32_t data = 0;
626
627 mutex_lock(&adev->grbm_idx_mutex);
628
629 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val);
630 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);
631
632 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
633 INSTANCE_BROADCAST_WRITES, 1);
634 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
635 SA_BROADCAST_WRITES, 1);
636 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
637 SE_BROADCAST_WRITES, 1);
638
639 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
640 mutex_unlock(&adev->grbm_idx_mutex);
641
642 return 0;
643}
644
645static uint32_t address_watch_get_offset_v10_3(struct kgd_dev *kgd,
646 unsigned int watch_point_id,
647 unsigned int reg_offset)
648{
649 return 0;
650}
651
652static void set_vm_context_page_table_base_v10_3(struct kgd_dev *kgd, uint32_t vmid,
653 uint64_t page_table_base)
654{
655 struct amdgpu_device *adev = get_amdgpu_device(kgd);
656
657 /* SDMA is on gfxhub as well for Navi1* series */
658 adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base);
659}
660
661#if 0
662uint32_t enable_debug_trap_v10_3(struct kgd_dev *kgd,
663 uint32_t trap_debug_wave_launch_mode,
664 uint32_t vmid)
665{
666 struct amdgpu_device *adev = get_amdgpu_device(kgd);
667 uint32_t data = 0;
668 uint32_t orig_wave_cntl_value;
669 uint32_t orig_stall_vmid;
670
671 mutex_lock(&adev->grbm_idx_mutex);
672
673 orig_wave_cntl_value = RREG32(SOC15_REG_OFFSET(GC,
674 0,
675 mmSPI_GDBG_WAVE_CNTL));
676 orig_stall_vmid = REG_GET_FIELD(orig_wave_cntl_value,
677 SPI_GDBG_WAVE_CNTL,
678 STALL_VMID);
679
680 data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL, STALL_RA, 1);
681 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data);
682
683 data = 0;
684 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), data);
685
686 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), orig_stall_vmid);
687
688 mutex_unlock(&adev->grbm_idx_mutex);
689
690 return 0;
691}
692
693uint32_t disable_debug_trap_v10_3(struct kgd_dev *kgd)
694{
695 struct amdgpu_device *adev = get_amdgpu_device(kgd);
696
697 mutex_lock(&adev->grbm_idx_mutex);
698
699 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
700
701 mutex_unlock(&adev->grbm_idx_mutex);
702
703 return 0;
704}
705
706uint32_t set_wave_launch_trap_override_v10_3(struct kgd_dev *kgd,
707 uint32_t trap_override,
708 uint32_t trap_mask)
709{
710 struct amdgpu_device *adev = get_amdgpu_device(kgd);
711 uint32_t data = 0;
712
713 mutex_lock(&adev->grbm_idx_mutex);
714
715 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
716 data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL, STALL_RA, 1);
717 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data);
718
719 data = 0;
720 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_MASK,
721 EXCP_EN, trap_mask);
722 data = REG_SET_FIELD(data, SPI_GDBG_TRAP_MASK,
723 REPLACE, trap_override);
724 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), data);
725
726 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
727 data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL, STALL_RA, 0);
728 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data);
729
730 mutex_unlock(&adev->grbm_idx_mutex);
731
732 return 0;
733}
734
735uint32_t set_wave_launch_mode_v10_3(struct kgd_dev *kgd,
736 uint8_t wave_launch_mode,
737 uint32_t vmid)
738{
739 struct amdgpu_device *adev = get_amdgpu_device(kgd);
740 uint32_t data = 0;
741 bool is_stall_mode;
742 bool is_mode_set;
743
744 is_stall_mode = (wave_launch_mode == 4);
745 is_mode_set = (wave_launch_mode != 0 && wave_launch_mode != 4);
746
747 mutex_lock(&adev->grbm_idx_mutex);
748
749 data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL2,
750 VMID_MASK, is_mode_set ? 1 << vmid : 0);
751 data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL2,
752 MODE, is_mode_set ? wave_launch_mode : 0);
753 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL2), data);
754
755 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL));
756 data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL,
757 STALL_VMID, is_stall_mode ? 1 << vmid : 0);
758 data = REG_SET_FIELD(data, SPI_GDBG_WAVE_CNTL,
759 STALL_RA, is_stall_mode ? 1 : 0);
760 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data);
761
762 mutex_unlock(&adev->grbm_idx_mutex);
763
764 return 0;
765}
766
767/* kgd_get_iq_wait_times: Returns the mmCP_IQ_WAIT_TIME1/2 values
768 * The values read are:
769 * ib_offload_wait_time -- Wait Count for Indirect Buffer Offloads.
770 * atomic_offload_wait_time -- Wait Count for L2 and GDS Atomics Offloads.
771 * wrm_offload_wait_time -- Wait Count for WAIT_REG_MEM Offloads.
772 * gws_wait_time -- Wait Count for Global Wave Syncs.
773 * que_sleep_wait_time -- Wait Count for Dequeue Retry.
774 * sch_wave_wait_time -- Wait Count for Scheduling Wave Message.
775 * sem_rearm_wait_time -- Wait Count for Semaphore re-arm.
776 * deq_retry_wait_time -- Wait Count for Global Wave Syncs.
777 */
778void get_iq_wait_times_v10_3(struct kgd_dev *kgd,
779 uint32_t *wait_times)
780
781{
782 struct amdgpu_device *adev = get_amdgpu_device(kgd);
783
784 *wait_times = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2));
785}
786
787void build_grace_period_packet_info_v10_3(struct kgd_dev *kgd,
788 uint32_t wait_times,
789 uint32_t grace_period,
790 uint32_t *reg_offset,
791 uint32_t *reg_data)
792{
793 *reg_data = wait_times;
794
795 *reg_data = REG_SET_FIELD(*reg_data,
796 CP_IQ_WAIT_TIME2,
797 SCH_WAVE,
798 grace_period);
799
800 *reg_offset = mmCP_IQ_WAIT_TIME2;
801}
802#endif
803
804const struct kfd2kgd_calls gfx_v10_3_kfd2kgd = {
805 .program_sh_mem_settings = program_sh_mem_settings_v10_3,
806 .set_pasid_vmid_mapping = set_pasid_vmid_mapping_v10_3,
807 .init_interrupts = init_interrupts_v10_3,
808 .hqd_load = hqd_load_v10_3,
809 .hiq_mqd_load = hiq_mqd_load_v10_3,
810 .hqd_sdma_load = hqd_sdma_load_v10_3,
811 .hqd_dump = hqd_dump_v10_3,
812 .hqd_sdma_dump = hqd_sdma_dump_v10_3,
813 .hqd_is_occupied = hqd_is_occupied_v10_3,
814 .hqd_sdma_is_occupied = hqd_sdma_is_occupied_v10_3,
815 .hqd_destroy = hqd_destroy_v10_3,
816 .hqd_sdma_destroy = hqd_sdma_destroy_v10_3,
817 .address_watch_disable = address_watch_disable_v10_3,
818 .address_watch_execute = address_watch_execute_v10_3,
819 .wave_control_execute = wave_control_execute_v10_3,
820 .address_watch_get_offset = address_watch_get_offset_v10_3,
821 .get_atc_vmid_pasid_mapping_info = NULL,
822 .set_vm_context_page_table_base = set_vm_context_page_table_base_v10_3,
823#if 0
824 .enable_debug_trap = enable_debug_trap_v10_3,
825 .disable_debug_trap = disable_debug_trap_v10_3,
826 .set_wave_launch_trap_override = set_wave_launch_trap_override_v10_3,
827 .set_wave_launch_mode = set_wave_launch_mode_v10_3,
828 .get_iq_wait_times = get_iq_wait_times_v10_3,
829 .build_grace_period_packet_info = build_grace_period_packet_info_v10_3,
830#endif
831};