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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include "amdgpu.h"
30#include <drm/amdgpu_drm.h>
31#include <drm/drm_drv.h>
32#include <drm/drm_fb_helper.h>
33#include "amdgpu_uvd.h"
34#include "amdgpu_vce.h"
35#include "atom.h"
36
37#include <linux/vga_switcheroo.h>
38#include <linux/slab.h>
39#include <linux/uaccess.h>
40#include <linux/pci.h>
41#include <linux/pm_runtime.h>
42#include "amdgpu_amdkfd.h"
43#include "amdgpu_gem.h"
44#include "amdgpu_display.h"
45#include "amdgpu_ras.h"
46#include "amd_pcie.h"
47
48void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
49{
50 struct amdgpu_gpu_instance *gpu_instance;
51 int i;
52
53 mutex_lock(&mgpu_info.mutex);
54
55 for (i = 0; i < mgpu_info.num_gpu; i++) {
56 gpu_instance = &(mgpu_info.gpu_ins[i]);
57 if (gpu_instance->adev == adev) {
58 mgpu_info.gpu_ins[i] =
59 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
60 mgpu_info.num_gpu--;
61 if (adev->flags & AMD_IS_APU)
62 mgpu_info.num_apu--;
63 else
64 mgpu_info.num_dgpu--;
65 break;
66 }
67 }
68
69 mutex_unlock(&mgpu_info.mutex);
70}
71
72/**
73 * amdgpu_driver_unload_kms - Main unload function for KMS.
74 *
75 * @dev: drm dev pointer
76 *
77 * This is the main unload function for KMS (all asics).
78 * Returns 0 on success.
79 */
80void amdgpu_driver_unload_kms(struct drm_device *dev)
81{
82 struct amdgpu_device *adev = drm_to_adev(dev);
83
84 if (adev == NULL)
85 return;
86
87 amdgpu_unregister_gpu_instance(adev);
88
89 if (adev->rmmio == NULL)
90 return;
91
92 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
93 DRM_WARN("smart shift update failed\n");
94
95 amdgpu_acpi_fini(adev);
96 amdgpu_device_fini_hw(adev);
97}
98
99void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
100{
101 struct amdgpu_gpu_instance *gpu_instance;
102
103 mutex_lock(&mgpu_info.mutex);
104
105 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
106 DRM_ERROR("Cannot register more gpu instance\n");
107 mutex_unlock(&mgpu_info.mutex);
108 return;
109 }
110
111 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
112 gpu_instance->adev = adev;
113 gpu_instance->mgpu_fan_enabled = 0;
114
115 mgpu_info.num_gpu++;
116 if (adev->flags & AMD_IS_APU)
117 mgpu_info.num_apu++;
118 else
119 mgpu_info.num_dgpu++;
120
121 mutex_unlock(&mgpu_info.mutex);
122}
123
124/**
125 * amdgpu_driver_load_kms - Main load function for KMS.
126 *
127 * @adev: pointer to struct amdgpu_device
128 * @flags: device flags
129 *
130 * This is the main load function for KMS (all asics).
131 * Returns 0 on success, error on failure.
132 */
133int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
134{
135 struct drm_device *dev;
136 int r, acpi_status;
137
138 dev = adev_to_drm(adev);
139
140 /* amdgpu_device_init should report only fatal error
141 * like memory allocation failure or iomapping failure,
142 * or memory manager initialization failure, it must
143 * properly initialize the GPU MC controller and permit
144 * VRAM allocation
145 */
146 r = amdgpu_device_init(adev, flags);
147 if (r) {
148 dev_err(dev->dev, "Fatal error during GPU init\n");
149 goto out;
150 }
151
152 adev->pm.rpm_mode = AMDGPU_RUNPM_NONE;
153 if (amdgpu_device_supports_px(dev) &&
154 (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */
155 adev->pm.rpm_mode = AMDGPU_RUNPM_PX;
156 dev_info(adev->dev, "Using ATPX for runtime pm\n");
157 } else if (amdgpu_device_supports_boco(dev) &&
158 (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */
159 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO;
160 dev_info(adev->dev, "Using BOCO for runtime pm\n");
161 } else if (amdgpu_device_supports_baco(dev) &&
162 (amdgpu_runtime_pm != 0)) {
163 switch (adev->asic_type) {
164 case CHIP_VEGA20:
165 case CHIP_ARCTURUS:
166 /* enable BACO as runpm mode if runpm=1 */
167 if (amdgpu_runtime_pm > 0)
168 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
169 break;
170 case CHIP_VEGA10:
171 /* enable BACO as runpm mode if noretry=0 */
172 if (!adev->gmc.noretry)
173 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
174 break;
175 default:
176 /* enable BACO as runpm mode on CI+ */
177 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
178 break;
179 }
180
181 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)
182 dev_info(adev->dev, "Using BACO for runtime pm\n");
183 }
184
185 /* Call ACPI methods: require modeset init
186 * but failure is not fatal
187 */
188
189 acpi_status = amdgpu_acpi_init(adev);
190 if (acpi_status)
191 dev_dbg(dev->dev, "Error during ACPI methods call\n");
192
193 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
194 DRM_WARN("smart shift update failed\n");
195
196out:
197 if (r)
198 amdgpu_driver_unload_kms(dev);
199
200 return r;
201}
202
203static enum amd_ip_block_type
204 amdgpu_ip_get_block_type(struct amdgpu_device *adev, uint32_t ip)
205{
206 enum amd_ip_block_type type;
207
208 switch (ip) {
209 case AMDGPU_HW_IP_GFX:
210 type = AMD_IP_BLOCK_TYPE_GFX;
211 break;
212 case AMDGPU_HW_IP_COMPUTE:
213 type = AMD_IP_BLOCK_TYPE_GFX;
214 break;
215 case AMDGPU_HW_IP_DMA:
216 type = AMD_IP_BLOCK_TYPE_SDMA;
217 break;
218 case AMDGPU_HW_IP_UVD:
219 case AMDGPU_HW_IP_UVD_ENC:
220 type = AMD_IP_BLOCK_TYPE_UVD;
221 break;
222 case AMDGPU_HW_IP_VCE:
223 type = AMD_IP_BLOCK_TYPE_VCE;
224 break;
225 case AMDGPU_HW_IP_VCN_DEC:
226 case AMDGPU_HW_IP_VCN_ENC:
227 type = AMD_IP_BLOCK_TYPE_VCN;
228 break;
229 case AMDGPU_HW_IP_VCN_JPEG:
230 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
231 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
232 break;
233 default:
234 type = AMD_IP_BLOCK_TYPE_NUM;
235 break;
236 }
237
238 return type;
239}
240
241static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
242 struct drm_amdgpu_query_fw *query_fw,
243 struct amdgpu_device *adev)
244{
245 switch (query_fw->fw_type) {
246 case AMDGPU_INFO_FW_VCE:
247 fw_info->ver = adev->vce.fw_version;
248 fw_info->feature = adev->vce.fb_version;
249 break;
250 case AMDGPU_INFO_FW_UVD:
251 fw_info->ver = adev->uvd.fw_version;
252 fw_info->feature = 0;
253 break;
254 case AMDGPU_INFO_FW_VCN:
255 fw_info->ver = adev->vcn.fw_version;
256 fw_info->feature = 0;
257 break;
258 case AMDGPU_INFO_FW_GMC:
259 fw_info->ver = adev->gmc.fw_version;
260 fw_info->feature = 0;
261 break;
262 case AMDGPU_INFO_FW_GFX_ME:
263 fw_info->ver = adev->gfx.me_fw_version;
264 fw_info->feature = adev->gfx.me_feature_version;
265 break;
266 case AMDGPU_INFO_FW_GFX_PFP:
267 fw_info->ver = adev->gfx.pfp_fw_version;
268 fw_info->feature = adev->gfx.pfp_feature_version;
269 break;
270 case AMDGPU_INFO_FW_GFX_CE:
271 fw_info->ver = adev->gfx.ce_fw_version;
272 fw_info->feature = adev->gfx.ce_feature_version;
273 break;
274 case AMDGPU_INFO_FW_GFX_RLC:
275 fw_info->ver = adev->gfx.rlc_fw_version;
276 fw_info->feature = adev->gfx.rlc_feature_version;
277 break;
278 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
279 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
280 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
281 break;
282 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
283 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
284 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
285 break;
286 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
287 fw_info->ver = adev->gfx.rlc_srls_fw_version;
288 fw_info->feature = adev->gfx.rlc_srls_feature_version;
289 break;
290 case AMDGPU_INFO_FW_GFX_RLCP:
291 fw_info->ver = adev->gfx.rlcp_ucode_version;
292 fw_info->feature = adev->gfx.rlcp_ucode_feature_version;
293 break;
294 case AMDGPU_INFO_FW_GFX_RLCV:
295 fw_info->ver = adev->gfx.rlcv_ucode_version;
296 fw_info->feature = adev->gfx.rlcv_ucode_feature_version;
297 break;
298 case AMDGPU_INFO_FW_GFX_MEC:
299 if (query_fw->index == 0) {
300 fw_info->ver = adev->gfx.mec_fw_version;
301 fw_info->feature = adev->gfx.mec_feature_version;
302 } else if (query_fw->index == 1) {
303 fw_info->ver = adev->gfx.mec2_fw_version;
304 fw_info->feature = adev->gfx.mec2_feature_version;
305 } else
306 return -EINVAL;
307 break;
308 case AMDGPU_INFO_FW_SMC:
309 fw_info->ver = adev->pm.fw_version;
310 fw_info->feature = 0;
311 break;
312 case AMDGPU_INFO_FW_TA:
313 switch (query_fw->index) {
314 case TA_FW_TYPE_PSP_XGMI:
315 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version;
316 fw_info->feature = adev->psp.xgmi_context.context
317 .bin_desc.feature_version;
318 break;
319 case TA_FW_TYPE_PSP_RAS:
320 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version;
321 fw_info->feature = adev->psp.ras_context.context
322 .bin_desc.feature_version;
323 break;
324 case TA_FW_TYPE_PSP_HDCP:
325 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version;
326 fw_info->feature = adev->psp.hdcp_context.context
327 .bin_desc.feature_version;
328 break;
329 case TA_FW_TYPE_PSP_DTM:
330 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version;
331 fw_info->feature = adev->psp.dtm_context.context
332 .bin_desc.feature_version;
333 break;
334 case TA_FW_TYPE_PSP_RAP:
335 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version;
336 fw_info->feature = adev->psp.rap_context.context
337 .bin_desc.feature_version;
338 break;
339 case TA_FW_TYPE_PSP_SECUREDISPLAY:
340 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version;
341 fw_info->feature =
342 adev->psp.securedisplay_context.context.bin_desc
343 .feature_version;
344 break;
345 default:
346 return -EINVAL;
347 }
348 break;
349 case AMDGPU_INFO_FW_SDMA:
350 if (query_fw->index >= adev->sdma.num_instances)
351 return -EINVAL;
352 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
353 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
354 break;
355 case AMDGPU_INFO_FW_SOS:
356 fw_info->ver = adev->psp.sos.fw_version;
357 fw_info->feature = adev->psp.sos.feature_version;
358 break;
359 case AMDGPU_INFO_FW_ASD:
360 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version;
361 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version;
362 break;
363 case AMDGPU_INFO_FW_DMCU:
364 fw_info->ver = adev->dm.dmcu_fw_version;
365 fw_info->feature = 0;
366 break;
367 case AMDGPU_INFO_FW_DMCUB:
368 fw_info->ver = adev->dm.dmcub_fw_version;
369 fw_info->feature = 0;
370 break;
371 case AMDGPU_INFO_FW_TOC:
372 fw_info->ver = adev->psp.toc.fw_version;
373 fw_info->feature = adev->psp.toc.feature_version;
374 break;
375 case AMDGPU_INFO_FW_CAP:
376 fw_info->ver = adev->psp.cap_fw_version;
377 fw_info->feature = adev->psp.cap_feature_version;
378 break;
379 case AMDGPU_INFO_FW_MES_KIQ:
380 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK;
381 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK)
382 >> AMDGPU_MES_FEAT_VERSION_SHIFT;
383 break;
384 case AMDGPU_INFO_FW_MES:
385 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;
386 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK)
387 >> AMDGPU_MES_FEAT_VERSION_SHIFT;
388 break;
389 case AMDGPU_INFO_FW_IMU:
390 fw_info->ver = adev->gfx.imu_fw_version;
391 fw_info->feature = 0;
392 break;
393 case AMDGPU_INFO_FW_VPE:
394 fw_info->ver = adev->vpe.fw_version;
395 fw_info->feature = adev->vpe.feature_version;
396 break;
397 default:
398 return -EINVAL;
399 }
400 return 0;
401}
402
403static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
404 struct drm_amdgpu_info *info,
405 struct drm_amdgpu_info_hw_ip *result)
406{
407 uint32_t ib_start_alignment = 0;
408 uint32_t ib_size_alignment = 0;
409 enum amd_ip_block_type type;
410 unsigned int num_rings = 0;
411 unsigned int i, j;
412
413 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
414 return -EINVAL;
415
416 switch (info->query_hw_ip.type) {
417 case AMDGPU_HW_IP_GFX:
418 type = AMD_IP_BLOCK_TYPE_GFX;
419 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
420 if (adev->gfx.gfx_ring[i].sched.ready)
421 ++num_rings;
422 ib_start_alignment = 32;
423 ib_size_alignment = 32;
424 break;
425 case AMDGPU_HW_IP_COMPUTE:
426 type = AMD_IP_BLOCK_TYPE_GFX;
427 for (i = 0; i < adev->gfx.num_compute_rings; i++)
428 if (adev->gfx.compute_ring[i].sched.ready)
429 ++num_rings;
430 ib_start_alignment = 32;
431 ib_size_alignment = 32;
432 break;
433 case AMDGPU_HW_IP_DMA:
434 type = AMD_IP_BLOCK_TYPE_SDMA;
435 for (i = 0; i < adev->sdma.num_instances; i++)
436 if (adev->sdma.instance[i].ring.sched.ready)
437 ++num_rings;
438 ib_start_alignment = 256;
439 ib_size_alignment = 4;
440 break;
441 case AMDGPU_HW_IP_UVD:
442 type = AMD_IP_BLOCK_TYPE_UVD;
443 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
444 if (adev->uvd.harvest_config & (1 << i))
445 continue;
446
447 if (adev->uvd.inst[i].ring.sched.ready)
448 ++num_rings;
449 }
450 ib_start_alignment = 256;
451 ib_size_alignment = 64;
452 break;
453 case AMDGPU_HW_IP_VCE:
454 type = AMD_IP_BLOCK_TYPE_VCE;
455 for (i = 0; i < adev->vce.num_rings; i++)
456 if (adev->vce.ring[i].sched.ready)
457 ++num_rings;
458 ib_start_alignment = 256;
459 ib_size_alignment = 4;
460 break;
461 case AMDGPU_HW_IP_UVD_ENC:
462 type = AMD_IP_BLOCK_TYPE_UVD;
463 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
464 if (adev->uvd.harvest_config & (1 << i))
465 continue;
466
467 for (j = 0; j < adev->uvd.num_enc_rings; j++)
468 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
469 ++num_rings;
470 }
471 ib_start_alignment = 256;
472 ib_size_alignment = 4;
473 break;
474 case AMDGPU_HW_IP_VCN_DEC:
475 type = AMD_IP_BLOCK_TYPE_VCN;
476 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
477 if (adev->vcn.harvest_config & (1 << i))
478 continue;
479
480 if (adev->vcn.inst[i].ring_dec.sched.ready)
481 ++num_rings;
482 }
483 ib_start_alignment = 256;
484 ib_size_alignment = 64;
485 break;
486 case AMDGPU_HW_IP_VCN_ENC:
487 type = AMD_IP_BLOCK_TYPE_VCN;
488 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
489 if (adev->vcn.harvest_config & (1 << i))
490 continue;
491
492 for (j = 0; j < adev->vcn.num_enc_rings; j++)
493 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
494 ++num_rings;
495 }
496 ib_start_alignment = 256;
497 ib_size_alignment = 4;
498 break;
499 case AMDGPU_HW_IP_VCN_JPEG:
500 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
501 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
502
503 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
504 if (adev->jpeg.harvest_config & (1 << i))
505 continue;
506
507 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++)
508 if (adev->jpeg.inst[i].ring_dec[j].sched.ready)
509 ++num_rings;
510 }
511 ib_start_alignment = 256;
512 ib_size_alignment = 64;
513 break;
514 case AMDGPU_HW_IP_VPE:
515 type = AMD_IP_BLOCK_TYPE_VPE;
516 if (adev->vpe.ring.sched.ready)
517 ++num_rings;
518 ib_start_alignment = 256;
519 ib_size_alignment = 4;
520 break;
521 default:
522 return -EINVAL;
523 }
524
525 for (i = 0; i < adev->num_ip_blocks; i++)
526 if (adev->ip_blocks[i].version->type == type &&
527 adev->ip_blocks[i].status.valid)
528 break;
529
530 if (i == adev->num_ip_blocks)
531 return 0;
532
533 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
534 num_rings);
535
536 result->hw_ip_version_major = adev->ip_blocks[i].version->major;
537 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
538
539 if (adev->asic_type >= CHIP_VEGA10) {
540 switch (type) {
541 case AMD_IP_BLOCK_TYPE_GFX:
542 result->ip_discovery_version =
543 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, GC_HWIP, 0));
544 break;
545 case AMD_IP_BLOCK_TYPE_SDMA:
546 result->ip_discovery_version =
547 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, SDMA0_HWIP, 0));
548 break;
549 case AMD_IP_BLOCK_TYPE_UVD:
550 case AMD_IP_BLOCK_TYPE_VCN:
551 case AMD_IP_BLOCK_TYPE_JPEG:
552 result->ip_discovery_version =
553 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, UVD_HWIP, 0));
554 break;
555 case AMD_IP_BLOCK_TYPE_VCE:
556 result->ip_discovery_version =
557 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VCE_HWIP, 0));
558 break;
559 case AMD_IP_BLOCK_TYPE_VPE:
560 result->ip_discovery_version =
561 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VPE_HWIP, 0));
562 break;
563 default:
564 result->ip_discovery_version = 0;
565 break;
566 }
567 } else {
568 result->ip_discovery_version = 0;
569 }
570 result->capabilities_flags = 0;
571 result->available_rings = (1 << num_rings) - 1;
572 result->ib_start_alignment = ib_start_alignment;
573 result->ib_size_alignment = ib_size_alignment;
574 return 0;
575}
576
577/*
578 * Userspace get information ioctl
579 */
580/**
581 * amdgpu_info_ioctl - answer a device specific request.
582 *
583 * @dev: drm device pointer
584 * @data: request object
585 * @filp: drm filp
586 *
587 * This function is used to pass device specific parameters to the userspace
588 * drivers. Examples include: pci device id, pipeline parms, tiling params,
589 * etc. (all asics).
590 * Returns 0 on success, -EINVAL on failure.
591 */
592int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
593{
594 struct amdgpu_device *adev = drm_to_adev(dev);
595 struct drm_amdgpu_info *info = data;
596 struct amdgpu_mode_info *minfo = &adev->mode_info;
597 void __user *out = (void __user *)(uintptr_t)info->return_pointer;
598 struct amdgpu_fpriv *fpriv;
599 struct amdgpu_ip_block *ip_block;
600 enum amd_ip_block_type type;
601 struct amdgpu_xcp *xcp;
602 u32 count, inst_mask;
603 uint32_t size = info->return_size;
604 struct drm_crtc *crtc;
605 uint32_t ui32 = 0;
606 uint64_t ui64 = 0;
607 int i, found, ret;
608 int ui32_size = sizeof(ui32);
609
610 if (!info->return_size || !info->return_pointer)
611 return -EINVAL;
612
613 switch (info->query) {
614 case AMDGPU_INFO_ACCEL_WORKING:
615 ui32 = adev->accel_working;
616 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
617 case AMDGPU_INFO_CRTC_FROM_ID:
618 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
619 crtc = (struct drm_crtc *)minfo->crtcs[i];
620 if (crtc && crtc->base.id == info->mode_crtc.id) {
621 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
622
623 ui32 = amdgpu_crtc->crtc_id;
624 found = 1;
625 break;
626 }
627 }
628 if (!found) {
629 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
630 return -EINVAL;
631 }
632 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
633 case AMDGPU_INFO_HW_IP_INFO: {
634 struct drm_amdgpu_info_hw_ip ip = {};
635
636 ret = amdgpu_hw_ip_info(adev, info, &ip);
637 if (ret)
638 return ret;
639
640 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip)));
641 return ret ? -EFAULT : 0;
642 }
643 case AMDGPU_INFO_HW_IP_COUNT: {
644 fpriv = (struct amdgpu_fpriv *)filp->driver_priv;
645 type = amdgpu_ip_get_block_type(adev, info->query_hw_ip.type);
646 ip_block = amdgpu_device_ip_get_ip_block(adev, type);
647
648 if (!ip_block || !ip_block->status.valid)
649 return -EINVAL;
650
651 if (adev->xcp_mgr && adev->xcp_mgr->num_xcps > 0 &&
652 fpriv->xcp_id >= 0 && fpriv->xcp_id < adev->xcp_mgr->num_xcps) {
653 xcp = &adev->xcp_mgr->xcp[fpriv->xcp_id];
654 switch (type) {
655 case AMD_IP_BLOCK_TYPE_GFX:
656 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask);
657 count = hweight32(inst_mask);
658 break;
659 case AMD_IP_BLOCK_TYPE_SDMA:
660 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_SDMA, &inst_mask);
661 count = hweight32(inst_mask);
662 break;
663 case AMD_IP_BLOCK_TYPE_JPEG:
664 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
665 count = hweight32(inst_mask) * adev->jpeg.num_jpeg_rings;
666 break;
667 case AMD_IP_BLOCK_TYPE_VCN:
668 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
669 count = hweight32(inst_mask);
670 break;
671 default:
672 return -EINVAL;
673 }
674 if (ret)
675 return ret;
676 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
677 }
678
679 switch (type) {
680 case AMD_IP_BLOCK_TYPE_GFX:
681 case AMD_IP_BLOCK_TYPE_VCE:
682 count = 1;
683 break;
684 case AMD_IP_BLOCK_TYPE_SDMA:
685 count = adev->sdma.num_instances;
686 break;
687 case AMD_IP_BLOCK_TYPE_JPEG:
688 count = adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings;
689 break;
690 case AMD_IP_BLOCK_TYPE_VCN:
691 count = adev->vcn.num_vcn_inst;
692 break;
693 case AMD_IP_BLOCK_TYPE_UVD:
694 count = adev->uvd.num_uvd_inst;
695 break;
696 /* For all other IP block types not listed in the switch statement
697 * the ip status is valid here and the instance count is one.
698 */
699 default:
700 count = 1;
701 break;
702 }
703
704 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
705 }
706 case AMDGPU_INFO_TIMESTAMP:
707 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
708 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
709 case AMDGPU_INFO_FW_VERSION: {
710 struct drm_amdgpu_info_firmware fw_info;
711
712 /* We only support one instance of each IP block right now. */
713 if (info->query_fw.ip_instance != 0)
714 return -EINVAL;
715
716 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
717 if (ret)
718 return ret;
719
720 return copy_to_user(out, &fw_info,
721 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
722 }
723 case AMDGPU_INFO_NUM_BYTES_MOVED:
724 ui64 = atomic64_read(&adev->num_bytes_moved);
725 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
726 case AMDGPU_INFO_NUM_EVICTIONS:
727 ui64 = atomic64_read(&adev->num_evictions);
728 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
729 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
730 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
731 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
732 case AMDGPU_INFO_VRAM_USAGE:
733 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
734 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
735 case AMDGPU_INFO_VIS_VRAM_USAGE:
736 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
737 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
738 case AMDGPU_INFO_GTT_USAGE:
739 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager);
740 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
741 case AMDGPU_INFO_GDS_CONFIG: {
742 struct drm_amdgpu_info_gds gds_info;
743
744 memset(&gds_info, 0, sizeof(gds_info));
745 gds_info.compute_partition_size = adev->gds.gds_size;
746 gds_info.gds_total_size = adev->gds.gds_size;
747 gds_info.gws_per_compute_partition = adev->gds.gws_size;
748 gds_info.oa_per_compute_partition = adev->gds.oa_size;
749 return copy_to_user(out, &gds_info,
750 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
751 }
752 case AMDGPU_INFO_VRAM_GTT: {
753 struct drm_amdgpu_info_vram_gtt vram_gtt;
754
755 vram_gtt.vram_size = adev->gmc.real_vram_size -
756 atomic64_read(&adev->vram_pin_size) -
757 AMDGPU_VM_RESERVED_VRAM;
758 vram_gtt.vram_cpu_accessible_size =
759 min(adev->gmc.visible_vram_size -
760 atomic64_read(&adev->visible_pin_size),
761 vram_gtt.vram_size);
762 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
763 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
764 return copy_to_user(out, &vram_gtt,
765 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
766 }
767 case AMDGPU_INFO_MEMORY: {
768 struct drm_amdgpu_memory_info mem;
769 struct ttm_resource_manager *gtt_man =
770 &adev->mman.gtt_mgr.manager;
771 struct ttm_resource_manager *vram_man =
772 &adev->mman.vram_mgr.manager;
773
774 memset(&mem, 0, sizeof(mem));
775 mem.vram.total_heap_size = adev->gmc.real_vram_size;
776 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
777 atomic64_read(&adev->vram_pin_size) -
778 AMDGPU_VM_RESERVED_VRAM;
779 mem.vram.heap_usage =
780 ttm_resource_manager_usage(vram_man);
781 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
782
783 mem.cpu_accessible_vram.total_heap_size =
784 adev->gmc.visible_vram_size;
785 mem.cpu_accessible_vram.usable_heap_size =
786 min(adev->gmc.visible_vram_size -
787 atomic64_read(&adev->visible_pin_size),
788 mem.vram.usable_heap_size);
789 mem.cpu_accessible_vram.heap_usage =
790 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
791 mem.cpu_accessible_vram.max_allocation =
792 mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
793
794 mem.gtt.total_heap_size = gtt_man->size;
795 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
796 atomic64_read(&adev->gart_pin_size);
797 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man);
798 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
799
800 return copy_to_user(out, &mem,
801 min((size_t)size, sizeof(mem)))
802 ? -EFAULT : 0;
803 }
804 case AMDGPU_INFO_READ_MMR_REG: {
805 unsigned int n, alloc_size;
806 uint32_t *regs;
807 unsigned int se_num = (info->read_mmr_reg.instance >>
808 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
809 AMDGPU_INFO_MMR_SE_INDEX_MASK;
810 unsigned int sh_num = (info->read_mmr_reg.instance >>
811 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
812 AMDGPU_INFO_MMR_SH_INDEX_MASK;
813
814 /* set full masks if the userspace set all bits
815 * in the bitfields
816 */
817 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
818 se_num = 0xffffffff;
819 else if (se_num >= AMDGPU_GFX_MAX_SE)
820 return -EINVAL;
821 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
822 sh_num = 0xffffffff;
823 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
824 return -EINVAL;
825
826 if (info->read_mmr_reg.count > 128)
827 return -EINVAL;
828
829 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
830 if (!regs)
831 return -ENOMEM;
832 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
833
834 amdgpu_gfx_off_ctrl(adev, false);
835 for (i = 0; i < info->read_mmr_reg.count; i++) {
836 if (amdgpu_asic_read_register(adev, se_num, sh_num,
837 info->read_mmr_reg.dword_offset + i,
838 ®s[i])) {
839 DRM_DEBUG_KMS("unallowed offset %#x\n",
840 info->read_mmr_reg.dword_offset + i);
841 kfree(regs);
842 amdgpu_gfx_off_ctrl(adev, true);
843 return -EFAULT;
844 }
845 }
846 amdgpu_gfx_off_ctrl(adev, true);
847 n = copy_to_user(out, regs, min(size, alloc_size));
848 kfree(regs);
849 return n ? -EFAULT : 0;
850 }
851 case AMDGPU_INFO_DEV_INFO: {
852 struct drm_amdgpu_info_device *dev_info;
853 uint64_t vm_size;
854 uint32_t pcie_gen_mask;
855
856 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
857 if (!dev_info)
858 return -ENOMEM;
859
860 dev_info->device_id = adev->pdev->device;
861 dev_info->chip_rev = adev->rev_id;
862 dev_info->external_rev = adev->external_rev_id;
863 dev_info->pci_rev = adev->pdev->revision;
864 dev_info->family = adev->family;
865 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
866 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
867 /* return all clocks in KHz */
868 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
869 if (adev->pm.dpm_enabled) {
870 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
871 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
872 dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10;
873 dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10;
874 } else {
875 dev_info->max_engine_clock =
876 dev_info->min_engine_clock =
877 adev->clock.default_sclk * 10;
878 dev_info->max_memory_clock =
879 dev_info->min_memory_clock =
880 adev->clock.default_mclk * 10;
881 }
882 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
883 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
884 adev->gfx.config.max_shader_engines;
885 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
886 dev_info->ids_flags = 0;
887 if (adev->flags & AMD_IS_APU)
888 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
889 if (adev->gfx.mcbp)
890 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
891 if (amdgpu_is_tmz(adev))
892 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
893 if (adev->gfx.config.ta_cntl2_truncate_coord_mode)
894 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD;
895
896 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
897 vm_size -= AMDGPU_VA_RESERVED_TOP;
898
899 /* Older VCE FW versions are buggy and can handle only 40bits */
900 if (adev->vce.fw_version &&
901 adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
902 vm_size = min(vm_size, 1ULL << 40);
903
904 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_BOTTOM;
905 dev_info->virtual_address_max =
906 min(vm_size, AMDGPU_GMC_HOLE_START);
907
908 if (vm_size > AMDGPU_GMC_HOLE_START) {
909 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
910 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
911 }
912 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
913 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
914 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
915 dev_info->cu_active_number = adev->gfx.cu_info.number;
916 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
917 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
918 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
919 sizeof(adev->gfx.cu_info.ao_cu_bitmap));
920 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
921 sizeof(dev_info->cu_bitmap));
922 dev_info->vram_type = adev->gmc.vram_type;
923 dev_info->vram_bit_width = adev->gmc.vram_width;
924 dev_info->vce_harvest_config = adev->vce.harvest_config;
925 dev_info->gc_double_offchip_lds_buf =
926 adev->gfx.config.double_offchip_lds_buf;
927 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
928 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
929 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
930 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
931 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
932 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
933 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
934
935 if (adev->family >= AMDGPU_FAMILY_NV)
936 dev_info->pa_sc_tile_steering_override =
937 adev->gfx.config.pa_sc_tile_steering_override;
938
939 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
940
941 /* Combine the chip gen mask with the platform (CPU/mobo) mask. */
942 pcie_gen_mask = adev->pm.pcie_gen_mask & (adev->pm.pcie_gen_mask >> 16);
943 dev_info->pcie_gen = fls(pcie_gen_mask);
944 dev_info->pcie_num_lanes =
945 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 :
946 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 :
947 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 :
948 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 :
949 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 :
950 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1;
951
952 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size;
953 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp;
954 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;
955 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;
956 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance *
957 adev->gfx.config.gc_gl1c_per_sa;
958 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu;
959 dev_info->mall_size = adev->gmc.mall_size;
960
961
962 if (adev->gfx.funcs->get_gfx_shadow_info) {
963 struct amdgpu_gfx_shadow_info shadow_info;
964
965 ret = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info);
966 if (!ret) {
967 dev_info->shadow_size = shadow_info.shadow_size;
968 dev_info->shadow_alignment = shadow_info.shadow_alignment;
969 dev_info->csa_size = shadow_info.csa_size;
970 dev_info->csa_alignment = shadow_info.csa_alignment;
971 }
972 }
973
974 ret = copy_to_user(out, dev_info,
975 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
976 kfree(dev_info);
977 return ret;
978 }
979 case AMDGPU_INFO_VCE_CLOCK_TABLE: {
980 unsigned int i;
981 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
982 struct amd_vce_state *vce_state;
983
984 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
985 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
986 if (vce_state) {
987 vce_clk_table.entries[i].sclk = vce_state->sclk;
988 vce_clk_table.entries[i].mclk = vce_state->mclk;
989 vce_clk_table.entries[i].eclk = vce_state->evclk;
990 vce_clk_table.num_valid_entries++;
991 }
992 }
993
994 return copy_to_user(out, &vce_clk_table,
995 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
996 }
997 case AMDGPU_INFO_VBIOS: {
998 uint32_t bios_size = adev->bios_size;
999
1000 switch (info->vbios_info.type) {
1001 case AMDGPU_INFO_VBIOS_SIZE:
1002 return copy_to_user(out, &bios_size,
1003 min((size_t)size, sizeof(bios_size)))
1004 ? -EFAULT : 0;
1005 case AMDGPU_INFO_VBIOS_IMAGE: {
1006 uint8_t *bios;
1007 uint32_t bios_offset = info->vbios_info.offset;
1008
1009 if (bios_offset >= bios_size)
1010 return -EINVAL;
1011
1012 bios = adev->bios + bios_offset;
1013 return copy_to_user(out, bios,
1014 min((size_t)size, (size_t)(bios_size - bios_offset)))
1015 ? -EFAULT : 0;
1016 }
1017 case AMDGPU_INFO_VBIOS_INFO: {
1018 struct drm_amdgpu_info_vbios vbios_info = {};
1019 struct atom_context *atom_context;
1020
1021 atom_context = adev->mode_info.atom_context;
1022 if (atom_context) {
1023 memcpy(vbios_info.name, atom_context->name,
1024 sizeof(atom_context->name));
1025 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn,
1026 sizeof(atom_context->vbios_pn));
1027 vbios_info.version = atom_context->version;
1028 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
1029 sizeof(atom_context->vbios_ver_str));
1030 memcpy(vbios_info.date, atom_context->date,
1031 sizeof(atom_context->date));
1032 }
1033
1034 return copy_to_user(out, &vbios_info,
1035 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
1036 }
1037 default:
1038 DRM_DEBUG_KMS("Invalid request %d\n",
1039 info->vbios_info.type);
1040 return -EINVAL;
1041 }
1042 }
1043 case AMDGPU_INFO_NUM_HANDLES: {
1044 struct drm_amdgpu_info_num_handles handle;
1045
1046 switch (info->query_hw_ip.type) {
1047 case AMDGPU_HW_IP_UVD:
1048 /* Starting Polaris, we support unlimited UVD handles */
1049 if (adev->asic_type < CHIP_POLARIS10) {
1050 handle.uvd_max_handles = adev->uvd.max_handles;
1051 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
1052
1053 return copy_to_user(out, &handle,
1054 min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
1055 } else {
1056 return -ENODATA;
1057 }
1058
1059 break;
1060 default:
1061 return -EINVAL;
1062 }
1063 }
1064 case AMDGPU_INFO_SENSOR: {
1065 if (!adev->pm.dpm_enabled)
1066 return -ENOENT;
1067
1068 switch (info->sensor_info.type) {
1069 case AMDGPU_INFO_SENSOR_GFX_SCLK:
1070 /* get sclk in Mhz */
1071 if (amdgpu_dpm_read_sensor(adev,
1072 AMDGPU_PP_SENSOR_GFX_SCLK,
1073 (void *)&ui32, &ui32_size)) {
1074 return -EINVAL;
1075 }
1076 ui32 /= 100;
1077 break;
1078 case AMDGPU_INFO_SENSOR_GFX_MCLK:
1079 /* get mclk in Mhz */
1080 if (amdgpu_dpm_read_sensor(adev,
1081 AMDGPU_PP_SENSOR_GFX_MCLK,
1082 (void *)&ui32, &ui32_size)) {
1083 return -EINVAL;
1084 }
1085 ui32 /= 100;
1086 break;
1087 case AMDGPU_INFO_SENSOR_GPU_TEMP:
1088 /* get temperature in millidegrees C */
1089 if (amdgpu_dpm_read_sensor(adev,
1090 AMDGPU_PP_SENSOR_GPU_TEMP,
1091 (void *)&ui32, &ui32_size)) {
1092 return -EINVAL;
1093 }
1094 break;
1095 case AMDGPU_INFO_SENSOR_GPU_LOAD:
1096 /* get GPU load */
1097 if (amdgpu_dpm_read_sensor(adev,
1098 AMDGPU_PP_SENSOR_GPU_LOAD,
1099 (void *)&ui32, &ui32_size)) {
1100 return -EINVAL;
1101 }
1102 break;
1103 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
1104 /* get average GPU power */
1105 if (amdgpu_dpm_read_sensor(adev,
1106 AMDGPU_PP_SENSOR_GPU_AVG_POWER,
1107 (void *)&ui32, &ui32_size)) {
1108 /* fall back to input power for backwards compat */
1109 if (amdgpu_dpm_read_sensor(adev,
1110 AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
1111 (void *)&ui32, &ui32_size)) {
1112 return -EINVAL;
1113 }
1114 }
1115 ui32 >>= 8;
1116 break;
1117 case AMDGPU_INFO_SENSOR_GPU_INPUT_POWER:
1118 /* get input GPU power */
1119 if (amdgpu_dpm_read_sensor(adev,
1120 AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
1121 (void *)&ui32, &ui32_size)) {
1122 return -EINVAL;
1123 }
1124 ui32 >>= 8;
1125 break;
1126 case AMDGPU_INFO_SENSOR_VDDNB:
1127 /* get VDDNB in millivolts */
1128 if (amdgpu_dpm_read_sensor(adev,
1129 AMDGPU_PP_SENSOR_VDDNB,
1130 (void *)&ui32, &ui32_size)) {
1131 return -EINVAL;
1132 }
1133 break;
1134 case AMDGPU_INFO_SENSOR_VDDGFX:
1135 /* get VDDGFX in millivolts */
1136 if (amdgpu_dpm_read_sensor(adev,
1137 AMDGPU_PP_SENSOR_VDDGFX,
1138 (void *)&ui32, &ui32_size)) {
1139 return -EINVAL;
1140 }
1141 break;
1142 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
1143 /* get stable pstate sclk in Mhz */
1144 if (amdgpu_dpm_read_sensor(adev,
1145 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
1146 (void *)&ui32, &ui32_size)) {
1147 return -EINVAL;
1148 }
1149 ui32 /= 100;
1150 break;
1151 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
1152 /* get stable pstate mclk in Mhz */
1153 if (amdgpu_dpm_read_sensor(adev,
1154 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
1155 (void *)&ui32, &ui32_size)) {
1156 return -EINVAL;
1157 }
1158 ui32 /= 100;
1159 break;
1160 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK:
1161 /* get peak pstate sclk in Mhz */
1162 if (amdgpu_dpm_read_sensor(adev,
1163 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
1164 (void *)&ui32, &ui32_size)) {
1165 return -EINVAL;
1166 }
1167 ui32 /= 100;
1168 break;
1169 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK:
1170 /* get peak pstate mclk in Mhz */
1171 if (amdgpu_dpm_read_sensor(adev,
1172 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
1173 (void *)&ui32, &ui32_size)) {
1174 return -EINVAL;
1175 }
1176 ui32 /= 100;
1177 break;
1178 default:
1179 DRM_DEBUG_KMS("Invalid request %d\n",
1180 info->sensor_info.type);
1181 return -EINVAL;
1182 }
1183 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1184 }
1185 case AMDGPU_INFO_VRAM_LOST_COUNTER:
1186 ui32 = atomic_read(&adev->vram_lost_counter);
1187 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1188 case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1189 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1190 uint64_t ras_mask;
1191
1192 if (!ras)
1193 return -EINVAL;
1194 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1195
1196 return copy_to_user(out, &ras_mask,
1197 min_t(u64, size, sizeof(ras_mask))) ?
1198 -EFAULT : 0;
1199 }
1200 case AMDGPU_INFO_VIDEO_CAPS: {
1201 const struct amdgpu_video_codecs *codecs;
1202 struct drm_amdgpu_info_video_caps *caps;
1203 int r;
1204
1205 if (!adev->asic_funcs->query_video_codecs)
1206 return -EINVAL;
1207
1208 switch (info->video_cap.type) {
1209 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1210 r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1211 if (r)
1212 return -EINVAL;
1213 break;
1214 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1215 r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1216 if (r)
1217 return -EINVAL;
1218 break;
1219 default:
1220 DRM_DEBUG_KMS("Invalid request %d\n",
1221 info->video_cap.type);
1222 return -EINVAL;
1223 }
1224
1225 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1226 if (!caps)
1227 return -ENOMEM;
1228
1229 for (i = 0; i < codecs->codec_count; i++) {
1230 int idx = codecs->codec_array[i].codec_type;
1231
1232 switch (idx) {
1233 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1234 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1235 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1236 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1237 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1238 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1239 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1240 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1241 caps->codec_info[idx].valid = 1;
1242 caps->codec_info[idx].max_width =
1243 codecs->codec_array[i].max_width;
1244 caps->codec_info[idx].max_height =
1245 codecs->codec_array[i].max_height;
1246 caps->codec_info[idx].max_pixels_per_frame =
1247 codecs->codec_array[i].max_pixels_per_frame;
1248 caps->codec_info[idx].max_level =
1249 codecs->codec_array[i].max_level;
1250 break;
1251 default:
1252 break;
1253 }
1254 }
1255 r = copy_to_user(out, caps,
1256 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1257 kfree(caps);
1258 return r;
1259 }
1260 case AMDGPU_INFO_MAX_IBS: {
1261 uint32_t max_ibs[AMDGPU_HW_IP_NUM];
1262
1263 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i)
1264 max_ibs[i] = amdgpu_ring_max_ibs(i);
1265
1266 return copy_to_user(out, max_ibs,
1267 min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0;
1268 }
1269 case AMDGPU_INFO_GPUVM_FAULT: {
1270 struct amdgpu_fpriv *fpriv = filp->driver_priv;
1271 struct amdgpu_vm *vm = &fpriv->vm;
1272 struct drm_amdgpu_info_gpuvm_fault gpuvm_fault;
1273 unsigned long flags;
1274
1275 if (!vm)
1276 return -EINVAL;
1277
1278 memset(&gpuvm_fault, 0, sizeof(gpuvm_fault));
1279
1280 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
1281 gpuvm_fault.addr = vm->fault_info.addr;
1282 gpuvm_fault.status = vm->fault_info.status;
1283 gpuvm_fault.vmhub = vm->fault_info.vmhub;
1284 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
1285
1286 return copy_to_user(out, &gpuvm_fault,
1287 min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0;
1288 }
1289 default:
1290 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1291 return -EINVAL;
1292 }
1293 return 0;
1294}
1295
1296
1297/*
1298 * Outdated mess for old drm with Xorg being in charge (void function now).
1299 */
1300/**
1301 * amdgpu_driver_lastclose_kms - drm callback for last close
1302 *
1303 * @dev: drm dev pointer
1304 *
1305 * Switch vga_switcheroo state after last close (all asics).
1306 */
1307void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1308{
1309 drm_fb_helper_lastclose(dev);
1310 vga_switcheroo_process_delayed_switch();
1311}
1312
1313/**
1314 * amdgpu_driver_open_kms - drm callback for open
1315 *
1316 * @dev: drm dev pointer
1317 * @file_priv: drm file
1318 *
1319 * On device open, init vm on cayman+ (all asics).
1320 * Returns 0 on success, error on failure.
1321 */
1322int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1323{
1324 struct amdgpu_device *adev = drm_to_adev(dev);
1325 struct amdgpu_fpriv *fpriv;
1326 int r, pasid;
1327
1328 /* Ensure IB tests are run on ring */
1329 flush_delayed_work(&adev->delayed_init_work);
1330
1331
1332 if (amdgpu_ras_intr_triggered()) {
1333 DRM_ERROR("RAS Intr triggered, device disabled!!");
1334 return -EHWPOISON;
1335 }
1336
1337 file_priv->driver_priv = NULL;
1338
1339 r = pm_runtime_get_sync(dev->dev);
1340 if (r < 0)
1341 goto pm_put;
1342
1343 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1344 if (unlikely(!fpriv)) {
1345 r = -ENOMEM;
1346 goto out_suspend;
1347 }
1348
1349 pasid = amdgpu_pasid_alloc(16);
1350 if (pasid < 0) {
1351 dev_warn(adev->dev, "No more PASIDs available!");
1352 pasid = 0;
1353 }
1354
1355 r = amdgpu_xcp_open_device(adev, fpriv, file_priv);
1356 if (r)
1357 goto error_pasid;
1358
1359 r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id);
1360 if (r)
1361 goto error_pasid;
1362
1363 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid);
1364 if (r)
1365 goto error_vm;
1366
1367 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1368 if (!fpriv->prt_va) {
1369 r = -ENOMEM;
1370 goto error_vm;
1371 }
1372
1373 if (adev->gfx.mcbp) {
1374 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1375
1376 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1377 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1378 if (r)
1379 goto error_vm;
1380 }
1381
1382 r = amdgpu_seq64_map(adev, &fpriv->vm, &fpriv->seq64_va);
1383 if (r)
1384 goto error_vm;
1385
1386 mutex_init(&fpriv->bo_list_lock);
1387 idr_init_base(&fpriv->bo_list_handles, 1);
1388
1389 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev);
1390
1391 file_priv->driver_priv = fpriv;
1392 goto out_suspend;
1393
1394error_vm:
1395 amdgpu_vm_fini(adev, &fpriv->vm);
1396
1397error_pasid:
1398 if (pasid) {
1399 amdgpu_pasid_free(pasid);
1400 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0);
1401 }
1402
1403 kfree(fpriv);
1404
1405out_suspend:
1406 pm_runtime_mark_last_busy(dev->dev);
1407pm_put:
1408 pm_runtime_put_autosuspend(dev->dev);
1409
1410 return r;
1411}
1412
1413/**
1414 * amdgpu_driver_postclose_kms - drm callback for post close
1415 *
1416 * @dev: drm dev pointer
1417 * @file_priv: drm file
1418 *
1419 * On device post close, tear down vm on cayman+ (all asics).
1420 */
1421void amdgpu_driver_postclose_kms(struct drm_device *dev,
1422 struct drm_file *file_priv)
1423{
1424 struct amdgpu_device *adev = drm_to_adev(dev);
1425 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1426 struct amdgpu_bo_list *list;
1427 struct amdgpu_bo *pd;
1428 u32 pasid;
1429 int handle;
1430
1431 if (!fpriv)
1432 return;
1433
1434 pm_runtime_get_sync(dev->dev);
1435
1436 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1437 amdgpu_uvd_free_handles(adev, file_priv);
1438 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1439 amdgpu_vce_free_handles(adev, file_priv);
1440
1441 if (fpriv->csa_va) {
1442 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1443
1444 WARN_ON(amdgpu_unmap_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1445 fpriv->csa_va, csa_addr));
1446 fpriv->csa_va = NULL;
1447 }
1448
1449 amdgpu_seq64_unmap(adev, fpriv);
1450
1451 pasid = fpriv->vm.pasid;
1452 pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1453 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {
1454 amdgpu_vm_bo_del(adev, fpriv->prt_va);
1455 amdgpu_bo_unreserve(pd);
1456 }
1457
1458 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1459 amdgpu_vm_fini(adev, &fpriv->vm);
1460
1461 if (pasid)
1462 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1463 amdgpu_bo_unref(&pd);
1464
1465 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1466 amdgpu_bo_list_put(list);
1467
1468 idr_destroy(&fpriv->bo_list_handles);
1469 mutex_destroy(&fpriv->bo_list_lock);
1470
1471 kfree(fpriv);
1472 file_priv->driver_priv = NULL;
1473
1474 pm_runtime_mark_last_busy(dev->dev);
1475 pm_runtime_put_autosuspend(dev->dev);
1476}
1477
1478
1479void amdgpu_driver_release_kms(struct drm_device *dev)
1480{
1481 struct amdgpu_device *adev = drm_to_adev(dev);
1482
1483 amdgpu_device_fini_sw(adev);
1484 pci_set_drvdata(adev->pdev, NULL);
1485}
1486
1487/*
1488 * VBlank related functions.
1489 */
1490/**
1491 * amdgpu_get_vblank_counter_kms - get frame count
1492 *
1493 * @crtc: crtc to get the frame count from
1494 *
1495 * Gets the frame count on the requested crtc (all asics).
1496 * Returns frame count on success, -EINVAL on failure.
1497 */
1498u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1499{
1500 struct drm_device *dev = crtc->dev;
1501 unsigned int pipe = crtc->index;
1502 struct amdgpu_device *adev = drm_to_adev(dev);
1503 int vpos, hpos, stat;
1504 u32 count;
1505
1506 if (pipe >= adev->mode_info.num_crtc) {
1507 DRM_ERROR("Invalid crtc %u\n", pipe);
1508 return -EINVAL;
1509 }
1510
1511 /* The hw increments its frame counter at start of vsync, not at start
1512 * of vblank, as is required by DRM core vblank counter handling.
1513 * Cook the hw count here to make it appear to the caller as if it
1514 * incremented at start of vblank. We measure distance to start of
1515 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1516 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1517 * result by 1 to give the proper appearance to caller.
1518 */
1519 if (adev->mode_info.crtcs[pipe]) {
1520 /* Repeat readout if needed to provide stable result if
1521 * we cross start of vsync during the queries.
1522 */
1523 do {
1524 count = amdgpu_display_vblank_get_counter(adev, pipe);
1525 /* Ask amdgpu_display_get_crtc_scanoutpos to return
1526 * vpos as distance to start of vblank, instead of
1527 * regular vertical scanout pos.
1528 */
1529 stat = amdgpu_display_get_crtc_scanoutpos(
1530 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1531 &vpos, &hpos, NULL, NULL,
1532 &adev->mode_info.crtcs[pipe]->base.hwmode);
1533 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1534
1535 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1536 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1537 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1538 } else {
1539 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1540 pipe, vpos);
1541
1542 /* Bump counter if we are at >= leading edge of vblank,
1543 * but before vsync where vpos would turn negative and
1544 * the hw counter really increments.
1545 */
1546 if (vpos >= 0)
1547 count++;
1548 }
1549 } else {
1550 /* Fallback to use value as is. */
1551 count = amdgpu_display_vblank_get_counter(adev, pipe);
1552 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1553 }
1554
1555 return count;
1556}
1557
1558/**
1559 * amdgpu_enable_vblank_kms - enable vblank interrupt
1560 *
1561 * @crtc: crtc to enable vblank interrupt for
1562 *
1563 * Enable the interrupt on the requested crtc (all asics).
1564 * Returns 0 on success, -EINVAL on failure.
1565 */
1566int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1567{
1568 struct drm_device *dev = crtc->dev;
1569 unsigned int pipe = crtc->index;
1570 struct amdgpu_device *adev = drm_to_adev(dev);
1571 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1572
1573 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1574}
1575
1576/**
1577 * amdgpu_disable_vblank_kms - disable vblank interrupt
1578 *
1579 * @crtc: crtc to disable vblank interrupt for
1580 *
1581 * Disable the interrupt on the requested crtc (all asics).
1582 */
1583void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1584{
1585 struct drm_device *dev = crtc->dev;
1586 unsigned int pipe = crtc->index;
1587 struct amdgpu_device *adev = drm_to_adev(dev);
1588 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1589
1590 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1591}
1592
1593/*
1594 * Debugfs info
1595 */
1596#if defined(CONFIG_DEBUG_FS)
1597
1598static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1599{
1600 struct amdgpu_device *adev = m->private;
1601 struct drm_amdgpu_info_firmware fw_info;
1602 struct drm_amdgpu_query_fw query_fw;
1603 struct atom_context *ctx = adev->mode_info.atom_context;
1604 uint8_t smu_program, smu_major, smu_minor, smu_debug;
1605 int ret, i;
1606
1607 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1608#define TA_FW_NAME(type)[TA_FW_TYPE_PSP_##type] = #type
1609 TA_FW_NAME(XGMI),
1610 TA_FW_NAME(RAS),
1611 TA_FW_NAME(HDCP),
1612 TA_FW_NAME(DTM),
1613 TA_FW_NAME(RAP),
1614 TA_FW_NAME(SECUREDISPLAY),
1615#undef TA_FW_NAME
1616 };
1617
1618 /* VCE */
1619 query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1620 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1621 if (ret)
1622 return ret;
1623 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1624 fw_info.feature, fw_info.ver);
1625
1626 /* UVD */
1627 query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1628 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1629 if (ret)
1630 return ret;
1631 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1632 fw_info.feature, fw_info.ver);
1633
1634 /* GMC */
1635 query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1636 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1637 if (ret)
1638 return ret;
1639 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1640 fw_info.feature, fw_info.ver);
1641
1642 /* ME */
1643 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1644 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1645 if (ret)
1646 return ret;
1647 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1648 fw_info.feature, fw_info.ver);
1649
1650 /* PFP */
1651 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1652 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1653 if (ret)
1654 return ret;
1655 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1656 fw_info.feature, fw_info.ver);
1657
1658 /* CE */
1659 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1660 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1661 if (ret)
1662 return ret;
1663 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1664 fw_info.feature, fw_info.ver);
1665
1666 /* RLC */
1667 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1668 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1669 if (ret)
1670 return ret;
1671 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1672 fw_info.feature, fw_info.ver);
1673
1674 /* RLC SAVE RESTORE LIST CNTL */
1675 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1676 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1677 if (ret)
1678 return ret;
1679 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1680 fw_info.feature, fw_info.ver);
1681
1682 /* RLC SAVE RESTORE LIST GPM MEM */
1683 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1684 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1685 if (ret)
1686 return ret;
1687 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1688 fw_info.feature, fw_info.ver);
1689
1690 /* RLC SAVE RESTORE LIST SRM MEM */
1691 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1692 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1693 if (ret)
1694 return ret;
1695 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1696 fw_info.feature, fw_info.ver);
1697
1698 /* RLCP */
1699 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP;
1700 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1701 if (ret)
1702 return ret;
1703 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n",
1704 fw_info.feature, fw_info.ver);
1705
1706 /* RLCV */
1707 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV;
1708 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1709 if (ret)
1710 return ret;
1711 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n",
1712 fw_info.feature, fw_info.ver);
1713
1714 /* MEC */
1715 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1716 query_fw.index = 0;
1717 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1718 if (ret)
1719 return ret;
1720 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1721 fw_info.feature, fw_info.ver);
1722
1723 /* MEC2 */
1724 if (adev->gfx.mec2_fw) {
1725 query_fw.index = 1;
1726 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1727 if (ret)
1728 return ret;
1729 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1730 fw_info.feature, fw_info.ver);
1731 }
1732
1733 /* IMU */
1734 query_fw.fw_type = AMDGPU_INFO_FW_IMU;
1735 query_fw.index = 0;
1736 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1737 if (ret)
1738 return ret;
1739 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n",
1740 fw_info.feature, fw_info.ver);
1741
1742 /* PSP SOS */
1743 query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1744 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1745 if (ret)
1746 return ret;
1747 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1748 fw_info.feature, fw_info.ver);
1749
1750
1751 /* PSP ASD */
1752 query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1753 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1754 if (ret)
1755 return ret;
1756 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1757 fw_info.feature, fw_info.ver);
1758
1759 query_fw.fw_type = AMDGPU_INFO_FW_TA;
1760 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1761 query_fw.index = i;
1762 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1763 if (ret)
1764 continue;
1765
1766 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1767 ta_fw_name[i], fw_info.feature, fw_info.ver);
1768 }
1769
1770 /* SMC */
1771 query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1772 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1773 if (ret)
1774 return ret;
1775 smu_program = (fw_info.ver >> 24) & 0xff;
1776 smu_major = (fw_info.ver >> 16) & 0xff;
1777 smu_minor = (fw_info.ver >> 8) & 0xff;
1778 smu_debug = (fw_info.ver >> 0) & 0xff;
1779 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n",
1780 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug);
1781
1782 /* SDMA */
1783 query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1784 for (i = 0; i < adev->sdma.num_instances; i++) {
1785 query_fw.index = i;
1786 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1787 if (ret)
1788 return ret;
1789 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1790 i, fw_info.feature, fw_info.ver);
1791 }
1792
1793 /* VCN */
1794 query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1795 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1796 if (ret)
1797 return ret;
1798 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1799 fw_info.feature, fw_info.ver);
1800
1801 /* DMCU */
1802 query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1803 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1804 if (ret)
1805 return ret;
1806 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1807 fw_info.feature, fw_info.ver);
1808
1809 /* DMCUB */
1810 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1811 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1812 if (ret)
1813 return ret;
1814 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1815 fw_info.feature, fw_info.ver);
1816
1817 /* TOC */
1818 query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1819 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1820 if (ret)
1821 return ret;
1822 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1823 fw_info.feature, fw_info.ver);
1824
1825 /* CAP */
1826 if (adev->psp.cap_fw) {
1827 query_fw.fw_type = AMDGPU_INFO_FW_CAP;
1828 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1829 if (ret)
1830 return ret;
1831 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n",
1832 fw_info.feature, fw_info.ver);
1833 }
1834
1835 /* MES_KIQ */
1836 query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ;
1837 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1838 if (ret)
1839 return ret;
1840 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n",
1841 fw_info.feature, fw_info.ver);
1842
1843 /* MES */
1844 query_fw.fw_type = AMDGPU_INFO_FW_MES;
1845 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1846 if (ret)
1847 return ret;
1848 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n",
1849 fw_info.feature, fw_info.ver);
1850
1851 /* VPE */
1852 query_fw.fw_type = AMDGPU_INFO_FW_VPE;
1853 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1854 if (ret)
1855 return ret;
1856 seq_printf(m, "VPE feature version: %u, firmware version: 0x%08x\n",
1857 fw_info.feature, fw_info.ver);
1858
1859 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_pn);
1860
1861 return 0;
1862}
1863
1864DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1865
1866#endif
1867
1868void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1869{
1870#if defined(CONFIG_DEBUG_FS)
1871 struct drm_minor *minor = adev_to_drm(adev)->primary;
1872 struct dentry *root = minor->debugfs_root;
1873
1874 debugfs_create_file("amdgpu_firmware_info", 0444, root,
1875 adev, &amdgpu_debugfs_firmware_info_fops);
1876
1877#endif
1878}
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <drm/drmP.h>
29#include "amdgpu.h"
30#include <drm/amdgpu_drm.h>
31#include "amdgpu_sched.h"
32#include "amdgpu_uvd.h"
33#include "amdgpu_vce.h"
34
35#include <linux/vga_switcheroo.h>
36#include <linux/slab.h>
37#include <linux/pm_runtime.h>
38#include "amdgpu_amdkfd.h"
39
40/**
41 * amdgpu_driver_unload_kms - Main unload function for KMS.
42 *
43 * @dev: drm dev pointer
44 *
45 * This is the main unload function for KMS (all asics).
46 * Returns 0 on success.
47 */
48void amdgpu_driver_unload_kms(struct drm_device *dev)
49{
50 struct amdgpu_device *adev = dev->dev_private;
51
52 if (adev == NULL)
53 return;
54
55 if (adev->rmmio == NULL)
56 goto done_free;
57
58 if (amdgpu_sriov_vf(adev))
59 amdgpu_virt_request_full_gpu(adev, false);
60
61 if (amdgpu_device_is_px(dev)) {
62 pm_runtime_get_sync(dev->dev);
63 pm_runtime_forbid(dev->dev);
64 }
65
66 amdgpu_acpi_fini(adev);
67
68 amdgpu_device_fini(adev);
69
70done_free:
71 kfree(adev);
72 dev->dev_private = NULL;
73}
74
75/**
76 * amdgpu_driver_load_kms - Main load function for KMS.
77 *
78 * @dev: drm dev pointer
79 * @flags: device flags
80 *
81 * This is the main load function for KMS (all asics).
82 * Returns 0 on success, error on failure.
83 */
84int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
85{
86 struct amdgpu_device *adev;
87 int r, acpi_status;
88
89#ifdef CONFIG_DRM_AMDGPU_SI
90 if (!amdgpu_si_support) {
91 switch (flags & AMD_ASIC_MASK) {
92 case CHIP_TAHITI:
93 case CHIP_PITCAIRN:
94 case CHIP_VERDE:
95 case CHIP_OLAND:
96 case CHIP_HAINAN:
97 dev_info(dev->dev,
98 "SI support provided by radeon.\n");
99 dev_info(dev->dev,
100 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
101 );
102 return -ENODEV;
103 }
104 }
105#endif
106#ifdef CONFIG_DRM_AMDGPU_CIK
107 if (!amdgpu_cik_support) {
108 switch (flags & AMD_ASIC_MASK) {
109 case CHIP_KAVERI:
110 case CHIP_BONAIRE:
111 case CHIP_HAWAII:
112 case CHIP_KABINI:
113 case CHIP_MULLINS:
114 dev_info(dev->dev,
115 "CIK support provided by radeon.\n");
116 dev_info(dev->dev,
117 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
118 );
119 return -ENODEV;
120 }
121 }
122#endif
123
124 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
125 if (adev == NULL) {
126 return -ENOMEM;
127 }
128 dev->dev_private = (void *)adev;
129
130 if ((amdgpu_runtime_pm != 0) &&
131 amdgpu_has_atpx() &&
132 (amdgpu_is_atpx_hybrid() ||
133 amdgpu_has_atpx_dgpu_power_cntl()) &&
134 ((flags & AMD_IS_APU) == 0) &&
135 !pci_is_thunderbolt_attached(dev->pdev))
136 flags |= AMD_IS_PX;
137
138 /* amdgpu_device_init should report only fatal error
139 * like memory allocation failure or iomapping failure,
140 * or memory manager initialization failure, it must
141 * properly initialize the GPU MC controller and permit
142 * VRAM allocation
143 */
144 r = amdgpu_device_init(adev, dev, dev->pdev, flags);
145 if (r) {
146 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
147 goto out;
148 }
149
150 /* Call ACPI methods: require modeset init
151 * but failure is not fatal
152 */
153 if (!r) {
154 acpi_status = amdgpu_acpi_init(adev);
155 if (acpi_status)
156 dev_dbg(&dev->pdev->dev,
157 "Error during ACPI methods call\n");
158 }
159
160 if (amdgpu_device_is_px(dev)) {
161 pm_runtime_use_autosuspend(dev->dev);
162 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
163 pm_runtime_set_active(dev->dev);
164 pm_runtime_allow(dev->dev);
165 pm_runtime_mark_last_busy(dev->dev);
166 pm_runtime_put_autosuspend(dev->dev);
167 }
168
169out:
170 if (r) {
171 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
172 if (adev->rmmio && amdgpu_device_is_px(dev))
173 pm_runtime_put_noidle(dev->dev);
174 amdgpu_driver_unload_kms(dev);
175 }
176
177 return r;
178}
179
180static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
181 struct drm_amdgpu_query_fw *query_fw,
182 struct amdgpu_device *adev)
183{
184 switch (query_fw->fw_type) {
185 case AMDGPU_INFO_FW_VCE:
186 fw_info->ver = adev->vce.fw_version;
187 fw_info->feature = adev->vce.fb_version;
188 break;
189 case AMDGPU_INFO_FW_UVD:
190 fw_info->ver = adev->uvd.fw_version;
191 fw_info->feature = 0;
192 break;
193 case AMDGPU_INFO_FW_VCN:
194 fw_info->ver = adev->vcn.fw_version;
195 fw_info->feature = 0;
196 break;
197 case AMDGPU_INFO_FW_GMC:
198 fw_info->ver = adev->gmc.fw_version;
199 fw_info->feature = 0;
200 break;
201 case AMDGPU_INFO_FW_GFX_ME:
202 fw_info->ver = adev->gfx.me_fw_version;
203 fw_info->feature = adev->gfx.me_feature_version;
204 break;
205 case AMDGPU_INFO_FW_GFX_PFP:
206 fw_info->ver = adev->gfx.pfp_fw_version;
207 fw_info->feature = adev->gfx.pfp_feature_version;
208 break;
209 case AMDGPU_INFO_FW_GFX_CE:
210 fw_info->ver = adev->gfx.ce_fw_version;
211 fw_info->feature = adev->gfx.ce_feature_version;
212 break;
213 case AMDGPU_INFO_FW_GFX_RLC:
214 fw_info->ver = adev->gfx.rlc_fw_version;
215 fw_info->feature = adev->gfx.rlc_feature_version;
216 break;
217 case AMDGPU_INFO_FW_GFX_MEC:
218 if (query_fw->index == 0) {
219 fw_info->ver = adev->gfx.mec_fw_version;
220 fw_info->feature = adev->gfx.mec_feature_version;
221 } else if (query_fw->index == 1) {
222 fw_info->ver = adev->gfx.mec2_fw_version;
223 fw_info->feature = adev->gfx.mec2_feature_version;
224 } else
225 return -EINVAL;
226 break;
227 case AMDGPU_INFO_FW_SMC:
228 fw_info->ver = adev->pm.fw_version;
229 fw_info->feature = 0;
230 break;
231 case AMDGPU_INFO_FW_SDMA:
232 if (query_fw->index >= adev->sdma.num_instances)
233 return -EINVAL;
234 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
235 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
236 break;
237 case AMDGPU_INFO_FW_SOS:
238 fw_info->ver = adev->psp.sos_fw_version;
239 fw_info->feature = adev->psp.sos_feature_version;
240 break;
241 case AMDGPU_INFO_FW_ASD:
242 fw_info->ver = adev->psp.asd_fw_version;
243 fw_info->feature = adev->psp.asd_feature_version;
244 break;
245 default:
246 return -EINVAL;
247 }
248 return 0;
249}
250
251/*
252 * Userspace get information ioctl
253 */
254/**
255 * amdgpu_info_ioctl - answer a device specific request.
256 *
257 * @adev: amdgpu device pointer
258 * @data: request object
259 * @filp: drm filp
260 *
261 * This function is used to pass device specific parameters to the userspace
262 * drivers. Examples include: pci device id, pipeline parms, tiling params,
263 * etc. (all asics).
264 * Returns 0 on success, -EINVAL on failure.
265 */
266static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
267{
268 struct amdgpu_device *adev = dev->dev_private;
269 struct drm_amdgpu_info *info = data;
270 struct amdgpu_mode_info *minfo = &adev->mode_info;
271 void __user *out = (void __user *)(uintptr_t)info->return_pointer;
272 uint32_t size = info->return_size;
273 struct drm_crtc *crtc;
274 uint32_t ui32 = 0;
275 uint64_t ui64 = 0;
276 int i, found;
277 int ui32_size = sizeof(ui32);
278
279 if (!info->return_size || !info->return_pointer)
280 return -EINVAL;
281
282 switch (info->query) {
283 case AMDGPU_INFO_ACCEL_WORKING:
284 ui32 = adev->accel_working;
285 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
286 case AMDGPU_INFO_CRTC_FROM_ID:
287 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
288 crtc = (struct drm_crtc *)minfo->crtcs[i];
289 if (crtc && crtc->base.id == info->mode_crtc.id) {
290 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
291 ui32 = amdgpu_crtc->crtc_id;
292 found = 1;
293 break;
294 }
295 }
296 if (!found) {
297 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
298 return -EINVAL;
299 }
300 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
301 case AMDGPU_INFO_HW_IP_INFO: {
302 struct drm_amdgpu_info_hw_ip ip = {};
303 enum amd_ip_block_type type;
304 uint32_t ring_mask = 0;
305 uint32_t ib_start_alignment = 0;
306 uint32_t ib_size_alignment = 0;
307
308 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
309 return -EINVAL;
310
311 switch (info->query_hw_ip.type) {
312 case AMDGPU_HW_IP_GFX:
313 type = AMD_IP_BLOCK_TYPE_GFX;
314 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
315 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);
316 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
317 ib_size_alignment = 8;
318 break;
319 case AMDGPU_HW_IP_COMPUTE:
320 type = AMD_IP_BLOCK_TYPE_GFX;
321 for (i = 0; i < adev->gfx.num_compute_rings; i++)
322 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);
323 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
324 ib_size_alignment = 8;
325 break;
326 case AMDGPU_HW_IP_DMA:
327 type = AMD_IP_BLOCK_TYPE_SDMA;
328 for (i = 0; i < adev->sdma.num_instances; i++)
329 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i);
330 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
331 ib_size_alignment = 1;
332 break;
333 case AMDGPU_HW_IP_UVD:
334 type = AMD_IP_BLOCK_TYPE_UVD;
335 ring_mask = adev->uvd.ring.ready ? 1 : 0;
336 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
337 ib_size_alignment = 16;
338 break;
339 case AMDGPU_HW_IP_VCE:
340 type = AMD_IP_BLOCK_TYPE_VCE;
341 for (i = 0; i < adev->vce.num_rings; i++)
342 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
343 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
344 ib_size_alignment = 1;
345 break;
346 case AMDGPU_HW_IP_UVD_ENC:
347 type = AMD_IP_BLOCK_TYPE_UVD;
348 for (i = 0; i < adev->uvd.num_enc_rings; i++)
349 ring_mask |= ((adev->uvd.ring_enc[i].ready ? 1 : 0) << i);
350 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
351 ib_size_alignment = 1;
352 break;
353 case AMDGPU_HW_IP_VCN_DEC:
354 type = AMD_IP_BLOCK_TYPE_VCN;
355 ring_mask = adev->vcn.ring_dec.ready ? 1 : 0;
356 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
357 ib_size_alignment = 16;
358 break;
359 case AMDGPU_HW_IP_VCN_ENC:
360 type = AMD_IP_BLOCK_TYPE_VCN;
361 for (i = 0; i < adev->vcn.num_enc_rings; i++)
362 ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0) << i);
363 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
364 ib_size_alignment = 1;
365 break;
366 default:
367 return -EINVAL;
368 }
369
370 for (i = 0; i < adev->num_ip_blocks; i++) {
371 if (adev->ip_blocks[i].version->type == type &&
372 adev->ip_blocks[i].status.valid) {
373 ip.hw_ip_version_major = adev->ip_blocks[i].version->major;
374 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor;
375 ip.capabilities_flags = 0;
376 ip.available_rings = ring_mask;
377 ip.ib_start_alignment = ib_start_alignment;
378 ip.ib_size_alignment = ib_size_alignment;
379 break;
380 }
381 }
382 return copy_to_user(out, &ip,
383 min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
384 }
385 case AMDGPU_INFO_HW_IP_COUNT: {
386 enum amd_ip_block_type type;
387 uint32_t count = 0;
388
389 switch (info->query_hw_ip.type) {
390 case AMDGPU_HW_IP_GFX:
391 type = AMD_IP_BLOCK_TYPE_GFX;
392 break;
393 case AMDGPU_HW_IP_COMPUTE:
394 type = AMD_IP_BLOCK_TYPE_GFX;
395 break;
396 case AMDGPU_HW_IP_DMA:
397 type = AMD_IP_BLOCK_TYPE_SDMA;
398 break;
399 case AMDGPU_HW_IP_UVD:
400 type = AMD_IP_BLOCK_TYPE_UVD;
401 break;
402 case AMDGPU_HW_IP_VCE:
403 type = AMD_IP_BLOCK_TYPE_VCE;
404 break;
405 case AMDGPU_HW_IP_UVD_ENC:
406 type = AMD_IP_BLOCK_TYPE_UVD;
407 break;
408 case AMDGPU_HW_IP_VCN_DEC:
409 case AMDGPU_HW_IP_VCN_ENC:
410 type = AMD_IP_BLOCK_TYPE_VCN;
411 break;
412 default:
413 return -EINVAL;
414 }
415
416 for (i = 0; i < adev->num_ip_blocks; i++)
417 if (adev->ip_blocks[i].version->type == type &&
418 adev->ip_blocks[i].status.valid &&
419 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
420 count++;
421
422 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
423 }
424 case AMDGPU_INFO_TIMESTAMP:
425 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
426 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
427 case AMDGPU_INFO_FW_VERSION: {
428 struct drm_amdgpu_info_firmware fw_info;
429 int ret;
430
431 /* We only support one instance of each IP block right now. */
432 if (info->query_fw.ip_instance != 0)
433 return -EINVAL;
434
435 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
436 if (ret)
437 return ret;
438
439 return copy_to_user(out, &fw_info,
440 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
441 }
442 case AMDGPU_INFO_NUM_BYTES_MOVED:
443 ui64 = atomic64_read(&adev->num_bytes_moved);
444 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
445 case AMDGPU_INFO_NUM_EVICTIONS:
446 ui64 = atomic64_read(&adev->num_evictions);
447 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
448 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
449 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
450 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
451 case AMDGPU_INFO_VRAM_USAGE:
452 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
453 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
454 case AMDGPU_INFO_VIS_VRAM_USAGE:
455 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
456 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
457 case AMDGPU_INFO_GTT_USAGE:
458 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
459 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
460 case AMDGPU_INFO_GDS_CONFIG: {
461 struct drm_amdgpu_info_gds gds_info;
462
463 memset(&gds_info, 0, sizeof(gds_info));
464 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
465 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
466 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
467 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
468 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
469 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
470 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
471 return copy_to_user(out, &gds_info,
472 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
473 }
474 case AMDGPU_INFO_VRAM_GTT: {
475 struct drm_amdgpu_info_vram_gtt vram_gtt;
476
477 vram_gtt.vram_size = adev->gmc.real_vram_size;
478 vram_gtt.vram_size -= adev->vram_pin_size;
479 vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size;
480 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);
481 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
482 vram_gtt.gtt_size *= PAGE_SIZE;
483 vram_gtt.gtt_size -= adev->gart_pin_size;
484 return copy_to_user(out, &vram_gtt,
485 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
486 }
487 case AMDGPU_INFO_MEMORY: {
488 struct drm_amdgpu_memory_info mem;
489
490 memset(&mem, 0, sizeof(mem));
491 mem.vram.total_heap_size = adev->gmc.real_vram_size;
492 mem.vram.usable_heap_size =
493 adev->gmc.real_vram_size - adev->vram_pin_size;
494 mem.vram.heap_usage =
495 amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
496 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
497
498 mem.cpu_accessible_vram.total_heap_size =
499 adev->gmc.visible_vram_size;
500 mem.cpu_accessible_vram.usable_heap_size =
501 adev->gmc.visible_vram_size -
502 (adev->vram_pin_size - adev->invisible_pin_size);
503 mem.cpu_accessible_vram.heap_usage =
504 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
505 mem.cpu_accessible_vram.max_allocation =
506 mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
507
508 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;
509 mem.gtt.total_heap_size *= PAGE_SIZE;
510 mem.gtt.usable_heap_size = mem.gtt.total_heap_size
511 - adev->gart_pin_size;
512 mem.gtt.heap_usage =
513 amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
514 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
515
516 return copy_to_user(out, &mem,
517 min((size_t)size, sizeof(mem)))
518 ? -EFAULT : 0;
519 }
520 case AMDGPU_INFO_READ_MMR_REG: {
521 unsigned n, alloc_size;
522 uint32_t *regs;
523 unsigned se_num = (info->read_mmr_reg.instance >>
524 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
525 AMDGPU_INFO_MMR_SE_INDEX_MASK;
526 unsigned sh_num = (info->read_mmr_reg.instance >>
527 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
528 AMDGPU_INFO_MMR_SH_INDEX_MASK;
529
530 /* set full masks if the userspace set all bits
531 * in the bitfields */
532 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
533 se_num = 0xffffffff;
534 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
535 sh_num = 0xffffffff;
536
537 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
538 if (!regs)
539 return -ENOMEM;
540 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
541
542 for (i = 0; i < info->read_mmr_reg.count; i++)
543 if (amdgpu_asic_read_register(adev, se_num, sh_num,
544 info->read_mmr_reg.dword_offset + i,
545 ®s[i])) {
546 DRM_DEBUG_KMS("unallowed offset %#x\n",
547 info->read_mmr_reg.dword_offset + i);
548 kfree(regs);
549 return -EFAULT;
550 }
551 n = copy_to_user(out, regs, min(size, alloc_size));
552 kfree(regs);
553 return n ? -EFAULT : 0;
554 }
555 case AMDGPU_INFO_DEV_INFO: {
556 struct drm_amdgpu_info_device dev_info = {};
557 uint64_t vm_size;
558
559 dev_info.device_id = dev->pdev->device;
560 dev_info.chip_rev = adev->rev_id;
561 dev_info.external_rev = adev->external_rev_id;
562 dev_info.pci_rev = dev->pdev->revision;
563 dev_info.family = adev->family;
564 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
565 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
566 /* return all clocks in KHz */
567 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
568 if (adev->pm.dpm_enabled) {
569 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
570 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
571 } else {
572 dev_info.max_engine_clock = adev->clock.default_sclk * 10;
573 dev_info.max_memory_clock = adev->clock.default_mclk * 10;
574 }
575 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
576 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
577 adev->gfx.config.max_shader_engines;
578 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
579 dev_info._pad = 0;
580 dev_info.ids_flags = 0;
581 if (adev->flags & AMD_IS_APU)
582 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
583 if (amdgpu_sriov_vf(adev))
584 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
585
586 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
587 vm_size -= AMDGPU_VA_RESERVED_SIZE;
588
589 /* Older VCE FW versions are buggy and can handle only 40bits */
590 if (adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
591 vm_size = min(vm_size, 1ULL << 40);
592
593 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
594 dev_info.virtual_address_max =
595 min(vm_size, AMDGPU_VA_HOLE_START);
596
597 if (vm_size > AMDGPU_VA_HOLE_START) {
598 dev_info.high_va_offset = AMDGPU_VA_HOLE_END;
599 dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size;
600 }
601 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
602 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
603 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
604 dev_info.cu_active_number = adev->gfx.cu_info.number;
605 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
606 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
607 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
608 sizeof(adev->gfx.cu_info.ao_cu_bitmap));
609 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
610 sizeof(adev->gfx.cu_info.bitmap));
611 dev_info.vram_type = adev->gmc.vram_type;
612 dev_info.vram_bit_width = adev->gmc.vram_width;
613 dev_info.vce_harvest_config = adev->vce.harvest_config;
614 dev_info.gc_double_offchip_lds_buf =
615 adev->gfx.config.double_offchip_lds_buf;
616
617 if (amdgpu_ngg) {
618 dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
619 dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
620 dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
621 dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
622 dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
623 dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
624 dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
625 dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
626 }
627 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
628 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
629 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
630 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
631 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
632 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
633 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
634
635 return copy_to_user(out, &dev_info,
636 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
637 }
638 case AMDGPU_INFO_VCE_CLOCK_TABLE: {
639 unsigned i;
640 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
641 struct amd_vce_state *vce_state;
642
643 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
644 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
645 if (vce_state) {
646 vce_clk_table.entries[i].sclk = vce_state->sclk;
647 vce_clk_table.entries[i].mclk = vce_state->mclk;
648 vce_clk_table.entries[i].eclk = vce_state->evclk;
649 vce_clk_table.num_valid_entries++;
650 }
651 }
652
653 return copy_to_user(out, &vce_clk_table,
654 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
655 }
656 case AMDGPU_INFO_VBIOS: {
657 uint32_t bios_size = adev->bios_size;
658
659 switch (info->vbios_info.type) {
660 case AMDGPU_INFO_VBIOS_SIZE:
661 return copy_to_user(out, &bios_size,
662 min((size_t)size, sizeof(bios_size)))
663 ? -EFAULT : 0;
664 case AMDGPU_INFO_VBIOS_IMAGE: {
665 uint8_t *bios;
666 uint32_t bios_offset = info->vbios_info.offset;
667
668 if (bios_offset >= bios_size)
669 return -EINVAL;
670
671 bios = adev->bios + bios_offset;
672 return copy_to_user(out, bios,
673 min((size_t)size, (size_t)(bios_size - bios_offset)))
674 ? -EFAULT : 0;
675 }
676 default:
677 DRM_DEBUG_KMS("Invalid request %d\n",
678 info->vbios_info.type);
679 return -EINVAL;
680 }
681 }
682 case AMDGPU_INFO_NUM_HANDLES: {
683 struct drm_amdgpu_info_num_handles handle;
684
685 switch (info->query_hw_ip.type) {
686 case AMDGPU_HW_IP_UVD:
687 /* Starting Polaris, we support unlimited UVD handles */
688 if (adev->asic_type < CHIP_POLARIS10) {
689 handle.uvd_max_handles = adev->uvd.max_handles;
690 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
691
692 return copy_to_user(out, &handle,
693 min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
694 } else {
695 return -ENODATA;
696 }
697
698 break;
699 default:
700 return -EINVAL;
701 }
702 }
703 case AMDGPU_INFO_SENSOR: {
704 struct pp_gpu_power query = {0};
705 int query_size = sizeof(query);
706
707 if (amdgpu_dpm == 0)
708 return -ENOENT;
709
710 switch (info->sensor_info.type) {
711 case AMDGPU_INFO_SENSOR_GFX_SCLK:
712 /* get sclk in Mhz */
713 if (amdgpu_dpm_read_sensor(adev,
714 AMDGPU_PP_SENSOR_GFX_SCLK,
715 (void *)&ui32, &ui32_size)) {
716 return -EINVAL;
717 }
718 ui32 /= 100;
719 break;
720 case AMDGPU_INFO_SENSOR_GFX_MCLK:
721 /* get mclk in Mhz */
722 if (amdgpu_dpm_read_sensor(adev,
723 AMDGPU_PP_SENSOR_GFX_MCLK,
724 (void *)&ui32, &ui32_size)) {
725 return -EINVAL;
726 }
727 ui32 /= 100;
728 break;
729 case AMDGPU_INFO_SENSOR_GPU_TEMP:
730 /* get temperature in millidegrees C */
731 if (amdgpu_dpm_read_sensor(adev,
732 AMDGPU_PP_SENSOR_GPU_TEMP,
733 (void *)&ui32, &ui32_size)) {
734 return -EINVAL;
735 }
736 break;
737 case AMDGPU_INFO_SENSOR_GPU_LOAD:
738 /* get GPU load */
739 if (amdgpu_dpm_read_sensor(adev,
740 AMDGPU_PP_SENSOR_GPU_LOAD,
741 (void *)&ui32, &ui32_size)) {
742 return -EINVAL;
743 }
744 break;
745 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
746 /* get average GPU power */
747 if (amdgpu_dpm_read_sensor(adev,
748 AMDGPU_PP_SENSOR_GPU_POWER,
749 (void *)&query, &query_size)) {
750 return -EINVAL;
751 }
752 ui32 = query.average_gpu_power >> 8;
753 break;
754 case AMDGPU_INFO_SENSOR_VDDNB:
755 /* get VDDNB in millivolts */
756 if (amdgpu_dpm_read_sensor(adev,
757 AMDGPU_PP_SENSOR_VDDNB,
758 (void *)&ui32, &ui32_size)) {
759 return -EINVAL;
760 }
761 break;
762 case AMDGPU_INFO_SENSOR_VDDGFX:
763 /* get VDDGFX in millivolts */
764 if (amdgpu_dpm_read_sensor(adev,
765 AMDGPU_PP_SENSOR_VDDGFX,
766 (void *)&ui32, &ui32_size)) {
767 return -EINVAL;
768 }
769 break;
770 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
771 /* get stable pstate sclk in Mhz */
772 if (amdgpu_dpm_read_sensor(adev,
773 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
774 (void *)&ui32, &ui32_size)) {
775 return -EINVAL;
776 }
777 ui32 /= 100;
778 break;
779 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
780 /* get stable pstate mclk in Mhz */
781 if (amdgpu_dpm_read_sensor(adev,
782 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
783 (void *)&ui32, &ui32_size)) {
784 return -EINVAL;
785 }
786 ui32 /= 100;
787 break;
788 default:
789 DRM_DEBUG_KMS("Invalid request %d\n",
790 info->sensor_info.type);
791 return -EINVAL;
792 }
793 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
794 }
795 case AMDGPU_INFO_VRAM_LOST_COUNTER:
796 ui32 = atomic_read(&adev->vram_lost_counter);
797 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
798 default:
799 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
800 return -EINVAL;
801 }
802 return 0;
803}
804
805
806/*
807 * Outdated mess for old drm with Xorg being in charge (void function now).
808 */
809/**
810 * amdgpu_driver_lastclose_kms - drm callback for last close
811 *
812 * @dev: drm dev pointer
813 *
814 * Switch vga_switcheroo state after last close (all asics).
815 */
816void amdgpu_driver_lastclose_kms(struct drm_device *dev)
817{
818 drm_fb_helper_lastclose(dev);
819 vga_switcheroo_process_delayed_switch();
820}
821
822/**
823 * amdgpu_driver_open_kms - drm callback for open
824 *
825 * @dev: drm dev pointer
826 * @file_priv: drm file
827 *
828 * On device open, init vm on cayman+ (all asics).
829 * Returns 0 on success, error on failure.
830 */
831int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
832{
833 struct amdgpu_device *adev = dev->dev_private;
834 struct amdgpu_fpriv *fpriv;
835 int r, pasid;
836
837 file_priv->driver_priv = NULL;
838
839 r = pm_runtime_get_sync(dev->dev);
840 if (r < 0)
841 return r;
842
843 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
844 if (unlikely(!fpriv)) {
845 r = -ENOMEM;
846 goto out_suspend;
847 }
848
849 pasid = amdgpu_pasid_alloc(16);
850 if (pasid < 0) {
851 dev_warn(adev->dev, "No more PASIDs available!");
852 pasid = 0;
853 }
854 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
855 if (r)
856 goto error_pasid;
857
858 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
859 if (!fpriv->prt_va) {
860 r = -ENOMEM;
861 goto error_vm;
862 }
863
864 if (amdgpu_sriov_vf(adev)) {
865 r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va);
866 if (r)
867 goto error_vm;
868 }
869
870 mutex_init(&fpriv->bo_list_lock);
871 idr_init(&fpriv->bo_list_handles);
872
873 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
874
875 file_priv->driver_priv = fpriv;
876 goto out_suspend;
877
878error_vm:
879 amdgpu_vm_fini(adev, &fpriv->vm);
880
881error_pasid:
882 if (pasid)
883 amdgpu_pasid_free(pasid);
884
885 kfree(fpriv);
886
887out_suspend:
888 pm_runtime_mark_last_busy(dev->dev);
889 pm_runtime_put_autosuspend(dev->dev);
890
891 return r;
892}
893
894/**
895 * amdgpu_driver_postclose_kms - drm callback for post close
896 *
897 * @dev: drm dev pointer
898 * @file_priv: drm file
899 *
900 * On device post close, tear down vm on cayman+ (all asics).
901 */
902void amdgpu_driver_postclose_kms(struct drm_device *dev,
903 struct drm_file *file_priv)
904{
905 struct amdgpu_device *adev = dev->dev_private;
906 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
907 struct amdgpu_bo_list *list;
908 struct amdgpu_bo *pd;
909 unsigned int pasid;
910 int handle;
911
912 if (!fpriv)
913 return;
914
915 pm_runtime_get_sync(dev->dev);
916
917 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
918
919 if (adev->asic_type != CHIP_RAVEN) {
920 amdgpu_uvd_free_handles(adev, file_priv);
921 amdgpu_vce_free_handles(adev, file_priv);
922 }
923
924 amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
925
926 if (amdgpu_sriov_vf(adev)) {
927 /* TODO: how to handle reserve failure */
928 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
929 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
930 fpriv->csa_va = NULL;
931 amdgpu_bo_unreserve(adev->virt.csa_obj);
932 }
933
934 pasid = fpriv->vm.pasid;
935 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
936
937 amdgpu_vm_fini(adev, &fpriv->vm);
938 if (pasid)
939 amdgpu_pasid_free_delayed(pd->tbo.resv, pasid);
940 amdgpu_bo_unref(&pd);
941
942 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
943 amdgpu_bo_list_free(list);
944
945 idr_destroy(&fpriv->bo_list_handles);
946 mutex_destroy(&fpriv->bo_list_lock);
947
948 kfree(fpriv);
949 file_priv->driver_priv = NULL;
950
951 pm_runtime_mark_last_busy(dev->dev);
952 pm_runtime_put_autosuspend(dev->dev);
953}
954
955/*
956 * VBlank related functions.
957 */
958/**
959 * amdgpu_get_vblank_counter_kms - get frame count
960 *
961 * @dev: drm dev pointer
962 * @pipe: crtc to get the frame count from
963 *
964 * Gets the frame count on the requested crtc (all asics).
965 * Returns frame count on success, -EINVAL on failure.
966 */
967u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
968{
969 struct amdgpu_device *adev = dev->dev_private;
970 int vpos, hpos, stat;
971 u32 count;
972
973 if (pipe >= adev->mode_info.num_crtc) {
974 DRM_ERROR("Invalid crtc %u\n", pipe);
975 return -EINVAL;
976 }
977
978 /* The hw increments its frame counter at start of vsync, not at start
979 * of vblank, as is required by DRM core vblank counter handling.
980 * Cook the hw count here to make it appear to the caller as if it
981 * incremented at start of vblank. We measure distance to start of
982 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
983 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
984 * result by 1 to give the proper appearance to caller.
985 */
986 if (adev->mode_info.crtcs[pipe]) {
987 /* Repeat readout if needed to provide stable result if
988 * we cross start of vsync during the queries.
989 */
990 do {
991 count = amdgpu_display_vblank_get_counter(adev, pipe);
992 /* Ask amdgpu_display_get_crtc_scanoutpos to return
993 * vpos as distance to start of vblank, instead of
994 * regular vertical scanout pos.
995 */
996 stat = amdgpu_display_get_crtc_scanoutpos(
997 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
998 &vpos, &hpos, NULL, NULL,
999 &adev->mode_info.crtcs[pipe]->base.hwmode);
1000 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1001
1002 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1003 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1004 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1005 } else {
1006 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1007 pipe, vpos);
1008
1009 /* Bump counter if we are at >= leading edge of vblank,
1010 * but before vsync where vpos would turn negative and
1011 * the hw counter really increments.
1012 */
1013 if (vpos >= 0)
1014 count++;
1015 }
1016 } else {
1017 /* Fallback to use value as is. */
1018 count = amdgpu_display_vblank_get_counter(adev, pipe);
1019 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1020 }
1021
1022 return count;
1023}
1024
1025/**
1026 * amdgpu_enable_vblank_kms - enable vblank interrupt
1027 *
1028 * @dev: drm dev pointer
1029 * @pipe: crtc to enable vblank interrupt for
1030 *
1031 * Enable the interrupt on the requested crtc (all asics).
1032 * Returns 0 on success, -EINVAL on failure.
1033 */
1034int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1035{
1036 struct amdgpu_device *adev = dev->dev_private;
1037 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1038
1039 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1040}
1041
1042/**
1043 * amdgpu_disable_vblank_kms - disable vblank interrupt
1044 *
1045 * @dev: drm dev pointer
1046 * @pipe: crtc to disable vblank interrupt for
1047 *
1048 * Disable the interrupt on the requested crtc (all asics).
1049 */
1050void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1051{
1052 struct amdgpu_device *adev = dev->dev_private;
1053 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1054
1055 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1056}
1057
1058const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
1059 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1060 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1061 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1062 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
1063 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1064 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1065 /* KMS */
1066 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1067 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1068 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1069 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1070 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1071 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1072 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1073 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1074 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1075 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)
1076};
1077const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
1078
1079/*
1080 * Debugfs info
1081 */
1082#if defined(CONFIG_DEBUG_FS)
1083
1084static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1085{
1086 struct drm_info_node *node = (struct drm_info_node *) m->private;
1087 struct drm_device *dev = node->minor->dev;
1088 struct amdgpu_device *adev = dev->dev_private;
1089 struct drm_amdgpu_info_firmware fw_info;
1090 struct drm_amdgpu_query_fw query_fw;
1091 int ret, i;
1092
1093 /* VCE */
1094 query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1095 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1096 if (ret)
1097 return ret;
1098 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1099 fw_info.feature, fw_info.ver);
1100
1101 /* UVD */
1102 query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1103 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1104 if (ret)
1105 return ret;
1106 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1107 fw_info.feature, fw_info.ver);
1108
1109 /* GMC */
1110 query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1111 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1112 if (ret)
1113 return ret;
1114 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1115 fw_info.feature, fw_info.ver);
1116
1117 /* ME */
1118 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1119 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1120 if (ret)
1121 return ret;
1122 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1123 fw_info.feature, fw_info.ver);
1124
1125 /* PFP */
1126 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1127 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1128 if (ret)
1129 return ret;
1130 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1131 fw_info.feature, fw_info.ver);
1132
1133 /* CE */
1134 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1135 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1136 if (ret)
1137 return ret;
1138 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1139 fw_info.feature, fw_info.ver);
1140
1141 /* RLC */
1142 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1143 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1144 if (ret)
1145 return ret;
1146 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1147 fw_info.feature, fw_info.ver);
1148
1149 /* MEC */
1150 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1151 query_fw.index = 0;
1152 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1153 if (ret)
1154 return ret;
1155 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1156 fw_info.feature, fw_info.ver);
1157
1158 /* MEC2 */
1159 if (adev->asic_type == CHIP_KAVERI ||
1160 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
1161 query_fw.index = 1;
1162 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1163 if (ret)
1164 return ret;
1165 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1166 fw_info.feature, fw_info.ver);
1167 }
1168
1169 /* PSP SOS */
1170 query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1171 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1172 if (ret)
1173 return ret;
1174 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1175 fw_info.feature, fw_info.ver);
1176
1177
1178 /* PSP ASD */
1179 query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1180 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1181 if (ret)
1182 return ret;
1183 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1184 fw_info.feature, fw_info.ver);
1185
1186 /* SMC */
1187 query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1188 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1189 if (ret)
1190 return ret;
1191 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1192 fw_info.feature, fw_info.ver);
1193
1194 /* SDMA */
1195 query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1196 for (i = 0; i < adev->sdma.num_instances; i++) {
1197 query_fw.index = i;
1198 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1199 if (ret)
1200 return ret;
1201 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1202 i, fw_info.feature, fw_info.ver);
1203 }
1204
1205 /* VCN */
1206 query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1207 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1208 if (ret)
1209 return ret;
1210 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1211 fw_info.feature, fw_info.ver);
1212
1213 return 0;
1214}
1215
1216static const struct drm_info_list amdgpu_firmware_info_list[] = {
1217 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1218};
1219#endif
1220
1221int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1222{
1223#if defined(CONFIG_DEBUG_FS)
1224 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1225 ARRAY_SIZE(amdgpu_firmware_info_list));
1226#else
1227 return 0;
1228#endif
1229}