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1/*
2 * Copyright © 2008-2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include <linux/dma-fence-array.h>
29#include <linux/kthread.h>
30#include <linux/dma-resv.h>
31#include <linux/shmem_fs.h>
32#include <linux/slab.h>
33#include <linux/stop_machine.h>
34#include <linux/swap.h>
35#include <linux/pci.h>
36#include <linux/dma-buf.h>
37#include <linux/mman.h>
38
39#include <drm/drm_cache.h>
40#include <drm/drm_vma_manager.h>
41
42#include "display/intel_display.h"
43
44#include "gem/i915_gem_clflush.h"
45#include "gem/i915_gem_context.h"
46#include "gem/i915_gem_ioctls.h"
47#include "gem/i915_gem_mman.h"
48#include "gem/i915_gem_object_frontbuffer.h"
49#include "gem/i915_gem_pm.h"
50#include "gem/i915_gem_region.h"
51#include "gt/intel_engine_user.h"
52#include "gt/intel_gt.h"
53#include "gt/intel_gt_pm.h"
54#include "gt/intel_workarounds.h"
55
56#include "i915_drv.h"
57#include "i915_file_private.h"
58#include "i915_trace.h"
59#include "i915_vgpu.h"
60#include "intel_clock_gating.h"
61
62static int
63insert_mappable_node(struct i915_ggtt *ggtt, struct drm_mm_node *node, u32 size)
64{
65 int err;
66
67 err = mutex_lock_interruptible(&ggtt->vm.mutex);
68 if (err)
69 return err;
70
71 memset(node, 0, sizeof(*node));
72 err = drm_mm_insert_node_in_range(&ggtt->vm.mm, node,
73 size, 0, I915_COLOR_UNEVICTABLE,
74 0, ggtt->mappable_end,
75 DRM_MM_INSERT_LOW);
76
77 mutex_unlock(&ggtt->vm.mutex);
78
79 return err;
80}
81
82static void
83remove_mappable_node(struct i915_ggtt *ggtt, struct drm_mm_node *node)
84{
85 mutex_lock(&ggtt->vm.mutex);
86 drm_mm_remove_node(node);
87 mutex_unlock(&ggtt->vm.mutex);
88}
89
90int
91i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
92 struct drm_file *file)
93{
94 struct drm_i915_private *i915 = to_i915(dev);
95 struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
96 struct drm_i915_gem_get_aperture *args = data;
97 struct i915_vma *vma;
98 u64 pinned;
99
100 if (mutex_lock_interruptible(&ggtt->vm.mutex))
101 return -EINTR;
102
103 pinned = ggtt->vm.reserved;
104 list_for_each_entry(vma, &ggtt->vm.bound_list, vm_link)
105 if (i915_vma_is_pinned(vma))
106 pinned += vma->node.size;
107
108 mutex_unlock(&ggtt->vm.mutex);
109
110 args->aper_size = ggtt->vm.total;
111 args->aper_available_size = args->aper_size - pinned;
112
113 return 0;
114}
115
116int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
117 unsigned long flags)
118{
119 struct intel_runtime_pm *rpm = &to_i915(obj->base.dev)->runtime_pm;
120 bool vm_trylock = !!(flags & I915_GEM_OBJECT_UNBIND_VM_TRYLOCK);
121 LIST_HEAD(still_in_list);
122 intel_wakeref_t wakeref;
123 struct i915_vma *vma;
124 int ret;
125
126 assert_object_held(obj);
127
128 if (list_empty(&obj->vma.list))
129 return 0;
130
131 /*
132 * As some machines use ACPI to handle runtime-resume callbacks, and
133 * ACPI is quite kmalloc happy, we cannot resume beneath the vm->mutex
134 * as they are required by the shrinker. Ergo, we wake the device up
135 * first just in case.
136 */
137 wakeref = intel_runtime_pm_get(rpm);
138
139try_again:
140 ret = 0;
141 spin_lock(&obj->vma.lock);
142 while (!ret && (vma = list_first_entry_or_null(&obj->vma.list,
143 struct i915_vma,
144 obj_link))) {
145 list_move_tail(&vma->obj_link, &still_in_list);
146 if (!i915_vma_is_bound(vma, I915_VMA_BIND_MASK))
147 continue;
148
149 if (flags & I915_GEM_OBJECT_UNBIND_TEST) {
150 ret = -EBUSY;
151 break;
152 }
153
154 /*
155 * Requiring the vm destructor to take the object lock
156 * before destroying a vma would help us eliminate the
157 * i915_vm_tryget() here, AND thus also the barrier stuff
158 * at the end. That's an easy fix, but sleeping locks in
159 * a kthread should generally be avoided.
160 */
161 ret = -EAGAIN;
162 if (!i915_vm_tryget(vma->vm))
163 break;
164
165 spin_unlock(&obj->vma.lock);
166
167 /*
168 * Since i915_vma_parked() takes the object lock
169 * before vma destruction, it won't race us here,
170 * and destroy the vma from under us.
171 */
172
173 ret = -EBUSY;
174 if (flags & I915_GEM_OBJECT_UNBIND_ASYNC) {
175 assert_object_held(vma->obj);
176 ret = i915_vma_unbind_async(vma, vm_trylock);
177 }
178
179 if (ret == -EBUSY && (flags & I915_GEM_OBJECT_UNBIND_ACTIVE ||
180 !i915_vma_is_active(vma))) {
181 if (vm_trylock) {
182 if (mutex_trylock(&vma->vm->mutex)) {
183 ret = __i915_vma_unbind(vma);
184 mutex_unlock(&vma->vm->mutex);
185 }
186 } else {
187 ret = i915_vma_unbind(vma);
188 }
189 }
190
191 i915_vm_put(vma->vm);
192 spin_lock(&obj->vma.lock);
193 }
194 list_splice_init(&still_in_list, &obj->vma.list);
195 spin_unlock(&obj->vma.lock);
196
197 if (ret == -EAGAIN && flags & I915_GEM_OBJECT_UNBIND_BARRIER) {
198 rcu_barrier(); /* flush the i915_vm_release() */
199 goto try_again;
200 }
201
202 intel_runtime_pm_put(rpm, wakeref);
203
204 return ret;
205}
206
207static int
208shmem_pread(struct page *page, int offset, int len, char __user *user_data,
209 bool needs_clflush)
210{
211 char *vaddr;
212 int ret;
213
214 vaddr = kmap(page);
215
216 if (needs_clflush)
217 drm_clflush_virt_range(vaddr + offset, len);
218
219 ret = __copy_to_user(user_data, vaddr + offset, len);
220
221 kunmap(page);
222
223 return ret ? -EFAULT : 0;
224}
225
226static int
227i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
228 struct drm_i915_gem_pread *args)
229{
230 unsigned int needs_clflush;
231 char __user *user_data;
232 unsigned long offset;
233 pgoff_t idx;
234 u64 remain;
235 int ret;
236
237 ret = i915_gem_object_lock_interruptible(obj, NULL);
238 if (ret)
239 return ret;
240
241 ret = i915_gem_object_pin_pages(obj);
242 if (ret)
243 goto err_unlock;
244
245 ret = i915_gem_object_prepare_read(obj, &needs_clflush);
246 if (ret)
247 goto err_unpin;
248
249 i915_gem_object_finish_access(obj);
250 i915_gem_object_unlock(obj);
251
252 remain = args->size;
253 user_data = u64_to_user_ptr(args->data_ptr);
254 offset = offset_in_page(args->offset);
255 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
256 struct page *page = i915_gem_object_get_page(obj, idx);
257 unsigned int length = min_t(u64, remain, PAGE_SIZE - offset);
258
259 ret = shmem_pread(page, offset, length, user_data,
260 needs_clflush);
261 if (ret)
262 break;
263
264 remain -= length;
265 user_data += length;
266 offset = 0;
267 }
268
269 i915_gem_object_unpin_pages(obj);
270 return ret;
271
272err_unpin:
273 i915_gem_object_unpin_pages(obj);
274err_unlock:
275 i915_gem_object_unlock(obj);
276 return ret;
277}
278
279static inline bool
280gtt_user_read(struct io_mapping *mapping,
281 loff_t base, int offset,
282 char __user *user_data, int length)
283{
284 void __iomem *vaddr;
285 unsigned long unwritten;
286
287 /* We can use the cpu mem copy function because this is X86. */
288 vaddr = io_mapping_map_atomic_wc(mapping, base);
289 unwritten = __copy_to_user_inatomic(user_data,
290 (void __force *)vaddr + offset,
291 length);
292 io_mapping_unmap_atomic(vaddr);
293 if (unwritten) {
294 vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE);
295 unwritten = copy_to_user(user_data,
296 (void __force *)vaddr + offset,
297 length);
298 io_mapping_unmap(vaddr);
299 }
300 return unwritten;
301}
302
303static struct i915_vma *i915_gem_gtt_prepare(struct drm_i915_gem_object *obj,
304 struct drm_mm_node *node,
305 bool write)
306{
307 struct drm_i915_private *i915 = to_i915(obj->base.dev);
308 struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
309 struct i915_vma *vma;
310 struct i915_gem_ww_ctx ww;
311 int ret;
312
313 i915_gem_ww_ctx_init(&ww, true);
314retry:
315 vma = ERR_PTR(-ENODEV);
316 ret = i915_gem_object_lock(obj, &ww);
317 if (ret)
318 goto err_ww;
319
320 ret = i915_gem_object_set_to_gtt_domain(obj, write);
321 if (ret)
322 goto err_ww;
323
324 if (!i915_gem_object_is_tiled(obj))
325 vma = i915_gem_object_ggtt_pin_ww(obj, &ww, NULL, 0, 0,
326 PIN_MAPPABLE |
327 PIN_NONBLOCK /* NOWARN */ |
328 PIN_NOEVICT);
329 if (vma == ERR_PTR(-EDEADLK)) {
330 ret = -EDEADLK;
331 goto err_ww;
332 } else if (!IS_ERR(vma)) {
333 node->start = i915_ggtt_offset(vma);
334 node->flags = 0;
335 } else {
336 ret = insert_mappable_node(ggtt, node, PAGE_SIZE);
337 if (ret)
338 goto err_ww;
339 GEM_BUG_ON(!drm_mm_node_allocated(node));
340 vma = NULL;
341 }
342
343 ret = i915_gem_object_pin_pages(obj);
344 if (ret) {
345 if (drm_mm_node_allocated(node)) {
346 ggtt->vm.clear_range(&ggtt->vm, node->start, node->size);
347 remove_mappable_node(ggtt, node);
348 } else {
349 i915_vma_unpin(vma);
350 }
351 }
352
353err_ww:
354 if (ret == -EDEADLK) {
355 ret = i915_gem_ww_ctx_backoff(&ww);
356 if (!ret)
357 goto retry;
358 }
359 i915_gem_ww_ctx_fini(&ww);
360
361 return ret ? ERR_PTR(ret) : vma;
362}
363
364static void i915_gem_gtt_cleanup(struct drm_i915_gem_object *obj,
365 struct drm_mm_node *node,
366 struct i915_vma *vma)
367{
368 struct drm_i915_private *i915 = to_i915(obj->base.dev);
369 struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
370
371 i915_gem_object_unpin_pages(obj);
372 if (drm_mm_node_allocated(node)) {
373 ggtt->vm.clear_range(&ggtt->vm, node->start, node->size);
374 remove_mappable_node(ggtt, node);
375 } else {
376 i915_vma_unpin(vma);
377 }
378}
379
380static int
381i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
382 const struct drm_i915_gem_pread *args)
383{
384 struct drm_i915_private *i915 = to_i915(obj->base.dev);
385 struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
386 unsigned long remain, offset;
387 intel_wakeref_t wakeref;
388 struct drm_mm_node node;
389 void __user *user_data;
390 struct i915_vma *vma;
391 int ret = 0;
392
393 if (overflows_type(args->size, remain) ||
394 overflows_type(args->offset, offset))
395 return -EINVAL;
396
397 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
398
399 vma = i915_gem_gtt_prepare(obj, &node, false);
400 if (IS_ERR(vma)) {
401 ret = PTR_ERR(vma);
402 goto out_rpm;
403 }
404
405 user_data = u64_to_user_ptr(args->data_ptr);
406 remain = args->size;
407 offset = args->offset;
408
409 while (remain > 0) {
410 /* Operation in this page
411 *
412 * page_base = page offset within aperture
413 * page_offset = offset within page
414 * page_length = bytes to copy for this page
415 */
416 u32 page_base = node.start;
417 unsigned page_offset = offset_in_page(offset);
418 unsigned page_length = PAGE_SIZE - page_offset;
419 page_length = remain < page_length ? remain : page_length;
420 if (drm_mm_node_allocated(&node)) {
421 ggtt->vm.insert_page(&ggtt->vm,
422 i915_gem_object_get_dma_address(obj,
423 offset >> PAGE_SHIFT),
424 node.start,
425 i915_gem_get_pat_index(i915,
426 I915_CACHE_NONE), 0);
427 } else {
428 page_base += offset & PAGE_MASK;
429 }
430
431 if (gtt_user_read(&ggtt->iomap, page_base, page_offset,
432 user_data, page_length)) {
433 ret = -EFAULT;
434 break;
435 }
436
437 remain -= page_length;
438 user_data += page_length;
439 offset += page_length;
440 }
441
442 i915_gem_gtt_cleanup(obj, &node, vma);
443out_rpm:
444 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
445 return ret;
446}
447
448/**
449 * i915_gem_pread_ioctl - Reads data from the object referenced by handle.
450 * @dev: drm device pointer
451 * @data: ioctl data blob
452 * @file: drm file pointer
453 *
454 * On error, the contents of *data are undefined.
455 */
456int
457i915_gem_pread_ioctl(struct drm_device *dev, void *data,
458 struct drm_file *file)
459{
460 struct drm_i915_private *i915 = to_i915(dev);
461 struct drm_i915_gem_pread *args = data;
462 struct drm_i915_gem_object *obj;
463 int ret;
464
465 /* PREAD is disallowed for all platforms after TGL-LP. This also
466 * covers all platforms with local memory.
467 */
468 if (GRAPHICS_VER(i915) >= 12 && !IS_TIGERLAKE(i915))
469 return -EOPNOTSUPP;
470
471 if (args->size == 0)
472 return 0;
473
474 if (!access_ok(u64_to_user_ptr(args->data_ptr),
475 args->size))
476 return -EFAULT;
477
478 obj = i915_gem_object_lookup(file, args->handle);
479 if (!obj)
480 return -ENOENT;
481
482 /* Bounds check source. */
483 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
484 ret = -EINVAL;
485 goto out;
486 }
487
488 trace_i915_gem_object_pread(obj, args->offset, args->size);
489 ret = -ENODEV;
490 if (obj->ops->pread)
491 ret = obj->ops->pread(obj, args);
492 if (ret != -ENODEV)
493 goto out;
494
495 ret = i915_gem_object_wait(obj,
496 I915_WAIT_INTERRUPTIBLE,
497 MAX_SCHEDULE_TIMEOUT);
498 if (ret)
499 goto out;
500
501 ret = i915_gem_shmem_pread(obj, args);
502 if (ret == -EFAULT || ret == -ENODEV)
503 ret = i915_gem_gtt_pread(obj, args);
504
505out:
506 i915_gem_object_put(obj);
507 return ret;
508}
509
510/* This is the fast write path which cannot handle
511 * page faults in the source data
512 */
513
514static inline bool
515ggtt_write(struct io_mapping *mapping,
516 loff_t base, int offset,
517 char __user *user_data, int length)
518{
519 void __iomem *vaddr;
520 unsigned long unwritten;
521
522 /* We can use the cpu mem copy function because this is X86. */
523 vaddr = io_mapping_map_atomic_wc(mapping, base);
524 unwritten = __copy_from_user_inatomic_nocache((void __force *)vaddr + offset,
525 user_data, length);
526 io_mapping_unmap_atomic(vaddr);
527 if (unwritten) {
528 vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE);
529 unwritten = copy_from_user((void __force *)vaddr + offset,
530 user_data, length);
531 io_mapping_unmap(vaddr);
532 }
533
534 return unwritten;
535}
536
537/**
538 * i915_gem_gtt_pwrite_fast - This is the fast pwrite path, where we copy the data directly from the
539 * user into the GTT, uncached.
540 * @obj: i915 GEM object
541 * @args: pwrite arguments structure
542 */
543static int
544i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
545 const struct drm_i915_gem_pwrite *args)
546{
547 struct drm_i915_private *i915 = to_i915(obj->base.dev);
548 struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
549 struct intel_runtime_pm *rpm = &i915->runtime_pm;
550 unsigned long remain, offset;
551 intel_wakeref_t wakeref;
552 struct drm_mm_node node;
553 struct i915_vma *vma;
554 void __user *user_data;
555 int ret = 0;
556
557 if (overflows_type(args->size, remain) ||
558 overflows_type(args->offset, offset))
559 return -EINVAL;
560
561 if (i915_gem_object_has_struct_page(obj)) {
562 /*
563 * Avoid waking the device up if we can fallback, as
564 * waking/resuming is very slow (worst-case 10-100 ms
565 * depending on PCI sleeps and our own resume time).
566 * This easily dwarfs any performance advantage from
567 * using the cache bypass of indirect GGTT access.
568 */
569 wakeref = intel_runtime_pm_get_if_in_use(rpm);
570 if (!wakeref)
571 return -EFAULT;
572 } else {
573 /* No backing pages, no fallback, we must force GGTT access */
574 wakeref = intel_runtime_pm_get(rpm);
575 }
576
577 vma = i915_gem_gtt_prepare(obj, &node, true);
578 if (IS_ERR(vma)) {
579 ret = PTR_ERR(vma);
580 goto out_rpm;
581 }
582
583 i915_gem_object_invalidate_frontbuffer(obj, ORIGIN_CPU);
584
585 user_data = u64_to_user_ptr(args->data_ptr);
586 offset = args->offset;
587 remain = args->size;
588 while (remain) {
589 /* Operation in this page
590 *
591 * page_base = page offset within aperture
592 * page_offset = offset within page
593 * page_length = bytes to copy for this page
594 */
595 u32 page_base = node.start;
596 unsigned int page_offset = offset_in_page(offset);
597 unsigned int page_length = PAGE_SIZE - page_offset;
598 page_length = remain < page_length ? remain : page_length;
599 if (drm_mm_node_allocated(&node)) {
600 /* flush the write before we modify the GGTT */
601 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
602 ggtt->vm.insert_page(&ggtt->vm,
603 i915_gem_object_get_dma_address(obj,
604 offset >> PAGE_SHIFT),
605 node.start,
606 i915_gem_get_pat_index(i915,
607 I915_CACHE_NONE), 0);
608 wmb(); /* flush modifications to the GGTT (insert_page) */
609 } else {
610 page_base += offset & PAGE_MASK;
611 }
612 /* If we get a fault while copying data, then (presumably) our
613 * source page isn't available. Return the error and we'll
614 * retry in the slow path.
615 * If the object is non-shmem backed, we retry again with the
616 * path that handles page fault.
617 */
618 if (ggtt_write(&ggtt->iomap, page_base, page_offset,
619 user_data, page_length)) {
620 ret = -EFAULT;
621 break;
622 }
623
624 remain -= page_length;
625 user_data += page_length;
626 offset += page_length;
627 }
628
629 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
630 i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
631
632 i915_gem_gtt_cleanup(obj, &node, vma);
633out_rpm:
634 intel_runtime_pm_put(rpm, wakeref);
635 return ret;
636}
637
638/* Per-page copy function for the shmem pwrite fastpath.
639 * Flushes invalid cachelines before writing to the target if
640 * needs_clflush_before is set and flushes out any written cachelines after
641 * writing if needs_clflush is set.
642 */
643static int
644shmem_pwrite(struct page *page, int offset, int len, char __user *user_data,
645 bool needs_clflush_before,
646 bool needs_clflush_after)
647{
648 char *vaddr;
649 int ret;
650
651 vaddr = kmap(page);
652
653 if (needs_clflush_before)
654 drm_clflush_virt_range(vaddr + offset, len);
655
656 ret = __copy_from_user(vaddr + offset, user_data, len);
657 if (!ret && needs_clflush_after)
658 drm_clflush_virt_range(vaddr + offset, len);
659
660 kunmap(page);
661
662 return ret ? -EFAULT : 0;
663}
664
665static int
666i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
667 const struct drm_i915_gem_pwrite *args)
668{
669 unsigned int partial_cacheline_write;
670 unsigned int needs_clflush;
671 void __user *user_data;
672 unsigned long offset;
673 pgoff_t idx;
674 u64 remain;
675 int ret;
676
677 ret = i915_gem_object_lock_interruptible(obj, NULL);
678 if (ret)
679 return ret;
680
681 ret = i915_gem_object_pin_pages(obj);
682 if (ret)
683 goto err_unlock;
684
685 ret = i915_gem_object_prepare_write(obj, &needs_clflush);
686 if (ret)
687 goto err_unpin;
688
689 i915_gem_object_finish_access(obj);
690 i915_gem_object_unlock(obj);
691
692 /* If we don't overwrite a cacheline completely we need to be
693 * careful to have up-to-date data by first clflushing. Don't
694 * overcomplicate things and flush the entire patch.
695 */
696 partial_cacheline_write = 0;
697 if (needs_clflush & CLFLUSH_BEFORE)
698 partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1;
699
700 user_data = u64_to_user_ptr(args->data_ptr);
701 remain = args->size;
702 offset = offset_in_page(args->offset);
703 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
704 struct page *page = i915_gem_object_get_page(obj, idx);
705 unsigned int length = min_t(u64, remain, PAGE_SIZE - offset);
706
707 ret = shmem_pwrite(page, offset, length, user_data,
708 (offset | length) & partial_cacheline_write,
709 needs_clflush & CLFLUSH_AFTER);
710 if (ret)
711 break;
712
713 remain -= length;
714 user_data += length;
715 offset = 0;
716 }
717
718 i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
719
720 i915_gem_object_unpin_pages(obj);
721 return ret;
722
723err_unpin:
724 i915_gem_object_unpin_pages(obj);
725err_unlock:
726 i915_gem_object_unlock(obj);
727 return ret;
728}
729
730/**
731 * i915_gem_pwrite_ioctl - Writes data to the object referenced by handle.
732 * @dev: drm device
733 * @data: ioctl data blob
734 * @file: drm file
735 *
736 * On error, the contents of the buffer that were to be modified are undefined.
737 */
738int
739i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
740 struct drm_file *file)
741{
742 struct drm_i915_private *i915 = to_i915(dev);
743 struct drm_i915_gem_pwrite *args = data;
744 struct drm_i915_gem_object *obj;
745 int ret;
746
747 /* PWRITE is disallowed for all platforms after TGL-LP. This also
748 * covers all platforms with local memory.
749 */
750 if (GRAPHICS_VER(i915) >= 12 && !IS_TIGERLAKE(i915))
751 return -EOPNOTSUPP;
752
753 if (args->size == 0)
754 return 0;
755
756 if (!access_ok(u64_to_user_ptr(args->data_ptr), args->size))
757 return -EFAULT;
758
759 obj = i915_gem_object_lookup(file, args->handle);
760 if (!obj)
761 return -ENOENT;
762
763 /* Bounds check destination. */
764 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
765 ret = -EINVAL;
766 goto err;
767 }
768
769 /* Writes not allowed into this read-only object */
770 if (i915_gem_object_is_readonly(obj)) {
771 ret = -EINVAL;
772 goto err;
773 }
774
775 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
776
777 ret = -ENODEV;
778 if (obj->ops->pwrite)
779 ret = obj->ops->pwrite(obj, args);
780 if (ret != -ENODEV)
781 goto err;
782
783 ret = i915_gem_object_wait(obj,
784 I915_WAIT_INTERRUPTIBLE |
785 I915_WAIT_ALL,
786 MAX_SCHEDULE_TIMEOUT);
787 if (ret)
788 goto err;
789
790 ret = -EFAULT;
791 /* We can only do the GTT pwrite on untiled buffers, as otherwise
792 * it would end up going through the fenced access, and we'll get
793 * different detiling behavior between reading and writing.
794 * pread/pwrite currently are reading and writing from the CPU
795 * perspective, requiring manual detiling by the client.
796 */
797 if (!i915_gem_object_has_struct_page(obj) ||
798 i915_gem_cpu_write_needs_clflush(obj))
799 /* Note that the gtt paths might fail with non-page-backed user
800 * pointers (e.g. gtt mappings when moving data between
801 * textures). Fallback to the shmem path in that case.
802 */
803 ret = i915_gem_gtt_pwrite_fast(obj, args);
804
805 if (ret == -EFAULT || ret == -ENOSPC) {
806 if (i915_gem_object_has_struct_page(obj))
807 ret = i915_gem_shmem_pwrite(obj, args);
808 }
809
810err:
811 i915_gem_object_put(obj);
812 return ret;
813}
814
815/**
816 * i915_gem_sw_finish_ioctl - Called when user space has done writes to this buffer
817 * @dev: drm device
818 * @data: ioctl data blob
819 * @file: drm file
820 */
821int
822i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
823 struct drm_file *file)
824{
825 struct drm_i915_gem_sw_finish *args = data;
826 struct drm_i915_gem_object *obj;
827
828 obj = i915_gem_object_lookup(file, args->handle);
829 if (!obj)
830 return -ENOENT;
831
832 /*
833 * Proxy objects are barred from CPU access, so there is no
834 * need to ban sw_finish as it is a nop.
835 */
836
837 /* Pinned buffers may be scanout, so flush the cache */
838 i915_gem_object_flush_if_display(obj);
839 i915_gem_object_put(obj);
840
841 return 0;
842}
843
844void i915_gem_runtime_suspend(struct drm_i915_private *i915)
845{
846 struct drm_i915_gem_object *obj, *on;
847 int i;
848
849 /*
850 * Only called during RPM suspend. All users of the userfault_list
851 * must be holding an RPM wakeref to ensure that this can not
852 * run concurrently with themselves (and use the struct_mutex for
853 * protection between themselves).
854 */
855
856 list_for_each_entry_safe(obj, on,
857 &to_gt(i915)->ggtt->userfault_list, userfault_link)
858 __i915_gem_object_release_mmap_gtt(obj);
859
860 list_for_each_entry_safe(obj, on,
861 &i915->runtime_pm.lmem_userfault_list, userfault_link)
862 i915_gem_object_runtime_pm_release_mmap_offset(obj);
863
864 /*
865 * The fence will be lost when the device powers down. If any were
866 * in use by hardware (i.e. they are pinned), we should not be powering
867 * down! All other fences will be reacquired by the user upon waking.
868 */
869 for (i = 0; i < to_gt(i915)->ggtt->num_fences; i++) {
870 struct i915_fence_reg *reg = &to_gt(i915)->ggtt->fence_regs[i];
871
872 /*
873 * Ideally we want to assert that the fence register is not
874 * live at this point (i.e. that no piece of code will be
875 * trying to write through fence + GTT, as that both violates
876 * our tracking of activity and associated locking/barriers,
877 * but also is illegal given that the hw is powered down).
878 *
879 * Previously we used reg->pin_count as a "liveness" indicator.
880 * That is not sufficient, and we need a more fine-grained
881 * tool if we want to have a sanity check here.
882 */
883
884 if (!reg->vma)
885 continue;
886
887 GEM_BUG_ON(i915_vma_has_userfault(reg->vma));
888 reg->dirty = true;
889 }
890}
891
892static void discard_ggtt_vma(struct i915_vma *vma)
893{
894 struct drm_i915_gem_object *obj = vma->obj;
895
896 spin_lock(&obj->vma.lock);
897 if (!RB_EMPTY_NODE(&vma->obj_node)) {
898 rb_erase(&vma->obj_node, &obj->vma.tree);
899 RB_CLEAR_NODE(&vma->obj_node);
900 }
901 spin_unlock(&obj->vma.lock);
902}
903
904struct i915_vma *
905i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
906 struct i915_gem_ww_ctx *ww,
907 const struct i915_gtt_view *view,
908 u64 size, u64 alignment, u64 flags)
909{
910 struct drm_i915_private *i915 = to_i915(obj->base.dev);
911 struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
912 struct i915_vma *vma;
913 int ret;
914
915 GEM_WARN_ON(!ww);
916
917 if (flags & PIN_MAPPABLE &&
918 (!view || view->type == I915_GTT_VIEW_NORMAL)) {
919 /*
920 * If the required space is larger than the available
921 * aperture, we will not able to find a slot for the
922 * object and unbinding the object now will be in
923 * vain. Worse, doing so may cause us to ping-pong
924 * the object in and out of the Global GTT and
925 * waste a lot of cycles under the mutex.
926 */
927 if (obj->base.size > ggtt->mappable_end)
928 return ERR_PTR(-E2BIG);
929
930 /*
931 * If NONBLOCK is set the caller is optimistically
932 * trying to cache the full object within the mappable
933 * aperture, and *must* have a fallback in place for
934 * situations where we cannot bind the object. We
935 * can be a little more lax here and use the fallback
936 * more often to avoid costly migrations of ourselves
937 * and other objects within the aperture.
938 *
939 * Half-the-aperture is used as a simple heuristic.
940 * More interesting would to do search for a free
941 * block prior to making the commitment to unbind.
942 * That caters for the self-harm case, and with a
943 * little more heuristics (e.g. NOFAULT, NOEVICT)
944 * we could try to minimise harm to others.
945 */
946 if (flags & PIN_NONBLOCK &&
947 obj->base.size > ggtt->mappable_end / 2)
948 return ERR_PTR(-ENOSPC);
949 }
950
951new_vma:
952 vma = i915_vma_instance(obj, &ggtt->vm, view);
953 if (IS_ERR(vma))
954 return vma;
955
956 if (i915_vma_misplaced(vma, size, alignment, flags)) {
957 if (flags & PIN_NONBLOCK) {
958 if (i915_vma_is_pinned(vma) || i915_vma_is_active(vma))
959 return ERR_PTR(-ENOSPC);
960
961 /*
962 * If this misplaced vma is too big (i.e, at-least
963 * half the size of aperture) or hasn't been pinned
964 * mappable before, we ignore the misplacement when
965 * PIN_NONBLOCK is set in order to avoid the ping-pong
966 * issue described above. In other words, we try to
967 * avoid the costly operation of unbinding this vma
968 * from the GGTT and rebinding it back because there
969 * may not be enough space for this vma in the aperture.
970 */
971 if (flags & PIN_MAPPABLE &&
972 (vma->fence_size > ggtt->mappable_end / 2 ||
973 !i915_vma_is_map_and_fenceable(vma)))
974 return ERR_PTR(-ENOSPC);
975 }
976
977 if (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)) {
978 discard_ggtt_vma(vma);
979 goto new_vma;
980 }
981
982 ret = i915_vma_unbind(vma);
983 if (ret)
984 return ERR_PTR(ret);
985 }
986
987 ret = i915_vma_pin_ww(vma, ww, size, alignment, flags | PIN_GLOBAL);
988
989 if (ret)
990 return ERR_PTR(ret);
991
992 if (vma->fence && !i915_gem_object_is_tiled(obj)) {
993 mutex_lock(&ggtt->vm.mutex);
994 i915_vma_revoke_fence(vma);
995 mutex_unlock(&ggtt->vm.mutex);
996 }
997
998 ret = i915_vma_wait_for_bind(vma);
999 if (ret) {
1000 i915_vma_unpin(vma);
1001 return ERR_PTR(ret);
1002 }
1003
1004 return vma;
1005}
1006
1007struct i915_vma * __must_check
1008i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
1009 const struct i915_gtt_view *view,
1010 u64 size, u64 alignment, u64 flags)
1011{
1012 struct i915_gem_ww_ctx ww;
1013 struct i915_vma *ret;
1014 int err;
1015
1016 for_i915_gem_ww(&ww, err, true) {
1017 err = i915_gem_object_lock(obj, &ww);
1018 if (err)
1019 continue;
1020
1021 ret = i915_gem_object_ggtt_pin_ww(obj, &ww, view, size,
1022 alignment, flags);
1023 if (IS_ERR(ret))
1024 err = PTR_ERR(ret);
1025 }
1026
1027 return err ? ERR_PTR(err) : ret;
1028}
1029
1030int
1031i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1032 struct drm_file *file_priv)
1033{
1034 struct drm_i915_private *i915 = to_i915(dev);
1035 struct drm_i915_gem_madvise *args = data;
1036 struct drm_i915_gem_object *obj;
1037 int err;
1038
1039 switch (args->madv) {
1040 case I915_MADV_DONTNEED:
1041 case I915_MADV_WILLNEED:
1042 break;
1043 default:
1044 return -EINVAL;
1045 }
1046
1047 obj = i915_gem_object_lookup(file_priv, args->handle);
1048 if (!obj)
1049 return -ENOENT;
1050
1051 err = i915_gem_object_lock_interruptible(obj, NULL);
1052 if (err)
1053 goto out;
1054
1055 if (i915_gem_object_has_pages(obj) &&
1056 i915_gem_object_is_tiled(obj) &&
1057 i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES) {
1058 if (obj->mm.madv == I915_MADV_WILLNEED) {
1059 GEM_BUG_ON(!i915_gem_object_has_tiling_quirk(obj));
1060 i915_gem_object_clear_tiling_quirk(obj);
1061 i915_gem_object_make_shrinkable(obj);
1062 }
1063 if (args->madv == I915_MADV_WILLNEED) {
1064 GEM_BUG_ON(i915_gem_object_has_tiling_quirk(obj));
1065 i915_gem_object_make_unshrinkable(obj);
1066 i915_gem_object_set_tiling_quirk(obj);
1067 }
1068 }
1069
1070 if (obj->mm.madv != __I915_MADV_PURGED) {
1071 obj->mm.madv = args->madv;
1072 if (obj->ops->adjust_lru)
1073 obj->ops->adjust_lru(obj);
1074 }
1075
1076 if (i915_gem_object_has_pages(obj) ||
1077 i915_gem_object_has_self_managed_shrink_list(obj)) {
1078 unsigned long flags;
1079
1080 spin_lock_irqsave(&i915->mm.obj_lock, flags);
1081 if (!list_empty(&obj->mm.link)) {
1082 struct list_head *list;
1083
1084 if (obj->mm.madv != I915_MADV_WILLNEED)
1085 list = &i915->mm.purge_list;
1086 else
1087 list = &i915->mm.shrink_list;
1088 list_move_tail(&obj->mm.link, list);
1089
1090 }
1091 spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
1092 }
1093
1094 /* if the object is no longer attached, discard its backing storage */
1095 if (obj->mm.madv == I915_MADV_DONTNEED &&
1096 !i915_gem_object_has_pages(obj))
1097 i915_gem_object_truncate(obj);
1098
1099 args->retained = obj->mm.madv != __I915_MADV_PURGED;
1100
1101 i915_gem_object_unlock(obj);
1102out:
1103 i915_gem_object_put(obj);
1104 return err;
1105}
1106
1107/*
1108 * A single pass should suffice to release all the freed objects (along most
1109 * call paths), but be a little more paranoid in that freeing the objects does
1110 * take a little amount of time, during which the rcu callbacks could have added
1111 * new objects into the freed list, and armed the work again.
1112 */
1113void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
1114{
1115 while (atomic_read(&i915->mm.free_count)) {
1116 flush_work(&i915->mm.free_work);
1117 drain_workqueue(i915->bdev.wq);
1118 rcu_barrier();
1119 }
1120}
1121
1122/*
1123 * Similar to objects above (see i915_gem_drain_freed-objects), in general we
1124 * have workers that are armed by RCU and then rearm themselves in their
1125 * callbacks. To be paranoid, we need to drain the workqueue a second time after
1126 * waiting for the RCU grace period so that we catch work queued via RCU from
1127 * the first pass. As neither drain_workqueue() nor flush_workqueue() report a
1128 * result, we make an assumption that we only don't require more than 3 passes
1129 * to catch all _recursive_ RCU delayed work.
1130 */
1131void i915_gem_drain_workqueue(struct drm_i915_private *i915)
1132{
1133 int i;
1134
1135 for (i = 0; i < 3; i++) {
1136 flush_workqueue(i915->wq);
1137 rcu_barrier();
1138 i915_gem_drain_freed_objects(i915);
1139 }
1140
1141 drain_workqueue(i915->wq);
1142}
1143
1144int i915_gem_init(struct drm_i915_private *dev_priv)
1145{
1146 struct intel_gt *gt;
1147 unsigned int i;
1148 int ret;
1149
1150 /*
1151 * In the proccess of replacing cache_level with pat_index a tricky
1152 * dependency is created on the definition of the enum i915_cache_level.
1153 * in case this enum is changed, PTE encode would be broken.
1154 * Add a WARNING here. And remove when we completely quit using this
1155 * enum
1156 */
1157 BUILD_BUG_ON(I915_CACHE_NONE != 0 ||
1158 I915_CACHE_LLC != 1 ||
1159 I915_CACHE_L3_LLC != 2 ||
1160 I915_CACHE_WT != 3 ||
1161 I915_MAX_CACHE_LEVEL != 4);
1162
1163 /* We need to fallback to 4K pages if host doesn't support huge gtt. */
1164 if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
1165 RUNTIME_INFO(dev_priv)->page_sizes = I915_GTT_PAGE_SIZE_4K;
1166
1167 for_each_gt(gt, dev_priv, i) {
1168 intel_uc_fetch_firmwares(>->uc);
1169 intel_wopcm_init(>->wopcm);
1170 if (GRAPHICS_VER(dev_priv) >= 8)
1171 setup_private_pat(gt);
1172 }
1173
1174 ret = i915_init_ggtt(dev_priv);
1175 if (ret) {
1176 GEM_BUG_ON(ret == -EIO);
1177 goto err_unlock;
1178 }
1179
1180 /*
1181 * Despite its name intel_clock_gating_init applies both display
1182 * clock gating workarounds; GT mmio workarounds and the occasional
1183 * GT power context workaround. Worse, sometimes it includes a context
1184 * register workaround which we need to apply before we record the
1185 * default HW state for all contexts.
1186 *
1187 * FIXME: break up the workarounds and apply them at the right time!
1188 */
1189 intel_clock_gating_init(dev_priv);
1190
1191 for_each_gt(gt, dev_priv, i) {
1192 ret = intel_gt_init(gt);
1193 if (ret)
1194 goto err_unlock;
1195 }
1196
1197 /*
1198 * Register engines early to ensure the engine list is in its final
1199 * rb-tree form, lowering the amount of code that has to deal with
1200 * the intermediate llist state.
1201 */
1202 intel_engines_driver_register(dev_priv);
1203
1204 return 0;
1205
1206 /*
1207 * Unwinding is complicated by that we want to handle -EIO to mean
1208 * disable GPU submission but keep KMS alive. We want to mark the
1209 * HW as irrevisibly wedged, but keep enough state around that the
1210 * driver doesn't explode during runtime.
1211 */
1212err_unlock:
1213 i915_gem_drain_workqueue(dev_priv);
1214
1215 if (ret != -EIO) {
1216 for_each_gt(gt, dev_priv, i) {
1217 intel_gt_driver_remove(gt);
1218 intel_gt_driver_release(gt);
1219 intel_uc_cleanup_firmwares(>->uc);
1220 }
1221 }
1222
1223 if (ret == -EIO) {
1224 /*
1225 * Allow engines or uC initialisation to fail by marking the GPU
1226 * as wedged. But we only want to do this when the GPU is angry,
1227 * for all other failure, such as an allocation failure, bail.
1228 */
1229 for_each_gt(gt, dev_priv, i) {
1230 if (!intel_gt_is_wedged(gt)) {
1231 i915_probe_error(dev_priv,
1232 "Failed to initialize GPU, declaring it wedged!\n");
1233 intel_gt_set_wedged(gt);
1234 }
1235 }
1236
1237 /* Minimal basic recovery for KMS */
1238 ret = i915_ggtt_enable_hw(dev_priv);
1239 i915_ggtt_resume(to_gt(dev_priv)->ggtt);
1240 intel_clock_gating_init(dev_priv);
1241 }
1242
1243 i915_gem_drain_freed_objects(dev_priv);
1244
1245 return ret;
1246}
1247
1248void i915_gem_driver_register(struct drm_i915_private *i915)
1249{
1250 i915_gem_driver_register__shrinker(i915);
1251}
1252
1253void i915_gem_driver_unregister(struct drm_i915_private *i915)
1254{
1255 i915_gem_driver_unregister__shrinker(i915);
1256}
1257
1258void i915_gem_driver_remove(struct drm_i915_private *dev_priv)
1259{
1260 struct intel_gt *gt;
1261 unsigned int i;
1262
1263 i915_gem_suspend_late(dev_priv);
1264 for_each_gt(gt, dev_priv, i)
1265 intel_gt_driver_remove(gt);
1266 dev_priv->uabi_engines = RB_ROOT;
1267
1268 /* Flush any outstanding unpin_work. */
1269 i915_gem_drain_workqueue(dev_priv);
1270}
1271
1272void i915_gem_driver_release(struct drm_i915_private *dev_priv)
1273{
1274 struct intel_gt *gt;
1275 unsigned int i;
1276
1277 for_each_gt(gt, dev_priv, i) {
1278 intel_gt_driver_release(gt);
1279 intel_uc_cleanup_firmwares(>->uc);
1280 }
1281
1282 /* Flush any outstanding work, including i915_gem_context.release_work. */
1283 i915_gem_drain_workqueue(dev_priv);
1284
1285 drm_WARN_ON(&dev_priv->drm, !list_empty(&dev_priv->gem.contexts.list));
1286}
1287
1288static void i915_gem_init__mm(struct drm_i915_private *i915)
1289{
1290 spin_lock_init(&i915->mm.obj_lock);
1291
1292 init_llist_head(&i915->mm.free_list);
1293
1294 INIT_LIST_HEAD(&i915->mm.purge_list);
1295 INIT_LIST_HEAD(&i915->mm.shrink_list);
1296
1297 i915_gem_init__objects(i915);
1298}
1299
1300void i915_gem_init_early(struct drm_i915_private *dev_priv)
1301{
1302 i915_gem_init__mm(dev_priv);
1303 i915_gem_init__contexts(dev_priv);
1304}
1305
1306void i915_gem_cleanup_early(struct drm_i915_private *dev_priv)
1307{
1308 i915_gem_drain_workqueue(dev_priv);
1309 GEM_BUG_ON(!llist_empty(&dev_priv->mm.free_list));
1310 GEM_BUG_ON(atomic_read(&dev_priv->mm.free_count));
1311 drm_WARN_ON(&dev_priv->drm, dev_priv->mm.shrink_count);
1312}
1313
1314int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file)
1315{
1316 struct drm_i915_file_private *file_priv;
1317 struct i915_drm_client *client;
1318 int ret = -ENOMEM;
1319
1320 drm_dbg(&i915->drm, "\n");
1321
1322 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
1323 if (!file_priv)
1324 goto err_alloc;
1325
1326 client = i915_drm_client_alloc();
1327 if (!client)
1328 goto err_client;
1329
1330 file->driver_priv = file_priv;
1331 file_priv->i915 = i915;
1332 file_priv->file = file;
1333 file_priv->client = client;
1334
1335 file_priv->bsd_engine = -1;
1336 file_priv->hang_timestamp = jiffies;
1337
1338 ret = i915_gem_context_open(i915, file);
1339 if (ret)
1340 goto err_context;
1341
1342 return 0;
1343
1344err_context:
1345 i915_drm_client_put(client);
1346err_client:
1347 kfree(file_priv);
1348err_alloc:
1349 return ret;
1350}
1351
1352#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1353#include "selftests/mock_gem_device.c"
1354#include "selftests/i915_gem.c"
1355#endif
1/*
2 * Copyright © 2008-2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include <drm/drmP.h>
29#include <drm/drm_vma_manager.h>
30#include <drm/i915_drm.h>
31#include "i915_drv.h"
32#include "i915_vgpu.h"
33#include "i915_trace.h"
34#include "intel_drv.h"
35#include "intel_frontbuffer.h"
36#include "intel_mocs.h"
37#include <linux/dma-fence-array.h>
38#include <linux/reservation.h>
39#include <linux/shmem_fs.h>
40#include <linux/slab.h>
41#include <linux/swap.h>
42#include <linux/pci.h>
43#include <linux/dma-buf.h>
44
45static void i915_gem_flush_free_objects(struct drm_i915_private *i915);
46static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
47static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
48
49static bool cpu_cache_is_coherent(struct drm_device *dev,
50 enum i915_cache_level level)
51{
52 return HAS_LLC(to_i915(dev)) || level != I915_CACHE_NONE;
53}
54
55static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
56{
57 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
58 return false;
59
60 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
61 return true;
62
63 return obj->pin_display;
64}
65
66static int
67insert_mappable_node(struct i915_ggtt *ggtt,
68 struct drm_mm_node *node, u32 size)
69{
70 memset(node, 0, sizeof(*node));
71 return drm_mm_insert_node_in_range_generic(&ggtt->base.mm, node,
72 size, 0, -1,
73 0, ggtt->mappable_end,
74 DRM_MM_SEARCH_DEFAULT,
75 DRM_MM_CREATE_DEFAULT);
76}
77
78static void
79remove_mappable_node(struct drm_mm_node *node)
80{
81 drm_mm_remove_node(node);
82}
83
84/* some bookkeeping */
85static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
86 u64 size)
87{
88 spin_lock(&dev_priv->mm.object_stat_lock);
89 dev_priv->mm.object_count++;
90 dev_priv->mm.object_memory += size;
91 spin_unlock(&dev_priv->mm.object_stat_lock);
92}
93
94static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
95 u64 size)
96{
97 spin_lock(&dev_priv->mm.object_stat_lock);
98 dev_priv->mm.object_count--;
99 dev_priv->mm.object_memory -= size;
100 spin_unlock(&dev_priv->mm.object_stat_lock);
101}
102
103static int
104i915_gem_wait_for_error(struct i915_gpu_error *error)
105{
106 int ret;
107
108 might_sleep();
109
110 if (!i915_reset_in_progress(error))
111 return 0;
112
113 /*
114 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
115 * userspace. If it takes that long something really bad is going on and
116 * we should simply try to bail out and fail as gracefully as possible.
117 */
118 ret = wait_event_interruptible_timeout(error->reset_queue,
119 !i915_reset_in_progress(error),
120 I915_RESET_TIMEOUT);
121 if (ret == 0) {
122 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
123 return -EIO;
124 } else if (ret < 0) {
125 return ret;
126 } else {
127 return 0;
128 }
129}
130
131int i915_mutex_lock_interruptible(struct drm_device *dev)
132{
133 struct drm_i915_private *dev_priv = to_i915(dev);
134 int ret;
135
136 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
137 if (ret)
138 return ret;
139
140 ret = mutex_lock_interruptible(&dev->struct_mutex);
141 if (ret)
142 return ret;
143
144 return 0;
145}
146
147int
148i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
149 struct drm_file *file)
150{
151 struct drm_i915_private *dev_priv = to_i915(dev);
152 struct i915_ggtt *ggtt = &dev_priv->ggtt;
153 struct drm_i915_gem_get_aperture *args = data;
154 struct i915_vma *vma;
155 size_t pinned;
156
157 pinned = 0;
158 mutex_lock(&dev->struct_mutex);
159 list_for_each_entry(vma, &ggtt->base.active_list, vm_link)
160 if (i915_vma_is_pinned(vma))
161 pinned += vma->node.size;
162 list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link)
163 if (i915_vma_is_pinned(vma))
164 pinned += vma->node.size;
165 mutex_unlock(&dev->struct_mutex);
166
167 args->aper_size = ggtt->base.total;
168 args->aper_available_size = args->aper_size - pinned;
169
170 return 0;
171}
172
173static struct sg_table *
174i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
175{
176 struct address_space *mapping = obj->base.filp->f_mapping;
177 drm_dma_handle_t *phys;
178 struct sg_table *st;
179 struct scatterlist *sg;
180 char *vaddr;
181 int i;
182
183 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
184 return ERR_PTR(-EINVAL);
185
186 /* Always aligning to the object size, allows a single allocation
187 * to handle all possible callers, and given typical object sizes,
188 * the alignment of the buddy allocation will naturally match.
189 */
190 phys = drm_pci_alloc(obj->base.dev,
191 obj->base.size,
192 roundup_pow_of_two(obj->base.size));
193 if (!phys)
194 return ERR_PTR(-ENOMEM);
195
196 vaddr = phys->vaddr;
197 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
198 struct page *page;
199 char *src;
200
201 page = shmem_read_mapping_page(mapping, i);
202 if (IS_ERR(page)) {
203 st = ERR_CAST(page);
204 goto err_phys;
205 }
206
207 src = kmap_atomic(page);
208 memcpy(vaddr, src, PAGE_SIZE);
209 drm_clflush_virt_range(vaddr, PAGE_SIZE);
210 kunmap_atomic(src);
211
212 put_page(page);
213 vaddr += PAGE_SIZE;
214 }
215
216 i915_gem_chipset_flush(to_i915(obj->base.dev));
217
218 st = kmalloc(sizeof(*st), GFP_KERNEL);
219 if (!st) {
220 st = ERR_PTR(-ENOMEM);
221 goto err_phys;
222 }
223
224 if (sg_alloc_table(st, 1, GFP_KERNEL)) {
225 kfree(st);
226 st = ERR_PTR(-ENOMEM);
227 goto err_phys;
228 }
229
230 sg = st->sgl;
231 sg->offset = 0;
232 sg->length = obj->base.size;
233
234 sg_dma_address(sg) = phys->busaddr;
235 sg_dma_len(sg) = obj->base.size;
236
237 obj->phys_handle = phys;
238 return st;
239
240err_phys:
241 drm_pci_free(obj->base.dev, phys);
242 return st;
243}
244
245static void
246__i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
247 struct sg_table *pages,
248 bool needs_clflush)
249{
250 GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
251
252 if (obj->mm.madv == I915_MADV_DONTNEED)
253 obj->mm.dirty = false;
254
255 if (needs_clflush &&
256 (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 &&
257 !cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
258 drm_clflush_sg(pages);
259
260 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
261 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
262}
263
264static void
265i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj,
266 struct sg_table *pages)
267{
268 __i915_gem_object_release_shmem(obj, pages, false);
269
270 if (obj->mm.dirty) {
271 struct address_space *mapping = obj->base.filp->f_mapping;
272 char *vaddr = obj->phys_handle->vaddr;
273 int i;
274
275 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
276 struct page *page;
277 char *dst;
278
279 page = shmem_read_mapping_page(mapping, i);
280 if (IS_ERR(page))
281 continue;
282
283 dst = kmap_atomic(page);
284 drm_clflush_virt_range(vaddr, PAGE_SIZE);
285 memcpy(dst, vaddr, PAGE_SIZE);
286 kunmap_atomic(dst);
287
288 set_page_dirty(page);
289 if (obj->mm.madv == I915_MADV_WILLNEED)
290 mark_page_accessed(page);
291 put_page(page);
292 vaddr += PAGE_SIZE;
293 }
294 obj->mm.dirty = false;
295 }
296
297 sg_free_table(pages);
298 kfree(pages);
299
300 drm_pci_free(obj->base.dev, obj->phys_handle);
301}
302
303static void
304i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
305{
306 i915_gem_object_unpin_pages(obj);
307}
308
309static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
310 .get_pages = i915_gem_object_get_pages_phys,
311 .put_pages = i915_gem_object_put_pages_phys,
312 .release = i915_gem_object_release_phys,
313};
314
315int i915_gem_object_unbind(struct drm_i915_gem_object *obj)
316{
317 struct i915_vma *vma;
318 LIST_HEAD(still_in_list);
319 int ret;
320
321 lockdep_assert_held(&obj->base.dev->struct_mutex);
322
323 /* Closed vma are removed from the obj->vma_list - but they may
324 * still have an active binding on the object. To remove those we
325 * must wait for all rendering to complete to the object (as unbinding
326 * must anyway), and retire the requests.
327 */
328 ret = i915_gem_object_wait(obj,
329 I915_WAIT_INTERRUPTIBLE |
330 I915_WAIT_LOCKED |
331 I915_WAIT_ALL,
332 MAX_SCHEDULE_TIMEOUT,
333 NULL);
334 if (ret)
335 return ret;
336
337 i915_gem_retire_requests(to_i915(obj->base.dev));
338
339 while ((vma = list_first_entry_or_null(&obj->vma_list,
340 struct i915_vma,
341 obj_link))) {
342 list_move_tail(&vma->obj_link, &still_in_list);
343 ret = i915_vma_unbind(vma);
344 if (ret)
345 break;
346 }
347 list_splice(&still_in_list, &obj->vma_list);
348
349 return ret;
350}
351
352static long
353i915_gem_object_wait_fence(struct dma_fence *fence,
354 unsigned int flags,
355 long timeout,
356 struct intel_rps_client *rps)
357{
358 struct drm_i915_gem_request *rq;
359
360 BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1);
361
362 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
363 return timeout;
364
365 if (!dma_fence_is_i915(fence))
366 return dma_fence_wait_timeout(fence,
367 flags & I915_WAIT_INTERRUPTIBLE,
368 timeout);
369
370 rq = to_request(fence);
371 if (i915_gem_request_completed(rq))
372 goto out;
373
374 /* This client is about to stall waiting for the GPU. In many cases
375 * this is undesirable and limits the throughput of the system, as
376 * many clients cannot continue processing user input/output whilst
377 * blocked. RPS autotuning may take tens of milliseconds to respond
378 * to the GPU load and thus incurs additional latency for the client.
379 * We can circumvent that by promoting the GPU frequency to maximum
380 * before we wait. This makes the GPU throttle up much more quickly
381 * (good for benchmarks and user experience, e.g. window animations),
382 * but at a cost of spending more power processing the workload
383 * (bad for battery). Not all clients even want their results
384 * immediately and for them we should just let the GPU select its own
385 * frequency to maximise efficiency. To prevent a single client from
386 * forcing the clocks too high for the whole system, we only allow
387 * each client to waitboost once in a busy period.
388 */
389 if (rps) {
390 if (INTEL_GEN(rq->i915) >= 6)
391 gen6_rps_boost(rq->i915, rps, rq->emitted_jiffies);
392 else
393 rps = NULL;
394 }
395
396 timeout = i915_wait_request(rq, flags, timeout);
397
398out:
399 if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq))
400 i915_gem_request_retire_upto(rq);
401
402 if (rps && rq->global_seqno == intel_engine_last_submit(rq->engine)) {
403 /* The GPU is now idle and this client has stalled.
404 * Since no other client has submitted a request in the
405 * meantime, assume that this client is the only one
406 * supplying work to the GPU but is unable to keep that
407 * work supplied because it is waiting. Since the GPU is
408 * then never kept fully busy, RPS autoclocking will
409 * keep the clocks relatively low, causing further delays.
410 * Compensate by giving the synchronous client credit for
411 * a waitboost next time.
412 */
413 spin_lock(&rq->i915->rps.client_lock);
414 list_del_init(&rps->link);
415 spin_unlock(&rq->i915->rps.client_lock);
416 }
417
418 return timeout;
419}
420
421static long
422i915_gem_object_wait_reservation(struct reservation_object *resv,
423 unsigned int flags,
424 long timeout,
425 struct intel_rps_client *rps)
426{
427 struct dma_fence *excl;
428
429 if (flags & I915_WAIT_ALL) {
430 struct dma_fence **shared;
431 unsigned int count, i;
432 int ret;
433
434 ret = reservation_object_get_fences_rcu(resv,
435 &excl, &count, &shared);
436 if (ret)
437 return ret;
438
439 for (i = 0; i < count; i++) {
440 timeout = i915_gem_object_wait_fence(shared[i],
441 flags, timeout,
442 rps);
443 if (timeout < 0)
444 break;
445
446 dma_fence_put(shared[i]);
447 }
448
449 for (; i < count; i++)
450 dma_fence_put(shared[i]);
451 kfree(shared);
452 } else {
453 excl = reservation_object_get_excl_rcu(resv);
454 }
455
456 if (excl && timeout >= 0)
457 timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps);
458
459 dma_fence_put(excl);
460
461 return timeout;
462}
463
464static void __fence_set_priority(struct dma_fence *fence, int prio)
465{
466 struct drm_i915_gem_request *rq;
467 struct intel_engine_cs *engine;
468
469 if (!dma_fence_is_i915(fence))
470 return;
471
472 rq = to_request(fence);
473 engine = rq->engine;
474 if (!engine->schedule)
475 return;
476
477 engine->schedule(rq, prio);
478}
479
480static void fence_set_priority(struct dma_fence *fence, int prio)
481{
482 /* Recurse once into a fence-array */
483 if (dma_fence_is_array(fence)) {
484 struct dma_fence_array *array = to_dma_fence_array(fence);
485 int i;
486
487 for (i = 0; i < array->num_fences; i++)
488 __fence_set_priority(array->fences[i], prio);
489 } else {
490 __fence_set_priority(fence, prio);
491 }
492}
493
494int
495i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
496 unsigned int flags,
497 int prio)
498{
499 struct dma_fence *excl;
500
501 if (flags & I915_WAIT_ALL) {
502 struct dma_fence **shared;
503 unsigned int count, i;
504 int ret;
505
506 ret = reservation_object_get_fences_rcu(obj->resv,
507 &excl, &count, &shared);
508 if (ret)
509 return ret;
510
511 for (i = 0; i < count; i++) {
512 fence_set_priority(shared[i], prio);
513 dma_fence_put(shared[i]);
514 }
515
516 kfree(shared);
517 } else {
518 excl = reservation_object_get_excl_rcu(obj->resv);
519 }
520
521 if (excl) {
522 fence_set_priority(excl, prio);
523 dma_fence_put(excl);
524 }
525 return 0;
526}
527
528/**
529 * Waits for rendering to the object to be completed
530 * @obj: i915 gem object
531 * @flags: how to wait (under a lock, for all rendering or just for writes etc)
532 * @timeout: how long to wait
533 * @rps: client (user process) to charge for any waitboosting
534 */
535int
536i915_gem_object_wait(struct drm_i915_gem_object *obj,
537 unsigned int flags,
538 long timeout,
539 struct intel_rps_client *rps)
540{
541 might_sleep();
542#if IS_ENABLED(CONFIG_LOCKDEP)
543 GEM_BUG_ON(debug_locks &&
544 !!lockdep_is_held(&obj->base.dev->struct_mutex) !=
545 !!(flags & I915_WAIT_LOCKED));
546#endif
547 GEM_BUG_ON(timeout < 0);
548
549 timeout = i915_gem_object_wait_reservation(obj->resv,
550 flags, timeout,
551 rps);
552 return timeout < 0 ? timeout : 0;
553}
554
555static struct intel_rps_client *to_rps_client(struct drm_file *file)
556{
557 struct drm_i915_file_private *fpriv = file->driver_priv;
558
559 return &fpriv->rps;
560}
561
562int
563i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
564 int align)
565{
566 int ret;
567
568 if (align > obj->base.size)
569 return -EINVAL;
570
571 if (obj->ops == &i915_gem_phys_ops)
572 return 0;
573
574 if (obj->mm.madv != I915_MADV_WILLNEED)
575 return -EFAULT;
576
577 if (obj->base.filp == NULL)
578 return -EINVAL;
579
580 ret = i915_gem_object_unbind(obj);
581 if (ret)
582 return ret;
583
584 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
585 if (obj->mm.pages)
586 return -EBUSY;
587
588 obj->ops = &i915_gem_phys_ops;
589
590 return i915_gem_object_pin_pages(obj);
591}
592
593static int
594i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
595 struct drm_i915_gem_pwrite *args,
596 struct drm_file *file)
597{
598 void *vaddr = obj->phys_handle->vaddr + args->offset;
599 char __user *user_data = u64_to_user_ptr(args->data_ptr);
600
601 /* We manually control the domain here and pretend that it
602 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
603 */
604 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
605 if (copy_from_user(vaddr, user_data, args->size))
606 return -EFAULT;
607
608 drm_clflush_virt_range(vaddr, args->size);
609 i915_gem_chipset_flush(to_i915(obj->base.dev));
610
611 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
612 return 0;
613}
614
615void *i915_gem_object_alloc(struct drm_device *dev)
616{
617 struct drm_i915_private *dev_priv = to_i915(dev);
618 return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
619}
620
621void i915_gem_object_free(struct drm_i915_gem_object *obj)
622{
623 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
624 kmem_cache_free(dev_priv->objects, obj);
625}
626
627static int
628i915_gem_create(struct drm_file *file,
629 struct drm_device *dev,
630 uint64_t size,
631 uint32_t *handle_p)
632{
633 struct drm_i915_gem_object *obj;
634 int ret;
635 u32 handle;
636
637 size = roundup(size, PAGE_SIZE);
638 if (size == 0)
639 return -EINVAL;
640
641 /* Allocate the new object */
642 obj = i915_gem_object_create(dev, size);
643 if (IS_ERR(obj))
644 return PTR_ERR(obj);
645
646 ret = drm_gem_handle_create(file, &obj->base, &handle);
647 /* drop reference from allocate - handle holds it now */
648 i915_gem_object_put(obj);
649 if (ret)
650 return ret;
651
652 *handle_p = handle;
653 return 0;
654}
655
656int
657i915_gem_dumb_create(struct drm_file *file,
658 struct drm_device *dev,
659 struct drm_mode_create_dumb *args)
660{
661 /* have to work out size/pitch and return them */
662 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
663 args->size = args->pitch * args->height;
664 return i915_gem_create(file, dev,
665 args->size, &args->handle);
666}
667
668/**
669 * Creates a new mm object and returns a handle to it.
670 * @dev: drm device pointer
671 * @data: ioctl data blob
672 * @file: drm file pointer
673 */
674int
675i915_gem_create_ioctl(struct drm_device *dev, void *data,
676 struct drm_file *file)
677{
678 struct drm_i915_gem_create *args = data;
679
680 i915_gem_flush_free_objects(to_i915(dev));
681
682 return i915_gem_create(file, dev,
683 args->size, &args->handle);
684}
685
686static inline int
687__copy_to_user_swizzled(char __user *cpu_vaddr,
688 const char *gpu_vaddr, int gpu_offset,
689 int length)
690{
691 int ret, cpu_offset = 0;
692
693 while (length > 0) {
694 int cacheline_end = ALIGN(gpu_offset + 1, 64);
695 int this_length = min(cacheline_end - gpu_offset, length);
696 int swizzled_gpu_offset = gpu_offset ^ 64;
697
698 ret = __copy_to_user(cpu_vaddr + cpu_offset,
699 gpu_vaddr + swizzled_gpu_offset,
700 this_length);
701 if (ret)
702 return ret + length;
703
704 cpu_offset += this_length;
705 gpu_offset += this_length;
706 length -= this_length;
707 }
708
709 return 0;
710}
711
712static inline int
713__copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
714 const char __user *cpu_vaddr,
715 int length)
716{
717 int ret, cpu_offset = 0;
718
719 while (length > 0) {
720 int cacheline_end = ALIGN(gpu_offset + 1, 64);
721 int this_length = min(cacheline_end - gpu_offset, length);
722 int swizzled_gpu_offset = gpu_offset ^ 64;
723
724 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
725 cpu_vaddr + cpu_offset,
726 this_length);
727 if (ret)
728 return ret + length;
729
730 cpu_offset += this_length;
731 gpu_offset += this_length;
732 length -= this_length;
733 }
734
735 return 0;
736}
737
738/*
739 * Pins the specified object's pages and synchronizes the object with
740 * GPU accesses. Sets needs_clflush to non-zero if the caller should
741 * flush the object from the CPU cache.
742 */
743int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
744 unsigned int *needs_clflush)
745{
746 int ret;
747
748 lockdep_assert_held(&obj->base.dev->struct_mutex);
749
750 *needs_clflush = 0;
751 if (!i915_gem_object_has_struct_page(obj))
752 return -ENODEV;
753
754 ret = i915_gem_object_wait(obj,
755 I915_WAIT_INTERRUPTIBLE |
756 I915_WAIT_LOCKED,
757 MAX_SCHEDULE_TIMEOUT,
758 NULL);
759 if (ret)
760 return ret;
761
762 ret = i915_gem_object_pin_pages(obj);
763 if (ret)
764 return ret;
765
766 i915_gem_object_flush_gtt_write_domain(obj);
767
768 /* If we're not in the cpu read domain, set ourself into the gtt
769 * read domain and manually flush cachelines (if required). This
770 * optimizes for the case when the gpu will dirty the data
771 * anyway again before the next pread happens.
772 */
773 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
774 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
775 obj->cache_level);
776
777 if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) {
778 ret = i915_gem_object_set_to_cpu_domain(obj, false);
779 if (ret)
780 goto err_unpin;
781
782 *needs_clflush = 0;
783 }
784
785 /* return with the pages pinned */
786 return 0;
787
788err_unpin:
789 i915_gem_object_unpin_pages(obj);
790 return ret;
791}
792
793int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
794 unsigned int *needs_clflush)
795{
796 int ret;
797
798 lockdep_assert_held(&obj->base.dev->struct_mutex);
799
800 *needs_clflush = 0;
801 if (!i915_gem_object_has_struct_page(obj))
802 return -ENODEV;
803
804 ret = i915_gem_object_wait(obj,
805 I915_WAIT_INTERRUPTIBLE |
806 I915_WAIT_LOCKED |
807 I915_WAIT_ALL,
808 MAX_SCHEDULE_TIMEOUT,
809 NULL);
810 if (ret)
811 return ret;
812
813 ret = i915_gem_object_pin_pages(obj);
814 if (ret)
815 return ret;
816
817 i915_gem_object_flush_gtt_write_domain(obj);
818
819 /* If we're not in the cpu write domain, set ourself into the
820 * gtt write domain and manually flush cachelines (as required).
821 * This optimizes for the case when the gpu will use the data
822 * right away and we therefore have to clflush anyway.
823 */
824 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
825 *needs_clflush |= cpu_write_needs_clflush(obj) << 1;
826
827 /* Same trick applies to invalidate partially written cachelines read
828 * before writing.
829 */
830 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU))
831 *needs_clflush |= !cpu_cache_is_coherent(obj->base.dev,
832 obj->cache_level);
833
834 if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) {
835 ret = i915_gem_object_set_to_cpu_domain(obj, true);
836 if (ret)
837 goto err_unpin;
838
839 *needs_clflush = 0;
840 }
841
842 if ((*needs_clflush & CLFLUSH_AFTER) == 0)
843 obj->cache_dirty = true;
844
845 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
846 obj->mm.dirty = true;
847 /* return with the pages pinned */
848 return 0;
849
850err_unpin:
851 i915_gem_object_unpin_pages(obj);
852 return ret;
853}
854
855static void
856shmem_clflush_swizzled_range(char *addr, unsigned long length,
857 bool swizzled)
858{
859 if (unlikely(swizzled)) {
860 unsigned long start = (unsigned long) addr;
861 unsigned long end = (unsigned long) addr + length;
862
863 /* For swizzling simply ensure that we always flush both
864 * channels. Lame, but simple and it works. Swizzled
865 * pwrite/pread is far from a hotpath - current userspace
866 * doesn't use it at all. */
867 start = round_down(start, 128);
868 end = round_up(end, 128);
869
870 drm_clflush_virt_range((void *)start, end - start);
871 } else {
872 drm_clflush_virt_range(addr, length);
873 }
874
875}
876
877/* Only difference to the fast-path function is that this can handle bit17
878 * and uses non-atomic copy and kmap functions. */
879static int
880shmem_pread_slow(struct page *page, int offset, int length,
881 char __user *user_data,
882 bool page_do_bit17_swizzling, bool needs_clflush)
883{
884 char *vaddr;
885 int ret;
886
887 vaddr = kmap(page);
888 if (needs_clflush)
889 shmem_clflush_swizzled_range(vaddr + offset, length,
890 page_do_bit17_swizzling);
891
892 if (page_do_bit17_swizzling)
893 ret = __copy_to_user_swizzled(user_data, vaddr, offset, length);
894 else
895 ret = __copy_to_user(user_data, vaddr + offset, length);
896 kunmap(page);
897
898 return ret ? - EFAULT : 0;
899}
900
901static int
902shmem_pread(struct page *page, int offset, int length, char __user *user_data,
903 bool page_do_bit17_swizzling, bool needs_clflush)
904{
905 int ret;
906
907 ret = -ENODEV;
908 if (!page_do_bit17_swizzling) {
909 char *vaddr = kmap_atomic(page);
910
911 if (needs_clflush)
912 drm_clflush_virt_range(vaddr + offset, length);
913 ret = __copy_to_user_inatomic(user_data, vaddr + offset, length);
914 kunmap_atomic(vaddr);
915 }
916 if (ret == 0)
917 return 0;
918
919 return shmem_pread_slow(page, offset, length, user_data,
920 page_do_bit17_swizzling, needs_clflush);
921}
922
923static int
924i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
925 struct drm_i915_gem_pread *args)
926{
927 char __user *user_data;
928 u64 remain;
929 unsigned int obj_do_bit17_swizzling;
930 unsigned int needs_clflush;
931 unsigned int idx, offset;
932 int ret;
933
934 obj_do_bit17_swizzling = 0;
935 if (i915_gem_object_needs_bit17_swizzle(obj))
936 obj_do_bit17_swizzling = BIT(17);
937
938 ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex);
939 if (ret)
940 return ret;
941
942 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
943 mutex_unlock(&obj->base.dev->struct_mutex);
944 if (ret)
945 return ret;
946
947 remain = args->size;
948 user_data = u64_to_user_ptr(args->data_ptr);
949 offset = offset_in_page(args->offset);
950 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
951 struct page *page = i915_gem_object_get_page(obj, idx);
952 int length;
953
954 length = remain;
955 if (offset + length > PAGE_SIZE)
956 length = PAGE_SIZE - offset;
957
958 ret = shmem_pread(page, offset, length, user_data,
959 page_to_phys(page) & obj_do_bit17_swizzling,
960 needs_clflush);
961 if (ret)
962 break;
963
964 remain -= length;
965 user_data += length;
966 offset = 0;
967 }
968
969 i915_gem_obj_finish_shmem_access(obj);
970 return ret;
971}
972
973static inline bool
974gtt_user_read(struct io_mapping *mapping,
975 loff_t base, int offset,
976 char __user *user_data, int length)
977{
978 void *vaddr;
979 unsigned long unwritten;
980
981 /* We can use the cpu mem copy function because this is X86. */
982 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
983 unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length);
984 io_mapping_unmap_atomic(vaddr);
985 if (unwritten) {
986 vaddr = (void __force *)
987 io_mapping_map_wc(mapping, base, PAGE_SIZE);
988 unwritten = copy_to_user(user_data, vaddr + offset, length);
989 io_mapping_unmap(vaddr);
990 }
991 return unwritten;
992}
993
994static int
995i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
996 const struct drm_i915_gem_pread *args)
997{
998 struct drm_i915_private *i915 = to_i915(obj->base.dev);
999 struct i915_ggtt *ggtt = &i915->ggtt;
1000 struct drm_mm_node node;
1001 struct i915_vma *vma;
1002 void __user *user_data;
1003 u64 remain, offset;
1004 int ret;
1005
1006 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1007 if (ret)
1008 return ret;
1009
1010 intel_runtime_pm_get(i915);
1011 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1012 PIN_MAPPABLE | PIN_NONBLOCK);
1013 if (!IS_ERR(vma)) {
1014 node.start = i915_ggtt_offset(vma);
1015 node.allocated = false;
1016 ret = i915_vma_put_fence(vma);
1017 if (ret) {
1018 i915_vma_unpin(vma);
1019 vma = ERR_PTR(ret);
1020 }
1021 }
1022 if (IS_ERR(vma)) {
1023 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1024 if (ret)
1025 goto out_unlock;
1026 GEM_BUG_ON(!node.allocated);
1027 }
1028
1029 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1030 if (ret)
1031 goto out_unpin;
1032
1033 mutex_unlock(&i915->drm.struct_mutex);
1034
1035 user_data = u64_to_user_ptr(args->data_ptr);
1036 remain = args->size;
1037 offset = args->offset;
1038
1039 while (remain > 0) {
1040 /* Operation in this page
1041 *
1042 * page_base = page offset within aperture
1043 * page_offset = offset within page
1044 * page_length = bytes to copy for this page
1045 */
1046 u32 page_base = node.start;
1047 unsigned page_offset = offset_in_page(offset);
1048 unsigned page_length = PAGE_SIZE - page_offset;
1049 page_length = remain < page_length ? remain : page_length;
1050 if (node.allocated) {
1051 wmb();
1052 ggtt->base.insert_page(&ggtt->base,
1053 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1054 node.start, I915_CACHE_NONE, 0);
1055 wmb();
1056 } else {
1057 page_base += offset & PAGE_MASK;
1058 }
1059
1060 if (gtt_user_read(&ggtt->mappable, page_base, page_offset,
1061 user_data, page_length)) {
1062 ret = -EFAULT;
1063 break;
1064 }
1065
1066 remain -= page_length;
1067 user_data += page_length;
1068 offset += page_length;
1069 }
1070
1071 mutex_lock(&i915->drm.struct_mutex);
1072out_unpin:
1073 if (node.allocated) {
1074 wmb();
1075 ggtt->base.clear_range(&ggtt->base,
1076 node.start, node.size);
1077 remove_mappable_node(&node);
1078 } else {
1079 i915_vma_unpin(vma);
1080 }
1081out_unlock:
1082 intel_runtime_pm_put(i915);
1083 mutex_unlock(&i915->drm.struct_mutex);
1084
1085 return ret;
1086}
1087
1088/**
1089 * Reads data from the object referenced by handle.
1090 * @dev: drm device pointer
1091 * @data: ioctl data blob
1092 * @file: drm file pointer
1093 *
1094 * On error, the contents of *data are undefined.
1095 */
1096int
1097i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1098 struct drm_file *file)
1099{
1100 struct drm_i915_gem_pread *args = data;
1101 struct drm_i915_gem_object *obj;
1102 int ret;
1103
1104 if (args->size == 0)
1105 return 0;
1106
1107 if (!access_ok(VERIFY_WRITE,
1108 u64_to_user_ptr(args->data_ptr),
1109 args->size))
1110 return -EFAULT;
1111
1112 obj = i915_gem_object_lookup(file, args->handle);
1113 if (!obj)
1114 return -ENOENT;
1115
1116 /* Bounds check source. */
1117 if (args->offset > obj->base.size ||
1118 args->size > obj->base.size - args->offset) {
1119 ret = -EINVAL;
1120 goto out;
1121 }
1122
1123 trace_i915_gem_object_pread(obj, args->offset, args->size);
1124
1125 ret = i915_gem_object_wait(obj,
1126 I915_WAIT_INTERRUPTIBLE,
1127 MAX_SCHEDULE_TIMEOUT,
1128 to_rps_client(file));
1129 if (ret)
1130 goto out;
1131
1132 ret = i915_gem_object_pin_pages(obj);
1133 if (ret)
1134 goto out;
1135
1136 ret = i915_gem_shmem_pread(obj, args);
1137 if (ret == -EFAULT || ret == -ENODEV)
1138 ret = i915_gem_gtt_pread(obj, args);
1139
1140 i915_gem_object_unpin_pages(obj);
1141out:
1142 i915_gem_object_put(obj);
1143 return ret;
1144}
1145
1146/* This is the fast write path which cannot handle
1147 * page faults in the source data
1148 */
1149
1150static inline bool
1151ggtt_write(struct io_mapping *mapping,
1152 loff_t base, int offset,
1153 char __user *user_data, int length)
1154{
1155 void *vaddr;
1156 unsigned long unwritten;
1157
1158 /* We can use the cpu mem copy function because this is X86. */
1159 vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base);
1160 unwritten = __copy_from_user_inatomic_nocache(vaddr + offset,
1161 user_data, length);
1162 io_mapping_unmap_atomic(vaddr);
1163 if (unwritten) {
1164 vaddr = (void __force *)
1165 io_mapping_map_wc(mapping, base, PAGE_SIZE);
1166 unwritten = copy_from_user(vaddr + offset, user_data, length);
1167 io_mapping_unmap(vaddr);
1168 }
1169
1170 return unwritten;
1171}
1172
1173/**
1174 * This is the fast pwrite path, where we copy the data directly from the
1175 * user into the GTT, uncached.
1176 * @obj: i915 GEM object
1177 * @args: pwrite arguments structure
1178 */
1179static int
1180i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
1181 const struct drm_i915_gem_pwrite *args)
1182{
1183 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1184 struct i915_ggtt *ggtt = &i915->ggtt;
1185 struct drm_mm_node node;
1186 struct i915_vma *vma;
1187 u64 remain, offset;
1188 void __user *user_data;
1189 int ret;
1190
1191 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1192 if (ret)
1193 return ret;
1194
1195 intel_runtime_pm_get(i915);
1196 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
1197 PIN_MAPPABLE | PIN_NONBLOCK);
1198 if (!IS_ERR(vma)) {
1199 node.start = i915_ggtt_offset(vma);
1200 node.allocated = false;
1201 ret = i915_vma_put_fence(vma);
1202 if (ret) {
1203 i915_vma_unpin(vma);
1204 vma = ERR_PTR(ret);
1205 }
1206 }
1207 if (IS_ERR(vma)) {
1208 ret = insert_mappable_node(ggtt, &node, PAGE_SIZE);
1209 if (ret)
1210 goto out_unlock;
1211 GEM_BUG_ON(!node.allocated);
1212 }
1213
1214 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1215 if (ret)
1216 goto out_unpin;
1217
1218 mutex_unlock(&i915->drm.struct_mutex);
1219
1220 intel_fb_obj_invalidate(obj, ORIGIN_CPU);
1221
1222 user_data = u64_to_user_ptr(args->data_ptr);
1223 offset = args->offset;
1224 remain = args->size;
1225 while (remain) {
1226 /* Operation in this page
1227 *
1228 * page_base = page offset within aperture
1229 * page_offset = offset within page
1230 * page_length = bytes to copy for this page
1231 */
1232 u32 page_base = node.start;
1233 unsigned int page_offset = offset_in_page(offset);
1234 unsigned int page_length = PAGE_SIZE - page_offset;
1235 page_length = remain < page_length ? remain : page_length;
1236 if (node.allocated) {
1237 wmb(); /* flush the write before we modify the GGTT */
1238 ggtt->base.insert_page(&ggtt->base,
1239 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
1240 node.start, I915_CACHE_NONE, 0);
1241 wmb(); /* flush modifications to the GGTT (insert_page) */
1242 } else {
1243 page_base += offset & PAGE_MASK;
1244 }
1245 /* If we get a fault while copying data, then (presumably) our
1246 * source page isn't available. Return the error and we'll
1247 * retry in the slow path.
1248 * If the object is non-shmem backed, we retry again with the
1249 * path that handles page fault.
1250 */
1251 if (ggtt_write(&ggtt->mappable, page_base, page_offset,
1252 user_data, page_length)) {
1253 ret = -EFAULT;
1254 break;
1255 }
1256
1257 remain -= page_length;
1258 user_data += page_length;
1259 offset += page_length;
1260 }
1261 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1262
1263 mutex_lock(&i915->drm.struct_mutex);
1264out_unpin:
1265 if (node.allocated) {
1266 wmb();
1267 ggtt->base.clear_range(&ggtt->base,
1268 node.start, node.size);
1269 remove_mappable_node(&node);
1270 } else {
1271 i915_vma_unpin(vma);
1272 }
1273out_unlock:
1274 intel_runtime_pm_put(i915);
1275 mutex_unlock(&i915->drm.struct_mutex);
1276 return ret;
1277}
1278
1279static int
1280shmem_pwrite_slow(struct page *page, int offset, int length,
1281 char __user *user_data,
1282 bool page_do_bit17_swizzling,
1283 bool needs_clflush_before,
1284 bool needs_clflush_after)
1285{
1286 char *vaddr;
1287 int ret;
1288
1289 vaddr = kmap(page);
1290 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
1291 shmem_clflush_swizzled_range(vaddr + offset, length,
1292 page_do_bit17_swizzling);
1293 if (page_do_bit17_swizzling)
1294 ret = __copy_from_user_swizzled(vaddr, offset, user_data,
1295 length);
1296 else
1297 ret = __copy_from_user(vaddr + offset, user_data, length);
1298 if (needs_clflush_after)
1299 shmem_clflush_swizzled_range(vaddr + offset, length,
1300 page_do_bit17_swizzling);
1301 kunmap(page);
1302
1303 return ret ? -EFAULT : 0;
1304}
1305
1306/* Per-page copy function for the shmem pwrite fastpath.
1307 * Flushes invalid cachelines before writing to the target if
1308 * needs_clflush_before is set and flushes out any written cachelines after
1309 * writing if needs_clflush is set.
1310 */
1311static int
1312shmem_pwrite(struct page *page, int offset, int len, char __user *user_data,
1313 bool page_do_bit17_swizzling,
1314 bool needs_clflush_before,
1315 bool needs_clflush_after)
1316{
1317 int ret;
1318
1319 ret = -ENODEV;
1320 if (!page_do_bit17_swizzling) {
1321 char *vaddr = kmap_atomic(page);
1322
1323 if (needs_clflush_before)
1324 drm_clflush_virt_range(vaddr + offset, len);
1325 ret = __copy_from_user_inatomic(vaddr + offset, user_data, len);
1326 if (needs_clflush_after)
1327 drm_clflush_virt_range(vaddr + offset, len);
1328
1329 kunmap_atomic(vaddr);
1330 }
1331 if (ret == 0)
1332 return ret;
1333
1334 return shmem_pwrite_slow(page, offset, len, user_data,
1335 page_do_bit17_swizzling,
1336 needs_clflush_before,
1337 needs_clflush_after);
1338}
1339
1340static int
1341i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
1342 const struct drm_i915_gem_pwrite *args)
1343{
1344 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1345 void __user *user_data;
1346 u64 remain;
1347 unsigned int obj_do_bit17_swizzling;
1348 unsigned int partial_cacheline_write;
1349 unsigned int needs_clflush;
1350 unsigned int offset, idx;
1351 int ret;
1352
1353 ret = mutex_lock_interruptible(&i915->drm.struct_mutex);
1354 if (ret)
1355 return ret;
1356
1357 ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush);
1358 mutex_unlock(&i915->drm.struct_mutex);
1359 if (ret)
1360 return ret;
1361
1362 obj_do_bit17_swizzling = 0;
1363 if (i915_gem_object_needs_bit17_swizzle(obj))
1364 obj_do_bit17_swizzling = BIT(17);
1365
1366 /* If we don't overwrite a cacheline completely we need to be
1367 * careful to have up-to-date data by first clflushing. Don't
1368 * overcomplicate things and flush the entire patch.
1369 */
1370 partial_cacheline_write = 0;
1371 if (needs_clflush & CLFLUSH_BEFORE)
1372 partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1;
1373
1374 user_data = u64_to_user_ptr(args->data_ptr);
1375 remain = args->size;
1376 offset = offset_in_page(args->offset);
1377 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
1378 struct page *page = i915_gem_object_get_page(obj, idx);
1379 int length;
1380
1381 length = remain;
1382 if (offset + length > PAGE_SIZE)
1383 length = PAGE_SIZE - offset;
1384
1385 ret = shmem_pwrite(page, offset, length, user_data,
1386 page_to_phys(page) & obj_do_bit17_swizzling,
1387 (offset | length) & partial_cacheline_write,
1388 needs_clflush & CLFLUSH_AFTER);
1389 if (ret)
1390 break;
1391
1392 remain -= length;
1393 user_data += length;
1394 offset = 0;
1395 }
1396
1397 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1398 i915_gem_obj_finish_shmem_access(obj);
1399 return ret;
1400}
1401
1402/**
1403 * Writes data to the object referenced by handle.
1404 * @dev: drm device
1405 * @data: ioctl data blob
1406 * @file: drm file
1407 *
1408 * On error, the contents of the buffer that were to be modified are undefined.
1409 */
1410int
1411i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1412 struct drm_file *file)
1413{
1414 struct drm_i915_gem_pwrite *args = data;
1415 struct drm_i915_gem_object *obj;
1416 int ret;
1417
1418 if (args->size == 0)
1419 return 0;
1420
1421 if (!access_ok(VERIFY_READ,
1422 u64_to_user_ptr(args->data_ptr),
1423 args->size))
1424 return -EFAULT;
1425
1426 obj = i915_gem_object_lookup(file, args->handle);
1427 if (!obj)
1428 return -ENOENT;
1429
1430 /* Bounds check destination. */
1431 if (args->offset > obj->base.size ||
1432 args->size > obj->base.size - args->offset) {
1433 ret = -EINVAL;
1434 goto err;
1435 }
1436
1437 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1438
1439 ret = i915_gem_object_wait(obj,
1440 I915_WAIT_INTERRUPTIBLE |
1441 I915_WAIT_ALL,
1442 MAX_SCHEDULE_TIMEOUT,
1443 to_rps_client(file));
1444 if (ret)
1445 goto err;
1446
1447 ret = i915_gem_object_pin_pages(obj);
1448 if (ret)
1449 goto err;
1450
1451 ret = -EFAULT;
1452 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1453 * it would end up going through the fenced access, and we'll get
1454 * different detiling behavior between reading and writing.
1455 * pread/pwrite currently are reading and writing from the CPU
1456 * perspective, requiring manual detiling by the client.
1457 */
1458 if (!i915_gem_object_has_struct_page(obj) ||
1459 cpu_write_needs_clflush(obj))
1460 /* Note that the gtt paths might fail with non-page-backed user
1461 * pointers (e.g. gtt mappings when moving data between
1462 * textures). Fallback to the shmem path in that case.
1463 */
1464 ret = i915_gem_gtt_pwrite_fast(obj, args);
1465
1466 if (ret == -EFAULT || ret == -ENOSPC) {
1467 if (obj->phys_handle)
1468 ret = i915_gem_phys_pwrite(obj, args, file);
1469 else
1470 ret = i915_gem_shmem_pwrite(obj, args);
1471 }
1472
1473 i915_gem_object_unpin_pages(obj);
1474err:
1475 i915_gem_object_put(obj);
1476 return ret;
1477}
1478
1479static inline enum fb_op_origin
1480write_origin(struct drm_i915_gem_object *obj, unsigned domain)
1481{
1482 return (domain == I915_GEM_DOMAIN_GTT ?
1483 obj->frontbuffer_ggtt_origin : ORIGIN_CPU);
1484}
1485
1486static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj)
1487{
1488 struct drm_i915_private *i915;
1489 struct list_head *list;
1490 struct i915_vma *vma;
1491
1492 list_for_each_entry(vma, &obj->vma_list, obj_link) {
1493 if (!i915_vma_is_ggtt(vma))
1494 continue;
1495
1496 if (i915_vma_is_active(vma))
1497 continue;
1498
1499 if (!drm_mm_node_allocated(&vma->node))
1500 continue;
1501
1502 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
1503 }
1504
1505 i915 = to_i915(obj->base.dev);
1506 list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list;
1507 list_move_tail(&obj->global_link, list);
1508}
1509
1510/**
1511 * Called when user space prepares to use an object with the CPU, either
1512 * through the mmap ioctl's mapping or a GTT mapping.
1513 * @dev: drm device
1514 * @data: ioctl data blob
1515 * @file: drm file
1516 */
1517int
1518i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1519 struct drm_file *file)
1520{
1521 struct drm_i915_gem_set_domain *args = data;
1522 struct drm_i915_gem_object *obj;
1523 uint32_t read_domains = args->read_domains;
1524 uint32_t write_domain = args->write_domain;
1525 int err;
1526
1527 /* Only handle setting domains to types used by the CPU. */
1528 if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS)
1529 return -EINVAL;
1530
1531 /* Having something in the write domain implies it's in the read
1532 * domain, and only that read domain. Enforce that in the request.
1533 */
1534 if (write_domain != 0 && read_domains != write_domain)
1535 return -EINVAL;
1536
1537 obj = i915_gem_object_lookup(file, args->handle);
1538 if (!obj)
1539 return -ENOENT;
1540
1541 /* Try to flush the object off the GPU without holding the lock.
1542 * We will repeat the flush holding the lock in the normal manner
1543 * to catch cases where we are gazumped.
1544 */
1545 err = i915_gem_object_wait(obj,
1546 I915_WAIT_INTERRUPTIBLE |
1547 (write_domain ? I915_WAIT_ALL : 0),
1548 MAX_SCHEDULE_TIMEOUT,
1549 to_rps_client(file));
1550 if (err)
1551 goto out;
1552
1553 /* Flush and acquire obj->pages so that we are coherent through
1554 * direct access in memory with previous cached writes through
1555 * shmemfs and that our cache domain tracking remains valid.
1556 * For example, if the obj->filp was moved to swap without us
1557 * being notified and releasing the pages, we would mistakenly
1558 * continue to assume that the obj remained out of the CPU cached
1559 * domain.
1560 */
1561 err = i915_gem_object_pin_pages(obj);
1562 if (err)
1563 goto out;
1564
1565 err = i915_mutex_lock_interruptible(dev);
1566 if (err)
1567 goto out_unpin;
1568
1569 if (read_domains & I915_GEM_DOMAIN_GTT)
1570 err = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1571 else
1572 err = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1573
1574 /* And bump the LRU for this access */
1575 i915_gem_object_bump_inactive_ggtt(obj);
1576
1577 mutex_unlock(&dev->struct_mutex);
1578
1579 if (write_domain != 0)
1580 intel_fb_obj_invalidate(obj, write_origin(obj, write_domain));
1581
1582out_unpin:
1583 i915_gem_object_unpin_pages(obj);
1584out:
1585 i915_gem_object_put(obj);
1586 return err;
1587}
1588
1589/**
1590 * Called when user space has done writes to this buffer
1591 * @dev: drm device
1592 * @data: ioctl data blob
1593 * @file: drm file
1594 */
1595int
1596i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1597 struct drm_file *file)
1598{
1599 struct drm_i915_gem_sw_finish *args = data;
1600 struct drm_i915_gem_object *obj;
1601 int err = 0;
1602
1603 obj = i915_gem_object_lookup(file, args->handle);
1604 if (!obj)
1605 return -ENOENT;
1606
1607 /* Pinned buffers may be scanout, so flush the cache */
1608 if (READ_ONCE(obj->pin_display)) {
1609 err = i915_mutex_lock_interruptible(dev);
1610 if (!err) {
1611 i915_gem_object_flush_cpu_write_domain(obj);
1612 mutex_unlock(&dev->struct_mutex);
1613 }
1614 }
1615
1616 i915_gem_object_put(obj);
1617 return err;
1618}
1619
1620/**
1621 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1622 * it is mapped to.
1623 * @dev: drm device
1624 * @data: ioctl data blob
1625 * @file: drm file
1626 *
1627 * While the mapping holds a reference on the contents of the object, it doesn't
1628 * imply a ref on the object itself.
1629 *
1630 * IMPORTANT:
1631 *
1632 * DRM driver writers who look a this function as an example for how to do GEM
1633 * mmap support, please don't implement mmap support like here. The modern way
1634 * to implement DRM mmap support is with an mmap offset ioctl (like
1635 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1636 * That way debug tooling like valgrind will understand what's going on, hiding
1637 * the mmap call in a driver private ioctl will break that. The i915 driver only
1638 * does cpu mmaps this way because we didn't know better.
1639 */
1640int
1641i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1642 struct drm_file *file)
1643{
1644 struct drm_i915_gem_mmap *args = data;
1645 struct drm_i915_gem_object *obj;
1646 unsigned long addr;
1647
1648 if (args->flags & ~(I915_MMAP_WC))
1649 return -EINVAL;
1650
1651 if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT))
1652 return -ENODEV;
1653
1654 obj = i915_gem_object_lookup(file, args->handle);
1655 if (!obj)
1656 return -ENOENT;
1657
1658 /* prime objects have no backing filp to GEM mmap
1659 * pages from.
1660 */
1661 if (!obj->base.filp) {
1662 i915_gem_object_put(obj);
1663 return -EINVAL;
1664 }
1665
1666 addr = vm_mmap(obj->base.filp, 0, args->size,
1667 PROT_READ | PROT_WRITE, MAP_SHARED,
1668 args->offset);
1669 if (args->flags & I915_MMAP_WC) {
1670 struct mm_struct *mm = current->mm;
1671 struct vm_area_struct *vma;
1672
1673 if (down_write_killable(&mm->mmap_sem)) {
1674 i915_gem_object_put(obj);
1675 return -EINTR;
1676 }
1677 vma = find_vma(mm, addr);
1678 if (vma)
1679 vma->vm_page_prot =
1680 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1681 else
1682 addr = -ENOMEM;
1683 up_write(&mm->mmap_sem);
1684
1685 /* This may race, but that's ok, it only gets set */
1686 WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU);
1687 }
1688 i915_gem_object_put(obj);
1689 if (IS_ERR((void *)addr))
1690 return addr;
1691
1692 args->addr_ptr = (uint64_t) addr;
1693
1694 return 0;
1695}
1696
1697static unsigned int tile_row_pages(struct drm_i915_gem_object *obj)
1698{
1699 u64 size;
1700
1701 size = i915_gem_object_get_stride(obj);
1702 size *= i915_gem_object_get_tiling(obj) == I915_TILING_Y ? 32 : 8;
1703
1704 return size >> PAGE_SHIFT;
1705}
1706
1707/**
1708 * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps
1709 *
1710 * A history of the GTT mmap interface:
1711 *
1712 * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to
1713 * aligned and suitable for fencing, and still fit into the available
1714 * mappable space left by the pinned display objects. A classic problem
1715 * we called the page-fault-of-doom where we would ping-pong between
1716 * two objects that could not fit inside the GTT and so the memcpy
1717 * would page one object in at the expense of the other between every
1718 * single byte.
1719 *
1720 * 1 - Objects can be any size, and have any compatible fencing (X Y, or none
1721 * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the
1722 * object is too large for the available space (or simply too large
1723 * for the mappable aperture!), a view is created instead and faulted
1724 * into userspace. (This view is aligned and sized appropriately for
1725 * fenced access.)
1726 *
1727 * Restrictions:
1728 *
1729 * * snoopable objects cannot be accessed via the GTT. It can cause machine
1730 * hangs on some architectures, corruption on others. An attempt to service
1731 * a GTT page fault from a snoopable object will generate a SIGBUS.
1732 *
1733 * * the object must be able to fit into RAM (physical memory, though no
1734 * limited to the mappable aperture).
1735 *
1736 *
1737 * Caveats:
1738 *
1739 * * a new GTT page fault will synchronize rendering from the GPU and flush
1740 * all data to system memory. Subsequent access will not be synchronized.
1741 *
1742 * * all mappings are revoked on runtime device suspend.
1743 *
1744 * * there are only 8, 16 or 32 fence registers to share between all users
1745 * (older machines require fence register for display and blitter access
1746 * as well). Contention of the fence registers will cause the previous users
1747 * to be unmapped and any new access will generate new page faults.
1748 *
1749 * * running out of memory while servicing a fault may generate a SIGBUS,
1750 * rather than the expected SIGSEGV.
1751 */
1752int i915_gem_mmap_gtt_version(void)
1753{
1754 return 1;
1755}
1756
1757/**
1758 * i915_gem_fault - fault a page into the GTT
1759 * @area: CPU VMA in question
1760 * @vmf: fault info
1761 *
1762 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1763 * from userspace. The fault handler takes care of binding the object to
1764 * the GTT (if needed), allocating and programming a fence register (again,
1765 * only if needed based on whether the old reg is still valid or the object
1766 * is tiled) and inserting a new PTE into the faulting process.
1767 *
1768 * Note that the faulting process may involve evicting existing objects
1769 * from the GTT and/or fence registers to make room. So performance may
1770 * suffer if the GTT working set is large or there are few fence registers
1771 * left.
1772 *
1773 * The current feature set supported by i915_gem_fault() and thus GTT mmaps
1774 * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version).
1775 */
1776int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf)
1777{
1778#define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */
1779 struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data);
1780 struct drm_device *dev = obj->base.dev;
1781 struct drm_i915_private *dev_priv = to_i915(dev);
1782 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1783 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1784 struct i915_vma *vma;
1785 pgoff_t page_offset;
1786 unsigned int flags;
1787 int ret;
1788
1789 /* We don't use vmf->pgoff since that has the fake offset */
1790 page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
1791
1792 trace_i915_gem_object_fault(obj, page_offset, true, write);
1793
1794 /* Try to flush the object off the GPU first without holding the lock.
1795 * Upon acquiring the lock, we will perform our sanity checks and then
1796 * repeat the flush holding the lock in the normal manner to catch cases
1797 * where we are gazumped.
1798 */
1799 ret = i915_gem_object_wait(obj,
1800 I915_WAIT_INTERRUPTIBLE,
1801 MAX_SCHEDULE_TIMEOUT,
1802 NULL);
1803 if (ret)
1804 goto err;
1805
1806 ret = i915_gem_object_pin_pages(obj);
1807 if (ret)
1808 goto err;
1809
1810 intel_runtime_pm_get(dev_priv);
1811
1812 ret = i915_mutex_lock_interruptible(dev);
1813 if (ret)
1814 goto err_rpm;
1815
1816 /* Access to snoopable pages through the GTT is incoherent. */
1817 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) {
1818 ret = -EFAULT;
1819 goto err_unlock;
1820 }
1821
1822 /* If the object is smaller than a couple of partial vma, it is
1823 * not worth only creating a single partial vma - we may as well
1824 * clear enough space for the full object.
1825 */
1826 flags = PIN_MAPPABLE;
1827 if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT)
1828 flags |= PIN_NONBLOCK | PIN_NONFAULT;
1829
1830 /* Now pin it into the GTT as needed */
1831 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags);
1832 if (IS_ERR(vma)) {
1833 struct i915_ggtt_view view;
1834 unsigned int chunk_size;
1835
1836 /* Use a partial view if it is bigger than available space */
1837 chunk_size = MIN_CHUNK_PAGES;
1838 if (i915_gem_object_is_tiled(obj))
1839 chunk_size = roundup(chunk_size, tile_row_pages(obj));
1840
1841 memset(&view, 0, sizeof(view));
1842 view.type = I915_GGTT_VIEW_PARTIAL;
1843 view.params.partial.offset = rounddown(page_offset, chunk_size);
1844 view.params.partial.size =
1845 min_t(unsigned int, chunk_size,
1846 vma_pages(area) - view.params.partial.offset);
1847
1848 /* If the partial covers the entire object, just create a
1849 * normal VMA.
1850 */
1851 if (chunk_size >= obj->base.size >> PAGE_SHIFT)
1852 view.type = I915_GGTT_VIEW_NORMAL;
1853
1854 /* Userspace is now writing through an untracked VMA, abandon
1855 * all hope that the hardware is able to track future writes.
1856 */
1857 obj->frontbuffer_ggtt_origin = ORIGIN_CPU;
1858
1859 vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
1860 }
1861 if (IS_ERR(vma)) {
1862 ret = PTR_ERR(vma);
1863 goto err_unlock;
1864 }
1865
1866 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1867 if (ret)
1868 goto err_unpin;
1869
1870 ret = i915_vma_get_fence(vma);
1871 if (ret)
1872 goto err_unpin;
1873
1874 /* Mark as being mmapped into userspace for later revocation */
1875 assert_rpm_wakelock_held(dev_priv);
1876 if (list_empty(&obj->userfault_link))
1877 list_add(&obj->userfault_link, &dev_priv->mm.userfault_list);
1878
1879 /* Finally, remap it using the new GTT offset */
1880 ret = remap_io_mapping(area,
1881 area->vm_start + (vma->ggtt_view.params.partial.offset << PAGE_SHIFT),
1882 (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT,
1883 min_t(u64, vma->size, area->vm_end - area->vm_start),
1884 &ggtt->mappable);
1885
1886err_unpin:
1887 __i915_vma_unpin(vma);
1888err_unlock:
1889 mutex_unlock(&dev->struct_mutex);
1890err_rpm:
1891 intel_runtime_pm_put(dev_priv);
1892 i915_gem_object_unpin_pages(obj);
1893err:
1894 switch (ret) {
1895 case -EIO:
1896 /*
1897 * We eat errors when the gpu is terminally wedged to avoid
1898 * userspace unduly crashing (gl has no provisions for mmaps to
1899 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1900 * and so needs to be reported.
1901 */
1902 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1903 ret = VM_FAULT_SIGBUS;
1904 break;
1905 }
1906 case -EAGAIN:
1907 /*
1908 * EAGAIN means the gpu is hung and we'll wait for the error
1909 * handler to reset everything when re-faulting in
1910 * i915_mutex_lock_interruptible.
1911 */
1912 case 0:
1913 case -ERESTARTSYS:
1914 case -EINTR:
1915 case -EBUSY:
1916 /*
1917 * EBUSY is ok: this just means that another thread
1918 * already did the job.
1919 */
1920 ret = VM_FAULT_NOPAGE;
1921 break;
1922 case -ENOMEM:
1923 ret = VM_FAULT_OOM;
1924 break;
1925 case -ENOSPC:
1926 case -EFAULT:
1927 ret = VM_FAULT_SIGBUS;
1928 break;
1929 default:
1930 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1931 ret = VM_FAULT_SIGBUS;
1932 break;
1933 }
1934 return ret;
1935}
1936
1937/**
1938 * i915_gem_release_mmap - remove physical page mappings
1939 * @obj: obj in question
1940 *
1941 * Preserve the reservation of the mmapping with the DRM core code, but
1942 * relinquish ownership of the pages back to the system.
1943 *
1944 * It is vital that we remove the page mapping if we have mapped a tiled
1945 * object through the GTT and then lose the fence register due to
1946 * resource pressure. Similarly if the object has been moved out of the
1947 * aperture, than pages mapped into userspace must be revoked. Removing the
1948 * mapping will then trigger a page fault on the next user access, allowing
1949 * fixup by i915_gem_fault().
1950 */
1951void
1952i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1953{
1954 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1955
1956 /* Serialisation between user GTT access and our code depends upon
1957 * revoking the CPU's PTE whilst the mutex is held. The next user
1958 * pagefault then has to wait until we release the mutex.
1959 *
1960 * Note that RPM complicates somewhat by adding an additional
1961 * requirement that operations to the GGTT be made holding the RPM
1962 * wakeref.
1963 */
1964 lockdep_assert_held(&i915->drm.struct_mutex);
1965 intel_runtime_pm_get(i915);
1966
1967 if (list_empty(&obj->userfault_link))
1968 goto out;
1969
1970 list_del_init(&obj->userfault_link);
1971 drm_vma_node_unmap(&obj->base.vma_node,
1972 obj->base.dev->anon_inode->i_mapping);
1973
1974 /* Ensure that the CPU's PTE are revoked and there are not outstanding
1975 * memory transactions from userspace before we return. The TLB
1976 * flushing implied above by changing the PTE above *should* be
1977 * sufficient, an extra barrier here just provides us with a bit
1978 * of paranoid documentation about our requirement to serialise
1979 * memory writes before touching registers / GSM.
1980 */
1981 wmb();
1982
1983out:
1984 intel_runtime_pm_put(i915);
1985}
1986
1987void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
1988{
1989 struct drm_i915_gem_object *obj, *on;
1990 int i;
1991
1992 /*
1993 * Only called during RPM suspend. All users of the userfault_list
1994 * must be holding an RPM wakeref to ensure that this can not
1995 * run concurrently with themselves (and use the struct_mutex for
1996 * protection between themselves).
1997 */
1998
1999 list_for_each_entry_safe(obj, on,
2000 &dev_priv->mm.userfault_list, userfault_link) {
2001 list_del_init(&obj->userfault_link);
2002 drm_vma_node_unmap(&obj->base.vma_node,
2003 obj->base.dev->anon_inode->i_mapping);
2004 }
2005
2006 /* The fence will be lost when the device powers down. If any were
2007 * in use by hardware (i.e. they are pinned), we should not be powering
2008 * down! All other fences will be reacquired by the user upon waking.
2009 */
2010 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2011 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2012
2013 /* Ideally we want to assert that the fence register is not
2014 * live at this point (i.e. that no piece of code will be
2015 * trying to write through fence + GTT, as that both violates
2016 * our tracking of activity and associated locking/barriers,
2017 * but also is illegal given that the hw is powered down).
2018 *
2019 * Previously we used reg->pin_count as a "liveness" indicator.
2020 * That is not sufficient, and we need a more fine-grained
2021 * tool if we want to have a sanity check here.
2022 */
2023
2024 if (!reg->vma)
2025 continue;
2026
2027 GEM_BUG_ON(!list_empty(®->vma->obj->userfault_link));
2028 reg->dirty = true;
2029 }
2030}
2031
2032/**
2033 * i915_gem_get_ggtt_size - return required global GTT size for an object
2034 * @dev_priv: i915 device
2035 * @size: object size
2036 * @tiling_mode: tiling mode
2037 *
2038 * Return the required global GTT size for an object, taking into account
2039 * potential fence register mapping.
2040 */
2041u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv,
2042 u64 size, int tiling_mode)
2043{
2044 u64 ggtt_size;
2045
2046 GEM_BUG_ON(size == 0);
2047
2048 if (INTEL_GEN(dev_priv) >= 4 ||
2049 tiling_mode == I915_TILING_NONE)
2050 return size;
2051
2052 /* Previous chips need a power-of-two fence region when tiling */
2053 if (IS_GEN3(dev_priv))
2054 ggtt_size = 1024*1024;
2055 else
2056 ggtt_size = 512*1024;
2057
2058 while (ggtt_size < size)
2059 ggtt_size <<= 1;
2060
2061 return ggtt_size;
2062}
2063
2064/**
2065 * i915_gem_get_ggtt_alignment - return required global GTT alignment
2066 * @dev_priv: i915 device
2067 * @size: object size
2068 * @tiling_mode: tiling mode
2069 * @fenced: is fenced alignment required or not
2070 *
2071 * Return the required global GTT alignment for an object, taking into account
2072 * potential fence register mapping.
2073 */
2074u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
2075 int tiling_mode, bool fenced)
2076{
2077 GEM_BUG_ON(size == 0);
2078
2079 /*
2080 * Minimum alignment is 4k (GTT page size), but might be greater
2081 * if a fence register is needed for the object.
2082 */
2083 if (INTEL_GEN(dev_priv) >= 4 || (!fenced && IS_G33(dev_priv)) ||
2084 tiling_mode == I915_TILING_NONE)
2085 return 4096;
2086
2087 /*
2088 * Previous chips need to be aligned to the size of the smallest
2089 * fence register that can contain the object.
2090 */
2091 return i915_gem_get_ggtt_size(dev_priv, size, tiling_mode);
2092}
2093
2094static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2095{
2096 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2097 int err;
2098
2099 err = drm_gem_create_mmap_offset(&obj->base);
2100 if (!err)
2101 return 0;
2102
2103 /* We can idle the GPU locklessly to flush stale objects, but in order
2104 * to claim that space for ourselves, we need to take the big
2105 * struct_mutex to free the requests+objects and allocate our slot.
2106 */
2107 err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE);
2108 if (err)
2109 return err;
2110
2111 err = i915_mutex_lock_interruptible(&dev_priv->drm);
2112 if (!err) {
2113 i915_gem_retire_requests(dev_priv);
2114 err = drm_gem_create_mmap_offset(&obj->base);
2115 mutex_unlock(&dev_priv->drm.struct_mutex);
2116 }
2117
2118 return err;
2119}
2120
2121static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2122{
2123 drm_gem_free_mmap_offset(&obj->base);
2124}
2125
2126int
2127i915_gem_mmap_gtt(struct drm_file *file,
2128 struct drm_device *dev,
2129 uint32_t handle,
2130 uint64_t *offset)
2131{
2132 struct drm_i915_gem_object *obj;
2133 int ret;
2134
2135 obj = i915_gem_object_lookup(file, handle);
2136 if (!obj)
2137 return -ENOENT;
2138
2139 ret = i915_gem_object_create_mmap_offset(obj);
2140 if (ret == 0)
2141 *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2142
2143 i915_gem_object_put(obj);
2144 return ret;
2145}
2146
2147/**
2148 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2149 * @dev: DRM device
2150 * @data: GTT mapping ioctl data
2151 * @file: GEM object info
2152 *
2153 * Simply returns the fake offset to userspace so it can mmap it.
2154 * The mmap call will end up in drm_gem_mmap(), which will set things
2155 * up so we can get faults in the handler above.
2156 *
2157 * The fault handler will take care of binding the object into the GTT
2158 * (since it may have been evicted to make room for something), allocating
2159 * a fence register, and mapping the appropriate aperture address into
2160 * userspace.
2161 */
2162int
2163i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2164 struct drm_file *file)
2165{
2166 struct drm_i915_gem_mmap_gtt *args = data;
2167
2168 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2169}
2170
2171/* Immediately discard the backing storage */
2172static void
2173i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2174{
2175 i915_gem_object_free_mmap_offset(obj);
2176
2177 if (obj->base.filp == NULL)
2178 return;
2179
2180 /* Our goal here is to return as much of the memory as
2181 * is possible back to the system as we are called from OOM.
2182 * To do this we must instruct the shmfs to drop all of its
2183 * backing pages, *now*.
2184 */
2185 shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2186 obj->mm.madv = __I915_MADV_PURGED;
2187 obj->mm.pages = ERR_PTR(-EFAULT);
2188}
2189
2190/* Try to discard unwanted pages */
2191void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2192{
2193 struct address_space *mapping;
2194
2195 lockdep_assert_held(&obj->mm.lock);
2196 GEM_BUG_ON(obj->mm.pages);
2197
2198 switch (obj->mm.madv) {
2199 case I915_MADV_DONTNEED:
2200 i915_gem_object_truncate(obj);
2201 case __I915_MADV_PURGED:
2202 return;
2203 }
2204
2205 if (obj->base.filp == NULL)
2206 return;
2207
2208 mapping = obj->base.filp->f_mapping,
2209 invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2210}
2211
2212static void
2213i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj,
2214 struct sg_table *pages)
2215{
2216 struct sgt_iter sgt_iter;
2217 struct page *page;
2218
2219 __i915_gem_object_release_shmem(obj, pages, true);
2220
2221 i915_gem_gtt_finish_pages(obj, pages);
2222
2223 if (i915_gem_object_needs_bit17_swizzle(obj))
2224 i915_gem_object_save_bit_17_swizzle(obj, pages);
2225
2226 for_each_sgt_page(page, sgt_iter, pages) {
2227 if (obj->mm.dirty)
2228 set_page_dirty(page);
2229
2230 if (obj->mm.madv == I915_MADV_WILLNEED)
2231 mark_page_accessed(page);
2232
2233 put_page(page);
2234 }
2235 obj->mm.dirty = false;
2236
2237 sg_free_table(pages);
2238 kfree(pages);
2239}
2240
2241static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj)
2242{
2243 struct radix_tree_iter iter;
2244 void **slot;
2245
2246 radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0)
2247 radix_tree_delete(&obj->mm.get_page.radix, iter.index);
2248}
2249
2250void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
2251 enum i915_mm_subclass subclass)
2252{
2253 struct sg_table *pages;
2254
2255 if (i915_gem_object_has_pinned_pages(obj))
2256 return;
2257
2258 GEM_BUG_ON(obj->bind_count);
2259 if (!READ_ONCE(obj->mm.pages))
2260 return;
2261
2262 /* May be called by shrinker from within get_pages() (on another bo) */
2263 mutex_lock_nested(&obj->mm.lock, subclass);
2264 if (unlikely(atomic_read(&obj->mm.pages_pin_count)))
2265 goto unlock;
2266
2267 /* ->put_pages might need to allocate memory for the bit17 swizzle
2268 * array, hence protect them from being reaped by removing them from gtt
2269 * lists early. */
2270 pages = fetch_and_zero(&obj->mm.pages);
2271 GEM_BUG_ON(!pages);
2272
2273 if (obj->mm.mapping) {
2274 void *ptr;
2275
2276 ptr = ptr_mask_bits(obj->mm.mapping);
2277 if (is_vmalloc_addr(ptr))
2278 vunmap(ptr);
2279 else
2280 kunmap(kmap_to_page(ptr));
2281
2282 obj->mm.mapping = NULL;
2283 }
2284
2285 __i915_gem_object_reset_page_iter(obj);
2286
2287 if (!IS_ERR(pages))
2288 obj->ops->put_pages(obj, pages);
2289
2290unlock:
2291 mutex_unlock(&obj->mm.lock);
2292}
2293
2294static void i915_sg_trim(struct sg_table *orig_st)
2295{
2296 struct sg_table new_st;
2297 struct scatterlist *sg, *new_sg;
2298 unsigned int i;
2299
2300 if (orig_st->nents == orig_st->orig_nents)
2301 return;
2302
2303 if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL | __GFP_NOWARN))
2304 return;
2305
2306 new_sg = new_st.sgl;
2307 for_each_sg(orig_st->sgl, sg, orig_st->nents, i) {
2308 sg_set_page(new_sg, sg_page(sg), sg->length, 0);
2309 /* called before being DMA mapped, no need to copy sg->dma_* */
2310 new_sg = sg_next(new_sg);
2311 }
2312
2313 sg_free_table(orig_st);
2314
2315 *orig_st = new_st;
2316}
2317
2318static struct sg_table *
2319i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2320{
2321 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2322 const unsigned long page_count = obj->base.size / PAGE_SIZE;
2323 unsigned long i;
2324 struct address_space *mapping;
2325 struct sg_table *st;
2326 struct scatterlist *sg;
2327 struct sgt_iter sgt_iter;
2328 struct page *page;
2329 unsigned long last_pfn = 0; /* suppress gcc warning */
2330 unsigned int max_segment;
2331 int ret;
2332 gfp_t gfp;
2333
2334 /* Assert that the object is not currently in any GPU domain. As it
2335 * wasn't in the GTT, there shouldn't be any way it could have been in
2336 * a GPU cache
2337 */
2338 GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2339 GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2340
2341 max_segment = swiotlb_max_segment();
2342 if (!max_segment)
2343 max_segment = rounddown(UINT_MAX, PAGE_SIZE);
2344
2345 st = kmalloc(sizeof(*st), GFP_KERNEL);
2346 if (st == NULL)
2347 return ERR_PTR(-ENOMEM);
2348
2349rebuild_st:
2350 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2351 kfree(st);
2352 return ERR_PTR(-ENOMEM);
2353 }
2354
2355 /* Get the list of pages out of our struct file. They'll be pinned
2356 * at this point until we release them.
2357 *
2358 * Fail silently without starting the shrinker
2359 */
2360 mapping = obj->base.filp->f_mapping;
2361 gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM));
2362 gfp |= __GFP_NORETRY | __GFP_NOWARN;
2363 sg = st->sgl;
2364 st->nents = 0;
2365 for (i = 0; i < page_count; i++) {
2366 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2367 if (IS_ERR(page)) {
2368 i915_gem_shrink(dev_priv,
2369 page_count,
2370 I915_SHRINK_BOUND |
2371 I915_SHRINK_UNBOUND |
2372 I915_SHRINK_PURGEABLE);
2373 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2374 }
2375 if (IS_ERR(page)) {
2376 /* We've tried hard to allocate the memory by reaping
2377 * our own buffer, now let the real VM do its job and
2378 * go down in flames if truly OOM.
2379 */
2380 page = shmem_read_mapping_page(mapping, i);
2381 if (IS_ERR(page)) {
2382 ret = PTR_ERR(page);
2383 goto err_sg;
2384 }
2385 }
2386 if (!i ||
2387 sg->length >= max_segment ||
2388 page_to_pfn(page) != last_pfn + 1) {
2389 if (i)
2390 sg = sg_next(sg);
2391 st->nents++;
2392 sg_set_page(sg, page, PAGE_SIZE, 0);
2393 } else {
2394 sg->length += PAGE_SIZE;
2395 }
2396 last_pfn = page_to_pfn(page);
2397
2398 /* Check that the i965g/gm workaround works. */
2399 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2400 }
2401 if (sg) /* loop terminated early; short sg table */
2402 sg_mark_end(sg);
2403
2404 /* Trim unused sg entries to avoid wasting memory. */
2405 i915_sg_trim(st);
2406
2407 ret = i915_gem_gtt_prepare_pages(obj, st);
2408 if (ret) {
2409 /* DMA remapping failed? One possible cause is that
2410 * it could not reserve enough large entries, asking
2411 * for PAGE_SIZE chunks instead may be helpful.
2412 */
2413 if (max_segment > PAGE_SIZE) {
2414 for_each_sgt_page(page, sgt_iter, st)
2415 put_page(page);
2416 sg_free_table(st);
2417
2418 max_segment = PAGE_SIZE;
2419 goto rebuild_st;
2420 } else {
2421 dev_warn(&dev_priv->drm.pdev->dev,
2422 "Failed to DMA remap %lu pages\n",
2423 page_count);
2424 goto err_pages;
2425 }
2426 }
2427
2428 if (i915_gem_object_needs_bit17_swizzle(obj))
2429 i915_gem_object_do_bit_17_swizzle(obj, st);
2430
2431 return st;
2432
2433err_sg:
2434 sg_mark_end(sg);
2435err_pages:
2436 for_each_sgt_page(page, sgt_iter, st)
2437 put_page(page);
2438 sg_free_table(st);
2439 kfree(st);
2440
2441 /* shmemfs first checks if there is enough memory to allocate the page
2442 * and reports ENOSPC should there be insufficient, along with the usual
2443 * ENOMEM for a genuine allocation failure.
2444 *
2445 * We use ENOSPC in our driver to mean that we have run out of aperture
2446 * space and so want to translate the error from shmemfs back to our
2447 * usual understanding of ENOMEM.
2448 */
2449 if (ret == -ENOSPC)
2450 ret = -ENOMEM;
2451
2452 return ERR_PTR(ret);
2453}
2454
2455void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2456 struct sg_table *pages)
2457{
2458 lockdep_assert_held(&obj->mm.lock);
2459
2460 obj->mm.get_page.sg_pos = pages->sgl;
2461 obj->mm.get_page.sg_idx = 0;
2462
2463 obj->mm.pages = pages;
2464
2465 if (i915_gem_object_is_tiled(obj) &&
2466 to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
2467 GEM_BUG_ON(obj->mm.quirked);
2468 __i915_gem_object_pin_pages(obj);
2469 obj->mm.quirked = true;
2470 }
2471}
2472
2473static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2474{
2475 struct sg_table *pages;
2476
2477 GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj));
2478
2479 if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) {
2480 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2481 return -EFAULT;
2482 }
2483
2484 pages = obj->ops->get_pages(obj);
2485 if (unlikely(IS_ERR(pages)))
2486 return PTR_ERR(pages);
2487
2488 __i915_gem_object_set_pages(obj, pages);
2489 return 0;
2490}
2491
2492/* Ensure that the associated pages are gathered from the backing storage
2493 * and pinned into our object. i915_gem_object_pin_pages() may be called
2494 * multiple times before they are released by a single call to
2495 * i915_gem_object_unpin_pages() - once the pages are no longer referenced
2496 * either as a result of memory pressure (reaping pages under the shrinker)
2497 * or as the object is itself released.
2498 */
2499int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2500{
2501 int err;
2502
2503 err = mutex_lock_interruptible(&obj->mm.lock);
2504 if (err)
2505 return err;
2506
2507 if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
2508 err = ____i915_gem_object_get_pages(obj);
2509 if (err)
2510 goto unlock;
2511
2512 smp_mb__before_atomic();
2513 }
2514 atomic_inc(&obj->mm.pages_pin_count);
2515
2516unlock:
2517 mutex_unlock(&obj->mm.lock);
2518 return err;
2519}
2520
2521/* The 'mapping' part of i915_gem_object_pin_map() below */
2522static void *i915_gem_object_map(const struct drm_i915_gem_object *obj,
2523 enum i915_map_type type)
2524{
2525 unsigned long n_pages = obj->base.size >> PAGE_SHIFT;
2526 struct sg_table *sgt = obj->mm.pages;
2527 struct sgt_iter sgt_iter;
2528 struct page *page;
2529 struct page *stack_pages[32];
2530 struct page **pages = stack_pages;
2531 unsigned long i = 0;
2532 pgprot_t pgprot;
2533 void *addr;
2534
2535 /* A single page can always be kmapped */
2536 if (n_pages == 1 && type == I915_MAP_WB)
2537 return kmap(sg_page(sgt->sgl));
2538
2539 if (n_pages > ARRAY_SIZE(stack_pages)) {
2540 /* Too big for stack -- allocate temporary array instead */
2541 pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY);
2542 if (!pages)
2543 return NULL;
2544 }
2545
2546 for_each_sgt_page(page, sgt_iter, sgt)
2547 pages[i++] = page;
2548
2549 /* Check that we have the expected number of pages */
2550 GEM_BUG_ON(i != n_pages);
2551
2552 switch (type) {
2553 case I915_MAP_WB:
2554 pgprot = PAGE_KERNEL;
2555 break;
2556 case I915_MAP_WC:
2557 pgprot = pgprot_writecombine(PAGE_KERNEL_IO);
2558 break;
2559 }
2560 addr = vmap(pages, n_pages, 0, pgprot);
2561
2562 if (pages != stack_pages)
2563 drm_free_large(pages);
2564
2565 return addr;
2566}
2567
2568/* get, pin, and map the pages of the object into kernel space */
2569void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
2570 enum i915_map_type type)
2571{
2572 enum i915_map_type has_type;
2573 bool pinned;
2574 void *ptr;
2575 int ret;
2576
2577 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
2578
2579 ret = mutex_lock_interruptible(&obj->mm.lock);
2580 if (ret)
2581 return ERR_PTR(ret);
2582
2583 pinned = true;
2584 if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {
2585 if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
2586 ret = ____i915_gem_object_get_pages(obj);
2587 if (ret)
2588 goto err_unlock;
2589
2590 smp_mb__before_atomic();
2591 }
2592 atomic_inc(&obj->mm.pages_pin_count);
2593 pinned = false;
2594 }
2595 GEM_BUG_ON(!obj->mm.pages);
2596
2597 ptr = ptr_unpack_bits(obj->mm.mapping, has_type);
2598 if (ptr && has_type != type) {
2599 if (pinned) {
2600 ret = -EBUSY;
2601 goto err_unpin;
2602 }
2603
2604 if (is_vmalloc_addr(ptr))
2605 vunmap(ptr);
2606 else
2607 kunmap(kmap_to_page(ptr));
2608
2609 ptr = obj->mm.mapping = NULL;
2610 }
2611
2612 if (!ptr) {
2613 ptr = i915_gem_object_map(obj, type);
2614 if (!ptr) {
2615 ret = -ENOMEM;
2616 goto err_unpin;
2617 }
2618
2619 obj->mm.mapping = ptr_pack_bits(ptr, type);
2620 }
2621
2622out_unlock:
2623 mutex_unlock(&obj->mm.lock);
2624 return ptr;
2625
2626err_unpin:
2627 atomic_dec(&obj->mm.pages_pin_count);
2628err_unlock:
2629 ptr = ERR_PTR(ret);
2630 goto out_unlock;
2631}
2632
2633static bool i915_context_is_banned(const struct i915_gem_context *ctx)
2634{
2635 unsigned long elapsed;
2636
2637 if (ctx->hang_stats.banned)
2638 return true;
2639
2640 elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2641 if (ctx->hang_stats.ban_period_seconds &&
2642 elapsed <= ctx->hang_stats.ban_period_seconds) {
2643 DRM_DEBUG("context hanging too fast, banning!\n");
2644 return true;
2645 }
2646
2647 return false;
2648}
2649
2650static void i915_set_reset_status(struct i915_gem_context *ctx,
2651 const bool guilty)
2652{
2653 struct i915_ctx_hang_stats *hs = &ctx->hang_stats;
2654
2655 if (guilty) {
2656 hs->banned = i915_context_is_banned(ctx);
2657 hs->batch_active++;
2658 hs->guilty_ts = get_seconds();
2659 } else {
2660 hs->batch_pending++;
2661 }
2662}
2663
2664struct drm_i915_gem_request *
2665i915_gem_find_active_request(struct intel_engine_cs *engine)
2666{
2667 struct drm_i915_gem_request *request;
2668
2669 /* We are called by the error capture and reset at a random
2670 * point in time. In particular, note that neither is crucially
2671 * ordered with an interrupt. After a hang, the GPU is dead and we
2672 * assume that no more writes can happen (we waited long enough for
2673 * all writes that were in transaction to be flushed) - adding an
2674 * extra delay for a recent interrupt is pointless. Hence, we do
2675 * not need an engine->irq_seqno_barrier() before the seqno reads.
2676 */
2677 list_for_each_entry(request, &engine->timeline->requests, link) {
2678 if (__i915_gem_request_completed(request))
2679 continue;
2680
2681 return request;
2682 }
2683
2684 return NULL;
2685}
2686
2687static void reset_request(struct drm_i915_gem_request *request)
2688{
2689 void *vaddr = request->ring->vaddr;
2690 u32 head;
2691
2692 /* As this request likely depends on state from the lost
2693 * context, clear out all the user operations leaving the
2694 * breadcrumb at the end (so we get the fence notifications).
2695 */
2696 head = request->head;
2697 if (request->postfix < head) {
2698 memset(vaddr + head, 0, request->ring->size - head);
2699 head = 0;
2700 }
2701 memset(vaddr + head, 0, request->postfix - head);
2702}
2703
2704static void i915_gem_reset_engine(struct intel_engine_cs *engine)
2705{
2706 struct drm_i915_gem_request *request;
2707 struct i915_gem_context *incomplete_ctx;
2708 struct intel_timeline *timeline;
2709 unsigned long flags;
2710 bool ring_hung;
2711
2712 if (engine->irq_seqno_barrier)
2713 engine->irq_seqno_barrier(engine);
2714
2715 request = i915_gem_find_active_request(engine);
2716 if (!request)
2717 return;
2718
2719 ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2720 if (engine->hangcheck.seqno != intel_engine_get_seqno(engine))
2721 ring_hung = false;
2722
2723 i915_set_reset_status(request->ctx, ring_hung);
2724 if (!ring_hung)
2725 return;
2726
2727 DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n",
2728 engine->name, request->global_seqno);
2729
2730 /* Setup the CS to resume from the breadcrumb of the hung request */
2731 engine->reset_hw(engine, request);
2732
2733 /* Users of the default context do not rely on logical state
2734 * preserved between batches. They have to emit full state on
2735 * every batch and so it is safe to execute queued requests following
2736 * the hang.
2737 *
2738 * Other contexts preserve state, now corrupt. We want to skip all
2739 * queued requests that reference the corrupt context.
2740 */
2741 incomplete_ctx = request->ctx;
2742 if (i915_gem_context_is_default(incomplete_ctx))
2743 return;
2744
2745 timeline = i915_gem_context_lookup_timeline(incomplete_ctx, engine);
2746
2747 spin_lock_irqsave(&engine->timeline->lock, flags);
2748 spin_lock(&timeline->lock);
2749
2750 list_for_each_entry_continue(request, &engine->timeline->requests, link)
2751 if (request->ctx == incomplete_ctx)
2752 reset_request(request);
2753
2754 list_for_each_entry(request, &timeline->requests, link)
2755 reset_request(request);
2756
2757 spin_unlock(&timeline->lock);
2758 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2759}
2760
2761void i915_gem_reset(struct drm_i915_private *dev_priv)
2762{
2763 struct intel_engine_cs *engine;
2764 enum intel_engine_id id;
2765
2766 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2767
2768 i915_gem_retire_requests(dev_priv);
2769
2770 for_each_engine(engine, dev_priv, id)
2771 i915_gem_reset_engine(engine);
2772
2773 i915_gem_restore_fences(dev_priv);
2774
2775 if (dev_priv->gt.awake) {
2776 intel_sanitize_gt_powersave(dev_priv);
2777 intel_enable_gt_powersave(dev_priv);
2778 if (INTEL_GEN(dev_priv) >= 6)
2779 gen6_rps_busy(dev_priv);
2780 }
2781}
2782
2783static void nop_submit_request(struct drm_i915_gem_request *request)
2784{
2785 i915_gem_request_submit(request);
2786 intel_engine_init_global_seqno(request->engine, request->global_seqno);
2787}
2788
2789static void i915_gem_cleanup_engine(struct intel_engine_cs *engine)
2790{
2791 engine->submit_request = nop_submit_request;
2792
2793 /* Mark all pending requests as complete so that any concurrent
2794 * (lockless) lookup doesn't try and wait upon the request as we
2795 * reset it.
2796 */
2797 intel_engine_init_global_seqno(engine,
2798 intel_engine_last_submit(engine));
2799
2800 /*
2801 * Clear the execlists queue up before freeing the requests, as those
2802 * are the ones that keep the context and ringbuffer backing objects
2803 * pinned in place.
2804 */
2805
2806 if (i915.enable_execlists) {
2807 unsigned long flags;
2808
2809 spin_lock_irqsave(&engine->timeline->lock, flags);
2810
2811 i915_gem_request_put(engine->execlist_port[0].request);
2812 i915_gem_request_put(engine->execlist_port[1].request);
2813 memset(engine->execlist_port, 0, sizeof(engine->execlist_port));
2814 engine->execlist_queue = RB_ROOT;
2815 engine->execlist_first = NULL;
2816
2817 spin_unlock_irqrestore(&engine->timeline->lock, flags);
2818 }
2819}
2820
2821void i915_gem_set_wedged(struct drm_i915_private *dev_priv)
2822{
2823 struct intel_engine_cs *engine;
2824 enum intel_engine_id id;
2825
2826 lockdep_assert_held(&dev_priv->drm.struct_mutex);
2827 set_bit(I915_WEDGED, &dev_priv->gpu_error.flags);
2828
2829 i915_gem_context_lost(dev_priv);
2830 for_each_engine(engine, dev_priv, id)
2831 i915_gem_cleanup_engine(engine);
2832 mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0);
2833
2834 i915_gem_retire_requests(dev_priv);
2835}
2836
2837static void
2838i915_gem_retire_work_handler(struct work_struct *work)
2839{
2840 struct drm_i915_private *dev_priv =
2841 container_of(work, typeof(*dev_priv), gt.retire_work.work);
2842 struct drm_device *dev = &dev_priv->drm;
2843
2844 /* Come back later if the device is busy... */
2845 if (mutex_trylock(&dev->struct_mutex)) {
2846 i915_gem_retire_requests(dev_priv);
2847 mutex_unlock(&dev->struct_mutex);
2848 }
2849
2850 /* Keep the retire handler running until we are finally idle.
2851 * We do not need to do this test under locking as in the worst-case
2852 * we queue the retire worker once too often.
2853 */
2854 if (READ_ONCE(dev_priv->gt.awake)) {
2855 i915_queue_hangcheck(dev_priv);
2856 queue_delayed_work(dev_priv->wq,
2857 &dev_priv->gt.retire_work,
2858 round_jiffies_up_relative(HZ));
2859 }
2860}
2861
2862static void
2863i915_gem_idle_work_handler(struct work_struct *work)
2864{
2865 struct drm_i915_private *dev_priv =
2866 container_of(work, typeof(*dev_priv), gt.idle_work.work);
2867 struct drm_device *dev = &dev_priv->drm;
2868 struct intel_engine_cs *engine;
2869 enum intel_engine_id id;
2870 bool rearm_hangcheck;
2871
2872 if (!READ_ONCE(dev_priv->gt.awake))
2873 return;
2874
2875 /*
2876 * Wait for last execlists context complete, but bail out in case a
2877 * new request is submitted.
2878 */
2879 wait_for(READ_ONCE(dev_priv->gt.active_requests) ||
2880 intel_execlists_idle(dev_priv), 10);
2881
2882 if (READ_ONCE(dev_priv->gt.active_requests))
2883 return;
2884
2885 rearm_hangcheck =
2886 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
2887
2888 if (!mutex_trylock(&dev->struct_mutex)) {
2889 /* Currently busy, come back later */
2890 mod_delayed_work(dev_priv->wq,
2891 &dev_priv->gt.idle_work,
2892 msecs_to_jiffies(50));
2893 goto out_rearm;
2894 }
2895
2896 /*
2897 * New request retired after this work handler started, extend active
2898 * period until next instance of the work.
2899 */
2900 if (work_pending(work))
2901 goto out_unlock;
2902
2903 if (dev_priv->gt.active_requests)
2904 goto out_unlock;
2905
2906 if (wait_for(intel_execlists_idle(dev_priv), 10))
2907 DRM_ERROR("Timeout waiting for engines to idle\n");
2908
2909 for_each_engine(engine, dev_priv, id)
2910 i915_gem_batch_pool_fini(&engine->batch_pool);
2911
2912 GEM_BUG_ON(!dev_priv->gt.awake);
2913 dev_priv->gt.awake = false;
2914 rearm_hangcheck = false;
2915
2916 if (INTEL_GEN(dev_priv) >= 6)
2917 gen6_rps_idle(dev_priv);
2918 intel_runtime_pm_put(dev_priv);
2919out_unlock:
2920 mutex_unlock(&dev->struct_mutex);
2921
2922out_rearm:
2923 if (rearm_hangcheck) {
2924 GEM_BUG_ON(!dev_priv->gt.awake);
2925 i915_queue_hangcheck(dev_priv);
2926 }
2927}
2928
2929void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file)
2930{
2931 struct drm_i915_gem_object *obj = to_intel_bo(gem);
2932 struct drm_i915_file_private *fpriv = file->driver_priv;
2933 struct i915_vma *vma, *vn;
2934
2935 mutex_lock(&obj->base.dev->struct_mutex);
2936 list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link)
2937 if (vma->vm->file == fpriv)
2938 i915_vma_close(vma);
2939
2940 if (i915_gem_object_is_active(obj) &&
2941 !i915_gem_object_has_active_reference(obj)) {
2942 i915_gem_object_set_active_reference(obj);
2943 i915_gem_object_get(obj);
2944 }
2945 mutex_unlock(&obj->base.dev->struct_mutex);
2946}
2947
2948static unsigned long to_wait_timeout(s64 timeout_ns)
2949{
2950 if (timeout_ns < 0)
2951 return MAX_SCHEDULE_TIMEOUT;
2952
2953 if (timeout_ns == 0)
2954 return 0;
2955
2956 return nsecs_to_jiffies_timeout(timeout_ns);
2957}
2958
2959/**
2960 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2961 * @dev: drm device pointer
2962 * @data: ioctl data blob
2963 * @file: drm file pointer
2964 *
2965 * Returns 0 if successful, else an error is returned with the remaining time in
2966 * the timeout parameter.
2967 * -ETIME: object is still busy after timeout
2968 * -ERESTARTSYS: signal interrupted the wait
2969 * -ENONENT: object doesn't exist
2970 * Also possible, but rare:
2971 * -EAGAIN: GPU wedged
2972 * -ENOMEM: damn
2973 * -ENODEV: Internal IRQ fail
2974 * -E?: The add request failed
2975 *
2976 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2977 * non-zero timeout parameter the wait ioctl will wait for the given number of
2978 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2979 * without holding struct_mutex the object may become re-busied before this
2980 * function completes. A similar but shorter * race condition exists in the busy
2981 * ioctl
2982 */
2983int
2984i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2985{
2986 struct drm_i915_gem_wait *args = data;
2987 struct drm_i915_gem_object *obj;
2988 ktime_t start;
2989 long ret;
2990
2991 if (args->flags != 0)
2992 return -EINVAL;
2993
2994 obj = i915_gem_object_lookup(file, args->bo_handle);
2995 if (!obj)
2996 return -ENOENT;
2997
2998 start = ktime_get();
2999
3000 ret = i915_gem_object_wait(obj,
3001 I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL,
3002 to_wait_timeout(args->timeout_ns),
3003 to_rps_client(file));
3004
3005 if (args->timeout_ns > 0) {
3006 args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start));
3007 if (args->timeout_ns < 0)
3008 args->timeout_ns = 0;
3009
3010 /*
3011 * Apparently ktime isn't accurate enough and occasionally has a
3012 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
3013 * things up to make the test happy. We allow up to 1 jiffy.
3014 *
3015 * This is a regression from the timespec->ktime conversion.
3016 */
3017 if (ret == -ETIME && !nsecs_to_jiffies(args->timeout_ns))
3018 args->timeout_ns = 0;
3019 }
3020
3021 i915_gem_object_put(obj);
3022 return ret;
3023}
3024
3025static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags)
3026{
3027 int ret, i;
3028
3029 for (i = 0; i < ARRAY_SIZE(tl->engine); i++) {
3030 ret = i915_gem_active_wait(&tl->engine[i].last_request, flags);
3031 if (ret)
3032 return ret;
3033 }
3034
3035 return 0;
3036}
3037
3038int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags)
3039{
3040 int ret;
3041
3042 if (flags & I915_WAIT_LOCKED) {
3043 struct i915_gem_timeline *tl;
3044
3045 lockdep_assert_held(&i915->drm.struct_mutex);
3046
3047 list_for_each_entry(tl, &i915->gt.timelines, link) {
3048 ret = wait_for_timeline(tl, flags);
3049 if (ret)
3050 return ret;
3051 }
3052 } else {
3053 ret = wait_for_timeline(&i915->gt.global_timeline, flags);
3054 if (ret)
3055 return ret;
3056 }
3057
3058 return 0;
3059}
3060
3061void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3062 bool force)
3063{
3064 /* If we don't have a page list set up, then we're not pinned
3065 * to GPU, and we can ignore the cache flush because it'll happen
3066 * again at bind time.
3067 */
3068 if (!obj->mm.pages)
3069 return;
3070
3071 /*
3072 * Stolen memory is always coherent with the GPU as it is explicitly
3073 * marked as wc by the system, or the system is cache-coherent.
3074 */
3075 if (obj->stolen || obj->phys_handle)
3076 return;
3077
3078 /* If the GPU is snooping the contents of the CPU cache,
3079 * we do not need to manually clear the CPU cache lines. However,
3080 * the caches are only snooped when the render cache is
3081 * flushed/invalidated. As we always have to emit invalidations
3082 * and flushes when moving into and out of the RENDER domain, correct
3083 * snooping behaviour occurs naturally as the result of our domain
3084 * tracking.
3085 */
3086 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3087 obj->cache_dirty = true;
3088 return;
3089 }
3090
3091 trace_i915_gem_object_clflush(obj);
3092 drm_clflush_sg(obj->mm.pages);
3093 obj->cache_dirty = false;
3094}
3095
3096/** Flushes the GTT write domain for the object if it's dirty. */
3097static void
3098i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3099{
3100 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3101
3102 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3103 return;
3104
3105 /* No actual flushing is required for the GTT write domain. Writes
3106 * to it "immediately" go to main memory as far as we know, so there's
3107 * no chipset flush. It also doesn't land in render cache.
3108 *
3109 * However, we do have to enforce the order so that all writes through
3110 * the GTT land before any writes to the device, such as updates to
3111 * the GATT itself.
3112 *
3113 * We also have to wait a bit for the writes to land from the GTT.
3114 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
3115 * timing. This issue has only been observed when switching quickly
3116 * between GTT writes and CPU reads from inside the kernel on recent hw,
3117 * and it appears to only affect discrete GTT blocks (i.e. on LLC
3118 * system agents we cannot reproduce this behaviour).
3119 */
3120 wmb();
3121 if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv))
3122 POSTING_READ(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
3123
3124 intel_fb_obj_flush(obj, false, write_origin(obj, I915_GEM_DOMAIN_GTT));
3125
3126 obj->base.write_domain = 0;
3127 trace_i915_gem_object_change_domain(obj,
3128 obj->base.read_domains,
3129 I915_GEM_DOMAIN_GTT);
3130}
3131
3132/** Flushes the CPU write domain for the object if it's dirty. */
3133static void
3134i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3135{
3136 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3137 return;
3138
3139 i915_gem_clflush_object(obj, obj->pin_display);
3140 intel_fb_obj_flush(obj, false, ORIGIN_CPU);
3141
3142 obj->base.write_domain = 0;
3143 trace_i915_gem_object_change_domain(obj,
3144 obj->base.read_domains,
3145 I915_GEM_DOMAIN_CPU);
3146}
3147
3148/**
3149 * Moves a single object to the GTT read, and possibly write domain.
3150 * @obj: object to act on
3151 * @write: ask for write access or read only
3152 *
3153 * This function returns when the move is complete, including waiting on
3154 * flushes to occur.
3155 */
3156int
3157i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3158{
3159 uint32_t old_write_domain, old_read_domains;
3160 int ret;
3161
3162 lockdep_assert_held(&obj->base.dev->struct_mutex);
3163
3164 ret = i915_gem_object_wait(obj,
3165 I915_WAIT_INTERRUPTIBLE |
3166 I915_WAIT_LOCKED |
3167 (write ? I915_WAIT_ALL : 0),
3168 MAX_SCHEDULE_TIMEOUT,
3169 NULL);
3170 if (ret)
3171 return ret;
3172
3173 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3174 return 0;
3175
3176 /* Flush and acquire obj->pages so that we are coherent through
3177 * direct access in memory with previous cached writes through
3178 * shmemfs and that our cache domain tracking remains valid.
3179 * For example, if the obj->filp was moved to swap without us
3180 * being notified and releasing the pages, we would mistakenly
3181 * continue to assume that the obj remained out of the CPU cached
3182 * domain.
3183 */
3184 ret = i915_gem_object_pin_pages(obj);
3185 if (ret)
3186 return ret;
3187
3188 i915_gem_object_flush_cpu_write_domain(obj);
3189
3190 /* Serialise direct access to this object with the barriers for
3191 * coherent writes from the GPU, by effectively invalidating the
3192 * GTT domain upon first access.
3193 */
3194 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3195 mb();
3196
3197 old_write_domain = obj->base.write_domain;
3198 old_read_domains = obj->base.read_domains;
3199
3200 /* It should now be out of any other write domains, and we can update
3201 * the domain values for our changes.
3202 */
3203 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3204 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3205 if (write) {
3206 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3207 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3208 obj->mm.dirty = true;
3209 }
3210
3211 trace_i915_gem_object_change_domain(obj,
3212 old_read_domains,
3213 old_write_domain);
3214
3215 i915_gem_object_unpin_pages(obj);
3216 return 0;
3217}
3218
3219/**
3220 * Changes the cache-level of an object across all VMA.
3221 * @obj: object to act on
3222 * @cache_level: new cache level to set for the object
3223 *
3224 * After this function returns, the object will be in the new cache-level
3225 * across all GTT and the contents of the backing storage will be coherent,
3226 * with respect to the new cache-level. In order to keep the backing storage
3227 * coherent for all users, we only allow a single cache level to be set
3228 * globally on the object and prevent it from being changed whilst the
3229 * hardware is reading from the object. That is if the object is currently
3230 * on the scanout it will be set to uncached (or equivalent display
3231 * cache coherency) and all non-MOCS GPU access will also be uncached so
3232 * that all direct access to the scanout remains coherent.
3233 */
3234int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3235 enum i915_cache_level cache_level)
3236{
3237 struct i915_vma *vma;
3238 int ret;
3239
3240 lockdep_assert_held(&obj->base.dev->struct_mutex);
3241
3242 if (obj->cache_level == cache_level)
3243 return 0;
3244
3245 /* Inspect the list of currently bound VMA and unbind any that would
3246 * be invalid given the new cache-level. This is principally to
3247 * catch the issue of the CS prefetch crossing page boundaries and
3248 * reading an invalid PTE on older architectures.
3249 */
3250restart:
3251 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3252 if (!drm_mm_node_allocated(&vma->node))
3253 continue;
3254
3255 if (i915_vma_is_pinned(vma)) {
3256 DRM_DEBUG("can not change the cache level of pinned objects\n");
3257 return -EBUSY;
3258 }
3259
3260 if (i915_gem_valid_gtt_space(vma, cache_level))
3261 continue;
3262
3263 ret = i915_vma_unbind(vma);
3264 if (ret)
3265 return ret;
3266
3267 /* As unbinding may affect other elements in the
3268 * obj->vma_list (due to side-effects from retiring
3269 * an active vma), play safe and restart the iterator.
3270 */
3271 goto restart;
3272 }
3273
3274 /* We can reuse the existing drm_mm nodes but need to change the
3275 * cache-level on the PTE. We could simply unbind them all and
3276 * rebind with the correct cache-level on next use. However since
3277 * we already have a valid slot, dma mapping, pages etc, we may as
3278 * rewrite the PTE in the belief that doing so tramples upon less
3279 * state and so involves less work.
3280 */
3281 if (obj->bind_count) {
3282 /* Before we change the PTE, the GPU must not be accessing it.
3283 * If we wait upon the object, we know that all the bound
3284 * VMA are no longer active.
3285 */
3286 ret = i915_gem_object_wait(obj,
3287 I915_WAIT_INTERRUPTIBLE |
3288 I915_WAIT_LOCKED |
3289 I915_WAIT_ALL,
3290 MAX_SCHEDULE_TIMEOUT,
3291 NULL);
3292 if (ret)
3293 return ret;
3294
3295 if (!HAS_LLC(to_i915(obj->base.dev)) &&
3296 cache_level != I915_CACHE_NONE) {
3297 /* Access to snoopable pages through the GTT is
3298 * incoherent and on some machines causes a hard
3299 * lockup. Relinquish the CPU mmaping to force
3300 * userspace to refault in the pages and we can
3301 * then double check if the GTT mapping is still
3302 * valid for that pointer access.
3303 */
3304 i915_gem_release_mmap(obj);
3305
3306 /* As we no longer need a fence for GTT access,
3307 * we can relinquish it now (and so prevent having
3308 * to steal a fence from someone else on the next
3309 * fence request). Note GPU activity would have
3310 * dropped the fence as all snoopable access is
3311 * supposed to be linear.
3312 */
3313 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3314 ret = i915_vma_put_fence(vma);
3315 if (ret)
3316 return ret;
3317 }
3318 } else {
3319 /* We either have incoherent backing store and
3320 * so no GTT access or the architecture is fully
3321 * coherent. In such cases, existing GTT mmaps
3322 * ignore the cache bit in the PTE and we can
3323 * rewrite it without confusing the GPU or having
3324 * to force userspace to fault back in its mmaps.
3325 */
3326 }
3327
3328 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3329 if (!drm_mm_node_allocated(&vma->node))
3330 continue;
3331
3332 ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
3333 if (ret)
3334 return ret;
3335 }
3336 }
3337
3338 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU &&
3339 cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3340 obj->cache_dirty = true;
3341
3342 list_for_each_entry(vma, &obj->vma_list, obj_link)
3343 vma->node.color = cache_level;
3344 obj->cache_level = cache_level;
3345
3346 return 0;
3347}
3348
3349int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3350 struct drm_file *file)
3351{
3352 struct drm_i915_gem_caching *args = data;
3353 struct drm_i915_gem_object *obj;
3354 int err = 0;
3355
3356 rcu_read_lock();
3357 obj = i915_gem_object_lookup_rcu(file, args->handle);
3358 if (!obj) {
3359 err = -ENOENT;
3360 goto out;
3361 }
3362
3363 switch (obj->cache_level) {
3364 case I915_CACHE_LLC:
3365 case I915_CACHE_L3_LLC:
3366 args->caching = I915_CACHING_CACHED;
3367 break;
3368
3369 case I915_CACHE_WT:
3370 args->caching = I915_CACHING_DISPLAY;
3371 break;
3372
3373 default:
3374 args->caching = I915_CACHING_NONE;
3375 break;
3376 }
3377out:
3378 rcu_read_unlock();
3379 return err;
3380}
3381
3382int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3383 struct drm_file *file)
3384{
3385 struct drm_i915_private *i915 = to_i915(dev);
3386 struct drm_i915_gem_caching *args = data;
3387 struct drm_i915_gem_object *obj;
3388 enum i915_cache_level level;
3389 int ret;
3390
3391 switch (args->caching) {
3392 case I915_CACHING_NONE:
3393 level = I915_CACHE_NONE;
3394 break;
3395 case I915_CACHING_CACHED:
3396 /*
3397 * Due to a HW issue on BXT A stepping, GPU stores via a
3398 * snooped mapping may leave stale data in a corresponding CPU
3399 * cacheline, whereas normally such cachelines would get
3400 * invalidated.
3401 */
3402 if (!HAS_LLC(i915) && !HAS_SNOOP(i915))
3403 return -ENODEV;
3404
3405 level = I915_CACHE_LLC;
3406 break;
3407 case I915_CACHING_DISPLAY:
3408 level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE;
3409 break;
3410 default:
3411 return -EINVAL;
3412 }
3413
3414 ret = i915_mutex_lock_interruptible(dev);
3415 if (ret)
3416 return ret;
3417
3418 obj = i915_gem_object_lookup(file, args->handle);
3419 if (!obj) {
3420 ret = -ENOENT;
3421 goto unlock;
3422 }
3423
3424 ret = i915_gem_object_set_cache_level(obj, level);
3425 i915_gem_object_put(obj);
3426unlock:
3427 mutex_unlock(&dev->struct_mutex);
3428 return ret;
3429}
3430
3431/*
3432 * Prepare buffer for display plane (scanout, cursors, etc).
3433 * Can be called from an uninterruptible phase (modesetting) and allows
3434 * any flushes to be pipelined (for pageflips).
3435 */
3436struct i915_vma *
3437i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3438 u32 alignment,
3439 const struct i915_ggtt_view *view)
3440{
3441 struct i915_vma *vma;
3442 u32 old_read_domains, old_write_domain;
3443 int ret;
3444
3445 lockdep_assert_held(&obj->base.dev->struct_mutex);
3446
3447 /* Mark the pin_display early so that we account for the
3448 * display coherency whilst setting up the cache domains.
3449 */
3450 obj->pin_display++;
3451
3452 /* The display engine is not coherent with the LLC cache on gen6. As
3453 * a result, we make sure that the pinning that is about to occur is
3454 * done with uncached PTEs. This is lowest common denominator for all
3455 * chipsets.
3456 *
3457 * However for gen6+, we could do better by using the GFDT bit instead
3458 * of uncaching, which would allow us to flush all the LLC-cached data
3459 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3460 */
3461 ret = i915_gem_object_set_cache_level(obj,
3462 HAS_WT(to_i915(obj->base.dev)) ?
3463 I915_CACHE_WT : I915_CACHE_NONE);
3464 if (ret) {
3465 vma = ERR_PTR(ret);
3466 goto err_unpin_display;
3467 }
3468
3469 /* As the user may map the buffer once pinned in the display plane
3470 * (e.g. libkms for the bootup splash), we have to ensure that we
3471 * always use map_and_fenceable for all scanout buffers. However,
3472 * it may simply be too big to fit into mappable, in which case
3473 * put it anyway and hope that userspace can cope (but always first
3474 * try to preserve the existing ABI).
3475 */
3476 vma = ERR_PTR(-ENOSPC);
3477 if (view->type == I915_GGTT_VIEW_NORMAL)
3478 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment,
3479 PIN_MAPPABLE | PIN_NONBLOCK);
3480 if (IS_ERR(vma)) {
3481 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3482 unsigned int flags;
3483
3484 /* Valleyview is definitely limited to scanning out the first
3485 * 512MiB. Lets presume this behaviour was inherited from the
3486 * g4x display engine and that all earlier gen are similarly
3487 * limited. Testing suggests that it is a little more
3488 * complicated than this. For example, Cherryview appears quite
3489 * happy to scanout from anywhere within its global aperture.
3490 */
3491 flags = 0;
3492 if (HAS_GMCH_DISPLAY(i915))
3493 flags = PIN_MAPPABLE;
3494 vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags);
3495 }
3496 if (IS_ERR(vma))
3497 goto err_unpin_display;
3498
3499 vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
3500
3501 /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
3502 if (obj->cache_dirty || obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
3503 i915_gem_clflush_object(obj, true);
3504 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
3505 }
3506
3507 old_write_domain = obj->base.write_domain;
3508 old_read_domains = obj->base.read_domains;
3509
3510 /* It should now be out of any other write domains, and we can update
3511 * the domain values for our changes.
3512 */
3513 obj->base.write_domain = 0;
3514 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3515
3516 trace_i915_gem_object_change_domain(obj,
3517 old_read_domains,
3518 old_write_domain);
3519
3520 return vma;
3521
3522err_unpin_display:
3523 obj->pin_display--;
3524 return vma;
3525}
3526
3527void
3528i915_gem_object_unpin_from_display_plane(struct i915_vma *vma)
3529{
3530 lockdep_assert_held(&vma->vm->dev->struct_mutex);
3531
3532 if (WARN_ON(vma->obj->pin_display == 0))
3533 return;
3534
3535 if (--vma->obj->pin_display == 0)
3536 vma->display_alignment = 0;
3537
3538 /* Bump the LRU to try and avoid premature eviction whilst flipping */
3539 if (!i915_vma_is_active(vma))
3540 list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
3541
3542 i915_vma_unpin(vma);
3543}
3544
3545/**
3546 * Moves a single object to the CPU read, and possibly write domain.
3547 * @obj: object to act on
3548 * @write: requesting write or read-only access
3549 *
3550 * This function returns when the move is complete, including waiting on
3551 * flushes to occur.
3552 */
3553int
3554i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3555{
3556 uint32_t old_write_domain, old_read_domains;
3557 int ret;
3558
3559 lockdep_assert_held(&obj->base.dev->struct_mutex);
3560
3561 ret = i915_gem_object_wait(obj,
3562 I915_WAIT_INTERRUPTIBLE |
3563 I915_WAIT_LOCKED |
3564 (write ? I915_WAIT_ALL : 0),
3565 MAX_SCHEDULE_TIMEOUT,
3566 NULL);
3567 if (ret)
3568 return ret;
3569
3570 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3571 return 0;
3572
3573 i915_gem_object_flush_gtt_write_domain(obj);
3574
3575 old_write_domain = obj->base.write_domain;
3576 old_read_domains = obj->base.read_domains;
3577
3578 /* Flush the CPU cache if it's still invalid. */
3579 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3580 i915_gem_clflush_object(obj, false);
3581
3582 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3583 }
3584
3585 /* It should now be out of any other write domains, and we can update
3586 * the domain values for our changes.
3587 */
3588 GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3589
3590 /* If we're writing through the CPU, then the GPU read domains will
3591 * need to be invalidated at next use.
3592 */
3593 if (write) {
3594 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3595 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3596 }
3597
3598 trace_i915_gem_object_change_domain(obj,
3599 old_read_domains,
3600 old_write_domain);
3601
3602 return 0;
3603}
3604
3605/* Throttle our rendering by waiting until the ring has completed our requests
3606 * emitted over 20 msec ago.
3607 *
3608 * Note that if we were to use the current jiffies each time around the loop,
3609 * we wouldn't escape the function with any frames outstanding if the time to
3610 * render a frame was over 20ms.
3611 *
3612 * This should get us reasonable parallelism between CPU and GPU but also
3613 * relatively low latency when blocking on a particular request to finish.
3614 */
3615static int
3616i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3617{
3618 struct drm_i915_private *dev_priv = to_i915(dev);
3619 struct drm_i915_file_private *file_priv = file->driver_priv;
3620 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
3621 struct drm_i915_gem_request *request, *target = NULL;
3622 long ret;
3623
3624 /* ABI: return -EIO if already wedged */
3625 if (i915_terminally_wedged(&dev_priv->gpu_error))
3626 return -EIO;
3627
3628 spin_lock(&file_priv->mm.lock);
3629 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3630 if (time_after_eq(request->emitted_jiffies, recent_enough))
3631 break;
3632
3633 /*
3634 * Note that the request might not have been submitted yet.
3635 * In which case emitted_jiffies will be zero.
3636 */
3637 if (!request->emitted_jiffies)
3638 continue;
3639
3640 target = request;
3641 }
3642 if (target)
3643 i915_gem_request_get(target);
3644 spin_unlock(&file_priv->mm.lock);
3645
3646 if (target == NULL)
3647 return 0;
3648
3649 ret = i915_wait_request(target,
3650 I915_WAIT_INTERRUPTIBLE,
3651 MAX_SCHEDULE_TIMEOUT);
3652 i915_gem_request_put(target);
3653
3654 return ret < 0 ? ret : 0;
3655}
3656
3657struct i915_vma *
3658i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3659 const struct i915_ggtt_view *view,
3660 u64 size,
3661 u64 alignment,
3662 u64 flags)
3663{
3664 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3665 struct i915_address_space *vm = &dev_priv->ggtt.base;
3666 struct i915_vma *vma;
3667 int ret;
3668
3669 lockdep_assert_held(&obj->base.dev->struct_mutex);
3670
3671 vma = i915_gem_obj_lookup_or_create_vma(obj, vm, view);
3672 if (IS_ERR(vma))
3673 return vma;
3674
3675 if (i915_vma_misplaced(vma, size, alignment, flags)) {
3676 if (flags & PIN_NONBLOCK &&
3677 (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)))
3678 return ERR_PTR(-ENOSPC);
3679
3680 if (flags & PIN_MAPPABLE) {
3681 u32 fence_size;
3682
3683 fence_size = i915_gem_get_ggtt_size(dev_priv, vma->size,
3684 i915_gem_object_get_tiling(obj));
3685 /* If the required space is larger than the available
3686 * aperture, we will not able to find a slot for the
3687 * object and unbinding the object now will be in
3688 * vain. Worse, doing so may cause us to ping-pong
3689 * the object in and out of the Global GTT and
3690 * waste a lot of cycles under the mutex.
3691 */
3692 if (fence_size > dev_priv->ggtt.mappable_end)
3693 return ERR_PTR(-E2BIG);
3694
3695 /* If NONBLOCK is set the caller is optimistically
3696 * trying to cache the full object within the mappable
3697 * aperture, and *must* have a fallback in place for
3698 * situations where we cannot bind the object. We
3699 * can be a little more lax here and use the fallback
3700 * more often to avoid costly migrations of ourselves
3701 * and other objects within the aperture.
3702 *
3703 * Half-the-aperture is used as a simple heuristic.
3704 * More interesting would to do search for a free
3705 * block prior to making the commitment to unbind.
3706 * That caters for the self-harm case, and with a
3707 * little more heuristics (e.g. NOFAULT, NOEVICT)
3708 * we could try to minimise harm to others.
3709 */
3710 if (flags & PIN_NONBLOCK &&
3711 fence_size > dev_priv->ggtt.mappable_end / 2)
3712 return ERR_PTR(-ENOSPC);
3713 }
3714
3715 WARN(i915_vma_is_pinned(vma),
3716 "bo is already pinned in ggtt with incorrect alignment:"
3717 " offset=%08x, req.alignment=%llx,"
3718 " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n",
3719 i915_ggtt_offset(vma), alignment,
3720 !!(flags & PIN_MAPPABLE),
3721 i915_vma_is_map_and_fenceable(vma));
3722 ret = i915_vma_unbind(vma);
3723 if (ret)
3724 return ERR_PTR(ret);
3725 }
3726
3727 ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL);
3728 if (ret)
3729 return ERR_PTR(ret);
3730
3731 return vma;
3732}
3733
3734static __always_inline unsigned int __busy_read_flag(unsigned int id)
3735{
3736 /* Note that we could alias engines in the execbuf API, but
3737 * that would be very unwise as it prevents userspace from
3738 * fine control over engine selection. Ahem.
3739 *
3740 * This should be something like EXEC_MAX_ENGINE instead of
3741 * I915_NUM_ENGINES.
3742 */
3743 BUILD_BUG_ON(I915_NUM_ENGINES > 16);
3744 return 0x10000 << id;
3745}
3746
3747static __always_inline unsigned int __busy_write_id(unsigned int id)
3748{
3749 /* The uABI guarantees an active writer is also amongst the read
3750 * engines. This would be true if we accessed the activity tracking
3751 * under the lock, but as we perform the lookup of the object and
3752 * its activity locklessly we can not guarantee that the last_write
3753 * being active implies that we have set the same engine flag from
3754 * last_read - hence we always set both read and write busy for
3755 * last_write.
3756 */
3757 return id | __busy_read_flag(id);
3758}
3759
3760static __always_inline unsigned int
3761__busy_set_if_active(const struct dma_fence *fence,
3762 unsigned int (*flag)(unsigned int id))
3763{
3764 struct drm_i915_gem_request *rq;
3765
3766 /* We have to check the current hw status of the fence as the uABI
3767 * guarantees forward progress. We could rely on the idle worker
3768 * to eventually flush us, but to minimise latency just ask the
3769 * hardware.
3770 *
3771 * Note we only report on the status of native fences.
3772 */
3773 if (!dma_fence_is_i915(fence))
3774 return 0;
3775
3776 /* opencode to_request() in order to avoid const warnings */
3777 rq = container_of(fence, struct drm_i915_gem_request, fence);
3778 if (i915_gem_request_completed(rq))
3779 return 0;
3780
3781 return flag(rq->engine->exec_id);
3782}
3783
3784static __always_inline unsigned int
3785busy_check_reader(const struct dma_fence *fence)
3786{
3787 return __busy_set_if_active(fence, __busy_read_flag);
3788}
3789
3790static __always_inline unsigned int
3791busy_check_writer(const struct dma_fence *fence)
3792{
3793 if (!fence)
3794 return 0;
3795
3796 return __busy_set_if_active(fence, __busy_write_id);
3797}
3798
3799int
3800i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3801 struct drm_file *file)
3802{
3803 struct drm_i915_gem_busy *args = data;
3804 struct drm_i915_gem_object *obj;
3805 struct reservation_object_list *list;
3806 unsigned int seq;
3807 int err;
3808
3809 err = -ENOENT;
3810 rcu_read_lock();
3811 obj = i915_gem_object_lookup_rcu(file, args->handle);
3812 if (!obj)
3813 goto out;
3814
3815 /* A discrepancy here is that we do not report the status of
3816 * non-i915 fences, i.e. even though we may report the object as idle,
3817 * a call to set-domain may still stall waiting for foreign rendering.
3818 * This also means that wait-ioctl may report an object as busy,
3819 * where busy-ioctl considers it idle.
3820 *
3821 * We trade the ability to warn of foreign fences to report on which
3822 * i915 engines are active for the object.
3823 *
3824 * Alternatively, we can trade that extra information on read/write
3825 * activity with
3826 * args->busy =
3827 * !reservation_object_test_signaled_rcu(obj->resv, true);
3828 * to report the overall busyness. This is what the wait-ioctl does.
3829 *
3830 */
3831retry:
3832 seq = raw_read_seqcount(&obj->resv->seq);
3833
3834 /* Translate the exclusive fence to the READ *and* WRITE engine */
3835 args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl));
3836
3837 /* Translate shared fences to READ set of engines */
3838 list = rcu_dereference(obj->resv->fence);
3839 if (list) {
3840 unsigned int shared_count = list->shared_count, i;
3841
3842 for (i = 0; i < shared_count; ++i) {
3843 struct dma_fence *fence =
3844 rcu_dereference(list->shared[i]);
3845
3846 args->busy |= busy_check_reader(fence);
3847 }
3848 }
3849
3850 if (args->busy && read_seqcount_retry(&obj->resv->seq, seq))
3851 goto retry;
3852
3853 err = 0;
3854out:
3855 rcu_read_unlock();
3856 return err;
3857}
3858
3859int
3860i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3861 struct drm_file *file_priv)
3862{
3863 return i915_gem_ring_throttle(dev, file_priv);
3864}
3865
3866int
3867i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3868 struct drm_file *file_priv)
3869{
3870 struct drm_i915_private *dev_priv = to_i915(dev);
3871 struct drm_i915_gem_madvise *args = data;
3872 struct drm_i915_gem_object *obj;
3873 int err;
3874
3875 switch (args->madv) {
3876 case I915_MADV_DONTNEED:
3877 case I915_MADV_WILLNEED:
3878 break;
3879 default:
3880 return -EINVAL;
3881 }
3882
3883 obj = i915_gem_object_lookup(file_priv, args->handle);
3884 if (!obj)
3885 return -ENOENT;
3886
3887 err = mutex_lock_interruptible(&obj->mm.lock);
3888 if (err)
3889 goto out;
3890
3891 if (obj->mm.pages &&
3892 i915_gem_object_is_tiled(obj) &&
3893 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
3894 if (obj->mm.madv == I915_MADV_WILLNEED) {
3895 GEM_BUG_ON(!obj->mm.quirked);
3896 __i915_gem_object_unpin_pages(obj);
3897 obj->mm.quirked = false;
3898 }
3899 if (args->madv == I915_MADV_WILLNEED) {
3900 GEM_BUG_ON(obj->mm.quirked);
3901 __i915_gem_object_pin_pages(obj);
3902 obj->mm.quirked = true;
3903 }
3904 }
3905
3906 if (obj->mm.madv != __I915_MADV_PURGED)
3907 obj->mm.madv = args->madv;
3908
3909 /* if the object is no longer attached, discard its backing storage */
3910 if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages)
3911 i915_gem_object_truncate(obj);
3912
3913 args->retained = obj->mm.madv != __I915_MADV_PURGED;
3914 mutex_unlock(&obj->mm.lock);
3915
3916out:
3917 i915_gem_object_put(obj);
3918 return err;
3919}
3920
3921static void
3922frontbuffer_retire(struct i915_gem_active *active,
3923 struct drm_i915_gem_request *request)
3924{
3925 struct drm_i915_gem_object *obj =
3926 container_of(active, typeof(*obj), frontbuffer_write);
3927
3928 intel_fb_obj_flush(obj, true, ORIGIN_CS);
3929}
3930
3931void i915_gem_object_init(struct drm_i915_gem_object *obj,
3932 const struct drm_i915_gem_object_ops *ops)
3933{
3934 mutex_init(&obj->mm.lock);
3935
3936 INIT_LIST_HEAD(&obj->global_link);
3937 INIT_LIST_HEAD(&obj->userfault_link);
3938 INIT_LIST_HEAD(&obj->obj_exec_link);
3939 INIT_LIST_HEAD(&obj->vma_list);
3940 INIT_LIST_HEAD(&obj->batch_pool_link);
3941
3942 obj->ops = ops;
3943
3944 reservation_object_init(&obj->__builtin_resv);
3945 obj->resv = &obj->__builtin_resv;
3946
3947 obj->frontbuffer_ggtt_origin = ORIGIN_GTT;
3948 init_request_active(&obj->frontbuffer_write, frontbuffer_retire);
3949
3950 obj->mm.madv = I915_MADV_WILLNEED;
3951 INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN);
3952 mutex_init(&obj->mm.get_page.lock);
3953
3954 i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size);
3955}
3956
3957static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3958 .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
3959 I915_GEM_OBJECT_IS_SHRINKABLE,
3960 .get_pages = i915_gem_object_get_pages_gtt,
3961 .put_pages = i915_gem_object_put_pages_gtt,
3962};
3963
3964/* Note we don't consider signbits :| */
3965#define overflows_type(x, T) \
3966 (sizeof(x) > sizeof(T) && (x) >> (sizeof(T) * BITS_PER_BYTE))
3967
3968struct drm_i915_gem_object *
3969i915_gem_object_create(struct drm_device *dev, u64 size)
3970{
3971 struct drm_i915_private *dev_priv = to_i915(dev);
3972 struct drm_i915_gem_object *obj;
3973 struct address_space *mapping;
3974 gfp_t mask;
3975 int ret;
3976
3977 /* There is a prevalence of the assumption that we fit the object's
3978 * page count inside a 32bit _signed_ variable. Let's document this and
3979 * catch if we ever need to fix it. In the meantime, if you do spot
3980 * such a local variable, please consider fixing!
3981 */
3982 if (WARN_ON(size >> PAGE_SHIFT > INT_MAX))
3983 return ERR_PTR(-E2BIG);
3984
3985 if (overflows_type(size, obj->base.size))
3986 return ERR_PTR(-E2BIG);
3987
3988 obj = i915_gem_object_alloc(dev);
3989 if (obj == NULL)
3990 return ERR_PTR(-ENOMEM);
3991
3992 ret = drm_gem_object_init(dev, &obj->base, size);
3993 if (ret)
3994 goto fail;
3995
3996 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3997 if (IS_CRESTLINE(dev_priv) || IS_BROADWATER(dev_priv)) {
3998 /* 965gm cannot relocate objects above 4GiB. */
3999 mask &= ~__GFP_HIGHMEM;
4000 mask |= __GFP_DMA32;
4001 }
4002
4003 mapping = obj->base.filp->f_mapping;
4004 mapping_set_gfp_mask(mapping, mask);
4005
4006 i915_gem_object_init(obj, &i915_gem_object_ops);
4007
4008 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4009 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4010
4011 if (HAS_LLC(dev_priv)) {
4012 /* On some devices, we can have the GPU use the LLC (the CPU
4013 * cache) for about a 10% performance improvement
4014 * compared to uncached. Graphics requests other than
4015 * display scanout are coherent with the CPU in
4016 * accessing this cache. This means in this mode we
4017 * don't need to clflush on the CPU side, and on the
4018 * GPU side we only need to flush internal caches to
4019 * get data visible to the CPU.
4020 *
4021 * However, we maintain the display planes as UC, and so
4022 * need to rebind when first used as such.
4023 */
4024 obj->cache_level = I915_CACHE_LLC;
4025 } else
4026 obj->cache_level = I915_CACHE_NONE;
4027
4028 trace_i915_gem_object_create(obj);
4029
4030 return obj;
4031
4032fail:
4033 i915_gem_object_free(obj);
4034 return ERR_PTR(ret);
4035}
4036
4037static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4038{
4039 /* If we are the last user of the backing storage (be it shmemfs
4040 * pages or stolen etc), we know that the pages are going to be
4041 * immediately released. In this case, we can then skip copying
4042 * back the contents from the GPU.
4043 */
4044
4045 if (obj->mm.madv != I915_MADV_WILLNEED)
4046 return false;
4047
4048 if (obj->base.filp == NULL)
4049 return true;
4050
4051 /* At first glance, this looks racy, but then again so would be
4052 * userspace racing mmap against close. However, the first external
4053 * reference to the filp can only be obtained through the
4054 * i915_gem_mmap_ioctl() which safeguards us against the user
4055 * acquiring such a reference whilst we are in the middle of
4056 * freeing the object.
4057 */
4058 return atomic_long_read(&obj->base.filp->f_count) == 1;
4059}
4060
4061static void __i915_gem_free_objects(struct drm_i915_private *i915,
4062 struct llist_node *freed)
4063{
4064 struct drm_i915_gem_object *obj, *on;
4065
4066 mutex_lock(&i915->drm.struct_mutex);
4067 intel_runtime_pm_get(i915);
4068 llist_for_each_entry(obj, freed, freed) {
4069 struct i915_vma *vma, *vn;
4070
4071 trace_i915_gem_object_destroy(obj);
4072
4073 GEM_BUG_ON(i915_gem_object_is_active(obj));
4074 list_for_each_entry_safe(vma, vn,
4075 &obj->vma_list, obj_link) {
4076 GEM_BUG_ON(!i915_vma_is_ggtt(vma));
4077 GEM_BUG_ON(i915_vma_is_active(vma));
4078 vma->flags &= ~I915_VMA_PIN_MASK;
4079 i915_vma_close(vma);
4080 }
4081 GEM_BUG_ON(!list_empty(&obj->vma_list));
4082 GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree));
4083
4084 list_del(&obj->global_link);
4085 }
4086 intel_runtime_pm_put(i915);
4087 mutex_unlock(&i915->drm.struct_mutex);
4088
4089 llist_for_each_entry_safe(obj, on, freed, freed) {
4090 GEM_BUG_ON(obj->bind_count);
4091 GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));
4092
4093 if (obj->ops->release)
4094 obj->ops->release(obj);
4095
4096 if (WARN_ON(i915_gem_object_has_pinned_pages(obj)))
4097 atomic_set(&obj->mm.pages_pin_count, 0);
4098 __i915_gem_object_put_pages(obj, I915_MM_NORMAL);
4099 GEM_BUG_ON(obj->mm.pages);
4100
4101 if (obj->base.import_attach)
4102 drm_prime_gem_destroy(&obj->base, NULL);
4103
4104 reservation_object_fini(&obj->__builtin_resv);
4105 drm_gem_object_release(&obj->base);
4106 i915_gem_info_remove_obj(i915, obj->base.size);
4107
4108 kfree(obj->bit_17);
4109 i915_gem_object_free(obj);
4110 }
4111}
4112
4113static void i915_gem_flush_free_objects(struct drm_i915_private *i915)
4114{
4115 struct llist_node *freed;
4116
4117 freed = llist_del_all(&i915->mm.free_list);
4118 if (unlikely(freed))
4119 __i915_gem_free_objects(i915, freed);
4120}
4121
4122static void __i915_gem_free_work(struct work_struct *work)
4123{
4124 struct drm_i915_private *i915 =
4125 container_of(work, struct drm_i915_private, mm.free_work);
4126 struct llist_node *freed;
4127
4128 /* All file-owned VMA should have been released by this point through
4129 * i915_gem_close_object(), or earlier by i915_gem_context_close().
4130 * However, the object may also be bound into the global GTT (e.g.
4131 * older GPUs without per-process support, or for direct access through
4132 * the GTT either for the user or for scanout). Those VMA still need to
4133 * unbound now.
4134 */
4135
4136 while ((freed = llist_del_all(&i915->mm.free_list)))
4137 __i915_gem_free_objects(i915, freed);
4138}
4139
4140static void __i915_gem_free_object_rcu(struct rcu_head *head)
4141{
4142 struct drm_i915_gem_object *obj =
4143 container_of(head, typeof(*obj), rcu);
4144 struct drm_i915_private *i915 = to_i915(obj->base.dev);
4145
4146 /* We can't simply use call_rcu() from i915_gem_free_object()
4147 * as we need to block whilst unbinding, and the call_rcu
4148 * task may be called from softirq context. So we take a
4149 * detour through a worker.
4150 */
4151 if (llist_add(&obj->freed, &i915->mm.free_list))
4152 schedule_work(&i915->mm.free_work);
4153}
4154
4155void i915_gem_free_object(struct drm_gem_object *gem_obj)
4156{
4157 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4158
4159 if (obj->mm.quirked)
4160 __i915_gem_object_unpin_pages(obj);
4161
4162 if (discard_backing_storage(obj))
4163 obj->mm.madv = I915_MADV_DONTNEED;
4164
4165 /* Before we free the object, make sure any pure RCU-only
4166 * read-side critical sections are complete, e.g.
4167 * i915_gem_busy_ioctl(). For the corresponding synchronized
4168 * lookup see i915_gem_object_lookup_rcu().
4169 */
4170 call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
4171}
4172
4173void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj)
4174{
4175 lockdep_assert_held(&obj->base.dev->struct_mutex);
4176
4177 GEM_BUG_ON(i915_gem_object_has_active_reference(obj));
4178 if (i915_gem_object_is_active(obj))
4179 i915_gem_object_set_active_reference(obj);
4180 else
4181 i915_gem_object_put(obj);
4182}
4183
4184static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv)
4185{
4186 struct intel_engine_cs *engine;
4187 enum intel_engine_id id;
4188
4189 for_each_engine(engine, dev_priv, id)
4190 GEM_BUG_ON(engine->last_context != dev_priv->kernel_context);
4191}
4192
4193int i915_gem_suspend(struct drm_device *dev)
4194{
4195 struct drm_i915_private *dev_priv = to_i915(dev);
4196 int ret;
4197
4198 intel_suspend_gt_powersave(dev_priv);
4199
4200 mutex_lock(&dev->struct_mutex);
4201
4202 /* We have to flush all the executing contexts to main memory so
4203 * that they can saved in the hibernation image. To ensure the last
4204 * context image is coherent, we have to switch away from it. That
4205 * leaves the dev_priv->kernel_context still active when
4206 * we actually suspend, and its image in memory may not match the GPU
4207 * state. Fortunately, the kernel_context is disposable and we do
4208 * not rely on its state.
4209 */
4210 ret = i915_gem_switch_to_kernel_context(dev_priv);
4211 if (ret)
4212 goto err;
4213
4214 ret = i915_gem_wait_for_idle(dev_priv,
4215 I915_WAIT_INTERRUPTIBLE |
4216 I915_WAIT_LOCKED);
4217 if (ret)
4218 goto err;
4219
4220 i915_gem_retire_requests(dev_priv);
4221 GEM_BUG_ON(dev_priv->gt.active_requests);
4222
4223 assert_kernel_context_is_current(dev_priv);
4224 i915_gem_context_lost(dev_priv);
4225 mutex_unlock(&dev->struct_mutex);
4226
4227 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4228 cancel_delayed_work_sync(&dev_priv->gt.retire_work);
4229 flush_delayed_work(&dev_priv->gt.idle_work);
4230 flush_work(&dev_priv->mm.free_work);
4231
4232 /* Assert that we sucessfully flushed all the work and
4233 * reset the GPU back to its idle, low power state.
4234 */
4235 WARN_ON(dev_priv->gt.awake);
4236 WARN_ON(!intel_execlists_idle(dev_priv));
4237
4238 /*
4239 * Neither the BIOS, ourselves or any other kernel
4240 * expects the system to be in execlists mode on startup,
4241 * so we need to reset the GPU back to legacy mode. And the only
4242 * known way to disable logical contexts is through a GPU reset.
4243 *
4244 * So in order to leave the system in a known default configuration,
4245 * always reset the GPU upon unload and suspend. Afterwards we then
4246 * clean up the GEM state tracking, flushing off the requests and
4247 * leaving the system in a known idle state.
4248 *
4249 * Note that is of the upmost importance that the GPU is idle and
4250 * all stray writes are flushed *before* we dismantle the backing
4251 * storage for the pinned objects.
4252 *
4253 * However, since we are uncertain that resetting the GPU on older
4254 * machines is a good idea, we don't - just in case it leaves the
4255 * machine in an unusable condition.
4256 */
4257 if (HAS_HW_CONTEXTS(dev_priv)) {
4258 int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
4259 WARN_ON(reset && reset != -ENODEV);
4260 }
4261
4262 return 0;
4263
4264err:
4265 mutex_unlock(&dev->struct_mutex);
4266 return ret;
4267}
4268
4269void i915_gem_resume(struct drm_device *dev)
4270{
4271 struct drm_i915_private *dev_priv = to_i915(dev);
4272
4273 WARN_ON(dev_priv->gt.awake);
4274
4275 mutex_lock(&dev->struct_mutex);
4276 i915_gem_restore_gtt_mappings(dev_priv);
4277
4278 /* As we didn't flush the kernel context before suspend, we cannot
4279 * guarantee that the context image is complete. So let's just reset
4280 * it and start again.
4281 */
4282 dev_priv->gt.resume(dev_priv);
4283
4284 mutex_unlock(&dev->struct_mutex);
4285}
4286
4287void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
4288{
4289 if (INTEL_GEN(dev_priv) < 5 ||
4290 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4291 return;
4292
4293 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4294 DISP_TILE_SURFACE_SWIZZLING);
4295
4296 if (IS_GEN5(dev_priv))
4297 return;
4298
4299 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4300 if (IS_GEN6(dev_priv))
4301 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4302 else if (IS_GEN7(dev_priv))
4303 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4304 else if (IS_GEN8(dev_priv))
4305 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4306 else
4307 BUG();
4308}
4309
4310static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
4311{
4312 I915_WRITE(RING_CTL(base), 0);
4313 I915_WRITE(RING_HEAD(base), 0);
4314 I915_WRITE(RING_TAIL(base), 0);
4315 I915_WRITE(RING_START(base), 0);
4316}
4317
4318static void init_unused_rings(struct drm_i915_private *dev_priv)
4319{
4320 if (IS_I830(dev_priv)) {
4321 init_unused_ring(dev_priv, PRB1_BASE);
4322 init_unused_ring(dev_priv, SRB0_BASE);
4323 init_unused_ring(dev_priv, SRB1_BASE);
4324 init_unused_ring(dev_priv, SRB2_BASE);
4325 init_unused_ring(dev_priv, SRB3_BASE);
4326 } else if (IS_GEN2(dev_priv)) {
4327 init_unused_ring(dev_priv, SRB0_BASE);
4328 init_unused_ring(dev_priv, SRB1_BASE);
4329 } else if (IS_GEN3(dev_priv)) {
4330 init_unused_ring(dev_priv, PRB1_BASE);
4331 init_unused_ring(dev_priv, PRB2_BASE);
4332 }
4333}
4334
4335int
4336i915_gem_init_hw(struct drm_device *dev)
4337{
4338 struct drm_i915_private *dev_priv = to_i915(dev);
4339 struct intel_engine_cs *engine;
4340 enum intel_engine_id id;
4341 int ret;
4342
4343 dev_priv->gt.last_init_time = ktime_get();
4344
4345 /* Double layer security blanket, see i915_gem_init() */
4346 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4347
4348 if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
4349 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4350
4351 if (IS_HASWELL(dev_priv))
4352 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
4353 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4354
4355 if (HAS_PCH_NOP(dev_priv)) {
4356 if (IS_IVYBRIDGE(dev_priv)) {
4357 u32 temp = I915_READ(GEN7_MSG_CTL);
4358 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4359 I915_WRITE(GEN7_MSG_CTL, temp);
4360 } else if (INTEL_GEN(dev_priv) >= 7) {
4361 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4362 temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4363 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4364 }
4365 }
4366
4367 i915_gem_init_swizzling(dev_priv);
4368
4369 /*
4370 * At least 830 can leave some of the unused rings
4371 * "active" (ie. head != tail) after resume which
4372 * will prevent c3 entry. Makes sure all unused rings
4373 * are totally idle.
4374 */
4375 init_unused_rings(dev_priv);
4376
4377 BUG_ON(!dev_priv->kernel_context);
4378
4379 ret = i915_ppgtt_init_hw(dev_priv);
4380 if (ret) {
4381 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
4382 goto out;
4383 }
4384
4385 /* Need to do basic initialisation of all rings first: */
4386 for_each_engine(engine, dev_priv, id) {
4387 ret = engine->init_hw(engine);
4388 if (ret)
4389 goto out;
4390 }
4391
4392 intel_mocs_init_l3cc_table(dev);
4393
4394 /* We can't enable contexts until all firmware is loaded */
4395 ret = intel_guc_setup(dev);
4396 if (ret)
4397 goto out;
4398
4399out:
4400 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4401 return ret;
4402}
4403
4404bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value)
4405{
4406 if (INTEL_INFO(dev_priv)->gen < 6)
4407 return false;
4408
4409 /* TODO: make semaphores and Execlists play nicely together */
4410 if (i915.enable_execlists)
4411 return false;
4412
4413 if (value >= 0)
4414 return value;
4415
4416#ifdef CONFIG_INTEL_IOMMU
4417 /* Enable semaphores on SNB when IO remapping is off */
4418 if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped)
4419 return false;
4420#endif
4421
4422 return true;
4423}
4424
4425int i915_gem_init(struct drm_device *dev)
4426{
4427 struct drm_i915_private *dev_priv = to_i915(dev);
4428 int ret;
4429
4430 mutex_lock(&dev->struct_mutex);
4431
4432 if (!i915.enable_execlists) {
4433 dev_priv->gt.resume = intel_legacy_submission_resume;
4434 dev_priv->gt.cleanup_engine = intel_engine_cleanup;
4435 } else {
4436 dev_priv->gt.resume = intel_lr_context_resume;
4437 dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
4438 }
4439
4440 /* This is just a security blanket to placate dragons.
4441 * On some systems, we very sporadically observe that the first TLBs
4442 * used by the CS may be stale, despite us poking the TLB reset. If
4443 * we hold the forcewake during initialisation these problems
4444 * just magically go away.
4445 */
4446 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4447
4448 i915_gem_init_userptr(dev_priv);
4449
4450 ret = i915_gem_init_ggtt(dev_priv);
4451 if (ret)
4452 goto out_unlock;
4453
4454 ret = i915_gem_context_init(dev);
4455 if (ret)
4456 goto out_unlock;
4457
4458 ret = intel_engines_init(dev);
4459 if (ret)
4460 goto out_unlock;
4461
4462 ret = i915_gem_init_hw(dev);
4463 if (ret == -EIO) {
4464 /* Allow engine initialisation to fail by marking the GPU as
4465 * wedged. But we only want to do this where the GPU is angry,
4466 * for all other failure, such as an allocation failure, bail.
4467 */
4468 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4469 i915_gem_set_wedged(dev_priv);
4470 ret = 0;
4471 }
4472
4473out_unlock:
4474 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4475 mutex_unlock(&dev->struct_mutex);
4476
4477 return ret;
4478}
4479
4480void
4481i915_gem_cleanup_engines(struct drm_device *dev)
4482{
4483 struct drm_i915_private *dev_priv = to_i915(dev);
4484 struct intel_engine_cs *engine;
4485 enum intel_engine_id id;
4486
4487 for_each_engine(engine, dev_priv, id)
4488 dev_priv->gt.cleanup_engine(engine);
4489}
4490
4491void
4492i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
4493{
4494 int i;
4495
4496 if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
4497 !IS_CHERRYVIEW(dev_priv))
4498 dev_priv->num_fence_regs = 32;
4499 else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) ||
4500 IS_I945GM(dev_priv) || IS_G33(dev_priv))
4501 dev_priv->num_fence_regs = 16;
4502 else
4503 dev_priv->num_fence_regs = 8;
4504
4505 if (intel_vgpu_active(dev_priv))
4506 dev_priv->num_fence_regs =
4507 I915_READ(vgtif_reg(avail_rs.fence_num));
4508
4509 /* Initialize fence registers to zero */
4510 for (i = 0; i < dev_priv->num_fence_regs; i++) {
4511 struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i];
4512
4513 fence->i915 = dev_priv;
4514 fence->id = i;
4515 list_add_tail(&fence->link, &dev_priv->mm.fence_list);
4516 }
4517 i915_gem_restore_fences(dev_priv);
4518
4519 i915_gem_detect_bit_6_swizzle(dev_priv);
4520}
4521
4522int
4523i915_gem_load_init(struct drm_device *dev)
4524{
4525 struct drm_i915_private *dev_priv = to_i915(dev);
4526 int err = -ENOMEM;
4527
4528 dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN);
4529 if (!dev_priv->objects)
4530 goto err_out;
4531
4532 dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN);
4533 if (!dev_priv->vmas)
4534 goto err_objects;
4535
4536 dev_priv->requests = KMEM_CACHE(drm_i915_gem_request,
4537 SLAB_HWCACHE_ALIGN |
4538 SLAB_RECLAIM_ACCOUNT |
4539 SLAB_DESTROY_BY_RCU);
4540 if (!dev_priv->requests)
4541 goto err_vmas;
4542
4543 dev_priv->dependencies = KMEM_CACHE(i915_dependency,
4544 SLAB_HWCACHE_ALIGN |
4545 SLAB_RECLAIM_ACCOUNT);
4546 if (!dev_priv->dependencies)
4547 goto err_requests;
4548
4549 mutex_lock(&dev_priv->drm.struct_mutex);
4550 INIT_LIST_HEAD(&dev_priv->gt.timelines);
4551 err = i915_gem_timeline_init__global(dev_priv);
4552 mutex_unlock(&dev_priv->drm.struct_mutex);
4553 if (err)
4554 goto err_dependencies;
4555
4556 INIT_LIST_HEAD(&dev_priv->context_list);
4557 INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work);
4558 init_llist_head(&dev_priv->mm.free_list);
4559 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4560 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4561 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4562 INIT_LIST_HEAD(&dev_priv->mm.userfault_list);
4563 INIT_DELAYED_WORK(&dev_priv->gt.retire_work,
4564 i915_gem_retire_work_handler);
4565 INIT_DELAYED_WORK(&dev_priv->gt.idle_work,
4566 i915_gem_idle_work_handler);
4567 init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
4568 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4569
4570 init_waitqueue_head(&dev_priv->pending_flip_queue);
4571
4572 dev_priv->mm.interruptible = true;
4573
4574 atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0);
4575
4576 spin_lock_init(&dev_priv->fb_tracking.lock);
4577
4578 return 0;
4579
4580err_dependencies:
4581 kmem_cache_destroy(dev_priv->dependencies);
4582err_requests:
4583 kmem_cache_destroy(dev_priv->requests);
4584err_vmas:
4585 kmem_cache_destroy(dev_priv->vmas);
4586err_objects:
4587 kmem_cache_destroy(dev_priv->objects);
4588err_out:
4589 return err;
4590}
4591
4592void i915_gem_load_cleanup(struct drm_device *dev)
4593{
4594 struct drm_i915_private *dev_priv = to_i915(dev);
4595
4596 WARN_ON(!llist_empty(&dev_priv->mm.free_list));
4597
4598 mutex_lock(&dev_priv->drm.struct_mutex);
4599 i915_gem_timeline_fini(&dev_priv->gt.global_timeline);
4600 WARN_ON(!list_empty(&dev_priv->gt.timelines));
4601 mutex_unlock(&dev_priv->drm.struct_mutex);
4602
4603 kmem_cache_destroy(dev_priv->dependencies);
4604 kmem_cache_destroy(dev_priv->requests);
4605 kmem_cache_destroy(dev_priv->vmas);
4606 kmem_cache_destroy(dev_priv->objects);
4607
4608 /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */
4609 rcu_barrier();
4610}
4611
4612int i915_gem_freeze(struct drm_i915_private *dev_priv)
4613{
4614 intel_runtime_pm_get(dev_priv);
4615
4616 mutex_lock(&dev_priv->drm.struct_mutex);
4617 i915_gem_shrink_all(dev_priv);
4618 mutex_unlock(&dev_priv->drm.struct_mutex);
4619
4620 intel_runtime_pm_put(dev_priv);
4621
4622 return 0;
4623}
4624
4625int i915_gem_freeze_late(struct drm_i915_private *dev_priv)
4626{
4627 struct drm_i915_gem_object *obj;
4628 struct list_head *phases[] = {
4629 &dev_priv->mm.unbound_list,
4630 &dev_priv->mm.bound_list,
4631 NULL
4632 }, **p;
4633
4634 /* Called just before we write the hibernation image.
4635 *
4636 * We need to update the domain tracking to reflect that the CPU
4637 * will be accessing all the pages to create and restore from the
4638 * hibernation, and so upon restoration those pages will be in the
4639 * CPU domain.
4640 *
4641 * To make sure the hibernation image contains the latest state,
4642 * we update that state just before writing out the image.
4643 *
4644 * To try and reduce the hibernation image, we manually shrink
4645 * the objects as well.
4646 */
4647
4648 mutex_lock(&dev_priv->drm.struct_mutex);
4649 i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND);
4650
4651 for (p = phases; *p; p++) {
4652 list_for_each_entry(obj, *p, global_link) {
4653 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4654 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4655 }
4656 }
4657 mutex_unlock(&dev_priv->drm.struct_mutex);
4658
4659 return 0;
4660}
4661
4662void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4663{
4664 struct drm_i915_file_private *file_priv = file->driver_priv;
4665 struct drm_i915_gem_request *request;
4666
4667 /* Clean up our request list when the client is going away, so that
4668 * later retire_requests won't dereference our soon-to-be-gone
4669 * file_priv.
4670 */
4671 spin_lock(&file_priv->mm.lock);
4672 list_for_each_entry(request, &file_priv->mm.request_list, client_list)
4673 request->file_priv = NULL;
4674 spin_unlock(&file_priv->mm.lock);
4675
4676 if (!list_empty(&file_priv->rps.link)) {
4677 spin_lock(&to_i915(dev)->rps.client_lock);
4678 list_del(&file_priv->rps.link);
4679 spin_unlock(&to_i915(dev)->rps.client_lock);
4680 }
4681}
4682
4683int i915_gem_open(struct drm_device *dev, struct drm_file *file)
4684{
4685 struct drm_i915_file_private *file_priv;
4686 int ret;
4687
4688 DRM_DEBUG("\n");
4689
4690 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
4691 if (!file_priv)
4692 return -ENOMEM;
4693
4694 file->driver_priv = file_priv;
4695 file_priv->dev_priv = to_i915(dev);
4696 file_priv->file = file;
4697 INIT_LIST_HEAD(&file_priv->rps.link);
4698
4699 spin_lock_init(&file_priv->mm.lock);
4700 INIT_LIST_HEAD(&file_priv->mm.request_list);
4701
4702 file_priv->bsd_engine = -1;
4703
4704 ret = i915_gem_context_open(dev, file);
4705 if (ret)
4706 kfree(file_priv);
4707
4708 return ret;
4709}
4710
4711/**
4712 * i915_gem_track_fb - update frontbuffer tracking
4713 * @old: current GEM buffer for the frontbuffer slots
4714 * @new: new GEM buffer for the frontbuffer slots
4715 * @frontbuffer_bits: bitmask of frontbuffer slots
4716 *
4717 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
4718 * from @old and setting them in @new. Both @old and @new can be NULL.
4719 */
4720void i915_gem_track_fb(struct drm_i915_gem_object *old,
4721 struct drm_i915_gem_object *new,
4722 unsigned frontbuffer_bits)
4723{
4724 /* Control of individual bits within the mask are guarded by
4725 * the owning plane->mutex, i.e. we can never see concurrent
4726 * manipulation of individual bits. But since the bitfield as a whole
4727 * is updated using RMW, we need to use atomics in order to update
4728 * the bits.
4729 */
4730 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES >
4731 sizeof(atomic_t) * BITS_PER_BYTE);
4732
4733 if (old) {
4734 WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits));
4735 atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits);
4736 }
4737
4738 if (new) {
4739 WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits);
4740 atomic_or(frontbuffer_bits, &new->frontbuffer_bits);
4741 }
4742}
4743
4744/* Allocate a new GEM object and fill it with the supplied data */
4745struct drm_i915_gem_object *
4746i915_gem_object_create_from_data(struct drm_device *dev,
4747 const void *data, size_t size)
4748{
4749 struct drm_i915_gem_object *obj;
4750 struct sg_table *sg;
4751 size_t bytes;
4752 int ret;
4753
4754 obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE));
4755 if (IS_ERR(obj))
4756 return obj;
4757
4758 ret = i915_gem_object_set_to_cpu_domain(obj, true);
4759 if (ret)
4760 goto fail;
4761
4762 ret = i915_gem_object_pin_pages(obj);
4763 if (ret)
4764 goto fail;
4765
4766 sg = obj->mm.pages;
4767 bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size);
4768 obj->mm.dirty = true; /* Backing store is now out of date */
4769 i915_gem_object_unpin_pages(obj);
4770
4771 if (WARN_ON(bytes != size)) {
4772 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size);
4773 ret = -EFAULT;
4774 goto fail;
4775 }
4776
4777 return obj;
4778
4779fail:
4780 i915_gem_object_put(obj);
4781 return ERR_PTR(ret);
4782}
4783
4784struct scatterlist *
4785i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
4786 unsigned int n,
4787 unsigned int *offset)
4788{
4789 struct i915_gem_object_page_iter *iter = &obj->mm.get_page;
4790 struct scatterlist *sg;
4791 unsigned int idx, count;
4792
4793 might_sleep();
4794 GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT);
4795 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
4796
4797 /* As we iterate forward through the sg, we record each entry in a
4798 * radixtree for quick repeated (backwards) lookups. If we have seen
4799 * this index previously, we will have an entry for it.
4800 *
4801 * Initial lookup is O(N), but this is amortized to O(1) for
4802 * sequential page access (where each new request is consecutive
4803 * to the previous one). Repeated lookups are O(lg(obj->base.size)),
4804 * i.e. O(1) with a large constant!
4805 */
4806 if (n < READ_ONCE(iter->sg_idx))
4807 goto lookup;
4808
4809 mutex_lock(&iter->lock);
4810
4811 /* We prefer to reuse the last sg so that repeated lookup of this
4812 * (or the subsequent) sg are fast - comparing against the last
4813 * sg is faster than going through the radixtree.
4814 */
4815
4816 sg = iter->sg_pos;
4817 idx = iter->sg_idx;
4818 count = __sg_page_count(sg);
4819
4820 while (idx + count <= n) {
4821 unsigned long exception, i;
4822 int ret;
4823
4824 /* If we cannot allocate and insert this entry, or the
4825 * individual pages from this range, cancel updating the
4826 * sg_idx so that on this lookup we are forced to linearly
4827 * scan onwards, but on future lookups we will try the
4828 * insertion again (in which case we need to be careful of
4829 * the error return reporting that we have already inserted
4830 * this index).
4831 */
4832 ret = radix_tree_insert(&iter->radix, idx, sg);
4833 if (ret && ret != -EEXIST)
4834 goto scan;
4835
4836 exception =
4837 RADIX_TREE_EXCEPTIONAL_ENTRY |
4838 idx << RADIX_TREE_EXCEPTIONAL_SHIFT;
4839 for (i = 1; i < count; i++) {
4840 ret = radix_tree_insert(&iter->radix, idx + i,
4841 (void *)exception);
4842 if (ret && ret != -EEXIST)
4843 goto scan;
4844 }
4845
4846 idx += count;
4847 sg = ____sg_next(sg);
4848 count = __sg_page_count(sg);
4849 }
4850
4851scan:
4852 iter->sg_pos = sg;
4853 iter->sg_idx = idx;
4854
4855 mutex_unlock(&iter->lock);
4856
4857 if (unlikely(n < idx)) /* insertion completed by another thread */
4858 goto lookup;
4859
4860 /* In case we failed to insert the entry into the radixtree, we need
4861 * to look beyond the current sg.
4862 */
4863 while (idx + count <= n) {
4864 idx += count;
4865 sg = ____sg_next(sg);
4866 count = __sg_page_count(sg);
4867 }
4868
4869 *offset = n - idx;
4870 return sg;
4871
4872lookup:
4873 rcu_read_lock();
4874
4875 sg = radix_tree_lookup(&iter->radix, n);
4876 GEM_BUG_ON(!sg);
4877
4878 /* If this index is in the middle of multi-page sg entry,
4879 * the radixtree will contain an exceptional entry that points
4880 * to the start of that range. We will return the pointer to
4881 * the base page and the offset of this page within the
4882 * sg entry's range.
4883 */
4884 *offset = 0;
4885 if (unlikely(radix_tree_exception(sg))) {
4886 unsigned long base =
4887 (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT;
4888
4889 sg = radix_tree_lookup(&iter->radix, base);
4890 GEM_BUG_ON(!sg);
4891
4892 *offset = n - base;
4893 }
4894
4895 rcu_read_unlock();
4896
4897 return sg;
4898}
4899
4900struct page *
4901i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n)
4902{
4903 struct scatterlist *sg;
4904 unsigned int offset;
4905
4906 GEM_BUG_ON(!i915_gem_object_has_struct_page(obj));
4907
4908 sg = i915_gem_object_get_sg(obj, n, &offset);
4909 return nth_page(sg_page(sg), offset);
4910}
4911
4912/* Like i915_gem_object_get_page(), but mark the returned page dirty */
4913struct page *
4914i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
4915 unsigned int n)
4916{
4917 struct page *page;
4918
4919 page = i915_gem_object_get_page(obj, n);
4920 if (!obj->mm.dirty)
4921 set_page_dirty(page);
4922
4923 return page;
4924}
4925
4926dma_addr_t
4927i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
4928 unsigned long n)
4929{
4930 struct scatterlist *sg;
4931 unsigned int offset;
4932
4933 sg = i915_gem_object_get_sg(obj, n, &offset);
4934 return sg_dma_address(sg) + (offset << PAGE_SHIFT);
4935}