Loading...
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27
28#include <drm/drm_cache.h>
29#include "amdgpu.h"
30#include "gmc_v8_0.h"
31#include "amdgpu_ucode.h"
32#include "amdgpu_amdkfd.h"
33#include "amdgpu_gem.h"
34
35#include "gmc/gmc_8_1_d.h"
36#include "gmc/gmc_8_1_sh_mask.h"
37
38#include "bif/bif_5_0_d.h"
39#include "bif/bif_5_0_sh_mask.h"
40
41#include "oss/oss_3_0_d.h"
42#include "oss/oss_3_0_sh_mask.h"
43
44#include "dce/dce_10_0_d.h"
45#include "dce/dce_10_0_sh_mask.h"
46
47#include "vid.h"
48#include "vi.h"
49
50#include "amdgpu_atombios.h"
51
52#include "ivsrcid/ivsrcid_vislands30.h"
53
54static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev);
55static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
56static int gmc_v8_0_wait_for_idle(void *handle);
57
58MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
59MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
60MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
61MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");
62MODULE_FIRMWARE("amdgpu/polaris12_32_mc.bin");
63MODULE_FIRMWARE("amdgpu/polaris11_k_mc.bin");
64MODULE_FIRMWARE("amdgpu/polaris10_k_mc.bin");
65MODULE_FIRMWARE("amdgpu/polaris12_k_mc.bin");
66
67static const u32 golden_settings_tonga_a11[] = {
68 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
69 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
70 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
71 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
72 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
73 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
74 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
75};
76
77static const u32 tonga_mgcg_cgcg_init[] = {
78 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
79};
80
81static const u32 golden_settings_fiji_a10[] = {
82 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
83 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
84 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
85 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
86};
87
88static const u32 fiji_mgcg_cgcg_init[] = {
89 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
90};
91
92static const u32 golden_settings_polaris11_a11[] = {
93 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
94 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
95 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
96 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
97};
98
99static const u32 golden_settings_polaris10_a11[] = {
100 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
101 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
102 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
103 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
104 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
105};
106
107static const u32 cz_mgcg_cgcg_init[] = {
108 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
109};
110
111static const u32 stoney_mgcg_cgcg_init[] = {
112 mmATC_MISC_CG, 0xffffffff, 0x000c0200,
113 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
114};
115
116static const u32 golden_settings_stoney_common[] = {
117 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
118 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
119};
120
121static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
122{
123 switch (adev->asic_type) {
124 case CHIP_FIJI:
125 amdgpu_device_program_register_sequence(adev,
126 fiji_mgcg_cgcg_init,
127 ARRAY_SIZE(fiji_mgcg_cgcg_init));
128 amdgpu_device_program_register_sequence(adev,
129 golden_settings_fiji_a10,
130 ARRAY_SIZE(golden_settings_fiji_a10));
131 break;
132 case CHIP_TONGA:
133 amdgpu_device_program_register_sequence(adev,
134 tonga_mgcg_cgcg_init,
135 ARRAY_SIZE(tonga_mgcg_cgcg_init));
136 amdgpu_device_program_register_sequence(adev,
137 golden_settings_tonga_a11,
138 ARRAY_SIZE(golden_settings_tonga_a11));
139 break;
140 case CHIP_POLARIS11:
141 case CHIP_POLARIS12:
142 case CHIP_VEGAM:
143 amdgpu_device_program_register_sequence(adev,
144 golden_settings_polaris11_a11,
145 ARRAY_SIZE(golden_settings_polaris11_a11));
146 break;
147 case CHIP_POLARIS10:
148 amdgpu_device_program_register_sequence(adev,
149 golden_settings_polaris10_a11,
150 ARRAY_SIZE(golden_settings_polaris10_a11));
151 break;
152 case CHIP_CARRIZO:
153 amdgpu_device_program_register_sequence(adev,
154 cz_mgcg_cgcg_init,
155 ARRAY_SIZE(cz_mgcg_cgcg_init));
156 break;
157 case CHIP_STONEY:
158 amdgpu_device_program_register_sequence(adev,
159 stoney_mgcg_cgcg_init,
160 ARRAY_SIZE(stoney_mgcg_cgcg_init));
161 amdgpu_device_program_register_sequence(adev,
162 golden_settings_stoney_common,
163 ARRAY_SIZE(golden_settings_stoney_common));
164 break;
165 default:
166 break;
167 }
168}
169
170static void gmc_v8_0_mc_stop(struct amdgpu_device *adev)
171{
172 u32 blackout;
173
174 gmc_v8_0_wait_for_idle(adev);
175
176 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
177 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
178 /* Block CPU access */
179 WREG32(mmBIF_FB_EN, 0);
180 /* blackout the MC */
181 blackout = REG_SET_FIELD(blackout,
182 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
183 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
184 }
185 /* wait for the MC to settle */
186 udelay(100);
187}
188
189static void gmc_v8_0_mc_resume(struct amdgpu_device *adev)
190{
191 u32 tmp;
192
193 /* unblackout the MC */
194 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
195 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
196 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
197 /* allow CPU access */
198 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
199 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
200 WREG32(mmBIF_FB_EN, tmp);
201}
202
203/**
204 * gmc_v8_0_init_microcode - load ucode images from disk
205 *
206 * @adev: amdgpu_device pointer
207 *
208 * Use the firmware interface to load the ucode images into
209 * the driver (not loaded into hw).
210 * Returns 0 on success, error on failure.
211 */
212static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
213{
214 const char *chip_name;
215 char fw_name[30];
216 int err;
217
218 DRM_DEBUG("\n");
219
220 switch (adev->asic_type) {
221 case CHIP_TONGA:
222 chip_name = "tonga";
223 break;
224 case CHIP_POLARIS11:
225 if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
226 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision))
227 chip_name = "polaris11_k";
228 else
229 chip_name = "polaris11";
230 break;
231 case CHIP_POLARIS10:
232 if (ASICID_IS_P30(adev->pdev->device, adev->pdev->revision))
233 chip_name = "polaris10_k";
234 else
235 chip_name = "polaris10";
236 break;
237 case CHIP_POLARIS12:
238 if (ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) {
239 chip_name = "polaris12_k";
240 } else {
241 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, ixMC_IO_DEBUG_UP_159);
242 /* Polaris12 32bit ASIC needs a special MC firmware */
243 if (RREG32(mmMC_SEQ_IO_DEBUG_DATA) == 0x05b4dc40)
244 chip_name = "polaris12_32";
245 else
246 chip_name = "polaris12";
247 }
248 break;
249 case CHIP_FIJI:
250 case CHIP_CARRIZO:
251 case CHIP_STONEY:
252 case CHIP_VEGAM:
253 return 0;
254 default:
255 return -EINVAL;
256 }
257
258 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
259 err = amdgpu_ucode_request(adev, &adev->gmc.fw, fw_name);
260 if (err) {
261 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);
262 amdgpu_ucode_release(&adev->gmc.fw);
263 }
264 return err;
265}
266
267/**
268 * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw
269 *
270 * @adev: amdgpu_device pointer
271 *
272 * Load the GDDR MC ucode into the hw (VI).
273 * Returns 0 on success, error on failure.
274 */
275static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
276{
277 const struct mc_firmware_header_v1_0 *hdr;
278 const __le32 *fw_data = NULL;
279 const __le32 *io_mc_regs = NULL;
280 u32 running;
281 int i, ucode_size, regs_size;
282
283 /* Skip MC ucode loading on SR-IOV capable boards.
284 * vbios does this for us in asic_init in that case.
285 * Skip MC ucode loading on VF, because hypervisor will do that
286 * for this adaptor.
287 */
288 if (amdgpu_sriov_bios(adev))
289 return 0;
290
291 if (!adev->gmc.fw)
292 return -EINVAL;
293
294 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
295 amdgpu_ucode_print_mc_hdr(&hdr->header);
296
297 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
298 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
299 io_mc_regs = (const __le32 *)
300 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
301 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
302 fw_data = (const __le32 *)
303 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
304
305 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
306
307 if (running == 0) {
308 /* reset the engine and set to writable */
309 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
310 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
311
312 /* load mc io regs */
313 for (i = 0; i < regs_size; i++) {
314 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
315 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
316 }
317 /* load the MC ucode */
318 for (i = 0; i < ucode_size; i++)
319 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
320
321 /* put the engine back into the active state */
322 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
323 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
324 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
325
326 /* wait for training to complete */
327 for (i = 0; i < adev->usec_timeout; i++) {
328 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
329 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
330 break;
331 udelay(1);
332 }
333 for (i = 0; i < adev->usec_timeout; i++) {
334 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
335 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
336 break;
337 udelay(1);
338 }
339 }
340
341 return 0;
342}
343
344static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
345{
346 const struct mc_firmware_header_v1_0 *hdr;
347 const __le32 *fw_data = NULL;
348 const __le32 *io_mc_regs = NULL;
349 u32 data;
350 int i, ucode_size, regs_size;
351
352 /* Skip MC ucode loading on SR-IOV capable boards.
353 * vbios does this for us in asic_init in that case.
354 * Skip MC ucode loading on VF, because hypervisor will do that
355 * for this adaptor.
356 */
357 if (amdgpu_sriov_bios(adev))
358 return 0;
359
360 if (!adev->gmc.fw)
361 return -EINVAL;
362
363 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
364 amdgpu_ucode_print_mc_hdr(&hdr->header);
365
366 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
367 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
368 io_mc_regs = (const __le32 *)
369 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
370 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
371 fw_data = (const __le32 *)
372 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
373
374 data = RREG32(mmMC_SEQ_MISC0);
375 data &= ~(0x40);
376 WREG32(mmMC_SEQ_MISC0, data);
377
378 /* load mc io regs */
379 for (i = 0; i < regs_size; i++) {
380 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
381 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
382 }
383
384 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
385 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
386
387 /* load the MC ucode */
388 for (i = 0; i < ucode_size; i++)
389 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
390
391 /* put the engine back into the active state */
392 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
393 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
394 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
395
396 /* wait for training to complete */
397 for (i = 0; i < adev->usec_timeout; i++) {
398 data = RREG32(mmMC_SEQ_MISC0);
399 if (data & 0x80)
400 break;
401 udelay(1);
402 }
403
404 return 0;
405}
406
407static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
408 struct amdgpu_gmc *mc)
409{
410 u64 base = 0;
411
412 if (!amdgpu_sriov_vf(adev))
413 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
414 base <<= 24;
415
416 amdgpu_gmc_set_agp_default(adev, mc);
417 amdgpu_gmc_vram_location(adev, mc, base);
418 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT);
419}
420
421/**
422 * gmc_v8_0_mc_program - program the GPU memory controller
423 *
424 * @adev: amdgpu_device pointer
425 *
426 * Set the location of vram, gart, and AGP in the GPU's
427 * physical address space (VI).
428 */
429static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
430{
431 u32 tmp;
432 int i, j;
433
434 /* Initialize HDP */
435 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
436 WREG32((0xb05 + j), 0x00000000);
437 WREG32((0xb06 + j), 0x00000000);
438 WREG32((0xb07 + j), 0x00000000);
439 WREG32((0xb08 + j), 0x00000000);
440 WREG32((0xb09 + j), 0x00000000);
441 }
442 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
443
444 if (gmc_v8_0_wait_for_idle((void *)adev))
445 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
446
447 if (adev->mode_info.num_crtc) {
448 /* Lockout access through VGA aperture*/
449 tmp = RREG32(mmVGA_HDP_CONTROL);
450 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
451 WREG32(mmVGA_HDP_CONTROL, tmp);
452
453 /* disable VGA render */
454 tmp = RREG32(mmVGA_RENDER_CONTROL);
455 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
456 WREG32(mmVGA_RENDER_CONTROL, tmp);
457 }
458 /* Update configuration */
459 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
460 adev->gmc.vram_start >> 12);
461 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
462 adev->gmc.vram_end >> 12);
463 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
464 adev->mem_scratch.gpu_addr >> 12);
465
466 if (amdgpu_sriov_vf(adev)) {
467 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;
468 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF);
469 WREG32(mmMC_VM_FB_LOCATION, tmp);
470 /* XXX double check these! */
471 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
472 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
473 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
474 }
475
476 WREG32(mmMC_VM_AGP_BASE, 0);
477 WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22);
478 WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22);
479 if (gmc_v8_0_wait_for_idle((void *)adev))
480 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
481
482 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
483
484 tmp = RREG32(mmHDP_MISC_CNTL);
485 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
486 WREG32(mmHDP_MISC_CNTL, tmp);
487
488 tmp = RREG32(mmHDP_HOST_PATH_CNTL);
489 WREG32(mmHDP_HOST_PATH_CNTL, tmp);
490}
491
492/**
493 * gmc_v8_0_mc_init - initialize the memory controller driver params
494 *
495 * @adev: amdgpu_device pointer
496 *
497 * Look up the amount of vram, vram width, and decide how to place
498 * vram and gart within the GPU's physical address space (VI).
499 * Returns 0 for success.
500 */
501static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
502{
503 int r;
504 u32 tmp;
505
506 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
507 if (!adev->gmc.vram_width) {
508 int chansize, numchan;
509
510 /* Get VRAM informations */
511 tmp = RREG32(mmMC_ARB_RAMCFG);
512 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE))
513 chansize = 64;
514 else
515 chansize = 32;
516
517 tmp = RREG32(mmMC_SHARED_CHMAP);
518 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
519 case 0:
520 default:
521 numchan = 1;
522 break;
523 case 1:
524 numchan = 2;
525 break;
526 case 2:
527 numchan = 4;
528 break;
529 case 3:
530 numchan = 8;
531 break;
532 case 4:
533 numchan = 3;
534 break;
535 case 5:
536 numchan = 6;
537 break;
538 case 6:
539 numchan = 10;
540 break;
541 case 7:
542 numchan = 12;
543 break;
544 case 8:
545 numchan = 16;
546 break;
547 }
548 adev->gmc.vram_width = numchan * chansize;
549 }
550 /* size in MB on si */
551 tmp = RREG32(mmCONFIG_MEMSIZE);
552 /* some boards may have garbage in the upper 16 bits */
553 if (tmp & 0xffff0000) {
554 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);
555 if (tmp & 0xffff)
556 tmp &= 0xffff;
557 }
558 adev->gmc.mc_vram_size = tmp * 1024ULL * 1024ULL;
559 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
560
561 if (!(adev->flags & AMD_IS_APU)) {
562 r = amdgpu_device_resize_fb_bar(adev);
563 if (r)
564 return r;
565 }
566 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
567 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
568
569#ifdef CONFIG_X86_64
570 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {
571 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
572 adev->gmc.aper_size = adev->gmc.real_vram_size;
573 }
574#endif
575
576 adev->gmc.visible_vram_size = adev->gmc.aper_size;
577
578 /* set the gart size */
579 if (amdgpu_gart_size == -1) {
580 switch (adev->asic_type) {
581 case CHIP_POLARIS10: /* all engines support GPUVM */
582 case CHIP_POLARIS11: /* all engines support GPUVM */
583 case CHIP_POLARIS12: /* all engines support GPUVM */
584 case CHIP_VEGAM: /* all engines support GPUVM */
585 default:
586 adev->gmc.gart_size = 256ULL << 20;
587 break;
588 case CHIP_TONGA: /* UVD, VCE do not support GPUVM */
589 case CHIP_FIJI: /* UVD, VCE do not support GPUVM */
590 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
591 case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */
592 adev->gmc.gart_size = 1024ULL << 20;
593 break;
594 }
595 } else {
596 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
597 }
598
599 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
600 gmc_v8_0_vram_gtt_location(adev, &adev->gmc);
601
602 return 0;
603}
604
605/**
606 * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid
607 *
608 * @adev: amdgpu_device pointer
609 * @pasid: pasid to be flush
610 * @flush_type: type of flush
611 * @all_hub: flush all hubs
612 * @inst: is used to select which instance of KIQ to use for the invalidation
613 *
614 * Flush the TLB for the requested pasid.
615 */
616static void gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
617 uint16_t pasid, uint32_t flush_type,
618 bool all_hub, uint32_t inst)
619{
620 u32 mask = 0x0;
621 int vmid;
622
623 for (vmid = 1; vmid < 16; vmid++) {
624 u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
625
626 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
627 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid)
628 mask |= 1 << vmid;
629 }
630
631 WREG32(mmVM_INVALIDATE_REQUEST, mask);
632 RREG32(mmVM_INVALIDATE_RESPONSE);
633}
634
635/*
636 * GART
637 * VMID 0 is the physical GPU addresses as used by the kernel.
638 * VMIDs 1-15 are used for userspace clients and are handled
639 * by the amdgpu vm/hsa code.
640 */
641
642/**
643 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback
644 *
645 * @adev: amdgpu_device pointer
646 * @vmid: vm instance to flush
647 * @vmhub: which hub to flush
648 * @flush_type: type of flush
649 *
650 * Flush the TLB for the requested page table (VI).
651 */
652static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
653 uint32_t vmhub, uint32_t flush_type)
654{
655 /* bits 0-15 are the VM contexts0-15 */
656 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
657}
658
659static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
660 unsigned int vmid, uint64_t pd_addr)
661{
662 uint32_t reg;
663
664 if (vmid < 8)
665 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
666 else
667 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
668 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
669
670 /* bits 0-15 are the VM contexts0-15 */
671 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
672
673 return pd_addr;
674}
675
676static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid,
677 unsigned int pasid)
678{
679 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
680}
681
682/*
683 * PTE format on VI:
684 * 63:40 reserved
685 * 39:12 4k physical page base address
686 * 11:7 fragment
687 * 6 write
688 * 5 read
689 * 4 exe
690 * 3 reserved
691 * 2 snooped
692 * 1 system
693 * 0 valid
694 *
695 * PDE format on VI:
696 * 63:59 block fragment size
697 * 58:40 reserved
698 * 39:1 physical base address of PTE
699 * bits 5:1 must be 0.
700 * 0 valid
701 */
702
703static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level,
704 uint64_t *addr, uint64_t *flags)
705{
706 BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
707}
708
709static void gmc_v8_0_get_vm_pte(struct amdgpu_device *adev,
710 struct amdgpu_bo_va_mapping *mapping,
711 uint64_t *flags)
712{
713 *flags &= ~AMDGPU_PTE_EXECUTABLE;
714 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
715 *flags &= ~AMDGPU_PTE_PRT;
716}
717
718/**
719 * gmc_v8_0_set_fault_enable_default - update VM fault handling
720 *
721 * @adev: amdgpu_device pointer
722 * @value: true redirects VM faults to the default page
723 */
724static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
725 bool value)
726{
727 u32 tmp;
728
729 tmp = RREG32(mmVM_CONTEXT1_CNTL);
730 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
731 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
732 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
733 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
734 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
735 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
736 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
737 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
738 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
739 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
740 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
741 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
742 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
743 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
744 WREG32(mmVM_CONTEXT1_CNTL, tmp);
745}
746
747/**
748 * gmc_v8_0_set_prt() - set PRT VM fault
749 *
750 * @adev: amdgpu_device pointer
751 * @enable: enable/disable VM fault handling for PRT
752 */
753static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
754{
755 u32 tmp;
756
757 if (enable && !adev->gmc.prt_warning) {
758 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
759 adev->gmc.prt_warning = true;
760 }
761
762 tmp = RREG32(mmVM_PRT_CNTL);
763 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
764 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
765 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
766 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
767 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
768 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
769 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
770 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
771 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
772 L2_CACHE_STORE_INVALID_ENTRIES, enable);
773 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
774 L1_TLB_STORE_INVALID_ENTRIES, enable);
775 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
776 MASK_PDE0_FAULT, enable);
777 WREG32(mmVM_PRT_CNTL, tmp);
778
779 if (enable) {
780 uint32_t low = AMDGPU_VA_RESERVED_BOTTOM >>
781 AMDGPU_GPU_PAGE_SHIFT;
782 uint32_t high = adev->vm_manager.max_pfn -
783 (AMDGPU_VA_RESERVED_TOP >> AMDGPU_GPU_PAGE_SHIFT);
784
785 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
786 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
787 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
788 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
789 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
790 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
791 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
792 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
793 } else {
794 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
795 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
796 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
797 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
798 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
799 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
800 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
801 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
802 }
803}
804
805/**
806 * gmc_v8_0_gart_enable - gart enable
807 *
808 * @adev: amdgpu_device pointer
809 *
810 * This sets up the TLBs, programs the page tables for VMID0,
811 * sets up the hw for VMIDs 1-15 which are allocated on
812 * demand, and sets up the global locations for the LDS, GDS,
813 * and GPUVM for FSA64 clients (VI).
814 * Returns 0 for success, errors for failure.
815 */
816static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
817{
818 uint64_t table_addr;
819 u32 tmp, field;
820 int i;
821
822 if (adev->gart.bo == NULL) {
823 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
824 return -EINVAL;
825 }
826 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
827 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
828
829 /* Setup TLB control */
830 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
831 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
832 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
833 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
834 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
835 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
836 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
837 /* Setup L2 cache */
838 tmp = RREG32(mmVM_L2_CNTL);
839 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
840 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
841 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
842 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
843 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
844 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
845 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
846 WREG32(mmVM_L2_CNTL, tmp);
847 tmp = RREG32(mmVM_L2_CNTL2);
848 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
849 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
850 WREG32(mmVM_L2_CNTL2, tmp);
851
852 field = adev->vm_manager.fragment_size;
853 tmp = RREG32(mmVM_L2_CNTL3);
854 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
855 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
856 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
857 WREG32(mmVM_L2_CNTL3, tmp);
858 /* XXX: set to enable PTE/PDE in system memory */
859 tmp = RREG32(mmVM_L2_CNTL4);
860 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
861 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
862 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
863 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
864 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
865 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
866 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
867 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
868 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
869 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
870 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
871 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
872 WREG32(mmVM_L2_CNTL4, tmp);
873 /* setup context0 */
874 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
875 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
876 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
877 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
878 (u32)(adev->dummy_page_addr >> 12));
879 WREG32(mmVM_CONTEXT0_CNTL2, 0);
880 tmp = RREG32(mmVM_CONTEXT0_CNTL);
881 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
882 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
883 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
884 WREG32(mmVM_CONTEXT0_CNTL, tmp);
885
886 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
887 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
888 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
889
890 /* empty context1-15 */
891 /* FIXME start with 4G, once using 2 level pt switch to full
892 * vm size space
893 */
894 /* set vm size, must be a multiple of 4 */
895 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
896 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
897 for (i = 1; i < AMDGPU_NUM_VMID; i++) {
898 if (i < 8)
899 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
900 table_addr >> 12);
901 else
902 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
903 table_addr >> 12);
904 }
905
906 /* enable context1-15 */
907 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
908 (u32)(adev->dummy_page_addr >> 12));
909 WREG32(mmVM_CONTEXT1_CNTL2, 4);
910 tmp = RREG32(mmVM_CONTEXT1_CNTL);
911 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
912 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
913 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
914 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
915 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
916 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
917 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
918 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
919 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
920 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
921 adev->vm_manager.block_size - 9);
922 WREG32(mmVM_CONTEXT1_CNTL, tmp);
923 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
924 gmc_v8_0_set_fault_enable_default(adev, false);
925 else
926 gmc_v8_0_set_fault_enable_default(adev, true);
927
928 gmc_v8_0_flush_gpu_tlb(adev, 0, 0, 0);
929 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
930 (unsigned int)(adev->gmc.gart_size >> 20),
931 (unsigned long long)table_addr);
932 return 0;
933}
934
935static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
936{
937 int r;
938
939 if (adev->gart.bo) {
940 WARN(1, "R600 PCIE GART already initialized\n");
941 return 0;
942 }
943 /* Initialize common gart structure */
944 r = amdgpu_gart_init(adev);
945 if (r)
946 return r;
947 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
948 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE;
949 return amdgpu_gart_table_vram_alloc(adev);
950}
951
952/**
953 * gmc_v8_0_gart_disable - gart disable
954 *
955 * @adev: amdgpu_device pointer
956 *
957 * This disables all VM page table (VI).
958 */
959static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
960{
961 u32 tmp;
962
963 /* Disable all tables */
964 WREG32(mmVM_CONTEXT0_CNTL, 0);
965 WREG32(mmVM_CONTEXT1_CNTL, 0);
966 /* Setup TLB control */
967 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
968 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
969 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
970 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
971 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
972 /* Setup L2 cache */
973 tmp = RREG32(mmVM_L2_CNTL);
974 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
975 WREG32(mmVM_L2_CNTL, tmp);
976 WREG32(mmVM_L2_CNTL2, 0);
977}
978
979/**
980 * gmc_v8_0_vm_decode_fault - print human readable fault info
981 *
982 * @adev: amdgpu_device pointer
983 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
984 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
985 * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value
986 * @pasid: debug logging only - no functional use
987 *
988 * Print human readable fault information (VI).
989 */
990static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
991 u32 addr, u32 mc_client, unsigned int pasid)
992{
993 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
994 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
995 PROTECTIONS);
996 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
997 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
998 u32 mc_id;
999
1000 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1001 MEMORY_CLIENT_ID);
1002
1003 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
1004 protections, vmid, pasid, addr,
1005 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1006 MEMORY_CLIENT_RW) ?
1007 "write" : "read", block, mc_client, mc_id);
1008}
1009
1010static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
1011{
1012 switch (mc_seq_vram_type) {
1013 case MC_SEQ_MISC0__MT__GDDR1:
1014 return AMDGPU_VRAM_TYPE_GDDR1;
1015 case MC_SEQ_MISC0__MT__DDR2:
1016 return AMDGPU_VRAM_TYPE_DDR2;
1017 case MC_SEQ_MISC0__MT__GDDR3:
1018 return AMDGPU_VRAM_TYPE_GDDR3;
1019 case MC_SEQ_MISC0__MT__GDDR4:
1020 return AMDGPU_VRAM_TYPE_GDDR4;
1021 case MC_SEQ_MISC0__MT__GDDR5:
1022 return AMDGPU_VRAM_TYPE_GDDR5;
1023 case MC_SEQ_MISC0__MT__HBM:
1024 return AMDGPU_VRAM_TYPE_HBM;
1025 case MC_SEQ_MISC0__MT__DDR3:
1026 return AMDGPU_VRAM_TYPE_DDR3;
1027 default:
1028 return AMDGPU_VRAM_TYPE_UNKNOWN;
1029 }
1030}
1031
1032static int gmc_v8_0_early_init(void *handle)
1033{
1034 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1035
1036 gmc_v8_0_set_gmc_funcs(adev);
1037 gmc_v8_0_set_irq_funcs(adev);
1038
1039 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1040 adev->gmc.shared_aperture_end =
1041 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1042 adev->gmc.private_aperture_start =
1043 adev->gmc.shared_aperture_end + 1;
1044 adev->gmc.private_aperture_end =
1045 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1046 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;
1047
1048 return 0;
1049}
1050
1051static int gmc_v8_0_late_init(void *handle)
1052{
1053 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1054
1055 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
1056 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1057 else
1058 return 0;
1059}
1060
1061static unsigned int gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev)
1062{
1063 u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
1064 unsigned int size;
1065
1066 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1067 size = AMDGPU_VBIOS_VGA_ALLOCATION;
1068 } else {
1069 u32 viewport = RREG32(mmVIEWPORT_SIZE);
1070
1071 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1072 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1073 4);
1074 }
1075
1076 return size;
1077}
1078
1079#define mmMC_SEQ_MISC0_FIJI 0xA71
1080
1081static int gmc_v8_0_sw_init(void *handle)
1082{
1083 int r;
1084 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1085
1086 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
1087
1088 if (adev->flags & AMD_IS_APU) {
1089 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
1090 } else {
1091 u32 tmp;
1092
1093 if ((adev->asic_type == CHIP_FIJI) ||
1094 (adev->asic_type == CHIP_VEGAM))
1095 tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
1096 else
1097 tmp = RREG32(mmMC_SEQ_MISC0);
1098 tmp &= MC_SEQ_MISC0__MT__MASK;
1099 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);
1100 }
1101
1102 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
1103 if (r)
1104 return r;
1105
1106 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
1107 if (r)
1108 return r;
1109
1110 /* Adjust VM size here.
1111 * Currently set to 4GB ((1 << 20) 4k pages).
1112 * Max GPUVM size for cayman and SI is 40 bits.
1113 */
1114 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1115
1116 /* Set the internal MC address mask
1117 * This is the max address of the GPU's
1118 * internal address space.
1119 */
1120 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1121
1122 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
1123 if (r) {
1124 pr_warn("No suitable DMA available\n");
1125 return r;
1126 }
1127 adev->need_swiotlb = drm_need_swiotlb(40);
1128
1129 r = gmc_v8_0_init_microcode(adev);
1130 if (r) {
1131 DRM_ERROR("Failed to load mc firmware!\n");
1132 return r;
1133 }
1134
1135 r = gmc_v8_0_mc_init(adev);
1136 if (r)
1137 return r;
1138
1139 amdgpu_gmc_get_vbios_allocations(adev);
1140
1141 /* Memory manager */
1142 r = amdgpu_bo_init(adev);
1143 if (r)
1144 return r;
1145
1146 r = gmc_v8_0_gart_init(adev);
1147 if (r)
1148 return r;
1149
1150 /*
1151 * number of VMs
1152 * VMID 0 is reserved for System
1153 * amdgpu graphics/compute will use VMIDs 1-7
1154 * amdkfd will use VMIDs 8-15
1155 */
1156 adev->vm_manager.first_kfd_vmid = 8;
1157 amdgpu_vm_manager_init(adev);
1158
1159 /* base offset of vram pages */
1160 if (adev->flags & AMD_IS_APU) {
1161 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1162
1163 tmp <<= 22;
1164 adev->vm_manager.vram_base_offset = tmp;
1165 } else {
1166 adev->vm_manager.vram_base_offset = 0;
1167 }
1168
1169 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),
1170 GFP_KERNEL);
1171 if (!adev->gmc.vm_fault_info)
1172 return -ENOMEM;
1173 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1174
1175 return 0;
1176}
1177
1178static int gmc_v8_0_sw_fini(void *handle)
1179{
1180 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1181
1182 amdgpu_gem_force_release(adev);
1183 amdgpu_vm_manager_fini(adev);
1184 kfree(adev->gmc.vm_fault_info);
1185 amdgpu_gart_table_vram_free(adev);
1186 amdgpu_bo_fini(adev);
1187 amdgpu_ucode_release(&adev->gmc.fw);
1188
1189 return 0;
1190}
1191
1192static int gmc_v8_0_hw_init(void *handle)
1193{
1194 int r;
1195 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1196
1197 gmc_v8_0_init_golden_registers(adev);
1198
1199 gmc_v8_0_mc_program(adev);
1200
1201 if (adev->asic_type == CHIP_TONGA) {
1202 r = gmc_v8_0_tonga_mc_load_microcode(adev);
1203 if (r) {
1204 DRM_ERROR("Failed to load MC firmware!\n");
1205 return r;
1206 }
1207 } else if (adev->asic_type == CHIP_POLARIS11 ||
1208 adev->asic_type == CHIP_POLARIS10 ||
1209 adev->asic_type == CHIP_POLARIS12) {
1210 r = gmc_v8_0_polaris_mc_load_microcode(adev);
1211 if (r) {
1212 DRM_ERROR("Failed to load MC firmware!\n");
1213 return r;
1214 }
1215 }
1216
1217 r = gmc_v8_0_gart_enable(adev);
1218 if (r)
1219 return r;
1220
1221 if (amdgpu_emu_mode == 1)
1222 return amdgpu_gmc_vram_checking(adev);
1223
1224 return 0;
1225}
1226
1227static int gmc_v8_0_hw_fini(void *handle)
1228{
1229 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1230
1231 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1232 gmc_v8_0_gart_disable(adev);
1233
1234 return 0;
1235}
1236
1237static int gmc_v8_0_suspend(void *handle)
1238{
1239 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1240
1241 gmc_v8_0_hw_fini(adev);
1242
1243 return 0;
1244}
1245
1246static int gmc_v8_0_resume(void *handle)
1247{
1248 int r;
1249 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1250
1251 r = gmc_v8_0_hw_init(adev);
1252 if (r)
1253 return r;
1254
1255 amdgpu_vmid_reset_all(adev);
1256
1257 return 0;
1258}
1259
1260static bool gmc_v8_0_is_idle(void *handle)
1261{
1262 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1263 u32 tmp = RREG32(mmSRBM_STATUS);
1264
1265 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1266 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1267 return false;
1268
1269 return true;
1270}
1271
1272static int gmc_v8_0_wait_for_idle(void *handle)
1273{
1274 unsigned int i;
1275 u32 tmp;
1276 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1277
1278 for (i = 0; i < adev->usec_timeout; i++) {
1279 /* read MC_STATUS */
1280 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1281 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1282 SRBM_STATUS__MCC_BUSY_MASK |
1283 SRBM_STATUS__MCD_BUSY_MASK |
1284 SRBM_STATUS__VMC_BUSY_MASK |
1285 SRBM_STATUS__VMC1_BUSY_MASK);
1286 if (!tmp)
1287 return 0;
1288 udelay(1);
1289 }
1290 return -ETIMEDOUT;
1291
1292}
1293
1294static bool gmc_v8_0_check_soft_reset(void *handle)
1295{
1296 u32 srbm_soft_reset = 0;
1297 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1298 u32 tmp = RREG32(mmSRBM_STATUS);
1299
1300 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1301 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1302 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1303
1304 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1305 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1306 if (!(adev->flags & AMD_IS_APU))
1307 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1308 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1309 }
1310
1311 if (srbm_soft_reset) {
1312 adev->gmc.srbm_soft_reset = srbm_soft_reset;
1313 return true;
1314 }
1315
1316 adev->gmc.srbm_soft_reset = 0;
1317
1318 return false;
1319}
1320
1321static int gmc_v8_0_pre_soft_reset(void *handle)
1322{
1323 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1324
1325 if (!adev->gmc.srbm_soft_reset)
1326 return 0;
1327
1328 gmc_v8_0_mc_stop(adev);
1329 if (gmc_v8_0_wait_for_idle(adev))
1330 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1331
1332 return 0;
1333}
1334
1335static int gmc_v8_0_soft_reset(void *handle)
1336{
1337 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1338 u32 srbm_soft_reset;
1339
1340 if (!adev->gmc.srbm_soft_reset)
1341 return 0;
1342 srbm_soft_reset = adev->gmc.srbm_soft_reset;
1343
1344 if (srbm_soft_reset) {
1345 u32 tmp;
1346
1347 tmp = RREG32(mmSRBM_SOFT_RESET);
1348 tmp |= srbm_soft_reset;
1349 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1350 WREG32(mmSRBM_SOFT_RESET, tmp);
1351 tmp = RREG32(mmSRBM_SOFT_RESET);
1352
1353 udelay(50);
1354
1355 tmp &= ~srbm_soft_reset;
1356 WREG32(mmSRBM_SOFT_RESET, tmp);
1357 tmp = RREG32(mmSRBM_SOFT_RESET);
1358
1359 /* Wait a little for things to settle down */
1360 udelay(50);
1361 }
1362
1363 return 0;
1364}
1365
1366static int gmc_v8_0_post_soft_reset(void *handle)
1367{
1368 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1369
1370 if (!adev->gmc.srbm_soft_reset)
1371 return 0;
1372
1373 gmc_v8_0_mc_resume(adev);
1374 return 0;
1375}
1376
1377static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1378 struct amdgpu_irq_src *src,
1379 unsigned int type,
1380 enum amdgpu_interrupt_state state)
1381{
1382 u32 tmp;
1383 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1384 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1385 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1386 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1387 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1388 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1389 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1390
1391 switch (state) {
1392 case AMDGPU_IRQ_STATE_DISABLE:
1393 /* system context */
1394 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1395 tmp &= ~bits;
1396 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1397 /* VMs */
1398 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1399 tmp &= ~bits;
1400 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1401 break;
1402 case AMDGPU_IRQ_STATE_ENABLE:
1403 /* system context */
1404 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1405 tmp |= bits;
1406 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1407 /* VMs */
1408 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1409 tmp |= bits;
1410 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1411 break;
1412 default:
1413 break;
1414 }
1415
1416 return 0;
1417}
1418
1419static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1420 struct amdgpu_irq_src *source,
1421 struct amdgpu_iv_entry *entry)
1422{
1423 u32 addr, status, mc_client, vmid;
1424
1425 if (amdgpu_sriov_vf(adev)) {
1426 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1427 entry->src_id, entry->src_data[0]);
1428 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
1429 return 0;
1430 }
1431
1432 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1433 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1434 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1435 /* reset addr and status */
1436 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1437
1438 if (!addr && !status)
1439 return 0;
1440
1441 amdgpu_vm_update_fault_cache(adev, entry->pasid,
1442 ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0));
1443
1444 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1445 gmc_v8_0_set_fault_enable_default(adev, false);
1446
1447 if (printk_ratelimit()) {
1448 struct amdgpu_task_info *task_info;
1449
1450 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1451 entry->src_id, entry->src_data[0]);
1452
1453 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid);
1454 if (task_info) {
1455 dev_err(adev->dev, " for process %s pid %d thread %s pid %d\n",
1456 task_info->process_name, task_info->tgid,
1457 task_info->task_name, task_info->pid);
1458 amdgpu_vm_put_task_info(task_info);
1459 }
1460
1461 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1462 addr);
1463 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1464 status);
1465
1466 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client,
1467 entry->pasid);
1468 }
1469
1470 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1471 VMID);
1472 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)
1473 && !atomic_read(&adev->gmc.vm_fault_info_updated)) {
1474 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;
1475 u32 protections = REG_GET_FIELD(status,
1476 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1477 PROTECTIONS);
1478
1479 info->vmid = vmid;
1480 info->mc_id = REG_GET_FIELD(status,
1481 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1482 MEMORY_CLIENT_ID);
1483 info->status = status;
1484 info->page_addr = addr;
1485 info->prot_valid = protections & 0x7 ? true : false;
1486 info->prot_read = protections & 0x8 ? true : false;
1487 info->prot_write = protections & 0x10 ? true : false;
1488 info->prot_exec = protections & 0x20 ? true : false;
1489 mb();
1490 atomic_set(&adev->gmc.vm_fault_info_updated, 1);
1491 }
1492
1493 return 0;
1494}
1495
1496static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1497 bool enable)
1498{
1499 uint32_t data;
1500
1501 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1502 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1503 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1504 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1505
1506 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1507 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1508 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1509
1510 data = RREG32(mmMC_HUB_MISC_VM_CG);
1511 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1512 WREG32(mmMC_HUB_MISC_VM_CG, data);
1513
1514 data = RREG32(mmMC_XPB_CLK_GAT);
1515 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1516 WREG32(mmMC_XPB_CLK_GAT, data);
1517
1518 data = RREG32(mmATC_MISC_CG);
1519 data |= ATC_MISC_CG__ENABLE_MASK;
1520 WREG32(mmATC_MISC_CG, data);
1521
1522 data = RREG32(mmMC_CITF_MISC_WR_CG);
1523 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1524 WREG32(mmMC_CITF_MISC_WR_CG, data);
1525
1526 data = RREG32(mmMC_CITF_MISC_RD_CG);
1527 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1528 WREG32(mmMC_CITF_MISC_RD_CG, data);
1529
1530 data = RREG32(mmMC_CITF_MISC_VM_CG);
1531 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1532 WREG32(mmMC_CITF_MISC_VM_CG, data);
1533
1534 data = RREG32(mmVM_L2_CG);
1535 data |= VM_L2_CG__ENABLE_MASK;
1536 WREG32(mmVM_L2_CG, data);
1537 } else {
1538 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1539 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1540 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1541
1542 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1543 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1544 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1545
1546 data = RREG32(mmMC_HUB_MISC_VM_CG);
1547 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1548 WREG32(mmMC_HUB_MISC_VM_CG, data);
1549
1550 data = RREG32(mmMC_XPB_CLK_GAT);
1551 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1552 WREG32(mmMC_XPB_CLK_GAT, data);
1553
1554 data = RREG32(mmATC_MISC_CG);
1555 data &= ~ATC_MISC_CG__ENABLE_MASK;
1556 WREG32(mmATC_MISC_CG, data);
1557
1558 data = RREG32(mmMC_CITF_MISC_WR_CG);
1559 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1560 WREG32(mmMC_CITF_MISC_WR_CG, data);
1561
1562 data = RREG32(mmMC_CITF_MISC_RD_CG);
1563 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1564 WREG32(mmMC_CITF_MISC_RD_CG, data);
1565
1566 data = RREG32(mmMC_CITF_MISC_VM_CG);
1567 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1568 WREG32(mmMC_CITF_MISC_VM_CG, data);
1569
1570 data = RREG32(mmVM_L2_CG);
1571 data &= ~VM_L2_CG__ENABLE_MASK;
1572 WREG32(mmVM_L2_CG, data);
1573 }
1574}
1575
1576static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1577 bool enable)
1578{
1579 uint32_t data;
1580
1581 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1582 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1583 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1584 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1585
1586 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1587 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1588 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1589
1590 data = RREG32(mmMC_HUB_MISC_VM_CG);
1591 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1592 WREG32(mmMC_HUB_MISC_VM_CG, data);
1593
1594 data = RREG32(mmMC_XPB_CLK_GAT);
1595 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1596 WREG32(mmMC_XPB_CLK_GAT, data);
1597
1598 data = RREG32(mmATC_MISC_CG);
1599 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1600 WREG32(mmATC_MISC_CG, data);
1601
1602 data = RREG32(mmMC_CITF_MISC_WR_CG);
1603 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1604 WREG32(mmMC_CITF_MISC_WR_CG, data);
1605
1606 data = RREG32(mmMC_CITF_MISC_RD_CG);
1607 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1608 WREG32(mmMC_CITF_MISC_RD_CG, data);
1609
1610 data = RREG32(mmMC_CITF_MISC_VM_CG);
1611 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1612 WREG32(mmMC_CITF_MISC_VM_CG, data);
1613
1614 data = RREG32(mmVM_L2_CG);
1615 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1616 WREG32(mmVM_L2_CG, data);
1617 } else {
1618 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1619 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1620 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1621
1622 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1623 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1624 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1625
1626 data = RREG32(mmMC_HUB_MISC_VM_CG);
1627 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1628 WREG32(mmMC_HUB_MISC_VM_CG, data);
1629
1630 data = RREG32(mmMC_XPB_CLK_GAT);
1631 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1632 WREG32(mmMC_XPB_CLK_GAT, data);
1633
1634 data = RREG32(mmATC_MISC_CG);
1635 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1636 WREG32(mmATC_MISC_CG, data);
1637
1638 data = RREG32(mmMC_CITF_MISC_WR_CG);
1639 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1640 WREG32(mmMC_CITF_MISC_WR_CG, data);
1641
1642 data = RREG32(mmMC_CITF_MISC_RD_CG);
1643 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1644 WREG32(mmMC_CITF_MISC_RD_CG, data);
1645
1646 data = RREG32(mmMC_CITF_MISC_VM_CG);
1647 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1648 WREG32(mmMC_CITF_MISC_VM_CG, data);
1649
1650 data = RREG32(mmVM_L2_CG);
1651 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1652 WREG32(mmVM_L2_CG, data);
1653 }
1654}
1655
1656static int gmc_v8_0_set_clockgating_state(void *handle,
1657 enum amd_clockgating_state state)
1658{
1659 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1660
1661 if (amdgpu_sriov_vf(adev))
1662 return 0;
1663
1664 switch (adev->asic_type) {
1665 case CHIP_FIJI:
1666 fiji_update_mc_medium_grain_clock_gating(adev,
1667 state == AMD_CG_STATE_GATE);
1668 fiji_update_mc_light_sleep(adev,
1669 state == AMD_CG_STATE_GATE);
1670 break;
1671 default:
1672 break;
1673 }
1674 return 0;
1675}
1676
1677static int gmc_v8_0_set_powergating_state(void *handle,
1678 enum amd_powergating_state state)
1679{
1680 return 0;
1681}
1682
1683static void gmc_v8_0_get_clockgating_state(void *handle, u64 *flags)
1684{
1685 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1686 int data;
1687
1688 if (amdgpu_sriov_vf(adev))
1689 *flags = 0;
1690
1691 /* AMD_CG_SUPPORT_MC_MGCG */
1692 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1693 if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
1694 *flags |= AMD_CG_SUPPORT_MC_MGCG;
1695
1696 /* AMD_CG_SUPPORT_MC_LS */
1697 if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
1698 *flags |= AMD_CG_SUPPORT_MC_LS;
1699}
1700
1701static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1702 .name = "gmc_v8_0",
1703 .early_init = gmc_v8_0_early_init,
1704 .late_init = gmc_v8_0_late_init,
1705 .sw_init = gmc_v8_0_sw_init,
1706 .sw_fini = gmc_v8_0_sw_fini,
1707 .hw_init = gmc_v8_0_hw_init,
1708 .hw_fini = gmc_v8_0_hw_fini,
1709 .suspend = gmc_v8_0_suspend,
1710 .resume = gmc_v8_0_resume,
1711 .is_idle = gmc_v8_0_is_idle,
1712 .wait_for_idle = gmc_v8_0_wait_for_idle,
1713 .check_soft_reset = gmc_v8_0_check_soft_reset,
1714 .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1715 .soft_reset = gmc_v8_0_soft_reset,
1716 .post_soft_reset = gmc_v8_0_post_soft_reset,
1717 .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1718 .set_powergating_state = gmc_v8_0_set_powergating_state,
1719 .get_clockgating_state = gmc_v8_0_get_clockgating_state,
1720};
1721
1722static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
1723 .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
1724 .flush_gpu_tlb_pasid = gmc_v8_0_flush_gpu_tlb_pasid,
1725 .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
1726 .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
1727 .set_prt = gmc_v8_0_set_prt,
1728 .get_vm_pde = gmc_v8_0_get_vm_pde,
1729 .get_vm_pte = gmc_v8_0_get_vm_pte,
1730 .get_vbios_fb_size = gmc_v8_0_get_vbios_fb_size,
1731};
1732
1733static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1734 .set = gmc_v8_0_vm_fault_interrupt_state,
1735 .process = gmc_v8_0_process_interrupt,
1736};
1737
1738static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev)
1739{
1740 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;
1741}
1742
1743static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1744{
1745 adev->gmc.vm_fault.num_types = 1;
1746 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1747}
1748
1749const struct amdgpu_ip_block_version gmc_v8_0_ip_block = {
1750 .type = AMD_IP_BLOCK_TYPE_GMC,
1751 .major = 8,
1752 .minor = 0,
1753 .rev = 0,
1754 .funcs = &gmc_v8_0_ip_funcs,
1755};
1756
1757const struct amdgpu_ip_block_version gmc_v8_1_ip_block = {
1758 .type = AMD_IP_BLOCK_TYPE_GMC,
1759 .major = 8,
1760 .minor = 1,
1761 .rev = 0,
1762 .funcs = &gmc_v8_0_ip_funcs,
1763};
1764
1765const struct amdgpu_ip_block_version gmc_v8_5_ip_block = {
1766 .type = AMD_IP_BLOCK_TYPE_GMC,
1767 .major = 8,
1768 .minor = 5,
1769 .rev = 0,
1770 .funcs = &gmc_v8_0_ip_funcs,
1771};
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "gmc_v8_0.h"
27#include "amdgpu_ucode.h"
28
29#include "gmc/gmc_8_1_d.h"
30#include "gmc/gmc_8_1_sh_mask.h"
31
32#include "bif/bif_5_0_d.h"
33#include "bif/bif_5_0_sh_mask.h"
34
35#include "oss/oss_3_0_d.h"
36#include "oss/oss_3_0_sh_mask.h"
37
38#include "vid.h"
39#include "vi.h"
40
41
42static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
43static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
44static int gmc_v8_0_wait_for_idle(void *handle);
45
46MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
47MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
48MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
49MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");
50
51static const u32 golden_settings_tonga_a11[] =
52{
53 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
54 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
55 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
56 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
57 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
58 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
59 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
60};
61
62static const u32 tonga_mgcg_cgcg_init[] =
63{
64 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
65};
66
67static const u32 golden_settings_fiji_a10[] =
68{
69 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
70 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
71 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
72 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
73};
74
75static const u32 fiji_mgcg_cgcg_init[] =
76{
77 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
78};
79
80static const u32 golden_settings_polaris11_a11[] =
81{
82 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
83 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
84 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
85 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
86};
87
88static const u32 golden_settings_polaris10_a11[] =
89{
90 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
91 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
92 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
93 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
94 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
95};
96
97static const u32 cz_mgcg_cgcg_init[] =
98{
99 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
100};
101
102static const u32 stoney_mgcg_cgcg_init[] =
103{
104 mmATC_MISC_CG, 0xffffffff, 0x000c0200,
105 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
106};
107
108static const u32 golden_settings_stoney_common[] =
109{
110 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
111 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
112};
113
114static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
115{
116 switch (adev->asic_type) {
117 case CHIP_FIJI:
118 amdgpu_program_register_sequence(adev,
119 fiji_mgcg_cgcg_init,
120 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
121 amdgpu_program_register_sequence(adev,
122 golden_settings_fiji_a10,
123 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
124 break;
125 case CHIP_TONGA:
126 amdgpu_program_register_sequence(adev,
127 tonga_mgcg_cgcg_init,
128 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
129 amdgpu_program_register_sequence(adev,
130 golden_settings_tonga_a11,
131 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
132 break;
133 case CHIP_POLARIS11:
134 case CHIP_POLARIS12:
135 amdgpu_program_register_sequence(adev,
136 golden_settings_polaris11_a11,
137 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
138 break;
139 case CHIP_POLARIS10:
140 amdgpu_program_register_sequence(adev,
141 golden_settings_polaris10_a11,
142 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
143 break;
144 case CHIP_CARRIZO:
145 amdgpu_program_register_sequence(adev,
146 cz_mgcg_cgcg_init,
147 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
148 break;
149 case CHIP_STONEY:
150 amdgpu_program_register_sequence(adev,
151 stoney_mgcg_cgcg_init,
152 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
153 amdgpu_program_register_sequence(adev,
154 golden_settings_stoney_common,
155 (const u32)ARRAY_SIZE(golden_settings_stoney_common));
156 break;
157 default:
158 break;
159 }
160}
161
162static void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
163 struct amdgpu_mode_mc_save *save)
164{
165 u32 blackout;
166
167 if (adev->mode_info.num_crtc)
168 amdgpu_display_stop_mc_access(adev, save);
169
170 gmc_v8_0_wait_for_idle(adev);
171
172 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
173 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
174 /* Block CPU access */
175 WREG32(mmBIF_FB_EN, 0);
176 /* blackout the MC */
177 blackout = REG_SET_FIELD(blackout,
178 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
179 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
180 }
181 /* wait for the MC to settle */
182 udelay(100);
183}
184
185static void gmc_v8_0_mc_resume(struct amdgpu_device *adev,
186 struct amdgpu_mode_mc_save *save)
187{
188 u32 tmp;
189
190 /* unblackout the MC */
191 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
192 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
193 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
194 /* allow CPU access */
195 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
196 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
197 WREG32(mmBIF_FB_EN, tmp);
198
199 if (adev->mode_info.num_crtc)
200 amdgpu_display_resume_mc_access(adev, save);
201}
202
203/**
204 * gmc_v8_0_init_microcode - load ucode images from disk
205 *
206 * @adev: amdgpu_device pointer
207 *
208 * Use the firmware interface to load the ucode images into
209 * the driver (not loaded into hw).
210 * Returns 0 on success, error on failure.
211 */
212static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
213{
214 const char *chip_name;
215 char fw_name[30];
216 int err;
217
218 DRM_DEBUG("\n");
219
220 switch (adev->asic_type) {
221 case CHIP_TONGA:
222 chip_name = "tonga";
223 break;
224 case CHIP_POLARIS11:
225 chip_name = "polaris11";
226 break;
227 case CHIP_POLARIS10:
228 chip_name = "polaris10";
229 break;
230 case CHIP_POLARIS12:
231 chip_name = "polaris12";
232 break;
233 case CHIP_FIJI:
234 case CHIP_CARRIZO:
235 case CHIP_STONEY:
236 return 0;
237 default: BUG();
238 }
239
240 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
241 err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
242 if (err)
243 goto out;
244 err = amdgpu_ucode_validate(adev->mc.fw);
245
246out:
247 if (err) {
248 printk(KERN_ERR
249 "mc: Failed to load firmware \"%s\"\n",
250 fw_name);
251 release_firmware(adev->mc.fw);
252 adev->mc.fw = NULL;
253 }
254 return err;
255}
256
257/**
258 * gmc_v8_0_mc_load_microcode - load MC ucode into the hw
259 *
260 * @adev: amdgpu_device pointer
261 *
262 * Load the GDDR MC ucode into the hw (CIK).
263 * Returns 0 on success, error on failure.
264 */
265static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev)
266{
267 const struct mc_firmware_header_v1_0 *hdr;
268 const __le32 *fw_data = NULL;
269 const __le32 *io_mc_regs = NULL;
270 u32 running;
271 int i, ucode_size, regs_size;
272
273 if (!adev->mc.fw)
274 return -EINVAL;
275
276 /* Skip MC ucode loading on SR-IOV capable boards.
277 * vbios does this for us in asic_init in that case.
278 * Skip MC ucode loading on VF, because hypervisor will do that
279 * for this adaptor.
280 */
281 if (amdgpu_sriov_bios(adev))
282 return 0;
283
284 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
285 amdgpu_ucode_print_mc_hdr(&hdr->header);
286
287 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
288 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
289 io_mc_regs = (const __le32 *)
290 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
291 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
292 fw_data = (const __le32 *)
293 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
294
295 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
296
297 if (running == 0) {
298 /* reset the engine and set to writable */
299 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
300 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
301
302 /* load mc io regs */
303 for (i = 0; i < regs_size; i++) {
304 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
305 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
306 }
307 /* load the MC ucode */
308 for (i = 0; i < ucode_size; i++)
309 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
310
311 /* put the engine back into the active state */
312 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
313 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
314 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
315
316 /* wait for training to complete */
317 for (i = 0; i < adev->usec_timeout; i++) {
318 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
319 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
320 break;
321 udelay(1);
322 }
323 for (i = 0; i < adev->usec_timeout; i++) {
324 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
325 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
326 break;
327 udelay(1);
328 }
329 }
330
331 return 0;
332}
333
334static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
335 struct amdgpu_mc *mc)
336{
337 if (mc->mc_vram_size > 0xFFC0000000ULL) {
338 /* leave room for at least 1024M GTT */
339 dev_warn(adev->dev, "limiting VRAM\n");
340 mc->real_vram_size = 0xFFC0000000ULL;
341 mc->mc_vram_size = 0xFFC0000000ULL;
342 }
343 amdgpu_vram_location(adev, &adev->mc, 0);
344 adev->mc.gtt_base_align = 0;
345 amdgpu_gtt_location(adev, mc);
346}
347
348/**
349 * gmc_v8_0_mc_program - program the GPU memory controller
350 *
351 * @adev: amdgpu_device pointer
352 *
353 * Set the location of vram, gart, and AGP in the GPU's
354 * physical address space (CIK).
355 */
356static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
357{
358 struct amdgpu_mode_mc_save save;
359 u32 tmp;
360 int i, j;
361
362 /* Initialize HDP */
363 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
364 WREG32((0xb05 + j), 0x00000000);
365 WREG32((0xb06 + j), 0x00000000);
366 WREG32((0xb07 + j), 0x00000000);
367 WREG32((0xb08 + j), 0x00000000);
368 WREG32((0xb09 + j), 0x00000000);
369 }
370 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
371
372 if (adev->mode_info.num_crtc)
373 amdgpu_display_set_vga_render_state(adev, false);
374
375 gmc_v8_0_mc_stop(adev, &save);
376 if (gmc_v8_0_wait_for_idle((void *)adev)) {
377 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
378 }
379 /* Update configuration */
380 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
381 adev->mc.vram_start >> 12);
382 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
383 adev->mc.vram_end >> 12);
384 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
385 adev->vram_scratch.gpu_addr >> 12);
386 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
387 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
388 WREG32(mmMC_VM_FB_LOCATION, tmp);
389 /* XXX double check these! */
390 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
391 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
392 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
393 WREG32(mmMC_VM_AGP_BASE, 0);
394 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
395 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
396 if (gmc_v8_0_wait_for_idle((void *)adev)) {
397 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
398 }
399 gmc_v8_0_mc_resume(adev, &save);
400
401 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
402
403 tmp = RREG32(mmHDP_MISC_CNTL);
404 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
405 WREG32(mmHDP_MISC_CNTL, tmp);
406
407 tmp = RREG32(mmHDP_HOST_PATH_CNTL);
408 WREG32(mmHDP_HOST_PATH_CNTL, tmp);
409}
410
411/**
412 * gmc_v8_0_mc_init - initialize the memory controller driver params
413 *
414 * @adev: amdgpu_device pointer
415 *
416 * Look up the amount of vram, vram width, and decide how to place
417 * vram and gart within the GPU's physical address space (CIK).
418 * Returns 0 for success.
419 */
420static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
421{
422 u32 tmp;
423 int chansize, numchan;
424
425 /* Get VRAM informations */
426 tmp = RREG32(mmMC_ARB_RAMCFG);
427 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
428 chansize = 64;
429 } else {
430 chansize = 32;
431 }
432 tmp = RREG32(mmMC_SHARED_CHMAP);
433 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
434 case 0:
435 default:
436 numchan = 1;
437 break;
438 case 1:
439 numchan = 2;
440 break;
441 case 2:
442 numchan = 4;
443 break;
444 case 3:
445 numchan = 8;
446 break;
447 case 4:
448 numchan = 3;
449 break;
450 case 5:
451 numchan = 6;
452 break;
453 case 6:
454 numchan = 10;
455 break;
456 case 7:
457 numchan = 12;
458 break;
459 case 8:
460 numchan = 16;
461 break;
462 }
463 adev->mc.vram_width = numchan * chansize;
464 /* Could aper size report 0 ? */
465 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
466 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
467 /* size in MB on si */
468 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
469 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
470 adev->mc.visible_vram_size = adev->mc.aper_size;
471
472 /* In case the PCI BAR is larger than the actual amount of vram */
473 if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
474 adev->mc.visible_vram_size = adev->mc.real_vram_size;
475
476 /* unless the user had overridden it, set the gart
477 * size equal to the 1024 or vram, whichever is larger.
478 */
479 if (amdgpu_gart_size == -1)
480 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
481 else
482 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
483
484 gmc_v8_0_vram_gtt_location(adev, &adev->mc);
485
486 return 0;
487}
488
489/*
490 * GART
491 * VMID 0 is the physical GPU addresses as used by the kernel.
492 * VMIDs 1-15 are used for userspace clients and are handled
493 * by the amdgpu vm/hsa code.
494 */
495
496/**
497 * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
498 *
499 * @adev: amdgpu_device pointer
500 * @vmid: vm instance to flush
501 *
502 * Flush the TLB for the requested page table (CIK).
503 */
504static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
505 uint32_t vmid)
506{
507 /* flush hdp cache */
508 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
509
510 /* bits 0-15 are the VM contexts0-15 */
511 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
512}
513
514/**
515 * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
516 *
517 * @adev: amdgpu_device pointer
518 * @cpu_pt_addr: cpu address of the page table
519 * @gpu_page_idx: entry in the page table to update
520 * @addr: dst addr to write into pte/pde
521 * @flags: access flags
522 *
523 * Update the page tables using the CPU.
524 */
525static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
526 void *cpu_pt_addr,
527 uint32_t gpu_page_idx,
528 uint64_t addr,
529 uint32_t flags)
530{
531 void __iomem *ptr = (void *)cpu_pt_addr;
532 uint64_t value;
533
534 /*
535 * PTE format on VI:
536 * 63:40 reserved
537 * 39:12 4k physical page base address
538 * 11:7 fragment
539 * 6 write
540 * 5 read
541 * 4 exe
542 * 3 reserved
543 * 2 snooped
544 * 1 system
545 * 0 valid
546 *
547 * PDE format on VI:
548 * 63:59 block fragment size
549 * 58:40 reserved
550 * 39:1 physical base address of PTE
551 * bits 5:1 must be 0.
552 * 0 valid
553 */
554 value = addr & 0x000000FFFFFFF000ULL;
555 value |= flags;
556 writeq(value, ptr + (gpu_page_idx * 8));
557
558 return 0;
559}
560
561/**
562 * gmc_v8_0_set_fault_enable_default - update VM fault handling
563 *
564 * @adev: amdgpu_device pointer
565 * @value: true redirects VM faults to the default page
566 */
567static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
568 bool value)
569{
570 u32 tmp;
571
572 tmp = RREG32(mmVM_CONTEXT1_CNTL);
573 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
574 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
575 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
576 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
577 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
578 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
579 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
580 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
581 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
582 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
583 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
584 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
585 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
586 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
587 WREG32(mmVM_CONTEXT1_CNTL, tmp);
588}
589
590/**
591 * gmc_v8_0_gart_enable - gart enable
592 *
593 * @adev: amdgpu_device pointer
594 *
595 * This sets up the TLBs, programs the page tables for VMID0,
596 * sets up the hw for VMIDs 1-15 which are allocated on
597 * demand, and sets up the global locations for the LDS, GDS,
598 * and GPUVM for FSA64 clients (CIK).
599 * Returns 0 for success, errors for failure.
600 */
601static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
602{
603 int r, i;
604 u32 tmp;
605
606 if (adev->gart.robj == NULL) {
607 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
608 return -EINVAL;
609 }
610 r = amdgpu_gart_table_vram_pin(adev);
611 if (r)
612 return r;
613 /* Setup TLB control */
614 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
615 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
616 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
617 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
618 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
619 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
620 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
621 /* Setup L2 cache */
622 tmp = RREG32(mmVM_L2_CNTL);
623 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
624 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
625 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
626 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
627 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
628 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
629 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
630 WREG32(mmVM_L2_CNTL, tmp);
631 tmp = RREG32(mmVM_L2_CNTL2);
632 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
633 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
634 WREG32(mmVM_L2_CNTL2, tmp);
635 tmp = RREG32(mmVM_L2_CNTL3);
636 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
637 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
638 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
639 WREG32(mmVM_L2_CNTL3, tmp);
640 /* XXX: set to enable PTE/PDE in system memory */
641 tmp = RREG32(mmVM_L2_CNTL4);
642 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
643 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
644 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
645 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
646 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
647 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
648 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
649 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
650 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
651 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
652 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
653 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
654 WREG32(mmVM_L2_CNTL4, tmp);
655 /* setup context0 */
656 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
657 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
658 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
659 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
660 (u32)(adev->dummy_page.addr >> 12));
661 WREG32(mmVM_CONTEXT0_CNTL2, 0);
662 tmp = RREG32(mmVM_CONTEXT0_CNTL);
663 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
664 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
665 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
666 WREG32(mmVM_CONTEXT0_CNTL, tmp);
667
668 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
669 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
670 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
671
672 /* empty context1-15 */
673 /* FIXME start with 4G, once using 2 level pt switch to full
674 * vm size space
675 */
676 /* set vm size, must be a multiple of 4 */
677 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
678 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
679 for (i = 1; i < 16; i++) {
680 if (i < 8)
681 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
682 adev->gart.table_addr >> 12);
683 else
684 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
685 adev->gart.table_addr >> 12);
686 }
687
688 /* enable context1-15 */
689 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
690 (u32)(adev->dummy_page.addr >> 12));
691 WREG32(mmVM_CONTEXT1_CNTL2, 4);
692 tmp = RREG32(mmVM_CONTEXT1_CNTL);
693 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
694 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
695 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
696 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
697 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
698 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
699 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
700 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
701 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
702 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
703 amdgpu_vm_block_size - 9);
704 WREG32(mmVM_CONTEXT1_CNTL, tmp);
705 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
706 gmc_v8_0_set_fault_enable_default(adev, false);
707 else
708 gmc_v8_0_set_fault_enable_default(adev, true);
709
710 gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
711 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
712 (unsigned)(adev->mc.gtt_size >> 20),
713 (unsigned long long)adev->gart.table_addr);
714 adev->gart.ready = true;
715 return 0;
716}
717
718static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
719{
720 int r;
721
722 if (adev->gart.robj) {
723 WARN(1, "R600 PCIE GART already initialized\n");
724 return 0;
725 }
726 /* Initialize common gart structure */
727 r = amdgpu_gart_init(adev);
728 if (r)
729 return r;
730 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
731 return amdgpu_gart_table_vram_alloc(adev);
732}
733
734/**
735 * gmc_v8_0_gart_disable - gart disable
736 *
737 * @adev: amdgpu_device pointer
738 *
739 * This disables all VM page table (CIK).
740 */
741static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
742{
743 u32 tmp;
744
745 /* Disable all tables */
746 WREG32(mmVM_CONTEXT0_CNTL, 0);
747 WREG32(mmVM_CONTEXT1_CNTL, 0);
748 /* Setup TLB control */
749 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
750 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
751 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
752 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
753 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
754 /* Setup L2 cache */
755 tmp = RREG32(mmVM_L2_CNTL);
756 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
757 WREG32(mmVM_L2_CNTL, tmp);
758 WREG32(mmVM_L2_CNTL2, 0);
759 amdgpu_gart_table_vram_unpin(adev);
760}
761
762/**
763 * gmc_v8_0_gart_fini - vm fini callback
764 *
765 * @adev: amdgpu_device pointer
766 *
767 * Tears down the driver GART/VM setup (CIK).
768 */
769static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
770{
771 amdgpu_gart_table_vram_free(adev);
772 amdgpu_gart_fini(adev);
773}
774
775/*
776 * vm
777 * VMID 0 is the physical GPU addresses as used by the kernel.
778 * VMIDs 1-15 are used for userspace clients and are handled
779 * by the amdgpu vm/hsa code.
780 */
781/**
782 * gmc_v8_0_vm_init - cik vm init callback
783 *
784 * @adev: amdgpu_device pointer
785 *
786 * Inits cik specific vm parameters (number of VMs, base of vram for
787 * VMIDs 1-15) (CIK).
788 * Returns 0 for success.
789 */
790static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
791{
792 /*
793 * number of VMs
794 * VMID 0 is reserved for System
795 * amdgpu graphics/compute will use VMIDs 1-7
796 * amdkfd will use VMIDs 8-15
797 */
798 adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
799 amdgpu_vm_manager_init(adev);
800
801 /* base offset of vram pages */
802 if (adev->flags & AMD_IS_APU) {
803 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
804 tmp <<= 22;
805 adev->vm_manager.vram_base_offset = tmp;
806 } else
807 adev->vm_manager.vram_base_offset = 0;
808
809 return 0;
810}
811
812/**
813 * gmc_v8_0_vm_fini - cik vm fini callback
814 *
815 * @adev: amdgpu_device pointer
816 *
817 * Tear down any asic specific VM setup (CIK).
818 */
819static void gmc_v8_0_vm_fini(struct amdgpu_device *adev)
820{
821}
822
823/**
824 * gmc_v8_0_vm_decode_fault - print human readable fault info
825 *
826 * @adev: amdgpu_device pointer
827 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
828 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
829 *
830 * Print human readable fault information (CIK).
831 */
832static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
833 u32 status, u32 addr, u32 mc_client)
834{
835 u32 mc_id;
836 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
837 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
838 PROTECTIONS);
839 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
840 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
841
842 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
843 MEMORY_CLIENT_ID);
844
845 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
846 protections, vmid, addr,
847 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
848 MEMORY_CLIENT_RW) ?
849 "write" : "read", block, mc_client, mc_id);
850}
851
852static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
853{
854 switch (mc_seq_vram_type) {
855 case MC_SEQ_MISC0__MT__GDDR1:
856 return AMDGPU_VRAM_TYPE_GDDR1;
857 case MC_SEQ_MISC0__MT__DDR2:
858 return AMDGPU_VRAM_TYPE_DDR2;
859 case MC_SEQ_MISC0__MT__GDDR3:
860 return AMDGPU_VRAM_TYPE_GDDR3;
861 case MC_SEQ_MISC0__MT__GDDR4:
862 return AMDGPU_VRAM_TYPE_GDDR4;
863 case MC_SEQ_MISC0__MT__GDDR5:
864 return AMDGPU_VRAM_TYPE_GDDR5;
865 case MC_SEQ_MISC0__MT__HBM:
866 return AMDGPU_VRAM_TYPE_HBM;
867 case MC_SEQ_MISC0__MT__DDR3:
868 return AMDGPU_VRAM_TYPE_DDR3;
869 default:
870 return AMDGPU_VRAM_TYPE_UNKNOWN;
871 }
872}
873
874static int gmc_v8_0_early_init(void *handle)
875{
876 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
877
878 gmc_v8_0_set_gart_funcs(adev);
879 gmc_v8_0_set_irq_funcs(adev);
880
881 return 0;
882}
883
884static int gmc_v8_0_late_init(void *handle)
885{
886 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
887
888 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
889 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
890 else
891 return 0;
892}
893
894#define mmMC_SEQ_MISC0_FIJI 0xA71
895
896static int gmc_v8_0_sw_init(void *handle)
897{
898 int r;
899 int dma_bits;
900 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
901
902 if (adev->flags & AMD_IS_APU) {
903 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
904 } else {
905 u32 tmp;
906
907 if (adev->asic_type == CHIP_FIJI)
908 tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
909 else
910 tmp = RREG32(mmMC_SEQ_MISC0);
911 tmp &= MC_SEQ_MISC0__MT__MASK;
912 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
913 }
914
915 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
916 if (r)
917 return r;
918
919 r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
920 if (r)
921 return r;
922
923 /* Adjust VM size here.
924 * Currently set to 4GB ((1 << 20) 4k pages).
925 * Max GPUVM size for cayman and SI is 40 bits.
926 */
927 adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
928
929 /* Set the internal MC address mask
930 * This is the max address of the GPU's
931 * internal address space.
932 */
933 adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
934
935 /* set DMA mask + need_dma32 flags.
936 * PCIE - can handle 40-bits.
937 * IGP - can handle 40-bits
938 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
939 */
940 adev->need_dma32 = false;
941 dma_bits = adev->need_dma32 ? 32 : 40;
942 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
943 if (r) {
944 adev->need_dma32 = true;
945 dma_bits = 32;
946 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
947 }
948 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
949 if (r) {
950 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
951 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
952 }
953
954 r = gmc_v8_0_init_microcode(adev);
955 if (r) {
956 DRM_ERROR("Failed to load mc firmware!\n");
957 return r;
958 }
959
960 r = gmc_v8_0_mc_init(adev);
961 if (r)
962 return r;
963
964 /* Memory manager */
965 r = amdgpu_bo_init(adev);
966 if (r)
967 return r;
968
969 r = gmc_v8_0_gart_init(adev);
970 if (r)
971 return r;
972
973 if (!adev->vm_manager.enabled) {
974 r = gmc_v8_0_vm_init(adev);
975 if (r) {
976 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
977 return r;
978 }
979 adev->vm_manager.enabled = true;
980 }
981
982 return r;
983}
984
985static int gmc_v8_0_sw_fini(void *handle)
986{
987 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
988
989 if (adev->vm_manager.enabled) {
990 amdgpu_vm_manager_fini(adev);
991 gmc_v8_0_vm_fini(adev);
992 adev->vm_manager.enabled = false;
993 }
994 gmc_v8_0_gart_fini(adev);
995 amdgpu_gem_force_release(adev);
996 amdgpu_bo_fini(adev);
997
998 return 0;
999}
1000
1001static int gmc_v8_0_hw_init(void *handle)
1002{
1003 int r;
1004 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1005
1006 gmc_v8_0_init_golden_registers(adev);
1007
1008 gmc_v8_0_mc_program(adev);
1009
1010 if (adev->asic_type == CHIP_TONGA) {
1011 r = gmc_v8_0_mc_load_microcode(adev);
1012 if (r) {
1013 DRM_ERROR("Failed to load MC firmware!\n");
1014 return r;
1015 }
1016 }
1017
1018 r = gmc_v8_0_gart_enable(adev);
1019 if (r)
1020 return r;
1021
1022 return r;
1023}
1024
1025static int gmc_v8_0_hw_fini(void *handle)
1026{
1027 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1028
1029 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1030 gmc_v8_0_gart_disable(adev);
1031
1032 return 0;
1033}
1034
1035static int gmc_v8_0_suspend(void *handle)
1036{
1037 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1038
1039 if (adev->vm_manager.enabled) {
1040 gmc_v8_0_vm_fini(adev);
1041 adev->vm_manager.enabled = false;
1042 }
1043 gmc_v8_0_hw_fini(adev);
1044
1045 return 0;
1046}
1047
1048static int gmc_v8_0_resume(void *handle)
1049{
1050 int r;
1051 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1052
1053 r = gmc_v8_0_hw_init(adev);
1054 if (r)
1055 return r;
1056
1057 if (!adev->vm_manager.enabled) {
1058 r = gmc_v8_0_vm_init(adev);
1059 if (r) {
1060 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1061 return r;
1062 }
1063 adev->vm_manager.enabled = true;
1064 }
1065
1066 return r;
1067}
1068
1069static bool gmc_v8_0_is_idle(void *handle)
1070{
1071 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1072 u32 tmp = RREG32(mmSRBM_STATUS);
1073
1074 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1075 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1076 return false;
1077
1078 return true;
1079}
1080
1081static int gmc_v8_0_wait_for_idle(void *handle)
1082{
1083 unsigned i;
1084 u32 tmp;
1085 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1086
1087 for (i = 0; i < adev->usec_timeout; i++) {
1088 /* read MC_STATUS */
1089 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1090 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1091 SRBM_STATUS__MCC_BUSY_MASK |
1092 SRBM_STATUS__MCD_BUSY_MASK |
1093 SRBM_STATUS__VMC_BUSY_MASK |
1094 SRBM_STATUS__VMC1_BUSY_MASK);
1095 if (!tmp)
1096 return 0;
1097 udelay(1);
1098 }
1099 return -ETIMEDOUT;
1100
1101}
1102
1103static bool gmc_v8_0_check_soft_reset(void *handle)
1104{
1105 u32 srbm_soft_reset = 0;
1106 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1107 u32 tmp = RREG32(mmSRBM_STATUS);
1108
1109 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1110 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1111 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1112
1113 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1114 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1115 if (!(adev->flags & AMD_IS_APU))
1116 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1117 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1118 }
1119 if (srbm_soft_reset) {
1120 adev->mc.srbm_soft_reset = srbm_soft_reset;
1121 return true;
1122 } else {
1123 adev->mc.srbm_soft_reset = 0;
1124 return false;
1125 }
1126}
1127
1128static int gmc_v8_0_pre_soft_reset(void *handle)
1129{
1130 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1131
1132 if (!adev->mc.srbm_soft_reset)
1133 return 0;
1134
1135 gmc_v8_0_mc_stop(adev, &adev->mc.save);
1136 if (gmc_v8_0_wait_for_idle(adev)) {
1137 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1138 }
1139
1140 return 0;
1141}
1142
1143static int gmc_v8_0_soft_reset(void *handle)
1144{
1145 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1146 u32 srbm_soft_reset;
1147
1148 if (!adev->mc.srbm_soft_reset)
1149 return 0;
1150 srbm_soft_reset = adev->mc.srbm_soft_reset;
1151
1152 if (srbm_soft_reset) {
1153 u32 tmp;
1154
1155 tmp = RREG32(mmSRBM_SOFT_RESET);
1156 tmp |= srbm_soft_reset;
1157 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1158 WREG32(mmSRBM_SOFT_RESET, tmp);
1159 tmp = RREG32(mmSRBM_SOFT_RESET);
1160
1161 udelay(50);
1162
1163 tmp &= ~srbm_soft_reset;
1164 WREG32(mmSRBM_SOFT_RESET, tmp);
1165 tmp = RREG32(mmSRBM_SOFT_RESET);
1166
1167 /* Wait a little for things to settle down */
1168 udelay(50);
1169 }
1170
1171 return 0;
1172}
1173
1174static int gmc_v8_0_post_soft_reset(void *handle)
1175{
1176 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1177
1178 if (!adev->mc.srbm_soft_reset)
1179 return 0;
1180
1181 gmc_v8_0_mc_resume(adev, &adev->mc.save);
1182 return 0;
1183}
1184
1185static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1186 struct amdgpu_irq_src *src,
1187 unsigned type,
1188 enum amdgpu_interrupt_state state)
1189{
1190 u32 tmp;
1191 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1192 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1193 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1194 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1195 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1196 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1197 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1198
1199 switch (state) {
1200 case AMDGPU_IRQ_STATE_DISABLE:
1201 /* system context */
1202 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1203 tmp &= ~bits;
1204 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1205 /* VMs */
1206 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1207 tmp &= ~bits;
1208 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1209 break;
1210 case AMDGPU_IRQ_STATE_ENABLE:
1211 /* system context */
1212 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1213 tmp |= bits;
1214 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1215 /* VMs */
1216 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1217 tmp |= bits;
1218 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1219 break;
1220 default:
1221 break;
1222 }
1223
1224 return 0;
1225}
1226
1227static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1228 struct amdgpu_irq_src *source,
1229 struct amdgpu_iv_entry *entry)
1230{
1231 u32 addr, status, mc_client;
1232
1233 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1234 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1235 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1236 /* reset addr and status */
1237 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1238
1239 if (!addr && !status)
1240 return 0;
1241
1242 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1243 gmc_v8_0_set_fault_enable_default(adev, false);
1244
1245 if (printk_ratelimit()) {
1246 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1247 entry->src_id, entry->src_data);
1248 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1249 addr);
1250 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1251 status);
1252 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
1253 }
1254
1255 return 0;
1256}
1257
1258static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1259 bool enable)
1260{
1261 uint32_t data;
1262
1263 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1264 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1265 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1266 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1267
1268 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1269 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1270 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1271
1272 data = RREG32(mmMC_HUB_MISC_VM_CG);
1273 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1274 WREG32(mmMC_HUB_MISC_VM_CG, data);
1275
1276 data = RREG32(mmMC_XPB_CLK_GAT);
1277 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1278 WREG32(mmMC_XPB_CLK_GAT, data);
1279
1280 data = RREG32(mmATC_MISC_CG);
1281 data |= ATC_MISC_CG__ENABLE_MASK;
1282 WREG32(mmATC_MISC_CG, data);
1283
1284 data = RREG32(mmMC_CITF_MISC_WR_CG);
1285 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1286 WREG32(mmMC_CITF_MISC_WR_CG, data);
1287
1288 data = RREG32(mmMC_CITF_MISC_RD_CG);
1289 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1290 WREG32(mmMC_CITF_MISC_RD_CG, data);
1291
1292 data = RREG32(mmMC_CITF_MISC_VM_CG);
1293 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1294 WREG32(mmMC_CITF_MISC_VM_CG, data);
1295
1296 data = RREG32(mmVM_L2_CG);
1297 data |= VM_L2_CG__ENABLE_MASK;
1298 WREG32(mmVM_L2_CG, data);
1299 } else {
1300 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1301 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1302 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1303
1304 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1305 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1306 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1307
1308 data = RREG32(mmMC_HUB_MISC_VM_CG);
1309 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1310 WREG32(mmMC_HUB_MISC_VM_CG, data);
1311
1312 data = RREG32(mmMC_XPB_CLK_GAT);
1313 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1314 WREG32(mmMC_XPB_CLK_GAT, data);
1315
1316 data = RREG32(mmATC_MISC_CG);
1317 data &= ~ATC_MISC_CG__ENABLE_MASK;
1318 WREG32(mmATC_MISC_CG, data);
1319
1320 data = RREG32(mmMC_CITF_MISC_WR_CG);
1321 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1322 WREG32(mmMC_CITF_MISC_WR_CG, data);
1323
1324 data = RREG32(mmMC_CITF_MISC_RD_CG);
1325 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1326 WREG32(mmMC_CITF_MISC_RD_CG, data);
1327
1328 data = RREG32(mmMC_CITF_MISC_VM_CG);
1329 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1330 WREG32(mmMC_CITF_MISC_VM_CG, data);
1331
1332 data = RREG32(mmVM_L2_CG);
1333 data &= ~VM_L2_CG__ENABLE_MASK;
1334 WREG32(mmVM_L2_CG, data);
1335 }
1336}
1337
1338static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1339 bool enable)
1340{
1341 uint32_t data;
1342
1343 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1344 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1345 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1346 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1347
1348 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1349 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1350 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1351
1352 data = RREG32(mmMC_HUB_MISC_VM_CG);
1353 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1354 WREG32(mmMC_HUB_MISC_VM_CG, data);
1355
1356 data = RREG32(mmMC_XPB_CLK_GAT);
1357 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1358 WREG32(mmMC_XPB_CLK_GAT, data);
1359
1360 data = RREG32(mmATC_MISC_CG);
1361 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1362 WREG32(mmATC_MISC_CG, data);
1363
1364 data = RREG32(mmMC_CITF_MISC_WR_CG);
1365 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1366 WREG32(mmMC_CITF_MISC_WR_CG, data);
1367
1368 data = RREG32(mmMC_CITF_MISC_RD_CG);
1369 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1370 WREG32(mmMC_CITF_MISC_RD_CG, data);
1371
1372 data = RREG32(mmMC_CITF_MISC_VM_CG);
1373 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1374 WREG32(mmMC_CITF_MISC_VM_CG, data);
1375
1376 data = RREG32(mmVM_L2_CG);
1377 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1378 WREG32(mmVM_L2_CG, data);
1379 } else {
1380 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1381 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1382 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1383
1384 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1385 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1386 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1387
1388 data = RREG32(mmMC_HUB_MISC_VM_CG);
1389 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1390 WREG32(mmMC_HUB_MISC_VM_CG, data);
1391
1392 data = RREG32(mmMC_XPB_CLK_GAT);
1393 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1394 WREG32(mmMC_XPB_CLK_GAT, data);
1395
1396 data = RREG32(mmATC_MISC_CG);
1397 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1398 WREG32(mmATC_MISC_CG, data);
1399
1400 data = RREG32(mmMC_CITF_MISC_WR_CG);
1401 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1402 WREG32(mmMC_CITF_MISC_WR_CG, data);
1403
1404 data = RREG32(mmMC_CITF_MISC_RD_CG);
1405 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1406 WREG32(mmMC_CITF_MISC_RD_CG, data);
1407
1408 data = RREG32(mmMC_CITF_MISC_VM_CG);
1409 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1410 WREG32(mmMC_CITF_MISC_VM_CG, data);
1411
1412 data = RREG32(mmVM_L2_CG);
1413 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1414 WREG32(mmVM_L2_CG, data);
1415 }
1416}
1417
1418static int gmc_v8_0_set_clockgating_state(void *handle,
1419 enum amd_clockgating_state state)
1420{
1421 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1422
1423 switch (adev->asic_type) {
1424 case CHIP_FIJI:
1425 fiji_update_mc_medium_grain_clock_gating(adev,
1426 state == AMD_CG_STATE_GATE ? true : false);
1427 fiji_update_mc_light_sleep(adev,
1428 state == AMD_CG_STATE_GATE ? true : false);
1429 break;
1430 default:
1431 break;
1432 }
1433 return 0;
1434}
1435
1436static int gmc_v8_0_set_powergating_state(void *handle,
1437 enum amd_powergating_state state)
1438{
1439 return 0;
1440}
1441
1442static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1443 .name = "gmc_v8_0",
1444 .early_init = gmc_v8_0_early_init,
1445 .late_init = gmc_v8_0_late_init,
1446 .sw_init = gmc_v8_0_sw_init,
1447 .sw_fini = gmc_v8_0_sw_fini,
1448 .hw_init = gmc_v8_0_hw_init,
1449 .hw_fini = gmc_v8_0_hw_fini,
1450 .suspend = gmc_v8_0_suspend,
1451 .resume = gmc_v8_0_resume,
1452 .is_idle = gmc_v8_0_is_idle,
1453 .wait_for_idle = gmc_v8_0_wait_for_idle,
1454 .check_soft_reset = gmc_v8_0_check_soft_reset,
1455 .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1456 .soft_reset = gmc_v8_0_soft_reset,
1457 .post_soft_reset = gmc_v8_0_post_soft_reset,
1458 .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1459 .set_powergating_state = gmc_v8_0_set_powergating_state,
1460};
1461
1462static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
1463 .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
1464 .set_pte_pde = gmc_v8_0_gart_set_pte_pde,
1465};
1466
1467static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1468 .set = gmc_v8_0_vm_fault_interrupt_state,
1469 .process = gmc_v8_0_process_interrupt,
1470};
1471
1472static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev)
1473{
1474 if (adev->gart.gart_funcs == NULL)
1475 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs;
1476}
1477
1478static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1479{
1480 adev->mc.vm_fault.num_types = 1;
1481 adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1482}
1483
1484const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
1485{
1486 .type = AMD_IP_BLOCK_TYPE_GMC,
1487 .major = 8,
1488 .minor = 0,
1489 .rev = 0,
1490 .funcs = &gmc_v8_0_ip_funcs,
1491};
1492
1493const struct amdgpu_ip_block_version gmc_v8_1_ip_block =
1494{
1495 .type = AMD_IP_BLOCK_TYPE_GMC,
1496 .major = 8,
1497 .minor = 1,
1498 .rev = 0,
1499 .funcs = &gmc_v8_0_ip_funcs,
1500};
1501
1502const struct amdgpu_ip_block_version gmc_v8_5_ip_block =
1503{
1504 .type = AMD_IP_BLOCK_TYPE_GMC,
1505 .major = 8,
1506 .minor = 5,
1507 .rev = 0,
1508 .funcs = &gmc_v8_0_ip_funcs,
1509};