1/*
   2 * Copyright 2009 Jerome Glisse.
   3 * All Rights Reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the
   7 * "Software"), to deal in the Software without restriction, including
   8 * without limitation the rights to use, copy, modify, merge, publish,
   9 * distribute, sub license, and/or sell copies of the Software, and to
  10 * permit persons to whom the Software is furnished to do so, subject to
  11 * the following conditions:
  12 *
  13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20 *
  21 * The above copyright notice and this permission notice (including the
  22 * next paragraph) shall be included in all copies or substantial portions
  23 * of the Software.
  24 *
  25 */
  26/*
  27 * Authors:
  28 *    Jerome Glisse <glisse@freedesktop.org>
  29 *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30 *    Dave Airlie
  31 */
  32
  33#include <linux/dma-mapping.h>
  34#include <linux/iommu.h>
  35#include <linux/pagemap.h>
  36#include <linux/sched/task.h>
  37#include <linux/sched/mm.h>
 
  38#include <linux/seq_file.h>
  39#include <linux/slab.h>
 
  40#include <linux/swap.h>
  41#include <linux/dma-buf.h>
  42#include <linux/sizes.h>
  43#include <linux/module.h>
  44
  45#include <drm/drm_drv.h>
  46#include <drm/ttm/ttm_bo.h>
  47#include <drm/ttm/ttm_placement.h>
  48#include <drm/ttm/ttm_range_manager.h>
  49#include <drm/ttm/ttm_tt.h>
  50
  51#include <drm/amdgpu_drm.h>
  52
  53#include "amdgpu.h"
  54#include "amdgpu_object.h"
  55#include "amdgpu_trace.h"
  56#include "amdgpu_amdkfd.h"
  57#include "amdgpu_sdma.h"
  58#include "amdgpu_ras.h"
  59#include "amdgpu_hmm.h"
  60#include "amdgpu_atomfirmware.h"
  61#include "amdgpu_res_cursor.h"
  62#include "bif/bif_4_1_d.h"
  63
  64MODULE_IMPORT_NS(DMA_BUF);
  65
  66#define AMDGPU_TTM_VRAM_MAX_DW_READ	((size_t)128)
 
  67
  68static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
  69				   struct ttm_tt *ttm,
  70				   struct ttm_resource *bo_mem);
  71static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
  72				      struct ttm_tt *ttm);
  73
  74static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  75				    unsigned int type,
  76				    uint64_t size_in_page)
  77{
  78	return ttm_range_man_init(&adev->mman.bdev, type,
  79				  false, size_in_page);
  80}
  81
  82/**
  83 * amdgpu_evict_flags - Compute placement flags
  84 *
  85 * @bo: The buffer object to evict
  86 * @placement: Possible destination(s) for evicted BO
  87 *
  88 * Fill in placement data when ttm_bo_evict() is called
  89 */
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  90static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  91				struct ttm_placement *placement)
  92{
  93	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  94	struct amdgpu_bo *abo;
  95	static const struct ttm_place placements = {
  96		.fpfn = 0,
  97		.lpfn = 0,
  98		.mem_type = TTM_PL_SYSTEM,
  99		.flags = 0
 100	};
 
 101
 102	/* Don't handle scatter gather BOs */
 103	if (bo->type == ttm_bo_type_sg) {
 104		placement->num_placement = 0;
 105		return;
 106	}
 107
 108	/* Object isn't an AMDGPU object so ignore */
 109	if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 110		placement->placement = &placements;
 
 111		placement->num_placement = 1;
 
 112		return;
 113	}
 114
 115	abo = ttm_to_amdgpu_bo(bo);
 116	if (abo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) {
 117		placement->num_placement = 0;
 118		return;
 119	}
 120
 121	switch (bo->resource->mem_type) {
 122	case AMDGPU_PL_GDS:
 123	case AMDGPU_PL_GWS:
 124	case AMDGPU_PL_OA:
 125	case AMDGPU_PL_DOORBELL:
 126		placement->num_placement = 0;
 127		return;
 128
 129	case TTM_PL_VRAM:
 130		if (!adev->mman.buffer_funcs_enabled) {
 131			/* Move to system memory */
 132			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 133
 134		} else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 135			   !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 136			   amdgpu_res_cpu_visible(adev, bo->resource)) {
 137
 138			/* Try evicting to the CPU inaccessible part of VRAM
 139			 * first, but only set GTT as busy placement, so this
 140			 * BO will be evicted to GTT rather than causing other
 141			 * BOs to be evicted from VRAM
 142			 */
 143			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 144							AMDGPU_GEM_DOMAIN_GTT |
 145							AMDGPU_GEM_DOMAIN_CPU);
 146			abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 147			abo->placements[0].lpfn = 0;
 148			abo->placements[0].flags |= TTM_PL_FLAG_DESIRED;
 149		} else {
 150			/* Move to GTT memory */
 151			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT |
 152							AMDGPU_GEM_DOMAIN_CPU);
 
 
 
 
 
 
 
 
 
 
 
 
 153		}
 154		break;
 155	case TTM_PL_TT:
 156	case AMDGPU_PL_PREEMPT:
 157	default:
 158		amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 159		break;
 160	}
 161	*placement = abo->placement;
 162}
 163
 164/**
 165 * amdgpu_ttm_map_buffer - Map memory into the GART windows
 166 * @bo: buffer object to map
 167 * @mem: memory object to map
 168 * @mm_cur: range to map
 169 * @window: which GART window to use
 170 * @ring: DMA ring to use for the copy
 171 * @tmz: if we should setup a TMZ enabled mapping
 172 * @size: in number of bytes to map, out number of bytes mapped
 173 * @addr: resulting address inside the MC address space
 174 *
 175 * Setup one of the GART windows to access a specific piece of memory or return
 176 * the physical address for local memory.
 177 */
 178static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 179				 struct ttm_resource *mem,
 180				 struct amdgpu_res_cursor *mm_cur,
 181				 unsigned int window, struct amdgpu_ring *ring,
 182				 bool tmz, uint64_t *size, uint64_t *addr)
 183{
 184	struct amdgpu_device *adev = ring->adev;
 185	unsigned int offset, num_pages, num_dw, num_bytes;
 186	uint64_t src_addr, dst_addr;
 187	struct amdgpu_job *job;
 188	void *cpu_addr;
 189	uint64_t flags;
 190	unsigned int i;
 191	int r;
 192
 193	BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 194	       AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 195
 196	if (WARN_ON(mem->mem_type == AMDGPU_PL_PREEMPT))
 197		return -EINVAL;
 198
 199	/* Map only what can't be accessed directly */
 200	if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 201		*addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
 202			mm_cur->start;
 203		return 0;
 204	}
 205
 206
 207	/*
 208	 * If start begins at an offset inside the page, then adjust the size
 209	 * and addr accordingly
 210	 */
 211	offset = mm_cur->start & ~PAGE_MASK;
 212
 213	num_pages = PFN_UP(*size + offset);
 214	num_pages = min_t(uint32_t, num_pages, AMDGPU_GTT_MAX_TRANSFER_SIZE);
 215
 216	*size = min(*size, (uint64_t)num_pages * PAGE_SIZE - offset);
 217
 218	*addr = adev->gmc.gart_start;
 219	*addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 220		AMDGPU_GPU_PAGE_SIZE;
 221	*addr += offset;
 222
 223	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 224	num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
 225
 226	r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
 227				     AMDGPU_FENCE_OWNER_UNDEFINED,
 228				     num_dw * 4 + num_bytes,
 229				     AMDGPU_IB_POOL_DELAYED, &job);
 230	if (r)
 231		return r;
 232
 233	src_addr = num_dw * 4;
 234	src_addr += job->ibs[0].gpu_addr;
 235
 236	dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 237	dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 238	amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 239				dst_addr, num_bytes, false);
 240
 241	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 242	WARN_ON(job->ibs[0].length_dw > num_dw);
 243
 244	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 245	if (tmz)
 246		flags |= AMDGPU_PTE_TMZ;
 247
 248	cpu_addr = &job->ibs[0].ptr[num_dw];
 
 
 
 249
 250	if (mem->mem_type == TTM_PL_TT) {
 251		dma_addr_t *dma_addr;
 
 
 252
 253		dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];
 254		amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, cpu_addr);
 255	} else {
 256		dma_addr_t dma_address;
 
 
 257
 258		dma_address = mm_cur->start;
 259		dma_address += adev->vm_manager.vram_base_offset;
 
 
 
 260
 261		for (i = 0; i < num_pages; ++i) {
 262			amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, &dma_address,
 263					flags, cpu_addr);
 264			dma_address += PAGE_SIZE;
 265		}
 
 
 266	}
 267
 268	dma_fence_put(amdgpu_job_submit(job));
 269	return 0;
 270}
 271
 272/**
 273 * amdgpu_ttm_copy_mem_to_mem - Helper function for copy
 274 * @adev: amdgpu device
 275 * @src: buffer/address where to read from
 276 * @dst: buffer/address where to write to
 277 * @size: number of bytes to copy
 278 * @tmz: if a secure copy should be used
 279 * @resv: resv object to sync to
 280 * @f: Returns the last fence if multiple jobs are submitted.
 281 *
 282 * The function copies @size bytes from {src->mem + src->offset} to
 283 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 284 * move and different for a BO to BO copy.
 285 *
 286 */
 287int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 288			       const struct amdgpu_copy_mem *src,
 289			       const struct amdgpu_copy_mem *dst,
 290			       uint64_t size, bool tmz,
 291			       struct dma_resv *resv,
 292			       struct dma_fence **f)
 293{
 
 294	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 295	struct amdgpu_res_cursor src_mm, dst_mm;
 
 
 
 296	struct dma_fence *fence = NULL;
 297	int r = 0;
 
 
 298
 299	if (!adev->mman.buffer_funcs_enabled) {
 300		DRM_ERROR("Trying to move memory with ring turned off.\n");
 301		return -EINVAL;
 302	}
 303
 304	amdgpu_res_first(src->mem, src->offset, size, &src_mm);
 305	amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm);
 306
 307	mutex_lock(&adev->mman.gtt_window_lock);
 308	while (src_mm.remaining) {
 309		uint64_t from, to, cur_size;
 310		struct dma_fence *next;
 311
 312		/* Never copy more than 256MiB at once to avoid a timeout */
 313		cur_size = min3(src_mm.size, dst_mm.size, 256ULL << 20);
 314
 315		/* Map src to window 0 and dst to window 1. */
 316		r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,
 317					  0, ring, tmz, &cur_size, &from);
 318		if (r)
 319			goto error;
 320
 321		r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,
 322					  1, ring, tmz, &cur_size, &to);
 323		if (r)
 324			goto error;
 325
 326		r = amdgpu_copy_buffer(ring, from, to, cur_size,
 327				       resv, &next, false, true, tmz);
 
 328		if (r)
 329			goto error;
 330
 331		dma_fence_put(fence);
 332		fence = next;
 333
 334		amdgpu_res_next(&src_mm, cur_size);
 335		amdgpu_res_next(&dst_mm, cur_size);
 336	}
 337error:
 338	mutex_unlock(&adev->mman.gtt_window_lock);
 339	if (f)
 340		*f = dma_fence_get(fence);
 341	dma_fence_put(fence);
 342	return r;
 343}
 344
 345/*
 346 * amdgpu_move_blit - Copy an entire buffer to another buffer
 347 *
 348 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 349 * help move buffers to and from VRAM.
 350 */
 351static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 352			    bool evict,
 353			    struct ttm_resource *new_mem,
 354			    struct ttm_resource *old_mem)
 355{
 356	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 357	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 358	struct amdgpu_copy_mem src, dst;
 359	struct dma_fence *fence = NULL;
 360	int r;
 361
 362	src.bo = bo;
 363	dst.bo = bo;
 364	src.mem = old_mem;
 365	dst.mem = new_mem;
 366	src.offset = 0;
 367	dst.offset = 0;
 368
 369	r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 370				       new_mem->size,
 371				       amdgpu_bo_encrypted(abo),
 372				       bo->base.resv, &fence);
 373	if (r)
 374		goto error;
 375
 376	/* clear the space being freed */
 377	if (old_mem->mem_type == TTM_PL_VRAM &&
 378	    (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 379		struct dma_fence *wipe_fence = NULL;
 
 
 380
 381		r = amdgpu_fill_buffer(abo, AMDGPU_POISON, NULL, &wipe_fence,
 382					false);
 383		if (r) {
 384			goto error;
 385		} else if (wipe_fence) {
 386			dma_fence_put(fence);
 387			fence = wipe_fence;
 388		}
 389	}
 390
 391	/* Always block for VM page tables before committing the new location */
 392	if (bo->type == ttm_bo_type_kernel)
 393		r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
 394	else
 395		r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
 396	dma_fence_put(fence);
 397	return r;
 398
 399error:
 400	if (fence)
 401		dma_fence_wait(fence, false);
 402	dma_fence_put(fence);
 403	return r;
 404}
 405
 406/**
 407 * amdgpu_res_cpu_visible - Check that resource can be accessed by CPU
 408 * @adev: amdgpu device
 409 * @res: the resource to check
 410 *
 411 * Returns: true if the full resource is CPU visible, false otherwise.
 412 */
 413bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,
 414			    struct ttm_resource *res)
 415{
 416	struct amdgpu_res_cursor cursor;
 417
 418	if (!res)
 419		return false;
 420
 421	if (res->mem_type == TTM_PL_SYSTEM || res->mem_type == TTM_PL_TT ||
 422	    res->mem_type == AMDGPU_PL_PREEMPT || res->mem_type == AMDGPU_PL_DOORBELL)
 423		return true;
 424
 425	if (res->mem_type != TTM_PL_VRAM)
 426		return false;
 427
 428	amdgpu_res_first(res, 0, res->size, &cursor);
 429	while (cursor.remaining) {
 430		if ((cursor.start + cursor.size) > adev->gmc.visible_vram_size)
 431			return false;
 432		amdgpu_res_next(&cursor, cursor.size);
 
 
 
 
 
 
 
 
 
 433	}
 434
 435	return true;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 436}
 437
 438/*
 439 * amdgpu_res_copyable - Check that memory can be accessed by ttm_bo_move_memcpy
 440 *
 441 * Called by amdgpu_bo_move()
 442 */
 443static bool amdgpu_res_copyable(struct amdgpu_device *adev,
 444				struct ttm_resource *mem)
 445{
 446	if (!amdgpu_res_cpu_visible(adev, mem))
 447		return false;
 448
 449	/* ttm_resource_ioremap only supports contiguous memory */
 450	if (mem->mem_type == TTM_PL_VRAM &&
 451	    !(mem->placement & TTM_PL_FLAG_CONTIGUOUS))
 452		return false;
 453
 454	return true;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 455}
 456
 457/*
 458 * amdgpu_bo_move - Move a buffer object to a new memory location
 459 *
 460 * Called by ttm_bo_handle_move_mem()
 461 */
 462static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 463			  struct ttm_operation_ctx *ctx,
 464			  struct ttm_resource *new_mem,
 465			  struct ttm_place *hop)
 466{
 467	struct amdgpu_device *adev;
 468	struct amdgpu_bo *abo;
 469	struct ttm_resource *old_mem = bo->resource;
 470	int r;
 471
 472	if (new_mem->mem_type == TTM_PL_TT ||
 473	    new_mem->mem_type == AMDGPU_PL_PREEMPT) {
 474		r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
 475		if (r)
 476			return r;
 477	}
 478
 479	abo = ttm_to_amdgpu_bo(bo);
 480	adev = amdgpu_ttm_adev(bo->bdev);
 481
 482	if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM &&
 483			 bo->ttm == NULL)) {
 484		amdgpu_bo_move_notify(bo, evict, new_mem);
 485		ttm_bo_move_null(bo, new_mem);
 486		return 0;
 487	}
 488	if (old_mem->mem_type == TTM_PL_SYSTEM &&
 489	    (new_mem->mem_type == TTM_PL_TT ||
 490	     new_mem->mem_type == AMDGPU_PL_PREEMPT)) {
 491		amdgpu_bo_move_notify(bo, evict, new_mem);
 492		ttm_bo_move_null(bo, new_mem);
 493		return 0;
 494	}
 495	if ((old_mem->mem_type == TTM_PL_TT ||
 496	     old_mem->mem_type == AMDGPU_PL_PREEMPT) &&
 497	    new_mem->mem_type == TTM_PL_SYSTEM) {
 498		r = ttm_bo_wait_ctx(bo, ctx);
 499		if (r)
 500			return r;
 501
 502		amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
 503		amdgpu_bo_move_notify(bo, evict, new_mem);
 504		ttm_resource_free(bo, &bo->resource);
 505		ttm_bo_assign_mem(bo, new_mem);
 506		return 0;
 507	}
 508
 509	if (old_mem->mem_type == AMDGPU_PL_GDS ||
 510	    old_mem->mem_type == AMDGPU_PL_GWS ||
 511	    old_mem->mem_type == AMDGPU_PL_OA ||
 512	    old_mem->mem_type == AMDGPU_PL_DOORBELL ||
 513	    new_mem->mem_type == AMDGPU_PL_GDS ||
 514	    new_mem->mem_type == AMDGPU_PL_GWS ||
 515	    new_mem->mem_type == AMDGPU_PL_OA ||
 516	    new_mem->mem_type == AMDGPU_PL_DOORBELL) {
 517		/* Nothing to save here */
 518		amdgpu_bo_move_notify(bo, evict, new_mem);
 519		ttm_bo_move_null(bo, new_mem);
 520		return 0;
 521	}
 522
 523	if (bo->type == ttm_bo_type_device &&
 524	    new_mem->mem_type == TTM_PL_VRAM &&
 525	    old_mem->mem_type != TTM_PL_VRAM) {
 526		/* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 527		 * accesses the BO after it's moved.
 528		 */
 529		abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 530	}
 531
 532	if (adev->mman.buffer_funcs_enabled &&
 533	    ((old_mem->mem_type == TTM_PL_SYSTEM &&
 534	      new_mem->mem_type == TTM_PL_VRAM) ||
 535	     (old_mem->mem_type == TTM_PL_VRAM &&
 536	      new_mem->mem_type == TTM_PL_SYSTEM))) {
 537		hop->fpfn = 0;
 538		hop->lpfn = 0;
 539		hop->mem_type = TTM_PL_TT;
 540		hop->flags = TTM_PL_FLAG_TEMPORARY;
 541		return -EMULTIHOP;
 542	}
 543
 544	amdgpu_bo_move_notify(bo, evict, new_mem);
 545	if (adev->mman.buffer_funcs_enabled)
 546		r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
 547	else
 548		r = -ENODEV;
 549
 550	if (r) {
 551		/* Check that all memory is CPU accessible */
 552		if (!amdgpu_res_copyable(adev, old_mem) ||
 553		    !amdgpu_res_copyable(adev, new_mem)) {
 554			pr_err("Move buffer fallback to memcpy unavailable\n");
 555			return r;
 556		}
 557
 558		r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 559		if (r)
 560			return r;
 561	}
 562
 563	/* update statistics after the move */
 564	if (evict)
 565		atomic64_inc(&adev->num_evictions);
 566	atomic64_add(bo->base.size, &adev->num_bytes_moved);
 567	return 0;
 568}
 569
 570/*
 571 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 572 *
 573 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 574 */
 575static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,
 576				     struct ttm_resource *mem)
 577{
 
 578	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 579
 
 
 
 
 
 
 
 580	switch (mem->mem_type) {
 581	case TTM_PL_SYSTEM:
 582		/* system memory */
 583		return 0;
 584	case TTM_PL_TT:
 585	case AMDGPU_PL_PREEMPT:
 586		break;
 587	case TTM_PL_VRAM:
 588		mem->bus.offset = mem->start << PAGE_SHIFT;
 589
 590		if (adev->mman.aper_base_kaddr &&
 591		    mem->placement & TTM_PL_FLAG_CONTIGUOUS)
 592			mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 593					mem->bus.offset;
 594
 595		mem->bus.offset += adev->gmc.aper_base;
 596		mem->bus.is_iomem = true;
 597		break;
 598	case AMDGPU_PL_DOORBELL:
 599		mem->bus.offset = mem->start << PAGE_SHIFT;
 600		mem->bus.offset += adev->doorbell.base;
 601		mem->bus.is_iomem = true;
 602		mem->bus.caching = ttm_uncached;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 603		break;
 604	default:
 605		return -EINVAL;
 606	}
 607	return 0;
 608}
 609
 610static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 611					   unsigned long page_offset)
 612{
 613	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 614	struct amdgpu_res_cursor cursor;
 615
 616	amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0,
 617			 &cursor);
 618
 619	if (bo->resource->mem_type == AMDGPU_PL_DOORBELL)
 620		return ((uint64_t)(adev->doorbell.base + cursor.start)) >> PAGE_SHIFT;
 621
 622	return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT;
 623}
 624
 625/**
 626 * amdgpu_ttm_domain_start - Returns GPU start address
 627 * @adev: amdgpu device object
 628 * @type: type of the memory
 629 *
 630 * Returns:
 631 * GPU start address of a memory domain
 632 */
 633
 634uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 635{
 636	switch (type) {
 637	case TTM_PL_TT:
 638		return adev->gmc.gart_start;
 639	case TTM_PL_VRAM:
 640		return adev->gmc.vram_start;
 641	}
 642
 643	return 0;
 644}
 645
 646/*
 647 * TTM backend functions.
 648 */
 
 
 
 
 
 649struct amdgpu_ttm_tt {
 650	struct ttm_tt	ttm;
 651	struct drm_gem_object	*gobj;
 652	u64			offset;
 653	uint64_t		userptr;
 654	struct task_struct	*usertask;
 655	uint32_t		userflags;
 656	bool			bound;
 657	int32_t			pool_id;
 
 
 658};
 659
 660#define ttm_to_amdgpu_ttm_tt(ptr)	container_of(ptr, struct amdgpu_ttm_tt, ttm)
 661
 662#ifdef CONFIG_DRM_AMDGPU_USERPTR
 663/*
 664 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 665 * memory and start HMM tracking CPU page table update
 666 *
 667 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 668 * once afterwards to stop HMM tracking
 669 */
 670int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages,
 671				 struct hmm_range **range)
 672{
 673	struct ttm_tt *ttm = bo->tbo.ttm;
 674	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 675	unsigned long start = gtt->userptr;
 676	struct vm_area_struct *vma;
 677	struct mm_struct *mm;
 678	bool readonly;
 679	int r = 0;
 680
 681	/* Make sure get_user_pages_done() can cleanup gracefully */
 682	*range = NULL;
 683
 684	mm = bo->notifier.mm;
 685	if (unlikely(!mm)) {
 686		DRM_DEBUG_DRIVER("BO is not registered?\n");
 687		return -EFAULT;
 688	}
 689
 690	if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 691		return -ESRCH;
 692
 693	mmap_read_lock(mm);
 694	vma = vma_lookup(mm, start);
 695	if (unlikely(!vma)) {
 696		r = -EFAULT;
 697		goto out_unlock;
 698	}
 699	if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 700		vma->vm_file)) {
 701		r = -EPERM;
 702		goto out_unlock;
 703	}
 704
 705	readonly = amdgpu_ttm_tt_is_readonly(ttm);
 706	r = amdgpu_hmm_range_get_pages(&bo->notifier, start, ttm->num_pages,
 707				       readonly, NULL, pages, range);
 708out_unlock:
 709	mmap_read_unlock(mm);
 710	if (r)
 711		pr_debug("failed %d to get user pages 0x%lx\n", r, start);
 712
 713	mmput(mm);
 
 714
 715	return r;
 716}
 
 
 
 717
 718/* amdgpu_ttm_tt_discard_user_pages - Discard range and pfn array allocations
 719 */
 720void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm,
 721				      struct hmm_range *range)
 722{
 723	struct amdgpu_ttm_tt *gtt = (void *)ttm;
 724
 725	if (gtt && gtt->userptr && range)
 726		amdgpu_hmm_range_get_pages_done(range);
 727}
 
 
 728
 729/*
 730 * amdgpu_ttm_tt_get_user_pages_done - stop HMM track the CPU page table change
 731 * Check if the pages backing this ttm range have been invalidated
 732 *
 733 * Returns: true if pages are still valid
 734 */
 735bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,
 736				       struct hmm_range *range)
 737{
 738	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 739
 740	if (!gtt || !gtt->userptr || !range)
 741		return false;
 742
 743	DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
 744		gtt->userptr, ttm->num_pages);
 
 745
 746	WARN_ONCE(!range->hmm_pfns, "No user pages to check\n");
 
 747
 748	return !amdgpu_hmm_range_get_pages_done(range);
 749}
 750#endif
 751
 752/*
 753 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 754 *
 755 * Called by amdgpu_cs_list_validate(). This creates the page list
 756 * that backs user memory and will ultimately be mapped into the device
 757 * address space.
 758 */
 759void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 760{
 761	unsigned long i;
 762
 763	for (i = 0; i < ttm->num_pages; ++i)
 764		ttm->pages[i] = pages ? pages[i] : NULL;
 
 
 
 765}
 766
 767/*
 768 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
 769 *
 770 * Called by amdgpu_ttm_backend_bind()
 771 **/
 772static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev,
 773				     struct ttm_tt *ttm)
 774{
 775	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 776	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 
 
 
 777	int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 778	enum dma_data_direction direction = write ?
 779		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 780	int r;
 781
 782	/* Allocate an SG array and squash pages into it */
 783	r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 784				      (u64)ttm->num_pages << PAGE_SHIFT,
 785				      GFP_KERNEL);
 786	if (r)
 787		goto release_sg;
 788
 789	/* Map SG to device */
 790	r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
 791	if (r)
 792		goto release_sg;
 793
 794	/* convert SG to linear array of pages and dma addresses */
 795	drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 796				       ttm->num_pages);
 797
 798	return 0;
 799
 800release_sg:
 801	kfree(ttm->sg);
 802	ttm->sg = NULL;
 803	return r;
 804}
 805
 806/*
 807 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 808 */
 809static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
 810					struct ttm_tt *ttm)
 811{
 812	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 813	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 
 
 814	int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 815	enum dma_data_direction direction = write ?
 816		DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 817
 818	/* double check that we don't free the table twice */
 819	if (!ttm->sg || !ttm->sg->sgl)
 820		return;
 821
 822	/* unmap the pages mapped to the device */
 823	dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
 824	sg_free_table(ttm->sg);
 825}
 826
 827/*
 828 * total_pages is constructed as MQD0+CtrlStack0 + MQD1+CtrlStack1 + ...
 829 * MQDn+CtrlStackn where n is the number of XCCs per partition.
 830 * pages_per_xcc is the size of one MQD+CtrlStack. The first page is MQD
 831 * and uses memory type default, UC. The rest of pages_per_xcc are
 832 * Ctrl stack and modify their memory type to NC.
 833 */
 834static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev,
 835				struct ttm_tt *ttm, uint64_t flags)
 836{
 837	struct amdgpu_ttm_tt *gtt = (void *)ttm;
 838	uint64_t total_pages = ttm->num_pages;
 839	int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp);
 840	uint64_t page_idx, pages_per_xcc;
 841	int i;
 842	uint64_t ctrl_flags = (flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) |
 843			AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
 844
 845	pages_per_xcc = total_pages;
 846	do_div(pages_per_xcc, num_xcc);
 847
 848	for (i = 0, page_idx = 0; i < num_xcc; i++, page_idx += pages_per_xcc) {
 849		/* MQD page: use default flags */
 850		amdgpu_gart_bind(adev,
 851				gtt->offset + (page_idx << PAGE_SHIFT),
 852				1, &gtt->ttm.dma_address[page_idx], flags);
 853		/*
 854		 * Ctrl pages - modify the memory type to NC (ctrl_flags) from
 855		 * the second page of the BO onward.
 856		 */
 857		amdgpu_gart_bind(adev,
 858				gtt->offset + ((page_idx + 1) << PAGE_SHIFT),
 859				pages_per_xcc - 1,
 860				&gtt->ttm.dma_address[page_idx + 1],
 861				ctrl_flags);
 862	}
 863}
 864
 865static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 866				 struct ttm_buffer_object *tbo,
 867				 uint64_t flags)
 868{
 869	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 870	struct ttm_tt *ttm = tbo->ttm;
 871	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 872
 873	if (amdgpu_bo_encrypted(abo))
 874		flags |= AMDGPU_PTE_TMZ;
 875
 876	if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
 877		amdgpu_ttm_gart_bind_gfx9_mqd(adev, ttm, flags);
 878	} else {
 879		amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 880				 gtt->ttm.dma_address, flags);
 881	}
 882	gtt->bound = true;
 
 883}
 884
 885/*
 886 * amdgpu_ttm_backend_bind - Bind GTT memory
 887 *
 888 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
 889 * This handles binding GTT memory to the device address space.
 890 */
 891static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
 892				   struct ttm_tt *ttm,
 893				   struct ttm_resource *bo_mem)
 894{
 895	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 896	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 897	uint64_t flags;
 898	int r;
 899
 900	if (!bo_mem)
 901		return -EINVAL;
 902
 903	if (gtt->bound)
 904		return 0;
 905
 906	if (gtt->userptr) {
 907		r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
 908		if (r) {
 909			DRM_ERROR("failed to pin userptr\n");
 910			return r;
 911		}
 912	} else if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) {
 913		if (!ttm->sg) {
 914			struct dma_buf_attachment *attach;
 915			struct sg_table *sgt;
 916
 917			attach = gtt->gobj->import_attach;
 918			sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
 919			if (IS_ERR(sgt))
 920				return PTR_ERR(sgt);
 921
 922			ttm->sg = sgt;
 923		}
 924
 925		drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 926					       ttm->num_pages);
 927	}
 928
 929	if (!ttm->num_pages) {
 930		WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
 931		     ttm->num_pages, bo_mem, ttm);
 932	}
 933
 934	if (bo_mem->mem_type != TTM_PL_TT ||
 935	    !amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
 936		gtt->offset = AMDGPU_BO_INVALID_OFFSET;
 937		return 0;
 938	}
 939
 940	/* compute PTE flags relevant to this BO memory */
 941	flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
 942
 943	/* bind pages into GART page tables */
 944	gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 945	amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 946			 gtt->ttm.dma_address, flags);
 947	gtt->bound = true;
 948	return 0;
 949}
 950
 951/*
 952 * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
 953 * through AGP or GART aperture.
 954 *
 955 * If bo is accessible through AGP aperture, then use AGP aperture
 956 * to access bo; otherwise allocate logical space in GART aperture
 957 * and map bo to GART aperture.
 958 */
 959int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 960{
 961	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 962	struct ttm_operation_ctx ctx = { false, false };
 963	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
 964	struct ttm_placement placement;
 965	struct ttm_place placements;
 966	struct ttm_resource *tmp;
 967	uint64_t addr, flags;
 968	int r;
 969
 970	if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET)
 971		return 0;
 972
 973	addr = amdgpu_gmc_agp_addr(bo);
 974	if (addr != AMDGPU_BO_INVALID_OFFSET)
 975		return 0;
 
 
 
 976
 977	/* allocate GART space */
 978	placement.num_placement = 1;
 979	placement.placement = &placements;
 980	placements.fpfn = 0;
 981	placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 982	placements.mem_type = TTM_PL_TT;
 983	placements.flags = bo->resource->placement;
 984
 985	r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
 986	if (unlikely(r))
 
 
 987		return r;
 
 988
 989	/* compute PTE flags for this buffer object */
 990	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp);
 991
 992	/* Bind pages */
 993	gtt->offset = (u64)tmp->start << PAGE_SHIFT;
 994	amdgpu_ttm_gart_bind(adev, bo, flags);
 995	amdgpu_gart_invalidate_tlb(adev);
 996	ttm_resource_free(bo, &bo->resource);
 997	ttm_bo_assign_mem(bo, tmp);
 998
 
 
 
 
 
 
 
 
 999	return 0;
1000}
1001
1002/*
1003 * amdgpu_ttm_recover_gart - Rebind GTT pages
1004 *
1005 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1006 * rebind GTT pages during a GPU reset.
1007 */
1008void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1009{
1010	struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1011	uint64_t flags;
1012
1013	if (!tbo->ttm)
1014		return;
1015
1016	flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource);
1017	amdgpu_ttm_gart_bind(adev, tbo, flags);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1018}
1019
1020/*
1021 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1022 *
1023 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1024 * ttm_tt_destroy().
1025 */
1026static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
1027				      struct ttm_tt *ttm)
1028{
1029	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1030	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1031
1032	/* if the pages have userptr pinning then clear that first */
1033	if (gtt->userptr) {
1034		amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1035	} else if (ttm->sg && gtt->gobj->import_attach) {
1036		struct dma_buf_attachment *attach;
1037
1038		attach = gtt->gobj->import_attach;
1039		dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1040		ttm->sg = NULL;
1041	}
1042
1043	if (!gtt->bound)
1044		return;
 
1045
1046	if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1047		return;
 
1048
1049	/* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1050	amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1051	gtt->bound = false;
1052}
1053
1054static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
1055				       struct ttm_tt *ttm)
1056{
1057	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1058
1059	if (gtt->usertask)
1060		put_task_struct(gtt->usertask);
1061
1062	ttm_tt_fini(&gtt->ttm);
1063	kfree(gtt);
1064}
1065
1066/**
1067 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1068 *
1069 * @bo: The buffer object to create a GTT ttm_tt object around
1070 * @page_flags: Page flags to be added to the ttm_tt object
1071 *
1072 * Called by ttm_tt_create().
1073 */
1074static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1075					   uint32_t page_flags)
1076{
1077	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1078	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1079	struct amdgpu_ttm_tt *gtt;
1080	enum ttm_caching caching;
 
1081
1082	gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1083	if (!gtt)
1084		return NULL;
1085
1086	gtt->gobj = &bo->base;
1087	if (adev->gmc.mem_partitions && abo->xcp_id >= 0)
1088		gtt->pool_id = KFD_XCP_MEM_ID(adev, abo->xcp_id);
1089	else
1090		gtt->pool_id = abo->xcp_id;
1091
1092	if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1093		caching = ttm_write_combined;
1094	else
1095		caching = ttm_cached;
1096
1097	/* allocate space for the uninitialized page entries */
1098	if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1099		kfree(gtt);
1100		return NULL;
1101	}
1102	return &gtt->ttm;
 
1103}
1104
1105/*
1106 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1107 *
1108 * Map the pages of a ttm_tt object to an address space visible
1109 * to the underlying device.
1110 */
1111static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
1112				  struct ttm_tt *ttm,
1113				  struct ttm_operation_ctx *ctx)
1114{
1115	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1116	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1117	struct ttm_pool *pool;
1118	pgoff_t i;
1119	int ret;
1120
1121	/* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1122	if (gtt->userptr) {
 
 
1123		ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1124		if (!ttm->sg)
1125			return -ENOMEM;
 
 
 
1126		return 0;
1127	}
1128
1129	if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL)
 
 
 
1130		return 0;
 
1131
1132	if (adev->mman.ttm_pools && gtt->pool_id >= 0)
1133		pool = &adev->mman.ttm_pools[gtt->pool_id];
1134	else
1135		pool = &adev->mman.bdev.pool;
1136	ret = ttm_pool_alloc(pool, ttm, ctx);
1137	if (ret)
1138		return ret;
1139
1140	for (i = 0; i < ttm->num_pages; ++i)
1141		ttm->pages[i]->mapping = bdev->dev_mapping;
 
 
 
1142
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1143	return 0;
1144}
1145
1146/*
1147 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1148 *
1149 * Unmaps pages of a ttm_tt object from the device address space and
1150 * unpopulates the page array backing it.
1151 */
1152static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
1153				     struct ttm_tt *ttm)
1154{
1155	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1156	struct amdgpu_device *adev;
1157	struct ttm_pool *pool;
1158	pgoff_t i;
1159
1160	amdgpu_ttm_backend_unbind(bdev, ttm);
1161
1162	if (gtt->userptr) {
1163		amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1164		kfree(ttm->sg);
1165		ttm->sg = NULL;
1166		return;
1167	}
1168
1169	if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL)
1170		return;
1171
1172	for (i = 0; i < ttm->num_pages; ++i)
1173		ttm->pages[i]->mapping = NULL;
1174
1175	adev = amdgpu_ttm_adev(bdev);
1176
1177	if (adev->mman.ttm_pools && gtt->pool_id >= 0)
1178		pool = &adev->mman.ttm_pools[gtt->pool_id];
1179	else
1180		pool = &adev->mman.bdev.pool;
1181
1182	return ttm_pool_free(pool, ttm);
1183}
1184
1185/**
1186 * amdgpu_ttm_tt_get_userptr - Return the userptr GTT ttm_tt for the current
1187 * task
1188 *
1189 * @tbo: The ttm_buffer_object that contains the userptr
1190 * @user_addr:  The returned value
1191 */
1192int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo,
1193			      uint64_t *user_addr)
1194{
1195	struct amdgpu_ttm_tt *gtt;
1196
1197	if (!tbo->ttm)
1198		return -EINVAL;
 
 
 
 
1199
1200	gtt = (void *)tbo->ttm;
1201	*user_addr = gtt->userptr;
1202	return 0;
1203}
1204
1205/**
1206 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1207 * task
1208 *
1209 * @bo: The ttm_buffer_object to bind this userptr to
1210 * @addr:  The address in the current tasks VM space to use
1211 * @flags: Requirements of userptr object.
1212 *
1213 * Called by amdgpu_gem_userptr_ioctl() and kfd_ioctl_alloc_memory_of_gpu() to
1214 * bind userptr pages to current task and by kfd_ioctl_acquire_vm() to
1215 * initialize GPU VM for a KFD process.
1216 */
1217int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1218			      uint64_t addr, uint32_t flags)
1219{
1220	struct amdgpu_ttm_tt *gtt;
1221
1222	if (!bo->ttm) {
1223		/* TODO: We want a separate TTM object type for userptrs */
1224		bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1225		if (bo->ttm == NULL)
1226			return -ENOMEM;
1227	}
1228
1229	/* Set TTM_TT_FLAG_EXTERNAL before populate but after create. */
1230	bo->ttm->page_flags |= TTM_TT_FLAG_EXTERNAL;
1231
1232	gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
1233	gtt->userptr = addr;
 
1234	gtt->userflags = flags;
1235
1236	if (gtt->usertask)
1237		put_task_struct(gtt->usertask);
1238	gtt->usertask = current->group_leader;
1239	get_task_struct(gtt->usertask);
1240
1241	return 0;
1242}
1243
1244/*
1245 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1246 */
1247struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1248{
1249	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1250
1251	if (gtt == NULL)
1252		return NULL;
1253
1254	if (gtt->usertask == NULL)
1255		return NULL;
1256
1257	return gtt->usertask->mm;
1258}
1259
1260/*
1261 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1262 * address range for the current task.
1263 *
1264 */
1265bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1266				  unsigned long end, unsigned long *userptr)
1267{
1268	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
 
1269	unsigned long size;
1270
1271	if (gtt == NULL || !gtt->userptr)
1272		return false;
1273
1274	/* Return false if no part of the ttm_tt object lies within
1275	 * the range
1276	 */
1277	size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1278	if (gtt->userptr > end || gtt->userptr + size <= start)
1279		return false;
1280
1281	if (userptr)
1282		*userptr = gtt->userptr;
 
 
 
 
 
 
 
 
 
1283	return true;
1284}
1285
1286/*
1287 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1288 */
1289bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1290{
1291	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1292
1293	if (gtt == NULL || !gtt->userptr)
1294		return false;
1295
1296	return true;
 
1297}
1298
1299/*
1300 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1301 */
1302bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1303{
1304	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
1305
1306	if (gtt == NULL)
1307		return false;
1308
1309	return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1310}
1311
1312/**
1313 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1314 *
1315 * @ttm: The ttm_tt object to compute the flags for
1316 * @mem: The memory registry backing this ttm_tt object
1317 *
1318 * Figure out the flags to use for a VM PDE (Page Directory Entry).
1319 */
1320uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1321{
1322	uint64_t flags = 0;
1323
1324	if (mem && mem->mem_type != TTM_PL_SYSTEM)
1325		flags |= AMDGPU_PTE_VALID;
1326
1327	if (mem && (mem->mem_type == TTM_PL_TT ||
1328		    mem->mem_type == AMDGPU_PL_DOORBELL ||
1329		    mem->mem_type == AMDGPU_PL_PREEMPT)) {
1330		flags |= AMDGPU_PTE_SYSTEM;
1331
1332		if (ttm->caching == ttm_cached)
1333			flags |= AMDGPU_PTE_SNOOPED;
1334	}
1335
1336	if (mem && mem->mem_type == TTM_PL_VRAM &&
1337			mem->bus.caching == ttm_cached)
1338		flags |= AMDGPU_PTE_SNOOPED;
1339
1340	return flags;
1341}
1342
1343/**
1344 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1345 *
1346 * @adev: amdgpu_device pointer
1347 * @ttm: The ttm_tt object to compute the flags for
1348 * @mem: The memory registry backing this ttm_tt object
1349 *
1350 * Figure out the flags to use for a VM PTE (Page Table Entry).
1351 */
1352uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1353				 struct ttm_resource *mem)
1354{
1355	uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1356
1357	flags |= adev->gart.gart_pte_flags;
1358	flags |= AMDGPU_PTE_READABLE;
1359
1360	if (!amdgpu_ttm_tt_is_readonly(ttm))
1361		flags |= AMDGPU_PTE_WRITEABLE;
1362
1363	return flags;
1364}
1365
1366/*
1367 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1368 * object.
1369 *
1370 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1371 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1372 * it can find space for a new object and by ttm_bo_force_list_clean() which is
1373 * used to clean out a memory space.
1374 */
1375static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1376					    const struct ttm_place *place)
1377{
1378	struct dma_resv_iter resv_cursor;
1379	struct dma_fence *f;
1380
1381	if (!amdgpu_bo_is_amdgpu_bo(bo))
1382		return ttm_bo_eviction_valuable(bo, place);
1383
1384	/* Swapout? */
1385	if (bo->resource->mem_type == TTM_PL_SYSTEM)
1386		return true;
1387
1388	if (bo->type == ttm_bo_type_kernel &&
1389	    !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1390		return false;
1391
1392	/* If bo is a KFD BO, check if the bo belongs to the current process.
1393	 * If true, then return false as any KFD process needs all its BOs to
1394	 * be resident to run successfully
1395	 */
1396	dma_resv_for_each_fence(&resv_cursor, bo->base.resv,
1397				DMA_RESV_USAGE_BOOKKEEP, f) {
1398		if (amdkfd_fence_check_mm(f, current->mm))
1399			return false;
1400	}
1401
1402	/* Preemptible BOs don't own system resources managed by the
1403	 * driver (pages, VRAM, GART space). They point to resources
1404	 * owned by someone else (e.g. pageable memory in user mode
1405	 * or a DMABuf). They are used in a preemptible context so we
1406	 * can guarantee no deadlocks and good QoS in case of MMU
1407	 * notifiers or DMABuf move notifiers from the resource owner.
1408	 */
1409	if (bo->resource->mem_type == AMDGPU_PL_PREEMPT)
1410		return false;
1411
1412	if (bo->resource->mem_type == TTM_PL_TT &&
1413	    amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1414		return false;
1415
1416	return ttm_bo_eviction_valuable(bo, place);
1417}
1418
1419static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos,
1420				      void *buf, size_t size, bool write)
1421{
1422	while (size) {
1423		uint64_t aligned_pos = ALIGN_DOWN(pos, 4);
1424		uint64_t bytes = 4 - (pos & 0x3);
1425		uint32_t shift = (pos & 0x3) * 8;
1426		uint32_t mask = 0xffffffff << shift;
1427		uint32_t value = 0;
1428
1429		if (size < bytes) {
1430			mask &= 0xffffffff >> (bytes - size) * 8;
1431			bytes = size;
1432		}
1433
1434		if (mask != 0xffffffff) {
1435			amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false);
1436			if (write) {
1437				value &= ~mask;
1438				value |= (*(uint32_t *)buf << shift) & mask;
1439				amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true);
1440			} else {
1441				value = (value & mask) >> shift;
1442				memcpy(buf, &value, bytes);
1443			}
1444		} else {
1445			amdgpu_device_mm_access(adev, aligned_pos, buf, 4, write);
1446		}
1447
1448		pos += bytes;
1449		buf += bytes;
1450		size -= bytes;
1451	}
1452}
1453
1454static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo,
1455					unsigned long offset, void *buf,
1456					int len, int write)
1457{
1458	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1459	struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1460	struct amdgpu_res_cursor src_mm;
1461	struct amdgpu_job *job;
1462	struct dma_fence *fence;
1463	uint64_t src_addr, dst_addr;
1464	unsigned int num_dw;
1465	int r, idx;
1466
1467	if (len != PAGE_SIZE)
1468		return -EINVAL;
1469
1470	if (!adev->mman.sdma_access_ptr)
1471		return -EACCES;
1472
1473	if (!drm_dev_enter(adev_to_drm(adev), &idx))
1474		return -ENODEV;
1475
1476	if (write)
1477		memcpy(adev->mman.sdma_access_ptr, buf, len);
1478
1479	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
1480	r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
1481				     AMDGPU_FENCE_OWNER_UNDEFINED,
1482				     num_dw * 4, AMDGPU_IB_POOL_DELAYED,
1483				     &job);
1484	if (r)
1485		goto out;
1486
1487	amdgpu_res_first(abo->tbo.resource, offset, len, &src_mm);
1488	src_addr = amdgpu_ttm_domain_start(adev, bo->resource->mem_type) +
1489		src_mm.start;
1490	dst_addr = amdgpu_bo_gpu_offset(adev->mman.sdma_access_bo);
1491	if (write)
1492		swap(src_addr, dst_addr);
1493
1494	amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr,
1495				PAGE_SIZE, false);
 
1496
1497	amdgpu_ring_pad_ib(adev->mman.buffer_funcs_ring, &job->ibs[0]);
1498	WARN_ON(job->ibs[0].length_dw > num_dw);
1499
1500	fence = amdgpu_job_submit(job);
 
 
 
1501
1502	if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout))
1503		r = -ETIMEDOUT;
1504	dma_fence_put(fence);
1505
1506	if (!(r || write))
1507		memcpy(buf, adev->mman.sdma_access_ptr, len);
1508out:
1509	drm_dev_exit(idx);
1510	return r;
1511}
1512
1513/**
1514 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1515 *
1516 * @bo:  The buffer object to read/write
1517 * @offset:  Offset into buffer object
1518 * @buf:  Secondary buffer to write/read from
1519 * @len: Length in bytes of access
1520 * @write:  true if writing
1521 *
1522 * This is used to access VRAM that backs a buffer object via MMIO
1523 * access for debugging purposes.
1524 */
1525static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1526				    unsigned long offset, void *buf, int len,
1527				    int write)
1528{
1529	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1530	struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1531	struct amdgpu_res_cursor cursor;
1532	int ret = 0;
1533
1534	if (bo->resource->mem_type != TTM_PL_VRAM)
1535		return -EIO;
1536
1537	if (amdgpu_device_has_timeouts_enabled(adev) &&
1538			!amdgpu_ttm_access_memory_sdma(bo, offset, buf, len, write))
1539		return len;
1540
1541	amdgpu_res_first(bo->resource, offset, len, &cursor);
1542	while (cursor.remaining) {
1543		size_t count, size = cursor.size;
1544		loff_t pos = cursor.start;
1545
1546		count = amdgpu_device_aper_access(adev, pos, buf, size, write);
1547		size -= count;
1548		if (size) {
1549			/* using MM to access rest vram and handle un-aligned address */
1550			pos += count;
1551			buf += count;
1552			amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write);
1553		}
1554
1555		ret += cursor.size;
1556		buf += cursor.size;
1557		amdgpu_res_next(&cursor, cursor.size);
1558	}
1559
1560	return ret;
1561}
1562
1563static void
1564amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1565{
1566	amdgpu_bo_move_notify(bo, false, NULL);
1567}
1568
1569static struct ttm_device_funcs amdgpu_bo_driver = {
1570	.ttm_tt_create = &amdgpu_ttm_tt_create,
1571	.ttm_tt_populate = &amdgpu_ttm_tt_populate,
1572	.ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1573	.ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
 
1574	.eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1575	.evict_flags = &amdgpu_evict_flags,
1576	.move = &amdgpu_bo_move,
1577	.delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1578	.release_notify = &amdgpu_bo_release_notify,
 
1579	.io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1580	.io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1581	.access_memory = &amdgpu_ttm_access_memory,
 
 
1582};
1583
1584/*
1585 * Firmware Reservation functions
1586 */
1587/**
1588 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1589 *
1590 * @adev: amdgpu_device pointer
1591 *
1592 * free fw reserved vram if it has been reserved.
1593 */
1594static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1595{
1596	amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1597		NULL, &adev->mman.fw_vram_usage_va);
1598}
1599
1600/*
1601 * Driver Reservation functions
1602 */
1603/**
1604 * amdgpu_ttm_drv_reserve_vram_fini - free drv reserved vram
1605 *
1606 * @adev: amdgpu_device pointer
1607 *
1608 * free drv reserved vram if it has been reserved.
1609 */
1610static void amdgpu_ttm_drv_reserve_vram_fini(struct amdgpu_device *adev)
1611{
1612	amdgpu_bo_free_kernel(&adev->mman.drv_vram_usage_reserved_bo,
1613						  NULL,
1614						  &adev->mman.drv_vram_usage_va);
1615}
1616
1617/**
1618 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1619 *
1620 * @adev: amdgpu_device pointer
1621 *
1622 * create bo vram reservation from fw.
1623 */
1624static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1625{
1626	uint64_t vram_size = adev->gmc.visible_vram_size;
1627
1628	adev->mman.fw_vram_usage_va = NULL;
1629	adev->mman.fw_vram_usage_reserved_bo = NULL;
1630
1631	if (adev->mman.fw_vram_usage_size == 0 ||
1632	    adev->mman.fw_vram_usage_size > vram_size)
1633		return 0;
1634
1635	return amdgpu_bo_create_kernel_at(adev,
1636					  adev->mman.fw_vram_usage_start_offset,
1637					  adev->mman.fw_vram_usage_size,
1638					  &adev->mman.fw_vram_usage_reserved_bo,
1639					  &adev->mman.fw_vram_usage_va);
1640}
1641
1642/**
1643 * amdgpu_ttm_drv_reserve_vram_init - create bo vram reservation from driver
1644 *
1645 * @adev: amdgpu_device pointer
1646 *
1647 * create bo vram reservation from drv.
1648 */
1649static int amdgpu_ttm_drv_reserve_vram_init(struct amdgpu_device *adev)
1650{
1651	u64 vram_size = adev->gmc.visible_vram_size;
1652
1653	adev->mman.drv_vram_usage_va = NULL;
1654	adev->mman.drv_vram_usage_reserved_bo = NULL;
1655
1656	if (adev->mman.drv_vram_usage_size == 0 ||
1657	    adev->mman.drv_vram_usage_size > vram_size)
1658		return 0;
1659
1660	return amdgpu_bo_create_kernel_at(adev,
1661					  adev->mman.drv_vram_usage_start_offset,
1662					  adev->mman.drv_vram_usage_size,
1663					  &adev->mman.drv_vram_usage_reserved_bo,
1664					  &adev->mman.drv_vram_usage_va);
1665}
1666
1667/*
1668 * Memoy training reservation functions
1669 */
1670
1671/**
1672 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1673 *
1674 * @adev: amdgpu_device pointer
1675 *
1676 * free memory training reserved vram if it has been reserved.
1677 */
1678static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1679{
1680	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1681
1682	ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1683	amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1684	ctx->c2p_bo = NULL;
1685
1686	return 0;
1687}
1688
1689static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev,
1690						uint32_t reserve_size)
1691{
1692	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1693
1694	memset(ctx, 0, sizeof(*ctx));
1695
1696	ctx->c2p_train_data_offset =
1697		ALIGN((adev->gmc.mc_vram_size - reserve_size - SZ_1M), SZ_1M);
1698	ctx->p2c_train_data_offset =
1699		(adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1700	ctx->train_data_size =
1701		GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1702
1703	DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1704			ctx->train_data_size,
1705			ctx->p2c_train_data_offset,
1706			ctx->c2p_train_data_offset);
1707}
1708
1709/*
1710 * reserve TMR memory at the top of VRAM which holds
1711 * IP Discovery data and is protected by PSP.
1712 */
1713static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1714{
1715	struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1716	bool mem_train_support = false;
1717	uint32_t reserve_size = 0;
1718	int ret;
1719
1720	if (adev->bios && !amdgpu_sriov_vf(adev)) {
1721		if (amdgpu_atomfirmware_mem_training_supported(adev))
1722			mem_train_support = true;
1723		else
1724			DRM_DEBUG("memory training does not support!\n");
1725	}
1726
1727	/*
1728	 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1729	 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1730	 *
1731	 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1732	 * discovery data and G6 memory training data respectively
1733	 */
1734	if (adev->bios)
1735		reserve_size =
1736			amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1737
1738	if (!adev->bios &&
1739	    amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))
1740		reserve_size = max(reserve_size, (uint32_t)280 << 20);
1741	else if (!reserve_size)
1742		reserve_size = DISCOVERY_TMR_OFFSET;
1743
1744	if (mem_train_support) {
1745		/* reserve vram for mem train according to TMR location */
1746		amdgpu_ttm_training_data_block_init(adev, reserve_size);
1747		ret = amdgpu_bo_create_kernel_at(adev,
1748						 ctx->c2p_train_data_offset,
1749						 ctx->train_data_size,
1750						 &ctx->c2p_bo,
1751						 NULL);
1752		if (ret) {
1753			DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1754			amdgpu_ttm_training_reserve_vram_fini(adev);
1755			return ret;
1756		}
1757		ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1758	}
1759
1760	if (!adev->gmc.is_app_apu) {
1761		ret = amdgpu_bo_create_kernel_at(
1762			adev, adev->gmc.real_vram_size - reserve_size,
1763			reserve_size, &adev->mman.fw_reserved_memory, NULL);
1764		if (ret) {
1765			DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1766			amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory,
1767					      NULL, NULL);
1768			return ret;
1769		}
1770	} else {
1771		DRM_DEBUG_DRIVER("backdoor fw loading path for PSP TMR, no reservation needed\n");
1772	}
1773
1774	return 0;
1775}
1776
1777static int amdgpu_ttm_pools_init(struct amdgpu_device *adev)
1778{
1779	int i;
1780
1781	if (!adev->gmc.is_app_apu || !adev->gmc.num_mem_partitions)
1782		return 0;
1783
1784	adev->mman.ttm_pools = kcalloc(adev->gmc.num_mem_partitions,
1785				       sizeof(*adev->mman.ttm_pools),
1786				       GFP_KERNEL);
1787	if (!adev->mman.ttm_pools)
1788		return -ENOMEM;
1789
1790	for (i = 0; i < adev->gmc.num_mem_partitions; i++) {
1791		ttm_pool_init(&adev->mman.ttm_pools[i], adev->dev,
1792			      adev->gmc.mem_partitions[i].numa.node,
1793			      false, false);
1794	}
1795	return 0;
1796}
1797
1798static void amdgpu_ttm_pools_fini(struct amdgpu_device *adev)
1799{
1800	int i;
1801
1802	if (!adev->gmc.is_app_apu || !adev->mman.ttm_pools)
1803		return;
1804
1805	for (i = 0; i < adev->gmc.num_mem_partitions; i++)
1806		ttm_pool_fini(&adev->mman.ttm_pools[i]);
1807
1808	kfree(adev->mman.ttm_pools);
1809	adev->mman.ttm_pools = NULL;
1810}
1811
1812/*
1813 * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1814 * gtt/vram related fields.
1815 *
1816 * This initializes all of the memory space pools that the TTM layer
1817 * will need such as the GTT space (system memory mapped to the device),
1818 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1819 * can be mapped per VMID.
1820 */
1821int amdgpu_ttm_init(struct amdgpu_device *adev)
1822{
1823	uint64_t gtt_size;
1824	int r;
1825
1826	mutex_init(&adev->mman.gtt_window_lock);
1827
1828	/* No others user of address space so set it to 0 */
1829	r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1830			       adev_to_drm(adev)->anon_inode->i_mapping,
1831			       adev_to_drm(adev)->vma_offset_manager,
1832			       adev->need_swiotlb,
1833			       dma_addressing_limited(adev->dev));
1834	if (r) {
1835		DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1836		return r;
1837	}
1838
1839	r = amdgpu_ttm_pools_init(adev);
1840	if (r) {
1841		DRM_ERROR("failed to init ttm pools(%d).\n", r);
1842		return r;
1843	}
1844	adev->mman.initialized = true;
1845
1846	/* Initialize VRAM pool with all of VRAM divided into pages */
1847	r = amdgpu_vram_mgr_init(adev);
 
 
 
1848	if (r) {
1849		DRM_ERROR("Failed initializing VRAM heap.\n");
1850		return r;
1851	}
1852
1853	/* Change the size here instead of the init above so only lpfn is affected */
1854	amdgpu_ttm_set_buffer_funcs_status(adev, false);
1855#ifdef CONFIG_64BIT
1856#ifdef CONFIG_X86
1857	if (adev->gmc.xgmi.connected_to_cpu)
1858		adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
1859				adev->gmc.visible_vram_size);
1860
1861	else if (adev->gmc.is_app_apu)
1862		DRM_DEBUG_DRIVER(
1863			"No need to ioremap when real vram size is 0\n");
1864	else
1865#endif
1866		adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1867				adev->gmc.visible_vram_size);
1868#endif
1869
1870	/*
1871	 *The reserved vram for firmware must be pinned to the specified
1872	 *place on the VRAM, so reserve it early.
1873	 */
1874	r = amdgpu_ttm_fw_reserve_vram_init(adev);
1875	if (r)
1876		return r;
1877
1878	/*
1879	 *The reserved vram for driver must be pinned to the specified
1880	 *place on the VRAM, so reserve it early.
1881	 */
1882	r = amdgpu_ttm_drv_reserve_vram_init(adev);
1883	if (r)
1884		return r;
1885
1886	/*
1887	 * only NAVI10 and onwards ASIC support for IP discovery.
1888	 * If IP discovery enabled, a block of memory should be
1889	 * reserved for IP discovey.
1890	 */
1891	if (adev->mman.discovery_bin) {
1892		r = amdgpu_ttm_reserve_tmr(adev);
1893		if (r)
1894			return r;
1895	}
1896
1897	/* allocate memory as required for VGA
1898	 * This is used for VGA emulation and pre-OS scanout buffers to
1899	 * avoid display artifacts while transitioning between pre-OS
1900	 * and driver.
1901	 */
1902	if (!adev->gmc.is_app_apu) {
1903		r = amdgpu_bo_create_kernel_at(adev, 0,
1904					       adev->mman.stolen_vga_size,
1905					       &adev->mman.stolen_vga_memory,
1906					       NULL);
1907		if (r)
1908			return r;
1909
1910		r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1911					       adev->mman.stolen_extended_size,
1912					       &adev->mman.stolen_extended_memory,
1913					       NULL);
1914
1915		if (r)
1916			return r;
1917
1918		r = amdgpu_bo_create_kernel_at(adev,
1919					       adev->mman.stolen_reserved_offset,
1920					       adev->mman.stolen_reserved_size,
1921					       &adev->mman.stolen_reserved_memory,
1922					       NULL);
1923		if (r)
1924			return r;
1925	} else {
1926		DRM_DEBUG_DRIVER("Skipped stolen memory reservation\n");
1927	}
1928
1929	DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1930		 (unsigned int)(adev->gmc.real_vram_size / (1024 * 1024)));
1931
1932	/* Compute GTT size, either based on TTM limit
1933	 * or whatever the user passed on module init.
1934	 */
1935	if (amdgpu_gtt_size == -1)
1936		gtt_size = ttm_tt_pages_limit() << PAGE_SHIFT;
1937	else
1938		gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1939
1940	/* Initialize GTT memory pool */
1941	r = amdgpu_gtt_mgr_init(adev, gtt_size);
1942	if (r) {
1943		DRM_ERROR("Failed initializing GTT heap.\n");
1944		return r;
1945	}
1946	DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1947		 (unsigned int)(gtt_size / (1024 * 1024)));
1948
1949	/* Initiailize doorbell pool on PCI BAR */
1950	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_DOORBELL, adev->doorbell.size / PAGE_SIZE);
 
 
 
1951	if (r) {
1952		DRM_ERROR("Failed initializing doorbell heap.\n");
1953		return r;
1954	}
1955
1956	/* Create a boorbell page for kernel usages */
1957	r = amdgpu_doorbell_create_kernel_doorbells(adev);
 
 
1958	if (r) {
1959		DRM_ERROR("Failed to initialize kernel doorbells.\n");
1960		return r;
1961	}
1962
1963	/* Initialize preemptible memory pool */
1964	r = amdgpu_preempt_mgr_init(adev);
 
1965	if (r) {
1966		DRM_ERROR("Failed initializing PREEMPT heap.\n");
1967		return r;
1968	}
 
 
1969
1970	/* Initialize various on-chip memory pools */
1971	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
 
 
 
 
 
 
 
 
 
 
1972	if (r) {
1973		DRM_ERROR("Failed initializing GDS heap.\n");
1974		return r;
1975	}
1976
1977	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
 
 
1978	if (r) {
1979		DRM_ERROR("Failed initializing gws heap.\n");
1980		return r;
1981	}
1982
1983	r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
 
 
1984	if (r) {
1985		DRM_ERROR("Failed initializing oa heap.\n");
1986		return r;
1987	}
1988	if (amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
1989				AMDGPU_GEM_DOMAIN_GTT,
1990				&adev->mman.sdma_access_bo, NULL,
1991				&adev->mman.sdma_access_ptr))
1992		DRM_WARN("Debug VRAM access will use slowpath MM access\n");
1993
 
 
 
 
 
1994	return 0;
1995}
1996
1997/*
1998 * amdgpu_ttm_fini - De-initialize the TTM memory pools
1999 */
2000void amdgpu_ttm_fini(struct amdgpu_device *adev)
2001{
2002	int idx;
2003
2004	if (!adev->mman.initialized)
2005		return;
2006
2007	amdgpu_ttm_pools_fini(adev);
2008
2009	amdgpu_ttm_training_reserve_vram_fini(adev);
2010	/* return the stolen vga memory back to VRAM */
2011	if (!adev->gmc.is_app_apu) {
2012		amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
2013		amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
2014		/* return the FW reserved memory back to VRAM */
2015		amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory, NULL,
2016				      NULL);
2017		if (adev->mman.stolen_reserved_size)
2018			amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory,
2019					      NULL, NULL);
2020	}
2021	amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL,
2022					&adev->mman.sdma_access_ptr);
2023	amdgpu_ttm_fw_reserve_vram_fini(adev);
2024	amdgpu_ttm_drv_reserve_vram_fini(adev);
2025
2026	if (drm_dev_enter(adev_to_drm(adev), &idx)) {
2027
2028		if (adev->mman.aper_base_kaddr)
2029			iounmap(adev->mman.aper_base_kaddr);
2030		adev->mman.aper_base_kaddr = NULL;
2031
2032		drm_dev_exit(idx);
2033	}
2034
2035	amdgpu_vram_mgr_fini(adev);
2036	amdgpu_gtt_mgr_fini(adev);
2037	amdgpu_preempt_mgr_fini(adev);
2038	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
2039	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
2040	ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
2041	ttm_device_fini(&adev->mman.bdev);
2042	adev->mman.initialized = false;
2043	DRM_INFO("amdgpu: ttm finalized\n");
2044}
2045
2046/**
2047 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
2048 *
2049 * @adev: amdgpu_device pointer
2050 * @enable: true when we can use buffer functions.
2051 *
2052 * Enable/disable use of buffer functions during suspend/resume. This should
2053 * only be called at bootup or when userspace isn't running.
2054 */
2055void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2056{
2057	struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
2058	uint64_t size;
2059	int r;
2060
2061	if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
2062	    adev->mman.buffer_funcs_enabled == enable || adev->gmc.is_app_apu)
2063		return;
2064
2065	if (enable) {
2066		struct amdgpu_ring *ring;
2067		struct drm_gpu_scheduler *sched;
2068
2069		ring = adev->mman.buffer_funcs_ring;
2070		sched = &ring->sched;
2071		r = drm_sched_entity_init(&adev->mman.high_pr,
2072					  DRM_SCHED_PRIORITY_KERNEL, &sched,
2073					  1, NULL);
2074		if (r) {
2075			DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2076				  r);
2077			return;
2078		}
2079
2080		r = drm_sched_entity_init(&adev->mman.low_pr,
2081					  DRM_SCHED_PRIORITY_NORMAL, &sched,
2082					  1, NULL);
2083		if (r) {
2084			DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2085				  r);
2086			goto error_free_entity;
2087		}
2088	} else {
2089		drm_sched_entity_destroy(&adev->mman.high_pr);
2090		drm_sched_entity_destroy(&adev->mman.low_pr);
2091		dma_fence_put(man->move);
2092		man->move = NULL;
2093	}
2094
2095	/* this just adjusts TTM size idea, which sets lpfn to the correct value */
2096	if (enable)
2097		size = adev->gmc.real_vram_size;
2098	else
2099		size = adev->gmc.visible_vram_size;
2100	man->size = size;
2101	adev->mman.buffer_funcs_enabled = enable;
2102
2103	return;
2104
2105error_free_entity:
2106	drm_sched_entity_destroy(&adev->mman.high_pr);
2107}
2108
2109static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
2110				  bool direct_submit,
2111				  unsigned int num_dw,
2112				  struct dma_resv *resv,
2113				  bool vm_needs_flush,
2114				  struct amdgpu_job **job,
2115				  bool delayed)
2116{
2117	enum amdgpu_ib_pool_type pool = direct_submit ?
2118		AMDGPU_IB_POOL_DIRECT :
2119		AMDGPU_IB_POOL_DELAYED;
2120	int r;
2121	struct drm_sched_entity *entity = delayed ? &adev->mman.low_pr :
2122						    &adev->mman.high_pr;
2123	r = amdgpu_job_alloc_with_ib(adev, entity,
2124				     AMDGPU_FENCE_OWNER_UNDEFINED,
2125				     num_dw * 4, pool, job);
2126	if (r)
2127		return r;
2128
2129	if (vm_needs_flush) {
2130		(*job)->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ?
2131							adev->gmc.pdb0_bo :
2132							adev->gart.bo);
2133		(*job)->vm_needs_flush = true;
2134	}
2135	if (!resv)
2136		return 0;
2137
2138	return drm_sched_job_add_resv_dependencies(&(*job)->base, resv,
2139						   DMA_RESV_USAGE_BOOKKEEP);
2140}
2141
2142int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2143		       uint64_t dst_offset, uint32_t byte_count,
2144		       struct dma_resv *resv,
2145		       struct dma_fence **fence, bool direct_submit,
2146		       bool vm_needs_flush, bool tmz)
 
2147{
2148	struct amdgpu_device *adev = ring->adev;
2149	unsigned int num_loops, num_dw;
2150	struct amdgpu_job *job;
 
2151	uint32_t max_bytes;
2152	unsigned int i;
 
2153	int r;
2154
2155	if (!direct_submit && !ring->sched.ready) {
2156		DRM_ERROR("Trying to move memory with ring turned off.\n");
2157		return -EINVAL;
2158	}
2159
2160	max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2161	num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2162	num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2163	r = amdgpu_ttm_prepare_job(adev, direct_submit, num_dw,
2164				   resv, vm_needs_flush, &job, false);
 
 
 
 
2165	if (r)
2166		return r;
2167
 
 
 
 
 
 
 
 
 
2168	for (i = 0; i < num_loops; i++) {
2169		uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2170
2171		amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2172					dst_offset, cur_size_in_bytes, tmz);
2173
2174		src_offset += cur_size_in_bytes;
2175		dst_offset += cur_size_in_bytes;
2176		byte_count -= cur_size_in_bytes;
2177	}
2178
2179	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2180	WARN_ON(job->ibs[0].length_dw > num_dw);
2181	if (direct_submit)
2182		r = amdgpu_job_submit_direct(job, ring, fence);
2183	else
2184		*fence = amdgpu_job_submit(job);
2185	if (r)
2186		goto error_free;
 
 
 
 
 
 
 
2187
2188	return r;
2189
2190error_free:
2191	amdgpu_job_free(job);
2192	DRM_ERROR("Error scheduling IBs (%d)\n", r);
2193	return r;
2194}
2195
2196static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data,
2197			       uint64_t dst_addr, uint32_t byte_count,
2198			       struct dma_resv *resv,
2199			       struct dma_fence **fence,
2200			       bool vm_needs_flush, bool delayed)
2201{
2202	struct amdgpu_device *adev = ring->adev;
 
 
 
 
 
2203	unsigned int num_loops, num_dw;
 
2204	struct amdgpu_job *job;
2205	uint32_t max_bytes;
2206	unsigned int i;
2207	int r;
2208
2209	max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2210	num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes);
2211	num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8);
2212	r = amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush,
2213				   &job, delayed);
2214	if (r)
2215		return r;
2216
2217	for (i = 0; i < num_loops; i++) {
2218		uint32_t cur_size = min(byte_count, max_bytes);
2219
2220		amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr,
2221					cur_size);
2222
2223		dst_addr += cur_size;
2224		byte_count -= cur_size;
 
 
 
 
 
 
 
2225	}
 
2226
2227	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2228	WARN_ON(job->ibs[0].length_dw > num_dw);
2229	*fence = amdgpu_job_submit(job);
2230	return 0;
2231}
2232
2233int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2234			uint32_t src_data,
2235			struct dma_resv *resv,
2236			struct dma_fence **f,
2237			bool delayed)
2238{
2239	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2240	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2241	struct dma_fence *fence = NULL;
2242	struct amdgpu_res_cursor dst;
2243	int r;
2244
2245	if (!adev->mman.buffer_funcs_enabled) {
2246		DRM_ERROR("Trying to clear memory with ring turned off.\n");
2247		return -EINVAL;
 
 
 
 
2248	}
2249
2250	amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
 
2251
2252	mutex_lock(&adev->mman.gtt_window_lock);
2253	while (dst.remaining) {
2254		struct dma_fence *next;
2255		uint64_t cur_size, to;
2256
2257		/* Never fill more than 256MiB at once to avoid timeouts */
2258		cur_size = min(dst.size, 256ULL << 20);
2259
2260		r = amdgpu_ttm_map_buffer(&bo->tbo, bo->tbo.resource, &dst,
2261					  1, ring, false, &cur_size, &to);
2262		if (r)
2263			goto error;
2264
2265		r = amdgpu_ttm_fill_mem(ring, src_data, to, cur_size, resv,
2266					&next, true, delayed);
2267		if (r)
2268			goto error;
2269
2270		dma_fence_put(fence);
2271		fence = next;
 
 
 
 
2272
2273		amdgpu_res_next(&dst, cur_size);
 
2274	}
2275error:
2276	mutex_unlock(&adev->mman.gtt_window_lock);
2277	if (f)
2278		*f = dma_fence_get(fence);
2279	dma_fence_put(fence);
2280	return r;
2281}
2282
2283/**
2284 * amdgpu_ttm_evict_resources - evict memory buffers
2285 * @adev: amdgpu device object
2286 * @mem_type: evicted BO's memory type
2287 *
2288 * Evicts all @mem_type buffers on the lru list of the memory type.
2289 *
2290 * Returns:
2291 * 0 for success or a negative error code on failure.
2292 */
2293int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type)
2294{
2295	struct ttm_resource_manager *man;
2296
2297	switch (mem_type) {
2298	case TTM_PL_VRAM:
2299	case TTM_PL_TT:
2300	case AMDGPU_PL_GWS:
2301	case AMDGPU_PL_GDS:
2302	case AMDGPU_PL_OA:
2303		man = ttm_manager_type(&adev->mman.bdev, mem_type);
2304		break;
2305	default:
2306		DRM_ERROR("Trying to evict invalid memory type\n");
2307		return -EINVAL;
2308	}
2309
2310	return ttm_resource_manager_evict_all(&adev->mman.bdev, man);
 
 
2311}
2312
2313#if defined(CONFIG_DEBUG_FS)
2314
2315static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused)
2316{
2317	struct amdgpu_device *adev = m->private;
 
 
 
 
 
 
2318
2319	return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
 
 
 
 
 
 
 
 
2320}
2321
2322DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool);
 
2323
2324/*
2325 * amdgpu_ttm_vram_read - Linear read access to VRAM
2326 *
2327 * Accesses VRAM via MMIO for debugging purposes.
2328 */
2329static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2330				    size_t size, loff_t *pos)
2331{
2332	struct amdgpu_device *adev = file_inode(f)->i_private;
2333	ssize_t result = 0;
2334
2335	if (size & 0x3 || *pos & 0x3)
2336		return -EINVAL;
2337
2338	if (*pos >= adev->gmc.mc_vram_size)
2339		return -ENXIO;
2340
2341	size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2342	while (size) {
2343		size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2344		uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2345
2346		amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2347		if (copy_to_user(buf, value, bytes))
2348			return -EFAULT;
2349
2350		result += bytes;
2351		buf += bytes;
2352		*pos += bytes;
2353		size -= bytes;
2354	}
2355
2356	return result;
2357}
2358
2359/*
2360 * amdgpu_ttm_vram_write - Linear write access to VRAM
2361 *
2362 * Accesses VRAM via MMIO for debugging purposes.
2363 */
2364static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2365				    size_t size, loff_t *pos)
2366{
2367	struct amdgpu_device *adev = file_inode(f)->i_private;
2368	ssize_t result = 0;
2369	int r;
2370
2371	if (size & 0x3 || *pos & 0x3)
2372		return -EINVAL;
2373
2374	if (*pos >= adev->gmc.mc_vram_size)
2375		return -ENXIO;
2376
2377	while (size) {
 
2378		uint32_t value;
2379
2380		if (*pos >= adev->gmc.mc_vram_size)
2381			return result;
2382
2383		r = get_user(value, (uint32_t *)buf);
 
 
 
 
 
 
2384		if (r)
2385			return r;
2386
2387		amdgpu_device_mm_access(adev, *pos, &value, 4, true);
2388
2389		result += 4;
2390		buf += 4;
2391		*pos += 4;
2392		size -= 4;
2393	}
2394
2395	return result;
2396}
2397
2398static const struct file_operations amdgpu_ttm_vram_fops = {
2399	.owner = THIS_MODULE,
2400	.read = amdgpu_ttm_vram_read,
2401	.write = amdgpu_ttm_vram_write,
2402	.llseek = default_llseek,
2403};
2404
2405/*
2406 * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2407 *
2408 * This function is used to read memory that has been mapped to the
2409 * GPU and the known addresses are not physical addresses but instead
2410 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2411 */
2412static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2413				 size_t size, loff_t *pos)
2414{
2415	struct amdgpu_device *adev = file_inode(f)->i_private;
2416	struct iommu_domain *dom;
2417	ssize_t result = 0;
2418	int r;
2419
2420	/* retrieve the IOMMU domain if any for this device */
2421	dom = iommu_get_domain_for_dev(adev->dev);
2422
2423	while (size) {
2424		phys_addr_t addr = *pos & PAGE_MASK;
2425		loff_t off = *pos & ~PAGE_MASK;
2426		size_t bytes = PAGE_SIZE - off;
2427		unsigned long pfn;
2428		struct page *p;
2429		void *ptr;
2430
2431		bytes = min(bytes, size);
2432
2433		/* Translate the bus address to a physical address.  If
2434		 * the domain is NULL it means there is no IOMMU active
2435		 * and the address translation is the identity
2436		 */
2437		addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2438
2439		pfn = addr >> PAGE_SHIFT;
2440		if (!pfn_valid(pfn))
2441			return -EPERM;
2442
2443		p = pfn_to_page(pfn);
2444		if (p->mapping != adev->mman.bdev.dev_mapping)
2445			return -EPERM;
 
 
 
 
 
 
2446
2447		ptr = kmap_local_page(p);
2448		r = copy_to_user(buf, ptr + off, bytes);
2449		kunmap_local(ptr);
2450		if (r)
2451			return -EFAULT;
2452
2453		size -= bytes;
2454		*pos += bytes;
2455		result += bytes;
 
2456	}
2457
2458	return result;
2459}
2460
2461/*
2462 * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2463 *
2464 * This function is used to write memory that has been mapped to the
2465 * GPU and the known addresses are not physical addresses but instead
2466 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2467 */
2468static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2469				 size_t size, loff_t *pos)
2470{
2471	struct amdgpu_device *adev = file_inode(f)->i_private;
2472	struct iommu_domain *dom;
2473	ssize_t result = 0;
2474	int r;
2475
2476	dom = iommu_get_domain_for_dev(adev->dev);
2477
2478	while (size) {
2479		phys_addr_t addr = *pos & PAGE_MASK;
2480		loff_t off = *pos & ~PAGE_MASK;
2481		size_t bytes = PAGE_SIZE - off;
2482		unsigned long pfn;
2483		struct page *p;
2484		void *ptr;
2485
2486		bytes = min(bytes, size);
2487
2488		addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2489
2490		pfn = addr >> PAGE_SHIFT;
2491		if (!pfn_valid(pfn))
2492			return -EPERM;
 
2493
2494		p = pfn_to_page(pfn);
2495		if (p->mapping != adev->mman.bdev.dev_mapping)
2496			return -EPERM;
2497
2498		ptr = kmap_local_page(p);
2499		r = copy_from_user(ptr + off, buf, bytes);
2500		kunmap_local(ptr);
2501		if (r)
2502			return -EFAULT;
 
 
 
 
 
 
 
 
 
2503
2504		size -= bytes;
2505		*pos += bytes;
2506		result += bytes;
2507	}
2508
2509	return result;
2510}
 
 
2511
2512static const struct file_operations amdgpu_ttm_iomem_fops = {
2513	.owner = THIS_MODULE,
2514	.read = amdgpu_iomem_read,
2515	.write = amdgpu_iomem_write,
2516	.llseek = default_llseek
2517};
2518
 
2519#endif
 
2520
2521void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2522{
2523#if defined(CONFIG_DEBUG_FS)
2524	struct drm_minor *minor = adev_to_drm(adev)->primary;
2525	struct dentry *root = minor->debugfs_root;
2526
2527	debugfs_create_file_size("amdgpu_vram", 0444, root, adev,
2528				 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size);
2529	debugfs_create_file("amdgpu_iomem", 0444, root, adev,
2530			    &amdgpu_ttm_iomem_fops);
2531	debugfs_create_file("ttm_page_pool", 0444, root, adev,
2532			    &amdgpu_ttm_page_pool_fops);
2533	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2534							     TTM_PL_VRAM),
2535					    root, "amdgpu_vram_mm");
2536	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2537							     TTM_PL_TT),
2538					    root, "amdgpu_gtt_mm");
2539	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2540							     AMDGPU_PL_GDS),
2541					    root, "amdgpu_gds_mm");
2542	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2543							     AMDGPU_PL_GWS),
2544					    root, "amdgpu_gws_mm");
2545	ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev,
2546							     AMDGPU_PL_OA),
2547					    root, "amdgpu_oa_mm");
2548
2549#endif
2550}