Loading...
1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include <uapi/drm/i915_drm.h>
34
35#include <linux/pm_qos.h>
36
37#include <drm/ttm/ttm_device.h>
38
39#include "display/intel_display_limits.h"
40#include "display/intel_display_core.h"
41
42#include "gem/i915_gem_context_types.h"
43#include "gem/i915_gem_shrinker.h"
44#include "gem/i915_gem_stolen.h"
45
46#include "gt/intel_engine.h"
47#include "gt/intel_gt_types.h"
48#include "gt/intel_region_lmem.h"
49#include "gt/intel_workarounds.h"
50#include "gt/uc/intel_uc.h"
51
52#include "soc/intel_pch.h"
53
54#include "i915_drm_client.h"
55#include "i915_gem.h"
56#include "i915_gpu_error.h"
57#include "i915_params.h"
58#include "i915_perf_types.h"
59#include "i915_scheduler.h"
60#include "i915_utils.h"
61#include "intel_device_info.h"
62#include "intel_memory_region.h"
63#include "intel_runtime_pm.h"
64#include "intel_step.h"
65#include "intel_uncore.h"
66
67struct drm_i915_clock_gating_funcs;
68struct vlv_s0ix_state;
69struct intel_pxp;
70
71#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
72
73/* Data Stolen Memory (DSM) aka "i915 stolen memory" */
74struct i915_dsm {
75 /*
76 * The start and end of DSM which we can optionally use to create GEM
77 * objects backed by stolen memory.
78 *
79 * Note that usable_size tells us exactly how much of this we are
80 * actually allowed to use, given that some portion of it is in fact
81 * reserved for use by hardware functions.
82 */
83 struct resource stolen;
84
85 /*
86 * Reserved portion of DSM.
87 */
88 struct resource reserved;
89
90 /*
91 * Total size minus reserved ranges.
92 *
93 * DSM is segmented in hardware with different portions offlimits to
94 * certain functions.
95 *
96 * The drm_mm is initialised to the total accessible range, as found
97 * from the PCI config. On Broadwell+, this is further restricted to
98 * avoid the first page! The upper end of DSM is reserved for hardware
99 * functions and similarly removed from the accessible range.
100 */
101 resource_size_t usable_size;
102};
103
104struct i915_suspend_saved_registers {
105 u32 saveDSPARB;
106 u32 saveSWF0[16];
107 u32 saveSWF1[16];
108 u32 saveSWF3[3];
109 u16 saveGCDGMBUS;
110};
111
112#define MAX_L3_SLICES 2
113struct intel_l3_parity {
114 u32 *remap_info[MAX_L3_SLICES];
115 struct work_struct error_work;
116 int which_slice;
117};
118
119struct i915_gem_mm {
120 /*
121 * Shortcut for the stolen region. This points to either
122 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or
123 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
124 * support stolen.
125 */
126 struct intel_memory_region *stolen_region;
127 /** Memory allocator for GTT stolen memory */
128 struct drm_mm stolen;
129 /** Protects the usage of the GTT stolen memory allocator. This is
130 * always the inner lock when overlapping with struct_mutex. */
131 struct mutex stolen_lock;
132
133 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
134 spinlock_t obj_lock;
135
136 /**
137 * List of objects which are purgeable.
138 */
139 struct list_head purge_list;
140
141 /**
142 * List of objects which have allocated pages and are shrinkable.
143 */
144 struct list_head shrink_list;
145
146 /**
147 * List of objects which are pending destruction.
148 */
149 struct llist_head free_list;
150 struct work_struct free_work;
151 /**
152 * Count of objects pending destructions. Used to skip needlessly
153 * waiting on an RCU barrier if no objects are waiting to be freed.
154 */
155 atomic_t free_count;
156
157 /**
158 * tmpfs instance used for shmem backed objects
159 */
160 struct vfsmount *gemfs;
161
162 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
163
164 struct notifier_block oom_notifier;
165 struct notifier_block vmap_notifier;
166 struct shrinker *shrinker;
167
168 /* shrinker accounting, also useful for userland debugging */
169 u64 shrink_memory;
170 u32 shrink_count;
171};
172
173struct i915_virtual_gpu {
174 struct mutex lock; /* serialises sending of g2v_notify command pkts */
175 bool active;
176 u32 caps;
177 u32 *initial_mmio;
178 u8 *initial_cfg_space;
179 struct list_head entry;
180};
181
182struct i915_selftest_stash {
183 atomic_t counter;
184 struct ida mock_region_instances;
185};
186
187struct drm_i915_private {
188 struct drm_device drm;
189
190 struct intel_display display;
191
192 /* FIXME: Device release actions should all be moved to drmm_ */
193 bool do_release;
194
195 /* i915 device parameters */
196 struct i915_params params;
197
198 const struct intel_device_info *__info; /* Use INTEL_INFO() to access. */
199 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
200 struct intel_driver_caps caps;
201
202 struct i915_dsm dsm;
203
204 struct intel_uncore uncore;
205 struct intel_uncore_mmio_debug mmio_debug;
206
207 struct i915_virtual_gpu vgpu;
208
209 struct intel_gvt *gvt;
210
211 struct {
212 struct pci_dev *pdev;
213 struct resource mch_res;
214 bool mchbar_need_disable;
215 } gmch;
216
217 /*
218 * Chaining user engines happens in multiple stages, starting with a
219 * simple lock-less linked list created by intel_engine_add_user(),
220 * which later gets sorted and converted to an intermediate regular
221 * list, just to be converted once again to its final rb tree structure
222 * in intel_engines_driver_register().
223 *
224 * Make sure to use the right iterator helper, depending on if the code
225 * in question runs before or after intel_engines_driver_register() --
226 * for_each_uabi_engine() can only be used afterwards!
227 */
228 union {
229 struct llist_head uabi_engines_llist;
230 struct list_head uabi_engines_list;
231 struct rb_root uabi_engines;
232 };
233 unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];
234
235 /* protects the irq masks */
236 spinlock_t irq_lock;
237
238 bool display_irqs_enabled;
239
240 /* Sideband mailbox protection */
241 struct mutex sb_lock;
242 struct pm_qos_request sb_qos;
243
244 /** Cached value of IMR to avoid reads in updating the bitfield */
245 union {
246 u32 irq_mask;
247 u32 de_irq_mask[I915_MAX_PIPES];
248 };
249 u32 pipestat_irq_mask[I915_MAX_PIPES];
250
251 bool preserve_bios_swizzle;
252
253 unsigned int fsb_freq, mem_freq, is_ddr3;
254 unsigned int skl_preferred_vco_freq;
255
256 unsigned int max_dotclk_freq;
257 unsigned int hpll_freq;
258 unsigned int czclk_freq;
259
260 /**
261 * wq - Driver workqueue for GEM.
262 *
263 * NOTE: Work items scheduled here are not allowed to grab any modeset
264 * locks, for otherwise the flushing done in the pageflip code will
265 * result in deadlocks.
266 */
267 struct workqueue_struct *wq;
268
269 /**
270 * unordered_wq - internal workqueue for unordered work
271 *
272 * This workqueue should be used for all unordered work
273 * scheduling within i915, which used to be scheduled on the
274 * system_wq before moving to a driver instance due
275 * deprecation of flush_scheduled_work().
276 */
277 struct workqueue_struct *unordered_wq;
278
279 /* pm private clock gating functions */
280 const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
281
282 /* PCH chipset type */
283 enum intel_pch pch_type;
284 unsigned short pch_id;
285
286 unsigned long gem_quirks;
287
288 struct i915_gem_mm mm;
289
290 struct intel_l3_parity l3_parity;
291
292 /*
293 * edram size in MB.
294 * Cannot be determined by PCIID. You must always read a register.
295 */
296 u32 edram_size_mb;
297
298 struct i915_gpu_error gpu_error;
299
300 u32 suspend_count;
301 struct i915_suspend_saved_registers regfile;
302 struct vlv_s0ix_state *vlv_s0ix_state;
303
304 struct dram_info {
305 bool wm_lv_0_adjust_needed;
306 u8 num_channels;
307 bool symmetric_memory;
308 enum intel_dram_type {
309 INTEL_DRAM_UNKNOWN,
310 INTEL_DRAM_DDR3,
311 INTEL_DRAM_DDR4,
312 INTEL_DRAM_LPDDR3,
313 INTEL_DRAM_LPDDR4,
314 INTEL_DRAM_DDR5,
315 INTEL_DRAM_LPDDR5,
316 } type;
317 u8 num_qgv_points;
318 u8 num_psf_gv_points;
319 } dram_info;
320
321 struct intel_runtime_pm runtime_pm;
322
323 struct i915_perf perf;
324
325 struct i915_hwmon *hwmon;
326
327 struct intel_gt *gt[I915_MAX_GT];
328
329 struct kobject *sysfs_gt;
330
331 /* Quick lookup of media GT (current platforms only have one) */
332 struct intel_gt *media_gt;
333
334 struct {
335 struct i915_gem_contexts {
336 spinlock_t lock; /* locks list */
337 struct list_head list;
338 } contexts;
339
340 /*
341 * We replace the local file with a global mappings as the
342 * backing storage for the mmap is on the device and not
343 * on the struct file, and we do not want to prolong the
344 * lifetime of the local fd. To minimise the number of
345 * anonymous inodes we create, we use a global singleton to
346 * share the global mapping.
347 */
348 struct file *mmap_singleton;
349 } gem;
350
351 struct intel_pxp *pxp;
352
353 /* For i915gm/i945gm vblank irq workaround */
354 u8 vblank_enabled;
355
356 bool irq_enabled;
357
358 struct i915_pmu pmu;
359
360 /* The TTM device structure. */
361 struct ttm_device bdev;
362
363 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
364
365 /*
366 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
367 * will be rejected. Instead look for a better place.
368 */
369};
370
371static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
372{
373 return container_of(dev, struct drm_i915_private, drm);
374}
375
376static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
377{
378 return dev_get_drvdata(kdev);
379}
380
381static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
382{
383 return pci_get_drvdata(pdev);
384}
385
386static inline struct intel_gt *to_gt(const struct drm_i915_private *i915)
387{
388 return i915->gt[0];
389}
390
391#define rb_to_uabi_engine(rb) \
392 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
393
394#define for_each_uabi_engine(engine__, i915__) \
395 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
396 (engine__); \
397 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
398
399#define INTEL_INFO(i915) ((i915)->__info)
400#define RUNTIME_INFO(i915) (&(i915)->__runtime)
401#define DRIVER_CAPS(i915) (&(i915)->caps)
402
403#define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id)
404
405#define IP_VER(ver, rel) ((ver) << 8 | (rel))
406
407#define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver)
408#define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
409 RUNTIME_INFO(i915)->graphics.ip.rel)
410#define IS_GRAPHICS_VER(i915, from, until) \
411 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
412
413#define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver)
414#define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
415 RUNTIME_INFO(i915)->media.ip.rel)
416#define IS_MEDIA_VER(i915, from, until) \
417 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
418
419#define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision)
420
421#define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
422#define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
423#define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
424#define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step)
425
426#define IS_DISPLAY_STEP(__i915, since, until) \
427 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
428 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
429
430#define IS_GRAPHICS_STEP(__i915, since, until) \
431 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \
432 INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until))
433
434#define IS_MEDIA_STEP(__i915, since, until) \
435 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
436 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until))
437
438#define IS_BASEDIE_STEP(__i915, since, until) \
439 (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \
440 INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until))
441
442static __always_inline unsigned int
443__platform_mask_index(const struct intel_runtime_info *info,
444 enum intel_platform p)
445{
446 const unsigned int pbits =
447 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
448
449 /* Expand the platform_mask array if this fails. */
450 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
451 pbits * ARRAY_SIZE(info->platform_mask));
452
453 return p / pbits;
454}
455
456static __always_inline unsigned int
457__platform_mask_bit(const struct intel_runtime_info *info,
458 enum intel_platform p)
459{
460 const unsigned int pbits =
461 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
462
463 return p % pbits + INTEL_SUBPLATFORM_BITS;
464}
465
466static inline u32
467intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
468{
469 const unsigned int pi = __platform_mask_index(info, p);
470
471 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
472}
473
474static __always_inline bool
475IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
476{
477 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
478 const unsigned int pi = __platform_mask_index(info, p);
479 const unsigned int pb = __platform_mask_bit(info, p);
480
481 BUILD_BUG_ON(!__builtin_constant_p(p));
482
483 return info->platform_mask[pi] & BIT(pb);
484}
485
486static __always_inline bool
487IS_SUBPLATFORM(const struct drm_i915_private *i915,
488 enum intel_platform p, unsigned int s)
489{
490 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
491 const unsigned int pi = __platform_mask_index(info, p);
492 const unsigned int pb = __platform_mask_bit(info, p);
493 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
494 const u32 mask = info->platform_mask[pi];
495
496 BUILD_BUG_ON(!__builtin_constant_p(p));
497 BUILD_BUG_ON(!__builtin_constant_p(s));
498 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
499
500 /* Shift and test on the MSB position so sign flag can be used. */
501 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
502}
503
504#define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile)
505#define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx)
506
507#define IS_I830(i915) IS_PLATFORM(i915, INTEL_I830)
508#define IS_I845G(i915) IS_PLATFORM(i915, INTEL_I845G)
509#define IS_I85X(i915) IS_PLATFORM(i915, INTEL_I85X)
510#define IS_I865G(i915) IS_PLATFORM(i915, INTEL_I865G)
511#define IS_I915G(i915) IS_PLATFORM(i915, INTEL_I915G)
512#define IS_I915GM(i915) IS_PLATFORM(i915, INTEL_I915GM)
513#define IS_I945G(i915) IS_PLATFORM(i915, INTEL_I945G)
514#define IS_I945GM(i915) IS_PLATFORM(i915, INTEL_I945GM)
515#define IS_I965G(i915) IS_PLATFORM(i915, INTEL_I965G)
516#define IS_I965GM(i915) IS_PLATFORM(i915, INTEL_I965GM)
517#define IS_G45(i915) IS_PLATFORM(i915, INTEL_G45)
518#define IS_GM45(i915) IS_PLATFORM(i915, INTEL_GM45)
519#define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915))
520#define IS_PINEVIEW(i915) IS_PLATFORM(i915, INTEL_PINEVIEW)
521#define IS_G33(i915) IS_PLATFORM(i915, INTEL_G33)
522#define IS_IRONLAKE(i915) IS_PLATFORM(i915, INTEL_IRONLAKE)
523#define IS_IRONLAKE_M(i915) \
524 (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915))
525#define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE)
526#define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE)
527#define IS_IVB_GT1(i915) (IS_IVYBRIDGE(i915) && \
528 INTEL_INFO(i915)->gt == 1)
529#define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW)
530#define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW)
531#define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL)
532#define IS_BROADWELL(i915) IS_PLATFORM(i915, INTEL_BROADWELL)
533#define IS_SKYLAKE(i915) IS_PLATFORM(i915, INTEL_SKYLAKE)
534#define IS_BROXTON(i915) IS_PLATFORM(i915, INTEL_BROXTON)
535#define IS_KABYLAKE(i915) IS_PLATFORM(i915, INTEL_KABYLAKE)
536#define IS_GEMINILAKE(i915) IS_PLATFORM(i915, INTEL_GEMINILAKE)
537#define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE)
538#define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE)
539#define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE)
540#define IS_JASPERLAKE(i915) IS_PLATFORM(i915, INTEL_JASPERLAKE)
541#define IS_ELKHARTLAKE(i915) IS_PLATFORM(i915, INTEL_ELKHARTLAKE)
542#define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE)
543#define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE)
544#define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1)
545#define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S)
546#define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P)
547#define IS_XEHPSDV(i915) IS_PLATFORM(i915, INTEL_XEHPSDV)
548#define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2)
549#define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
550#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
551#define IS_LUNARLAKE(i915) 0
552
553#define IS_DG2_G10(i915) \
554 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
555#define IS_DG2_G11(i915) \
556 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
557#define IS_DG2_G12(i915) \
558 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
559#define IS_RAPTORLAKE_S(i915) \
560 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
561#define IS_ALDERLAKE_P_N(i915) \
562 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
563#define IS_RAPTORLAKE_P(i915) \
564 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
565#define IS_RAPTORLAKE_U(i915) \
566 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
567#define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \
568 (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
569#define IS_BROADWELL_ULT(i915) \
570 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
571#define IS_BROADWELL_ULX(i915) \
572 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
573#define IS_BROADWELL_GT3(i915) (IS_BROADWELL(i915) && \
574 INTEL_INFO(i915)->gt == 3)
575#define IS_HASWELL_ULT(i915) \
576 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
577#define IS_HASWELL_GT3(i915) (IS_HASWELL(i915) && \
578 INTEL_INFO(i915)->gt == 3)
579#define IS_HASWELL_GT1(i915) (IS_HASWELL(i915) && \
580 INTEL_INFO(i915)->gt == 1)
581/* ULX machines are also considered ULT. */
582#define IS_HASWELL_ULX(i915) \
583 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
584#define IS_SKYLAKE_ULT(i915) \
585 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
586#define IS_SKYLAKE_ULX(i915) \
587 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
588#define IS_KABYLAKE_ULT(i915) \
589 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
590#define IS_KABYLAKE_ULX(i915) \
591 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
592#define IS_SKYLAKE_GT2(i915) (IS_SKYLAKE(i915) && \
593 INTEL_INFO(i915)->gt == 2)
594#define IS_SKYLAKE_GT3(i915) (IS_SKYLAKE(i915) && \
595 INTEL_INFO(i915)->gt == 3)
596#define IS_SKYLAKE_GT4(i915) (IS_SKYLAKE(i915) && \
597 INTEL_INFO(i915)->gt == 4)
598#define IS_KABYLAKE_GT2(i915) (IS_KABYLAKE(i915) && \
599 INTEL_INFO(i915)->gt == 2)
600#define IS_KABYLAKE_GT3(i915) (IS_KABYLAKE(i915) && \
601 INTEL_INFO(i915)->gt == 3)
602#define IS_COFFEELAKE_ULT(i915) \
603 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
604#define IS_COFFEELAKE_ULX(i915) \
605 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
606#define IS_COFFEELAKE_GT2(i915) (IS_COFFEELAKE(i915) && \
607 INTEL_INFO(i915)->gt == 2)
608#define IS_COFFEELAKE_GT3(i915) (IS_COFFEELAKE(i915) && \
609 INTEL_INFO(i915)->gt == 3)
610
611#define IS_COMETLAKE_ULT(i915) \
612 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
613#define IS_COMETLAKE_ULX(i915) \
614 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
615#define IS_COMETLAKE_GT2(i915) (IS_COMETLAKE(i915) && \
616 INTEL_INFO(i915)->gt == 2)
617
618#define IS_ICL_WITH_PORT_F(i915) \
619 IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
620
621#define IS_TIGERLAKE_UY(i915) \
622 IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
623
624#define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
625 (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
626
627#define IS_PVC_BD_STEP(__i915, since, until) \
628 (IS_PONTEVECCHIO(__i915) && \
629 IS_BASEDIE_STEP(__i915, since, until))
630
631#define IS_PVC_CT_STEP(__i915, since, until) \
632 (IS_PONTEVECCHIO(__i915) && \
633 IS_GRAPHICS_STEP(__i915, since, until))
634
635#define IS_LP(i915) (INTEL_INFO(i915)->is_lp)
636#define IS_GEN9_LP(i915) (GRAPHICS_VER(i915) == 9 && IS_LP(i915))
637#define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_LP(i915))
638
639#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
640#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
641
642#define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \
643 unsigned int first__ = (first); \
644 unsigned int count__ = (count); \
645 ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \
646})
647
648#define ENGINE_INSTANCES_MASK(gt, first, count) \
649 __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
650
651#define RCS_MASK(gt) \
652 ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
653#define BCS_MASK(gt) \
654 ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
655#define VDBOX_MASK(gt) \
656 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
657#define VEBOX_MASK(gt) \
658 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
659#define CCS_MASK(gt) \
660 ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
661
662#define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode)
663
664/*
665 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
666 * All later gens can run the final buffer from the ppgtt
667 */
668#define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7)
669
670#define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc)
671#define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop)
672#define HAS_EDRAM(i915) ((i915)->edram_size_mb)
673#define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6)
674#define HAS_WT(i915) HAS_EDRAM(i915)
675
676#define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical)
677
678#define HAS_LOGICAL_RING_CONTEXTS(i915) \
679 (INTEL_INFO(i915)->has_logical_ring_contexts)
680#define HAS_LOGICAL_RING_ELSQ(i915) \
681 (INTEL_INFO(i915)->has_logical_ring_elsq)
682
683#define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915)
684
685#define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type)
686#define HAS_PPGTT(i915) \
687 (INTEL_PPGTT(i915) != INTEL_PPGTT_NONE)
688#define HAS_FULL_PPGTT(i915) \
689 (INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL)
690
691#define HAS_PAGE_SIZES(i915, sizes) ({ \
692 GEM_BUG_ON((sizes) == 0); \
693 ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
694})
695
696/* Early gen2 have a totally busted CS tlb and require pinned batches. */
697#define HAS_BROKEN_CS_TLB(i915) (IS_I830(i915) || IS_I845G(i915))
698
699#define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \
700 (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9)
701
702/* WaRsDisableCoarsePowerGating:skl,cnl */
703#define NEEDS_WaRsDisableCoarsePowerGating(i915) \
704 (IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915))
705
706/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
707 * rows, which changed the alignment requirements and fence programming.
708 */
709#define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
710 !(IS_I915G(i915) || IS_I915GM(i915)))
711
712#define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6)
713#define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p)
714#define HAS_RC6pp(i915) (false) /* HW was never validated */
715
716#define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps)
717
718#define HAS_HECI_PXP(i915) \
719 (INTEL_INFO(i915)->has_heci_pxp)
720
721#define HAS_HECI_GSCFI(i915) \
722 (INTEL_INFO(i915)->has_heci_gscfi)
723
724#define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915))
725
726#define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm)
727#define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc)
728
729#define HAS_OA_BPC_REPORTING(i915) \
730 (INTEL_INFO(i915)->has_oa_bpc_reporting)
731#define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \
732 (INTEL_INFO(i915)->has_oa_slice_contrib_limits)
733#define HAS_OAM(i915) \
734 (INTEL_INFO(i915)->has_oam)
735
736/*
737 * Set this flag, when platform requires 64K GTT page sizes or larger for
738 * device local memory access.
739 */
740#define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
741
742#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
743#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
744
745#define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list)
746
747/*
748 * Platform has the dedicated compression control state for each lmem surfaces
749 * stored in lmem to support the 3D and media compression formats.
750 */
751#define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs)
752
753#define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc)
754
755#define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu)
756
757#define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs)
758
759#define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
760
761#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
762
763/* DPF == dynamic parity feature */
764#define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf)
765#define NUM_L3_SLICES(i915) (IS_HASWELL_GT3(i915) ? \
766 2 : HAS_L3_DPF(i915))
767
768#define HAS_GUC_DEPRIVILEGE(i915) \
769 (INTEL_INFO(i915)->has_guc_deprivilege)
770
771#define HAS_GUC_TLB_INVALIDATION(i915) (INTEL_INFO(i915)->has_guc_tlb_invalidation)
772
773#define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
774
775#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
776
777#define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
778 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
779
780#endif
1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include <uapi/drm/i915_drm.h>
34
35#include "i915_reg.h"
36#include "intel_bios.h"
37#include "intel_ringbuffer.h"
38#include <linux/io-mapping.h>
39#include <linux/i2c.h>
40#include <linux/i2c-algo-bit.h>
41#include <drm/intel-gtt.h>
42#include <linux/backlight.h>
43#include <linux/intel-iommu.h>
44#include <linux/kref.h>
45#include <linux/pm_qos.h>
46
47/* General customization:
48 */
49
50#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
51
52#define DRIVER_NAME "i915"
53#define DRIVER_DESC "Intel Graphics"
54#define DRIVER_DATE "20080730"
55
56enum pipe {
57 INVALID_PIPE = -1,
58 PIPE_A = 0,
59 PIPE_B,
60 PIPE_C,
61 _PIPE_EDP,
62 I915_MAX_PIPES = _PIPE_EDP
63};
64#define pipe_name(p) ((p) + 'A')
65
66enum transcoder {
67 TRANSCODER_A = 0,
68 TRANSCODER_B,
69 TRANSCODER_C,
70 TRANSCODER_EDP,
71 I915_MAX_TRANSCODERS
72};
73#define transcoder_name(t) ((t) + 'A')
74
75enum plane {
76 PLANE_A = 0,
77 PLANE_B,
78 PLANE_C,
79};
80#define plane_name(p) ((p) + 'A')
81
82#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
83
84enum port {
85 PORT_A = 0,
86 PORT_B,
87 PORT_C,
88 PORT_D,
89 PORT_E,
90 I915_MAX_PORTS
91};
92#define port_name(p) ((p) + 'A')
93
94#define I915_NUM_PHYS_VLV 1
95
96enum dpio_channel {
97 DPIO_CH0,
98 DPIO_CH1
99};
100
101enum dpio_phy {
102 DPIO_PHY0,
103 DPIO_PHY1
104};
105
106enum intel_display_power_domain {
107 POWER_DOMAIN_PIPE_A,
108 POWER_DOMAIN_PIPE_B,
109 POWER_DOMAIN_PIPE_C,
110 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
111 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
112 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
113 POWER_DOMAIN_TRANSCODER_A,
114 POWER_DOMAIN_TRANSCODER_B,
115 POWER_DOMAIN_TRANSCODER_C,
116 POWER_DOMAIN_TRANSCODER_EDP,
117 POWER_DOMAIN_PORT_DDI_A_2_LANES,
118 POWER_DOMAIN_PORT_DDI_A_4_LANES,
119 POWER_DOMAIN_PORT_DDI_B_2_LANES,
120 POWER_DOMAIN_PORT_DDI_B_4_LANES,
121 POWER_DOMAIN_PORT_DDI_C_2_LANES,
122 POWER_DOMAIN_PORT_DDI_C_4_LANES,
123 POWER_DOMAIN_PORT_DDI_D_2_LANES,
124 POWER_DOMAIN_PORT_DDI_D_4_LANES,
125 POWER_DOMAIN_PORT_DSI,
126 POWER_DOMAIN_PORT_CRT,
127 POWER_DOMAIN_PORT_OTHER,
128 POWER_DOMAIN_VGA,
129 POWER_DOMAIN_AUDIO,
130 POWER_DOMAIN_INIT,
131
132 POWER_DOMAIN_NUM,
133};
134
135#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
136#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
137 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
138#define POWER_DOMAIN_TRANSCODER(tran) \
139 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
140 (tran) + POWER_DOMAIN_TRANSCODER_A)
141
142enum hpd_pin {
143 HPD_NONE = 0,
144 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
145 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
146 HPD_CRT,
147 HPD_SDVO_B,
148 HPD_SDVO_C,
149 HPD_PORT_B,
150 HPD_PORT_C,
151 HPD_PORT_D,
152 HPD_NUM_PINS
153};
154
155#define I915_GEM_GPU_DOMAINS \
156 (I915_GEM_DOMAIN_RENDER | \
157 I915_GEM_DOMAIN_SAMPLER | \
158 I915_GEM_DOMAIN_COMMAND | \
159 I915_GEM_DOMAIN_INSTRUCTION | \
160 I915_GEM_DOMAIN_VERTEX)
161
162#define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
163#define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
164
165#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
166 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
167 if ((intel_encoder)->base.crtc == (__crtc))
168
169#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
170 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
171 if ((intel_connector)->base.encoder == (__encoder))
172
173struct drm_i915_private;
174
175enum intel_dpll_id {
176 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
177 /* real shared dpll ids must be >= 0 */
178 DPLL_ID_PCH_PLL_A,
179 DPLL_ID_PCH_PLL_B,
180};
181#define I915_NUM_PLLS 2
182
183struct intel_dpll_hw_state {
184 uint32_t dpll;
185 uint32_t dpll_md;
186 uint32_t fp0;
187 uint32_t fp1;
188};
189
190struct intel_shared_dpll {
191 int refcount; /* count of number of CRTCs sharing this PLL */
192 int active; /* count of number of active CRTCs (i.e. DPMS on) */
193 bool on; /* is the PLL actually active? Disabled during modeset */
194 const char *name;
195 /* should match the index in the dev_priv->shared_dplls array */
196 enum intel_dpll_id id;
197 struct intel_dpll_hw_state hw_state;
198 void (*mode_set)(struct drm_i915_private *dev_priv,
199 struct intel_shared_dpll *pll);
200 void (*enable)(struct drm_i915_private *dev_priv,
201 struct intel_shared_dpll *pll);
202 void (*disable)(struct drm_i915_private *dev_priv,
203 struct intel_shared_dpll *pll);
204 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
205 struct intel_shared_dpll *pll,
206 struct intel_dpll_hw_state *hw_state);
207};
208
209/* Used by dp and fdi links */
210struct intel_link_m_n {
211 uint32_t tu;
212 uint32_t gmch_m;
213 uint32_t gmch_n;
214 uint32_t link_m;
215 uint32_t link_n;
216};
217
218void intel_link_compute_m_n(int bpp, int nlanes,
219 int pixel_clock, int link_clock,
220 struct intel_link_m_n *m_n);
221
222struct intel_ddi_plls {
223 int spll_refcount;
224 int wrpll1_refcount;
225 int wrpll2_refcount;
226};
227
228/* Interface history:
229 *
230 * 1.1: Original.
231 * 1.2: Add Power Management
232 * 1.3: Add vblank support
233 * 1.4: Fix cmdbuffer path, add heap destroy
234 * 1.5: Add vblank pipe configuration
235 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
236 * - Support vertical blank on secondary display pipe
237 */
238#define DRIVER_MAJOR 1
239#define DRIVER_MINOR 6
240#define DRIVER_PATCHLEVEL 0
241
242#define WATCH_LISTS 0
243#define WATCH_GTT 0
244
245struct opregion_header;
246struct opregion_acpi;
247struct opregion_swsci;
248struct opregion_asle;
249
250struct intel_opregion {
251 struct opregion_header __iomem *header;
252 struct opregion_acpi __iomem *acpi;
253 struct opregion_swsci __iomem *swsci;
254 u32 swsci_gbda_sub_functions;
255 u32 swsci_sbcb_sub_functions;
256 struct opregion_asle __iomem *asle;
257 void __iomem *vbt;
258 u32 __iomem *lid_state;
259 struct work_struct asle_work;
260};
261#define OPREGION_SIZE (8*1024)
262
263struct intel_overlay;
264struct intel_overlay_error_state;
265
266struct drm_i915_master_private {
267 drm_local_map_t *sarea;
268 struct _drm_i915_sarea *sarea_priv;
269};
270#define I915_FENCE_REG_NONE -1
271#define I915_MAX_NUM_FENCES 32
272/* 32 fences + sign bit for FENCE_REG_NONE */
273#define I915_MAX_NUM_FENCE_BITS 6
274
275struct drm_i915_fence_reg {
276 struct list_head lru_list;
277 struct drm_i915_gem_object *obj;
278 int pin_count;
279};
280
281struct sdvo_device_mapping {
282 u8 initialized;
283 u8 dvo_port;
284 u8 slave_addr;
285 u8 dvo_wiring;
286 u8 i2c_pin;
287 u8 ddc_pin;
288};
289
290struct intel_display_error_state;
291
292struct drm_i915_error_state {
293 struct kref ref;
294 struct timeval time;
295
296 char error_msg[128];
297 u32 reset_count;
298 u32 suspend_count;
299
300 /* Generic register state */
301 u32 eir;
302 u32 pgtbl_er;
303 u32 ier;
304 u32 ccid;
305 u32 derrmr;
306 u32 forcewake;
307 u32 error; /* gen6+ */
308 u32 err_int; /* gen7 */
309 u32 done_reg;
310 u32 gac_eco;
311 u32 gam_ecochk;
312 u32 gab_ctl;
313 u32 gfx_mode;
314 u32 extra_instdone[I915_NUM_INSTDONE_REG];
315 u32 pipestat[I915_MAX_PIPES];
316 u64 fence[I915_MAX_NUM_FENCES];
317 struct intel_overlay_error_state *overlay;
318 struct intel_display_error_state *display;
319
320 struct drm_i915_error_ring {
321 bool valid;
322 /* Software tracked state */
323 bool waiting;
324 int hangcheck_score;
325 enum intel_ring_hangcheck_action hangcheck_action;
326 int num_requests;
327
328 /* our own tracking of ring head and tail */
329 u32 cpu_ring_head;
330 u32 cpu_ring_tail;
331
332 u32 semaphore_seqno[I915_NUM_RINGS - 1];
333
334 /* Register state */
335 u32 tail;
336 u32 head;
337 u32 ctl;
338 u32 hws;
339 u32 ipeir;
340 u32 ipehr;
341 u32 instdone;
342 u32 bbstate;
343 u32 instpm;
344 u32 instps;
345 u32 seqno;
346 u64 bbaddr;
347 u64 acthd;
348 u32 fault_reg;
349 u32 faddr;
350 u32 rc_psmi; /* sleep state */
351 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
352
353 struct drm_i915_error_object {
354 int page_count;
355 u32 gtt_offset;
356 u32 *pages[0];
357 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
358
359 struct drm_i915_error_request {
360 long jiffies;
361 u32 seqno;
362 u32 tail;
363 } *requests;
364
365 struct {
366 u32 gfx_mode;
367 union {
368 u64 pdp[4];
369 u32 pp_dir_base;
370 };
371 } vm_info;
372
373 pid_t pid;
374 char comm[TASK_COMM_LEN];
375 } ring[I915_NUM_RINGS];
376 struct drm_i915_error_buffer {
377 u32 size;
378 u32 name;
379 u32 rseqno, wseqno;
380 u32 gtt_offset;
381 u32 read_domains;
382 u32 write_domain;
383 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
384 s32 pinned:2;
385 u32 tiling:2;
386 u32 dirty:1;
387 u32 purgeable:1;
388 s32 ring:4;
389 u32 cache_level:3;
390 } **active_bo, **pinned_bo;
391
392 u32 *active_bo_count, *pinned_bo_count;
393};
394
395struct intel_connector;
396struct intel_crtc_config;
397struct intel_plane_config;
398struct intel_crtc;
399struct intel_limit;
400struct dpll;
401
402struct drm_i915_display_funcs {
403 bool (*fbc_enabled)(struct drm_device *dev);
404 void (*enable_fbc)(struct drm_crtc *crtc);
405 void (*disable_fbc)(struct drm_device *dev);
406 int (*get_display_clock_speed)(struct drm_device *dev);
407 int (*get_fifo_size)(struct drm_device *dev, int plane);
408 /**
409 * find_dpll() - Find the best values for the PLL
410 * @limit: limits for the PLL
411 * @crtc: current CRTC
412 * @target: target frequency in kHz
413 * @refclk: reference clock frequency in kHz
414 * @match_clock: if provided, @best_clock P divider must
415 * match the P divider from @match_clock
416 * used for LVDS downclocking
417 * @best_clock: best PLL values found
418 *
419 * Returns true on success, false on failure.
420 */
421 bool (*find_dpll)(const struct intel_limit *limit,
422 struct drm_crtc *crtc,
423 int target, int refclk,
424 struct dpll *match_clock,
425 struct dpll *best_clock);
426 void (*update_wm)(struct drm_crtc *crtc);
427 void (*update_sprite_wm)(struct drm_plane *plane,
428 struct drm_crtc *crtc,
429 uint32_t sprite_width, int pixel_size,
430 bool enable, bool scaled);
431 void (*modeset_global_resources)(struct drm_device *dev);
432 /* Returns the active state of the crtc, and if the crtc is active,
433 * fills out the pipe-config with the hw state. */
434 bool (*get_pipe_config)(struct intel_crtc *,
435 struct intel_crtc_config *);
436 void (*get_plane_config)(struct intel_crtc *,
437 struct intel_plane_config *);
438 int (*crtc_mode_set)(struct drm_crtc *crtc,
439 int x, int y,
440 struct drm_framebuffer *old_fb);
441 void (*crtc_enable)(struct drm_crtc *crtc);
442 void (*crtc_disable)(struct drm_crtc *crtc);
443 void (*off)(struct drm_crtc *crtc);
444 void (*write_eld)(struct drm_connector *connector,
445 struct drm_crtc *crtc,
446 struct drm_display_mode *mode);
447 void (*fdi_link_train)(struct drm_crtc *crtc);
448 void (*init_clock_gating)(struct drm_device *dev);
449 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
450 struct drm_framebuffer *fb,
451 struct drm_i915_gem_object *obj,
452 uint32_t flags);
453 int (*update_primary_plane)(struct drm_crtc *crtc,
454 struct drm_framebuffer *fb,
455 int x, int y);
456 void (*hpd_irq_setup)(struct drm_device *dev);
457 /* clock updates for mode set */
458 /* cursor updates */
459 /* render clock increase/decrease */
460 /* display clock increase/decrease */
461 /* pll clock increase/decrease */
462
463 int (*setup_backlight)(struct intel_connector *connector);
464 uint32_t (*get_backlight)(struct intel_connector *connector);
465 void (*set_backlight)(struct intel_connector *connector,
466 uint32_t level);
467 void (*disable_backlight)(struct intel_connector *connector);
468 void (*enable_backlight)(struct intel_connector *connector);
469};
470
471struct intel_uncore_funcs {
472 void (*force_wake_get)(struct drm_i915_private *dev_priv,
473 int fw_engine);
474 void (*force_wake_put)(struct drm_i915_private *dev_priv,
475 int fw_engine);
476
477 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
478 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
479 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
480 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
481
482 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
483 uint8_t val, bool trace);
484 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
485 uint16_t val, bool trace);
486 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
487 uint32_t val, bool trace);
488 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
489 uint64_t val, bool trace);
490};
491
492struct intel_uncore {
493 spinlock_t lock; /** lock is also taken in irq contexts. */
494
495 struct intel_uncore_funcs funcs;
496
497 unsigned fifo_count;
498 unsigned forcewake_count;
499
500 unsigned fw_rendercount;
501 unsigned fw_mediacount;
502
503 struct timer_list force_wake_timer;
504};
505
506#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
507 func(is_mobile) sep \
508 func(is_i85x) sep \
509 func(is_i915g) sep \
510 func(is_i945gm) sep \
511 func(is_g33) sep \
512 func(need_gfx_hws) sep \
513 func(is_g4x) sep \
514 func(is_pineview) sep \
515 func(is_broadwater) sep \
516 func(is_crestline) sep \
517 func(is_ivybridge) sep \
518 func(is_valleyview) sep \
519 func(is_haswell) sep \
520 func(is_preliminary) sep \
521 func(has_fbc) sep \
522 func(has_pipe_cxsr) sep \
523 func(has_hotplug) sep \
524 func(cursor_needs_physical) sep \
525 func(has_overlay) sep \
526 func(overlay_needs_physical) sep \
527 func(supports_tv) sep \
528 func(has_llc) sep \
529 func(has_ddi) sep \
530 func(has_fpga_dbg)
531
532#define DEFINE_FLAG(name) u8 name:1
533#define SEP_SEMICOLON ;
534
535struct intel_device_info {
536 u32 display_mmio_offset;
537 u8 num_pipes:3;
538 u8 num_sprites[I915_MAX_PIPES];
539 u8 gen;
540 u8 ring_mask; /* Rings supported by the HW */
541 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
542 /* Register offsets for the various display pipes and transcoders */
543 int pipe_offsets[I915_MAX_TRANSCODERS];
544 int trans_offsets[I915_MAX_TRANSCODERS];
545 int dpll_offsets[I915_MAX_PIPES];
546 int dpll_md_offsets[I915_MAX_PIPES];
547 int palette_offsets[I915_MAX_PIPES];
548};
549
550#undef DEFINE_FLAG
551#undef SEP_SEMICOLON
552
553enum i915_cache_level {
554 I915_CACHE_NONE = 0,
555 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
556 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
557 caches, eg sampler/render caches, and the
558 large Last-Level-Cache. LLC is coherent with
559 the CPU, but L3 is only visible to the GPU. */
560 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
561};
562
563typedef uint32_t gen6_gtt_pte_t;
564
565/**
566 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
567 * VMA's presence cannot be guaranteed before binding, or after unbinding the
568 * object into/from the address space.
569 *
570 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
571 * will always be <= an objects lifetime. So object refcounting should cover us.
572 */
573struct i915_vma {
574 struct drm_mm_node node;
575 struct drm_i915_gem_object *obj;
576 struct i915_address_space *vm;
577
578 /** This object's place on the active/inactive lists */
579 struct list_head mm_list;
580
581 struct list_head vma_link; /* Link in the object's VMA list */
582
583 /** This vma's place in the batchbuffer or on the eviction list */
584 struct list_head exec_list;
585
586 /**
587 * Used for performing relocations during execbuffer insertion.
588 */
589 struct hlist_node exec_node;
590 unsigned long exec_handle;
591 struct drm_i915_gem_exec_object2 *exec_entry;
592
593 /**
594 * How many users have pinned this object in GTT space. The following
595 * users can each hold at most one reference: pwrite/pread, pin_ioctl
596 * (via user_pin_count), execbuffer (objects are not allowed multiple
597 * times for the same batchbuffer), and the framebuffer code. When
598 * switching/pageflipping, the framebuffer code has at most two buffers
599 * pinned per crtc.
600 *
601 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
602 * bits with absolutely no headroom. So use 4 bits. */
603 unsigned int pin_count:4;
604#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
605
606 /** Unmap an object from an address space. This usually consists of
607 * setting the valid PTE entries to a reserved scratch page. */
608 void (*unbind_vma)(struct i915_vma *vma);
609 /* Map an object into an address space with the given cache flags. */
610#define GLOBAL_BIND (1<<0)
611 void (*bind_vma)(struct i915_vma *vma,
612 enum i915_cache_level cache_level,
613 u32 flags);
614};
615
616struct i915_address_space {
617 struct drm_mm mm;
618 struct drm_device *dev;
619 struct list_head global_link;
620 unsigned long start; /* Start offset always 0 for dri2 */
621 size_t total; /* size addr space maps (ex. 2GB for ggtt) */
622
623 struct {
624 dma_addr_t addr;
625 struct page *page;
626 } scratch;
627
628 /**
629 * List of objects currently involved in rendering.
630 *
631 * Includes buffers having the contents of their GPU caches
632 * flushed, not necessarily primitives. last_rendering_seqno
633 * represents when the rendering involved will be completed.
634 *
635 * A reference is held on the buffer while on this list.
636 */
637 struct list_head active_list;
638
639 /**
640 * LRU list of objects which are not in the ringbuffer and
641 * are ready to unbind, but are still in the GTT.
642 *
643 * last_rendering_seqno is 0 while an object is in this list.
644 *
645 * A reference is not held on the buffer while on this list,
646 * as merely being GTT-bound shouldn't prevent its being
647 * freed, and we'll pull it off the list in the free path.
648 */
649 struct list_head inactive_list;
650
651 /* FIXME: Need a more generic return type */
652 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
653 enum i915_cache_level level,
654 bool valid); /* Create a valid PTE */
655 void (*clear_range)(struct i915_address_space *vm,
656 uint64_t start,
657 uint64_t length,
658 bool use_scratch);
659 void (*insert_entries)(struct i915_address_space *vm,
660 struct sg_table *st,
661 uint64_t start,
662 enum i915_cache_level cache_level);
663 void (*cleanup)(struct i915_address_space *vm);
664};
665
666/* The Graphics Translation Table is the way in which GEN hardware translates a
667 * Graphics Virtual Address into a Physical Address. In addition to the normal
668 * collateral associated with any va->pa translations GEN hardware also has a
669 * portion of the GTT which can be mapped by the CPU and remain both coherent
670 * and correct (in cases like swizzling). That region is referred to as GMADR in
671 * the spec.
672 */
673struct i915_gtt {
674 struct i915_address_space base;
675 size_t stolen_size; /* Total size of stolen memory */
676
677 unsigned long mappable_end; /* End offset that we can CPU map */
678 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
679 phys_addr_t mappable_base; /* PA of our GMADR */
680
681 /** "Graphics Stolen Memory" holds the global PTEs */
682 void __iomem *gsm;
683
684 bool do_idle_maps;
685
686 int mtrr;
687
688 /* global gtt ops */
689 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
690 size_t *stolen, phys_addr_t *mappable_base,
691 unsigned long *mappable_end);
692};
693#define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
694
695#define GEN8_LEGACY_PDPS 4
696struct i915_hw_ppgtt {
697 struct i915_address_space base;
698 struct kref ref;
699 struct drm_mm_node node;
700 unsigned num_pd_entries;
701 unsigned num_pd_pages; /* gen8+ */
702 union {
703 struct page **pt_pages;
704 struct page **gen8_pt_pages[GEN8_LEGACY_PDPS];
705 };
706 struct page *pd_pages;
707 union {
708 uint32_t pd_offset;
709 dma_addr_t pd_dma_addr[GEN8_LEGACY_PDPS];
710 };
711 union {
712 dma_addr_t *pt_dma_addr;
713 dma_addr_t *gen8_pt_dma_addr[4];
714 };
715
716 struct i915_hw_context *ctx;
717
718 int (*enable)(struct i915_hw_ppgtt *ppgtt);
719 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
720 struct intel_ring_buffer *ring,
721 bool synchronous);
722 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
723};
724
725struct i915_ctx_hang_stats {
726 /* This context had batch pending when hang was declared */
727 unsigned batch_pending;
728
729 /* This context had batch active when hang was declared */
730 unsigned batch_active;
731
732 /* Time when this context was last blamed for a GPU reset */
733 unsigned long guilty_ts;
734
735 /* This context is banned to submit more work */
736 bool banned;
737};
738
739/* This must match up with the value previously used for execbuf2.rsvd1. */
740#define DEFAULT_CONTEXT_ID 0
741struct i915_hw_context {
742 struct kref ref;
743 int id;
744 bool is_initialized;
745 uint8_t remap_slice;
746 struct drm_i915_file_private *file_priv;
747 struct intel_ring_buffer *last_ring;
748 struct drm_i915_gem_object *obj;
749 struct i915_ctx_hang_stats hang_stats;
750 struct i915_address_space *vm;
751
752 struct list_head link;
753};
754
755struct i915_fbc {
756 unsigned long size;
757 unsigned int fb_id;
758 enum plane plane;
759 int y;
760
761 struct drm_mm_node *compressed_fb;
762 struct drm_mm_node *compressed_llb;
763
764 struct intel_fbc_work {
765 struct delayed_work work;
766 struct drm_crtc *crtc;
767 struct drm_framebuffer *fb;
768 } *fbc_work;
769
770 enum no_fbc_reason {
771 FBC_OK, /* FBC is enabled */
772 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
773 FBC_NO_OUTPUT, /* no outputs enabled to compress */
774 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
775 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
776 FBC_MODE_TOO_LARGE, /* mode too large for compression */
777 FBC_BAD_PLANE, /* fbc not supported on plane */
778 FBC_NOT_TILED, /* buffer not tiled */
779 FBC_MULTIPLE_PIPES, /* more than one pipe active */
780 FBC_MODULE_PARAM,
781 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
782 } no_fbc_reason;
783};
784
785struct i915_psr {
786 bool sink_support;
787 bool source_ok;
788};
789
790enum intel_pch {
791 PCH_NONE = 0, /* No PCH present */
792 PCH_IBX, /* Ibexpeak PCH */
793 PCH_CPT, /* Cougarpoint PCH */
794 PCH_LPT, /* Lynxpoint PCH */
795 PCH_NOP,
796};
797
798enum intel_sbi_destination {
799 SBI_ICLK,
800 SBI_MPHY,
801};
802
803#define QUIRK_PIPEA_FORCE (1<<0)
804#define QUIRK_LVDS_SSC_DISABLE (1<<1)
805#define QUIRK_INVERT_BRIGHTNESS (1<<2)
806
807struct intel_fbdev;
808struct intel_fbc_work;
809
810struct intel_gmbus {
811 struct i2c_adapter adapter;
812 u32 force_bit;
813 u32 reg0;
814 u32 gpio_reg;
815 struct i2c_algo_bit_data bit_algo;
816 struct drm_i915_private *dev_priv;
817};
818
819struct i915_suspend_saved_registers {
820 u8 saveLBB;
821 u32 saveDSPACNTR;
822 u32 saveDSPBCNTR;
823 u32 saveDSPARB;
824 u32 savePIPEACONF;
825 u32 savePIPEBCONF;
826 u32 savePIPEASRC;
827 u32 savePIPEBSRC;
828 u32 saveFPA0;
829 u32 saveFPA1;
830 u32 saveDPLL_A;
831 u32 saveDPLL_A_MD;
832 u32 saveHTOTAL_A;
833 u32 saveHBLANK_A;
834 u32 saveHSYNC_A;
835 u32 saveVTOTAL_A;
836 u32 saveVBLANK_A;
837 u32 saveVSYNC_A;
838 u32 saveBCLRPAT_A;
839 u32 saveTRANSACONF;
840 u32 saveTRANS_HTOTAL_A;
841 u32 saveTRANS_HBLANK_A;
842 u32 saveTRANS_HSYNC_A;
843 u32 saveTRANS_VTOTAL_A;
844 u32 saveTRANS_VBLANK_A;
845 u32 saveTRANS_VSYNC_A;
846 u32 savePIPEASTAT;
847 u32 saveDSPASTRIDE;
848 u32 saveDSPASIZE;
849 u32 saveDSPAPOS;
850 u32 saveDSPAADDR;
851 u32 saveDSPASURF;
852 u32 saveDSPATILEOFF;
853 u32 savePFIT_PGM_RATIOS;
854 u32 saveBLC_HIST_CTL;
855 u32 saveBLC_PWM_CTL;
856 u32 saveBLC_PWM_CTL2;
857 u32 saveBLC_HIST_CTL_B;
858 u32 saveBLC_CPU_PWM_CTL;
859 u32 saveBLC_CPU_PWM_CTL2;
860 u32 saveFPB0;
861 u32 saveFPB1;
862 u32 saveDPLL_B;
863 u32 saveDPLL_B_MD;
864 u32 saveHTOTAL_B;
865 u32 saveHBLANK_B;
866 u32 saveHSYNC_B;
867 u32 saveVTOTAL_B;
868 u32 saveVBLANK_B;
869 u32 saveVSYNC_B;
870 u32 saveBCLRPAT_B;
871 u32 saveTRANSBCONF;
872 u32 saveTRANS_HTOTAL_B;
873 u32 saveTRANS_HBLANK_B;
874 u32 saveTRANS_HSYNC_B;
875 u32 saveTRANS_VTOTAL_B;
876 u32 saveTRANS_VBLANK_B;
877 u32 saveTRANS_VSYNC_B;
878 u32 savePIPEBSTAT;
879 u32 saveDSPBSTRIDE;
880 u32 saveDSPBSIZE;
881 u32 saveDSPBPOS;
882 u32 saveDSPBADDR;
883 u32 saveDSPBSURF;
884 u32 saveDSPBTILEOFF;
885 u32 saveVGA0;
886 u32 saveVGA1;
887 u32 saveVGA_PD;
888 u32 saveVGACNTRL;
889 u32 saveADPA;
890 u32 saveLVDS;
891 u32 savePP_ON_DELAYS;
892 u32 savePP_OFF_DELAYS;
893 u32 saveDVOA;
894 u32 saveDVOB;
895 u32 saveDVOC;
896 u32 savePP_ON;
897 u32 savePP_OFF;
898 u32 savePP_CONTROL;
899 u32 savePP_DIVISOR;
900 u32 savePFIT_CONTROL;
901 u32 save_palette_a[256];
902 u32 save_palette_b[256];
903 u32 saveFBC_CONTROL;
904 u32 saveIER;
905 u32 saveIIR;
906 u32 saveIMR;
907 u32 saveDEIER;
908 u32 saveDEIMR;
909 u32 saveGTIER;
910 u32 saveGTIMR;
911 u32 saveFDI_RXA_IMR;
912 u32 saveFDI_RXB_IMR;
913 u32 saveCACHE_MODE_0;
914 u32 saveMI_ARB_STATE;
915 u32 saveSWF0[16];
916 u32 saveSWF1[16];
917 u32 saveSWF2[3];
918 u8 saveMSR;
919 u8 saveSR[8];
920 u8 saveGR[25];
921 u8 saveAR_INDEX;
922 u8 saveAR[21];
923 u8 saveDACMASK;
924 u8 saveCR[37];
925 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
926 u32 saveCURACNTR;
927 u32 saveCURAPOS;
928 u32 saveCURABASE;
929 u32 saveCURBCNTR;
930 u32 saveCURBPOS;
931 u32 saveCURBBASE;
932 u32 saveCURSIZE;
933 u32 saveDP_B;
934 u32 saveDP_C;
935 u32 saveDP_D;
936 u32 savePIPEA_GMCH_DATA_M;
937 u32 savePIPEB_GMCH_DATA_M;
938 u32 savePIPEA_GMCH_DATA_N;
939 u32 savePIPEB_GMCH_DATA_N;
940 u32 savePIPEA_DP_LINK_M;
941 u32 savePIPEB_DP_LINK_M;
942 u32 savePIPEA_DP_LINK_N;
943 u32 savePIPEB_DP_LINK_N;
944 u32 saveFDI_RXA_CTL;
945 u32 saveFDI_TXA_CTL;
946 u32 saveFDI_RXB_CTL;
947 u32 saveFDI_TXB_CTL;
948 u32 savePFA_CTL_1;
949 u32 savePFB_CTL_1;
950 u32 savePFA_WIN_SZ;
951 u32 savePFB_WIN_SZ;
952 u32 savePFA_WIN_POS;
953 u32 savePFB_WIN_POS;
954 u32 savePCH_DREF_CONTROL;
955 u32 saveDISP_ARB_CTL;
956 u32 savePIPEA_DATA_M1;
957 u32 savePIPEA_DATA_N1;
958 u32 savePIPEA_LINK_M1;
959 u32 savePIPEA_LINK_N1;
960 u32 savePIPEB_DATA_M1;
961 u32 savePIPEB_DATA_N1;
962 u32 savePIPEB_LINK_M1;
963 u32 savePIPEB_LINK_N1;
964 u32 saveMCHBAR_RENDER_STANDBY;
965 u32 savePCH_PORT_HOTPLUG;
966};
967
968struct intel_gen6_power_mgmt {
969 /* work and pm_iir are protected by dev_priv->irq_lock */
970 struct work_struct work;
971 u32 pm_iir;
972
973 /* Frequencies are stored in potentially platform dependent multiples.
974 * In other words, *_freq needs to be multiplied by X to be interesting.
975 * Soft limits are those which are used for the dynamic reclocking done
976 * by the driver (raise frequencies under heavy loads, and lower for
977 * lighter loads). Hard limits are those imposed by the hardware.
978 *
979 * A distinction is made for overclocking, which is never enabled by
980 * default, and is considered to be above the hard limit if it's
981 * possible at all.
982 */
983 u8 cur_freq; /* Current frequency (cached, may not == HW) */
984 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
985 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
986 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
987 u8 min_freq; /* AKA RPn. Minimum frequency */
988 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
989 u8 rp1_freq; /* "less than" RP0 power/freqency */
990 u8 rp0_freq; /* Non-overclocked max frequency. */
991
992 int last_adj;
993 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
994
995 bool enabled;
996 struct delayed_work delayed_resume_work;
997
998 /*
999 * Protects RPS/RC6 register access and PCU communication.
1000 * Must be taken after struct_mutex if nested.
1001 */
1002 struct mutex hw_lock;
1003};
1004
1005/* defined intel_pm.c */
1006extern spinlock_t mchdev_lock;
1007
1008struct intel_ilk_power_mgmt {
1009 u8 cur_delay;
1010 u8 min_delay;
1011 u8 max_delay;
1012 u8 fmax;
1013 u8 fstart;
1014
1015 u64 last_count1;
1016 unsigned long last_time1;
1017 unsigned long chipset_power;
1018 u64 last_count2;
1019 struct timespec last_time2;
1020 unsigned long gfx_power;
1021 u8 corr;
1022
1023 int c_m;
1024 int r_t;
1025
1026 struct drm_i915_gem_object *pwrctx;
1027 struct drm_i915_gem_object *renderctx;
1028};
1029
1030struct drm_i915_private;
1031struct i915_power_well;
1032
1033struct i915_power_well_ops {
1034 /*
1035 * Synchronize the well's hw state to match the current sw state, for
1036 * example enable/disable it based on the current refcount. Called
1037 * during driver init and resume time, possibly after first calling
1038 * the enable/disable handlers.
1039 */
1040 void (*sync_hw)(struct drm_i915_private *dev_priv,
1041 struct i915_power_well *power_well);
1042 /*
1043 * Enable the well and resources that depend on it (for example
1044 * interrupts located on the well). Called after the 0->1 refcount
1045 * transition.
1046 */
1047 void (*enable)(struct drm_i915_private *dev_priv,
1048 struct i915_power_well *power_well);
1049 /*
1050 * Disable the well and resources that depend on it. Called after
1051 * the 1->0 refcount transition.
1052 */
1053 void (*disable)(struct drm_i915_private *dev_priv,
1054 struct i915_power_well *power_well);
1055 /* Returns the hw enabled state. */
1056 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1057 struct i915_power_well *power_well);
1058};
1059
1060/* Power well structure for haswell */
1061struct i915_power_well {
1062 const char *name;
1063 bool always_on;
1064 /* power well enable/disable usage count */
1065 int count;
1066 unsigned long domains;
1067 unsigned long data;
1068 const struct i915_power_well_ops *ops;
1069};
1070
1071struct i915_power_domains {
1072 /*
1073 * Power wells needed for initialization at driver init and suspend
1074 * time are on. They are kept on until after the first modeset.
1075 */
1076 bool init_power_on;
1077 int power_well_count;
1078
1079 struct mutex lock;
1080 int domain_use_count[POWER_DOMAIN_NUM];
1081 struct i915_power_well *power_wells;
1082};
1083
1084struct i915_dri1_state {
1085 unsigned allow_batchbuffer : 1;
1086 u32 __iomem *gfx_hws_cpu_addr;
1087
1088 unsigned int cpp;
1089 int back_offset;
1090 int front_offset;
1091 int current_page;
1092 int page_flipping;
1093
1094 uint32_t counter;
1095};
1096
1097struct i915_ums_state {
1098 /**
1099 * Flag if the X Server, and thus DRM, is not currently in
1100 * control of the device.
1101 *
1102 * This is set between LeaveVT and EnterVT. It needs to be
1103 * replaced with a semaphore. It also needs to be
1104 * transitioned away from for kernel modesetting.
1105 */
1106 int mm_suspended;
1107};
1108
1109#define MAX_L3_SLICES 2
1110struct intel_l3_parity {
1111 u32 *remap_info[MAX_L3_SLICES];
1112 struct work_struct error_work;
1113 int which_slice;
1114};
1115
1116struct i915_gem_mm {
1117 /** Memory allocator for GTT stolen memory */
1118 struct drm_mm stolen;
1119 /** List of all objects in gtt_space. Used to restore gtt
1120 * mappings on resume */
1121 struct list_head bound_list;
1122 /**
1123 * List of objects which are not bound to the GTT (thus
1124 * are idle and not used by the GPU) but still have
1125 * (presumably uncached) pages still attached.
1126 */
1127 struct list_head unbound_list;
1128
1129 /** Usable portion of the GTT for GEM */
1130 unsigned long stolen_base; /* limited to low memory (32-bit) */
1131
1132 /** PPGTT used for aliasing the PPGTT with the GTT */
1133 struct i915_hw_ppgtt *aliasing_ppgtt;
1134
1135 struct shrinker inactive_shrinker;
1136 bool shrinker_no_lock_stealing;
1137
1138 /** LRU list of objects with fence regs on them. */
1139 struct list_head fence_list;
1140
1141 /**
1142 * We leave the user IRQ off as much as possible,
1143 * but this means that requests will finish and never
1144 * be retired once the system goes idle. Set a timer to
1145 * fire periodically while the ring is running. When it
1146 * fires, go retire requests.
1147 */
1148 struct delayed_work retire_work;
1149
1150 /**
1151 * When we detect an idle GPU, we want to turn on
1152 * powersaving features. So once we see that there
1153 * are no more requests outstanding and no more
1154 * arrive within a small period of time, we fire
1155 * off the idle_work.
1156 */
1157 struct delayed_work idle_work;
1158
1159 /**
1160 * Are we in a non-interruptible section of code like
1161 * modesetting?
1162 */
1163 bool interruptible;
1164
1165 /**
1166 * Is the GPU currently considered idle, or busy executing userspace
1167 * requests? Whilst idle, we attempt to power down the hardware and
1168 * display clocks. In order to reduce the effect on performance, there
1169 * is a slight delay before we do so.
1170 */
1171 bool busy;
1172
1173 /** Bit 6 swizzling required for X tiling */
1174 uint32_t bit_6_swizzle_x;
1175 /** Bit 6 swizzling required for Y tiling */
1176 uint32_t bit_6_swizzle_y;
1177
1178 /* accounting, useful for userland debugging */
1179 spinlock_t object_stat_lock;
1180 size_t object_memory;
1181 u32 object_count;
1182};
1183
1184struct drm_i915_error_state_buf {
1185 unsigned bytes;
1186 unsigned size;
1187 int err;
1188 u8 *buf;
1189 loff_t start;
1190 loff_t pos;
1191};
1192
1193struct i915_error_state_file_priv {
1194 struct drm_device *dev;
1195 struct drm_i915_error_state *error;
1196};
1197
1198struct i915_gpu_error {
1199 /* For hangcheck timer */
1200#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1201#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1202 /* Hang gpu twice in this window and your context gets banned */
1203#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1204
1205 struct timer_list hangcheck_timer;
1206
1207 /* For reset and error_state handling. */
1208 spinlock_t lock;
1209 /* Protected by the above dev->gpu_error.lock. */
1210 struct drm_i915_error_state *first_error;
1211 struct work_struct work;
1212
1213
1214 unsigned long missed_irq_rings;
1215
1216 /**
1217 * State variable controlling the reset flow and count
1218 *
1219 * This is a counter which gets incremented when reset is triggered,
1220 * and again when reset has been handled. So odd values (lowest bit set)
1221 * means that reset is in progress and even values that
1222 * (reset_counter >> 1):th reset was successfully completed.
1223 *
1224 * If reset is not completed succesfully, the I915_WEDGE bit is
1225 * set meaning that hardware is terminally sour and there is no
1226 * recovery. All waiters on the reset_queue will be woken when
1227 * that happens.
1228 *
1229 * This counter is used by the wait_seqno code to notice that reset
1230 * event happened and it needs to restart the entire ioctl (since most
1231 * likely the seqno it waited for won't ever signal anytime soon).
1232 *
1233 * This is important for lock-free wait paths, where no contended lock
1234 * naturally enforces the correct ordering between the bail-out of the
1235 * waiter and the gpu reset work code.
1236 */
1237 atomic_t reset_counter;
1238
1239#define I915_RESET_IN_PROGRESS_FLAG 1
1240#define I915_WEDGED (1 << 31)
1241
1242 /**
1243 * Waitqueue to signal when the reset has completed. Used by clients
1244 * that wait for dev_priv->mm.wedged to settle.
1245 */
1246 wait_queue_head_t reset_queue;
1247
1248 /* For gpu hang simulation. */
1249 unsigned int stop_rings;
1250
1251 /* For missed irq/seqno simulation. */
1252 unsigned int test_irq_rings;
1253};
1254
1255enum modeset_restore {
1256 MODESET_ON_LID_OPEN,
1257 MODESET_DONE,
1258 MODESET_SUSPENDED,
1259};
1260
1261struct ddi_vbt_port_info {
1262 uint8_t hdmi_level_shift;
1263
1264 uint8_t supports_dvi:1;
1265 uint8_t supports_hdmi:1;
1266 uint8_t supports_dp:1;
1267};
1268
1269struct intel_vbt_data {
1270 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1271 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1272
1273 /* Feature bits */
1274 unsigned int int_tv_support:1;
1275 unsigned int lvds_dither:1;
1276 unsigned int lvds_vbt:1;
1277 unsigned int int_crt_support:1;
1278 unsigned int lvds_use_ssc:1;
1279 unsigned int display_clock_mode:1;
1280 unsigned int fdi_rx_polarity_inverted:1;
1281 int lvds_ssc_freq;
1282 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1283
1284 /* eDP */
1285 int edp_rate;
1286 int edp_lanes;
1287 int edp_preemphasis;
1288 int edp_vswing;
1289 bool edp_initialized;
1290 bool edp_support;
1291 int edp_bpp;
1292 struct edp_power_seq edp_pps;
1293
1294 struct {
1295 u16 pwm_freq_hz;
1296 bool present;
1297 bool active_low_pwm;
1298 } backlight;
1299
1300 /* MIPI DSI */
1301 struct {
1302 u16 panel_id;
1303 } dsi;
1304
1305 int crt_ddc_pin;
1306
1307 int child_dev_num;
1308 union child_device_config *child_dev;
1309
1310 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1311};
1312
1313enum intel_ddb_partitioning {
1314 INTEL_DDB_PART_1_2,
1315 INTEL_DDB_PART_5_6, /* IVB+ */
1316};
1317
1318struct intel_wm_level {
1319 bool enable;
1320 uint32_t pri_val;
1321 uint32_t spr_val;
1322 uint32_t cur_val;
1323 uint32_t fbc_val;
1324};
1325
1326struct ilk_wm_values {
1327 uint32_t wm_pipe[3];
1328 uint32_t wm_lp[3];
1329 uint32_t wm_lp_spr[3];
1330 uint32_t wm_linetime[3];
1331 bool enable_fbc_wm;
1332 enum intel_ddb_partitioning partitioning;
1333};
1334
1335/*
1336 * This struct helps tracking the state needed for runtime PM, which puts the
1337 * device in PCI D3 state. Notice that when this happens, nothing on the
1338 * graphics device works, even register access, so we don't get interrupts nor
1339 * anything else.
1340 *
1341 * Every piece of our code that needs to actually touch the hardware needs to
1342 * either call intel_runtime_pm_get or call intel_display_power_get with the
1343 * appropriate power domain.
1344 *
1345 * Our driver uses the autosuspend delay feature, which means we'll only really
1346 * suspend if we stay with zero refcount for a certain amount of time. The
1347 * default value is currently very conservative (see intel_init_runtime_pm), but
1348 * it can be changed with the standard runtime PM files from sysfs.
1349 *
1350 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1351 * goes back to false exactly before we reenable the IRQs. We use this variable
1352 * to check if someone is trying to enable/disable IRQs while they're supposed
1353 * to be disabled. This shouldn't happen and we'll print some error messages in
1354 * case it happens, but if it actually happens we'll also update the variables
1355 * inside struct regsave so when we restore the IRQs they will contain the
1356 * latest expected values.
1357 *
1358 * For more, read the Documentation/power/runtime_pm.txt.
1359 */
1360struct i915_runtime_pm {
1361 bool suspended;
1362 bool irqs_disabled;
1363
1364 struct {
1365 uint32_t deimr;
1366 uint32_t sdeimr;
1367 uint32_t gtimr;
1368 uint32_t gtier;
1369 uint32_t gen6_pmimr;
1370 } regsave;
1371};
1372
1373enum intel_pipe_crc_source {
1374 INTEL_PIPE_CRC_SOURCE_NONE,
1375 INTEL_PIPE_CRC_SOURCE_PLANE1,
1376 INTEL_PIPE_CRC_SOURCE_PLANE2,
1377 INTEL_PIPE_CRC_SOURCE_PF,
1378 INTEL_PIPE_CRC_SOURCE_PIPE,
1379 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1380 INTEL_PIPE_CRC_SOURCE_TV,
1381 INTEL_PIPE_CRC_SOURCE_DP_B,
1382 INTEL_PIPE_CRC_SOURCE_DP_C,
1383 INTEL_PIPE_CRC_SOURCE_DP_D,
1384 INTEL_PIPE_CRC_SOURCE_AUTO,
1385 INTEL_PIPE_CRC_SOURCE_MAX,
1386};
1387
1388struct intel_pipe_crc_entry {
1389 uint32_t frame;
1390 uint32_t crc[5];
1391};
1392
1393#define INTEL_PIPE_CRC_ENTRIES_NR 128
1394struct intel_pipe_crc {
1395 spinlock_t lock;
1396 bool opened; /* exclusive access to the result file */
1397 struct intel_pipe_crc_entry *entries;
1398 enum intel_pipe_crc_source source;
1399 int head, tail;
1400 wait_queue_head_t wq;
1401};
1402
1403typedef struct drm_i915_private {
1404 struct drm_device *dev;
1405 struct kmem_cache *slab;
1406
1407 const struct intel_device_info info;
1408
1409 int relative_constants_mode;
1410
1411 void __iomem *regs;
1412
1413 struct intel_uncore uncore;
1414
1415 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1416
1417
1418 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1419 * controller on different i2c buses. */
1420 struct mutex gmbus_mutex;
1421
1422 /**
1423 * Base address of the gmbus and gpio block.
1424 */
1425 uint32_t gpio_mmio_base;
1426
1427 wait_queue_head_t gmbus_wait_queue;
1428
1429 struct pci_dev *bridge_dev;
1430 struct intel_ring_buffer ring[I915_NUM_RINGS];
1431 uint32_t last_seqno, next_seqno;
1432
1433 drm_dma_handle_t *status_page_dmah;
1434 struct resource mch_res;
1435
1436 /* protects the irq masks */
1437 spinlock_t irq_lock;
1438
1439 bool display_irqs_enabled;
1440
1441 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1442 struct pm_qos_request pm_qos;
1443
1444 /* DPIO indirect register protection */
1445 struct mutex dpio_lock;
1446
1447 /** Cached value of IMR to avoid reads in updating the bitfield */
1448 union {
1449 u32 irq_mask;
1450 u32 de_irq_mask[I915_MAX_PIPES];
1451 };
1452 u32 gt_irq_mask;
1453 u32 pm_irq_mask;
1454 u32 pm_rps_events;
1455 u32 pipestat_irq_mask[I915_MAX_PIPES];
1456
1457 struct work_struct hotplug_work;
1458 bool enable_hotplug_processing;
1459 struct {
1460 unsigned long hpd_last_jiffies;
1461 int hpd_cnt;
1462 enum {
1463 HPD_ENABLED = 0,
1464 HPD_DISABLED = 1,
1465 HPD_MARK_DISABLED = 2
1466 } hpd_mark;
1467 } hpd_stats[HPD_NUM_PINS];
1468 u32 hpd_event_bits;
1469 struct timer_list hotplug_reenable_timer;
1470
1471 struct i915_fbc fbc;
1472 struct intel_opregion opregion;
1473 struct intel_vbt_data vbt;
1474
1475 /* overlay */
1476 struct intel_overlay *overlay;
1477
1478 /* backlight registers and fields in struct intel_panel */
1479 spinlock_t backlight_lock;
1480
1481 /* LVDS info */
1482 bool no_aux_handshake;
1483
1484 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1485 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1486 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1487
1488 unsigned int fsb_freq, mem_freq, is_ddr3;
1489
1490 /**
1491 * wq - Driver workqueue for GEM.
1492 *
1493 * NOTE: Work items scheduled here are not allowed to grab any modeset
1494 * locks, for otherwise the flushing done in the pageflip code will
1495 * result in deadlocks.
1496 */
1497 struct workqueue_struct *wq;
1498
1499 /* Display functions */
1500 struct drm_i915_display_funcs display;
1501
1502 /* PCH chipset type */
1503 enum intel_pch pch_type;
1504 unsigned short pch_id;
1505
1506 unsigned long quirks;
1507
1508 enum modeset_restore modeset_restore;
1509 struct mutex modeset_restore_lock;
1510
1511 struct list_head vm_list; /* Global list of all address spaces */
1512 struct i915_gtt gtt; /* VMA representing the global address space */
1513
1514 struct i915_gem_mm mm;
1515
1516 /* Kernel Modesetting */
1517
1518 struct sdvo_device_mapping sdvo_mappings[2];
1519
1520 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1521 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1522 wait_queue_head_t pending_flip_queue;
1523
1524#ifdef CONFIG_DEBUG_FS
1525 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1526#endif
1527
1528 int num_shared_dpll;
1529 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1530 struct intel_ddi_plls ddi_plls;
1531 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1532
1533 /* Reclocking support */
1534 bool render_reclock_avail;
1535 bool lvds_downclock_avail;
1536 /* indicates the reduced downclock for LVDS*/
1537 int lvds_downclock;
1538 u16 orig_clock;
1539
1540 bool mchbar_need_disable;
1541
1542 struct intel_l3_parity l3_parity;
1543
1544 /* Cannot be determined by PCIID. You must always read a register. */
1545 size_t ellc_size;
1546
1547 /* gen6+ rps state */
1548 struct intel_gen6_power_mgmt rps;
1549
1550 /* ilk-only ips/rps state. Everything in here is protected by the global
1551 * mchdev_lock in intel_pm.c */
1552 struct intel_ilk_power_mgmt ips;
1553
1554 struct i915_power_domains power_domains;
1555
1556 struct i915_psr psr;
1557
1558 struct i915_gpu_error gpu_error;
1559
1560 struct drm_i915_gem_object *vlv_pctx;
1561
1562#ifdef CONFIG_DRM_I915_FBDEV
1563 /* list of fbdev register on this device */
1564 struct intel_fbdev *fbdev;
1565#endif
1566
1567 /*
1568 * The console may be contended at resume, but we don't
1569 * want it to block on it.
1570 */
1571 struct work_struct console_resume_work;
1572
1573 struct drm_property *broadcast_rgb_property;
1574 struct drm_property *force_audio_property;
1575
1576 uint32_t hw_context_size;
1577 struct list_head context_list;
1578
1579 u32 fdi_rx_config;
1580
1581 u32 suspend_count;
1582 struct i915_suspend_saved_registers regfile;
1583
1584 struct {
1585 /*
1586 * Raw watermark latency values:
1587 * in 0.1us units for WM0,
1588 * in 0.5us units for WM1+.
1589 */
1590 /* primary */
1591 uint16_t pri_latency[5];
1592 /* sprite */
1593 uint16_t spr_latency[5];
1594 /* cursor */
1595 uint16_t cur_latency[5];
1596
1597 /* current hardware state */
1598 struct ilk_wm_values hw;
1599 } wm;
1600
1601 struct i915_runtime_pm pm;
1602
1603 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1604 * here! */
1605 struct i915_dri1_state dri1;
1606 /* Old ums support infrastructure, same warning applies. */
1607 struct i915_ums_state ums;
1608} drm_i915_private_t;
1609
1610static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1611{
1612 return dev->dev_private;
1613}
1614
1615/* Iterate over initialised rings */
1616#define for_each_ring(ring__, dev_priv__, i__) \
1617 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1618 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1619
1620enum hdmi_force_audio {
1621 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1622 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1623 HDMI_AUDIO_AUTO, /* trust EDID */
1624 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1625};
1626
1627#define I915_GTT_OFFSET_NONE ((u32)-1)
1628
1629struct drm_i915_gem_object_ops {
1630 /* Interface between the GEM object and its backing storage.
1631 * get_pages() is called once prior to the use of the associated set
1632 * of pages before to binding them into the GTT, and put_pages() is
1633 * called after we no longer need them. As we expect there to be
1634 * associated cost with migrating pages between the backing storage
1635 * and making them available for the GPU (e.g. clflush), we may hold
1636 * onto the pages after they are no longer referenced by the GPU
1637 * in case they may be used again shortly (for example migrating the
1638 * pages to a different memory domain within the GTT). put_pages()
1639 * will therefore most likely be called when the object itself is
1640 * being released or under memory pressure (where we attempt to
1641 * reap pages for the shrinker).
1642 */
1643 int (*get_pages)(struct drm_i915_gem_object *);
1644 void (*put_pages)(struct drm_i915_gem_object *);
1645};
1646
1647struct drm_i915_gem_object {
1648 struct drm_gem_object base;
1649
1650 const struct drm_i915_gem_object_ops *ops;
1651
1652 /** List of VMAs backed by this object */
1653 struct list_head vma_list;
1654
1655 /** Stolen memory for this object, instead of being backed by shmem. */
1656 struct drm_mm_node *stolen;
1657 struct list_head global_list;
1658
1659 struct list_head ring_list;
1660 /** Used in execbuf to temporarily hold a ref */
1661 struct list_head obj_exec_link;
1662
1663 /**
1664 * This is set if the object is on the active lists (has pending
1665 * rendering and so a non-zero seqno), and is not set if it i s on
1666 * inactive (ready to be unbound) list.
1667 */
1668 unsigned int active:1;
1669
1670 /**
1671 * This is set if the object has been written to since last bound
1672 * to the GTT
1673 */
1674 unsigned int dirty:1;
1675
1676 /**
1677 * Fence register bits (if any) for this object. Will be set
1678 * as needed when mapped into the GTT.
1679 * Protected by dev->struct_mutex.
1680 */
1681 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1682
1683 /**
1684 * Advice: are the backing pages purgeable?
1685 */
1686 unsigned int madv:2;
1687
1688 /**
1689 * Current tiling mode for the object.
1690 */
1691 unsigned int tiling_mode:2;
1692 /**
1693 * Whether the tiling parameters for the currently associated fence
1694 * register have changed. Note that for the purposes of tracking
1695 * tiling changes we also treat the unfenced register, the register
1696 * slot that the object occupies whilst it executes a fenced
1697 * command (such as BLT on gen2/3), as a "fence".
1698 */
1699 unsigned int fence_dirty:1;
1700
1701 /**
1702 * Is the object at the current location in the gtt mappable and
1703 * fenceable? Used to avoid costly recalculations.
1704 */
1705 unsigned int map_and_fenceable:1;
1706
1707 /**
1708 * Whether the current gtt mapping needs to be mappable (and isn't just
1709 * mappable by accident). Track pin and fault separate for a more
1710 * accurate mappable working set.
1711 */
1712 unsigned int fault_mappable:1;
1713 unsigned int pin_mappable:1;
1714 unsigned int pin_display:1;
1715
1716 /*
1717 * Is the GPU currently using a fence to access this buffer,
1718 */
1719 unsigned int pending_fenced_gpu_access:1;
1720 unsigned int fenced_gpu_access:1;
1721
1722 unsigned int cache_level:3;
1723
1724 unsigned int has_aliasing_ppgtt_mapping:1;
1725 unsigned int has_global_gtt_mapping:1;
1726 unsigned int has_dma_mapping:1;
1727
1728 struct sg_table *pages;
1729 int pages_pin_count;
1730
1731 /* prime dma-buf support */
1732 void *dma_buf_vmapping;
1733 int vmapping_count;
1734
1735 struct intel_ring_buffer *ring;
1736
1737 /** Breadcrumb of last rendering to the buffer. */
1738 uint32_t last_read_seqno;
1739 uint32_t last_write_seqno;
1740 /** Breadcrumb of last fenced GPU access to the buffer. */
1741 uint32_t last_fenced_seqno;
1742
1743 /** Current tiling stride for the object, if it's tiled. */
1744 uint32_t stride;
1745
1746 /** References from framebuffers, locks out tiling changes. */
1747 unsigned long framebuffer_references;
1748
1749 /** Record of address bit 17 of each page at last unbind. */
1750 unsigned long *bit_17;
1751
1752 /** User space pin count and filp owning the pin */
1753 unsigned long user_pin_count;
1754 struct drm_file *pin_filp;
1755
1756 /** for phy allocated objects */
1757 drm_dma_handle_t *phys_handle;
1758};
1759
1760#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1761
1762/**
1763 * Request queue structure.
1764 *
1765 * The request queue allows us to note sequence numbers that have been emitted
1766 * and may be associated with active buffers to be retired.
1767 *
1768 * By keeping this list, we can avoid having to do questionable
1769 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1770 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1771 */
1772struct drm_i915_gem_request {
1773 /** On Which ring this request was generated */
1774 struct intel_ring_buffer *ring;
1775
1776 /** GEM sequence number associated with this request. */
1777 uint32_t seqno;
1778
1779 /** Position in the ringbuffer of the start of the request */
1780 u32 head;
1781
1782 /** Position in the ringbuffer of the end of the request */
1783 u32 tail;
1784
1785 /** Context related to this request */
1786 struct i915_hw_context *ctx;
1787
1788 /** Batch buffer related to this request if any */
1789 struct drm_i915_gem_object *batch_obj;
1790
1791 /** Time at which this request was emitted, in jiffies. */
1792 unsigned long emitted_jiffies;
1793
1794 /** global list entry for this request */
1795 struct list_head list;
1796
1797 struct drm_i915_file_private *file_priv;
1798 /** file_priv list entry for this request */
1799 struct list_head client_list;
1800};
1801
1802struct drm_i915_file_private {
1803 struct drm_i915_private *dev_priv;
1804 struct drm_file *file;
1805
1806 struct {
1807 spinlock_t lock;
1808 struct list_head request_list;
1809 struct delayed_work idle_work;
1810 } mm;
1811 struct idr context_idr;
1812
1813 struct i915_hw_context *private_default_ctx;
1814 atomic_t rps_wait_boost;
1815};
1816
1817/*
1818 * A command that requires special handling by the command parser.
1819 */
1820struct drm_i915_cmd_descriptor {
1821 /*
1822 * Flags describing how the command parser processes the command.
1823 *
1824 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1825 * a length mask if not set
1826 * CMD_DESC_SKIP: The command is allowed but does not follow the
1827 * standard length encoding for the opcode range in
1828 * which it falls
1829 * CMD_DESC_REJECT: The command is never allowed
1830 * CMD_DESC_REGISTER: The command should be checked against the
1831 * register whitelist for the appropriate ring
1832 * CMD_DESC_MASTER: The command is allowed if the submitting process
1833 * is the DRM master
1834 */
1835 u32 flags;
1836#define CMD_DESC_FIXED (1<<0)
1837#define CMD_DESC_SKIP (1<<1)
1838#define CMD_DESC_REJECT (1<<2)
1839#define CMD_DESC_REGISTER (1<<3)
1840#define CMD_DESC_BITMASK (1<<4)
1841#define CMD_DESC_MASTER (1<<5)
1842
1843 /*
1844 * The command's unique identification bits and the bitmask to get them.
1845 * This isn't strictly the opcode field as defined in the spec and may
1846 * also include type, subtype, and/or subop fields.
1847 */
1848 struct {
1849 u32 value;
1850 u32 mask;
1851 } cmd;
1852
1853 /*
1854 * The command's length. The command is either fixed length (i.e. does
1855 * not include a length field) or has a length field mask. The flag
1856 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
1857 * a length mask. All command entries in a command table must include
1858 * length information.
1859 */
1860 union {
1861 u32 fixed;
1862 u32 mask;
1863 } length;
1864
1865 /*
1866 * Describes where to find a register address in the command to check
1867 * against the ring's register whitelist. Only valid if flags has the
1868 * CMD_DESC_REGISTER bit set.
1869 */
1870 struct {
1871 u32 offset;
1872 u32 mask;
1873 } reg;
1874
1875#define MAX_CMD_DESC_BITMASKS 3
1876 /*
1877 * Describes command checks where a particular dword is masked and
1878 * compared against an expected value. If the command does not match
1879 * the expected value, the parser rejects it. Only valid if flags has
1880 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
1881 * are valid.
1882 */
1883 struct {
1884 u32 offset;
1885 u32 mask;
1886 u32 expected;
1887 } bits[MAX_CMD_DESC_BITMASKS];
1888};
1889
1890/*
1891 * A table of commands requiring special handling by the command parser.
1892 *
1893 * Each ring has an array of tables. Each table consists of an array of command
1894 * descriptors, which must be sorted with command opcodes in ascending order.
1895 */
1896struct drm_i915_cmd_table {
1897 const struct drm_i915_cmd_descriptor *table;
1898 int count;
1899};
1900
1901#define INTEL_INFO(dev) (&to_i915(dev)->info)
1902
1903#define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1904#define IS_845G(dev) ((dev)->pdev->device == 0x2562)
1905#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1906#define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
1907#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1908#define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1909#define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
1910#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1911#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1912#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1913#define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
1914#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1915#define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1916#define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
1917#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1918#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1919#define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
1920#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1921#define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1922 (dev)->pdev->device == 0x0152 || \
1923 (dev)->pdev->device == 0x015a)
1924#define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1925 (dev)->pdev->device == 0x0106 || \
1926 (dev)->pdev->device == 0x010A)
1927#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1928#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1929#define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8)
1930#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1931#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1932 ((dev)->pdev->device & 0xFF00) == 0x0C00)
1933#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
1934 (((dev)->pdev->device & 0xf) == 0x2 || \
1935 ((dev)->pdev->device & 0xf) == 0x6 || \
1936 ((dev)->pdev->device & 0xf) == 0xe))
1937#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
1938 ((dev)->pdev->device & 0xFF00) == 0x0A00)
1939#define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
1940#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1941 ((dev)->pdev->device & 0x00F0) == 0x0020)
1942/* ULX machines are also considered ULT. */
1943#define IS_HSW_ULX(dev) ((dev)->pdev->device == 0x0A0E || \
1944 (dev)->pdev->device == 0x0A1E)
1945#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1946
1947/*
1948 * The genX designation typically refers to the render engine, so render
1949 * capability related checks should use IS_GEN, while display and other checks
1950 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1951 * chips, etc.).
1952 */
1953#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1954#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1955#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1956#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1957#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1958#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1959#define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
1960
1961#define RENDER_RING (1<<RCS)
1962#define BSD_RING (1<<VCS)
1963#define BLT_RING (1<<BCS)
1964#define VEBOX_RING (1<<VECS)
1965#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
1966#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
1967#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
1968#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1969#define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
1970#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1971
1972#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1973#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev))
1974#define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) \
1975 && !IS_BROADWELL(dev))
1976#define USES_PPGTT(dev) intel_enable_ppgtt(dev, false)
1977#define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true)
1978
1979#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1980#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1981
1982/* Early gen2 have a totally busted CS tlb and require pinned batches. */
1983#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1984/*
1985 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
1986 * even when in MSI mode. This results in spurious interrupt warnings if the
1987 * legacy irq no. is shared with another device. The kernel then disables that
1988 * interrupt source and so prevents the other device from working properly.
1989 */
1990#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
1991#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
1992
1993/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1994 * rows, which changed the alignment requirements and fence programming.
1995 */
1996#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1997 IS_I915GM(dev)))
1998#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1999#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2000#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2001#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2002#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2003
2004#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2005#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2006#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2007
2008#define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
2009
2010#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2011#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2012#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
2013#define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */
2014#define HAS_RUNTIME_PM(dev) (IS_HASWELL(dev))
2015
2016#define INTEL_PCH_DEVICE_ID_MASK 0xff00
2017#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2018#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2019#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2020#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2021#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2022
2023#define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
2024#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2025#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2026#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2027#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2028#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2029
2030/* DPF == dynamic parity feature */
2031#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2032#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2033
2034#define GT_FREQUENCY_MULTIPLIER 50
2035
2036#include "i915_trace.h"
2037
2038extern const struct drm_ioctl_desc i915_ioctls[];
2039extern int i915_max_ioctl;
2040
2041extern int i915_suspend(struct drm_device *dev, pm_message_t state);
2042extern int i915_resume(struct drm_device *dev);
2043extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
2044extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
2045
2046/* i915_params.c */
2047struct i915_params {
2048 int modeset;
2049 int panel_ignore_lid;
2050 unsigned int powersave;
2051 int semaphores;
2052 unsigned int lvds_downclock;
2053 int lvds_channel_mode;
2054 int panel_use_ssc;
2055 int vbt_sdvo_panel_type;
2056 int enable_rc6;
2057 int enable_fbc;
2058 int enable_ppgtt;
2059 int enable_psr;
2060 unsigned int preliminary_hw_support;
2061 int disable_power_well;
2062 int enable_ips;
2063 int invert_brightness;
2064 int enable_cmd_parser;
2065 /* leave bools at the end to not create holes */
2066 bool enable_hangcheck;
2067 bool fastboot;
2068 bool prefault_disable;
2069 bool reset;
2070 bool disable_display;
2071};
2072extern struct i915_params i915 __read_mostly;
2073
2074 /* i915_dma.c */
2075void i915_update_dri1_breadcrumb(struct drm_device *dev);
2076extern void i915_kernel_lost_context(struct drm_device * dev);
2077extern int i915_driver_load(struct drm_device *, unsigned long flags);
2078extern int i915_driver_unload(struct drm_device *);
2079extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
2080extern void i915_driver_lastclose(struct drm_device * dev);
2081extern void i915_driver_preclose(struct drm_device *dev,
2082 struct drm_file *file_priv);
2083extern void i915_driver_postclose(struct drm_device *dev,
2084 struct drm_file *file_priv);
2085extern int i915_driver_device_is_agp(struct drm_device * dev);
2086#ifdef CONFIG_COMPAT
2087extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2088 unsigned long arg);
2089#endif
2090extern int i915_emit_box(struct drm_device *dev,
2091 struct drm_clip_rect *box,
2092 int DR1, int DR4);
2093extern int intel_gpu_reset(struct drm_device *dev);
2094extern int i915_reset(struct drm_device *dev);
2095extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2096extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2097extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2098extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2099
2100extern void intel_console_resume(struct work_struct *work);
2101
2102/* i915_irq.c */
2103void i915_queue_hangcheck(struct drm_device *dev);
2104__printf(3, 4)
2105void i915_handle_error(struct drm_device *dev, bool wedged,
2106 const char *fmt, ...);
2107
2108void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir,
2109 int new_delay);
2110extern void intel_irq_init(struct drm_device *dev);
2111extern void intel_hpd_init(struct drm_device *dev);
2112
2113extern void intel_uncore_sanitize(struct drm_device *dev);
2114extern void intel_uncore_early_sanitize(struct drm_device *dev);
2115extern void intel_uncore_init(struct drm_device *dev);
2116extern void intel_uncore_check_errors(struct drm_device *dev);
2117extern void intel_uncore_fini(struct drm_device *dev);
2118
2119void
2120i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2121 u32 status_mask);
2122
2123void
2124i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2125 u32 status_mask);
2126
2127void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2128void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2129
2130/* i915_gem.c */
2131int i915_gem_init_ioctl(struct drm_device *dev, void *data,
2132 struct drm_file *file_priv);
2133int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2134 struct drm_file *file_priv);
2135int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2136 struct drm_file *file_priv);
2137int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2138 struct drm_file *file_priv);
2139int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2140 struct drm_file *file_priv);
2141int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2142 struct drm_file *file_priv);
2143int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2144 struct drm_file *file_priv);
2145int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2146 struct drm_file *file_priv);
2147int i915_gem_execbuffer(struct drm_device *dev, void *data,
2148 struct drm_file *file_priv);
2149int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2150 struct drm_file *file_priv);
2151int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2152 struct drm_file *file_priv);
2153int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2154 struct drm_file *file_priv);
2155int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2156 struct drm_file *file_priv);
2157int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2158 struct drm_file *file);
2159int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2160 struct drm_file *file);
2161int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2162 struct drm_file *file_priv);
2163int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2164 struct drm_file *file_priv);
2165int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2166 struct drm_file *file_priv);
2167int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2168 struct drm_file *file_priv);
2169int i915_gem_set_tiling(struct drm_device *dev, void *data,
2170 struct drm_file *file_priv);
2171int i915_gem_get_tiling(struct drm_device *dev, void *data,
2172 struct drm_file *file_priv);
2173int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2174 struct drm_file *file_priv);
2175int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2176 struct drm_file *file_priv);
2177void i915_gem_load(struct drm_device *dev);
2178void *i915_gem_object_alloc(struct drm_device *dev);
2179void i915_gem_object_free(struct drm_i915_gem_object *obj);
2180void i915_gem_object_init(struct drm_i915_gem_object *obj,
2181 const struct drm_i915_gem_object_ops *ops);
2182struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2183 size_t size);
2184void i915_init_vm(struct drm_i915_private *dev_priv,
2185 struct i915_address_space *vm);
2186void i915_gem_free_object(struct drm_gem_object *obj);
2187void i915_gem_vma_destroy(struct i915_vma *vma);
2188
2189#define PIN_MAPPABLE 0x1
2190#define PIN_NONBLOCK 0x2
2191#define PIN_GLOBAL 0x4
2192#define PIN_OFFSET_BIAS 0x8
2193#define PIN_OFFSET_MASK (~4095)
2194int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
2195 struct i915_address_space *vm,
2196 uint32_t alignment,
2197 uint64_t flags);
2198int __must_check i915_vma_unbind(struct i915_vma *vma);
2199int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2200void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2201void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2202void i915_gem_lastclose(struct drm_device *dev);
2203
2204int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2205 int *needs_clflush);
2206
2207int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2208static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2209{
2210 struct sg_page_iter sg_iter;
2211
2212 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2213 return sg_page_iter_page(&sg_iter);
2214
2215 return NULL;
2216}
2217static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2218{
2219 BUG_ON(obj->pages == NULL);
2220 obj->pages_pin_count++;
2221}
2222static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2223{
2224 BUG_ON(obj->pages_pin_count == 0);
2225 obj->pages_pin_count--;
2226}
2227
2228int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2229int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2230 struct intel_ring_buffer *to);
2231void i915_vma_move_to_active(struct i915_vma *vma,
2232 struct intel_ring_buffer *ring);
2233int i915_gem_dumb_create(struct drm_file *file_priv,
2234 struct drm_device *dev,
2235 struct drm_mode_create_dumb *args);
2236int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2237 uint32_t handle, uint64_t *offset);
2238/**
2239 * Returns true if seq1 is later than seq2.
2240 */
2241static inline bool
2242i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2243{
2244 return (int32_t)(seq1 - seq2) >= 0;
2245}
2246
2247int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2248int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2249int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2250int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2251
2252static inline bool
2253i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
2254{
2255 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2256 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2257 dev_priv->fence_regs[obj->fence_reg].pin_count++;
2258 return true;
2259 } else
2260 return false;
2261}
2262
2263static inline void
2264i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
2265{
2266 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2267 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2268 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
2269 dev_priv->fence_regs[obj->fence_reg].pin_count--;
2270 }
2271}
2272
2273struct drm_i915_gem_request *
2274i915_gem_find_active_request(struct intel_ring_buffer *ring);
2275
2276bool i915_gem_retire_requests(struct drm_device *dev);
2277int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2278 bool interruptible);
2279static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2280{
2281 return unlikely(atomic_read(&error->reset_counter)
2282 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2283}
2284
2285static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2286{
2287 return atomic_read(&error->reset_counter) & I915_WEDGED;
2288}
2289
2290static inline u32 i915_reset_count(struct i915_gpu_error *error)
2291{
2292 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2293}
2294
2295void i915_gem_reset(struct drm_device *dev);
2296bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2297int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2298int __must_check i915_gem_init(struct drm_device *dev);
2299int __must_check i915_gem_init_hw(struct drm_device *dev);
2300int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice);
2301void i915_gem_init_swizzling(struct drm_device *dev);
2302void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2303int __must_check i915_gpu_idle(struct drm_device *dev);
2304int __must_check i915_gem_suspend(struct drm_device *dev);
2305int __i915_add_request(struct intel_ring_buffer *ring,
2306 struct drm_file *file,
2307 struct drm_i915_gem_object *batch_obj,
2308 u32 *seqno);
2309#define i915_add_request(ring, seqno) \
2310 __i915_add_request(ring, NULL, NULL, seqno)
2311int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
2312 uint32_t seqno);
2313int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2314int __must_check
2315i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2316 bool write);
2317int __must_check
2318i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2319int __must_check
2320i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2321 u32 alignment,
2322 struct intel_ring_buffer *pipelined);
2323void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2324int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2325 int align);
2326int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2327void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2328
2329uint32_t
2330i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2331uint32_t
2332i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2333 int tiling_mode, bool fenced);
2334
2335int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2336 enum i915_cache_level cache_level);
2337
2338struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2339 struct dma_buf *dma_buf);
2340
2341struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2342 struct drm_gem_object *gem_obj, int flags);
2343
2344void i915_gem_restore_fences(struct drm_device *dev);
2345
2346unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2347 struct i915_address_space *vm);
2348bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2349bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2350 struct i915_address_space *vm);
2351unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2352 struct i915_address_space *vm);
2353struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2354 struct i915_address_space *vm);
2355struct i915_vma *
2356i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2357 struct i915_address_space *vm);
2358
2359struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2360static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2361 struct i915_vma *vma;
2362 list_for_each_entry(vma, &obj->vma_list, vma_link)
2363 if (vma->pin_count > 0)
2364 return true;
2365 return false;
2366}
2367
2368/* Some GGTT VM helpers */
2369#define obj_to_ggtt(obj) \
2370 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2371static inline bool i915_is_ggtt(struct i915_address_space *vm)
2372{
2373 struct i915_address_space *ggtt =
2374 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2375 return vm == ggtt;
2376}
2377
2378static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2379{
2380 return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
2381}
2382
2383static inline unsigned long
2384i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2385{
2386 return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
2387}
2388
2389static inline unsigned long
2390i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2391{
2392 return i915_gem_obj_size(obj, obj_to_ggtt(obj));
2393}
2394
2395static inline int __must_check
2396i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2397 uint32_t alignment,
2398 unsigned flags)
2399{
2400 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL);
2401}
2402
2403static inline int
2404i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2405{
2406 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2407}
2408
2409void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2410
2411/* i915_gem_context.c */
2412#define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)
2413int __must_check i915_gem_context_init(struct drm_device *dev);
2414void i915_gem_context_fini(struct drm_device *dev);
2415void i915_gem_context_reset(struct drm_device *dev);
2416int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2417int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2418void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2419int i915_switch_context(struct intel_ring_buffer *ring,
2420 struct i915_hw_context *to);
2421struct i915_hw_context *
2422i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2423void i915_gem_context_free(struct kref *ctx_ref);
2424static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
2425{
2426 kref_get(&ctx->ref);
2427}
2428
2429static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
2430{
2431 kref_put(&ctx->ref, i915_gem_context_free);
2432}
2433
2434static inline bool i915_gem_context_is_default(const struct i915_hw_context *c)
2435{
2436 return c->id == DEFAULT_CONTEXT_ID;
2437}
2438
2439int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2440 struct drm_file *file);
2441int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2442 struct drm_file *file);
2443
2444/* i915_gem_evict.c */
2445int __must_check i915_gem_evict_something(struct drm_device *dev,
2446 struct i915_address_space *vm,
2447 int min_size,
2448 unsigned alignment,
2449 unsigned cache_level,
2450 unsigned long start,
2451 unsigned long end,
2452 unsigned flags);
2453int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2454int i915_gem_evict_everything(struct drm_device *dev);
2455
2456/* i915_gem_gtt.c */
2457void i915_check_and_clear_faults(struct drm_device *dev);
2458void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
2459void i915_gem_restore_gtt_mappings(struct drm_device *dev);
2460int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
2461void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
2462void i915_gem_init_global_gtt(struct drm_device *dev);
2463void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
2464 unsigned long mappable_end, unsigned long end);
2465int i915_gem_gtt_init(struct drm_device *dev);
2466static inline void i915_gem_chipset_flush(struct drm_device *dev)
2467{
2468 if (INTEL_INFO(dev)->gen < 6)
2469 intel_gtt_chipset_flush();
2470}
2471int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt);
2472bool intel_enable_ppgtt(struct drm_device *dev, bool full);
2473
2474/* i915_gem_stolen.c */
2475int i915_gem_init_stolen(struct drm_device *dev);
2476int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
2477void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2478void i915_gem_cleanup_stolen(struct drm_device *dev);
2479struct drm_i915_gem_object *
2480i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2481struct drm_i915_gem_object *
2482i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2483 u32 stolen_offset,
2484 u32 gtt_offset,
2485 u32 size);
2486void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
2487
2488/* i915_gem_tiling.c */
2489static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2490{
2491 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2492
2493 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2494 obj->tiling_mode != I915_TILING_NONE;
2495}
2496
2497void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2498void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2499void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2500
2501/* i915_gem_debug.c */
2502#if WATCH_LISTS
2503int i915_verify_lists(struct drm_device *dev);
2504#else
2505#define i915_verify_lists(dev) 0
2506#endif
2507
2508/* i915_debugfs.c */
2509int i915_debugfs_init(struct drm_minor *minor);
2510void i915_debugfs_cleanup(struct drm_minor *minor);
2511#ifdef CONFIG_DEBUG_FS
2512void intel_display_crc_init(struct drm_device *dev);
2513#else
2514static inline void intel_display_crc_init(struct drm_device *dev) {}
2515#endif
2516
2517/* i915_gpu_error.c */
2518__printf(2, 3)
2519void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2520int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2521 const struct i915_error_state_file_priv *error);
2522int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2523 size_t count, loff_t pos);
2524static inline void i915_error_state_buf_release(
2525 struct drm_i915_error_state_buf *eb)
2526{
2527 kfree(eb->buf);
2528}
2529void i915_capture_error_state(struct drm_device *dev, bool wedge,
2530 const char *error_msg);
2531void i915_error_state_get(struct drm_device *dev,
2532 struct i915_error_state_file_priv *error_priv);
2533void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2534void i915_destroy_error_state(struct drm_device *dev);
2535
2536void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2537const char *i915_cache_level_str(int type);
2538
2539/* i915_cmd_parser.c */
2540void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring);
2541bool i915_needs_cmd_parser(struct intel_ring_buffer *ring);
2542int i915_parse_cmds(struct intel_ring_buffer *ring,
2543 struct drm_i915_gem_object *batch_obj,
2544 u32 batch_start_offset,
2545 bool is_master);
2546
2547/* i915_suspend.c */
2548extern int i915_save_state(struct drm_device *dev);
2549extern int i915_restore_state(struct drm_device *dev);
2550
2551/* i915_ums.c */
2552void i915_save_display_reg(struct drm_device *dev);
2553void i915_restore_display_reg(struct drm_device *dev);
2554
2555/* i915_sysfs.c */
2556void i915_setup_sysfs(struct drm_device *dev_priv);
2557void i915_teardown_sysfs(struct drm_device *dev_priv);
2558
2559/* intel_i2c.c */
2560extern int intel_setup_gmbus(struct drm_device *dev);
2561extern void intel_teardown_gmbus(struct drm_device *dev);
2562static inline bool intel_gmbus_is_port_valid(unsigned port)
2563{
2564 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2565}
2566
2567extern struct i2c_adapter *intel_gmbus_get_adapter(
2568 struct drm_i915_private *dev_priv, unsigned port);
2569extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2570extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2571static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2572{
2573 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2574}
2575extern void intel_i2c_reset(struct drm_device *dev);
2576
2577/* intel_opregion.c */
2578struct intel_encoder;
2579#ifdef CONFIG_ACPI
2580extern int intel_opregion_setup(struct drm_device *dev);
2581extern void intel_opregion_init(struct drm_device *dev);
2582extern void intel_opregion_fini(struct drm_device *dev);
2583extern void intel_opregion_asle_intr(struct drm_device *dev);
2584extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2585 bool enable);
2586extern int intel_opregion_notify_adapter(struct drm_device *dev,
2587 pci_power_t state);
2588#else
2589static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
2590static inline void intel_opregion_init(struct drm_device *dev) { return; }
2591static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2592static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2593static inline int
2594intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2595{
2596 return 0;
2597}
2598static inline int
2599intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2600{
2601 return 0;
2602}
2603#endif
2604
2605/* intel_acpi.c */
2606#ifdef CONFIG_ACPI
2607extern void intel_register_dsm_handler(void);
2608extern void intel_unregister_dsm_handler(void);
2609#else
2610static inline void intel_register_dsm_handler(void) { return; }
2611static inline void intel_unregister_dsm_handler(void) { return; }
2612#endif /* CONFIG_ACPI */
2613
2614/* modesetting */
2615extern void intel_modeset_init_hw(struct drm_device *dev);
2616extern void intel_modeset_suspend_hw(struct drm_device *dev);
2617extern void intel_modeset_init(struct drm_device *dev);
2618extern void intel_modeset_gem_init(struct drm_device *dev);
2619extern void intel_modeset_cleanup(struct drm_device *dev);
2620extern void intel_connector_unregister(struct intel_connector *);
2621extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2622extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2623 bool force_restore);
2624extern void i915_redisable_vga(struct drm_device *dev);
2625extern void i915_redisable_vga_power_on(struct drm_device *dev);
2626extern bool intel_fbc_enabled(struct drm_device *dev);
2627extern void intel_disable_fbc(struct drm_device *dev);
2628extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2629extern void intel_init_pch_refclk(struct drm_device *dev);
2630extern void gen6_set_rps(struct drm_device *dev, u8 val);
2631extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2632extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2633extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
2634extern void intel_detect_pch(struct drm_device *dev);
2635extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2636extern int intel_enable_rc6(const struct drm_device *dev);
2637
2638extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2639int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2640 struct drm_file *file);
2641int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2642 struct drm_file *file);
2643
2644/* overlay */
2645extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2646extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2647 struct intel_overlay_error_state *error);
2648
2649extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2650extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2651 struct drm_device *dev,
2652 struct intel_display_error_state *error);
2653
2654/* On SNB platform, before reading ring registers forcewake bit
2655 * must be set to prevent GT core from power down and stale values being
2656 * returned.
2657 */
2658void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2659void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2660void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
2661
2662int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2663int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2664
2665/* intel_sideband.c */
2666u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2667void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2668u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2669u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2670void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2671u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2672void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2673u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2674void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2675u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2676void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2677u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2678void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2679u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2680void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2681u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2682 enum intel_sbi_destination destination);
2683void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2684 enum intel_sbi_destination destination);
2685u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
2686void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2687
2688int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2689int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
2690
2691void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2692void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2693
2694#define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
2695 (((reg) >= 0x2000 && (reg) < 0x4000) ||\
2696 ((reg) >= 0x5000 && (reg) < 0x8000) ||\
2697 ((reg) >= 0xB000 && (reg) < 0x12000) ||\
2698 ((reg) >= 0x2E000 && (reg) < 0x30000))
2699
2700#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\
2701 (((reg) >= 0x12000 && (reg) < 0x14000) ||\
2702 ((reg) >= 0x22000 && (reg) < 0x24000) ||\
2703 ((reg) >= 0x30000 && (reg) < 0x40000))
2704
2705#define FORCEWAKE_RENDER (1 << 0)
2706#define FORCEWAKE_MEDIA (1 << 1)
2707#define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2708
2709
2710#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2711#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2712
2713#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2714#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2715#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2716#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2717
2718#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2719#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2720#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2721#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2722
2723/* Be very careful with read/write 64-bit values. On 32-bit machines, they
2724 * will be implemented using 2 32-bit writes in an arbitrary order with
2725 * an arbitrary delay between them. This can cause the hardware to
2726 * act upon the intermediate value, possibly leading to corruption and
2727 * machine death. You have been warned.
2728 */
2729#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2730#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2731
2732#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
2733 u32 upper = I915_READ(upper_reg); \
2734 u32 lower = I915_READ(lower_reg); \
2735 u32 tmp = I915_READ(upper_reg); \
2736 if (upper != tmp) { \
2737 upper = tmp; \
2738 lower = I915_READ(lower_reg); \
2739 WARN_ON(I915_READ(upper_reg) != upper); \
2740 } \
2741 (u64)upper << 32 | lower; })
2742
2743#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2744#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2745
2746/* "Broadcast RGB" property */
2747#define INTEL_BROADCAST_RGB_AUTO 0
2748#define INTEL_BROADCAST_RGB_FULL 1
2749#define INTEL_BROADCAST_RGB_LIMITED 2
2750
2751static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2752{
2753 if (HAS_PCH_SPLIT(dev))
2754 return CPU_VGACNTRL;
2755 else if (IS_VALLEYVIEW(dev))
2756 return VLV_VGACNTRL;
2757 else
2758 return VGACNTRL;
2759}
2760
2761static inline void __user *to_user_ptr(u64 address)
2762{
2763 return (void __user *)(uintptr_t)address;
2764}
2765
2766static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2767{
2768 unsigned long j = msecs_to_jiffies(m);
2769
2770 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2771}
2772
2773static inline unsigned long
2774timespec_to_jiffies_timeout(const struct timespec *value)
2775{
2776 unsigned long j = timespec_to_jiffies(value);
2777
2778 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2779}
2780
2781/*
2782 * If you need to wait X milliseconds between events A and B, but event B
2783 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2784 * when event A happened, then just before event B you call this function and
2785 * pass the timestamp as the first argument, and X as the second argument.
2786 */
2787static inline void
2788wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
2789{
2790 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
2791
2792 /*
2793 * Don't re-read the value of "jiffies" every time since it may change
2794 * behind our back and break the math.
2795 */
2796 tmp_jiffies = jiffies;
2797 target_jiffies = timestamp_jiffies +
2798 msecs_to_jiffies_timeout(to_wait_ms);
2799
2800 if (time_after(target_jiffies, tmp_jiffies)) {
2801 remaining_jiffies = target_jiffies - tmp_jiffies;
2802 while (remaining_jiffies)
2803 remaining_jiffies =
2804 schedule_timeout_uninterruptible(remaining_jiffies);
2805 }
2806}
2807
2808#endif