1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * xHCI host controller driver PCI Bus Glue.
  4 *
  5 * Copyright (C) 2008 Intel Corp.
  6 *
  7 * Author: Sarah Sharp
  8 * Some code borrowed from the Linux EHCI driver.
  9 */
 10
 11#include <linux/pci.h>
 12#include <linux/slab.h>
 13#include <linux/module.h>
 14#include <linux/acpi.h>
 15#include <linux/reset.h>
 16#include <linux/suspend.h>
 17
 18#include "xhci.h"
 19#include "xhci-trace.h"
 20#include "xhci-pci.h"
 21
 22#define SSIC_PORT_NUM		2
 23#define SSIC_PORT_CFG2		0x880c
 24#define SSIC_PORT_CFG2_OFFSET	0x30
 25#define PROG_DONE		(1 << 30)
 26#define SSIC_PORT_UNUSED	(1 << 31)
 27#define SPARSE_DISABLE_BIT	17
 28#define SPARSE_CNTL_ENABLE	0xC12C
 29
 30/* Device for a quirk */
 31#define PCI_VENDOR_ID_FRESCO_LOGIC	0x1b73
 32#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK	0x1000
 33#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009	0x1009
 34#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100	0x1100
 35#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400	0x1400
 36
 37#define PCI_VENDOR_ID_ETRON		0x1b6f
 38#define PCI_DEVICE_ID_EJ168		0x7023
 39
 40#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI	0x8c31
 41#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI	0x9c31
 42#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI	0x9cb1
 43#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI		0x22b5
 44#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI		0xa12f
 45#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI	0x9d2f
 46#define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI		0x0aa8
 47#define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI		0x1aa8
 48#define PCI_DEVICE_ID_INTEL_APL_XHCI			0x5aa8
 49#define PCI_DEVICE_ID_INTEL_DNV_XHCI			0x19d0
 50#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI	0x15b5
 51#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI	0x15b6
 52#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI	0x15c1
 53#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI	0x15db
 54#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI	0x15d4
 55#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI		0x15e9
 56#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI		0x15ec
 57#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI		0x15f0
 58#define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI		0x8a13
 59#define PCI_DEVICE_ID_INTEL_CML_XHCI			0xa3af
 60#define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI		0x9a13
 61#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI		0x1138
 62#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI		0x51ed
 63#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI	0x54ed
 64
 65#define PCI_DEVICE_ID_AMD_RENOIR_XHCI			0x1639
 66#define PCI_DEVICE_ID_AMD_PROMONTORYA_4			0x43b9
 67#define PCI_DEVICE_ID_AMD_PROMONTORYA_3			0x43ba
 68#define PCI_DEVICE_ID_AMD_PROMONTORYA_2			0x43bb
 69#define PCI_DEVICE_ID_AMD_PROMONTORYA_1			0x43bc
 70
 71#define PCI_DEVICE_ID_ASMEDIA_1042_XHCI			0x1042
 72#define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI		0x1142
 73#define PCI_DEVICE_ID_ASMEDIA_1142_XHCI			0x1242
 74#define PCI_DEVICE_ID_ASMEDIA_2142_XHCI			0x2142
 75#define PCI_DEVICE_ID_ASMEDIA_3242_XHCI			0x3242
 76
 77static const char hcd_name[] = "xhci_hcd";
 78
 79static struct hc_driver __read_mostly xhci_pci_hc_driver;
 80
 81static int xhci_pci_setup(struct usb_hcd *hcd);
 82static int xhci_pci_run(struct usb_hcd *hcd);
 83static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
 84				      struct usb_tt *tt, gfp_t mem_flags);
 85
 86static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
 87	.reset = xhci_pci_setup,
 88	.start = xhci_pci_run,
 89	.update_hub_device = xhci_pci_update_hub_device,
 90};
 91
 92static void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
 93{
 94	struct usb_hcd *hcd = xhci_to_hcd(xhci);
 95
 96	if (hcd->msix_enabled) {
 97		struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
 98
 99		/* for now, the driver only supports one primary interrupter */
100		synchronize_irq(pci_irq_vector(pdev, 0));
101	}
102}
103
104/* Free any IRQs and disable MSI-X */
105static void xhci_cleanup_msix(struct xhci_hcd *xhci)
106{
107	struct usb_hcd *hcd = xhci_to_hcd(xhci);
108	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
109
110	/* return if using legacy interrupt */
111	if (hcd->irq > 0)
112		return;
113
114	free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
115	pci_free_irq_vectors(pdev);
116	hcd->msix_enabled = 0;
117}
118
119/* Try enabling MSI-X with MSI and legacy IRQ as fallback */
120static int xhci_try_enable_msi(struct usb_hcd *hcd)
121{
122	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
123	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
124	int ret;
125
126	/*
127	 * Some Fresco Logic host controllers advertise MSI, but fail to
128	 * generate interrupts.  Don't even try to enable MSI.
129	 */
130	if (xhci->quirks & XHCI_BROKEN_MSI)
131		goto legacy_irq;
132
133	/* unregister the legacy interrupt */
134	if (hcd->irq)
135		free_irq(hcd->irq, hcd);
136	hcd->irq = 0;
137
138	/*
139	 * calculate number of MSI-X vectors supported.
140	 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
141	 *   with max number of interrupters based on the xhci HCSPARAMS1.
142	 * - num_online_cpus: maximum MSI-X vectors per CPUs core.
143	 *   Add additional 1 vector to ensure always available interrupt.
144	 */
145	xhci->nvecs = min(num_online_cpus() + 1,
146			  HCS_MAX_INTRS(xhci->hcs_params1));
147
148	/* TODO: Check with MSI Soc for sysdev */
149	xhci->nvecs = pci_alloc_irq_vectors(pdev, 1, xhci->nvecs,
150					    PCI_IRQ_MSIX | PCI_IRQ_MSI);
151	if (xhci->nvecs < 0) {
152		xhci_dbg_trace(xhci, trace_xhci_dbg_init,
153			       "failed to allocate IRQ vectors");
154		goto legacy_irq;
155	}
156
157	ret = request_irq(pci_irq_vector(pdev, 0), xhci_msi_irq, 0, "xhci_hcd",
158			  xhci_to_hcd(xhci));
159	if (ret)
160		goto free_irq_vectors;
161
162	hcd->msi_enabled = 1;
163	hcd->msix_enabled = pdev->msix_enabled;
164	return 0;
165
166free_irq_vectors:
167	xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable %s interrupt",
168		       pdev->msix_enabled ? "MSI-X" : "MSI");
169	pci_free_irq_vectors(pdev);
170
171legacy_irq:
172	if (!pdev->irq) {
173		xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
174		return -EINVAL;
175	}
176
177	if (!strlen(hcd->irq_descr))
178		snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
179			 hcd->driver->description, hcd->self.busnum);
180
181	/* fall back to legacy interrupt */
182	ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, hcd->irq_descr, hcd);
183	if (ret) {
184		xhci_err(xhci, "request interrupt %d failed\n", pdev->irq);
185		return ret;
186	}
187	hcd->irq = pdev->irq;
188	return 0;
189}
190
191static int xhci_pci_run(struct usb_hcd *hcd)
192{
193	int ret;
194
195	if (usb_hcd_is_primary_hcd(hcd)) {
196		ret = xhci_try_enable_msi(hcd);
197		if (ret)
198			return ret;
199	}
200
201	return xhci_run(hcd);
202}
203
204static void xhci_pci_stop(struct usb_hcd *hcd)
205{
206	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
207
208	xhci_stop(hcd);
209
210	if (usb_hcd_is_primary_hcd(hcd))
211		xhci_cleanup_msix(xhci);
212}
213
214/* called after powerup, by probe or system-pm "wakeup" */
215static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
216{
217	/*
218	 * TODO: Implement finding debug ports later.
219	 * TODO: see if there are any quirks that need to be added to handle
220	 * new extended capabilities.
221	 */
222
223	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
224	if (!pci_set_mwi(pdev))
225		xhci_dbg(xhci, "MWI active\n");
226
227	xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
228	return 0;
229}
230
231static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
232{
233	struct pci_dev                  *pdev = to_pci_dev(dev);
234	struct xhci_driver_data         *driver_data;
235	const struct pci_device_id      *id;
236
237	id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev);
238
239	if (id && id->driver_data) {
240		driver_data = (struct xhci_driver_data *)id->driver_data;
241		xhci->quirks |= driver_data->quirks;
242	}
243
244	/* Look for vendor-specific quirks */
245	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
246			(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
247			 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
248		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
249				pdev->revision == 0x0) {
250			xhci->quirks |= XHCI_RESET_EP_QUIRK;
251			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
252				"XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated");
253		}
254		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
255				pdev->revision == 0x4) {
256			xhci->quirks |= XHCI_SLOW_SUSPEND;
257			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
258				"QUIRK: Fresco Logic xHC revision %u"
259				"must be suspended extra slowly",
260				pdev->revision);
261		}
262		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
263			xhci->quirks |= XHCI_BROKEN_STREAMS;
264		/* Fresco Logic confirms: all revisions of this chip do not
265		 * support MSI, even though some of them claim to in their PCI
266		 * capabilities.
267		 */
268		xhci->quirks |= XHCI_BROKEN_MSI;
269		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
270				"QUIRK: Fresco Logic revision %u "
271				"has broken MSI implementation",
272				pdev->revision);
273		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
274	}
275
276	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
277			pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
278		xhci->quirks |= XHCI_BROKEN_STREAMS;
279
280	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
281			pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100)
282		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
283
284	if (pdev->vendor == PCI_VENDOR_ID_NEC)
285		xhci->quirks |= XHCI_NEC_HOST;
286
287	if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
288		xhci->quirks |= XHCI_AMD_0x96_HOST;
289
290	/* AMD PLL quirk */
291	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
292		xhci->quirks |= XHCI_AMD_PLL_FIX;
293
294	if (pdev->vendor == PCI_VENDOR_ID_AMD &&
295		(pdev->device == 0x145c ||
296		 pdev->device == 0x15e0 ||
297		 pdev->device == 0x15e1 ||
298		 pdev->device == 0x43bb))
299		xhci->quirks |= XHCI_SUSPEND_DELAY;
300
301	if (pdev->vendor == PCI_VENDOR_ID_AMD &&
302	    (pdev->device == 0x15e0 || pdev->device == 0x15e1))
303		xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
304
305	if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
306		xhci->quirks |= XHCI_DISABLE_SPARSE;
307		xhci->quirks |= XHCI_RESET_ON_RESUME;
308	}
309
310	if (pdev->vendor == PCI_VENDOR_ID_AMD)
311		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 
 
 
312
313	if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
314		((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
315		(pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
316		(pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
317		(pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
318		xhci->quirks |= XHCI_U2_DISABLE_WAKE;
319
320	if (pdev->vendor == PCI_VENDOR_ID_AMD &&
321		pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI)
322		xhci->quirks |= XHCI_BROKEN_D3COLD_S2I;
323
324	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
325		xhci->quirks |= XHCI_LPM_SUPPORT;
326		xhci->quirks |= XHCI_INTEL_HOST;
327		xhci->quirks |= XHCI_AVOID_BEI;
328	}
329	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
330			pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
331		xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
332		xhci->limit_active_eps = 64;
333		xhci->quirks |= XHCI_SW_BW_CHECKING;
334		/*
335		 * PPT desktop boards DH77EB and DH77DF will power back on after
336		 * a few seconds of being shutdown.  The fix for this is to
337		 * switch the ports from xHCI to EHCI on shutdown.  We can't use
338		 * DMI information to find those particular boards (since each
339		 * vendor will change the board name), so we have to key off all
340		 * PPT chipsets.
341		 */
342		xhci->quirks |= XHCI_SPURIOUS_REBOOT;
343	}
344	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
345		(pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
346		 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
347		xhci->quirks |= XHCI_SPURIOUS_REBOOT;
348		xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
349	}
350	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
351		(pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
352		 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
353		 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
354		 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
355		 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
356		 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
357		 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
358		 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
359		xhci->quirks |= XHCI_PME_STUCK_QUIRK;
360	}
361	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
362	    pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
363		xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
364	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
365	    (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
366	     pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
367	     pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
368		xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
369	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
370	    (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
371	     pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
372	     pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
373	     pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
374	     pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
375		xhci->quirks |= XHCI_MISSING_CAS;
376
377	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
378	    (pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI ||
379	     pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI))
380		xhci->quirks |= XHCI_RESET_TO_DEFAULT;
381
382	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
383	    (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
384	     pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
385	     pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
386	     pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
387	     pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
388	     pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
389	     pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
390	     pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
391	     pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
392	     pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
393	     pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI))
394		xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
395
396	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
397			pdev->device == PCI_DEVICE_ID_EJ168) {
398		xhci->quirks |= XHCI_RESET_ON_RESUME;
399		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
400		xhci->quirks |= XHCI_BROKEN_STREAMS;
401	}
402	if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
403	    pdev->device == 0x0014) {
404		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
405		xhci->quirks |= XHCI_ZERO_64B_REGS;
406	}
407	if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
408	    pdev->device == 0x0015) {
409		xhci->quirks |= XHCI_RESET_ON_RESUME;
410		xhci->quirks |= XHCI_ZERO_64B_REGS;
411	}
412	if (pdev->vendor == PCI_VENDOR_ID_VIA)
413		xhci->quirks |= XHCI_RESET_ON_RESUME;
414
415	/* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
416	if (pdev->vendor == PCI_VENDOR_ID_VIA &&
417			pdev->device == 0x3432)
418		xhci->quirks |= XHCI_BROKEN_STREAMS;
419
420	if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483)
421		xhci->quirks |= XHCI_LPM_SUPPORT;
422
423	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
424		pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) {
425		/*
426		 * try to tame the ASMedia 1042 controller which reports 0.96
427		 * but appears to behave more like 1.0
428		 */
429		xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
430		xhci->quirks |= XHCI_BROKEN_STREAMS;
431	}
432	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
433		pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
434		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
435		xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
436	}
437	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
438	    (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
439	     pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
440	     pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
441		xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
442
443	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
444		pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
445		xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
446
447	if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
448		xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
449
450	if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
451	     pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
452	     pdev->device == 0x9026)
453		xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
454
455	if (pdev->vendor == PCI_VENDOR_ID_AMD &&
456	    (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
457	     pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
458		xhci->quirks |= XHCI_NO_SOFT_RETRY;
459
460	if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) {
461		xhci->quirks |= XHCI_ZHAOXIN_HOST;
462		xhci->quirks |= XHCI_LPM_SUPPORT;
463
464		if (pdev->device == 0x9202) {
465			xhci->quirks |= XHCI_RESET_ON_RESUME;
466			xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH;
467		}
468
469		if (pdev->device == 0x9203)
470			xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH;
471	}
472
473	/* xHC spec requires PCI devices to support D3hot and D3cold */
474	if (xhci->hci_version >= 0x120)
475		xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
476
477	if (xhci->quirks & XHCI_RESET_ON_RESUME)
478		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
479				"QUIRK: Resetting on resume");
480}
481
482#ifdef CONFIG_ACPI
483static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
484{
485	static const guid_t intel_dsm_guid =
486		GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
487			  0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
488	union acpi_object *obj;
489
490	obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
491				NULL);
492	ACPI_FREE(obj);
493}
494
495static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev)
496{
497	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
498	struct xhci_hub *rhub = &xhci->usb3_rhub;
499	int ret;
500	int i;
501
502	/* This is not the usb3 roothub we are looking for */
503	if (hcd != rhub->hcd)
504		return;
505
506	if (hdev->maxchild > rhub->num_ports) {
507		dev_err(&hdev->dev, "USB3 roothub port number mismatch\n");
508		return;
509	}
510
511	for (i = 0; i < hdev->maxchild; i++) {
512		ret = usb_acpi_port_lpm_incapable(hdev, i);
513
514		dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret);
515
516		if (ret >= 0) {
517			rhub->ports[i]->lpm_incapable = ret;
518			continue;
519		}
520	}
521}
522
523#else
524static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
525static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { }
526#endif /* CONFIG_ACPI */
527
528/* called during probe() after chip reset completes */
529static int xhci_pci_setup(struct usb_hcd *hcd)
530{
531	struct xhci_hcd		*xhci;
532	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
533	int			retval;
534
535	xhci = hcd_to_xhci(hcd);
536	if (!xhci->sbrn)
537		pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
538
539	/* imod_interval is the interrupt moderation value in nanoseconds. */
540	xhci->imod_interval = 40000;
541
542	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
543	if (retval)
544		return retval;
545
546	if (!usb_hcd_is_primary_hcd(hcd))
547		return 0;
548
549	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
550		xhci_pme_acpi_rtd3_enable(pdev);
551
552	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
553
554	/* Find any debug ports */
555	return xhci_pci_reinit(xhci, pdev);
556}
557
558static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
559				      struct usb_tt *tt, gfp_t mem_flags)
560{
561	/* Check if acpi claims some USB3 roothub ports are lpm incapable */
562	if (!hdev->parent)
563		xhci_find_lpm_incapable_ports(hcd, hdev);
564
565	return xhci_update_hub_device(hcd, hdev, tt, mem_flags);
566}
567
568/*
569 * We need to register our own PCI probe function (instead of the USB core's
570 * function) in order to create a second roothub under xHCI.
571 */
572static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
573{
574	int retval;
575	struct xhci_hcd *xhci;
576	struct usb_hcd *hcd;
577	struct xhci_driver_data *driver_data;
578	struct reset_control *reset;
579
580	driver_data = (struct xhci_driver_data *)id->driver_data;
581	if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
582		retval = renesas_xhci_check_request_fw(dev, id);
583		if (retval)
584			return retval;
585	}
586
587	reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
588	if (IS_ERR(reset))
589		return PTR_ERR(reset);
590	reset_control_reset(reset);
591
592	/* Prevent runtime suspending between USB-2 and USB-3 initialization */
593	pm_runtime_get_noresume(&dev->dev);
594
595	/* Register the USB 2.0 roothub.
596	 * FIXME: USB core must know to register the USB 2.0 roothub first.
597	 * This is sort of silly, because we could just set the HCD driver flags
598	 * to say USB 2.0, but I'm not sure what the implications would be in
599	 * the other parts of the HCD code.
600	 */
601	retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver);
602
603	if (retval)
604		goto put_runtime_pm;
605
606	/* USB 2.0 roothub is stored in the PCI device now. */
607	hcd = dev_get_drvdata(&dev->dev);
608	xhci = hcd_to_xhci(hcd);
609	xhci->reset = reset;
610	xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
611						 pci_name(dev), hcd);
612	if (!xhci->shared_hcd) {
613		retval = -ENOMEM;
614		goto dealloc_usb2_hcd;
615	}
616
617	retval = xhci_ext_cap_init(xhci);
618	if (retval)
619		goto put_usb3_hcd;
620
621	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
622			IRQF_SHARED);
623	if (retval)
624		goto put_usb3_hcd;
625	/* Roothub already marked as USB 3.0 speed */
626
627	if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
628			HCC_MAX_PSA(xhci->hcc_params) >= 4)
629		xhci->shared_hcd->can_do_streams = 1;
630
631	/* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
632	pm_runtime_put_noidle(&dev->dev);
633
634	if (pci_choose_state(dev, PMSG_SUSPEND) == PCI_D0)
635		pm_runtime_forbid(&dev->dev);
636	else if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
637		pm_runtime_allow(&dev->dev);
638
639	dma_set_max_seg_size(&dev->dev, UINT_MAX);
640
641	return 0;
642
643put_usb3_hcd:
644	usb_put_hcd(xhci->shared_hcd);
645dealloc_usb2_hcd:
646	usb_hcd_pci_remove(dev);
647put_runtime_pm:
648	pm_runtime_put_noidle(&dev->dev);
649	return retval;
650}
651
652static void xhci_pci_remove(struct pci_dev *dev)
653{
654	struct xhci_hcd *xhci;
655
656	xhci = hcd_to_xhci(pci_get_drvdata(dev));
657
658	xhci->xhc_state |= XHCI_STATE_REMOVING;
659
660	if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
661		pm_runtime_forbid(&dev->dev);
662
663	if (xhci->shared_hcd) {
664		usb_remove_hcd(xhci->shared_hcd);
665		usb_put_hcd(xhci->shared_hcd);
666		xhci->shared_hcd = NULL;
667	}
668
669	/* Workaround for spurious wakeups at shutdown with HSW */
670	if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
671		pci_set_power_state(dev, PCI_D3hot);
672
673	usb_hcd_pci_remove(dev);
674}
675
676/*
677 * In some Intel xHCI controllers, in order to get D3 working,
678 * through a vendor specific SSIC CONFIG register at offset 0x883c,
679 * SSIC PORT need to be marked as "unused" before putting xHCI
680 * into D3. After D3 exit, the SSIC port need to be marked as "used".
681 * Without this change, xHCI might not enter D3 state.
682 */
683static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
684{
685	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
686	u32 val;
687	void __iomem *reg;
688	int i;
689
690	for (i = 0; i < SSIC_PORT_NUM; i++) {
691		reg = (void __iomem *) xhci->cap_regs +
692				SSIC_PORT_CFG2 +
693				i * SSIC_PORT_CFG2_OFFSET;
694
695		/* Notify SSIC that SSIC profile programming is not done. */
696		val = readl(reg) & ~PROG_DONE;
697		writel(val, reg);
698
699		/* Mark SSIC port as unused(suspend) or used(resume) */
700		val = readl(reg);
701		if (suspend)
702			val |= SSIC_PORT_UNUSED;
703		else
704			val &= ~SSIC_PORT_UNUSED;
705		writel(val, reg);
706
707		/* Notify SSIC that SSIC profile programming is done */
708		val = readl(reg) | PROG_DONE;
709		writel(val, reg);
710		readl(reg);
711	}
712}
713
714/*
715 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
716 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
717 */
718static void xhci_pme_quirk(struct usb_hcd *hcd)
719{
720	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
721	void __iomem *reg;
722	u32 val;
723
724	reg = (void __iomem *) xhci->cap_regs + 0x80a4;
725	val = readl(reg);
726	writel(val | BIT(28), reg);
727	readl(reg);
728}
729
730static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
731{
732	u32 reg;
733
734	reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
735	reg &= ~BIT(SPARSE_DISABLE_BIT);
736	writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
737}
738
739static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
740{
741	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
742	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
743	int			ret;
744
745	/*
746	 * Systems with the TI redriver that loses port status change events
747	 * need to have the registers polled during D3, so avoid D3cold.
748	 */
749	if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
750		pci_d3cold_disable(pdev);
751
752#ifdef CONFIG_SUSPEND
753	/* d3cold is broken, but only when s2idle is used */
754	if (pm_suspend_target_state == PM_SUSPEND_TO_IDLE &&
755	    xhci->quirks & (XHCI_BROKEN_D3COLD_S2I))
756		pci_d3cold_disable(pdev);
757#endif
758
759	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
760		xhci_pme_quirk(hcd);
761
762	if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
763		xhci_ssic_port_unused_quirk(hcd, true);
764
765	if (xhci->quirks & XHCI_DISABLE_SPARSE)
766		xhci_sparse_control_quirk(hcd);
767
768	ret = xhci_suspend(xhci, do_wakeup);
769
770	/* synchronize irq when using MSI-X */
771	xhci_msix_sync_irqs(xhci);
772
773	if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
774		xhci_ssic_port_unused_quirk(hcd, false);
775
776	return ret;
777}
778
779static int xhci_pci_resume(struct usb_hcd *hcd, pm_message_t msg)
780{
781	struct xhci_hcd		*xhci = hcd_to_xhci(hcd);
782	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
783	int			retval = 0;
784
785	reset_control_reset(xhci->reset);
786
787	/* The BIOS on systems with the Intel Panther Point chipset may or may
788	 * not support xHCI natively.  That means that during system resume, it
789	 * may switch the ports back to EHCI so that users can use their
790	 * keyboard to select a kernel from GRUB after resume from hibernate.
791	 *
792	 * The BIOS is supposed to remember whether the OS had xHCI ports
793	 * enabled before resume, and switch the ports back to xHCI when the
794	 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
795	 * writers.
796	 *
797	 * Unconditionally switch the ports back to xHCI after a system resume.
798	 * It should not matter whether the EHCI or xHCI controller is
799	 * resumed first. It's enough to do the switchover in xHCI because
800	 * USB core won't notice anything as the hub driver doesn't start
801	 * running again until after all the devices (including both EHCI and
802	 * xHCI host controllers) have been resumed.
803	 */
804
805	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
806		usb_enable_intel_xhci_ports(pdev);
807
808	if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
809		xhci_ssic_port_unused_quirk(hcd, false);
810
811	if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
812		xhci_pme_quirk(hcd);
813
814	retval = xhci_resume(xhci, msg);
815	return retval;
816}
817
818static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup)
819{
820	struct xhci_hcd		*xhci = hcd_to_xhci(hcd);
821	struct xhci_port	*port;
822	struct usb_device	*udev;
823	unsigned int		slot_id;
824	u32			portsc;
825	int			i;
826
827	/*
828	 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that
829	 * cause significant boot delay if usb ports are in suspended U3 state
830	 * during boot. Some USB devices survive in U3 state over S4 hibernate
831	 *
832	 * Disable ports that are in U3 if remote wake is not enabled for either
833	 * host controller or connected device
834	 */
835
836	if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT))
837		return 0;
838
839	for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
840		port = &xhci->hw_ports[i];
841		portsc = readl(port->addr);
842
843		if ((portsc & PORT_PLS_MASK) != XDEV_U3)
844			continue;
845
846		slot_id = xhci_find_slot_id_by_port(port->rhub->hcd, xhci,
847						    port->hcd_portnum + 1);
848		if (!slot_id || !xhci->devs[slot_id]) {
849			xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n",
850				 slot_id, port->rhub->hcd->self.busnum, port->hcd_portnum + 1);
 
851			continue;
852		}
853
854		udev = xhci->devs[slot_id]->udev;
855
856		/* if wakeup is enabled then don't disable the port */
857		if (udev->do_remote_wakeup && do_wakeup)
858			continue;
859
860		xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n",
861			 port->rhub->hcd->self.busnum, port->hcd_portnum + 1);
862		portsc = xhci_port_state_to_neutral(portsc);
863		writel(portsc | PORT_PE, port->addr);
864	}
865
866	return 0;
867}
868
869static void xhci_pci_shutdown(struct usb_hcd *hcd)
870{
871	struct xhci_hcd		*xhci = hcd_to_xhci(hcd);
872	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
873
874	xhci_shutdown(hcd);
875	xhci_cleanup_msix(xhci);
876
877	/* Yet another workaround for spurious wakeups at shutdown with HSW */
878	if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
879		pci_set_power_state(pdev, PCI_D3hot);
880}
881
882/*-------------------------------------------------------------------------*/
883
884static const struct xhci_driver_data reneses_data = {
885	.quirks  = XHCI_RENESAS_FW_QUIRK,
886	.firmware = "renesas_usb_fw.mem",
887};
888
889/* PCI driver selection metadata; PCI hotplugging uses this */
890static const struct pci_device_id pci_ids[] = {
891	{ PCI_DEVICE(0x1912, 0x0014),
892		.driver_data =  (unsigned long)&reneses_data,
893	},
894	{ PCI_DEVICE(0x1912, 0x0015),
895		.driver_data =  (unsigned long)&reneses_data,
896	},
897	/* handle any USB 3.0 xHCI controller */
898	{ PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
899	},
900	{ /* end: all zeroes */ }
901};
902MODULE_DEVICE_TABLE(pci, pci_ids);
903
904/*
905 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
906 * load firmware, so don't encumber the xhci-pci driver with it.
907 */
908#if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
909MODULE_FIRMWARE("renesas_usb_fw.mem");
910#endif
911
912/* pci driver glue; this is a "new style" PCI driver module */
913static struct pci_driver xhci_pci_driver = {
914	.name =		hcd_name,
915	.id_table =	pci_ids,
916
917	.probe =	xhci_pci_probe,
918	.remove =	xhci_pci_remove,
919	/* suspend and resume implemented later */
920
921	.shutdown = 	usb_hcd_pci_shutdown,
922	.driver = {
923		.pm = pm_ptr(&usb_hcd_pci_pm_ops),
924	},
925};
926
927static int __init xhci_pci_init(void)
928{
929	xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
930	xhci_pci_hc_driver.pci_suspend = pm_ptr(xhci_pci_suspend);
931	xhci_pci_hc_driver.pci_resume = pm_ptr(xhci_pci_resume);
932	xhci_pci_hc_driver.pci_poweroff_late = pm_ptr(xhci_pci_poweroff_late);
933	xhci_pci_hc_driver.shutdown = pm_ptr(xhci_pci_shutdown);
934	xhci_pci_hc_driver.stop = xhci_pci_stop;
935	return pci_register_driver(&xhci_pci_driver);
936}
937module_init(xhci_pci_init);
938
939static void __exit xhci_pci_exit(void)
940{
941	pci_unregister_driver(&xhci_pci_driver);
942}
943module_exit(xhci_pci_exit);
944
945MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
946MODULE_LICENSE("GPL");