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1// SPDX-License-Identifier: BSD-3-Clause-Clear
2/*
3 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7#include <linux/msi.h>
8#include <linux/pci.h>
9
10#include "core.h"
11#include "debug.h"
12#include "mhi.h"
13#include "pci.h"
14
15#define MHI_TIMEOUT_DEFAULT_MS 90000
16
17static const struct mhi_channel_config ath12k_mhi_channels_qcn9274[] = {
18 {
19 .num = 0,
20 .name = "LOOPBACK",
21 .num_elements = 32,
22 .event_ring = 1,
23 .dir = DMA_TO_DEVICE,
24 .ee_mask = 0x4,
25 .pollcfg = 0,
26 .doorbell = MHI_DB_BRST_DISABLE,
27 .lpm_notify = false,
28 .offload_channel = false,
29 .doorbell_mode_switch = false,
30 .auto_queue = false,
31 },
32 {
33 .num = 1,
34 .name = "LOOPBACK",
35 .num_elements = 32,
36 .event_ring = 1,
37 .dir = DMA_FROM_DEVICE,
38 .ee_mask = 0x4,
39 .pollcfg = 0,
40 .doorbell = MHI_DB_BRST_DISABLE,
41 .lpm_notify = false,
42 .offload_channel = false,
43 .doorbell_mode_switch = false,
44 .auto_queue = false,
45 },
46 {
47 .num = 20,
48 .name = "IPCR",
49 .num_elements = 32,
50 .event_ring = 1,
51 .dir = DMA_TO_DEVICE,
52 .ee_mask = 0x4,
53 .pollcfg = 0,
54 .doorbell = MHI_DB_BRST_DISABLE,
55 .lpm_notify = false,
56 .offload_channel = false,
57 .doorbell_mode_switch = false,
58 .auto_queue = false,
59 },
60 {
61 .num = 21,
62 .name = "IPCR",
63 .num_elements = 32,
64 .event_ring = 1,
65 .dir = DMA_FROM_DEVICE,
66 .ee_mask = 0x4,
67 .pollcfg = 0,
68 .doorbell = MHI_DB_BRST_DISABLE,
69 .lpm_notify = false,
70 .offload_channel = false,
71 .doorbell_mode_switch = false,
72 .auto_queue = true,
73 },
74};
75
76static struct mhi_event_config ath12k_mhi_events_qcn9274[] = {
77 {
78 .num_elements = 32,
79 .irq_moderation_ms = 0,
80 .irq = 1,
81 .data_type = MHI_ER_CTRL,
82 .mode = MHI_DB_BRST_DISABLE,
83 .hardware_event = false,
84 .client_managed = false,
85 .offload_channel = false,
86 },
87 {
88 .num_elements = 256,
89 .irq_moderation_ms = 1,
90 .irq = 2,
91 .mode = MHI_DB_BRST_DISABLE,
92 .priority = 1,
93 .hardware_event = false,
94 .client_managed = false,
95 .offload_channel = false,
96 },
97};
98
99const struct mhi_controller_config ath12k_mhi_config_qcn9274 = {
100 .max_channels = 30,
101 .timeout_ms = 10000,
102 .use_bounce_buf = false,
103 .buf_len = 0,
104 .num_channels = ARRAY_SIZE(ath12k_mhi_channels_qcn9274),
105 .ch_cfg = ath12k_mhi_channels_qcn9274,
106 .num_events = ARRAY_SIZE(ath12k_mhi_events_qcn9274),
107 .event_cfg = ath12k_mhi_events_qcn9274,
108};
109
110static const struct mhi_channel_config ath12k_mhi_channels_wcn7850[] = {
111 {
112 .num = 0,
113 .name = "LOOPBACK",
114 .num_elements = 32,
115 .event_ring = 0,
116 .dir = DMA_TO_DEVICE,
117 .ee_mask = 0x4,
118 .pollcfg = 0,
119 .doorbell = MHI_DB_BRST_DISABLE,
120 .lpm_notify = false,
121 .offload_channel = false,
122 .doorbell_mode_switch = false,
123 .auto_queue = false,
124 },
125 {
126 .num = 1,
127 .name = "LOOPBACK",
128 .num_elements = 32,
129 .event_ring = 0,
130 .dir = DMA_FROM_DEVICE,
131 .ee_mask = 0x4,
132 .pollcfg = 0,
133 .doorbell = MHI_DB_BRST_DISABLE,
134 .lpm_notify = false,
135 .offload_channel = false,
136 .doorbell_mode_switch = false,
137 .auto_queue = false,
138 },
139 {
140 .num = 20,
141 .name = "IPCR",
142 .num_elements = 64,
143 .event_ring = 1,
144 .dir = DMA_TO_DEVICE,
145 .ee_mask = 0x4,
146 .pollcfg = 0,
147 .doorbell = MHI_DB_BRST_DISABLE,
148 .lpm_notify = false,
149 .offload_channel = false,
150 .doorbell_mode_switch = false,
151 .auto_queue = false,
152 },
153 {
154 .num = 21,
155 .name = "IPCR",
156 .num_elements = 64,
157 .event_ring = 1,
158 .dir = DMA_FROM_DEVICE,
159 .ee_mask = 0x4,
160 .pollcfg = 0,
161 .doorbell = MHI_DB_BRST_DISABLE,
162 .lpm_notify = false,
163 .offload_channel = false,
164 .doorbell_mode_switch = false,
165 .auto_queue = true,
166 },
167};
168
169static struct mhi_event_config ath12k_mhi_events_wcn7850[] = {
170 {
171 .num_elements = 32,
172 .irq_moderation_ms = 0,
173 .irq = 1,
174 .mode = MHI_DB_BRST_DISABLE,
175 .data_type = MHI_ER_CTRL,
176 .hardware_event = false,
177 .client_managed = false,
178 .offload_channel = false,
179 },
180 {
181 .num_elements = 256,
182 .irq_moderation_ms = 1,
183 .irq = 2,
184 .mode = MHI_DB_BRST_DISABLE,
185 .priority = 1,
186 .hardware_event = false,
187 .client_managed = false,
188 .offload_channel = false,
189 },
190};
191
192const struct mhi_controller_config ath12k_mhi_config_wcn7850 = {
193 .max_channels = 128,
194 .timeout_ms = 2000,
195 .use_bounce_buf = false,
196 .buf_len = 0,
197 .num_channels = ARRAY_SIZE(ath12k_mhi_channels_wcn7850),
198 .ch_cfg = ath12k_mhi_channels_wcn7850,
199 .num_events = ARRAY_SIZE(ath12k_mhi_events_wcn7850),
200 .event_cfg = ath12k_mhi_events_wcn7850,
201};
202
203void ath12k_mhi_set_mhictrl_reset(struct ath12k_base *ab)
204{
205 u32 val;
206
207 val = ath12k_pci_read32(ab, MHISTATUS);
208
209 ath12k_dbg(ab, ATH12K_DBG_PCI, "MHISTATUS 0x%x\n", val);
210
211 /* Observed on some targets that after SOC_GLOBAL_RESET, MHISTATUS
212 * has SYSERR bit set and thus need to set MHICTRL_RESET
213 * to clear SYSERR.
214 */
215 ath12k_pci_write32(ab, MHICTRL, MHICTRL_RESET_MASK);
216
217 mdelay(10);
218}
219
220static void ath12k_mhi_reset_txvecdb(struct ath12k_base *ab)
221{
222 ath12k_pci_write32(ab, PCIE_TXVECDB, 0);
223}
224
225static void ath12k_mhi_reset_txvecstatus(struct ath12k_base *ab)
226{
227 ath12k_pci_write32(ab, PCIE_TXVECSTATUS, 0);
228}
229
230static void ath12k_mhi_reset_rxvecdb(struct ath12k_base *ab)
231{
232 ath12k_pci_write32(ab, PCIE_RXVECDB, 0);
233}
234
235static void ath12k_mhi_reset_rxvecstatus(struct ath12k_base *ab)
236{
237 ath12k_pci_write32(ab, PCIE_RXVECSTATUS, 0);
238}
239
240void ath12k_mhi_clear_vector(struct ath12k_base *ab)
241{
242 ath12k_mhi_reset_txvecdb(ab);
243 ath12k_mhi_reset_txvecstatus(ab);
244 ath12k_mhi_reset_rxvecdb(ab);
245 ath12k_mhi_reset_rxvecstatus(ab);
246}
247
248static int ath12k_mhi_get_msi(struct ath12k_pci *ab_pci)
249{
250 struct ath12k_base *ab = ab_pci->ab;
251 u32 user_base_data, base_vector;
252 int ret, num_vectors, i;
253 int *irq;
254 unsigned int msi_data;
255
256 ret = ath12k_pci_get_user_msi_assignment(ab,
257 "MHI", &num_vectors,
258 &user_base_data, &base_vector);
259 if (ret)
260 return ret;
261
262 ath12k_dbg(ab, ATH12K_DBG_PCI, "Number of assigned MSI for MHI is %d, base vector is %d\n",
263 num_vectors, base_vector);
264
265 irq = kcalloc(num_vectors, sizeof(*irq), GFP_KERNEL);
266 if (!irq)
267 return -ENOMEM;
268
269 msi_data = base_vector;
270 for (i = 0; i < num_vectors; i++) {
271 if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
272 irq[i] = ath12k_pci_get_msi_irq(ab->dev,
273 msi_data++);
274 else
275 irq[i] = ath12k_pci_get_msi_irq(ab->dev,
276 msi_data);
277 }
278
279 ab_pci->mhi_ctrl->irq = irq;
280 ab_pci->mhi_ctrl->nr_irqs = num_vectors;
281
282 return 0;
283}
284
285static int ath12k_mhi_op_runtime_get(struct mhi_controller *mhi_cntrl)
286{
287 return 0;
288}
289
290static void ath12k_mhi_op_runtime_put(struct mhi_controller *mhi_cntrl)
291{
292}
293
294static char *ath12k_mhi_op_callback_to_str(enum mhi_callback reason)
295{
296 switch (reason) {
297 case MHI_CB_IDLE:
298 return "MHI_CB_IDLE";
299 case MHI_CB_PENDING_DATA:
300 return "MHI_CB_PENDING_DATA";
301 case MHI_CB_LPM_ENTER:
302 return "MHI_CB_LPM_ENTER";
303 case MHI_CB_LPM_EXIT:
304 return "MHI_CB_LPM_EXIT";
305 case MHI_CB_EE_RDDM:
306 return "MHI_CB_EE_RDDM";
307 case MHI_CB_EE_MISSION_MODE:
308 return "MHI_CB_EE_MISSION_MODE";
309 case MHI_CB_SYS_ERROR:
310 return "MHI_CB_SYS_ERROR";
311 case MHI_CB_FATAL_ERROR:
312 return "MHI_CB_FATAL_ERROR";
313 case MHI_CB_BW_REQ:
314 return "MHI_CB_BW_REQ";
315 default:
316 return "UNKNOWN";
317 }
318}
319
320static void ath12k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl,
321 enum mhi_callback cb)
322{
323 struct ath12k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev);
324
325 ath12k_dbg(ab, ATH12K_DBG_BOOT, "mhi notify status reason %s\n",
326 ath12k_mhi_op_callback_to_str(cb));
327
328 switch (cb) {
329 case MHI_CB_SYS_ERROR:
330 ath12k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n");
331 break;
332 case MHI_CB_EE_RDDM:
333 if (!(test_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags)))
334 queue_work(ab->workqueue_aux, &ab->reset_work);
335 break;
336 default:
337 break;
338 }
339}
340
341static int ath12k_mhi_op_read_reg(struct mhi_controller *mhi_cntrl,
342 void __iomem *addr,
343 u32 *out)
344{
345 *out = readl(addr);
346
347 return 0;
348}
349
350static void ath12k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl,
351 void __iomem *addr,
352 u32 val)
353{
354 writel(val, addr);
355}
356
357int ath12k_mhi_register(struct ath12k_pci *ab_pci)
358{
359 struct ath12k_base *ab = ab_pci->ab;
360 struct mhi_controller *mhi_ctrl;
361 int ret;
362
363 mhi_ctrl = mhi_alloc_controller();
364 if (!mhi_ctrl)
365 return -ENOMEM;
366
367 ath12k_core_create_firmware_path(ab, ATH12K_AMSS_FILE,
368 ab_pci->amss_path,
369 sizeof(ab_pci->amss_path));
370
371 ab_pci->mhi_ctrl = mhi_ctrl;
372 mhi_ctrl->cntrl_dev = ab->dev;
373 mhi_ctrl->fw_image = ab_pci->amss_path;
374 mhi_ctrl->regs = ab->mem;
375 mhi_ctrl->reg_len = ab->mem_len;
376 mhi_ctrl->rddm_size = ab->hw_params->rddm_size;
377
378 ret = ath12k_mhi_get_msi(ab_pci);
379 if (ret) {
380 ath12k_err(ab, "failed to get msi for mhi\n");
381 goto free_controller;
382 }
383
384 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
385 mhi_ctrl->irq_flags = IRQF_SHARED | IRQF_NOBALANCING;
386
387 mhi_ctrl->iova_start = 0;
388 mhi_ctrl->iova_stop = 0xffffffff;
389 mhi_ctrl->sbl_size = SZ_512K;
390 mhi_ctrl->seg_len = SZ_512K;
391 mhi_ctrl->fbc_download = true;
392 mhi_ctrl->runtime_get = ath12k_mhi_op_runtime_get;
393 mhi_ctrl->runtime_put = ath12k_mhi_op_runtime_put;
394 mhi_ctrl->status_cb = ath12k_mhi_op_status_cb;
395 mhi_ctrl->read_reg = ath12k_mhi_op_read_reg;
396 mhi_ctrl->write_reg = ath12k_mhi_op_write_reg;
397
398 ret = mhi_register_controller(mhi_ctrl, ab->hw_params->mhi_config);
399 if (ret) {
400 ath12k_err(ab, "failed to register to mhi bus, err = %d\n", ret);
401 goto free_controller;
402 }
403
404 return 0;
405
406free_controller:
407 mhi_free_controller(mhi_ctrl);
408 ab_pci->mhi_ctrl = NULL;
409 return ret;
410}
411
412void ath12k_mhi_unregister(struct ath12k_pci *ab_pci)
413{
414 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl;
415
416 mhi_unregister_controller(mhi_ctrl);
417 kfree(mhi_ctrl->irq);
418 mhi_free_controller(mhi_ctrl);
419 ab_pci->mhi_ctrl = NULL;
420}
421
422static char *ath12k_mhi_state_to_str(enum ath12k_mhi_state mhi_state)
423{
424 switch (mhi_state) {
425 case ATH12K_MHI_INIT:
426 return "INIT";
427 case ATH12K_MHI_DEINIT:
428 return "DEINIT";
429 case ATH12K_MHI_POWER_ON:
430 return "POWER_ON";
431 case ATH12K_MHI_POWER_OFF:
432 return "POWER_OFF";
433 case ATH12K_MHI_FORCE_POWER_OFF:
434 return "FORCE_POWER_OFF";
435 case ATH12K_MHI_SUSPEND:
436 return "SUSPEND";
437 case ATH12K_MHI_RESUME:
438 return "RESUME";
439 case ATH12K_MHI_TRIGGER_RDDM:
440 return "TRIGGER_RDDM";
441 case ATH12K_MHI_RDDM_DONE:
442 return "RDDM_DONE";
443 default:
444 return "UNKNOWN";
445 }
446};
447
448static void ath12k_mhi_set_state_bit(struct ath12k_pci *ab_pci,
449 enum ath12k_mhi_state mhi_state)
450{
451 struct ath12k_base *ab = ab_pci->ab;
452
453 switch (mhi_state) {
454 case ATH12K_MHI_INIT:
455 set_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state);
456 break;
457 case ATH12K_MHI_DEINIT:
458 clear_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state);
459 break;
460 case ATH12K_MHI_POWER_ON:
461 set_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state);
462 break;
463 case ATH12K_MHI_POWER_OFF:
464 case ATH12K_MHI_FORCE_POWER_OFF:
465 clear_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state);
466 clear_bit(ATH12K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state);
467 clear_bit(ATH12K_MHI_RDDM_DONE, &ab_pci->mhi_state);
468 break;
469 case ATH12K_MHI_SUSPEND:
470 set_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state);
471 break;
472 case ATH12K_MHI_RESUME:
473 clear_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state);
474 break;
475 case ATH12K_MHI_TRIGGER_RDDM:
476 set_bit(ATH12K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state);
477 break;
478 case ATH12K_MHI_RDDM_DONE:
479 set_bit(ATH12K_MHI_RDDM_DONE, &ab_pci->mhi_state);
480 break;
481 default:
482 ath12k_err(ab, "unhandled mhi state (%d)\n", mhi_state);
483 }
484}
485
486static int ath12k_mhi_check_state_bit(struct ath12k_pci *ab_pci,
487 enum ath12k_mhi_state mhi_state)
488{
489 struct ath12k_base *ab = ab_pci->ab;
490
491 switch (mhi_state) {
492 case ATH12K_MHI_INIT:
493 if (!test_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state))
494 return 0;
495 break;
496 case ATH12K_MHI_DEINIT:
497 case ATH12K_MHI_POWER_ON:
498 if (test_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state) &&
499 !test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state))
500 return 0;
501 break;
502 case ATH12K_MHI_FORCE_POWER_OFF:
503 if (test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state))
504 return 0;
505 break;
506 case ATH12K_MHI_POWER_OFF:
507 case ATH12K_MHI_SUSPEND:
508 if (test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state) &&
509 !test_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state))
510 return 0;
511 break;
512 case ATH12K_MHI_RESUME:
513 if (test_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state))
514 return 0;
515 break;
516 case ATH12K_MHI_TRIGGER_RDDM:
517 if (test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state) &&
518 !test_bit(ATH12K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state))
519 return 0;
520 break;
521 case ATH12K_MHI_RDDM_DONE:
522 return 0;
523 default:
524 ath12k_err(ab, "unhandled mhi state: %s(%d)\n",
525 ath12k_mhi_state_to_str(mhi_state), mhi_state);
526 }
527
528 ath12k_err(ab, "failed to set mhi state %s(%d) in current mhi state (0x%lx)\n",
529 ath12k_mhi_state_to_str(mhi_state), mhi_state,
530 ab_pci->mhi_state);
531
532 return -EINVAL;
533}
534
535static int ath12k_mhi_set_state(struct ath12k_pci *ab_pci,
536 enum ath12k_mhi_state mhi_state)
537{
538 struct ath12k_base *ab = ab_pci->ab;
539 int ret;
540
541 ret = ath12k_mhi_check_state_bit(ab_pci, mhi_state);
542 if (ret)
543 goto out;
544
545 ath12k_dbg(ab, ATH12K_DBG_PCI, "setting mhi state: %s(%d)\n",
546 ath12k_mhi_state_to_str(mhi_state), mhi_state);
547
548 switch (mhi_state) {
549 case ATH12K_MHI_INIT:
550 ret = mhi_prepare_for_power_up(ab_pci->mhi_ctrl);
551 break;
552 case ATH12K_MHI_DEINIT:
553 mhi_unprepare_after_power_down(ab_pci->mhi_ctrl);
554 ret = 0;
555 break;
556 case ATH12K_MHI_POWER_ON:
557 ret = mhi_async_power_up(ab_pci->mhi_ctrl);
558 break;
559 case ATH12K_MHI_POWER_OFF:
560 mhi_power_down(ab_pci->mhi_ctrl, true);
561 ret = 0;
562 break;
563 case ATH12K_MHI_FORCE_POWER_OFF:
564 mhi_power_down(ab_pci->mhi_ctrl, false);
565 ret = 0;
566 break;
567 case ATH12K_MHI_SUSPEND:
568 ret = mhi_pm_suspend(ab_pci->mhi_ctrl);
569 break;
570 case ATH12K_MHI_RESUME:
571 ret = mhi_pm_resume(ab_pci->mhi_ctrl);
572 break;
573 case ATH12K_MHI_TRIGGER_RDDM:
574 ret = mhi_force_rddm_mode(ab_pci->mhi_ctrl);
575 break;
576 case ATH12K_MHI_RDDM_DONE:
577 break;
578 default:
579 ath12k_err(ab, "unhandled MHI state (%d)\n", mhi_state);
580 ret = -EINVAL;
581 }
582
583 if (ret)
584 goto out;
585
586 ath12k_mhi_set_state_bit(ab_pci, mhi_state);
587
588 return 0;
589
590out:
591 ath12k_err(ab, "failed to set mhi state: %s(%d)\n",
592 ath12k_mhi_state_to_str(mhi_state), mhi_state);
593 return ret;
594}
595
596int ath12k_mhi_start(struct ath12k_pci *ab_pci)
597{
598 int ret;
599
600 ab_pci->mhi_ctrl->timeout_ms = MHI_TIMEOUT_DEFAULT_MS;
601
602 ret = ath12k_mhi_set_state(ab_pci, ATH12K_MHI_INIT);
603 if (ret)
604 goto out;
605
606 ret = ath12k_mhi_set_state(ab_pci, ATH12K_MHI_POWER_ON);
607 if (ret)
608 goto out;
609
610 return 0;
611
612out:
613 return ret;
614}
615
616void ath12k_mhi_stop(struct ath12k_pci *ab_pci)
617{
618 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_POWER_OFF);
619 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_DEINIT);
620}
621
622void ath12k_mhi_suspend(struct ath12k_pci *ab_pci)
623{
624 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_SUSPEND);
625}
626
627void ath12k_mhi_resume(struct ath12k_pci *ab_pci)
628{
629 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_RESUME);
630}
1// SPDX-License-Identifier: BSD-3-Clause-Clear
2/*
3 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7#include <linux/msi.h>
8#include <linux/pci.h>
9#include <linux/firmware.h>
10
11#include "core.h"
12#include "debug.h"
13#include "mhi.h"
14#include "pci.h"
15
16#define MHI_TIMEOUT_DEFAULT_MS 90000
17#define OTP_INVALID_BOARD_ID 0xFFFF
18#define OTP_VALID_DUALMAC_BOARD_ID_MASK 0x1000
19
20static const struct mhi_channel_config ath12k_mhi_channels_qcn9274[] = {
21 {
22 .num = 0,
23 .name = "LOOPBACK",
24 .num_elements = 32,
25 .event_ring = 1,
26 .dir = DMA_TO_DEVICE,
27 .ee_mask = 0x4,
28 .pollcfg = 0,
29 .doorbell = MHI_DB_BRST_DISABLE,
30 .lpm_notify = false,
31 .offload_channel = false,
32 .doorbell_mode_switch = false,
33 .auto_queue = false,
34 },
35 {
36 .num = 1,
37 .name = "LOOPBACK",
38 .num_elements = 32,
39 .event_ring = 1,
40 .dir = DMA_FROM_DEVICE,
41 .ee_mask = 0x4,
42 .pollcfg = 0,
43 .doorbell = MHI_DB_BRST_DISABLE,
44 .lpm_notify = false,
45 .offload_channel = false,
46 .doorbell_mode_switch = false,
47 .auto_queue = false,
48 },
49 {
50 .num = 20,
51 .name = "IPCR",
52 .num_elements = 32,
53 .event_ring = 1,
54 .dir = DMA_TO_DEVICE,
55 .ee_mask = 0x4,
56 .pollcfg = 0,
57 .doorbell = MHI_DB_BRST_DISABLE,
58 .lpm_notify = false,
59 .offload_channel = false,
60 .doorbell_mode_switch = false,
61 .auto_queue = false,
62 },
63 {
64 .num = 21,
65 .name = "IPCR",
66 .num_elements = 32,
67 .event_ring = 1,
68 .dir = DMA_FROM_DEVICE,
69 .ee_mask = 0x4,
70 .pollcfg = 0,
71 .doorbell = MHI_DB_BRST_DISABLE,
72 .lpm_notify = false,
73 .offload_channel = false,
74 .doorbell_mode_switch = false,
75 .auto_queue = true,
76 },
77};
78
79static struct mhi_event_config ath12k_mhi_events_qcn9274[] = {
80 {
81 .num_elements = 32,
82 .irq_moderation_ms = 0,
83 .irq = 1,
84 .data_type = MHI_ER_CTRL,
85 .mode = MHI_DB_BRST_DISABLE,
86 .hardware_event = false,
87 .client_managed = false,
88 .offload_channel = false,
89 },
90 {
91 .num_elements = 256,
92 .irq_moderation_ms = 1,
93 .irq = 2,
94 .mode = MHI_DB_BRST_DISABLE,
95 .priority = 1,
96 .hardware_event = false,
97 .client_managed = false,
98 .offload_channel = false,
99 },
100};
101
102const struct mhi_controller_config ath12k_mhi_config_qcn9274 = {
103 .max_channels = 30,
104 .timeout_ms = 10000,
105 .use_bounce_buf = false,
106 .buf_len = 0,
107 .num_channels = ARRAY_SIZE(ath12k_mhi_channels_qcn9274),
108 .ch_cfg = ath12k_mhi_channels_qcn9274,
109 .num_events = ARRAY_SIZE(ath12k_mhi_events_qcn9274),
110 .event_cfg = ath12k_mhi_events_qcn9274,
111};
112
113static const struct mhi_channel_config ath12k_mhi_channels_wcn7850[] = {
114 {
115 .num = 0,
116 .name = "LOOPBACK",
117 .num_elements = 32,
118 .event_ring = 0,
119 .dir = DMA_TO_DEVICE,
120 .ee_mask = 0x4,
121 .pollcfg = 0,
122 .doorbell = MHI_DB_BRST_DISABLE,
123 .lpm_notify = false,
124 .offload_channel = false,
125 .doorbell_mode_switch = false,
126 .auto_queue = false,
127 },
128 {
129 .num = 1,
130 .name = "LOOPBACK",
131 .num_elements = 32,
132 .event_ring = 0,
133 .dir = DMA_FROM_DEVICE,
134 .ee_mask = 0x4,
135 .pollcfg = 0,
136 .doorbell = MHI_DB_BRST_DISABLE,
137 .lpm_notify = false,
138 .offload_channel = false,
139 .doorbell_mode_switch = false,
140 .auto_queue = false,
141 },
142 {
143 .num = 20,
144 .name = "IPCR",
145 .num_elements = 64,
146 .event_ring = 1,
147 .dir = DMA_TO_DEVICE,
148 .ee_mask = 0x4,
149 .pollcfg = 0,
150 .doorbell = MHI_DB_BRST_DISABLE,
151 .lpm_notify = false,
152 .offload_channel = false,
153 .doorbell_mode_switch = false,
154 .auto_queue = false,
155 },
156 {
157 .num = 21,
158 .name = "IPCR",
159 .num_elements = 64,
160 .event_ring = 1,
161 .dir = DMA_FROM_DEVICE,
162 .ee_mask = 0x4,
163 .pollcfg = 0,
164 .doorbell = MHI_DB_BRST_DISABLE,
165 .lpm_notify = false,
166 .offload_channel = false,
167 .doorbell_mode_switch = false,
168 .auto_queue = true,
169 },
170};
171
172static struct mhi_event_config ath12k_mhi_events_wcn7850[] = {
173 {
174 .num_elements = 32,
175 .irq_moderation_ms = 0,
176 .irq = 1,
177 .mode = MHI_DB_BRST_DISABLE,
178 .data_type = MHI_ER_CTRL,
179 .hardware_event = false,
180 .client_managed = false,
181 .offload_channel = false,
182 },
183 {
184 .num_elements = 256,
185 .irq_moderation_ms = 1,
186 .irq = 2,
187 .mode = MHI_DB_BRST_DISABLE,
188 .priority = 1,
189 .hardware_event = false,
190 .client_managed = false,
191 .offload_channel = false,
192 },
193};
194
195const struct mhi_controller_config ath12k_mhi_config_wcn7850 = {
196 .max_channels = 128,
197 .timeout_ms = 2000,
198 .use_bounce_buf = false,
199 .buf_len = 0,
200 .num_channels = ARRAY_SIZE(ath12k_mhi_channels_wcn7850),
201 .ch_cfg = ath12k_mhi_channels_wcn7850,
202 .num_events = ARRAY_SIZE(ath12k_mhi_events_wcn7850),
203 .event_cfg = ath12k_mhi_events_wcn7850,
204};
205
206void ath12k_mhi_set_mhictrl_reset(struct ath12k_base *ab)
207{
208 u32 val;
209
210 val = ath12k_pci_read32(ab, MHISTATUS);
211
212 ath12k_dbg(ab, ATH12K_DBG_PCI, "MHISTATUS 0x%x\n", val);
213
214 /* Observed on some targets that after SOC_GLOBAL_RESET, MHISTATUS
215 * has SYSERR bit set and thus need to set MHICTRL_RESET
216 * to clear SYSERR.
217 */
218 ath12k_pci_write32(ab, MHICTRL, MHICTRL_RESET_MASK);
219
220 mdelay(10);
221}
222
223static void ath12k_mhi_reset_txvecdb(struct ath12k_base *ab)
224{
225 ath12k_pci_write32(ab, PCIE_TXVECDB, 0);
226}
227
228static void ath12k_mhi_reset_txvecstatus(struct ath12k_base *ab)
229{
230 ath12k_pci_write32(ab, PCIE_TXVECSTATUS, 0);
231}
232
233static void ath12k_mhi_reset_rxvecdb(struct ath12k_base *ab)
234{
235 ath12k_pci_write32(ab, PCIE_RXVECDB, 0);
236}
237
238static void ath12k_mhi_reset_rxvecstatus(struct ath12k_base *ab)
239{
240 ath12k_pci_write32(ab, PCIE_RXVECSTATUS, 0);
241}
242
243void ath12k_mhi_clear_vector(struct ath12k_base *ab)
244{
245 ath12k_mhi_reset_txvecdb(ab);
246 ath12k_mhi_reset_txvecstatus(ab);
247 ath12k_mhi_reset_rxvecdb(ab);
248 ath12k_mhi_reset_rxvecstatus(ab);
249}
250
251static int ath12k_mhi_get_msi(struct ath12k_pci *ab_pci)
252{
253 struct ath12k_base *ab = ab_pci->ab;
254 u32 user_base_data, base_vector;
255 int ret, num_vectors, i;
256 int *irq;
257 unsigned int msi_data;
258
259 ret = ath12k_pci_get_user_msi_assignment(ab,
260 "MHI", &num_vectors,
261 &user_base_data, &base_vector);
262 if (ret)
263 return ret;
264
265 ath12k_dbg(ab, ATH12K_DBG_PCI, "Number of assigned MSI for MHI is %d, base vector is %d\n",
266 num_vectors, base_vector);
267
268 irq = kcalloc(num_vectors, sizeof(*irq), GFP_KERNEL);
269 if (!irq)
270 return -ENOMEM;
271
272 msi_data = base_vector;
273 for (i = 0; i < num_vectors; i++) {
274 if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
275 irq[i] = ath12k_pci_get_msi_irq(ab->dev,
276 msi_data++);
277 else
278 irq[i] = ath12k_pci_get_msi_irq(ab->dev,
279 msi_data);
280 }
281
282 ab_pci->mhi_ctrl->irq = irq;
283 ab_pci->mhi_ctrl->nr_irqs = num_vectors;
284
285 return 0;
286}
287
288static int ath12k_mhi_op_runtime_get(struct mhi_controller *mhi_cntrl)
289{
290 return 0;
291}
292
293static void ath12k_mhi_op_runtime_put(struct mhi_controller *mhi_cntrl)
294{
295}
296
297static char *ath12k_mhi_op_callback_to_str(enum mhi_callback reason)
298{
299 switch (reason) {
300 case MHI_CB_IDLE:
301 return "MHI_CB_IDLE";
302 case MHI_CB_PENDING_DATA:
303 return "MHI_CB_PENDING_DATA";
304 case MHI_CB_LPM_ENTER:
305 return "MHI_CB_LPM_ENTER";
306 case MHI_CB_LPM_EXIT:
307 return "MHI_CB_LPM_EXIT";
308 case MHI_CB_EE_RDDM:
309 return "MHI_CB_EE_RDDM";
310 case MHI_CB_EE_MISSION_MODE:
311 return "MHI_CB_EE_MISSION_MODE";
312 case MHI_CB_SYS_ERROR:
313 return "MHI_CB_SYS_ERROR";
314 case MHI_CB_FATAL_ERROR:
315 return "MHI_CB_FATAL_ERROR";
316 case MHI_CB_BW_REQ:
317 return "MHI_CB_BW_REQ";
318 default:
319 return "UNKNOWN";
320 }
321}
322
323static void ath12k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl,
324 enum mhi_callback cb)
325{
326 struct ath12k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev);
327
328 ath12k_dbg(ab, ATH12K_DBG_BOOT, "mhi notify status reason %s\n",
329 ath12k_mhi_op_callback_to_str(cb));
330
331 switch (cb) {
332 case MHI_CB_SYS_ERROR:
333 ath12k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n");
334 break;
335 case MHI_CB_EE_RDDM:
336 if (!(test_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags)))
337 queue_work(ab->workqueue_aux, &ab->reset_work);
338 break;
339 default:
340 break;
341 }
342}
343
344static int ath12k_mhi_op_read_reg(struct mhi_controller *mhi_cntrl,
345 void __iomem *addr,
346 u32 *out)
347{
348 *out = readl(addr);
349
350 return 0;
351}
352
353static void ath12k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl,
354 void __iomem *addr,
355 u32 val)
356{
357 writel(val, addr);
358}
359
360int ath12k_mhi_register(struct ath12k_pci *ab_pci)
361{
362 struct ath12k_base *ab = ab_pci->ab;
363 struct mhi_controller *mhi_ctrl;
364 unsigned int board_id;
365 int ret;
366 bool dualmac = false;
367
368 mhi_ctrl = mhi_alloc_controller();
369 if (!mhi_ctrl)
370 return -ENOMEM;
371
372 ab_pci->mhi_ctrl = mhi_ctrl;
373 mhi_ctrl->cntrl_dev = ab->dev;
374 mhi_ctrl->regs = ab->mem;
375 mhi_ctrl->reg_len = ab->mem_len;
376 mhi_ctrl->rddm_size = ab->hw_params->rddm_size;
377
378 if (ab->hw_params->otp_board_id_register) {
379 board_id =
380 ath12k_pci_read32(ab, ab->hw_params->otp_board_id_register);
381 board_id = u32_get_bits(board_id, OTP_BOARD_ID_MASK);
382
383 if (!board_id || (board_id == OTP_INVALID_BOARD_ID)) {
384 ath12k_dbg(ab, ATH12K_DBG_BOOT,
385 "failed to read board id\n");
386 } else if (board_id & OTP_VALID_DUALMAC_BOARD_ID_MASK) {
387 dualmac = true;
388 ab->slo_capable = false;
389 ath12k_dbg(ab, ATH12K_DBG_BOOT,
390 "dualmac fw selected for board id: %x\n", board_id);
391 }
392 }
393
394 if (dualmac) {
395 if (ab->fw.amss_dualmac_data && ab->fw.amss_dualmac_len > 0) {
396 /* use MHI firmware file from firmware-N.bin */
397 mhi_ctrl->fw_data = ab->fw.amss_dualmac_data;
398 mhi_ctrl->fw_sz = ab->fw.amss_dualmac_len;
399 } else {
400 ath12k_warn(ab, "dualmac firmware IE not present in firmware-N.bin\n");
401 ret = -ENOENT;
402 goto free_controller;
403 }
404 } else {
405 if (ab->fw.amss_data && ab->fw.amss_len > 0) {
406 /* use MHI firmware file from firmware-N.bin */
407 mhi_ctrl->fw_data = ab->fw.amss_data;
408 mhi_ctrl->fw_sz = ab->fw.amss_len;
409 } else {
410 /* use the old separate mhi.bin MHI firmware file */
411 ath12k_core_create_firmware_path(ab, ATH12K_AMSS_FILE,
412 ab_pci->amss_path,
413 sizeof(ab_pci->amss_path));
414 mhi_ctrl->fw_image = ab_pci->amss_path;
415 }
416 }
417
418 ret = ath12k_mhi_get_msi(ab_pci);
419 if (ret) {
420 ath12k_err(ab, "failed to get msi for mhi\n");
421 goto free_controller;
422 }
423
424 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags))
425 mhi_ctrl->irq_flags = IRQF_SHARED | IRQF_NOBALANCING;
426
427 mhi_ctrl->iova_start = 0;
428 mhi_ctrl->iova_stop = 0xffffffff;
429 mhi_ctrl->sbl_size = SZ_512K;
430 mhi_ctrl->seg_len = SZ_512K;
431 mhi_ctrl->fbc_download = true;
432 mhi_ctrl->runtime_get = ath12k_mhi_op_runtime_get;
433 mhi_ctrl->runtime_put = ath12k_mhi_op_runtime_put;
434 mhi_ctrl->status_cb = ath12k_mhi_op_status_cb;
435 mhi_ctrl->read_reg = ath12k_mhi_op_read_reg;
436 mhi_ctrl->write_reg = ath12k_mhi_op_write_reg;
437
438 ret = mhi_register_controller(mhi_ctrl, ab->hw_params->mhi_config);
439 if (ret) {
440 ath12k_err(ab, "failed to register to mhi bus, err = %d\n", ret);
441 goto free_controller;
442 }
443
444 return 0;
445
446free_controller:
447 mhi_free_controller(mhi_ctrl);
448 ab_pci->mhi_ctrl = NULL;
449 return ret;
450}
451
452void ath12k_mhi_unregister(struct ath12k_pci *ab_pci)
453{
454 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl;
455
456 mhi_unregister_controller(mhi_ctrl);
457 kfree(mhi_ctrl->irq);
458 mhi_free_controller(mhi_ctrl);
459 ab_pci->mhi_ctrl = NULL;
460}
461
462static char *ath12k_mhi_state_to_str(enum ath12k_mhi_state mhi_state)
463{
464 switch (mhi_state) {
465 case ATH12K_MHI_INIT:
466 return "INIT";
467 case ATH12K_MHI_DEINIT:
468 return "DEINIT";
469 case ATH12K_MHI_POWER_ON:
470 return "POWER_ON";
471 case ATH12K_MHI_POWER_OFF:
472 return "POWER_OFF";
473 case ATH12K_MHI_FORCE_POWER_OFF:
474 return "FORCE_POWER_OFF";
475 case ATH12K_MHI_SUSPEND:
476 return "SUSPEND";
477 case ATH12K_MHI_RESUME:
478 return "RESUME";
479 case ATH12K_MHI_TRIGGER_RDDM:
480 return "TRIGGER_RDDM";
481 case ATH12K_MHI_RDDM_DONE:
482 return "RDDM_DONE";
483 default:
484 return "UNKNOWN";
485 }
486};
487
488static void ath12k_mhi_set_state_bit(struct ath12k_pci *ab_pci,
489 enum ath12k_mhi_state mhi_state)
490{
491 struct ath12k_base *ab = ab_pci->ab;
492
493 switch (mhi_state) {
494 case ATH12K_MHI_INIT:
495 set_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state);
496 break;
497 case ATH12K_MHI_DEINIT:
498 clear_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state);
499 break;
500 case ATH12K_MHI_POWER_ON:
501 set_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state);
502 break;
503 case ATH12K_MHI_POWER_OFF:
504 case ATH12K_MHI_FORCE_POWER_OFF:
505 clear_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state);
506 clear_bit(ATH12K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state);
507 clear_bit(ATH12K_MHI_RDDM_DONE, &ab_pci->mhi_state);
508 break;
509 case ATH12K_MHI_SUSPEND:
510 set_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state);
511 break;
512 case ATH12K_MHI_RESUME:
513 clear_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state);
514 break;
515 case ATH12K_MHI_TRIGGER_RDDM:
516 set_bit(ATH12K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state);
517 break;
518 case ATH12K_MHI_RDDM_DONE:
519 set_bit(ATH12K_MHI_RDDM_DONE, &ab_pci->mhi_state);
520 break;
521 default:
522 ath12k_err(ab, "unhandled mhi state (%d)\n", mhi_state);
523 }
524}
525
526static int ath12k_mhi_check_state_bit(struct ath12k_pci *ab_pci,
527 enum ath12k_mhi_state mhi_state)
528{
529 struct ath12k_base *ab = ab_pci->ab;
530
531 switch (mhi_state) {
532 case ATH12K_MHI_INIT:
533 if (!test_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state))
534 return 0;
535 break;
536 case ATH12K_MHI_DEINIT:
537 case ATH12K_MHI_POWER_ON:
538 if (test_bit(ATH12K_MHI_INIT, &ab_pci->mhi_state) &&
539 !test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state))
540 return 0;
541 break;
542 case ATH12K_MHI_FORCE_POWER_OFF:
543 if (test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state))
544 return 0;
545 break;
546 case ATH12K_MHI_POWER_OFF:
547 case ATH12K_MHI_SUSPEND:
548 if (test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state) &&
549 !test_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state))
550 return 0;
551 break;
552 case ATH12K_MHI_RESUME:
553 if (test_bit(ATH12K_MHI_SUSPEND, &ab_pci->mhi_state))
554 return 0;
555 break;
556 case ATH12K_MHI_TRIGGER_RDDM:
557 if (test_bit(ATH12K_MHI_POWER_ON, &ab_pci->mhi_state) &&
558 !test_bit(ATH12K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state))
559 return 0;
560 break;
561 case ATH12K_MHI_RDDM_DONE:
562 return 0;
563 default:
564 ath12k_err(ab, "unhandled mhi state: %s(%d)\n",
565 ath12k_mhi_state_to_str(mhi_state), mhi_state);
566 }
567
568 ath12k_err(ab, "failed to set mhi state %s(%d) in current mhi state (0x%lx)\n",
569 ath12k_mhi_state_to_str(mhi_state), mhi_state,
570 ab_pci->mhi_state);
571
572 return -EINVAL;
573}
574
575static int ath12k_mhi_set_state(struct ath12k_pci *ab_pci,
576 enum ath12k_mhi_state mhi_state)
577{
578 struct ath12k_base *ab = ab_pci->ab;
579 int ret;
580
581 ret = ath12k_mhi_check_state_bit(ab_pci, mhi_state);
582 if (ret)
583 goto out;
584
585 ath12k_dbg(ab, ATH12K_DBG_PCI, "setting mhi state: %s(%d)\n",
586 ath12k_mhi_state_to_str(mhi_state), mhi_state);
587
588 switch (mhi_state) {
589 case ATH12K_MHI_INIT:
590 ret = mhi_prepare_for_power_up(ab_pci->mhi_ctrl);
591 break;
592 case ATH12K_MHI_DEINIT:
593 mhi_unprepare_after_power_down(ab_pci->mhi_ctrl);
594 ret = 0;
595 break;
596 case ATH12K_MHI_POWER_ON:
597 ret = mhi_async_power_up(ab_pci->mhi_ctrl);
598 break;
599 case ATH12K_MHI_POWER_OFF:
600 mhi_power_down(ab_pci->mhi_ctrl, true);
601 ret = 0;
602 break;
603 case ATH12K_MHI_FORCE_POWER_OFF:
604 mhi_power_down(ab_pci->mhi_ctrl, false);
605 ret = 0;
606 break;
607 case ATH12K_MHI_SUSPEND:
608 ret = mhi_pm_suspend(ab_pci->mhi_ctrl);
609 break;
610 case ATH12K_MHI_RESUME:
611 ret = mhi_pm_resume(ab_pci->mhi_ctrl);
612 break;
613 case ATH12K_MHI_TRIGGER_RDDM:
614 ret = mhi_force_rddm_mode(ab_pci->mhi_ctrl);
615 break;
616 case ATH12K_MHI_RDDM_DONE:
617 break;
618 default:
619 ath12k_err(ab, "unhandled MHI state (%d)\n", mhi_state);
620 ret = -EINVAL;
621 }
622
623 if (ret)
624 goto out;
625
626 ath12k_mhi_set_state_bit(ab_pci, mhi_state);
627
628 return 0;
629
630out:
631 ath12k_err(ab, "failed to set mhi state: %s(%d)\n",
632 ath12k_mhi_state_to_str(mhi_state), mhi_state);
633 return ret;
634}
635
636int ath12k_mhi_start(struct ath12k_pci *ab_pci)
637{
638 int ret;
639
640 ab_pci->mhi_ctrl->timeout_ms = MHI_TIMEOUT_DEFAULT_MS;
641
642 ret = ath12k_mhi_set_state(ab_pci, ATH12K_MHI_INIT);
643 if (ret)
644 goto out;
645
646 ret = ath12k_mhi_set_state(ab_pci, ATH12K_MHI_POWER_ON);
647 if (ret)
648 goto out;
649
650 return 0;
651
652out:
653 return ret;
654}
655
656void ath12k_mhi_stop(struct ath12k_pci *ab_pci)
657{
658 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_POWER_OFF);
659 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_DEINIT);
660}
661
662void ath12k_mhi_suspend(struct ath12k_pci *ab_pci)
663{
664 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_SUSPEND);
665}
666
667void ath12k_mhi_resume(struct ath12k_pci *ab_pci)
668{
669 ath12k_mhi_set_state(ab_pci, ATH12K_MHI_RESUME);
670}