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1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
2/*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7#ifndef ATH12K_CORE_H
8#define ATH12K_CORE_H
9
10#include <linux/types.h>
11#include <linux/interrupt.h>
12#include <linux/irq.h>
13#include <linux/bitfield.h>
14#include <linux/dmi.h>
15#include <linux/ctype.h>
16#include <linux/firmware.h>
17#include "qmi.h"
18#include "htc.h"
19#include "wmi.h"
20#include "hal.h"
21#include "dp.h"
22#include "ce.h"
23#include "mac.h"
24#include "hw.h"
25#include "hal_rx.h"
26#include "reg.h"
27#include "dbring.h"
28#include "fw.h"
29
30#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
31
32#define ATH12K_TX_MGMT_NUM_PENDING_MAX 512
33
34#define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64
35
36/* Pending management packets threshold for dropping probe responses */
37#define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4)
38
39/* SMBIOS type containing Board Data File Name Extension */
40#define ATH12K_SMBIOS_BDF_EXT_TYPE 0xF8
41
42/* SMBIOS type structure length (excluding strings-set) */
43#define ATH12K_SMBIOS_BDF_EXT_LENGTH 0x9
44
45/* The magic used by QCA spec */
46#define ATH12K_SMBIOS_BDF_EXT_MAGIC "BDF_"
47
48#define ATH12K_INVALID_HW_MAC_ID 0xFF
49#define ATH12K_RX_RATE_TABLE_NUM 320
50#define ATH12K_RX_RATE_TABLE_11AX_NUM 576
51
52#define ATH12K_MON_TIMER_INTERVAL 10
53#define ATH12K_RESET_TIMEOUT_HZ (20 * HZ)
54#define ATH12K_RESET_MAX_FAIL_COUNT_FIRST 3
55#define ATH12K_RESET_MAX_FAIL_COUNT_FINAL 5
56#define ATH12K_RESET_FAIL_TIMEOUT_HZ (20 * HZ)
57#define ATH12K_RECONFIGURE_TIMEOUT_HZ (10 * HZ)
58#define ATH12K_RECOVER_START_TIMEOUT_HZ (20 * HZ)
59
60enum ath12k_bdf_search {
61 ATH12K_BDF_SEARCH_DEFAULT,
62 ATH12K_BDF_SEARCH_BUS_AND_BOARD,
63};
64
65enum wme_ac {
66 WME_AC_BE,
67 WME_AC_BK,
68 WME_AC_VI,
69 WME_AC_VO,
70 WME_NUM_AC
71};
72
73#define ATH12K_HT_MCS_MAX 7
74#define ATH12K_VHT_MCS_MAX 9
75#define ATH12K_HE_MCS_MAX 11
76
77enum ath12k_crypt_mode {
78 /* Only use hardware crypto engine */
79 ATH12K_CRYPT_MODE_HW,
80 /* Only use software crypto */
81 ATH12K_CRYPT_MODE_SW,
82};
83
84static inline enum wme_ac ath12k_tid_to_ac(u32 tid)
85{
86 return (((tid == 0) || (tid == 3)) ? WME_AC_BE :
87 ((tid == 1) || (tid == 2)) ? WME_AC_BK :
88 ((tid == 4) || (tid == 5)) ? WME_AC_VI :
89 WME_AC_VO);
90}
91
92enum ath12k_skb_flags {
93 ATH12K_SKB_HW_80211_ENCAP = BIT(0),
94 ATH12K_SKB_CIPHER_SET = BIT(1),
95};
96
97struct ath12k_skb_cb {
98 dma_addr_t paddr;
99 struct ath12k *ar;
100 struct ieee80211_vif *vif;
101 dma_addr_t paddr_ext_desc;
102 u32 cipher;
103 u8 flags;
104};
105
106struct ath12k_skb_rxcb {
107 dma_addr_t paddr;
108 bool is_first_msdu;
109 bool is_last_msdu;
110 bool is_continuation;
111 bool is_mcbc;
112 bool is_eapol;
113 struct hal_rx_desc *rx_desc;
114 u8 err_rel_src;
115 u8 err_code;
116 u8 mac_id;
117 u8 unmapped;
118 u8 is_frag;
119 u8 tid;
120 u16 peer_id;
121};
122
123enum ath12k_hw_rev {
124 ATH12K_HW_QCN9274_HW10,
125 ATH12K_HW_QCN9274_HW20,
126 ATH12K_HW_WCN7850_HW20
127};
128
129enum ath12k_firmware_mode {
130 /* the default mode, standard 802.11 functionality */
131 ATH12K_FIRMWARE_MODE_NORMAL,
132
133 /* factory tests etc */
134 ATH12K_FIRMWARE_MODE_FTM,
135};
136
137#define ATH12K_IRQ_NUM_MAX 57
138#define ATH12K_EXT_IRQ_NUM_MAX 16
139
140struct ath12k_ext_irq_grp {
141 struct ath12k_base *ab;
142 u32 irqs[ATH12K_EXT_IRQ_NUM_MAX];
143 u32 num_irq;
144 u32 grp_id;
145 u64 timestamp;
146 struct napi_struct napi;
147 struct net_device napi_ndev;
148};
149
150struct ath12k_smbios_bdf {
151 struct dmi_header hdr;
152 u32 padding;
153 u8 bdf_enabled;
154 u8 bdf_ext[];
155} __packed;
156
157#define HEHANDLE_CAP_PHYINFO_SIZE 3
158#define HECAP_PHYINFO_SIZE 9
159#define HECAP_MACINFO_SIZE 5
160#define HECAP_TXRX_MCS_NSS_SIZE 2
161#define HECAP_PPET16_PPET8_MAX_SIZE 25
162
163#define HE_PPET16_PPET8_SIZE 8
164
165/* 802.11ax PPE (PPDU packet Extension) threshold */
166struct he_ppe_threshold {
167 u32 numss_m1;
168 u32 ru_mask;
169 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE];
170};
171
172struct ath12k_he {
173 u8 hecap_macinfo[HECAP_MACINFO_SIZE];
174 u32 hecap_rxmcsnssmap;
175 u32 hecap_txmcsnssmap;
176 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE];
177 struct he_ppe_threshold hecap_ppet;
178 u32 heop_param;
179};
180
181#define MAX_RADIOS 3
182
183enum {
184 WMI_HOST_TP_SCALE_MAX = 0,
185 WMI_HOST_TP_SCALE_50 = 1,
186 WMI_HOST_TP_SCALE_25 = 2,
187 WMI_HOST_TP_SCALE_12 = 3,
188 WMI_HOST_TP_SCALE_MIN = 4,
189 WMI_HOST_TP_SCALE_SIZE = 5,
190};
191
192enum ath12k_scan_state {
193 ATH12K_SCAN_IDLE,
194 ATH12K_SCAN_STARTING,
195 ATH12K_SCAN_RUNNING,
196 ATH12K_SCAN_ABORTING,
197};
198
199enum ath12k_dev_flags {
200 ATH12K_CAC_RUNNING,
201 ATH12K_FLAG_CRASH_FLUSH,
202 ATH12K_FLAG_RAW_MODE,
203 ATH12K_FLAG_HW_CRYPTO_DISABLED,
204 ATH12K_FLAG_RECOVERY,
205 ATH12K_FLAG_UNREGISTERING,
206 ATH12K_FLAG_REGISTERED,
207 ATH12K_FLAG_QMI_FAIL,
208 ATH12K_FLAG_HTC_SUSPEND_COMPLETE,
209 ATH12K_FLAG_CE_IRQ_ENABLED,
210 ATH12K_FLAG_EXT_IRQ_ENABLED,
211};
212
213enum ath12k_monitor_flags {
214 ATH12K_FLAG_MONITOR_ENABLED,
215};
216
217struct ath12k_vif {
218 u32 vdev_id;
219 enum wmi_vdev_type vdev_type;
220 enum wmi_vdev_subtype vdev_subtype;
221 u32 beacon_interval;
222 u32 dtim_period;
223 u16 ast_hash;
224 u16 ast_idx;
225 u16 tcl_metadata;
226 u8 hal_addr_search_flags;
227 u8 search_type;
228
229 struct ath12k *ar;
230 struct ieee80211_vif *vif;
231
232 int bank_id;
233 u8 vdev_id_check_en;
234
235 struct wmi_wmm_params_all_arg wmm_params;
236 struct list_head list;
237 union {
238 struct {
239 u32 uapsd;
240 } sta;
241 struct {
242 /* 127 stations; wmi limit */
243 u8 tim_bitmap[16];
244 u8 tim_len;
245 u32 ssid_len;
246 u8 ssid[IEEE80211_MAX_SSID_LEN];
247 bool hidden_ssid;
248 /* P2P_IE with NoA attribute for P2P_GO case */
249 u32 noa_len;
250 u8 *noa_data;
251 } ap;
252 } u;
253
254 bool is_started;
255 bool is_up;
256 u32 aid;
257 u8 bssid[ETH_ALEN];
258 struct cfg80211_bitrate_mask bitrate_mask;
259 int num_legacy_stations;
260 int rtscts_prot_mode;
261 int txpower;
262 bool rsnie_present;
263 bool wpaie_present;
264 struct ieee80211_chanctx_conf chanctx;
265 u32 key_cipher;
266 u8 tx_encap_type;
267 u8 vdev_stats_id;
268 u32 punct_bitmap;
269 bool ps;
270};
271
272struct ath12k_vif_iter {
273 u32 vdev_id;
274 struct ath12k_vif *arvif;
275};
276
277#define HAL_AST_IDX_INVALID 0xFFFF
278#define HAL_RX_MAX_MCS 12
279#define HAL_RX_MAX_MCS_HT 31
280#define HAL_RX_MAX_MCS_VHT 9
281#define HAL_RX_MAX_MCS_HE 11
282#define HAL_RX_MAX_NSS 8
283#define HAL_RX_MAX_NUM_LEGACY_RATES 12
284#define ATH12K_RX_RATE_TABLE_11AX_NUM 576
285#define ATH12K_RX_RATE_TABLE_NUM 320
286
287struct ath12k_rx_peer_rate_stats {
288 u64 ht_mcs_count[HAL_RX_MAX_MCS_HT + 1];
289 u64 vht_mcs_count[HAL_RX_MAX_MCS_VHT + 1];
290 u64 he_mcs_count[HAL_RX_MAX_MCS_HE + 1];
291 u64 nss_count[HAL_RX_MAX_NSS];
292 u64 bw_count[HAL_RX_BW_MAX];
293 u64 gi_count[HAL_RX_GI_MAX];
294 u64 legacy_count[HAL_RX_MAX_NUM_LEGACY_RATES];
295 u64 rx_rate[ATH12K_RX_RATE_TABLE_11AX_NUM];
296};
297
298struct ath12k_rx_peer_stats {
299 u64 num_msdu;
300 u64 num_mpdu_fcs_ok;
301 u64 num_mpdu_fcs_err;
302 u64 tcp_msdu_count;
303 u64 udp_msdu_count;
304 u64 other_msdu_count;
305 u64 ampdu_msdu_count;
306 u64 non_ampdu_msdu_count;
307 u64 stbc_count;
308 u64 beamformed_count;
309 u64 mcs_count[HAL_RX_MAX_MCS + 1];
310 u64 nss_count[HAL_RX_MAX_NSS];
311 u64 bw_count[HAL_RX_BW_MAX];
312 u64 gi_count[HAL_RX_GI_MAX];
313 u64 coding_count[HAL_RX_SU_MU_CODING_MAX];
314 u64 tid_count[IEEE80211_NUM_TIDS + 1];
315 u64 pream_cnt[HAL_RX_PREAMBLE_MAX];
316 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX];
317 u64 rx_duration;
318 u64 dcm_count;
319 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX];
320 struct ath12k_rx_peer_rate_stats pkt_stats;
321 struct ath12k_rx_peer_rate_stats byte_stats;
322};
323
324#define ATH12K_HE_MCS_NUM 12
325#define ATH12K_VHT_MCS_NUM 10
326#define ATH12K_BW_NUM 5
327#define ATH12K_NSS_NUM 4
328#define ATH12K_LEGACY_NUM 12
329#define ATH12K_GI_NUM 4
330#define ATH12K_HT_MCS_NUM 32
331
332enum ath12k_pkt_rx_err {
333 ATH12K_PKT_RX_ERR_FCS,
334 ATH12K_PKT_RX_ERR_TKIP,
335 ATH12K_PKT_RX_ERR_CRYPT,
336 ATH12K_PKT_RX_ERR_PEER_IDX_INVAL,
337 ATH12K_PKT_RX_ERR_MAX,
338};
339
340enum ath12k_ampdu_subfrm_num {
341 ATH12K_AMPDU_SUBFRM_NUM_10,
342 ATH12K_AMPDU_SUBFRM_NUM_20,
343 ATH12K_AMPDU_SUBFRM_NUM_30,
344 ATH12K_AMPDU_SUBFRM_NUM_40,
345 ATH12K_AMPDU_SUBFRM_NUM_50,
346 ATH12K_AMPDU_SUBFRM_NUM_60,
347 ATH12K_AMPDU_SUBFRM_NUM_MORE,
348 ATH12K_AMPDU_SUBFRM_NUM_MAX,
349};
350
351enum ath12k_amsdu_subfrm_num {
352 ATH12K_AMSDU_SUBFRM_NUM_1,
353 ATH12K_AMSDU_SUBFRM_NUM_2,
354 ATH12K_AMSDU_SUBFRM_NUM_3,
355 ATH12K_AMSDU_SUBFRM_NUM_4,
356 ATH12K_AMSDU_SUBFRM_NUM_MORE,
357 ATH12K_AMSDU_SUBFRM_NUM_MAX,
358};
359
360enum ath12k_counter_type {
361 ATH12K_COUNTER_TYPE_BYTES,
362 ATH12K_COUNTER_TYPE_PKTS,
363 ATH12K_COUNTER_TYPE_MAX,
364};
365
366enum ath12k_stats_type {
367 ATH12K_STATS_TYPE_SUCC,
368 ATH12K_STATS_TYPE_FAIL,
369 ATH12K_STATS_TYPE_RETRY,
370 ATH12K_STATS_TYPE_AMPDU,
371 ATH12K_STATS_TYPE_MAX,
372};
373
374struct ath12k_htt_data_stats {
375 u64 legacy[ATH12K_COUNTER_TYPE_MAX][ATH12K_LEGACY_NUM];
376 u64 ht[ATH12K_COUNTER_TYPE_MAX][ATH12K_HT_MCS_NUM];
377 u64 vht[ATH12K_COUNTER_TYPE_MAX][ATH12K_VHT_MCS_NUM];
378 u64 he[ATH12K_COUNTER_TYPE_MAX][ATH12K_HE_MCS_NUM];
379 u64 bw[ATH12K_COUNTER_TYPE_MAX][ATH12K_BW_NUM];
380 u64 nss[ATH12K_COUNTER_TYPE_MAX][ATH12K_NSS_NUM];
381 u64 gi[ATH12K_COUNTER_TYPE_MAX][ATH12K_GI_NUM];
382 u64 transmit_type[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RECEPTION_TYPE_MAX];
383 u64 ru_loc[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RU_ALLOC_TYPE_MAX];
384};
385
386struct ath12k_htt_tx_stats {
387 struct ath12k_htt_data_stats stats[ATH12K_STATS_TYPE_MAX];
388 u64 tx_duration;
389 u64 ba_fails;
390 u64 ack_fails;
391 u16 ru_start;
392 u16 ru_tones;
393 u32 mu_group[MAX_MU_GROUP_ID];
394};
395
396struct ath12k_per_ppdu_tx_stats {
397 u16 succ_pkts;
398 u16 failed_pkts;
399 u16 retry_pkts;
400 u32 succ_bytes;
401 u32 failed_bytes;
402 u32 retry_bytes;
403};
404
405struct ath12k_wbm_tx_stats {
406 u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX];
407};
408
409struct ath12k_sta {
410 struct ath12k_vif *arvif;
411
412 /* the following are protected by ar->data_lock */
413 u32 changed; /* IEEE80211_RC_* */
414 u32 bw;
415 u32 nss;
416 u32 smps;
417 enum hal_pn_type pn_type;
418
419 struct work_struct update_wk;
420 struct rate_info txrate;
421 struct rate_info last_txrate;
422 u64 rx_duration;
423 u64 tx_duration;
424 u8 rssi_comb;
425 struct ath12k_rx_peer_stats *rx_stats;
426 struct ath12k_wbm_tx_stats *wbm_tx_stats;
427 u32 bw_prev;
428};
429
430#define ATH12K_MIN_5G_FREQ 4150
431#define ATH12K_MIN_6G_FREQ 5925
432#define ATH12K_MAX_6G_FREQ 7115
433#define ATH12K_NUM_CHANS 100
434#define ATH12K_MAX_5G_CHAN 173
435
436enum ath12k_state {
437 ATH12K_STATE_OFF,
438 ATH12K_STATE_ON,
439 ATH12K_STATE_RESTARTING,
440 ATH12K_STATE_RESTARTED,
441 ATH12K_STATE_WEDGED,
442 /* Add other states as required */
443};
444
445/* Antenna noise floor */
446#define ATH12K_DEFAULT_NOISE_FLOOR -95
447
448struct ath12k_fw_stats {
449 u32 pdev_id;
450 u32 stats_id;
451 struct list_head pdevs;
452 struct list_head vdevs;
453 struct list_head bcn;
454};
455
456struct ath12k_per_peer_tx_stats {
457 u32 succ_bytes;
458 u32 retry_bytes;
459 u32 failed_bytes;
460 u32 duration;
461 u16 succ_pkts;
462 u16 retry_pkts;
463 u16 failed_pkts;
464 u16 ru_start;
465 u16 ru_tones;
466 u8 ba_fails;
467 u8 ppdu_type;
468 u32 mu_grpid;
469 u32 mu_pos;
470 bool is_ampdu;
471};
472
473#define ATH12K_FLUSH_TIMEOUT (5 * HZ)
474#define ATH12K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ)
475
476struct ath12k {
477 struct ath12k_base *ab;
478 struct ath12k_pdev *pdev;
479 struct ath12k_hw *ah;
480 struct ath12k_wmi_pdev *wmi;
481 struct ath12k_pdev_dp dp;
482 u8 mac_addr[ETH_ALEN];
483 u32 ht_cap_info;
484 u32 vht_cap_info;
485 struct ath12k_he ar_he;
486 enum ath12k_state state;
487 bool supports_6ghz;
488 struct {
489 struct completion started;
490 struct completion completed;
491 struct completion on_channel;
492 struct delayed_work timeout;
493 enum ath12k_scan_state state;
494 bool is_roc;
495 int vdev_id;
496 int roc_freq;
497 bool roc_notify;
498 } scan;
499
500 struct {
501 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
502 struct ieee80211_sband_iftype_data
503 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
504 } mac;
505
506 unsigned long dev_flags;
507 unsigned int filter_flags;
508 unsigned long monitor_flags;
509 u32 min_tx_power;
510 u32 max_tx_power;
511 u32 txpower_limit_2g;
512 u32 txpower_limit_5g;
513 u32 txpower_scale;
514 u32 power_scale;
515 u32 chan_tx_pwr;
516 u32 num_stations;
517 u32 max_num_stations;
518 bool monitor_present;
519 /* To synchronize concurrent synchronous mac80211 callback operations,
520 * concurrent debugfs configuration and concurrent FW statistics events.
521 */
522 struct mutex conf_mutex;
523 /* protects the radio specific data like debug stats, ppdu_stats_info stats,
524 * vdev_stop_status info, scan data, ath12k_sta info, ath12k_vif info,
525 * channel context data, survey info, test mode data.
526 */
527 spinlock_t data_lock;
528
529 struct list_head arvifs;
530 /* should never be NULL; needed for regular htt rx */
531 struct ieee80211_channel *rx_channel;
532
533 /* valid during scan; needed for mgmt rx during scan */
534 struct ieee80211_channel *scan_channel;
535
536 u8 cfg_tx_chainmask;
537 u8 cfg_rx_chainmask;
538 u8 num_rx_chains;
539 u8 num_tx_chains;
540 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */
541 u8 pdev_idx;
542 u8 lmac_id;
543 u8 hw_link_id;
544
545 struct completion peer_assoc_done;
546 struct completion peer_delete_done;
547
548 int install_key_status;
549 struct completion install_key_done;
550
551 int last_wmi_vdev_start_status;
552 struct completion vdev_setup_done;
553 struct completion vdev_delete_done;
554
555 int num_peers;
556 int max_num_peers;
557 u32 num_started_vdevs;
558 u32 num_created_vdevs;
559 unsigned long long allocated_vdev_map;
560
561 struct idr txmgmt_idr;
562 /* protects txmgmt_idr data */
563 spinlock_t txmgmt_idr_lock;
564 atomic_t num_pending_mgmt_tx;
565 wait_queue_head_t txmgmt_empty_waitq;
566
567 /* cycle count is reported twice for each visited channel during scan.
568 * access protected by data_lock
569 */
570 u32 survey_last_rx_clear_count;
571 u32 survey_last_cycle_count;
572
573 /* Channel info events are expected to come in pairs without and with
574 * COMPLETE flag set respectively for each channel visit during scan.
575 *
576 * However there are deviations from this rule. This flag is used to
577 * avoid reporting garbage data.
578 */
579 bool ch_info_can_report_survey;
580 struct survey_info survey[ATH12K_NUM_CHANS];
581 struct completion bss_survey_done;
582
583 struct work_struct regd_update_work;
584
585 struct work_struct wmi_mgmt_tx_work;
586 struct sk_buff_head wmi_mgmt_tx_queue;
587
588 struct ath12k_per_peer_tx_stats peer_tx_stats;
589 struct list_head ppdu_stats_info;
590 u32 ppdu_stat_list_depth;
591
592 struct ath12k_per_peer_tx_stats cached_stats;
593 u32 last_ppdu_id;
594 u32 cached_ppdu_id;
595
596 bool dfs_block_radar_events;
597 bool monitor_conf_enabled;
598 bool monitor_vdev_created;
599 bool monitor_started;
600 int monitor_vdev_id;
601};
602
603struct ath12k_hw {
604 struct ieee80211_hw *hw;
605
606 u8 num_radio;
607 struct ath12k radio[] __aligned(sizeof(void *));
608};
609
610struct ath12k_band_cap {
611 u32 phy_id;
612 u32 max_bw_supported;
613 u32 ht_cap_info;
614 u32 he_cap_info[2];
615 u32 he_mcs;
616 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE];
617 struct ath12k_wmi_ppe_threshold_arg he_ppet;
618 u16 he_6ghz_capa;
619 u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE];
620 u32 eht_cap_phy_info[WMI_MAX_EHTCAP_PHY_SIZE];
621 u32 eht_mcs_20_only;
622 u32 eht_mcs_80;
623 u32 eht_mcs_160;
624 u32 eht_mcs_320;
625 struct ath12k_wmi_ppe_threshold_arg eht_ppet;
626 u32 eht_cap_info_internal;
627};
628
629struct ath12k_pdev_cap {
630 u32 supported_bands;
631 u32 ampdu_density;
632 u32 vht_cap;
633 u32 vht_mcs;
634 u32 he_mcs;
635 u32 tx_chain_mask;
636 u32 rx_chain_mask;
637 u32 tx_chain_mask_shift;
638 u32 rx_chain_mask_shift;
639 struct ath12k_band_cap band[NUM_NL80211_BANDS];
640};
641
642struct mlo_timestamp {
643 u32 info;
644 u32 sync_timestamp_lo_us;
645 u32 sync_timestamp_hi_us;
646 u32 mlo_offset_lo;
647 u32 mlo_offset_hi;
648 u32 mlo_offset_clks;
649 u32 mlo_comp_clks;
650 u32 mlo_comp_timer;
651};
652
653struct ath12k_pdev {
654 struct ath12k *ar;
655 u32 pdev_id;
656 struct ath12k_pdev_cap cap;
657 u8 mac_addr[ETH_ALEN];
658 struct mlo_timestamp timestamp;
659};
660
661struct ath12k_fw_pdev {
662 u32 pdev_id;
663 u32 phy_id;
664 u32 supported_bands;
665};
666
667struct ath12k_board_data {
668 const struct firmware *fw;
669 const void *data;
670 size_t len;
671};
672
673struct ath12k_soc_dp_tx_err_stats {
674 /* TCL Ring Descriptor unavailable */
675 u32 desc_na[DP_TCL_NUM_RING_MAX];
676 /* Other failures during dp_tx due to mem allocation failure
677 * idr unavailable etc.
678 */
679 atomic_t misc_fail;
680};
681
682struct ath12k_soc_dp_stats {
683 u32 err_ring_pkts;
684 u32 invalid_rbm;
685 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX];
686 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX];
687 u32 hal_reo_error[DP_REO_DST_RING_MAX];
688 struct ath12k_soc_dp_tx_err_stats tx_err;
689};
690
691/* Master structure to hold the hw data which may be used in core module */
692struct ath12k_base {
693 enum ath12k_hw_rev hw_rev;
694 struct platform_device *pdev;
695 struct device *dev;
696 struct ath12k_qmi qmi;
697 struct ath12k_wmi_base wmi_ab;
698 struct completion fw_ready;
699 int num_radios;
700 /* HW channel counters frequency value in hertz common to all MACs */
701 u32 cc_freq_hz;
702
703 struct ath12k_htc htc;
704
705 struct ath12k_dp dp;
706
707 void __iomem *mem;
708 unsigned long mem_len;
709
710 struct {
711 enum ath12k_bus bus;
712 const struct ath12k_hif_ops *ops;
713 } hif;
714
715 struct ath12k_ce ce;
716 struct timer_list rx_replenish_retry;
717 struct ath12k_hal hal;
718 /* To synchronize core_start/core_stop */
719 struct mutex core_lock;
720 /* Protects data like peers */
721 spinlock_t base_lock;
722
723 /* Single pdev device (struct ath12k_hw_params::single_pdev_only):
724 *
725 * Firmware maintains data for all bands but advertises a single
726 * phy to the host which is stored as a single element in this
727 * array.
728 *
729 * Other devices:
730 *
731 * This array will contain as many elements as the number of
732 * radios.
733 */
734 struct ath12k_pdev pdevs[MAX_RADIOS];
735
736 /* struct ath12k_hw_params::single_pdev_only devices use this to
737 * store phy specific data
738 */
739 struct ath12k_fw_pdev fw_pdev[MAX_RADIOS];
740 u8 fw_pdev_count;
741
742 struct ath12k_pdev __rcu *pdevs_active[MAX_RADIOS];
743
744 /* Holds information of wiphy (hw) registration.
745 *
746 * In Multi/Single Link Operation case, all pdevs are registered as
747 * a single wiphy. In other (legacy/Non-MLO) cases, each pdev is
748 * registered as separate wiphys.
749 */
750 struct ath12k_hw *ah[MAX_RADIOS];
751 u8 num_hw;
752
753 struct ath12k_wmi_hal_reg_capabilities_ext_arg hal_reg_cap[MAX_RADIOS];
754 unsigned long long free_vdev_map;
755 unsigned long long free_vdev_stats_id_map;
756 struct list_head peers;
757 wait_queue_head_t peer_mapping_wq;
758 u8 mac_addr[ETH_ALEN];
759 bool wmi_ready;
760 u32 wlan_init_status;
761 int irq_num[ATH12K_IRQ_NUM_MAX];
762 struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX];
763 struct napi_struct *napi;
764 struct ath12k_wmi_target_cap_arg target_caps;
765 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE];
766 bool pdevs_macaddr_valid;
767
768 const struct ath12k_hw_params *hw_params;
769
770 const struct firmware *cal_file;
771
772 /* Below regd's are protected by ab->data_lock */
773 /* This is the regd set for every radio
774 * by the firmware during initialization
775 */
776 struct ieee80211_regdomain *default_regd[MAX_RADIOS];
777 /* This regd is set during dynamic country setting
778 * This may or may not be used during the runtime
779 */
780 struct ieee80211_regdomain *new_regd[MAX_RADIOS];
781
782 /* Current DFS Regulatory */
783 enum ath12k_dfs_region dfs_region;
784 struct ath12k_soc_dp_stats soc_stats;
785
786 unsigned long dev_flags;
787 struct completion driver_recovery;
788 struct workqueue_struct *workqueue;
789 struct work_struct restart_work;
790 struct workqueue_struct *workqueue_aux;
791 struct work_struct reset_work;
792 atomic_t reset_count;
793 atomic_t recovery_count;
794 atomic_t recovery_start_count;
795 bool is_reset;
796 struct completion reset_complete;
797 struct completion reconfigure_complete;
798 struct completion recovery_start;
799 /* continuous recovery fail count */
800 atomic_t fail_cont_count;
801 unsigned long reset_fail_timeout;
802 struct {
803 /* protected by data_lock */
804 u32 fw_crash_counter;
805 } stats;
806 u32 pktlog_defs_checksum;
807
808 struct ath12k_dbring_cap *db_caps;
809 u32 num_db_cap;
810
811 struct timer_list mon_reap_timer;
812
813 struct completion htc_suspend;
814
815 u64 fw_soc_drop_count;
816 bool static_window_map;
817
818 struct work_struct rfkill_work;
819 /* true means radio is on */
820 bool rfkill_radio_on;
821
822 struct {
823 enum ath12k_bdf_search bdf_search;
824 u32 vendor;
825 u32 device;
826 u32 subsystem_vendor;
827 u32 subsystem_device;
828 } id;
829
830 struct {
831 u32 api_version;
832
833 const struct firmware *fw;
834 const u8 *amss_data;
835 size_t amss_len;
836 const u8 *amss_dualmac_data;
837 size_t amss_dualmac_len;
838 const u8 *m3_data;
839 size_t m3_len;
840
841 DECLARE_BITMAP(fw_features, ATH12K_FW_FEATURE_COUNT);
842 } fw;
843
844 const struct hal_rx_ops *hal_rx_ops;
845
846 /* slo_capable denotes if the single/multi link operation
847 * is supported within the same chip (SoC).
848 */
849 bool slo_capable;
850
851 /* must be last */
852 u8 drv_priv[] __aligned(sizeof(void *));
853};
854
855struct ath12k_pdev_map {
856 struct ath12k_base *ab;
857 u8 pdev_idx;
858};
859
860int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab);
861int ath12k_core_pre_init(struct ath12k_base *ab);
862int ath12k_core_init(struct ath12k_base *ath12k);
863void ath12k_core_deinit(struct ath12k_base *ath12k);
864struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size,
865 enum ath12k_bus bus);
866void ath12k_core_free(struct ath12k_base *ath12k);
867int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab,
868 struct ath12k_board_data *bd,
869 char *filename);
870int ath12k_core_fetch_bdf(struct ath12k_base *ath12k,
871 struct ath12k_board_data *bd);
872void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd);
873int ath12k_core_fetch_regdb(struct ath12k_base *ab, struct ath12k_board_data *bd);
874int ath12k_core_check_dt(struct ath12k_base *ath12k);
875int ath12k_core_check_smbios(struct ath12k_base *ab);
876void ath12k_core_halt(struct ath12k *ar);
877int ath12k_core_resume(struct ath12k_base *ab);
878int ath12k_core_suspend(struct ath12k_base *ab);
879
880const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab,
881 const char *filename);
882u32 ath12k_core_get_max_station_per_radio(struct ath12k_base *ab);
883u32 ath12k_core_get_max_peers_per_radio(struct ath12k_base *ab);
884u32 ath12k_core_get_max_num_tids(struct ath12k_base *ab);
885
886static inline const char *ath12k_scan_state_str(enum ath12k_scan_state state)
887{
888 switch (state) {
889 case ATH12K_SCAN_IDLE:
890 return "idle";
891 case ATH12K_SCAN_STARTING:
892 return "starting";
893 case ATH12K_SCAN_RUNNING:
894 return "running";
895 case ATH12K_SCAN_ABORTING:
896 return "aborting";
897 }
898
899 return "unknown";
900}
901
902static inline struct ath12k_skb_cb *ATH12K_SKB_CB(struct sk_buff *skb)
903{
904 BUILD_BUG_ON(sizeof(struct ath12k_skb_cb) >
905 IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
906 return (struct ath12k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
907}
908
909static inline struct ath12k_skb_rxcb *ATH12K_SKB_RXCB(struct sk_buff *skb)
910{
911 BUILD_BUG_ON(sizeof(struct ath12k_skb_rxcb) > sizeof(skb->cb));
912 return (struct ath12k_skb_rxcb *)skb->cb;
913}
914
915static inline struct ath12k_vif *ath12k_vif_to_arvif(struct ieee80211_vif *vif)
916{
917 return (struct ath12k_vif *)vif->drv_priv;
918}
919
920static inline struct ath12k_sta *ath12k_sta_to_arsta(struct ieee80211_sta *sta)
921{
922 return (struct ath12k_sta *)sta->drv_priv;
923}
924
925static inline struct ath12k *ath12k_ab_to_ar(struct ath12k_base *ab,
926 int mac_id)
927{
928 return ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar;
929}
930
931static inline void ath12k_core_create_firmware_path(struct ath12k_base *ab,
932 const char *filename,
933 void *buf, size_t buf_len)
934{
935 snprintf(buf, buf_len, "%s/%s/%s", ATH12K_FW_DIR,
936 ab->hw_params->fw.dir, filename);
937}
938
939static inline const char *ath12k_bus_str(enum ath12k_bus bus)
940{
941 switch (bus) {
942 case ATH12K_BUS_PCI:
943 return "pci";
944 }
945
946 return "unknown";
947}
948
949static inline struct ath12k_hw *ath12k_hw_to_ah(struct ieee80211_hw *hw)
950{
951 return hw->priv;
952}
953
954static inline struct ath12k *ath12k_ah_to_ar(struct ath12k_hw *ah)
955{
956 return ah->radio;
957}
958
959static inline struct ieee80211_hw *ath12k_ar_to_hw(struct ath12k *ar)
960{
961 return ar->ah->hw;
962}
963#endif /* _CORE_H_ */