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1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
2/*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7#ifndef ATH11K_WMI_H
8#define ATH11K_WMI_H
9
10#include <net/mac80211.h>
11#include "htc.h"
12
13struct ath11k_base;
14struct ath11k;
15struct ath11k_fw_stats;
16struct ath11k_fw_dbglog;
17struct ath11k_vif;
18
19#define PSOC_HOST_MAX_NUM_SS (8)
20
21/* defines to set Packet extension values which can be 0 us, 8 usec or 16 usec */
22#define MAX_HE_NSS 8
23#define MAX_HE_MODULATION 8
24#define MAX_HE_RU 4
25#define HE_MODULATION_NONE 7
26#define HE_PET_0_USEC 0
27#define HE_PET_8_USEC 1
28#define HE_PET_16_USEC 2
29
30#define WMI_MAX_CHAINS 8
31
32#define WMI_MAX_NUM_SS MAX_HE_NSS
33#define WMI_MAX_NUM_RU MAX_HE_RU
34
35#define WMI_TLV_CMD(grp_id) (((grp_id) << 12) | 0x1)
36#define WMI_TLV_EV(grp_id) (((grp_id) << 12) | 0x1)
37#define WMI_TLV_CMD_UNSUPPORTED 0
38#define WMI_TLV_PDEV_PARAM_UNSUPPORTED 0
39#define WMI_TLV_VDEV_PARAM_UNSUPPORTED 0
40
41struct wmi_cmd_hdr {
42 u32 cmd_id;
43} __packed;
44
45struct wmi_tlv {
46 u32 header;
47 u8 value[];
48} __packed;
49
50#define WMI_TLV_LEN GENMASK(15, 0)
51#define WMI_TLV_TAG GENMASK(31, 16)
52#define TLV_HDR_SIZE sizeof_field(struct wmi_tlv, header)
53
54#define WMI_CMD_HDR_CMD_ID GENMASK(23, 0)
55#define WMI_MAX_MEM_REQS 32
56#define ATH11K_MAX_HW_LISTEN_INTERVAL 5
57
58#define WLAN_SCAN_MAX_HINT_S_SSID 10
59#define WLAN_SCAN_MAX_HINT_BSSID 10
60#define MAX_RNR_BSS 5
61
62#define WLAN_SCAN_MAX_HINT_S_SSID 10
63#define WLAN_SCAN_MAX_HINT_BSSID 10
64#define MAX_RNR_BSS 5
65
66#define WLAN_SCAN_PARAMS_MAX_SSID 16
67#define WLAN_SCAN_PARAMS_MAX_BSSID 4
68#define WLAN_SCAN_PARAMS_MAX_IE_LEN 256
69
70#define WMI_APPEND_TO_EXISTING_CHAN_LIST_FLAG 1
71
72#define MAX_WMI_UTF_LEN 252
73#define WMI_BA_MODE_BUFFER_SIZE_256 3
74/*
75 * HW mode config type replicated from FW header
76 * @WMI_HOST_HW_MODE_SINGLE: Only one PHY is active.
77 * @WMI_HOST_HW_MODE_DBS: Both PHYs are active in different bands,
78 * one in 2G and another in 5G.
79 * @WMI_HOST_HW_MODE_SBS_PASSIVE: Both PHYs are in passive mode (only rx) in
80 * same band; no tx allowed.
81 * @WMI_HOST_HW_MODE_SBS: Both PHYs are active in the same band.
82 * Support for both PHYs within one band is planned
83 * for 5G only(as indicated in WMI_MAC_PHY_CAPABILITIES),
84 * but could be extended to other bands in the future.
85 * The separation of the band between the two PHYs needs
86 * to be communicated separately.
87 * @WMI_HOST_HW_MODE_DBS_SBS: 3 PHYs, with 2 on the same band doing SBS
88 * as in WMI_HW_MODE_SBS, and 3rd on the other band
89 * @WMI_HOST_HW_MODE_DBS_OR_SBS: Two PHY with one PHY capabale of both 2G and
90 * 5G. It can support SBS (5G + 5G) OR DBS (5G + 2G).
91 * @WMI_HOST_HW_MODE_MAX: Max hw_mode_id. Used to indicate invalid mode.
92 */
93enum wmi_host_hw_mode_config_type {
94 WMI_HOST_HW_MODE_SINGLE = 0,
95 WMI_HOST_HW_MODE_DBS = 1,
96 WMI_HOST_HW_MODE_SBS_PASSIVE = 2,
97 WMI_HOST_HW_MODE_SBS = 3,
98 WMI_HOST_HW_MODE_DBS_SBS = 4,
99 WMI_HOST_HW_MODE_DBS_OR_SBS = 5,
100
101 /* keep last */
102 WMI_HOST_HW_MODE_MAX
103};
104
105/* HW mode priority values used to detect the preferred HW mode
106 * on the available modes.
107 */
108enum wmi_host_hw_mode_priority {
109 WMI_HOST_HW_MODE_DBS_SBS_PRI,
110 WMI_HOST_HW_MODE_DBS_PRI,
111 WMI_HOST_HW_MODE_DBS_OR_SBS_PRI,
112 WMI_HOST_HW_MODE_SBS_PRI,
113 WMI_HOST_HW_MODE_SBS_PASSIVE_PRI,
114 WMI_HOST_HW_MODE_SINGLE_PRI,
115
116 /* keep last the lowest priority */
117 WMI_HOST_HW_MODE_MAX_PRI
118};
119
120enum WMI_HOST_WLAN_BAND {
121 WMI_HOST_WLAN_2G_CAP = 0x1,
122 WMI_HOST_WLAN_5G_CAP = 0x2,
123 WMI_HOST_WLAN_2G_5G_CAP = WMI_HOST_WLAN_2G_CAP | WMI_HOST_WLAN_5G_CAP,
124};
125
126/* Parameters used for WMI_VDEV_PARAM_AUTORATE_MISC_CFG command.
127 * Used only for HE auto rate mode.
128 */
129enum {
130 /* HE LTF related configuration */
131 WMI_HE_AUTORATE_LTF_1X = BIT(0),
132 WMI_HE_AUTORATE_LTF_2X = BIT(1),
133 WMI_HE_AUTORATE_LTF_4X = BIT(2),
134
135 /* HE GI related configuration */
136 WMI_AUTORATE_400NS_GI = BIT(8),
137 WMI_AUTORATE_800NS_GI = BIT(9),
138 WMI_AUTORATE_1600NS_GI = BIT(10),
139 WMI_AUTORATE_3200NS_GI = BIT(11),
140};
141
142enum {
143 WMI_HOST_VDEV_FLAGS_NON_MBSSID_AP = 0x00000001,
144 WMI_HOST_VDEV_FLAGS_TRANSMIT_AP = 0x00000002,
145 WMI_HOST_VDEV_FLAGS_NON_TRANSMIT_AP = 0x00000004,
146 WMI_HOST_VDEV_FLAGS_EMA_MODE = 0x00000008,
147 WMI_HOST_VDEV_FLAGS_SCAN_MODE_VAP = 0x00000010,
148};
149
150/*
151 * wmi command groups.
152 */
153enum wmi_cmd_group {
154 /* 0 to 2 are reserved */
155 WMI_GRP_START = 0x3,
156 WMI_GRP_SCAN = WMI_GRP_START,
157 WMI_GRP_PDEV = 0x4,
158 WMI_GRP_VDEV = 0x5,
159 WMI_GRP_PEER = 0x6,
160 WMI_GRP_MGMT = 0x7,
161 WMI_GRP_BA_NEG = 0x8,
162 WMI_GRP_STA_PS = 0x9,
163 WMI_GRP_DFS = 0xa,
164 WMI_GRP_ROAM = 0xb,
165 WMI_GRP_OFL_SCAN = 0xc,
166 WMI_GRP_P2P = 0xd,
167 WMI_GRP_AP_PS = 0xe,
168 WMI_GRP_RATE_CTRL = 0xf,
169 WMI_GRP_PROFILE = 0x10,
170 WMI_GRP_SUSPEND = 0x11,
171 WMI_GRP_BCN_FILTER = 0x12,
172 WMI_GRP_WOW = 0x13,
173 WMI_GRP_RTT = 0x14,
174 WMI_GRP_SPECTRAL = 0x15,
175 WMI_GRP_STATS = 0x16,
176 WMI_GRP_ARP_NS_OFL = 0x17,
177 WMI_GRP_NLO_OFL = 0x18,
178 WMI_GRP_GTK_OFL = 0x19,
179 WMI_GRP_CSA_OFL = 0x1a,
180 WMI_GRP_CHATTER = 0x1b,
181 WMI_GRP_TID_ADDBA = 0x1c,
182 WMI_GRP_MISC = 0x1d,
183 WMI_GRP_GPIO = 0x1e,
184 WMI_GRP_FWTEST = 0x1f,
185 WMI_GRP_TDLS = 0x20,
186 WMI_GRP_RESMGR = 0x21,
187 WMI_GRP_STA_SMPS = 0x22,
188 WMI_GRP_WLAN_HB = 0x23,
189 WMI_GRP_RMC = 0x24,
190 WMI_GRP_MHF_OFL = 0x25,
191 WMI_GRP_LOCATION_SCAN = 0x26,
192 WMI_GRP_OEM = 0x27,
193 WMI_GRP_NAN = 0x28,
194 WMI_GRP_COEX = 0x29,
195 WMI_GRP_OBSS_OFL = 0x2a,
196 WMI_GRP_LPI = 0x2b,
197 WMI_GRP_EXTSCAN = 0x2c,
198 WMI_GRP_DHCP_OFL = 0x2d,
199 WMI_GRP_IPA = 0x2e,
200 WMI_GRP_MDNS_OFL = 0x2f,
201 WMI_GRP_SAP_OFL = 0x30,
202 WMI_GRP_OCB = 0x31,
203 WMI_GRP_SOC = 0x32,
204 WMI_GRP_PKT_FILTER = 0x33,
205 WMI_GRP_MAWC = 0x34,
206 WMI_GRP_PMF_OFFLOAD = 0x35,
207 WMI_GRP_BPF_OFFLOAD = 0x36,
208 WMI_GRP_NAN_DATA = 0x37,
209 WMI_GRP_PROTOTYPE = 0x38,
210 WMI_GRP_MONITOR = 0x39,
211 WMI_GRP_REGULATORY = 0x3a,
212 WMI_GRP_HW_DATA_FILTER = 0x3b,
213 WMI_GRP_WLM = 0x3c,
214 WMI_GRP_11K_OFFLOAD = 0x3d,
215 WMI_GRP_TWT = 0x3e,
216 WMI_GRP_MOTION_DET = 0x3f,
217 WMI_GRP_SPATIAL_REUSE = 0x40,
218};
219
220#define WMI_CMD_GRP(grp_id) (((grp_id) << 12) | 0x1)
221#define WMI_EVT_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1)
222
223#define WMI_CMD_UNSUPPORTED 0
224
225enum wmi_tlv_cmd_id {
226 WMI_INIT_CMDID = 0x1,
227 WMI_START_SCAN_CMDID = WMI_TLV_CMD(WMI_GRP_SCAN),
228 WMI_STOP_SCAN_CMDID,
229 WMI_SCAN_CHAN_LIST_CMDID,
230 WMI_SCAN_SCH_PRIO_TBL_CMDID,
231 WMI_SCAN_UPDATE_REQUEST_CMDID,
232 WMI_SCAN_PROB_REQ_OUI_CMDID,
233 WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID,
234 WMI_PDEV_SET_REGDOMAIN_CMDID = WMI_TLV_CMD(WMI_GRP_PDEV),
235 WMI_PDEV_SET_CHANNEL_CMDID,
236 WMI_PDEV_SET_PARAM_CMDID,
237 WMI_PDEV_PKTLOG_ENABLE_CMDID,
238 WMI_PDEV_PKTLOG_DISABLE_CMDID,
239 WMI_PDEV_SET_WMM_PARAMS_CMDID,
240 WMI_PDEV_SET_HT_CAP_IE_CMDID,
241 WMI_PDEV_SET_VHT_CAP_IE_CMDID,
242 WMI_PDEV_SET_DSCP_TID_MAP_CMDID,
243 WMI_PDEV_SET_QUIET_MODE_CMDID,
244 WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID,
245 WMI_PDEV_GET_TPC_CONFIG_CMDID,
246 WMI_PDEV_SET_BASE_MACADDR_CMDID,
247 WMI_PDEV_DUMP_CMDID,
248 WMI_PDEV_SET_LED_CONFIG_CMDID,
249 WMI_PDEV_GET_TEMPERATURE_CMDID,
250 WMI_PDEV_SET_LED_FLASHING_CMDID,
251 WMI_PDEV_SMART_ANT_ENABLE_CMDID,
252 WMI_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID,
253 WMI_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID,
254 WMI_PDEV_SET_CTL_TABLE_CMDID,
255 WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID,
256 WMI_PDEV_FIPS_CMDID,
257 WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID,
258 WMI_PDEV_GET_ANI_OFDM_CONFIG_CMDID,
259 WMI_PDEV_GET_NFCAL_POWER_CMDID,
260 WMI_PDEV_GET_TPC_CMDID,
261 WMI_MIB_STATS_ENABLE_CMDID,
262 WMI_PDEV_SET_PCL_CMDID,
263 WMI_PDEV_SET_HW_MODE_CMDID,
264 WMI_PDEV_SET_MAC_CONFIG_CMDID,
265 WMI_PDEV_SET_ANTENNA_MODE_CMDID,
266 WMI_SET_PERIODIC_CHANNEL_STATS_CONFIG_CMDID,
267 WMI_PDEV_WAL_POWER_DEBUG_CMDID,
268 WMI_PDEV_SET_REORDER_TIMEOUT_VAL_CMDID,
269 WMI_PDEV_SET_WAKEUP_CONFIG_CMDID,
270 WMI_PDEV_GET_ANTDIV_STATUS_CMDID,
271 WMI_PDEV_GET_CHIP_POWER_STATS_CMDID,
272 WMI_PDEV_SET_STATS_THRESHOLD_CMDID,
273 WMI_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMDID,
274 WMI_PDEV_UPDATE_PKT_ROUTING_CMDID,
275 WMI_PDEV_CHECK_CAL_VERSION_CMDID,
276 WMI_PDEV_SET_DIVERSITY_GAIN_CMDID,
277 WMI_PDEV_DIV_GET_RSSI_ANTID_CMDID,
278 WMI_PDEV_BSS_CHAN_INFO_REQUEST_CMDID,
279 WMI_PDEV_UPDATE_PMK_CACHE_CMDID,
280 WMI_PDEV_UPDATE_FILS_HLP_PKT_CMDID,
281 WMI_PDEV_UPDATE_CTLTABLE_REQUEST_CMDID,
282 WMI_PDEV_CONFIG_VENDOR_OUI_ACTION_CMDID,
283 WMI_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMDID,
284 WMI_PDEV_SET_RX_FILTER_PROMISCUOUS_CMDID,
285 WMI_PDEV_DMA_RING_CFG_REQ_CMDID,
286 WMI_PDEV_HE_TB_ACTION_FRM_CMDID,
287 WMI_PDEV_PKTLOG_FILTER_CMDID,
288 WMI_PDEV_SET_RAP_CONFIG_CMDID,
289 WMI_PDEV_DSM_FILTER_CMDID,
290 WMI_PDEV_FRAME_INJECT_CMDID,
291 WMI_PDEV_TBTT_OFFSET_SYNC_CMDID,
292 WMI_PDEV_SET_SRG_BSS_COLOR_BITMAP_CMDID,
293 WMI_PDEV_SET_SRG_PARTIAL_BSSID_BITMAP_CMDID,
294 WMI_PDEV_SET_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID,
295 WMI_PDEV_SET_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID,
296 WMI_PDEV_SET_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID,
297 WMI_PDEV_SET_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID,
298 WMI_PDEV_GET_TPC_STATS_CMDID,
299 WMI_PDEV_ENABLE_DURATION_BASED_TX_MODE_SELECTION_CMDID,
300 WMI_PDEV_GET_DPD_STATUS_CMDID,
301 WMI_PDEV_SET_BIOS_SAR_TABLE_CMDID,
302 WMI_PDEV_SET_BIOS_GEO_TABLE_CMDID,
303 WMI_VDEV_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_VDEV),
304 WMI_VDEV_DELETE_CMDID,
305 WMI_VDEV_START_REQUEST_CMDID,
306 WMI_VDEV_RESTART_REQUEST_CMDID,
307 WMI_VDEV_UP_CMDID,
308 WMI_VDEV_STOP_CMDID,
309 WMI_VDEV_DOWN_CMDID,
310 WMI_VDEV_SET_PARAM_CMDID,
311 WMI_VDEV_INSTALL_KEY_CMDID,
312 WMI_VDEV_WNM_SLEEPMODE_CMDID,
313 WMI_VDEV_WMM_ADDTS_CMDID,
314 WMI_VDEV_WMM_DELTS_CMDID,
315 WMI_VDEV_SET_WMM_PARAMS_CMDID,
316 WMI_VDEV_SET_GTX_PARAMS_CMDID,
317 WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID,
318 WMI_VDEV_PLMREQ_START_CMDID,
319 WMI_VDEV_PLMREQ_STOP_CMDID,
320 WMI_VDEV_TSF_TSTAMP_ACTION_CMDID,
321 WMI_VDEV_SET_IE_CMDID,
322 WMI_VDEV_RATEMASK_CMDID,
323 WMI_VDEV_ATF_REQUEST_CMDID,
324 WMI_VDEV_SET_DSCP_TID_MAP_CMDID,
325 WMI_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID,
326 WMI_VDEV_SET_QUIET_MODE_CMDID,
327 WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID,
328 WMI_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMDID,
329 WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMDID,
330 WMI_PEER_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_PEER),
331 WMI_PEER_DELETE_CMDID,
332 WMI_PEER_FLUSH_TIDS_CMDID,
333 WMI_PEER_SET_PARAM_CMDID,
334 WMI_PEER_ASSOC_CMDID,
335 WMI_PEER_ADD_WDS_ENTRY_CMDID,
336 WMI_PEER_REMOVE_WDS_ENTRY_CMDID,
337 WMI_PEER_MCAST_GROUP_CMDID,
338 WMI_PEER_INFO_REQ_CMDID,
339 WMI_PEER_GET_ESTIMATED_LINKSPEED_CMDID,
340 WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID,
341 WMI_PEER_UPDATE_WDS_ENTRY_CMDID,
342 WMI_PEER_ADD_PROXY_STA_ENTRY_CMDID,
343 WMI_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID,
344 WMI_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID,
345 WMI_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID,
346 WMI_PEER_ATF_REQUEST_CMDID,
347 WMI_PEER_BWF_REQUEST_CMDID,
348 WMI_PEER_REORDER_QUEUE_SETUP_CMDID,
349 WMI_PEER_REORDER_QUEUE_REMOVE_CMDID,
350 WMI_PEER_SET_RX_BLOCKSIZE_CMDID,
351 WMI_PEER_ANTDIV_INFO_REQ_CMDID,
352 WMI_BCN_TX_CMDID = WMI_TLV_CMD(WMI_GRP_MGMT),
353 WMI_PDEV_SEND_BCN_CMDID,
354 WMI_BCN_TMPL_CMDID,
355 WMI_BCN_FILTER_RX_CMDID,
356 WMI_PRB_REQ_FILTER_RX_CMDID,
357 WMI_MGMT_TX_CMDID,
358 WMI_PRB_TMPL_CMDID,
359 WMI_MGMT_TX_SEND_CMDID,
360 WMI_OFFCHAN_DATA_TX_SEND_CMDID,
361 WMI_PDEV_SEND_FD_CMDID,
362 WMI_BCN_OFFLOAD_CTRL_CMDID,
363 WMI_BSS_COLOR_CHANGE_ENABLE_CMDID,
364 WMI_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMDID,
365 WMI_FILS_DISCOVERY_TMPL_CMDID,
366 WMI_ADDBA_CLEAR_RESP_CMDID = WMI_TLV_CMD(WMI_GRP_BA_NEG),
367 WMI_ADDBA_SEND_CMDID,
368 WMI_ADDBA_STATUS_CMDID,
369 WMI_DELBA_SEND_CMDID,
370 WMI_ADDBA_SET_RESP_CMDID,
371 WMI_SEND_SINGLEAMSDU_CMDID,
372 WMI_STA_POWERSAVE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_PS),
373 WMI_STA_POWERSAVE_PARAM_CMDID,
374 WMI_STA_MIMO_PS_MODE_CMDID,
375 WMI_PDEV_DFS_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_DFS),
376 WMI_PDEV_DFS_DISABLE_CMDID,
377 WMI_DFS_PHYERR_FILTER_ENA_CMDID,
378 WMI_DFS_PHYERR_FILTER_DIS_CMDID,
379 WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMDID,
380 WMI_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMDID,
381 WMI_VDEV_ADFS_CH_CFG_CMDID,
382 WMI_VDEV_ADFS_OCAC_ABORT_CMDID,
383 WMI_ROAM_SCAN_MODE = WMI_TLV_CMD(WMI_GRP_ROAM),
384 WMI_ROAM_SCAN_RSSI_THRESHOLD,
385 WMI_ROAM_SCAN_PERIOD,
386 WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD,
387 WMI_ROAM_AP_PROFILE,
388 WMI_ROAM_CHAN_LIST,
389 WMI_ROAM_SCAN_CMD,
390 WMI_ROAM_SYNCH_COMPLETE,
391 WMI_ROAM_SET_RIC_REQUEST_CMDID,
392 WMI_ROAM_INVOKE_CMDID,
393 WMI_ROAM_FILTER_CMDID,
394 WMI_ROAM_SUBNET_CHANGE_CONFIG_CMDID,
395 WMI_ROAM_CONFIGURE_MAWC_CMDID,
396 WMI_ROAM_SET_MBO_PARAM_CMDID,
397 WMI_ROAM_PER_CONFIG_CMDID,
398 WMI_ROAM_BTM_CONFIG_CMDID,
399 WMI_ENABLE_FILS_CMDID,
400 WMI_OFL_SCAN_ADD_AP_PROFILE = WMI_TLV_CMD(WMI_GRP_OFL_SCAN),
401 WMI_OFL_SCAN_REMOVE_AP_PROFILE,
402 WMI_OFL_SCAN_PERIOD,
403 WMI_P2P_DEV_SET_DEVICE_INFO = WMI_TLV_CMD(WMI_GRP_P2P),
404 WMI_P2P_DEV_SET_DISCOVERABILITY,
405 WMI_P2P_GO_SET_BEACON_IE,
406 WMI_P2P_GO_SET_PROBE_RESP_IE,
407 WMI_P2P_SET_VENDOR_IE_DATA_CMDID,
408 WMI_P2P_DISC_OFFLOAD_CONFIG_CMDID,
409 WMI_P2P_DISC_OFFLOAD_APPIE_CMDID,
410 WMI_P2P_DISC_OFFLOAD_PATTERN_CMDID,
411 WMI_P2P_SET_OPPPS_PARAM_CMDID,
412 WMI_P2P_LISTEN_OFFLOAD_START_CMDID,
413 WMI_P2P_LISTEN_OFFLOAD_STOP_CMDID,
414 WMI_AP_PS_PEER_PARAM_CMDID = WMI_TLV_CMD(WMI_GRP_AP_PS),
415 WMI_AP_PS_PEER_UAPSD_COEX_CMDID,
416 WMI_AP_PS_EGAP_PARAM_CMDID,
417 WMI_PEER_RATE_RETRY_SCHED_CMDID = WMI_TLV_CMD(WMI_GRP_RATE_CTRL),
418 WMI_WLAN_PROFILE_TRIGGER_CMDID = WMI_TLV_CMD(WMI_GRP_PROFILE),
419 WMI_WLAN_PROFILE_SET_HIST_INTVL_CMDID,
420 WMI_WLAN_PROFILE_GET_PROFILE_DATA_CMDID,
421 WMI_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID,
422 WMI_WLAN_PROFILE_LIST_PROFILE_ID_CMDID,
423 WMI_PDEV_SUSPEND_CMDID = WMI_TLV_CMD(WMI_GRP_SUSPEND),
424 WMI_PDEV_RESUME_CMDID,
425 WMI_ADD_BCN_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_BCN_FILTER),
426 WMI_RMV_BCN_FILTER_CMDID,
427 WMI_WOW_ADD_WAKE_PATTERN_CMDID = WMI_TLV_CMD(WMI_GRP_WOW),
428 WMI_WOW_DEL_WAKE_PATTERN_CMDID,
429 WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID,
430 WMI_WOW_ENABLE_CMDID,
431 WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID,
432 WMI_WOW_IOAC_ADD_KEEPALIVE_CMDID,
433 WMI_WOW_IOAC_DEL_KEEPALIVE_CMDID,
434 WMI_WOW_IOAC_ADD_WAKE_PATTERN_CMDID,
435 WMI_WOW_IOAC_DEL_WAKE_PATTERN_CMDID,
436 WMI_D0_WOW_ENABLE_DISABLE_CMDID,
437 WMI_EXTWOW_ENABLE_CMDID,
438 WMI_EXTWOW_SET_APP_TYPE1_PARAMS_CMDID,
439 WMI_EXTWOW_SET_APP_TYPE2_PARAMS_CMDID,
440 WMI_WOW_ENABLE_ICMPV6_NA_FLT_CMDID,
441 WMI_WOW_UDP_SVC_OFLD_CMDID,
442 WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMDID,
443 WMI_WOW_SET_ACTION_WAKE_UP_CMDID,
444 WMI_RTT_MEASREQ_CMDID = WMI_TLV_CMD(WMI_GRP_RTT),
445 WMI_RTT_TSF_CMDID,
446 WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID = WMI_TLV_CMD(WMI_GRP_SPECTRAL),
447 WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID,
448 WMI_REQUEST_STATS_CMDID = WMI_TLV_CMD(WMI_GRP_STATS),
449 WMI_MCC_SCHED_TRAFFIC_STATS_CMDID,
450 WMI_REQUEST_STATS_EXT_CMDID,
451 WMI_REQUEST_LINK_STATS_CMDID,
452 WMI_START_LINK_STATS_CMDID,
453 WMI_CLEAR_LINK_STATS_CMDID,
454 WMI_GET_FW_MEM_DUMP_CMDID,
455 WMI_DEBUG_MESG_FLUSH_CMDID,
456 WMI_DIAG_EVENT_LOG_CONFIG_CMDID,
457 WMI_REQUEST_WLAN_STATS_CMDID,
458 WMI_REQUEST_RCPI_CMDID,
459 WMI_REQUEST_PEER_STATS_INFO_CMDID,
460 WMI_REQUEST_RADIO_CHAN_STATS_CMDID,
461 WMI_SET_ARP_NS_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_ARP_NS_OFL),
462 WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMDID,
463 WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMDID,
464 WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_NLO_OFL),
465 WMI_APFIND_CMDID,
466 WMI_PASSPOINT_LIST_CONFIG_CMDID,
467 WMI_NLO_CONFIGURE_MAWC_CMDID,
468 WMI_GTK_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_GTK_OFL),
469 WMI_CSA_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_CSA_OFL),
470 WMI_CSA_OFFLOAD_CHANSWITCH_CMDID,
471 WMI_CHATTER_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_CHATTER),
472 WMI_CHATTER_ADD_COALESCING_FILTER_CMDID,
473 WMI_CHATTER_DELETE_COALESCING_FILTER_CMDID,
474 WMI_CHATTER_COALESCING_QUERY_CMDID,
475 WMI_PEER_TID_ADDBA_CMDID = WMI_TLV_CMD(WMI_GRP_TID_ADDBA),
476 WMI_PEER_TID_DELBA_CMDID,
477 WMI_STA_DTIM_PS_METHOD_CMDID,
478 WMI_STA_UAPSD_AUTO_TRIG_CMDID,
479 WMI_STA_KEEPALIVE_CMDID,
480 WMI_BA_REQ_SSN_CMDID,
481 WMI_ECHO_CMDID = WMI_TLV_CMD(WMI_GRP_MISC),
482 WMI_PDEV_UTF_CMDID,
483 WMI_DBGLOG_CFG_CMDID,
484 WMI_PDEV_QVIT_CMDID,
485 WMI_PDEV_FTM_INTG_CMDID,
486 WMI_VDEV_SET_KEEPALIVE_CMDID,
487 WMI_VDEV_GET_KEEPALIVE_CMDID,
488 WMI_FORCE_FW_HANG_CMDID,
489 WMI_SET_MCASTBCAST_FILTER_CMDID,
490 WMI_THERMAL_MGMT_CMDID,
491 WMI_HOST_AUTO_SHUTDOWN_CFG_CMDID,
492 WMI_TPC_CHAINMASK_CONFIG_CMDID,
493 WMI_SET_ANTENNA_DIVERSITY_CMDID,
494 WMI_OCB_SET_SCHED_CMDID,
495 WMI_RSSI_BREACH_MONITOR_CONFIG_CMDID,
496 WMI_LRO_CONFIG_CMDID,
497 WMI_TRANSFER_DATA_TO_FLASH_CMDID,
498 WMI_CONFIG_ENHANCED_MCAST_FILTER_CMDID,
499 WMI_VDEV_WISA_CMDID,
500 WMI_DBGLOG_TIME_STAMP_SYNC_CMDID,
501 WMI_SET_MULTIPLE_MCAST_FILTER_CMDID,
502 WMI_READ_DATA_FROM_FLASH_CMDID,
503 WMI_THERM_THROT_SET_CONF_CMDID,
504 WMI_RUNTIME_DPD_RECAL_CMDID,
505 WMI_GET_TPC_POWER_CMDID,
506 WMI_IDLE_TRIGGER_MONITOR_CMDID,
507 WMI_GPIO_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_GPIO),
508 WMI_GPIO_OUTPUT_CMDID,
509 WMI_TXBF_CMDID,
510 WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_FWTEST),
511 WMI_FWTEST_P2P_SET_NOA_PARAM_CMDID,
512 WMI_UNIT_TEST_CMDID,
513 WMI_FWTEST_CMDID,
514 WMI_QBOOST_CFG_CMDID,
515 WMI_TDLS_SET_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_TDLS),
516 WMI_TDLS_PEER_UPDATE_CMDID,
517 WMI_TDLS_SET_OFFCHAN_MODE_CMDID,
518 WMI_RESMGR_ADAPTIVE_OCS_EN_DIS_CMDID = WMI_TLV_CMD(WMI_GRP_RESMGR),
519 WMI_RESMGR_SET_CHAN_TIME_QUOTA_CMDID,
520 WMI_RESMGR_SET_CHAN_LATENCY_CMDID,
521 WMI_STA_SMPS_FORCE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_SMPS),
522 WMI_STA_SMPS_PARAM_CMDID,
523 WMI_HB_SET_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_WLAN_HB),
524 WMI_HB_SET_TCP_PARAMS_CMDID,
525 WMI_HB_SET_TCP_PKT_FILTER_CMDID,
526 WMI_HB_SET_UDP_PARAMS_CMDID,
527 WMI_HB_SET_UDP_PKT_FILTER_CMDID,
528 WMI_RMC_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_RMC),
529 WMI_RMC_SET_ACTION_PERIOD_CMDID,
530 WMI_RMC_CONFIG_CMDID,
531 WMI_RMC_SET_MANUAL_LEADER_CMDID,
532 WMI_MHF_OFFLOAD_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_MHF_OFL),
533 WMI_MHF_OFFLOAD_PLUMB_ROUTING_TBL_CMDID,
534 WMI_BATCH_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN),
535 WMI_BATCH_SCAN_DISABLE_CMDID,
536 WMI_BATCH_SCAN_TRIGGER_RESULT_CMDID,
537 WMI_OEM_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_OEM),
538 WMI_OEM_REQUEST_CMDID,
539 WMI_LPI_OEM_REQ_CMDID,
540 WMI_NAN_CMDID = WMI_TLV_CMD(WMI_GRP_NAN),
541 WMI_MODEM_POWER_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_COEX),
542 WMI_CHAN_AVOID_UPDATE_CMDID,
543 WMI_COEX_CONFIG_CMDID,
544 WMI_CHAN_AVOID_RPT_ALLOW_CMDID,
545 WMI_COEX_GET_ANTENNA_ISOLATION_CMDID,
546 WMI_SAR_LIMITS_CMDID,
547 WMI_OBSS_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_OBSS_OFL),
548 WMI_OBSS_SCAN_DISABLE_CMDID,
549 WMI_OBSS_COLOR_COLLISION_DET_CONFIG_CMDID,
550 WMI_LPI_MGMT_SNOOPING_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_LPI),
551 WMI_LPI_START_SCAN_CMDID,
552 WMI_LPI_STOP_SCAN_CMDID,
553 WMI_EXTSCAN_START_CMDID = WMI_TLV_CMD(WMI_GRP_EXTSCAN),
554 WMI_EXTSCAN_STOP_CMDID,
555 WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID,
556 WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID,
557 WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID,
558 WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID,
559 WMI_EXTSCAN_SET_CAPABILITIES_CMDID,
560 WMI_EXTSCAN_GET_CAPABILITIES_CMDID,
561 WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID,
562 WMI_EXTSCAN_CONFIGURE_MAWC_CMDID,
563 WMI_SET_DHCP_SERVER_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_DHCP_OFL),
564 WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID = WMI_TLV_CMD(WMI_GRP_IPA),
565 WMI_MDNS_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL),
566 WMI_MDNS_SET_FQDN_CMDID,
567 WMI_MDNS_SET_RESPONSE_CMDID,
568 WMI_MDNS_GET_STATS_CMDID,
569 WMI_SAP_OFL_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_SAP_OFL),
570 WMI_SAP_SET_BLACKLIST_PARAM_CMDID,
571 WMI_OCB_SET_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_OCB),
572 WMI_OCB_SET_UTC_TIME_CMDID,
573 WMI_OCB_START_TIMING_ADVERT_CMDID,
574 WMI_OCB_STOP_TIMING_ADVERT_CMDID,
575 WMI_OCB_GET_TSF_TIMER_CMDID,
576 WMI_DCC_GET_STATS_CMDID,
577 WMI_DCC_CLEAR_STATS_CMDID,
578 WMI_DCC_UPDATE_NDL_CMDID,
579 WMI_SOC_SET_PCL_CMDID = WMI_TLV_CMD(WMI_GRP_SOC),
580 WMI_SOC_SET_HW_MODE_CMDID,
581 WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID,
582 WMI_SOC_SET_ANTENNA_MODE_CMDID,
583 WMI_PACKET_FILTER_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_PKT_FILTER),
584 WMI_PACKET_FILTER_ENABLE_CMDID,
585 WMI_MAWC_SENSOR_REPORT_IND_CMDID = WMI_TLV_CMD(WMI_GRP_MAWC),
586 WMI_PMF_OFFLOAD_SET_SA_QUERY_CMDID = WMI_TLV_CMD(WMI_GRP_PMF_OFFLOAD),
587 WMI_BPF_GET_CAPABILITY_CMDID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD),
588 WMI_BPF_GET_VDEV_STATS_CMDID,
589 WMI_BPF_SET_VDEV_INSTRUCTIONS_CMDID,
590 WMI_BPF_DEL_VDEV_INSTRUCTIONS_CMDID,
591 WMI_BPF_SET_VDEV_ACTIVE_MODE_CMDID,
592 WMI_MNT_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_MONITOR),
593 WMI_SET_CURRENT_COUNTRY_CMDID = WMI_TLV_CMD(WMI_GRP_REGULATORY),
594 WMI_11D_SCAN_START_CMDID,
595 WMI_11D_SCAN_STOP_CMDID,
596 WMI_SET_INIT_COUNTRY_CMDID,
597 WMI_NDI_GET_CAP_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE),
598 WMI_NDP_INITIATOR_REQ_CMDID,
599 WMI_NDP_RESPONDER_REQ_CMDID,
600 WMI_NDP_END_REQ_CMDID,
601 WMI_HW_DATA_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_HW_DATA_FILTER),
602 WMI_TWT_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_TWT),
603 WMI_TWT_DISABLE_CMDID,
604 WMI_TWT_ADD_DIALOG_CMDID,
605 WMI_TWT_DEL_DIALOG_CMDID,
606 WMI_TWT_PAUSE_DIALOG_CMDID,
607 WMI_TWT_RESUME_DIALOG_CMDID,
608 WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID =
609 WMI_TLV_CMD(WMI_GRP_SPATIAL_REUSE),
610 WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID,
611};
612
613enum wmi_tlv_event_id {
614 WMI_SERVICE_READY_EVENTID = 0x1,
615 WMI_READY_EVENTID,
616 WMI_SERVICE_AVAILABLE_EVENTID,
617 WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN),
618 WMI_PDEV_TPC_CONFIG_EVENTID = WMI_TLV_CMD(WMI_GRP_PDEV),
619 WMI_CHAN_INFO_EVENTID,
620 WMI_PHYERR_EVENTID,
621 WMI_PDEV_DUMP_EVENTID,
622 WMI_TX_PAUSE_EVENTID,
623 WMI_DFS_RADAR_EVENTID,
624 WMI_PDEV_L1SS_TRACK_EVENTID,
625 WMI_PDEV_TEMPERATURE_EVENTID,
626 WMI_SERVICE_READY_EXT_EVENTID,
627 WMI_PDEV_FIPS_EVENTID,
628 WMI_PDEV_CHANNEL_HOPPING_EVENTID,
629 WMI_PDEV_ANI_CCK_LEVEL_EVENTID,
630 WMI_PDEV_ANI_OFDM_LEVEL_EVENTID,
631 WMI_PDEV_TPC_EVENTID,
632 WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID,
633 WMI_PDEV_SET_HW_MODE_RESP_EVENTID,
634 WMI_PDEV_HW_MODE_TRANSITION_EVENTID,
635 WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID,
636 WMI_PDEV_ANTDIV_STATUS_EVENTID,
637 WMI_PDEV_CHIP_POWER_STATS_EVENTID,
638 WMI_PDEV_CHIP_POWER_SAVE_FAILURE_DETECTED_EVENTID,
639 WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID,
640 WMI_PDEV_CHECK_CAL_VERSION_EVENTID,
641 WMI_PDEV_DIV_RSSI_ANTID_EVENTID,
642 WMI_PDEV_BSS_CHAN_INFO_EVENTID,
643 WMI_PDEV_UPDATE_CTLTABLE_EVENTID,
644 WMI_PDEV_DMA_RING_CFG_RSP_EVENTID,
645 WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID,
646 WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID,
647 WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID,
648 WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID,
649 WMI_PDEV_RAP_INFO_EVENTID,
650 WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID,
651 WMI_SERVICE_READY_EXT2_EVENTID,
652 WMI_VDEV_START_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_VDEV),
653 WMI_VDEV_STOPPED_EVENTID,
654 WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID,
655 WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID,
656 WMI_VDEV_TSF_REPORT_EVENTID,
657 WMI_VDEV_DELETE_RESP_EVENTID,
658 WMI_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENTID,
659 WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENTID,
660 WMI_PEER_STA_KICKOUT_EVENTID = WMI_TLV_CMD(WMI_GRP_PEER),
661 WMI_PEER_INFO_EVENTID,
662 WMI_PEER_TX_FAIL_CNT_THR_EVENTID,
663 WMI_PEER_ESTIMATED_LINKSPEED_EVENTID,
664 WMI_PEER_STATE_EVENTID,
665 WMI_PEER_ASSOC_CONF_EVENTID,
666 WMI_PEER_DELETE_RESP_EVENTID,
667 WMI_PEER_RATECODE_LIST_EVENTID,
668 WMI_WDS_PEER_EVENTID,
669 WMI_PEER_STA_PS_STATECHG_EVENTID,
670 WMI_PEER_ANTDIV_INFO_EVENTID,
671 WMI_PEER_RESERVED0_EVENTID,
672 WMI_PEER_RESERVED1_EVENTID,
673 WMI_PEER_RESERVED2_EVENTID,
674 WMI_PEER_RESERVED3_EVENTID,
675 WMI_PEER_RESERVED4_EVENTID,
676 WMI_PEER_RESERVED5_EVENTID,
677 WMI_PEER_RESERVED6_EVENTID,
678 WMI_PEER_RESERVED7_EVENTID,
679 WMI_PEER_RESERVED8_EVENTID,
680 WMI_PEER_RESERVED9_EVENTID,
681 WMI_PEER_RESERVED10_EVENTID,
682 WMI_PEER_OPER_MODE_CHANGE_EVENTID,
683 WMI_PEER_TX_PN_RESPONSE_EVENTID,
684 WMI_PEER_CFR_CAPTURE_EVENTID,
685 WMI_PEER_CREATE_CONF_EVENTID,
686 WMI_MGMT_RX_EVENTID = WMI_TLV_CMD(WMI_GRP_MGMT),
687 WMI_HOST_SWBA_EVENTID,
688 WMI_TBTTOFFSET_UPDATE_EVENTID,
689 WMI_OFFLOAD_BCN_TX_STATUS_EVENTID,
690 WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID,
691 WMI_MGMT_TX_COMPLETION_EVENTID,
692 WMI_MGMT_TX_BUNDLE_COMPLETION_EVENTID,
693 WMI_TBTTOFFSET_EXT_UPDATE_EVENTID,
694 WMI_OFFCHAN_DATA_TX_COMPLETION_EVENTID,
695 WMI_HOST_FILS_DISCOVERY_EVENTID,
696 WMI_TX_DELBA_COMPLETE_EVENTID = WMI_TLV_CMD(WMI_GRP_BA_NEG),
697 WMI_TX_ADDBA_COMPLETE_EVENTID,
698 WMI_BA_RSP_SSN_EVENTID,
699 WMI_AGGR_STATE_TRIG_EVENTID,
700 WMI_ROAM_EVENTID = WMI_TLV_CMD(WMI_GRP_ROAM),
701 WMI_PROFILE_MATCH,
702 WMI_ROAM_SYNCH_EVENTID,
703 WMI_P2P_DISC_EVENTID = WMI_TLV_CMD(WMI_GRP_P2P),
704 WMI_P2P_NOA_EVENTID,
705 WMI_P2P_LISTEN_OFFLOAD_STOPPED_EVENTID,
706 WMI_AP_PS_EGAP_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_AP_PS),
707 WMI_PDEV_RESUME_EVENTID = WMI_TLV_CMD(WMI_GRP_SUSPEND),
708 WMI_WOW_WAKEUP_HOST_EVENTID = WMI_TLV_CMD(WMI_GRP_WOW),
709 WMI_D0_WOW_DISABLE_ACK_EVENTID,
710 WMI_WOW_INITIAL_WAKEUP_EVENTID,
711 WMI_RTT_MEASUREMENT_REPORT_EVENTID = WMI_TLV_CMD(WMI_GRP_RTT),
712 WMI_TSF_MEASUREMENT_REPORT_EVENTID,
713 WMI_RTT_ERROR_REPORT_EVENTID,
714 WMI_STATS_EXT_EVENTID = WMI_TLV_CMD(WMI_GRP_STATS),
715 WMI_IFACE_LINK_STATS_EVENTID,
716 WMI_PEER_LINK_STATS_EVENTID,
717 WMI_RADIO_LINK_STATS_EVENTID,
718 WMI_UPDATE_FW_MEM_DUMP_EVENTID,
719 WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID,
720 WMI_INST_RSSI_STATS_EVENTID,
721 WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID,
722 WMI_REPORT_STATS_EVENTID,
723 WMI_UPDATE_RCPI_EVENTID,
724 WMI_PEER_STATS_INFO_EVENTID,
725 WMI_RADIO_CHAN_STATS_EVENTID,
726 WMI_NLO_MATCH_EVENTID = WMI_TLV_CMD(WMI_GRP_NLO_OFL),
727 WMI_NLO_SCAN_COMPLETE_EVENTID,
728 WMI_APFIND_EVENTID,
729 WMI_PASSPOINT_MATCH_EVENTID,
730 WMI_GTK_OFFLOAD_STATUS_EVENTID = WMI_TLV_CMD(WMI_GRP_GTK_OFL),
731 WMI_GTK_REKEY_FAIL_EVENTID,
732 WMI_CSA_HANDLING_EVENTID = WMI_TLV_CMD(WMI_GRP_CSA_OFL),
733 WMI_CHATTER_PC_QUERY_EVENTID = WMI_TLV_CMD(WMI_GRP_CHATTER),
734 WMI_PDEV_DFS_RADAR_DETECTION_EVENTID = WMI_TLV_CMD(WMI_GRP_DFS),
735 WMI_VDEV_DFS_CAC_COMPLETE_EVENTID,
736 WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID,
737 WMI_ECHO_EVENTID = WMI_TLV_CMD(WMI_GRP_MISC),
738 WMI_PDEV_UTF_EVENTID,
739 WMI_DEBUG_MESG_EVENTID,
740 WMI_UPDATE_STATS_EVENTID,
741 WMI_DEBUG_PRINT_EVENTID,
742 WMI_DCS_INTERFERENCE_EVENTID,
743 WMI_PDEV_QVIT_EVENTID,
744 WMI_WLAN_PROFILE_DATA_EVENTID,
745 WMI_PDEV_FTM_INTG_EVENTID,
746 WMI_WLAN_FREQ_AVOID_EVENTID,
747 WMI_VDEV_GET_KEEPALIVE_EVENTID,
748 WMI_THERMAL_MGMT_EVENTID,
749 WMI_DIAG_DATA_CONTAINER_EVENTID,
750 WMI_HOST_AUTO_SHUTDOWN_EVENTID,
751 WMI_UPDATE_WHAL_MIB_STATS_EVENTID,
752 WMI_UPDATE_VDEV_RATE_STATS_EVENTID,
753 WMI_DIAG_EVENTID,
754 WMI_OCB_SET_SCHED_EVENTID,
755 WMI_DEBUG_MESG_FLUSH_COMPLETE_EVENTID,
756 WMI_RSSI_BREACH_EVENTID,
757 WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID,
758 WMI_PDEV_UTF_SCPC_EVENTID,
759 WMI_READ_DATA_FROM_FLASH_EVENTID,
760 WMI_REPORT_RX_AGGR_FAILURE_EVENTID,
761 WMI_PKGID_EVENTID,
762 WMI_GPIO_INPUT_EVENTID = WMI_TLV_CMD(WMI_GRP_GPIO),
763 WMI_UPLOADH_EVENTID,
764 WMI_CAPTUREH_EVENTID,
765 WMI_RFKILL_STATE_CHANGE_EVENTID,
766 WMI_TDLS_PEER_EVENTID = WMI_TLV_CMD(WMI_GRP_TDLS),
767 WMI_STA_SMPS_FORCE_MODE_COMPL_EVENTID = WMI_TLV_CMD(WMI_GRP_STA_SMPS),
768 WMI_BATCH_SCAN_ENABLED_EVENTID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN),
769 WMI_BATCH_SCAN_RESULT_EVENTID,
770 WMI_OEM_CAPABILITY_EVENTID = WMI_TLV_CMD(WMI_GRP_OEM),
771 WMI_OEM_MEASUREMENT_REPORT_EVENTID,
772 WMI_OEM_ERROR_REPORT_EVENTID,
773 WMI_OEM_RESPONSE_EVENTID,
774 WMI_NAN_EVENTID = WMI_TLV_CMD(WMI_GRP_NAN),
775 WMI_NAN_DISC_IFACE_CREATED_EVENTID,
776 WMI_NAN_DISC_IFACE_DELETED_EVENTID,
777 WMI_NAN_STARTED_CLUSTER_EVENTID,
778 WMI_NAN_JOINED_CLUSTER_EVENTID,
779 WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_TLV_CMD(WMI_GRP_COEX),
780 WMI_LPI_RESULT_EVENTID = WMI_TLV_CMD(WMI_GRP_LPI),
781 WMI_LPI_STATUS_EVENTID,
782 WMI_LPI_HANDOFF_EVENTID,
783 WMI_EXTSCAN_START_STOP_EVENTID = WMI_TLV_CMD(WMI_GRP_EXTSCAN),
784 WMI_EXTSCAN_OPERATION_EVENTID,
785 WMI_EXTSCAN_TABLE_USAGE_EVENTID,
786 WMI_EXTSCAN_CACHED_RESULTS_EVENTID,
787 WMI_EXTSCAN_WLAN_CHANGE_RESULTS_EVENTID,
788 WMI_EXTSCAN_HOTLIST_MATCH_EVENTID,
789 WMI_EXTSCAN_CAPABILITIES_EVENTID,
790 WMI_EXTSCAN_HOTLIST_SSID_MATCH_EVENTID,
791 WMI_MDNS_STATS_EVENTID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL),
792 WMI_SAP_OFL_ADD_STA_EVENTID = WMI_TLV_CMD(WMI_GRP_SAP_OFL),
793 WMI_SAP_OFL_DEL_STA_EVENTID,
794 WMI_OBSS_COLOR_COLLISION_DETECTION_EVENTID =
795 WMI_EVT_GRP_START_ID(WMI_GRP_OBSS_OFL),
796 WMI_OCB_SET_CONFIG_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_OCB),
797 WMI_OCB_GET_TSF_TIMER_RESP_EVENTID,
798 WMI_DCC_GET_STATS_RESP_EVENTID,
799 WMI_DCC_UPDATE_NDL_RESP_EVENTID,
800 WMI_DCC_STATS_EVENTID,
801 WMI_SOC_SET_HW_MODE_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_SOC),
802 WMI_SOC_HW_MODE_TRANSITION_EVENTID,
803 WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID,
804 WMI_MAWC_ENABLE_SENSOR_EVENTID = WMI_TLV_CMD(WMI_GRP_MAWC),
805 WMI_BPF_CAPABILIY_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD),
806 WMI_BPF_VDEV_STATS_INFO_EVENTID,
807 WMI_RMC_NEW_LEADER_EVENTID = WMI_TLV_CMD(WMI_GRP_RMC),
808 WMI_REG_CHAN_LIST_CC_EVENTID = WMI_TLV_CMD(WMI_GRP_REGULATORY),
809 WMI_11D_NEW_COUNTRY_EVENTID,
810 WMI_REG_CHAN_LIST_CC_EXT_EVENTID,
811 WMI_NDI_CAP_RSP_EVENTID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE),
812 WMI_NDP_INITIATOR_RSP_EVENTID,
813 WMI_NDP_RESPONDER_RSP_EVENTID,
814 WMI_NDP_END_RSP_EVENTID,
815 WMI_NDP_INDICATION_EVENTID,
816 WMI_NDP_CONFIRM_EVENTID,
817 WMI_NDP_END_INDICATION_EVENTID,
818
819 WMI_TWT_ENABLE_EVENTID = WMI_TLV_CMD(WMI_GRP_TWT),
820 WMI_TWT_DISABLE_EVENTID,
821 WMI_TWT_ADD_DIALOG_EVENTID,
822 WMI_TWT_DEL_DIALOG_EVENTID,
823 WMI_TWT_PAUSE_DIALOG_EVENTID,
824 WMI_TWT_RESUME_DIALOG_EVENTID,
825};
826
827enum wmi_tlv_pdev_param {
828 WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1,
829 WMI_PDEV_PARAM_RX_CHAIN_MASK,
830 WMI_PDEV_PARAM_TXPOWER_LIMIT2G,
831 WMI_PDEV_PARAM_TXPOWER_LIMIT5G,
832 WMI_PDEV_PARAM_TXPOWER_SCALE,
833 WMI_PDEV_PARAM_BEACON_GEN_MODE,
834 WMI_PDEV_PARAM_BEACON_TX_MODE,
835 WMI_PDEV_PARAM_RESMGR_OFFCHAN_MODE,
836 WMI_PDEV_PARAM_PROTECTION_MODE,
837 WMI_PDEV_PARAM_DYNAMIC_BW,
838 WMI_PDEV_PARAM_NON_AGG_SW_RETRY_TH,
839 WMI_PDEV_PARAM_AGG_SW_RETRY_TH,
840 WMI_PDEV_PARAM_STA_KICKOUT_TH,
841 WMI_PDEV_PARAM_AC_AGGRSIZE_SCALING,
842 WMI_PDEV_PARAM_LTR_ENABLE,
843 WMI_PDEV_PARAM_LTR_AC_LATENCY_BE,
844 WMI_PDEV_PARAM_LTR_AC_LATENCY_BK,
845 WMI_PDEV_PARAM_LTR_AC_LATENCY_VI,
846 WMI_PDEV_PARAM_LTR_AC_LATENCY_VO,
847 WMI_PDEV_PARAM_LTR_AC_LATENCY_TIMEOUT,
848 WMI_PDEV_PARAM_LTR_SLEEP_OVERRIDE,
849 WMI_PDEV_PARAM_LTR_RX_OVERRIDE,
850 WMI_PDEV_PARAM_LTR_TX_ACTIVITY_TIMEOUT,
851 WMI_PDEV_PARAM_L1SS_ENABLE,
852 WMI_PDEV_PARAM_DSLEEP_ENABLE,
853 WMI_PDEV_PARAM_PCIELP_TXBUF_FLUSH,
854 WMI_PDEV_PARAM_PCIELP_TXBUF_WATERMARK,
855 WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_EN,
856 WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_VALUE,
857 WMI_PDEV_PARAM_PDEV_STATS_UPDATE_PERIOD,
858 WMI_PDEV_PARAM_VDEV_STATS_UPDATE_PERIOD,
859 WMI_PDEV_PARAM_PEER_STATS_UPDATE_PERIOD,
860 WMI_PDEV_PARAM_BCNFLT_STATS_UPDATE_PERIOD,
861 WMI_PDEV_PARAM_PMF_QOS,
862 WMI_PDEV_PARAM_ARP_AC_OVERRIDE,
863 WMI_PDEV_PARAM_DCS,
864 WMI_PDEV_PARAM_ANI_ENABLE,
865 WMI_PDEV_PARAM_ANI_POLL_PERIOD,
866 WMI_PDEV_PARAM_ANI_LISTEN_PERIOD,
867 WMI_PDEV_PARAM_ANI_OFDM_LEVEL,
868 WMI_PDEV_PARAM_ANI_CCK_LEVEL,
869 WMI_PDEV_PARAM_DYNTXCHAIN,
870 WMI_PDEV_PARAM_PROXY_STA,
871 WMI_PDEV_PARAM_IDLE_PS_CONFIG,
872 WMI_PDEV_PARAM_POWER_GATING_SLEEP,
873 WMI_PDEV_PARAM_RFKILL_ENABLE,
874 WMI_PDEV_PARAM_BURST_DUR,
875 WMI_PDEV_PARAM_BURST_ENABLE,
876 WMI_PDEV_PARAM_HW_RFKILL_CONFIG,
877 WMI_PDEV_PARAM_LOW_POWER_RF_ENABLE,
878 WMI_PDEV_PARAM_L1SS_TRACK,
879 WMI_PDEV_PARAM_HYST_EN,
880 WMI_PDEV_PARAM_POWER_COLLAPSE_ENABLE,
881 WMI_PDEV_PARAM_LED_SYS_STATE,
882 WMI_PDEV_PARAM_LED_ENABLE,
883 WMI_PDEV_PARAM_AUDIO_OVER_WLAN_LATENCY,
884 WMI_PDEV_PARAM_AUDIO_OVER_WLAN_ENABLE,
885 WMI_PDEV_PARAM_WHAL_MIB_STATS_UPDATE_ENABLE,
886 WMI_PDEV_PARAM_VDEV_RATE_STATS_UPDATE_PERIOD,
887 WMI_PDEV_PARAM_CTS_CBW,
888 WMI_PDEV_PARAM_WNTS_CONFIG,
889 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_ENABLE,
890 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_MIN_SLEEP_SLOP,
891 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_INC_DEC_STEP,
892 WMI_PDEV_PARAM_EARLY_RX_FIX_SLEEP_SLOP,
893 WMI_PDEV_PARAM_BMISS_BASED_ADAPTIVE_BTO_ENABLE,
894 WMI_PDEV_PARAM_BMISS_BTO_MIN_BCN_TIMEOUT,
895 WMI_PDEV_PARAM_BMISS_BTO_INC_DEC_STEP,
896 WMI_PDEV_PARAM_BTO_FIX_BCN_TIMEOUT,
897 WMI_PDEV_PARAM_CE_BASED_ADAPTIVE_BTO_ENABLE,
898 WMI_PDEV_PARAM_CE_BTO_COMBO_CE_VALUE,
899 WMI_PDEV_PARAM_TX_CHAIN_MASK_2G,
900 WMI_PDEV_PARAM_RX_CHAIN_MASK_2G,
901 WMI_PDEV_PARAM_TX_CHAIN_MASK_5G,
902 WMI_PDEV_PARAM_RX_CHAIN_MASK_5G,
903 WMI_PDEV_PARAM_TX_CHAIN_MASK_CCK,
904 WMI_PDEV_PARAM_TX_CHAIN_MASK_1SS,
905 WMI_PDEV_PARAM_CTS2SELF_FOR_P2P_GO_CONFIG,
906 WMI_PDEV_PARAM_TXPOWER_DECR_DB,
907 WMI_PDEV_PARAM_AGGR_BURST,
908 WMI_PDEV_PARAM_RX_DECAP_MODE,
909 WMI_PDEV_PARAM_FAST_CHANNEL_RESET,
910 WMI_PDEV_PARAM_SMART_ANTENNA_DEFAULT_ANTENNA,
911 WMI_PDEV_PARAM_ANTENNA_GAIN,
912 WMI_PDEV_PARAM_RX_FILTER,
913 WMI_PDEV_SET_MCAST_TO_UCAST_TID,
914 WMI_PDEV_PARAM_PROXY_STA_MODE,
915 WMI_PDEV_PARAM_SET_MCAST2UCAST_MODE,
916 WMI_PDEV_PARAM_SET_MCAST2UCAST_BUFFER,
917 WMI_PDEV_PARAM_REMOVE_MCAST2UCAST_BUFFER,
918 WMI_PDEV_PEER_STA_PS_STATECHG_ENABLE,
919 WMI_PDEV_PARAM_IGMPMLD_AC_OVERRIDE,
920 WMI_PDEV_PARAM_BLOCK_INTERBSS,
921 WMI_PDEV_PARAM_SET_DISABLE_RESET_CMDID,
922 WMI_PDEV_PARAM_SET_MSDU_TTL_CMDID,
923 WMI_PDEV_PARAM_SET_PPDU_DURATION_CMDID,
924 WMI_PDEV_PARAM_TXBF_SOUND_PERIOD_CMDID,
925 WMI_PDEV_PARAM_SET_PROMISC_MODE_CMDID,
926 WMI_PDEV_PARAM_SET_BURST_MODE_CMDID,
927 WMI_PDEV_PARAM_EN_STATS,
928 WMI_PDEV_PARAM_MU_GROUP_POLICY,
929 WMI_PDEV_PARAM_NOISE_DETECTION,
930 WMI_PDEV_PARAM_NOISE_THRESHOLD,
931 WMI_PDEV_PARAM_DPD_ENABLE,
932 WMI_PDEV_PARAM_SET_MCAST_BCAST_ECHO,
933 WMI_PDEV_PARAM_ATF_STRICT_SCH,
934 WMI_PDEV_PARAM_ATF_SCHED_DURATION,
935 WMI_PDEV_PARAM_ANT_PLZN,
936 WMI_PDEV_PARAM_MGMT_RETRY_LIMIT,
937 WMI_PDEV_PARAM_SENSITIVITY_LEVEL,
938 WMI_PDEV_PARAM_SIGNED_TXPOWER_2G,
939 WMI_PDEV_PARAM_SIGNED_TXPOWER_5G,
940 WMI_PDEV_PARAM_ENABLE_PER_TID_AMSDU,
941 WMI_PDEV_PARAM_ENABLE_PER_TID_AMPDU,
942 WMI_PDEV_PARAM_CCA_THRESHOLD,
943 WMI_PDEV_PARAM_RTS_FIXED_RATE,
944 WMI_PDEV_PARAM_PDEV_RESET,
945 WMI_PDEV_PARAM_WAPI_MBSSID_OFFSET,
946 WMI_PDEV_PARAM_ARP_DBG_SRCADDR,
947 WMI_PDEV_PARAM_ARP_DBG_DSTADDR,
948 WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCH,
949 WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCALING_FACTOR,
950 WMI_PDEV_PARAM_CUST_TXPOWER_SCALE,
951 WMI_PDEV_PARAM_ATF_DYNAMIC_ENABLE,
952 WMI_PDEV_PARAM_CTRL_RETRY_LIMIT,
953 WMI_PDEV_PARAM_PROPAGATION_DELAY,
954 WMI_PDEV_PARAM_ENA_ANT_DIV,
955 WMI_PDEV_PARAM_FORCE_CHAIN_ANT,
956 WMI_PDEV_PARAM_ANT_DIV_SELFTEST,
957 WMI_PDEV_PARAM_ANT_DIV_SELFTEST_INTVL,
958 WMI_PDEV_PARAM_STATS_OBSERVATION_PERIOD,
959 WMI_PDEV_PARAM_TX_PPDU_DELAY_BIN_SIZE_MS,
960 WMI_PDEV_PARAM_TX_PPDU_DELAY_ARRAY_LEN,
961 WMI_PDEV_PARAM_TX_MPDU_AGGR_ARRAY_LEN,
962 WMI_PDEV_PARAM_RX_MPDU_AGGR_ARRAY_LEN,
963 WMI_PDEV_PARAM_TX_SCH_DELAY,
964 WMI_PDEV_PARAM_ENABLE_RTS_SIFS_BURSTING,
965 WMI_PDEV_PARAM_MAX_MPDUS_IN_AMPDU,
966 WMI_PDEV_PARAM_PEER_STATS_INFO_ENABLE,
967 WMI_PDEV_PARAM_FAST_PWR_TRANSITION,
968 WMI_PDEV_PARAM_RADIO_CHAN_STATS_ENABLE,
969 WMI_PDEV_PARAM_RADIO_DIAGNOSIS_ENABLE,
970 WMI_PDEV_PARAM_MESH_MCAST_ENABLE,
971 WMI_PDEV_PARAM_SET_CMD_OBSS_PD_THRESHOLD = 0xbc,
972 WMI_PDEV_PARAM_SET_CMD_OBSS_PD_PER_AC = 0xbe,
973 WMI_PDEV_PARAM_ENABLE_SR_PROHIBIT = 0xc6,
974};
975
976enum wmi_tlv_vdev_param {
977 WMI_VDEV_PARAM_RTS_THRESHOLD = 0x1,
978 WMI_VDEV_PARAM_FRAGMENTATION_THRESHOLD,
979 WMI_VDEV_PARAM_BEACON_INTERVAL,
980 WMI_VDEV_PARAM_LISTEN_INTERVAL,
981 WMI_VDEV_PARAM_MULTICAST_RATE,
982 WMI_VDEV_PARAM_MGMT_TX_RATE,
983 WMI_VDEV_PARAM_SLOT_TIME,
984 WMI_VDEV_PARAM_PREAMBLE,
985 WMI_VDEV_PARAM_SWBA_TIME,
986 WMI_VDEV_STATS_UPDATE_PERIOD,
987 WMI_VDEV_PWRSAVE_AGEOUT_TIME,
988 WMI_VDEV_HOST_SWBA_INTERVAL,
989 WMI_VDEV_PARAM_DTIM_PERIOD,
990 WMI_VDEV_OC_SCHEDULER_AIR_TIME_LIMIT,
991 WMI_VDEV_PARAM_WDS,
992 WMI_VDEV_PARAM_ATIM_WINDOW,
993 WMI_VDEV_PARAM_BMISS_COUNT_MAX,
994 WMI_VDEV_PARAM_BMISS_FIRST_BCNT,
995 WMI_VDEV_PARAM_BMISS_FINAL_BCNT,
996 WMI_VDEV_PARAM_FEATURE_WMM,
997 WMI_VDEV_PARAM_CHWIDTH,
998 WMI_VDEV_PARAM_CHEXTOFFSET,
999 WMI_VDEV_PARAM_DISABLE_HTPROTECTION,
1000 WMI_VDEV_PARAM_STA_QUICKKICKOUT,
1001 WMI_VDEV_PARAM_MGMT_RATE,
1002 WMI_VDEV_PARAM_PROTECTION_MODE,
1003 WMI_VDEV_PARAM_FIXED_RATE,
1004 WMI_VDEV_PARAM_SGI,
1005 WMI_VDEV_PARAM_LDPC,
1006 WMI_VDEV_PARAM_TX_STBC,
1007 WMI_VDEV_PARAM_RX_STBC,
1008 WMI_VDEV_PARAM_INTRA_BSS_FWD,
1009 WMI_VDEV_PARAM_DEF_KEYID,
1010 WMI_VDEV_PARAM_NSS,
1011 WMI_VDEV_PARAM_BCAST_DATA_RATE,
1012 WMI_VDEV_PARAM_MCAST_DATA_RATE,
1013 WMI_VDEV_PARAM_MCAST_INDICATE,
1014 WMI_VDEV_PARAM_DHCP_INDICATE,
1015 WMI_VDEV_PARAM_UNKNOWN_DEST_INDICATE,
1016 WMI_VDEV_PARAM_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS,
1017 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS,
1018 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS,
1019 WMI_VDEV_PARAM_AP_ENABLE_NAWDS,
1020 WMI_VDEV_PARAM_ENABLE_RTSCTS,
1021 WMI_VDEV_PARAM_TXBF,
1022 WMI_VDEV_PARAM_PACKET_POWERSAVE,
1023 WMI_VDEV_PARAM_DROP_UNENCRY,
1024 WMI_VDEV_PARAM_TX_ENCAP_TYPE,
1025 WMI_VDEV_PARAM_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS,
1026 WMI_VDEV_PARAM_EARLY_RX_ADJUST_ENABLE,
1027 WMI_VDEV_PARAM_EARLY_RX_TGT_BMISS_NUM,
1028 WMI_VDEV_PARAM_EARLY_RX_BMISS_SAMPLE_CYCLE,
1029 WMI_VDEV_PARAM_EARLY_RX_SLOP_STEP,
1030 WMI_VDEV_PARAM_EARLY_RX_INIT_SLOP,
1031 WMI_VDEV_PARAM_EARLY_RX_ADJUST_PAUSE,
1032 WMI_VDEV_PARAM_TX_PWRLIMIT,
1033 WMI_VDEV_PARAM_SNR_NUM_FOR_CAL,
1034 WMI_VDEV_PARAM_ROAM_FW_OFFLOAD,
1035 WMI_VDEV_PARAM_ENABLE_RMC,
1036 WMI_VDEV_PARAM_IBSS_MAX_BCN_LOST_MS,
1037 WMI_VDEV_PARAM_MAX_RATE,
1038 WMI_VDEV_PARAM_EARLY_RX_DRIFT_SAMPLE,
1039 WMI_VDEV_PARAM_SET_IBSS_TX_FAIL_CNT_THR,
1040 WMI_VDEV_PARAM_EBT_RESYNC_TIMEOUT,
1041 WMI_VDEV_PARAM_AGGR_TRIG_EVENT_ENABLE,
1042 WMI_VDEV_PARAM_IS_IBSS_POWER_SAVE_ALLOWED,
1043 WMI_VDEV_PARAM_IS_POWER_COLLAPSE_ALLOWED,
1044 WMI_VDEV_PARAM_IS_AWAKE_ON_TXRX_ENABLED,
1045 WMI_VDEV_PARAM_INACTIVITY_CNT,
1046 WMI_VDEV_PARAM_TXSP_END_INACTIVITY_TIME_MS,
1047 WMI_VDEV_PARAM_DTIM_POLICY,
1048 WMI_VDEV_PARAM_IBSS_PS_WARMUP_TIME_SECS,
1049 WMI_VDEV_PARAM_IBSS_PS_1RX_CHAIN_IN_ATIM_WINDOW_ENABLE,
1050 WMI_VDEV_PARAM_RX_LEAK_WINDOW,
1051 WMI_VDEV_PARAM_STATS_AVG_FACTOR,
1052 WMI_VDEV_PARAM_DISCONNECT_TH,
1053 WMI_VDEV_PARAM_RTSCTS_RATE,
1054 WMI_VDEV_PARAM_MCC_RTSCTS_PROTECTION_ENABLE,
1055 WMI_VDEV_PARAM_MCC_BROADCAST_PROBE_ENABLE,
1056 WMI_VDEV_PARAM_TXPOWER_SCALE,
1057 WMI_VDEV_PARAM_TXPOWER_SCALE_DECR_DB,
1058 WMI_VDEV_PARAM_MCAST2UCAST_SET,
1059 WMI_VDEV_PARAM_RC_NUM_RETRIES,
1060 WMI_VDEV_PARAM_CABQ_MAXDUR,
1061 WMI_VDEV_PARAM_MFPTEST_SET,
1062 WMI_VDEV_PARAM_RTS_FIXED_RATE,
1063 WMI_VDEV_PARAM_VHT_SGIMASK,
1064 WMI_VDEV_PARAM_VHT80_RATEMASK,
1065 WMI_VDEV_PARAM_PROXY_STA,
1066 WMI_VDEV_PARAM_VIRTUAL_CELL_MODE,
1067 WMI_VDEV_PARAM_RX_DECAP_TYPE,
1068 WMI_VDEV_PARAM_BW_NSS_RATEMASK,
1069 WMI_VDEV_PARAM_SENSOR_AP,
1070 WMI_VDEV_PARAM_BEACON_RATE,
1071 WMI_VDEV_PARAM_DTIM_ENABLE_CTS,
1072 WMI_VDEV_PARAM_STA_KICKOUT,
1073 WMI_VDEV_PARAM_CAPABILITIES,
1074 WMI_VDEV_PARAM_TSF_INCREMENT,
1075 WMI_VDEV_PARAM_AMPDU_PER_AC,
1076 WMI_VDEV_PARAM_RX_FILTER,
1077 WMI_VDEV_PARAM_MGMT_TX_POWER,
1078 WMI_VDEV_PARAM_NON_AGG_SW_RETRY_TH,
1079 WMI_VDEV_PARAM_AGG_SW_RETRY_TH,
1080 WMI_VDEV_PARAM_DISABLE_DYN_BW_RTS,
1081 WMI_VDEV_PARAM_ATF_SSID_SCHED_POLICY,
1082 WMI_VDEV_PARAM_HE_DCM,
1083 WMI_VDEV_PARAM_HE_RANGE_EXT,
1084 WMI_VDEV_PARAM_ENABLE_BCAST_PROBE_RESPONSE,
1085 WMI_VDEV_PARAM_FILS_MAX_CHANNEL_GUARD_TIME,
1086 WMI_VDEV_PARAM_HE_LTF = 0x74,
1087 WMI_VDEV_PARAM_ENABLE_DISABLE_RTT_RESPONDER_ROLE = 0x7d,
1088 WMI_VDEV_PARAM_BA_MODE = 0x7e,
1089 WMI_VDEV_PARAM_AUTORATE_MISC_CFG = 0x80,
1090 WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE = 0x87,
1091 WMI_VDEV_PARAM_6GHZ_PARAMS = 0x99,
1092 WMI_VDEV_PARAM_PROTOTYPE = 0x8000,
1093 WMI_VDEV_PARAM_BSS_COLOR,
1094 WMI_VDEV_PARAM_SET_HEMU_MODE,
1095 WMI_VDEV_PARAM_HEOPS_0_31 = 0x8003,
1096};
1097
1098enum wmi_tlv_peer_flags {
1099 WMI_PEER_AUTH = 0x00000001,
1100 WMI_PEER_QOS = 0x00000002,
1101 WMI_PEER_NEED_PTK_4_WAY = 0x00000004,
1102 WMI_PEER_NEED_GTK_2_WAY = 0x00000010,
1103 WMI_PEER_HE = 0x00000400,
1104 WMI_PEER_APSD = 0x00000800,
1105 WMI_PEER_HT = 0x00001000,
1106 WMI_PEER_40MHZ = 0x00002000,
1107 WMI_PEER_STBC = 0x00008000,
1108 WMI_PEER_LDPC = 0x00010000,
1109 WMI_PEER_DYN_MIMOPS = 0x00020000,
1110 WMI_PEER_STATIC_MIMOPS = 0x00040000,
1111 WMI_PEER_SPATIAL_MUX = 0x00200000,
1112 WMI_PEER_TWT_REQ = 0x00400000,
1113 WMI_PEER_TWT_RESP = 0x00800000,
1114 WMI_PEER_VHT = 0x02000000,
1115 WMI_PEER_80MHZ = 0x04000000,
1116 WMI_PEER_PMF = 0x08000000,
1117 WMI_PEER_IS_P2P_CAPABLE = 0x20000000,
1118 WMI_PEER_160MHZ = 0x40000000,
1119 WMI_PEER_SAFEMODE_EN = 0x80000000,
1120};
1121
1122/** Enum list of TLV Tags for each parameter structure type. */
1123enum wmi_tlv_tag {
1124 WMI_TAG_LAST_RESERVED = 15,
1125 WMI_TAG_FIRST_ARRAY_ENUM,
1126 WMI_TAG_ARRAY_UINT32 = WMI_TAG_FIRST_ARRAY_ENUM,
1127 WMI_TAG_ARRAY_BYTE,
1128 WMI_TAG_ARRAY_STRUCT,
1129 WMI_TAG_ARRAY_FIXED_STRUCT,
1130 WMI_TAG_LAST_ARRAY_ENUM = 31,
1131 WMI_TAG_SERVICE_READY_EVENT,
1132 WMI_TAG_HAL_REG_CAPABILITIES,
1133 WMI_TAG_WLAN_HOST_MEM_REQ,
1134 WMI_TAG_READY_EVENT,
1135 WMI_TAG_SCAN_EVENT,
1136 WMI_TAG_PDEV_TPC_CONFIG_EVENT,
1137 WMI_TAG_CHAN_INFO_EVENT,
1138 WMI_TAG_COMB_PHYERR_RX_HDR,
1139 WMI_TAG_VDEV_START_RESPONSE_EVENT,
1140 WMI_TAG_VDEV_STOPPED_EVENT,
1141 WMI_TAG_VDEV_INSTALL_KEY_COMPLETE_EVENT,
1142 WMI_TAG_PEER_STA_KICKOUT_EVENT,
1143 WMI_TAG_MGMT_RX_HDR,
1144 WMI_TAG_TBTT_OFFSET_EVENT,
1145 WMI_TAG_TX_DELBA_COMPLETE_EVENT,
1146 WMI_TAG_TX_ADDBA_COMPLETE_EVENT,
1147 WMI_TAG_ROAM_EVENT,
1148 WMI_TAG_WOW_EVENT_INFO,
1149 WMI_TAG_WOW_EVENT_INFO_SECTION_BITMAP,
1150 WMI_TAG_RTT_EVENT_HEADER,
1151 WMI_TAG_RTT_ERROR_REPORT_EVENT,
1152 WMI_TAG_RTT_MEAS_EVENT,
1153 WMI_TAG_ECHO_EVENT,
1154 WMI_TAG_FTM_INTG_EVENT,
1155 WMI_TAG_VDEV_GET_KEEPALIVE_EVENT,
1156 WMI_TAG_GPIO_INPUT_EVENT,
1157 WMI_TAG_CSA_EVENT,
1158 WMI_TAG_GTK_OFFLOAD_STATUS_EVENT,
1159 WMI_TAG_IGTK_INFO,
1160 WMI_TAG_DCS_INTERFERENCE_EVENT,
1161 WMI_TAG_ATH_DCS_CW_INT,
1162 WMI_TAG_WLAN_DCS_CW_INT = /* ALIAS */
1163 WMI_TAG_ATH_DCS_CW_INT,
1164 WMI_TAG_ATH_DCS_WLAN_INT_STAT,
1165 WMI_TAG_WLAN_DCS_IM_TGT_STATS_T = /* ALIAS */
1166 WMI_TAG_ATH_DCS_WLAN_INT_STAT,
1167 WMI_TAG_WLAN_PROFILE_CTX_T,
1168 WMI_TAG_WLAN_PROFILE_T,
1169 WMI_TAG_PDEV_QVIT_EVENT,
1170 WMI_TAG_HOST_SWBA_EVENT,
1171 WMI_TAG_TIM_INFO,
1172 WMI_TAG_P2P_NOA_INFO,
1173 WMI_TAG_STATS_EVENT,
1174 WMI_TAG_AVOID_FREQ_RANGES_EVENT,
1175 WMI_TAG_AVOID_FREQ_RANGE_DESC,
1176 WMI_TAG_GTK_REKEY_FAIL_EVENT,
1177 WMI_TAG_INIT_CMD,
1178 WMI_TAG_RESOURCE_CONFIG,
1179 WMI_TAG_WLAN_HOST_MEMORY_CHUNK,
1180 WMI_TAG_START_SCAN_CMD,
1181 WMI_TAG_STOP_SCAN_CMD,
1182 WMI_TAG_SCAN_CHAN_LIST_CMD,
1183 WMI_TAG_CHANNEL,
1184 WMI_TAG_PDEV_SET_REGDOMAIN_CMD,
1185 WMI_TAG_PDEV_SET_PARAM_CMD,
1186 WMI_TAG_PDEV_SET_WMM_PARAMS_CMD,
1187 WMI_TAG_WMM_PARAMS,
1188 WMI_TAG_PDEV_SET_QUIET_CMD,
1189 WMI_TAG_VDEV_CREATE_CMD,
1190 WMI_TAG_VDEV_DELETE_CMD,
1191 WMI_TAG_VDEV_START_REQUEST_CMD,
1192 WMI_TAG_P2P_NOA_DESCRIPTOR,
1193 WMI_TAG_P2P_GO_SET_BEACON_IE,
1194 WMI_TAG_GTK_OFFLOAD_CMD,
1195 WMI_TAG_VDEV_UP_CMD,
1196 WMI_TAG_VDEV_STOP_CMD,
1197 WMI_TAG_VDEV_DOWN_CMD,
1198 WMI_TAG_VDEV_SET_PARAM_CMD,
1199 WMI_TAG_VDEV_INSTALL_KEY_CMD,
1200 WMI_TAG_PEER_CREATE_CMD,
1201 WMI_TAG_PEER_DELETE_CMD,
1202 WMI_TAG_PEER_FLUSH_TIDS_CMD,
1203 WMI_TAG_PEER_SET_PARAM_CMD,
1204 WMI_TAG_PEER_ASSOC_COMPLETE_CMD,
1205 WMI_TAG_VHT_RATE_SET,
1206 WMI_TAG_BCN_TMPL_CMD,
1207 WMI_TAG_PRB_TMPL_CMD,
1208 WMI_TAG_BCN_PRB_INFO,
1209 WMI_TAG_PEER_TID_ADDBA_CMD,
1210 WMI_TAG_PEER_TID_DELBA_CMD,
1211 WMI_TAG_STA_POWERSAVE_MODE_CMD,
1212 WMI_TAG_STA_POWERSAVE_PARAM_CMD,
1213 WMI_TAG_STA_DTIM_PS_METHOD_CMD,
1214 WMI_TAG_ROAM_SCAN_MODE,
1215 WMI_TAG_ROAM_SCAN_RSSI_THRESHOLD,
1216 WMI_TAG_ROAM_SCAN_PERIOD,
1217 WMI_TAG_ROAM_SCAN_RSSI_CHANGE_THRESHOLD,
1218 WMI_TAG_PDEV_SUSPEND_CMD,
1219 WMI_TAG_PDEV_RESUME_CMD,
1220 WMI_TAG_ADD_BCN_FILTER_CMD,
1221 WMI_TAG_RMV_BCN_FILTER_CMD,
1222 WMI_TAG_WOW_ENABLE_CMD,
1223 WMI_TAG_WOW_HOSTWAKEUP_FROM_SLEEP_CMD,
1224 WMI_TAG_STA_UAPSD_AUTO_TRIG_CMD,
1225 WMI_TAG_STA_UAPSD_AUTO_TRIG_PARAM,
1226 WMI_TAG_SET_ARP_NS_OFFLOAD_CMD,
1227 WMI_TAG_ARP_OFFLOAD_TUPLE,
1228 WMI_TAG_NS_OFFLOAD_TUPLE,
1229 WMI_TAG_FTM_INTG_CMD,
1230 WMI_TAG_STA_KEEPALIVE_CMD,
1231 WMI_TAG_STA_KEEPALIVE_ARP_RESPONSE,
1232 WMI_TAG_P2P_SET_VENDOR_IE_DATA_CMD,
1233 WMI_TAG_AP_PS_PEER_CMD,
1234 WMI_TAG_PEER_RATE_RETRY_SCHED_CMD,
1235 WMI_TAG_WLAN_PROFILE_TRIGGER_CMD,
1236 WMI_TAG_WLAN_PROFILE_SET_HIST_INTVL_CMD,
1237 WMI_TAG_WLAN_PROFILE_GET_PROF_DATA_CMD,
1238 WMI_TAG_WLAN_PROFILE_ENABLE_PROFILE_ID_CMD,
1239 WMI_TAG_WOW_DEL_PATTERN_CMD,
1240 WMI_TAG_WOW_ADD_DEL_EVT_CMD,
1241 WMI_TAG_RTT_MEASREQ_HEAD,
1242 WMI_TAG_RTT_MEASREQ_BODY,
1243 WMI_TAG_RTT_TSF_CMD,
1244 WMI_TAG_VDEV_SPECTRAL_CONFIGURE_CMD,
1245 WMI_TAG_VDEV_SPECTRAL_ENABLE_CMD,
1246 WMI_TAG_REQUEST_STATS_CMD,
1247 WMI_TAG_NLO_CONFIG_CMD,
1248 WMI_TAG_NLO_CONFIGURED_PARAMETERS,
1249 WMI_TAG_CSA_OFFLOAD_ENABLE_CMD,
1250 WMI_TAG_CSA_OFFLOAD_CHANSWITCH_CMD,
1251 WMI_TAG_CHATTER_SET_MODE_CMD,
1252 WMI_TAG_ECHO_CMD,
1253 WMI_TAG_VDEV_SET_KEEPALIVE_CMD,
1254 WMI_TAG_VDEV_GET_KEEPALIVE_CMD,
1255 WMI_TAG_FORCE_FW_HANG_CMD,
1256 WMI_TAG_GPIO_CONFIG_CMD,
1257 WMI_TAG_GPIO_OUTPUT_CMD,
1258 WMI_TAG_PEER_ADD_WDS_ENTRY_CMD,
1259 WMI_TAG_PEER_REMOVE_WDS_ENTRY_CMD,
1260 WMI_TAG_BCN_TX_HDR,
1261 WMI_TAG_BCN_SEND_FROM_HOST_CMD,
1262 WMI_TAG_MGMT_TX_HDR,
1263 WMI_TAG_ADDBA_CLEAR_RESP_CMD,
1264 WMI_TAG_ADDBA_SEND_CMD,
1265 WMI_TAG_DELBA_SEND_CMD,
1266 WMI_TAG_ADDBA_SETRESPONSE_CMD,
1267 WMI_TAG_SEND_SINGLEAMSDU_CMD,
1268 WMI_TAG_PDEV_PKTLOG_ENABLE_CMD,
1269 WMI_TAG_PDEV_PKTLOG_DISABLE_CMD,
1270 WMI_TAG_PDEV_SET_HT_IE_CMD,
1271 WMI_TAG_PDEV_SET_VHT_IE_CMD,
1272 WMI_TAG_PDEV_SET_DSCP_TID_MAP_CMD,
1273 WMI_TAG_PDEV_GREEN_AP_PS_ENABLE_CMD,
1274 WMI_TAG_PDEV_GET_TPC_CONFIG_CMD,
1275 WMI_TAG_PDEV_SET_BASE_MACADDR_CMD,
1276 WMI_TAG_PEER_MCAST_GROUP_CMD,
1277 WMI_TAG_ROAM_AP_PROFILE,
1278 WMI_TAG_AP_PROFILE,
1279 WMI_TAG_SCAN_SCH_PRIORITY_TABLE_CMD,
1280 WMI_TAG_PDEV_DFS_ENABLE_CMD,
1281 WMI_TAG_PDEV_DFS_DISABLE_CMD,
1282 WMI_TAG_WOW_ADD_PATTERN_CMD,
1283 WMI_TAG_WOW_BITMAP_PATTERN_T,
1284 WMI_TAG_WOW_IPV4_SYNC_PATTERN_T,
1285 WMI_TAG_WOW_IPV6_SYNC_PATTERN_T,
1286 WMI_TAG_WOW_MAGIC_PATTERN_CMD,
1287 WMI_TAG_SCAN_UPDATE_REQUEST_CMD,
1288 WMI_TAG_CHATTER_PKT_COALESCING_FILTER,
1289 WMI_TAG_CHATTER_COALESCING_ADD_FILTER_CMD,
1290 WMI_TAG_CHATTER_COALESCING_DELETE_FILTER_CMD,
1291 WMI_TAG_CHATTER_COALESCING_QUERY_CMD,
1292 WMI_TAG_TXBF_CMD,
1293 WMI_TAG_DEBUG_LOG_CONFIG_CMD,
1294 WMI_TAG_NLO_EVENT,
1295 WMI_TAG_CHATTER_QUERY_REPLY_EVENT,
1296 WMI_TAG_UPLOAD_H_HDR,
1297 WMI_TAG_CAPTURE_H_EVENT_HDR,
1298 WMI_TAG_VDEV_WNM_SLEEPMODE_CMD,
1299 WMI_TAG_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD,
1300 WMI_TAG_VDEV_WMM_ADDTS_CMD,
1301 WMI_TAG_VDEV_WMM_DELTS_CMD,
1302 WMI_TAG_VDEV_SET_WMM_PARAMS_CMD,
1303 WMI_TAG_TDLS_SET_STATE_CMD,
1304 WMI_TAG_TDLS_PEER_UPDATE_CMD,
1305 WMI_TAG_TDLS_PEER_EVENT,
1306 WMI_TAG_TDLS_PEER_CAPABILITIES,
1307 WMI_TAG_VDEV_MCC_SET_TBTT_MODE_CMD,
1308 WMI_TAG_ROAM_CHAN_LIST,
1309 WMI_TAG_VDEV_MCC_BCN_INTVL_CHANGE_EVENT,
1310 WMI_TAG_RESMGR_ADAPTIVE_OCS_ENABLE_DISABLE_CMD,
1311 WMI_TAG_RESMGR_SET_CHAN_TIME_QUOTA_CMD,
1312 WMI_TAG_RESMGR_SET_CHAN_LATENCY_CMD,
1313 WMI_TAG_BA_REQ_SSN_CMD,
1314 WMI_TAG_BA_RSP_SSN_EVENT,
1315 WMI_TAG_STA_SMPS_FORCE_MODE_CMD,
1316 WMI_TAG_SET_MCASTBCAST_FILTER_CMD,
1317 WMI_TAG_P2P_SET_OPPPS_CMD,
1318 WMI_TAG_P2P_SET_NOA_CMD,
1319 WMI_TAG_BA_REQ_SSN_CMD_SUB_STRUCT_PARAM,
1320 WMI_TAG_BA_REQ_SSN_EVENT_SUB_STRUCT_PARAM,
1321 WMI_TAG_STA_SMPS_PARAM_CMD,
1322 WMI_TAG_VDEV_SET_GTX_PARAMS_CMD,
1323 WMI_TAG_MCC_SCHED_TRAFFIC_STATS_CMD,
1324 WMI_TAG_MCC_SCHED_STA_TRAFFIC_STATS,
1325 WMI_TAG_OFFLOAD_BCN_TX_STATUS_EVENT,
1326 WMI_TAG_P2P_NOA_EVENT,
1327 WMI_TAG_HB_SET_ENABLE_CMD,
1328 WMI_TAG_HB_SET_TCP_PARAMS_CMD,
1329 WMI_TAG_HB_SET_TCP_PKT_FILTER_CMD,
1330 WMI_TAG_HB_SET_UDP_PARAMS_CMD,
1331 WMI_TAG_HB_SET_UDP_PKT_FILTER_CMD,
1332 WMI_TAG_HB_IND_EVENT,
1333 WMI_TAG_TX_PAUSE_EVENT,
1334 WMI_TAG_RFKILL_EVENT,
1335 WMI_TAG_DFS_RADAR_EVENT,
1336 WMI_TAG_DFS_PHYERR_FILTER_ENA_CMD,
1337 WMI_TAG_DFS_PHYERR_FILTER_DIS_CMD,
1338 WMI_TAG_BATCH_SCAN_RESULT_SCAN_LIST,
1339 WMI_TAG_BATCH_SCAN_RESULT_NETWORK_INFO,
1340 WMI_TAG_BATCH_SCAN_ENABLE_CMD,
1341 WMI_TAG_BATCH_SCAN_DISABLE_CMD,
1342 WMI_TAG_BATCH_SCAN_TRIGGER_RESULT_CMD,
1343 WMI_TAG_BATCH_SCAN_ENABLED_EVENT,
1344 WMI_TAG_BATCH_SCAN_RESULT_EVENT,
1345 WMI_TAG_VDEV_PLMREQ_START_CMD,
1346 WMI_TAG_VDEV_PLMREQ_STOP_CMD,
1347 WMI_TAG_THERMAL_MGMT_CMD,
1348 WMI_TAG_THERMAL_MGMT_EVENT,
1349 WMI_TAG_PEER_INFO_REQ_CMD,
1350 WMI_TAG_PEER_INFO_EVENT,
1351 WMI_TAG_PEER_INFO,
1352 WMI_TAG_PEER_TX_FAIL_CNT_THR_EVENT,
1353 WMI_TAG_RMC_SET_MODE_CMD,
1354 WMI_TAG_RMC_SET_ACTION_PERIOD_CMD,
1355 WMI_TAG_RMC_CONFIG_CMD,
1356 WMI_TAG_MHF_OFFLOAD_SET_MODE_CMD,
1357 WMI_TAG_MHF_OFFLOAD_PLUMB_ROUTING_TABLE_CMD,
1358 WMI_TAG_ADD_PROACTIVE_ARP_RSP_PATTERN_CMD,
1359 WMI_TAG_DEL_PROACTIVE_ARP_RSP_PATTERN_CMD,
1360 WMI_TAG_NAN_CMD_PARAM,
1361 WMI_TAG_NAN_EVENT_HDR,
1362 WMI_TAG_PDEV_L1SS_TRACK_EVENT,
1363 WMI_TAG_DIAG_DATA_CONTAINER_EVENT,
1364 WMI_TAG_MODEM_POWER_STATE_CMD_PARAM,
1365 WMI_TAG_PEER_GET_ESTIMATED_LINKSPEED_CMD,
1366 WMI_TAG_PEER_ESTIMATED_LINKSPEED_EVENT,
1367 WMI_TAG_AGGR_STATE_TRIG_EVENT,
1368 WMI_TAG_MHF_OFFLOAD_ROUTING_TABLE_ENTRY,
1369 WMI_TAG_ROAM_SCAN_CMD,
1370 WMI_TAG_REQ_STATS_EXT_CMD,
1371 WMI_TAG_STATS_EXT_EVENT,
1372 WMI_TAG_OBSS_SCAN_ENABLE_CMD,
1373 WMI_TAG_OBSS_SCAN_DISABLE_CMD,
1374 WMI_TAG_OFFLOAD_PRB_RSP_TX_STATUS_EVENT,
1375 WMI_TAG_PDEV_SET_LED_CONFIG_CMD,
1376 WMI_TAG_HOST_AUTO_SHUTDOWN_CFG_CMD,
1377 WMI_TAG_HOST_AUTO_SHUTDOWN_EVENT,
1378 WMI_TAG_UPDATE_WHAL_MIB_STATS_EVENT,
1379 WMI_TAG_CHAN_AVOID_UPDATE_CMD_PARAM,
1380 WMI_TAG_WOW_IOAC_PKT_PATTERN_T,
1381 WMI_TAG_WOW_IOAC_TMR_PATTERN_T,
1382 WMI_TAG_WOW_IOAC_ADD_KEEPALIVE_CMD,
1383 WMI_TAG_WOW_IOAC_DEL_KEEPALIVE_CMD,
1384 WMI_TAG_WOW_IOAC_KEEPALIVE_T,
1385 WMI_TAG_WOW_IOAC_ADD_PATTERN_CMD,
1386 WMI_TAG_WOW_IOAC_DEL_PATTERN_CMD,
1387 WMI_TAG_START_LINK_STATS_CMD,
1388 WMI_TAG_CLEAR_LINK_STATS_CMD,
1389 WMI_TAG_REQUEST_LINK_STATS_CMD,
1390 WMI_TAG_IFACE_LINK_STATS_EVENT,
1391 WMI_TAG_RADIO_LINK_STATS_EVENT,
1392 WMI_TAG_PEER_STATS_EVENT,
1393 WMI_TAG_CHANNEL_STATS,
1394 WMI_TAG_RADIO_LINK_STATS,
1395 WMI_TAG_RATE_STATS,
1396 WMI_TAG_PEER_LINK_STATS,
1397 WMI_TAG_WMM_AC_STATS,
1398 WMI_TAG_IFACE_LINK_STATS,
1399 WMI_TAG_LPI_MGMT_SNOOPING_CONFIG_CMD,
1400 WMI_TAG_LPI_START_SCAN_CMD,
1401 WMI_TAG_LPI_STOP_SCAN_CMD,
1402 WMI_TAG_LPI_RESULT_EVENT,
1403 WMI_TAG_PEER_STATE_EVENT,
1404 WMI_TAG_EXTSCAN_BUCKET_CMD,
1405 WMI_TAG_EXTSCAN_BUCKET_CHANNEL_EVENT,
1406 WMI_TAG_EXTSCAN_START_CMD,
1407 WMI_TAG_EXTSCAN_STOP_CMD,
1408 WMI_TAG_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMD,
1409 WMI_TAG_EXTSCAN_WLAN_CHANGE_BSSID_PARAM_CMD,
1410 WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMD,
1411 WMI_TAG_EXTSCAN_GET_CACHED_RESULTS_CMD,
1412 WMI_TAG_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMD,
1413 WMI_TAG_EXTSCAN_SET_CAPABILITIES_CMD,
1414 WMI_TAG_EXTSCAN_GET_CAPABILITIES_CMD,
1415 WMI_TAG_EXTSCAN_OPERATION_EVENT,
1416 WMI_TAG_EXTSCAN_START_STOP_EVENT,
1417 WMI_TAG_EXTSCAN_TABLE_USAGE_EVENT,
1418 WMI_TAG_EXTSCAN_WLAN_DESCRIPTOR_EVENT,
1419 WMI_TAG_EXTSCAN_RSSI_INFO_EVENT,
1420 WMI_TAG_EXTSCAN_CACHED_RESULTS_EVENT,
1421 WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULTS_EVENT,
1422 WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULT_BSSID_EVENT,
1423 WMI_TAG_EXTSCAN_HOTLIST_MATCH_EVENT,
1424 WMI_TAG_EXTSCAN_CAPABILITIES_EVENT,
1425 WMI_TAG_EXTSCAN_CACHE_CAPABILITIES_EVENT,
1426 WMI_TAG_EXTSCAN_WLAN_CHANGE_MONITOR_CAPABILITIES_EVENT,
1427 WMI_TAG_EXTSCAN_HOTLIST_MONITOR_CAPABILITIES_EVENT,
1428 WMI_TAG_D0_WOW_ENABLE_DISABLE_CMD,
1429 WMI_TAG_D0_WOW_DISABLE_ACK_EVENT,
1430 WMI_TAG_UNIT_TEST_CMD,
1431 WMI_TAG_ROAM_OFFLOAD_TLV_PARAM,
1432 WMI_TAG_ROAM_11I_OFFLOAD_TLV_PARAM,
1433 WMI_TAG_ROAM_11R_OFFLOAD_TLV_PARAM,
1434 WMI_TAG_ROAM_ESE_OFFLOAD_TLV_PARAM,
1435 WMI_TAG_ROAM_SYNCH_EVENT,
1436 WMI_TAG_ROAM_SYNCH_COMPLETE,
1437 WMI_TAG_EXTWOW_ENABLE_CMD,
1438 WMI_TAG_EXTWOW_SET_APP_TYPE1_PARAMS_CMD,
1439 WMI_TAG_EXTWOW_SET_APP_TYPE2_PARAMS_CMD,
1440 WMI_TAG_LPI_STATUS_EVENT,
1441 WMI_TAG_LPI_HANDOFF_EVENT,
1442 WMI_TAG_VDEV_RATE_STATS_EVENT,
1443 WMI_TAG_VDEV_RATE_HT_INFO,
1444 WMI_TAG_RIC_REQUEST,
1445 WMI_TAG_PDEV_GET_TEMPERATURE_CMD,
1446 WMI_TAG_PDEV_TEMPERATURE_EVENT,
1447 WMI_TAG_SET_DHCP_SERVER_OFFLOAD_CMD,
1448 WMI_TAG_TPC_CHAINMASK_CONFIG_CMD,
1449 WMI_TAG_RIC_TSPEC,
1450 WMI_TAG_TPC_CHAINMASK_CONFIG,
1451 WMI_TAG_IPA_OFFLOAD_ENABLE_DISABLE_CMD,
1452 WMI_TAG_SCAN_PROB_REQ_OUI_CMD,
1453 WMI_TAG_KEY_MATERIAL,
1454 WMI_TAG_TDLS_SET_OFFCHAN_MODE_CMD,
1455 WMI_TAG_SET_LED_FLASHING_CMD,
1456 WMI_TAG_MDNS_OFFLOAD_CMD,
1457 WMI_TAG_MDNS_SET_FQDN_CMD,
1458 WMI_TAG_MDNS_SET_RESP_CMD,
1459 WMI_TAG_MDNS_GET_STATS_CMD,
1460 WMI_TAG_MDNS_STATS_EVENT,
1461 WMI_TAG_ROAM_INVOKE_CMD,
1462 WMI_TAG_PDEV_RESUME_EVENT,
1463 WMI_TAG_PDEV_SET_ANTENNA_DIVERSITY_CMD,
1464 WMI_TAG_SAP_OFL_ENABLE_CMD,
1465 WMI_TAG_SAP_OFL_ADD_STA_EVENT,
1466 WMI_TAG_SAP_OFL_DEL_STA_EVENT,
1467 WMI_TAG_APFIND_CMD_PARAM,
1468 WMI_TAG_APFIND_EVENT_HDR,
1469 WMI_TAG_OCB_SET_SCHED_CMD,
1470 WMI_TAG_OCB_SET_SCHED_EVENT,
1471 WMI_TAG_OCB_SET_CONFIG_CMD,
1472 WMI_TAG_OCB_SET_CONFIG_RESP_EVENT,
1473 WMI_TAG_OCB_SET_UTC_TIME_CMD,
1474 WMI_TAG_OCB_START_TIMING_ADVERT_CMD,
1475 WMI_TAG_OCB_STOP_TIMING_ADVERT_CMD,
1476 WMI_TAG_OCB_GET_TSF_TIMER_CMD,
1477 WMI_TAG_OCB_GET_TSF_TIMER_RESP_EVENT,
1478 WMI_TAG_DCC_GET_STATS_CMD,
1479 WMI_TAG_DCC_CHANNEL_STATS_REQUEST,
1480 WMI_TAG_DCC_GET_STATS_RESP_EVENT,
1481 WMI_TAG_DCC_CLEAR_STATS_CMD,
1482 WMI_TAG_DCC_UPDATE_NDL_CMD,
1483 WMI_TAG_DCC_UPDATE_NDL_RESP_EVENT,
1484 WMI_TAG_DCC_STATS_EVENT,
1485 WMI_TAG_OCB_CHANNEL,
1486 WMI_TAG_OCB_SCHEDULE_ELEMENT,
1487 WMI_TAG_DCC_NDL_STATS_PER_CHANNEL,
1488 WMI_TAG_DCC_NDL_CHAN,
1489 WMI_TAG_QOS_PARAMETER,
1490 WMI_TAG_DCC_NDL_ACTIVE_STATE_CONFIG,
1491 WMI_TAG_ROAM_SCAN_EXTENDED_THRESHOLD_PARAM,
1492 WMI_TAG_ROAM_FILTER,
1493 WMI_TAG_PASSPOINT_CONFIG_CMD,
1494 WMI_TAG_PASSPOINT_EVENT_HDR,
1495 WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMD,
1496 WMI_TAG_EXTSCAN_HOTLIST_SSID_MATCH_EVENT,
1497 WMI_TAG_VDEV_TSF_TSTAMP_ACTION_CMD,
1498 WMI_TAG_VDEV_TSF_REPORT_EVENT,
1499 WMI_TAG_GET_FW_MEM_DUMP,
1500 WMI_TAG_UPDATE_FW_MEM_DUMP,
1501 WMI_TAG_FW_MEM_DUMP_PARAMS,
1502 WMI_TAG_DEBUG_MESG_FLUSH,
1503 WMI_TAG_DEBUG_MESG_FLUSH_COMPLETE,
1504 WMI_TAG_PEER_SET_RATE_REPORT_CONDITION,
1505 WMI_TAG_ROAM_SUBNET_CHANGE_CONFIG,
1506 WMI_TAG_VDEV_SET_IE_CMD,
1507 WMI_TAG_RSSI_BREACH_MONITOR_CONFIG,
1508 WMI_TAG_RSSI_BREACH_EVENT,
1509 WMI_TAG_WOW_EVENT_INITIAL_WAKEUP,
1510 WMI_TAG_SOC_SET_PCL_CMD,
1511 WMI_TAG_SOC_SET_HW_MODE_CMD,
1512 WMI_TAG_SOC_SET_HW_MODE_RESPONSE_EVENT,
1513 WMI_TAG_SOC_HW_MODE_TRANSITION_EVENT,
1514 WMI_TAG_VDEV_TXRX_STREAMS,
1515 WMI_TAG_SOC_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY,
1516 WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_CMD,
1517 WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_RESPONSE_EVENT,
1518 WMI_TAG_WOW_IOAC_SOCK_PATTERN_T,
1519 WMI_TAG_WOW_ENABLE_ICMPV6_NA_FLT_CMD,
1520 WMI_TAG_DIAG_EVENT_LOG_CONFIG,
1521 WMI_TAG_DIAG_EVENT_LOG_SUPPORTED_EVENT_FIXED_PARAMS,
1522 WMI_TAG_PACKET_FILTER_CONFIG,
1523 WMI_TAG_PACKET_FILTER_ENABLE,
1524 WMI_TAG_SAP_SET_BLACKLIST_PARAM_CMD,
1525 WMI_TAG_MGMT_TX_SEND_CMD,
1526 WMI_TAG_MGMT_TX_COMPL_EVENT,
1527 WMI_TAG_SOC_SET_ANTENNA_MODE_CMD,
1528 WMI_TAG_WOW_UDP_SVC_OFLD_CMD,
1529 WMI_TAG_LRO_INFO_CMD,
1530 WMI_TAG_ROAM_EARLYSTOP_RSSI_THRES_PARAM,
1531 WMI_TAG_SERVICE_READY_EXT_EVENT,
1532 WMI_TAG_MAWC_SENSOR_REPORT_IND_CMD,
1533 WMI_TAG_MAWC_ENABLE_SENSOR_EVENT,
1534 WMI_TAG_ROAM_CONFIGURE_MAWC_CMD,
1535 WMI_TAG_NLO_CONFIGURE_MAWC_CMD,
1536 WMI_TAG_EXTSCAN_CONFIGURE_MAWC_CMD,
1537 WMI_TAG_PEER_ASSOC_CONF_EVENT,
1538 WMI_TAG_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMD,
1539 WMI_TAG_AP_PS_EGAP_PARAM_CMD,
1540 WMI_TAG_AP_PS_EGAP_INFO_EVENT,
1541 WMI_TAG_PMF_OFFLOAD_SET_SA_QUERY_CMD,
1542 WMI_TAG_TRANSFER_DATA_TO_FLASH_CMD,
1543 WMI_TAG_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENT,
1544 WMI_TAG_SCPC_EVENT,
1545 WMI_TAG_AP_PS_EGAP_INFO_CHAINMASK_LIST,
1546 WMI_TAG_STA_SMPS_FORCE_MODE_COMPLETE_EVENT,
1547 WMI_TAG_BPF_GET_CAPABILITY_CMD,
1548 WMI_TAG_BPF_CAPABILITY_INFO_EVT,
1549 WMI_TAG_BPF_GET_VDEV_STATS_CMD,
1550 WMI_TAG_BPF_VDEV_STATS_INFO_EVT,
1551 WMI_TAG_BPF_SET_VDEV_INSTRUCTIONS_CMD,
1552 WMI_TAG_BPF_DEL_VDEV_INSTRUCTIONS_CMD,
1553 WMI_TAG_VDEV_DELETE_RESP_EVENT,
1554 WMI_TAG_PEER_DELETE_RESP_EVENT,
1555 WMI_TAG_ROAM_DENSE_THRES_PARAM,
1556 WMI_TAG_ENLO_CANDIDATE_SCORE_PARAM,
1557 WMI_TAG_PEER_UPDATE_WDS_ENTRY_CMD,
1558 WMI_TAG_VDEV_CONFIG_RATEMASK,
1559 WMI_TAG_PDEV_FIPS_CMD,
1560 WMI_TAG_PDEV_SMART_ANT_ENABLE_CMD,
1561 WMI_TAG_PDEV_SMART_ANT_SET_RX_ANTENNA_CMD,
1562 WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_CMD,
1563 WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_CMD,
1564 WMI_TAG_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMD,
1565 WMI_TAG_PDEV_SET_ANT_SWITCH_TBL_CMD,
1566 WMI_TAG_PDEV_SET_CTL_TABLE_CMD,
1567 WMI_TAG_PDEV_SET_MIMOGAIN_TABLE_CMD,
1568 WMI_TAG_FWTEST_SET_PARAM_CMD,
1569 WMI_TAG_PEER_ATF_REQUEST,
1570 WMI_TAG_VDEV_ATF_REQUEST,
1571 WMI_TAG_PDEV_GET_ANI_CCK_CONFIG_CMD,
1572 WMI_TAG_PDEV_GET_ANI_OFDM_CONFIG_CMD,
1573 WMI_TAG_INST_RSSI_STATS_RESP,
1574 WMI_TAG_MED_UTIL_REPORT_EVENT,
1575 WMI_TAG_PEER_STA_PS_STATECHANGE_EVENT,
1576 WMI_TAG_WDS_ADDR_EVENT,
1577 WMI_TAG_PEER_RATECODE_LIST_EVENT,
1578 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENT,
1579 WMI_TAG_PDEV_TPC_EVENT,
1580 WMI_TAG_ANI_OFDM_EVENT,
1581 WMI_TAG_ANI_CCK_EVENT,
1582 WMI_TAG_PDEV_CHANNEL_HOPPING_EVENT,
1583 WMI_TAG_PDEV_FIPS_EVENT,
1584 WMI_TAG_ATF_PEER_INFO,
1585 WMI_TAG_PDEV_GET_TPC_CMD,
1586 WMI_TAG_VDEV_FILTER_NRP_CONFIG_CMD,
1587 WMI_TAG_QBOOST_CFG_CMD,
1588 WMI_TAG_PDEV_SMART_ANT_GPIO_HANDLE,
1589 WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_SERIES,
1590 WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_PARAM,
1591 WMI_TAG_PDEV_SET_ANT_CTRL_CHAIN,
1592 WMI_TAG_PEER_CCK_OFDM_RATE_INFO,
1593 WMI_TAG_PEER_MCS_RATE_INFO,
1594 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBR,
1595 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBM,
1596 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_FREQNUM,
1597 WMI_TAG_MU_REPORT_TOTAL_MU,
1598 WMI_TAG_VDEV_SET_DSCP_TID_MAP_CMD,
1599 WMI_TAG_ROAM_SET_MBO,
1600 WMI_TAG_MIB_STATS_ENABLE_CMD,
1601 WMI_TAG_NAN_DISC_IFACE_CREATED_EVENT,
1602 WMI_TAG_NAN_DISC_IFACE_DELETED_EVENT,
1603 WMI_TAG_NAN_STARTED_CLUSTER_EVENT,
1604 WMI_TAG_NAN_JOINED_CLUSTER_EVENT,
1605 WMI_TAG_NDI_GET_CAP_REQ,
1606 WMI_TAG_NDP_INITIATOR_REQ,
1607 WMI_TAG_NDP_RESPONDER_REQ,
1608 WMI_TAG_NDP_END_REQ,
1609 WMI_TAG_NDI_CAP_RSP_EVENT,
1610 WMI_TAG_NDP_INITIATOR_RSP_EVENT,
1611 WMI_TAG_NDP_RESPONDER_RSP_EVENT,
1612 WMI_TAG_NDP_END_RSP_EVENT,
1613 WMI_TAG_NDP_INDICATION_EVENT,
1614 WMI_TAG_NDP_CONFIRM_EVENT,
1615 WMI_TAG_NDP_END_INDICATION_EVENT,
1616 WMI_TAG_VDEV_SET_QUIET_CMD,
1617 WMI_TAG_PDEV_SET_PCL_CMD,
1618 WMI_TAG_PDEV_SET_HW_MODE_CMD,
1619 WMI_TAG_PDEV_SET_MAC_CONFIG_CMD,
1620 WMI_TAG_PDEV_SET_ANTENNA_MODE_CMD,
1621 WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_EVENT,
1622 WMI_TAG_PDEV_HW_MODE_TRANSITION_EVENT,
1623 WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY,
1624 WMI_TAG_PDEV_SET_MAC_CONFIG_RESPONSE_EVENT,
1625 WMI_TAG_COEX_CONFIG_CMD,
1626 WMI_TAG_CONFIG_ENHANCED_MCAST_FILTER,
1627 WMI_TAG_CHAN_AVOID_RPT_ALLOW_CMD,
1628 WMI_TAG_SET_PERIODIC_CHANNEL_STATS_CONFIG,
1629 WMI_TAG_VDEV_SET_CUSTOM_AGGR_SIZE_CMD,
1630 WMI_TAG_PDEV_WAL_POWER_DEBUG_CMD,
1631 WMI_TAG_MAC_PHY_CAPABILITIES,
1632 WMI_TAG_HW_MODE_CAPABILITIES,
1633 WMI_TAG_SOC_MAC_PHY_HW_MODE_CAPS,
1634 WMI_TAG_HAL_REG_CAPABILITIES_EXT,
1635 WMI_TAG_SOC_HAL_REG_CAPABILITIES,
1636 WMI_TAG_VDEV_WISA_CMD,
1637 WMI_TAG_TX_POWER_LEVEL_STATS_EVT,
1638 WMI_TAG_SCAN_ADAPTIVE_DWELL_PARAMETERS_TLV,
1639 WMI_TAG_SCAN_ADAPTIVE_DWELL_CONFIG,
1640 WMI_TAG_WOW_SET_ACTION_WAKE_UP_CMD,
1641 WMI_TAG_NDP_END_RSP_PER_NDI,
1642 WMI_TAG_PEER_BWF_REQUEST,
1643 WMI_TAG_BWF_PEER_INFO,
1644 WMI_TAG_DBGLOG_TIME_STAMP_SYNC_CMD,
1645 WMI_TAG_RMC_SET_LEADER_CMD,
1646 WMI_TAG_RMC_MANUAL_LEADER_EVENT,
1647 WMI_TAG_PER_CHAIN_RSSI_STATS,
1648 WMI_TAG_RSSI_STATS,
1649 WMI_TAG_P2P_LO_START_CMD,
1650 WMI_TAG_P2P_LO_STOP_CMD,
1651 WMI_TAG_P2P_LO_STOPPED_EVENT,
1652 WMI_TAG_REORDER_QUEUE_SETUP_CMD,
1653 WMI_TAG_REORDER_QUEUE_REMOVE_CMD,
1654 WMI_TAG_SET_MULTIPLE_MCAST_FILTER_CMD,
1655 WMI_TAG_MGMT_TX_COMPL_BUNDLE_EVENT,
1656 WMI_TAG_READ_DATA_FROM_FLASH_CMD,
1657 WMI_TAG_READ_DATA_FROM_FLASH_EVENT,
1658 WMI_TAG_PDEV_SET_REORDER_TIMEOUT_VAL_CMD,
1659 WMI_TAG_PEER_SET_RX_BLOCKSIZE_CMD,
1660 WMI_TAG_PDEV_SET_WAKEUP_CONFIG_CMDID,
1661 WMI_TAG_TLV_BUF_LEN_PARAM,
1662 WMI_TAG_SERVICE_AVAILABLE_EVENT,
1663 WMI_TAG_PEER_ANTDIV_INFO_REQ_CMD,
1664 WMI_TAG_PEER_ANTDIV_INFO_EVENT,
1665 WMI_TAG_PEER_ANTDIV_INFO,
1666 WMI_TAG_PDEV_GET_ANTDIV_STATUS_CMD,
1667 WMI_TAG_PDEV_ANTDIV_STATUS_EVENT,
1668 WMI_TAG_MNT_FILTER_CMD,
1669 WMI_TAG_GET_CHIP_POWER_STATS_CMD,
1670 WMI_TAG_PDEV_CHIP_POWER_STATS_EVENT,
1671 WMI_TAG_COEX_GET_ANTENNA_ISOLATION_CMD,
1672 WMI_TAG_COEX_REPORT_ISOLATION_EVENT,
1673 WMI_TAG_CHAN_CCA_STATS,
1674 WMI_TAG_PEER_SIGNAL_STATS,
1675 WMI_TAG_TX_STATS,
1676 WMI_TAG_PEER_AC_TX_STATS,
1677 WMI_TAG_RX_STATS,
1678 WMI_TAG_PEER_AC_RX_STATS,
1679 WMI_TAG_REPORT_STATS_EVENT,
1680 WMI_TAG_CHAN_CCA_STATS_THRESH,
1681 WMI_TAG_PEER_SIGNAL_STATS_THRESH,
1682 WMI_TAG_TX_STATS_THRESH,
1683 WMI_TAG_RX_STATS_THRESH,
1684 WMI_TAG_PDEV_SET_STATS_THRESHOLD_CMD,
1685 WMI_TAG_REQUEST_WLAN_STATS_CMD,
1686 WMI_TAG_RX_AGGR_FAILURE_EVENT,
1687 WMI_TAG_RX_AGGR_FAILURE_INFO,
1688 WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMD,
1689 WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENT,
1690 WMI_TAG_PDEV_BAND_TO_MAC,
1691 WMI_TAG_TBTT_OFFSET_INFO,
1692 WMI_TAG_TBTT_OFFSET_EXT_EVENT,
1693 WMI_TAG_SAR_LIMITS_CMD,
1694 WMI_TAG_SAR_LIMIT_CMD_ROW,
1695 WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMD,
1696 WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMD,
1697 WMI_TAG_VDEV_ADFS_CH_CFG_CMD,
1698 WMI_TAG_VDEV_ADFS_OCAC_ABORT_CMD,
1699 WMI_TAG_PDEV_DFS_RADAR_DETECTION_EVENT,
1700 WMI_TAG_VDEV_ADFS_OCAC_COMPLETE_EVENT,
1701 WMI_TAG_VDEV_DFS_CAC_COMPLETE_EVENT,
1702 WMI_TAG_VENDOR_OUI,
1703 WMI_TAG_REQUEST_RCPI_CMD,
1704 WMI_TAG_UPDATE_RCPI_EVENT,
1705 WMI_TAG_REQUEST_PEER_STATS_INFO_CMD,
1706 WMI_TAG_PEER_STATS_INFO,
1707 WMI_TAG_PEER_STATS_INFO_EVENT,
1708 WMI_TAG_PKGID_EVENT,
1709 WMI_TAG_CONNECTED_NLO_RSSI_PARAMS,
1710 WMI_TAG_SET_CURRENT_COUNTRY_CMD,
1711 WMI_TAG_REGULATORY_RULE_STRUCT,
1712 WMI_TAG_REG_CHAN_LIST_CC_EVENT,
1713 WMI_TAG_11D_SCAN_START_CMD,
1714 WMI_TAG_11D_SCAN_STOP_CMD,
1715 WMI_TAG_11D_NEW_COUNTRY_EVENT,
1716 WMI_TAG_REQUEST_RADIO_CHAN_STATS_CMD,
1717 WMI_TAG_RADIO_CHAN_STATS,
1718 WMI_TAG_RADIO_CHAN_STATS_EVENT,
1719 WMI_TAG_ROAM_PER_CONFIG,
1720 WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMD,
1721 WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENT,
1722 WMI_TAG_BPF_SET_VDEV_ACTIVE_MODE_CMD,
1723 WMI_TAG_HW_DATA_FILTER_CMD,
1724 WMI_TAG_CONNECTED_NLO_BSS_BAND_RSSI_PREF,
1725 WMI_TAG_PEER_OPER_MODE_CHANGE_EVENT,
1726 WMI_TAG_CHIP_POWER_SAVE_FAILURE_DETECTED,
1727 WMI_TAG_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMD,
1728 WMI_TAG_PDEV_CSA_SWITCH_COUNT_STATUS_EVENT,
1729 WMI_TAG_PDEV_UPDATE_PKT_ROUTING_CMD,
1730 WMI_TAG_PDEV_CHECK_CAL_VERSION_CMD,
1731 WMI_TAG_PDEV_CHECK_CAL_VERSION_EVENT,
1732 WMI_TAG_PDEV_SET_DIVERSITY_GAIN_CMD,
1733 WMI_TAG_MAC_PHY_CHAINMASK_COMBO,
1734 WMI_TAG_MAC_PHY_CHAINMASK_CAPABILITY,
1735 WMI_TAG_VDEV_SET_ARP_STATS_CMD,
1736 WMI_TAG_VDEV_GET_ARP_STATS_CMD,
1737 WMI_TAG_VDEV_GET_ARP_STATS_EVENT,
1738 WMI_TAG_IFACE_OFFLOAD_STATS,
1739 WMI_TAG_REQUEST_STATS_CMD_SUB_STRUCT_PARAM,
1740 WMI_TAG_RSSI_CTL_EXT,
1741 WMI_TAG_SINGLE_PHYERR_EXT_RX_HDR,
1742 WMI_TAG_COEX_BT_ACTIVITY_EVENT,
1743 WMI_TAG_VDEV_GET_TX_POWER_CMD,
1744 WMI_TAG_VDEV_TX_POWER_EVENT,
1745 WMI_TAG_OFFCHAN_DATA_TX_COMPL_EVENT,
1746 WMI_TAG_OFFCHAN_DATA_TX_SEND_CMD,
1747 WMI_TAG_TX_SEND_PARAMS,
1748 WMI_TAG_HE_RATE_SET,
1749 WMI_TAG_CONGESTION_STATS,
1750 WMI_TAG_SET_INIT_COUNTRY_CMD,
1751 WMI_TAG_SCAN_DBS_DUTY_CYCLE,
1752 WMI_TAG_SCAN_DBS_DUTY_CYCLE_PARAM_TLV,
1753 WMI_TAG_PDEV_DIV_GET_RSSI_ANTID,
1754 WMI_TAG_THERM_THROT_CONFIG_REQUEST,
1755 WMI_TAG_THERM_THROT_LEVEL_CONFIG_INFO,
1756 WMI_TAG_THERM_THROT_STATS_EVENT,
1757 WMI_TAG_THERM_THROT_LEVEL_STATS_INFO,
1758 WMI_TAG_PDEV_DIV_RSSI_ANTID_EVENT,
1759 WMI_TAG_OEM_DMA_RING_CAPABILITIES,
1760 WMI_TAG_OEM_DMA_RING_CFG_REQ,
1761 WMI_TAG_OEM_DMA_RING_CFG_RSP,
1762 WMI_TAG_OEM_INDIRECT_DATA,
1763 WMI_TAG_OEM_DMA_BUF_RELEASE,
1764 WMI_TAG_OEM_DMA_BUF_RELEASE_ENTRY,
1765 WMI_TAG_PDEV_BSS_CHAN_INFO_REQUEST,
1766 WMI_TAG_PDEV_BSS_CHAN_INFO_EVENT,
1767 WMI_TAG_ROAM_LCA_DISALLOW_CONFIG,
1768 WMI_TAG_VDEV_LIMIT_OFFCHAN_CMD,
1769 WMI_TAG_ROAM_RSSI_REJECTION_OCE_CONFIG,
1770 WMI_TAG_UNIT_TEST_EVENT,
1771 WMI_TAG_ROAM_FILS_OFFLOAD,
1772 WMI_TAG_PDEV_UPDATE_PMK_CACHE_CMD,
1773 WMI_TAG_PMK_CACHE,
1774 WMI_TAG_PDEV_UPDATE_FILS_HLP_PKT_CMD,
1775 WMI_TAG_ROAM_FILS_SYNCH,
1776 WMI_TAG_GTK_OFFLOAD_EXTENDED,
1777 WMI_TAG_ROAM_BG_SCAN_ROAMING,
1778 WMI_TAG_OIC_PING_OFFLOAD_PARAMS_CMD,
1779 WMI_TAG_OIC_PING_OFFLOAD_SET_ENABLE_CMD,
1780 WMI_TAG_OIC_PING_HANDOFF_EVENT,
1781 WMI_TAG_DHCP_LEASE_RENEW_OFFLOAD_CMD,
1782 WMI_TAG_DHCP_LEASE_RENEW_EVENT,
1783 WMI_TAG_BTM_CONFIG,
1784 WMI_TAG_DEBUG_MESG_FW_DATA_STALL,
1785 WMI_TAG_WLM_CONFIG_CMD,
1786 WMI_TAG_PDEV_UPDATE_CTLTABLE_REQUEST,
1787 WMI_TAG_PDEV_UPDATE_CTLTABLE_EVENT,
1788 WMI_TAG_ROAM_CND_SCORING_PARAM,
1789 WMI_TAG_PDEV_CONFIG_VENDOR_OUI_ACTION,
1790 WMI_TAG_VENDOR_OUI_EXT,
1791 WMI_TAG_ROAM_SYNCH_FRAME_EVENT,
1792 WMI_TAG_FD_SEND_FROM_HOST_CMD,
1793 WMI_TAG_ENABLE_FILS_CMD,
1794 WMI_TAG_HOST_SWFDA_EVENT,
1795 WMI_TAG_BCN_OFFLOAD_CTRL_CMD,
1796 WMI_TAG_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMD,
1797 WMI_TAG_STATS_PERIOD,
1798 WMI_TAG_NDL_SCHEDULE_UPDATE,
1799 WMI_TAG_PEER_TID_MSDUQ_QDEPTH_THRESH_UPDATE_CMD,
1800 WMI_TAG_MSDUQ_QDEPTH_THRESH_UPDATE,
1801 WMI_TAG_PDEV_SET_RX_FILTER_PROMISCUOUS_CMD,
1802 WMI_TAG_SAR2_RESULT_EVENT,
1803 WMI_TAG_SAR_CAPABILITIES,
1804 WMI_TAG_SAP_OBSS_DETECTION_CFG_CMD,
1805 WMI_TAG_SAP_OBSS_DETECTION_INFO_EVT,
1806 WMI_TAG_DMA_RING_CAPABILITIES,
1807 WMI_TAG_DMA_RING_CFG_REQ,
1808 WMI_TAG_DMA_RING_CFG_RSP,
1809 WMI_TAG_DMA_BUF_RELEASE,
1810 WMI_TAG_DMA_BUF_RELEASE_ENTRY,
1811 WMI_TAG_SAR_GET_LIMITS_CMD,
1812 WMI_TAG_SAR_GET_LIMITS_EVENT,
1813 WMI_TAG_SAR_GET_LIMITS_EVENT_ROW,
1814 WMI_TAG_OFFLOAD_11K_REPORT,
1815 WMI_TAG_INVOKE_NEIGHBOR_REPORT,
1816 WMI_TAG_NEIGHBOR_REPORT_OFFLOAD,
1817 WMI_TAG_VDEV_SET_CONNECTIVITY_CHECK_STATS,
1818 WMI_TAG_VDEV_GET_CONNECTIVITY_CHECK_STATS,
1819 WMI_TAG_BPF_SET_VDEV_ENABLE_CMD,
1820 WMI_TAG_BPF_SET_VDEV_WORK_MEMORY_CMD,
1821 WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_CMD,
1822 WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_RESP_EVT,
1823 WMI_TAG_PDEV_GET_NFCAL_POWER,
1824 WMI_TAG_BSS_COLOR_CHANGE_ENABLE,
1825 WMI_TAG_OBSS_COLOR_COLLISION_DET_CONFIG,
1826 WMI_TAG_OBSS_COLOR_COLLISION_EVT,
1827 WMI_TAG_RUNTIME_DPD_RECAL_CMD,
1828 WMI_TAG_TWT_ENABLE_CMD,
1829 WMI_TAG_TWT_DISABLE_CMD,
1830 WMI_TAG_TWT_ADD_DIALOG_CMD,
1831 WMI_TAG_TWT_DEL_DIALOG_CMD,
1832 WMI_TAG_TWT_PAUSE_DIALOG_CMD,
1833 WMI_TAG_TWT_RESUME_DIALOG_CMD,
1834 WMI_TAG_TWT_ENABLE_COMPLETE_EVENT,
1835 WMI_TAG_TWT_DISABLE_COMPLETE_EVENT,
1836 WMI_TAG_TWT_ADD_DIALOG_COMPLETE_EVENT,
1837 WMI_TAG_TWT_DEL_DIALOG_COMPLETE_EVENT,
1838 WMI_TAG_TWT_PAUSE_DIALOG_COMPLETE_EVENT,
1839 WMI_TAG_TWT_RESUME_DIALOG_COMPLETE_EVENT,
1840 WMI_TAG_REQUEST_ROAM_SCAN_STATS_CMD,
1841 WMI_TAG_ROAM_SCAN_STATS_EVENT,
1842 WMI_TAG_PEER_TID_CONFIGURATIONS_CMD,
1843 WMI_TAG_VDEV_SET_CUSTOM_SW_RETRY_TH_CMD,
1844 WMI_TAG_GET_TPC_POWER_CMD,
1845 WMI_TAG_GET_TPC_POWER_EVENT,
1846 WMI_TAG_DMA_BUF_RELEASE_SPECTRAL_META_DATA,
1847 WMI_TAG_MOTION_DET_CONFIG_PARAMS_CMD,
1848 WMI_TAG_MOTION_DET_BASE_LINE_CONFIG_PARAMS_CMD,
1849 WMI_TAG_MOTION_DET_START_STOP_CMD,
1850 WMI_TAG_MOTION_DET_BASE_LINE_START_STOP_CMD,
1851 WMI_TAG_MOTION_DET_EVENT,
1852 WMI_TAG_MOTION_DET_BASE_LINE_EVENT,
1853 WMI_TAG_NDP_TRANSPORT_IP,
1854 WMI_TAG_OBSS_SPATIAL_REUSE_SET_CMD,
1855 WMI_TAG_ESP_ESTIMATE_EVENT,
1856 WMI_TAG_NAN_HOST_CONFIG,
1857 WMI_TAG_SPECTRAL_BIN_SCALING_PARAMS,
1858 WMI_TAG_PEER_CFR_CAPTURE_CMD,
1859 WMI_TAG_PEER_CHAN_WIDTH_SWITCH_CMD,
1860 WMI_TAG_CHAN_WIDTH_PEER_LIST,
1861 WMI_TAG_OBSS_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMD,
1862 WMI_TAG_PDEV_HE_TB_ACTION_FRM_CMD,
1863 WMI_TAG_PEER_EXTD2_STATS,
1864 WMI_TAG_HPCS_PULSE_START_CMD,
1865 WMI_TAG_PDEV_CTL_FAILSAFE_CHECK_EVENT,
1866 WMI_TAG_VDEV_CHAINMASK_CONFIG_CMD,
1867 WMI_TAG_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMD,
1868 WMI_TAG_NAN_EVENT_INFO,
1869 WMI_TAG_NDP_CHANNEL_INFO,
1870 WMI_TAG_NDP_CMD,
1871 WMI_TAG_NDP_EVENT,
1872 WMI_TAG_PDEV_PEER_PKTLOG_FILTER_CMD = 0x301,
1873 WMI_TAG_PDEV_PEER_PKTLOG_FILTER_INFO,
1874 WMI_TAG_FILS_DISCOVERY_TMPL_CMD = 0x344,
1875 WMI_TAG_PDEV_SRG_BSS_COLOR_BITMAP_CMD = 0x37b,
1876 WMI_TAG_PDEV_SRG_PARTIAL_BSSID_BITMAP_CMD,
1877 WMI_TAG_PDEV_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD = 0x381,
1878 WMI_TAG_PDEV_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD,
1879 WMI_TAG_PDEV_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD,
1880 WMI_TAG_PDEV_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD,
1881 WMI_TAG_REGULATORY_RULE_EXT_STRUCT = 0x3A9,
1882 WMI_TAG_REG_CHAN_LIST_CC_EXT_EVENT,
1883 WMI_TAG_PDEV_SET_BIOS_SAR_TABLE_CMD = 0x3D8,
1884 WMI_TAG_PDEV_SET_BIOS_GEO_TABLE_CMD,
1885 WMI_TAG_MAX
1886};
1887
1888enum wmi_tlv_service {
1889 WMI_TLV_SERVICE_BEACON_OFFLOAD = 0,
1890 WMI_TLV_SERVICE_SCAN_OFFLOAD = 1,
1891 WMI_TLV_SERVICE_ROAM_SCAN_OFFLOAD = 2,
1892 WMI_TLV_SERVICE_BCN_MISS_OFFLOAD = 3,
1893 WMI_TLV_SERVICE_STA_PWRSAVE = 4,
1894 WMI_TLV_SERVICE_STA_ADVANCED_PWRSAVE = 5,
1895 WMI_TLV_SERVICE_AP_UAPSD = 6,
1896 WMI_TLV_SERVICE_AP_DFS = 7,
1897 WMI_TLV_SERVICE_11AC = 8,
1898 WMI_TLV_SERVICE_BLOCKACK = 9,
1899 WMI_TLV_SERVICE_PHYERR = 10,
1900 WMI_TLV_SERVICE_BCN_FILTER = 11,
1901 WMI_TLV_SERVICE_RTT = 12,
1902 WMI_TLV_SERVICE_WOW = 13,
1903 WMI_TLV_SERVICE_RATECTRL_CACHE = 14,
1904 WMI_TLV_SERVICE_IRAM_TIDS = 15,
1905 WMI_TLV_SERVICE_ARPNS_OFFLOAD = 16,
1906 WMI_TLV_SERVICE_NLO = 17,
1907 WMI_TLV_SERVICE_GTK_OFFLOAD = 18,
1908 WMI_TLV_SERVICE_SCAN_SCH = 19,
1909 WMI_TLV_SERVICE_CSA_OFFLOAD = 20,
1910 WMI_TLV_SERVICE_CHATTER = 21,
1911 WMI_TLV_SERVICE_COEX_FREQAVOID = 22,
1912 WMI_TLV_SERVICE_PACKET_POWER_SAVE = 23,
1913 WMI_TLV_SERVICE_FORCE_FW_HANG = 24,
1914 WMI_TLV_SERVICE_GPIO = 25,
1915 WMI_TLV_SERVICE_STA_DTIM_PS_MODULATED_DTIM = 26,
1916 WMI_STA_UAPSD_BASIC_AUTO_TRIG = 27,
1917 WMI_STA_UAPSD_VAR_AUTO_TRIG = 28,
1918 WMI_TLV_SERVICE_STA_KEEP_ALIVE = 29,
1919 WMI_TLV_SERVICE_TX_ENCAP = 30,
1920 WMI_TLV_SERVICE_AP_PS_DETECT_OUT_OF_SYNC = 31,
1921 WMI_TLV_SERVICE_EARLY_RX = 32,
1922 WMI_TLV_SERVICE_STA_SMPS = 33,
1923 WMI_TLV_SERVICE_FWTEST = 34,
1924 WMI_TLV_SERVICE_STA_WMMAC = 35,
1925 WMI_TLV_SERVICE_TDLS = 36,
1926 WMI_TLV_SERVICE_BURST = 37,
1927 WMI_TLV_SERVICE_MCC_BCN_INTERVAL_CHANGE = 38,
1928 WMI_TLV_SERVICE_ADAPTIVE_OCS = 39,
1929 WMI_TLV_SERVICE_BA_SSN_SUPPORT = 40,
1930 WMI_TLV_SERVICE_FILTER_IPSEC_NATKEEPALIVE = 41,
1931 WMI_TLV_SERVICE_WLAN_HB = 42,
1932 WMI_TLV_SERVICE_LTE_ANT_SHARE_SUPPORT = 43,
1933 WMI_TLV_SERVICE_BATCH_SCAN = 44,
1934 WMI_TLV_SERVICE_QPOWER = 45,
1935 WMI_TLV_SERVICE_PLMREQ = 46,
1936 WMI_TLV_SERVICE_THERMAL_MGMT = 47,
1937 WMI_TLV_SERVICE_RMC = 48,
1938 WMI_TLV_SERVICE_MHF_OFFLOAD = 49,
1939 WMI_TLV_SERVICE_COEX_SAR = 50,
1940 WMI_TLV_SERVICE_BCN_TXRATE_OVERRIDE = 51,
1941 WMI_TLV_SERVICE_NAN = 52,
1942 WMI_TLV_SERVICE_L1SS_STAT = 53,
1943 WMI_TLV_SERVICE_ESTIMATE_LINKSPEED = 54,
1944 WMI_TLV_SERVICE_OBSS_SCAN = 55,
1945 WMI_TLV_SERVICE_TDLS_OFFCHAN = 56,
1946 WMI_TLV_SERVICE_TDLS_UAPSD_BUFFER_STA = 57,
1947 WMI_TLV_SERVICE_TDLS_UAPSD_SLEEP_STA = 58,
1948 WMI_TLV_SERVICE_IBSS_PWRSAVE = 59,
1949 WMI_TLV_SERVICE_LPASS = 60,
1950 WMI_TLV_SERVICE_EXTSCAN = 61,
1951 WMI_TLV_SERVICE_D0WOW = 62,
1952 WMI_TLV_SERVICE_HSOFFLOAD = 63,
1953 WMI_TLV_SERVICE_ROAM_HO_OFFLOAD = 64,
1954 WMI_TLV_SERVICE_RX_FULL_REORDER = 65,
1955 WMI_TLV_SERVICE_DHCP_OFFLOAD = 66,
1956 WMI_TLV_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT = 67,
1957 WMI_TLV_SERVICE_MDNS_OFFLOAD = 68,
1958 WMI_TLV_SERVICE_SAP_AUTH_OFFLOAD = 69,
1959 WMI_TLV_SERVICE_DUAL_BAND_SIMULTANEOUS_SUPPORT = 70,
1960 WMI_TLV_SERVICE_OCB = 71,
1961 WMI_TLV_SERVICE_AP_ARPNS_OFFLOAD = 72,
1962 WMI_TLV_SERVICE_PER_BAND_CHAINMASK_SUPPORT = 73,
1963 WMI_TLV_SERVICE_PACKET_FILTER_OFFLOAD = 74,
1964 WMI_TLV_SERVICE_MGMT_TX_HTT = 75,
1965 WMI_TLV_SERVICE_MGMT_TX_WMI = 76,
1966 WMI_TLV_SERVICE_EXT_MSG = 77,
1967 WMI_TLV_SERVICE_MAWC = 78,
1968 WMI_TLV_SERVICE_PEER_ASSOC_CONF = 79,
1969 WMI_TLV_SERVICE_EGAP = 80,
1970 WMI_TLV_SERVICE_STA_PMF_OFFLOAD = 81,
1971 WMI_TLV_SERVICE_UNIFIED_WOW_CAPABILITY = 82,
1972 WMI_TLV_SERVICE_ENHANCED_PROXY_STA = 83,
1973 WMI_TLV_SERVICE_ATF = 84,
1974 WMI_TLV_SERVICE_COEX_GPIO = 85,
1975 WMI_TLV_SERVICE_AUX_SPECTRAL_INTF = 86,
1976 WMI_TLV_SERVICE_AUX_CHAN_LOAD_INTF = 87,
1977 WMI_TLV_SERVICE_BSS_CHANNEL_INFO_64 = 88,
1978 WMI_TLV_SERVICE_ENTERPRISE_MESH = 89,
1979 WMI_TLV_SERVICE_RESTRT_CHNL_SUPPORT = 90,
1980 WMI_TLV_SERVICE_BPF_OFFLOAD = 91,
1981 WMI_TLV_SERVICE_SYNC_DELETE_CMDS = 92,
1982 WMI_TLV_SERVICE_SMART_ANTENNA_SW_SUPPORT = 93,
1983 WMI_TLV_SERVICE_SMART_ANTENNA_HW_SUPPORT = 94,
1984 WMI_TLV_SERVICE_RATECTRL_LIMIT_MAX_MIN_RATES = 95,
1985 WMI_TLV_SERVICE_NAN_DATA = 96,
1986 WMI_TLV_SERVICE_NAN_RTT = 97,
1987 WMI_TLV_SERVICE_11AX = 98,
1988 WMI_TLV_SERVICE_DEPRECATED_REPLACE = 99,
1989 WMI_TLV_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE = 100,
1990 WMI_TLV_SERVICE_ENHANCED_MCAST_FILTER = 101,
1991 WMI_TLV_SERVICE_PERIODIC_CHAN_STAT_SUPPORT = 102,
1992 WMI_TLV_SERVICE_MESH_11S = 103,
1993 WMI_TLV_SERVICE_HALF_RATE_QUARTER_RATE_SUPPORT = 104,
1994 WMI_TLV_SERVICE_VDEV_RX_FILTER = 105,
1995 WMI_TLV_SERVICE_P2P_LISTEN_OFFLOAD_SUPPORT = 106,
1996 WMI_TLV_SERVICE_MARK_FIRST_WAKEUP_PACKET = 107,
1997 WMI_TLV_SERVICE_MULTIPLE_MCAST_FILTER_SET = 108,
1998 WMI_TLV_SERVICE_HOST_MANAGED_RX_REORDER = 109,
1999 WMI_TLV_SERVICE_FLASH_RDWR_SUPPORT = 110,
2000 WMI_TLV_SERVICE_WLAN_STATS_REPORT = 111,
2001 WMI_TLV_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT = 112,
2002 WMI_TLV_SERVICE_DFS_PHYERR_OFFLOAD = 113,
2003 WMI_TLV_SERVICE_RCPI_SUPPORT = 114,
2004 WMI_TLV_SERVICE_FW_MEM_DUMP_SUPPORT = 115,
2005 WMI_TLV_SERVICE_PEER_STATS_INFO = 116,
2006 WMI_TLV_SERVICE_REGULATORY_DB = 117,
2007 WMI_TLV_SERVICE_11D_OFFLOAD = 118,
2008 WMI_TLV_SERVICE_HW_DATA_FILTERING = 119,
2009 WMI_TLV_SERVICE_MULTIPLE_VDEV_RESTART = 120,
2010 WMI_TLV_SERVICE_PKT_ROUTING = 121,
2011 WMI_TLV_SERVICE_CHECK_CAL_VERSION = 122,
2012 WMI_TLV_SERVICE_OFFCHAN_TX_WMI = 123,
2013 WMI_TLV_SERVICE_8SS_TX_BFEE = 124,
2014 WMI_TLV_SERVICE_EXTENDED_NSS_SUPPORT = 125,
2015 WMI_TLV_SERVICE_ACK_TIMEOUT = 126,
2016 WMI_TLV_SERVICE_PDEV_BSS_CHANNEL_INFO_64 = 127,
2017
2018 /* The first 128 bits */
2019 WMI_MAX_SERVICE = 128,
2020
2021 WMI_TLV_SERVICE_CHAN_LOAD_INFO = 128,
2022 WMI_TLV_SERVICE_TX_PPDU_INFO_STATS_SUPPORT = 129,
2023 WMI_TLV_SERVICE_VDEV_LIMIT_OFFCHAN_SUPPORT = 130,
2024 WMI_TLV_SERVICE_FILS_SUPPORT = 131,
2025 WMI_TLV_SERVICE_WLAN_OIC_PING_OFFLOAD = 132,
2026 WMI_TLV_SERVICE_WLAN_DHCP_RENEW = 133,
2027 WMI_TLV_SERVICE_MAWC_SUPPORT = 134,
2028 WMI_TLV_SERVICE_VDEV_LATENCY_CONFIG = 135,
2029 WMI_TLV_SERVICE_PDEV_UPDATE_CTLTABLE_SUPPORT = 136,
2030 WMI_TLV_SERVICE_PKTLOG_SUPPORT_OVER_HTT = 137,
2031 WMI_TLV_SERVICE_VDEV_MULTI_GROUP_KEY_SUPPORT = 138,
2032 WMI_TLV_SERVICE_SCAN_PHYMODE_SUPPORT = 139,
2033 WMI_TLV_SERVICE_THERM_THROT = 140,
2034 WMI_TLV_SERVICE_BCN_OFFLOAD_START_STOP_SUPPORT = 141,
2035 WMI_TLV_SERVICE_WOW_WAKEUP_BY_TIMER_PATTERN = 142,
2036 WMI_TLV_SERVICE_PEER_MAP_UNMAP_V2_SUPPORT = 143,
2037 WMI_TLV_SERVICE_OFFCHAN_DATA_TID_SUPPORT = 144,
2038 WMI_TLV_SERVICE_RX_PROMISC_ENABLE_SUPPORT = 145,
2039 WMI_TLV_SERVICE_SUPPORT_DIRECT_DMA = 146,
2040 WMI_TLV_SERVICE_AP_OBSS_DETECTION_OFFLOAD = 147,
2041 WMI_TLV_SERVICE_11K_NEIGHBOUR_REPORT_SUPPORT = 148,
2042 WMI_TLV_SERVICE_LISTEN_INTERVAL_OFFLOAD_SUPPORT = 149,
2043 WMI_TLV_SERVICE_BSS_COLOR_OFFLOAD = 150,
2044 WMI_TLV_SERVICE_RUNTIME_DPD_RECAL = 151,
2045 WMI_TLV_SERVICE_STA_TWT = 152,
2046 WMI_TLV_SERVICE_AP_TWT = 153,
2047 WMI_TLV_SERVICE_GMAC_OFFLOAD_SUPPORT = 154,
2048 WMI_TLV_SERVICE_SPOOF_MAC_SUPPORT = 155,
2049 WMI_TLV_SERVICE_PEER_TID_CONFIGS_SUPPORT = 156,
2050 WMI_TLV_SERVICE_VDEV_SWRETRY_PER_AC_CONFIG_SUPPORT = 157,
2051 WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_SCC_SUPPORT = 158,
2052 WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_MCC_SUPPORT = 159,
2053 WMI_TLV_SERVICE_MOTION_DET = 160,
2054 WMI_TLV_SERVICE_INFRA_MBSSID = 161,
2055 WMI_TLV_SERVICE_OBSS_SPATIAL_REUSE = 162,
2056 WMI_TLV_SERVICE_VDEV_DIFFERENT_BEACON_INTERVAL_SUPPORT = 163,
2057 WMI_TLV_SERVICE_NAN_DBS_SUPPORT = 164,
2058 WMI_TLV_SERVICE_NDI_DBS_SUPPORT = 165,
2059 WMI_TLV_SERVICE_NAN_SAP_SUPPORT = 166,
2060 WMI_TLV_SERVICE_NDI_SAP_SUPPORT = 167,
2061 WMI_TLV_SERVICE_CFR_CAPTURE_SUPPORT = 168,
2062 WMI_TLV_SERVICE_CFR_CAPTURE_IND_MSG_TYPE_1 = 169,
2063 WMI_TLV_SERVICE_ESP_SUPPORT = 170,
2064 WMI_TLV_SERVICE_PEER_CHWIDTH_CHANGE = 171,
2065 WMI_TLV_SERVICE_WLAN_HPCS_PULSE = 172,
2066 WMI_TLV_SERVICE_PER_VDEV_CHAINMASK_CONFIG_SUPPORT = 173,
2067 WMI_TLV_SERVICE_TX_DATA_MGMT_ACK_RSSI = 174,
2068 WMI_TLV_SERVICE_NAN_DISABLE_SUPPORT = 175,
2069 WMI_TLV_SERVICE_HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN = 176,
2070 WMI_TLV_SERVICE_COEX_SUPPORT_UNEQUAL_ISOLATION = 177,
2071 WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT = 178,
2072 WMI_TLV_SERVICE_SUPPORT_EXTEND_ADDRESS = 179,
2073 WMI_TLV_SERVICE_BEACON_RECEPTION_STATS = 180,
2074 WMI_TLV_SERVICE_FETCH_TX_PN = 181,
2075 WMI_TLV_SERVICE_PEER_UNMAP_RESPONSE_SUPPORT = 182,
2076 WMI_TLV_SERVICE_TX_PER_PEER_AMPDU_SIZE = 183,
2077 WMI_TLV_SERVICE_BSS_COLOR_SWITCH_COUNT = 184,
2078 WMI_TLV_SERVICE_HTT_PEER_STATS_SUPPORT = 185,
2079 WMI_TLV_SERVICE_UL_RU26_ALLOWED = 186,
2080 WMI_TLV_SERVICE_GET_MWS_COEX_STATE = 187,
2081 WMI_TLV_SERVICE_GET_MWS_DPWB_STATE = 188,
2082 WMI_TLV_SERVICE_GET_MWS_TDM_STATE = 189,
2083 WMI_TLV_SERVICE_GET_MWS_IDRX_STATE = 190,
2084 WMI_TLV_SERVICE_GET_MWS_ANTENNA_SHARING_STATE = 191,
2085 WMI_TLV_SERVICE_ENHANCED_TPC_CONFIG_EVENT = 192,
2086 WMI_TLV_SERVICE_WLM_STATS_REQUEST = 193,
2087 WMI_TLV_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT = 194,
2088 WMI_TLV_SERVICE_WPA3_FT_SAE_SUPPORT = 195,
2089 WMI_TLV_SERVICE_WPA3_FT_SUITE_B_SUPPORT = 196,
2090 WMI_TLV_SERVICE_VOW_ENABLE = 197,
2091 WMI_TLV_SERVICE_CFR_CAPTURE_IND_EVT_TYPE_1 = 198,
2092 WMI_TLV_SERVICE_BROADCAST_TWT = 199,
2093 WMI_TLV_SERVICE_RAP_DETECTION_SUPPORT = 200,
2094 WMI_TLV_SERVICE_PS_TDCC = 201,
2095 WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_LEGACY = 202,
2096 WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_OVERRIDE = 203,
2097 WMI_TLV_SERVICE_TX_PWR_PER_PEER = 204,
2098 WMI_TLV_SERVICE_STA_PLUS_STA_SUPPORT = 205,
2099 WMI_TLV_SERVICE_WPA3_FT_FILS = 206,
2100 WMI_TLV_SERVICE_ADAPTIVE_11R_ROAM = 207,
2101 WMI_TLV_SERVICE_CHAN_RF_CHARACTERIZATION_INFO = 208,
2102 WMI_TLV_SERVICE_FW_IFACE_COMBINATION_SUPPORT = 209,
2103 WMI_TLV_SERVICE_TX_COMPL_TSF64 = 210,
2104 WMI_TLV_SERVICE_DSM_ROAM_FILTER = 211,
2105 WMI_TLV_SERVICE_PACKET_CAPTURE_SUPPORT = 212,
2106 WMI_TLV_SERVICE_PER_PEER_HTT_STATS_RESET = 213,
2107 WMI_TLV_SERVICE_FREQINFO_IN_METADATA = 219,
2108 WMI_TLV_SERVICE_EXT2_MSG = 220,
2109 WMI_TLV_SERVICE_PEER_POWER_SAVE_DURATION_SUPPORT = 246,
2110 WMI_TLV_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT = 249,
2111 WMI_TLV_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT = 253,
2112 WMI_TLV_SERVICE_PASSIVE_SCAN_START_TIME_ENHANCE = 263,
2113
2114 /* The second 128 bits */
2115 WMI_MAX_EXT_SERVICE = 256,
2116 WMI_TLV_SERVICE_SCAN_CONFIG_PER_CHANNEL = 265,
2117 WMI_TLV_SERVICE_REG_CC_EXT_EVENT_SUPPORT = 281,
2118 WMI_TLV_SERVICE_BIOS_SAR_SUPPORT = 326,
2119 WMI_TLV_SERVICE_SUPPORT_11D_FOR_HOST_SCAN = 357,
2120
2121 /* The third 128 bits */
2122 WMI_MAX_EXT2_SERVICE = 384
2123};
2124
2125enum {
2126 WMI_SMPS_FORCED_MODE_NONE = 0,
2127 WMI_SMPS_FORCED_MODE_DISABLED,
2128 WMI_SMPS_FORCED_MODE_STATIC,
2129 WMI_SMPS_FORCED_MODE_DYNAMIC
2130};
2131
2132#define WMI_TPC_CHAINMASK_CONFIG_BAND_2G 0
2133#define WMI_TPC_CHAINMASK_CONFIG_BAND_5G 1
2134#define WMI_NUM_SUPPORTED_BAND_MAX 2
2135
2136#define WMI_PEER_MIMO_PS_STATE 0x1
2137#define WMI_PEER_AMPDU 0x2
2138#define WMI_PEER_AUTHORIZE 0x3
2139#define WMI_PEER_CHWIDTH 0x4
2140#define WMI_PEER_NSS 0x5
2141#define WMI_PEER_USE_4ADDR 0x6
2142#define WMI_PEER_MEMBERSHIP 0x7
2143#define WMI_PEER_USERPOS 0x8
2144#define WMI_PEER_CRIT_PROTO_HINT_ENABLED 0x9
2145#define WMI_PEER_TX_FAIL_CNT_THR 0xA
2146#define WMI_PEER_SET_HW_RETRY_CTS2S 0xB
2147#define WMI_PEER_IBSS_ATIM_WINDOW_LENGTH 0xC
2148#define WMI_PEER_PHYMODE 0xD
2149#define WMI_PEER_USE_FIXED_PWR 0xE
2150#define WMI_PEER_PARAM_FIXED_RATE 0xF
2151#define WMI_PEER_SET_MU_WHITELIST 0x10
2152#define WMI_PEER_SET_MAX_TX_RATE 0x11
2153#define WMI_PEER_SET_MIN_TX_RATE 0x12
2154#define WMI_PEER_SET_DEFAULT_ROUTING 0x13
2155
2156/* slot time long */
2157#define WMI_VDEV_SLOT_TIME_LONG 0x1
2158/* slot time short */
2159#define WMI_VDEV_SLOT_TIME_SHORT 0x2
2160/* preablbe long */
2161#define WMI_VDEV_PREAMBLE_LONG 0x1
2162/* preablbe short */
2163#define WMI_VDEV_PREAMBLE_SHORT 0x2
2164
2165enum wmi_peer_smps_state {
2166 WMI_PEER_SMPS_PS_NONE = 0x0,
2167 WMI_PEER_SMPS_STATIC = 0x1,
2168 WMI_PEER_SMPS_DYNAMIC = 0x2
2169};
2170
2171enum wmi_peer_chwidth {
2172 WMI_PEER_CHWIDTH_20MHZ = 0,
2173 WMI_PEER_CHWIDTH_40MHZ = 1,
2174 WMI_PEER_CHWIDTH_80MHZ = 2,
2175 WMI_PEER_CHWIDTH_160MHZ = 3,
2176};
2177
2178enum wmi_beacon_gen_mode {
2179 WMI_BEACON_STAGGERED_MODE = 0,
2180 WMI_BEACON_BURST_MODE = 1
2181};
2182
2183enum wmi_direct_buffer_module {
2184 WMI_DIRECT_BUF_SPECTRAL = 0,
2185 WMI_DIRECT_BUF_CFR = 1,
2186
2187 /* keep it last */
2188 WMI_DIRECT_BUF_MAX
2189};
2190
2191/* enum wmi_nss_ratio - NSS ratio received from FW during service ready ext
2192 * event
2193 * WMI_NSS_RATIO_1BY2_NSS -Max nss of 160MHz is equals to half of the max nss
2194 * of 80MHz
2195 * WMI_NSS_RATIO_3BY4_NSS - Max nss of 160MHz is equals to 3/4 of the max nss
2196 * of 80MHz
2197 * WMI_NSS_RATIO_1_NSS - Max nss of 160MHz is equals to the max nss of 80MHz
2198 * WMI_NSS_RATIO_2_NSS - Max nss of 160MHz is equals to two times the max
2199 * nss of 80MHz
2200 */
2201
2202enum wmi_nss_ratio {
2203 WMI_NSS_RATIO_1BY2_NSS = 0x0,
2204 WMI_NSS_RATIO_3BY4_NSS = 0x1,
2205 WMI_NSS_RATIO_1_NSS = 0x2,
2206 WMI_NSS_RATIO_2_NSS = 0x3,
2207};
2208
2209enum wmi_dtim_policy {
2210 WMI_DTIM_POLICY_IGNORE = 1,
2211 WMI_DTIM_POLICY_NORMAL = 2,
2212 WMI_DTIM_POLICY_STICK = 3,
2213 WMI_DTIM_POLICY_AUTO = 4,
2214};
2215
2216struct wmi_host_pdev_band_to_mac {
2217 u32 pdev_id;
2218 u32 start_freq;
2219 u32 end_freq;
2220};
2221
2222struct ath11k_ppe_threshold {
2223 u32 numss_m1;
2224 u32 ru_bit_mask;
2225 u32 ppet16_ppet8_ru3_ru0[PSOC_HOST_MAX_NUM_SS];
2226};
2227
2228struct ath11k_service_ext_param {
2229 u32 default_conc_scan_config_bits;
2230 u32 default_fw_config_bits;
2231 struct ath11k_ppe_threshold ppet;
2232 u32 he_cap_info;
2233 u32 mpdu_density;
2234 u32 max_bssid_rx_filters;
2235 u32 num_hw_modes;
2236 u32 num_phy;
2237};
2238
2239struct ath11k_hw_mode_caps {
2240 u32 hw_mode_id;
2241 u32 phy_id_map;
2242 u32 hw_mode_config_type;
2243};
2244
2245#define PSOC_HOST_MAX_PHY_SIZE (3)
2246#define ATH11K_11B_SUPPORT BIT(0)
2247#define ATH11K_11G_SUPPORT BIT(1)
2248#define ATH11K_11A_SUPPORT BIT(2)
2249#define ATH11K_11N_SUPPORT BIT(3)
2250#define ATH11K_11AC_SUPPORT BIT(4)
2251#define ATH11K_11AX_SUPPORT BIT(5)
2252
2253struct ath11k_hal_reg_capabilities_ext {
2254 u32 phy_id;
2255 u32 eeprom_reg_domain;
2256 u32 eeprom_reg_domain_ext;
2257 u32 regcap1;
2258 u32 regcap2;
2259 u32 wireless_modes;
2260 u32 low_2ghz_chan;
2261 u32 high_2ghz_chan;
2262 u32 low_5ghz_chan;
2263 u32 high_5ghz_chan;
2264};
2265
2266#define WMI_HOST_MAX_PDEV 3
2267
2268struct wlan_host_mem_chunk {
2269 u32 tlv_header;
2270 u32 req_id;
2271 u32 ptr;
2272 u32 size;
2273} __packed;
2274
2275struct wmi_host_mem_chunk {
2276 void *vaddr;
2277 dma_addr_t paddr;
2278 u32 len;
2279 u32 req_id;
2280};
2281
2282struct wmi_init_cmd_param {
2283 u32 tlv_header;
2284 struct target_resource_config *res_cfg;
2285 u8 num_mem_chunks;
2286 struct wmi_host_mem_chunk *mem_chunks;
2287 u32 hw_mode_id;
2288 u32 num_band_to_mac;
2289 struct wmi_host_pdev_band_to_mac band_to_mac[WMI_HOST_MAX_PDEV];
2290};
2291
2292struct wmi_pdev_band_to_mac {
2293 u32 tlv_header;
2294 u32 pdev_id;
2295 u32 start_freq;
2296 u32 end_freq;
2297} __packed;
2298
2299struct wmi_pdev_set_hw_mode_cmd_param {
2300 u32 tlv_header;
2301 u32 pdev_id;
2302 u32 hw_mode_index;
2303 u32 num_band_to_mac;
2304} __packed;
2305
2306struct wmi_ppe_threshold {
2307 u32 numss_m1; /** NSS - 1*/
2308 union {
2309 u32 ru_count;
2310 u32 ru_mask;
2311 } __packed;
2312 u32 ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS];
2313} __packed;
2314
2315#define HW_BD_INFO_SIZE 5
2316
2317struct wmi_abi_version {
2318 u32 abi_version_0;
2319 u32 abi_version_1;
2320 u32 abi_version_ns_0;
2321 u32 abi_version_ns_1;
2322 u32 abi_version_ns_2;
2323 u32 abi_version_ns_3;
2324} __packed;
2325
2326struct wmi_init_cmd {
2327 u32 tlv_header;
2328 struct wmi_abi_version host_abi_vers;
2329 u32 num_host_mem_chunks;
2330} __packed;
2331
2332#define WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64 BIT(5)
2333#define WMI_RSRC_CFG_FLAG2_CALC_NEXT_DTIM_COUNT_SET BIT(9)
2334#define WMI_RSRC_CFG_FLAG1_ACK_RSSI BIT(18)
2335
2336#define WMI_CFG_HOST_SERVICE_FLAG_REG_CC_EXT 4
2337
2338struct wmi_resource_config {
2339 u32 tlv_header;
2340 u32 num_vdevs;
2341 u32 num_peers;
2342 u32 num_offload_peers;
2343 u32 num_offload_reorder_buffs;
2344 u32 num_peer_keys;
2345 u32 num_tids;
2346 u32 ast_skid_limit;
2347 u32 tx_chain_mask;
2348 u32 rx_chain_mask;
2349 u32 rx_timeout_pri[4];
2350 u32 rx_decap_mode;
2351 u32 scan_max_pending_req;
2352 u32 bmiss_offload_max_vdev;
2353 u32 roam_offload_max_vdev;
2354 u32 roam_offload_max_ap_profiles;
2355 u32 num_mcast_groups;
2356 u32 num_mcast_table_elems;
2357 u32 mcast2ucast_mode;
2358 u32 tx_dbg_log_size;
2359 u32 num_wds_entries;
2360 u32 dma_burst_size;
2361 u32 mac_aggr_delim;
2362 u32 rx_skip_defrag_timeout_dup_detection_check;
2363 u32 vow_config;
2364 u32 gtk_offload_max_vdev;
2365 u32 num_msdu_desc;
2366 u32 max_frag_entries;
2367 u32 num_tdls_vdevs;
2368 u32 num_tdls_conn_table_entries;
2369 u32 beacon_tx_offload_max_vdev;
2370 u32 num_multicast_filter_entries;
2371 u32 num_wow_filters;
2372 u32 num_keep_alive_pattern;
2373 u32 keep_alive_pattern_size;
2374 u32 max_tdls_concurrent_sleep_sta;
2375 u32 max_tdls_concurrent_buffer_sta;
2376 u32 wmi_send_separate;
2377 u32 num_ocb_vdevs;
2378 u32 num_ocb_channels;
2379 u32 num_ocb_schedules;
2380 u32 flag1;
2381 u32 smart_ant_cap;
2382 u32 bk_minfree;
2383 u32 be_minfree;
2384 u32 vi_minfree;
2385 u32 vo_minfree;
2386 u32 alloc_frag_desc_for_data_pkt;
2387 u32 num_ns_ext_tuples_cfg;
2388 u32 bpf_instruction_size;
2389 u32 max_bssid_rx_filters;
2390 u32 use_pdev_id;
2391 u32 max_num_dbs_scan_duty_cycle;
2392 u32 max_num_group_keys;
2393 u32 peer_map_unmap_v2_support;
2394 u32 sched_params;
2395 u32 twt_ap_pdev_count;
2396 u32 twt_ap_sta_count;
2397 u32 max_nlo_ssids;
2398 u32 num_pkt_filters;
2399 u32 num_max_sta_vdevs;
2400 u32 max_bssid_indicator;
2401 u32 ul_resp_config;
2402 u32 msdu_flow_override_config0;
2403 u32 msdu_flow_override_config1;
2404 u32 flags2;
2405 u32 host_service_flags;
2406 u32 max_rnr_neighbours;
2407 u32 ema_max_vap_cnt;
2408 u32 ema_max_profile_period;
2409} __packed;
2410
2411struct wmi_service_ready_event {
2412 u32 fw_build_vers;
2413 struct wmi_abi_version fw_abi_vers;
2414 u32 phy_capability;
2415 u32 max_frag_entry;
2416 u32 num_rf_chains;
2417 u32 ht_cap_info;
2418 u32 vht_cap_info;
2419 u32 vht_supp_mcs;
2420 u32 hw_min_tx_power;
2421 u32 hw_max_tx_power;
2422 u32 sys_cap_info;
2423 u32 min_pkt_size_enable;
2424 u32 max_bcn_ie_size;
2425 u32 num_mem_reqs;
2426 u32 max_num_scan_channels;
2427 u32 hw_bd_id;
2428 u32 hw_bd_info[HW_BD_INFO_SIZE];
2429 u32 max_supported_macs;
2430 u32 wmi_fw_sub_feat_caps;
2431 u32 num_dbs_hw_modes;
2432 /* txrx_chainmask
2433 * [7:0] - 2G band tx chain mask
2434 * [15:8] - 2G band rx chain mask
2435 * [23:16] - 5G band tx chain mask
2436 * [31:24] - 5G band rx chain mask
2437 */
2438 u32 txrx_chainmask;
2439 u32 default_dbs_hw_mode_index;
2440 u32 num_msdu_desc;
2441} __packed;
2442
2443#define WMI_SERVICE_BM_SIZE ((WMI_MAX_SERVICE + sizeof(u32) - 1) / sizeof(u32))
2444
2445#define WMI_SERVICE_SEGMENT_BM_SIZE32 4 /* 4x u32 = 128 bits */
2446#define WMI_SERVICE_EXT_BM_SIZE (WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(u32))
2447#define WMI_AVAIL_SERVICE_BITS_IN_SIZE32 32
2448#define WMI_SERVICE_BITS_IN_SIZE32 4
2449
2450struct wmi_service_ready_ext_event {
2451 u32 default_conc_scan_config_bits;
2452 u32 default_fw_config_bits;
2453 struct wmi_ppe_threshold ppet;
2454 u32 he_cap_info;
2455 u32 mpdu_density;
2456 u32 max_bssid_rx_filters;
2457 u32 fw_build_vers_ext;
2458 u32 max_nlo_ssids;
2459 u32 max_bssid_indicator;
2460 u32 he_cap_info_ext;
2461} __packed;
2462
2463struct wmi_soc_mac_phy_hw_mode_caps {
2464 u32 num_hw_modes;
2465 u32 num_chainmask_tables;
2466} __packed;
2467
2468struct wmi_hw_mode_capabilities {
2469 u32 tlv_header;
2470 u32 hw_mode_id;
2471 u32 phy_id_map;
2472 u32 hw_mode_config_type;
2473} __packed;
2474
2475#define WMI_MAX_HECAP_PHY_SIZE (3)
2476#define WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS BIT(0)
2477#define WMI_NSS_RATIO_ENABLE_DISABLE_GET(_val) \
2478 FIELD_GET(WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS, _val)
2479#define WMI_NSS_RATIO_INFO_BITPOS GENMASK(4, 1)
2480#define WMI_NSS_RATIO_INFO_GET(_val) \
2481 FIELD_GET(WMI_NSS_RATIO_INFO_BITPOS, _val)
2482
2483struct wmi_mac_phy_capabilities {
2484 u32 hw_mode_id;
2485 u32 pdev_id;
2486 u32 phy_id;
2487 u32 supported_flags;
2488 u32 supported_bands;
2489 u32 ampdu_density;
2490 u32 max_bw_supported_2g;
2491 u32 ht_cap_info_2g;
2492 u32 vht_cap_info_2g;
2493 u32 vht_supp_mcs_2g;
2494 u32 he_cap_info_2g;
2495 u32 he_supp_mcs_2g;
2496 u32 tx_chain_mask_2g;
2497 u32 rx_chain_mask_2g;
2498 u32 max_bw_supported_5g;
2499 u32 ht_cap_info_5g;
2500 u32 vht_cap_info_5g;
2501 u32 vht_supp_mcs_5g;
2502 u32 he_cap_info_5g;
2503 u32 he_supp_mcs_5g;
2504 u32 tx_chain_mask_5g;
2505 u32 rx_chain_mask_5g;
2506 u32 he_cap_phy_info_2g[WMI_MAX_HECAP_PHY_SIZE];
2507 u32 he_cap_phy_info_5g[WMI_MAX_HECAP_PHY_SIZE];
2508 struct wmi_ppe_threshold he_ppet2g;
2509 struct wmi_ppe_threshold he_ppet5g;
2510 u32 chainmask_table_id;
2511 u32 lmac_id;
2512 u32 he_cap_info_2g_ext;
2513 u32 he_cap_info_5g_ext;
2514 u32 he_cap_info_internal;
2515 u32 wireless_modes;
2516 u32 low_2ghz_chan_freq;
2517 u32 high_2ghz_chan_freq;
2518 u32 low_5ghz_chan_freq;
2519 u32 high_5ghz_chan_freq;
2520 u32 nss_ratio;
2521} __packed;
2522
2523struct wmi_hal_reg_capabilities_ext {
2524 u32 tlv_header;
2525 u32 phy_id;
2526 u32 eeprom_reg_domain;
2527 u32 eeprom_reg_domain_ext;
2528 u32 regcap1;
2529 u32 regcap2;
2530 u32 wireless_modes;
2531 u32 low_2ghz_chan;
2532 u32 high_2ghz_chan;
2533 u32 low_5ghz_chan;
2534 u32 high_5ghz_chan;
2535} __packed;
2536
2537struct wmi_soc_hal_reg_capabilities {
2538 u32 num_phy;
2539} __packed;
2540
2541/* 2 word representation of MAC addr */
2542struct wmi_mac_addr {
2543 union {
2544 u8 addr[6];
2545 struct {
2546 u32 word0;
2547 u32 word1;
2548 } __packed;
2549 } __packed;
2550} __packed;
2551
2552struct wmi_dma_ring_capabilities {
2553 u32 tlv_header;
2554 u32 pdev_id;
2555 u32 module_id;
2556 u32 min_elem;
2557 u32 min_buf_sz;
2558 u32 min_buf_align;
2559} __packed;
2560
2561struct wmi_ready_event_min {
2562 struct wmi_abi_version fw_abi_vers;
2563 struct wmi_mac_addr mac_addr;
2564 u32 status;
2565 u32 num_dscp_table;
2566 u32 num_extra_mac_addr;
2567 u32 num_total_peers;
2568 u32 num_extra_peers;
2569} __packed;
2570
2571struct wmi_ready_event {
2572 struct wmi_ready_event_min ready_event_min;
2573 u32 max_ast_index;
2574 u32 pktlog_defs_checksum;
2575} __packed;
2576
2577struct wmi_service_available_event {
2578 u32 wmi_service_segment_offset;
2579 u32 wmi_service_segment_bitmap[WMI_SERVICE_SEGMENT_BM_SIZE32];
2580} __packed;
2581
2582struct ath11k_pdev_wmi {
2583 struct ath11k_wmi_base *wmi_ab;
2584 enum ath11k_htc_ep_id eid;
2585 u32 rx_decap_mode;
2586 wait_queue_head_t tx_ce_desc_wq;
2587};
2588
2589struct vdev_create_params {
2590 u8 if_id;
2591 u32 type;
2592 u32 subtype;
2593 struct {
2594 u8 tx;
2595 u8 rx;
2596 } chains[NUM_NL80211_BANDS];
2597 u32 pdev_id;
2598 u32 mbssid_flags;
2599 u32 mbssid_tx_vdev_id;
2600};
2601
2602struct wmi_vdev_create_cmd {
2603 u32 tlv_header;
2604 u32 vdev_id;
2605 u32 vdev_type;
2606 u32 vdev_subtype;
2607 struct wmi_mac_addr vdev_macaddr;
2608 u32 num_cfg_txrx_streams;
2609 u32 pdev_id;
2610 u32 mbssid_flags;
2611 u32 mbssid_tx_vdev_id;
2612} __packed;
2613
2614struct wmi_vdev_txrx_streams {
2615 u32 tlv_header;
2616 u32 band;
2617 u32 supported_tx_streams;
2618 u32 supported_rx_streams;
2619} __packed;
2620
2621struct wmi_vdev_delete_cmd {
2622 u32 tlv_header;
2623 u32 vdev_id;
2624} __packed;
2625
2626struct wmi_vdev_up_cmd {
2627 u32 tlv_header;
2628 u32 vdev_id;
2629 u32 vdev_assoc_id;
2630 struct wmi_mac_addr vdev_bssid;
2631 struct wmi_mac_addr tx_vdev_bssid;
2632 u32 nontx_profile_idx;
2633 u32 nontx_profile_cnt;
2634} __packed;
2635
2636struct wmi_vdev_stop_cmd {
2637 u32 tlv_header;
2638 u32 vdev_id;
2639} __packed;
2640
2641struct wmi_vdev_down_cmd {
2642 u32 tlv_header;
2643 u32 vdev_id;
2644} __packed;
2645
2646#define WMI_VDEV_START_HIDDEN_SSID BIT(0)
2647#define WMI_VDEV_START_PMF_ENABLED BIT(1)
2648#define WMI_VDEV_START_LDPC_RX_ENABLED BIT(3)
2649#define WMI_VDEV_START_HW_ENCRYPTION_DISABLED BIT(4)
2650
2651struct wmi_ssid {
2652 u32 ssid_len;
2653 u32 ssid[8];
2654} __packed;
2655
2656#define ATH11K_VDEV_SETUP_TIMEOUT_HZ (1 * HZ)
2657
2658struct wmi_vdev_start_request_cmd {
2659 u32 tlv_header;
2660 u32 vdev_id;
2661 u32 requestor_id;
2662 u32 beacon_interval;
2663 u32 dtim_period;
2664 u32 flags;
2665 struct wmi_ssid ssid;
2666 u32 bcn_tx_rate;
2667 u32 bcn_txpower;
2668 u32 num_noa_descriptors;
2669 u32 disable_hw_ack;
2670 u32 preferred_tx_streams;
2671 u32 preferred_rx_streams;
2672 u32 he_ops;
2673 u32 cac_duration_ms;
2674 u32 regdomain;
2675 u32 min_data_rate;
2676 u32 mbssid_flags;
2677 u32 mbssid_tx_vdev_id;
2678} __packed;
2679
2680#define MGMT_TX_DL_FRM_LEN 64
2681#define WMI_MAC_MAX_SSID_LENGTH 32
2682struct mac_ssid {
2683 u8 length;
2684 u8 mac_ssid[WMI_MAC_MAX_SSID_LENGTH];
2685} __packed;
2686
2687struct wmi_p2p_noa_descriptor {
2688 u32 type_count;
2689 u32 duration;
2690 u32 interval;
2691 u32 start_time;
2692};
2693
2694struct channel_param {
2695 u8 chan_id;
2696 u8 pwr;
2697 u32 mhz;
2698 u32 half_rate:1,
2699 quarter_rate:1,
2700 dfs_set:1,
2701 dfs_set_cfreq2:1,
2702 is_chan_passive:1,
2703 allow_ht:1,
2704 allow_vht:1,
2705 allow_he:1,
2706 set_agile:1,
2707 psc_channel:1;
2708 u32 phy_mode;
2709 u32 cfreq1;
2710 u32 cfreq2;
2711 char maxpower;
2712 char minpower;
2713 char maxregpower;
2714 u8 antennamax;
2715 u8 reg_class_id;
2716} __packed;
2717
2718enum wmi_phy_mode {
2719 MODE_11A = 0,
2720 MODE_11G = 1, /* 11b/g Mode */
2721 MODE_11B = 2, /* 11b Mode */
2722 MODE_11GONLY = 3, /* 11g only Mode */
2723 MODE_11NA_HT20 = 4,
2724 MODE_11NG_HT20 = 5,
2725 MODE_11NA_HT40 = 6,
2726 MODE_11NG_HT40 = 7,
2727 MODE_11AC_VHT20 = 8,
2728 MODE_11AC_VHT40 = 9,
2729 MODE_11AC_VHT80 = 10,
2730 MODE_11AC_VHT20_2G = 11,
2731 MODE_11AC_VHT40_2G = 12,
2732 MODE_11AC_VHT80_2G = 13,
2733 MODE_11AC_VHT80_80 = 14,
2734 MODE_11AC_VHT160 = 15,
2735 MODE_11AX_HE20 = 16,
2736 MODE_11AX_HE40 = 17,
2737 MODE_11AX_HE80 = 18,
2738 MODE_11AX_HE80_80 = 19,
2739 MODE_11AX_HE160 = 20,
2740 MODE_11AX_HE20_2G = 21,
2741 MODE_11AX_HE40_2G = 22,
2742 MODE_11AX_HE80_2G = 23,
2743 MODE_UNKNOWN = 24,
2744 MODE_MAX = 24
2745};
2746
2747static inline const char *ath11k_wmi_phymode_str(enum wmi_phy_mode mode)
2748{
2749 switch (mode) {
2750 case MODE_11A:
2751 return "11a";
2752 case MODE_11G:
2753 return "11g";
2754 case MODE_11B:
2755 return "11b";
2756 case MODE_11GONLY:
2757 return "11gonly";
2758 case MODE_11NA_HT20:
2759 return "11na-ht20";
2760 case MODE_11NG_HT20:
2761 return "11ng-ht20";
2762 case MODE_11NA_HT40:
2763 return "11na-ht40";
2764 case MODE_11NG_HT40:
2765 return "11ng-ht40";
2766 case MODE_11AC_VHT20:
2767 return "11ac-vht20";
2768 case MODE_11AC_VHT40:
2769 return "11ac-vht40";
2770 case MODE_11AC_VHT80:
2771 return "11ac-vht80";
2772 case MODE_11AC_VHT160:
2773 return "11ac-vht160";
2774 case MODE_11AC_VHT80_80:
2775 return "11ac-vht80+80";
2776 case MODE_11AC_VHT20_2G:
2777 return "11ac-vht20-2g";
2778 case MODE_11AC_VHT40_2G:
2779 return "11ac-vht40-2g";
2780 case MODE_11AC_VHT80_2G:
2781 return "11ac-vht80-2g";
2782 case MODE_11AX_HE20:
2783 return "11ax-he20";
2784 case MODE_11AX_HE40:
2785 return "11ax-he40";
2786 case MODE_11AX_HE80:
2787 return "11ax-he80";
2788 case MODE_11AX_HE80_80:
2789 return "11ax-he80+80";
2790 case MODE_11AX_HE160:
2791 return "11ax-he160";
2792 case MODE_11AX_HE20_2G:
2793 return "11ax-he20-2g";
2794 case MODE_11AX_HE40_2G:
2795 return "11ax-he40-2g";
2796 case MODE_11AX_HE80_2G:
2797 return "11ax-he80-2g";
2798 case MODE_UNKNOWN:
2799 /* skip */
2800 break;
2801
2802 /* no default handler to allow compiler to check that the
2803 * enum is fully handled
2804 */
2805 }
2806
2807 return "<unknown>";
2808}
2809
2810struct wmi_channel_arg {
2811 u32 freq;
2812 u32 band_center_freq1;
2813 u32 band_center_freq2;
2814 bool passive;
2815 bool allow_ibss;
2816 bool allow_ht;
2817 bool allow_vht;
2818 bool ht40plus;
2819 bool chan_radar;
2820 bool freq2_radar;
2821 bool allow_he;
2822 u32 min_power;
2823 u32 max_power;
2824 u32 max_reg_power;
2825 u32 max_antenna_gain;
2826 enum wmi_phy_mode mode;
2827};
2828
2829struct wmi_vdev_start_req_arg {
2830 u32 vdev_id;
2831 struct wmi_channel_arg channel;
2832 u32 bcn_intval;
2833 u32 dtim_period;
2834 u8 *ssid;
2835 u32 ssid_len;
2836 u32 bcn_tx_rate;
2837 u32 bcn_tx_power;
2838 bool disable_hw_ack;
2839 bool hidden_ssid;
2840 bool pmf_enabled;
2841 u32 he_ops;
2842 u32 cac_duration_ms;
2843 u32 regdomain;
2844 u32 pref_rx_streams;
2845 u32 pref_tx_streams;
2846 u32 num_noa_descriptors;
2847 u32 min_data_rate;
2848 u32 mbssid_flags;
2849 u32 mbssid_tx_vdev_id;
2850};
2851
2852struct peer_create_params {
2853 const u8 *peer_addr;
2854 u32 peer_type;
2855 u32 vdev_id;
2856};
2857
2858struct peer_delete_params {
2859 u8 vdev_id;
2860};
2861
2862struct peer_flush_params {
2863 u32 peer_tid_bitmap;
2864 u8 vdev_id;
2865};
2866
2867struct pdev_set_regdomain_params {
2868 u16 current_rd_in_use;
2869 u16 current_rd_2g;
2870 u16 current_rd_5g;
2871 u32 ctl_2g;
2872 u32 ctl_5g;
2873 u8 dfs_domain;
2874 u32 pdev_id;
2875};
2876
2877struct rx_reorder_queue_remove_params {
2878 u8 *peer_macaddr;
2879 u16 vdev_id;
2880 u32 peer_tid_bitmap;
2881};
2882
2883#define WMI_HOST_PDEV_ID_SOC 0xFF
2884#define WMI_HOST_PDEV_ID_0 0
2885#define WMI_HOST_PDEV_ID_1 1
2886#define WMI_HOST_PDEV_ID_2 2
2887
2888#define WMI_PDEV_ID_SOC 0
2889#define WMI_PDEV_ID_1ST 1
2890#define WMI_PDEV_ID_2ND 2
2891#define WMI_PDEV_ID_3RD 3
2892
2893/* Freq units in MHz */
2894#define REG_RULE_START_FREQ 0x0000ffff
2895#define REG_RULE_END_FREQ 0xffff0000
2896#define REG_RULE_FLAGS 0x0000ffff
2897#define REG_RULE_MAX_BW 0x0000ffff
2898#define REG_RULE_REG_PWR 0x00ff0000
2899#define REG_RULE_ANT_GAIN 0xff000000
2900#define REG_RULE_PSD_INFO BIT(0)
2901#define REG_RULE_PSD_EIRP 0xff0000
2902
2903#define WMI_VDEV_PARAM_TXBF_SU_TX_BFEE BIT(0)
2904#define WMI_VDEV_PARAM_TXBF_MU_TX_BFEE BIT(1)
2905#define WMI_VDEV_PARAM_TXBF_SU_TX_BFER BIT(2)
2906#define WMI_VDEV_PARAM_TXBF_MU_TX_BFER BIT(3)
2907
2908#define HE_PHYCAP_BYTE_0 0
2909#define HE_PHYCAP_BYTE_1 1
2910#define HE_PHYCAP_BYTE_2 2
2911#define HE_PHYCAP_BYTE_3 3
2912#define HE_PHYCAP_BYTE_4 4
2913
2914#define HECAP_PHY_SU_BFER BIT(7)
2915#define HECAP_PHY_SU_BFEE BIT(0)
2916#define HECAP_PHY_MU_BFER BIT(1)
2917#define HECAP_PHY_UL_MUMIMO BIT(6)
2918#define HECAP_PHY_UL_MUOFDMA BIT(7)
2919
2920#define HECAP_PHY_SUBFMR_GET(hecap_phy) \
2921 FIELD_GET(HECAP_PHY_SU_BFER, hecap_phy[HE_PHYCAP_BYTE_3])
2922
2923#define HECAP_PHY_SUBFME_GET(hecap_phy) \
2924 FIELD_GET(HECAP_PHY_SU_BFEE, hecap_phy[HE_PHYCAP_BYTE_4])
2925
2926#define HECAP_PHY_MUBFMR_GET(hecap_phy) \
2927 FIELD_GET(HECAP_PHY_MU_BFER, hecap_phy[HE_PHYCAP_BYTE_4])
2928
2929#define HECAP_PHY_ULMUMIMO_GET(hecap_phy) \
2930 FIELD_GET(HECAP_PHY_UL_MUMIMO, hecap_phy[HE_PHYCAP_BYTE_2])
2931
2932#define HECAP_PHY_ULOFDMA_GET(hecap_phy) \
2933 FIELD_GET(HECAP_PHY_UL_MUOFDMA, hecap_phy[HE_PHYCAP_BYTE_2])
2934
2935#define HE_MODE_SU_TX_BFEE BIT(0)
2936#define HE_MODE_SU_TX_BFER BIT(1)
2937#define HE_MODE_MU_TX_BFEE BIT(2)
2938#define HE_MODE_MU_TX_BFER BIT(3)
2939#define HE_MODE_DL_OFDMA BIT(4)
2940#define HE_MODE_UL_OFDMA BIT(5)
2941#define HE_MODE_UL_MUMIMO BIT(6)
2942
2943#define HE_DL_MUOFDMA_ENABLE 1
2944#define HE_UL_MUOFDMA_ENABLE 1
2945#define HE_DL_MUMIMO_ENABLE 1
2946#define HE_UL_MUMIMO_ENABLE 1
2947#define HE_MU_BFEE_ENABLE 1
2948#define HE_SU_BFEE_ENABLE 1
2949#define HE_MU_BFER_ENABLE 1
2950#define HE_SU_BFER_ENABLE 1
2951
2952#define HE_VHT_SOUNDING_MODE_ENABLE 1
2953#define HE_SU_MU_SOUNDING_MODE_ENABLE 1
2954#define HE_TRIG_NONTRIG_SOUNDING_MODE_ENABLE 1
2955
2956/* HE or VHT Sounding */
2957#define HE_VHT_SOUNDING_MODE BIT(0)
2958/* SU or MU Sounding */
2959#define HE_SU_MU_SOUNDING_MODE BIT(2)
2960/* Trig or Non-Trig Sounding */
2961#define HE_TRIG_NONTRIG_SOUNDING_MODE BIT(3)
2962
2963#define WMI_TXBF_STS_CAP_OFFSET_LSB 4
2964#define WMI_TXBF_STS_CAP_OFFSET_MASK 0x70
2965#define WMI_BF_SOUND_DIM_OFFSET_LSB 8
2966#define WMI_BF_SOUND_DIM_OFFSET_MASK 0x700
2967
2968struct pdev_params {
2969 u32 param_id;
2970 u32 param_value;
2971};
2972
2973enum wmi_peer_type {
2974 WMI_PEER_TYPE_DEFAULT = 0,
2975 WMI_PEER_TYPE_BSS = 1,
2976 WMI_PEER_TYPE_TDLS = 2,
2977};
2978
2979struct wmi_peer_create_cmd {
2980 u32 tlv_header;
2981 u32 vdev_id;
2982 struct wmi_mac_addr peer_macaddr;
2983 u32 peer_type;
2984} __packed;
2985
2986struct wmi_peer_delete_cmd {
2987 u32 tlv_header;
2988 u32 vdev_id;
2989 struct wmi_mac_addr peer_macaddr;
2990} __packed;
2991
2992struct wmi_peer_reorder_queue_setup_cmd {
2993 u32 tlv_header;
2994 u32 vdev_id;
2995 struct wmi_mac_addr peer_macaddr;
2996 u32 tid;
2997 u32 queue_ptr_lo;
2998 u32 queue_ptr_hi;
2999 u32 queue_no;
3000 u32 ba_window_size_valid;
3001 u32 ba_window_size;
3002} __packed;
3003
3004struct wmi_peer_reorder_queue_remove_cmd {
3005 u32 tlv_header;
3006 u32 vdev_id;
3007 struct wmi_mac_addr peer_macaddr;
3008 u32 tid_mask;
3009} __packed;
3010
3011struct gpio_config_params {
3012 u32 gpio_num;
3013 u32 input;
3014 u32 pull_type;
3015 u32 intr_mode;
3016};
3017
3018enum wmi_gpio_type {
3019 WMI_GPIO_PULL_NONE,
3020 WMI_GPIO_PULL_UP,
3021 WMI_GPIO_PULL_DOWN
3022};
3023
3024enum wmi_gpio_intr_type {
3025 WMI_GPIO_INTTYPE_DISABLE,
3026 WMI_GPIO_INTTYPE_RISING_EDGE,
3027 WMI_GPIO_INTTYPE_FALLING_EDGE,
3028 WMI_GPIO_INTTYPE_BOTH_EDGE,
3029 WMI_GPIO_INTTYPE_LEVEL_LOW,
3030 WMI_GPIO_INTTYPE_LEVEL_HIGH
3031};
3032
3033enum wmi_bss_chan_info_req_type {
3034 WMI_BSS_SURVEY_REQ_TYPE_READ = 1,
3035 WMI_BSS_SURVEY_REQ_TYPE_READ_CLEAR,
3036};
3037
3038struct wmi_gpio_config_cmd_param {
3039 u32 tlv_header;
3040 u32 gpio_num;
3041 u32 input;
3042 u32 pull_type;
3043 u32 intr_mode;
3044};
3045
3046struct gpio_output_params {
3047 u32 gpio_num;
3048 u32 set;
3049};
3050
3051struct wmi_gpio_output_cmd_param {
3052 u32 tlv_header;
3053 u32 gpio_num;
3054 u32 set;
3055};
3056
3057struct set_fwtest_params {
3058 u32 arg;
3059 u32 value;
3060};
3061
3062struct wmi_fwtest_set_param_cmd_param {
3063 u32 tlv_header;
3064 u32 param_id;
3065 u32 param_value;
3066};
3067
3068struct wmi_pdev_set_param_cmd {
3069 u32 tlv_header;
3070 u32 pdev_id;
3071 u32 param_id;
3072 u32 param_value;
3073} __packed;
3074
3075struct wmi_pdev_set_ps_mode_cmd {
3076 u32 tlv_header;
3077 u32 vdev_id;
3078 u32 sta_ps_mode;
3079} __packed;
3080
3081struct wmi_pdev_suspend_cmd {
3082 u32 tlv_header;
3083 u32 pdev_id;
3084 u32 suspend_opt;
3085} __packed;
3086
3087struct wmi_pdev_resume_cmd {
3088 u32 tlv_header;
3089 u32 pdev_id;
3090} __packed;
3091
3092struct wmi_pdev_bss_chan_info_req_cmd {
3093 u32 tlv_header;
3094 /* ref wmi_bss_chan_info_req_type */
3095 u32 req_type;
3096 u32 pdev_id;
3097} __packed;
3098
3099struct wmi_ap_ps_peer_cmd {
3100 u32 tlv_header;
3101 u32 vdev_id;
3102 struct wmi_mac_addr peer_macaddr;
3103 u32 param;
3104 u32 value;
3105} __packed;
3106
3107struct wmi_sta_powersave_param_cmd {
3108 u32 tlv_header;
3109 u32 vdev_id;
3110 u32 param;
3111 u32 value;
3112} __packed;
3113
3114struct wmi_pdev_set_regdomain_cmd {
3115 u32 tlv_header;
3116 u32 pdev_id;
3117 u32 reg_domain;
3118 u32 reg_domain_2g;
3119 u32 reg_domain_5g;
3120 u32 conformance_test_limit_2g;
3121 u32 conformance_test_limit_5g;
3122 u32 dfs_domain;
3123} __packed;
3124
3125struct wmi_peer_set_param_cmd {
3126 u32 tlv_header;
3127 u32 vdev_id;
3128 struct wmi_mac_addr peer_macaddr;
3129 u32 param_id;
3130 u32 param_value;
3131} __packed;
3132
3133struct wmi_peer_flush_tids_cmd {
3134 u32 tlv_header;
3135 u32 vdev_id;
3136 struct wmi_mac_addr peer_macaddr;
3137 u32 peer_tid_bitmap;
3138} __packed;
3139
3140struct wmi_dfs_phyerr_offload_cmd {
3141 u32 tlv_header;
3142 u32 pdev_id;
3143} __packed;
3144
3145struct wmi_bcn_offload_ctrl_cmd {
3146 u32 tlv_header;
3147 u32 vdev_id;
3148 u32 bcn_ctrl_op;
3149} __packed;
3150
3151enum scan_dwelltime_adaptive_mode {
3152 SCAN_DWELL_MODE_DEFAULT = 0,
3153 SCAN_DWELL_MODE_CONSERVATIVE = 1,
3154 SCAN_DWELL_MODE_MODERATE = 2,
3155 SCAN_DWELL_MODE_AGGRESSIVE = 3,
3156 SCAN_DWELL_MODE_STATIC = 4
3157};
3158
3159#define WLAN_SSID_MAX_LEN 32
3160
3161struct element_info {
3162 u32 len;
3163 u8 *ptr;
3164};
3165
3166struct wlan_ssid {
3167 u8 length;
3168 u8 ssid[WLAN_SSID_MAX_LEN];
3169};
3170
3171#define WMI_IE_BITMAP_SIZE 8
3172
3173/* prefix used by scan requestor ids on the host */
3174#define WMI_HOST_SCAN_REQUESTOR_ID_PREFIX 0xA000
3175
3176/* prefix used by scan request ids generated on the host */
3177/* host cycles through the lower 12 bits to generate ids */
3178#define WMI_HOST_SCAN_REQ_ID_PREFIX 0xA000
3179
3180/* Values lower than this may be refused by some firmware revisions with a scan
3181 * completion with a timedout reason.
3182 */
3183#define WMI_SCAN_CHAN_MIN_TIME_MSEC 40
3184
3185/* Scan priority numbers must be sequential, starting with 0 */
3186enum wmi_scan_priority {
3187 WMI_SCAN_PRIORITY_VERY_LOW = 0,
3188 WMI_SCAN_PRIORITY_LOW,
3189 WMI_SCAN_PRIORITY_MEDIUM,
3190 WMI_SCAN_PRIORITY_HIGH,
3191 WMI_SCAN_PRIORITY_VERY_HIGH,
3192 WMI_SCAN_PRIORITY_COUNT /* number of priorities supported */
3193};
3194
3195enum wmi_scan_event_type {
3196 WMI_SCAN_EVENT_STARTED = BIT(0),
3197 WMI_SCAN_EVENT_COMPLETED = BIT(1),
3198 WMI_SCAN_EVENT_BSS_CHANNEL = BIT(2),
3199 WMI_SCAN_EVENT_FOREIGN_CHAN = BIT(3),
3200 WMI_SCAN_EVENT_DEQUEUED = BIT(4),
3201 /* possibly by high-prio scan */
3202 WMI_SCAN_EVENT_PREEMPTED = BIT(5),
3203 WMI_SCAN_EVENT_START_FAILED = BIT(6),
3204 WMI_SCAN_EVENT_RESTARTED = BIT(7),
3205 WMI_SCAN_EVENT_FOREIGN_CHAN_EXIT = BIT(8),
3206 WMI_SCAN_EVENT_SUSPENDED = BIT(9),
3207 WMI_SCAN_EVENT_RESUMED = BIT(10),
3208 WMI_SCAN_EVENT_MAX = BIT(15),
3209};
3210
3211enum wmi_scan_completion_reason {
3212 WMI_SCAN_REASON_COMPLETED,
3213 WMI_SCAN_REASON_CANCELLED,
3214 WMI_SCAN_REASON_PREEMPTED,
3215 WMI_SCAN_REASON_TIMEDOUT,
3216 WMI_SCAN_REASON_INTERNAL_FAILURE,
3217 WMI_SCAN_REASON_MAX,
3218};
3219
3220struct wmi_start_scan_cmd {
3221 u32 tlv_header;
3222 u32 scan_id;
3223 u32 scan_req_id;
3224 u32 vdev_id;
3225 u32 scan_priority;
3226 u32 notify_scan_events;
3227 u32 dwell_time_active;
3228 u32 dwell_time_passive;
3229 u32 min_rest_time;
3230 u32 max_rest_time;
3231 u32 repeat_probe_time;
3232 u32 probe_spacing_time;
3233 u32 idle_time;
3234 u32 max_scan_time;
3235 u32 probe_delay;
3236 u32 scan_ctrl_flags;
3237 u32 burst_duration;
3238 u32 num_chan;
3239 u32 num_bssid;
3240 u32 num_ssids;
3241 u32 ie_len;
3242 u32 n_probes;
3243 struct wmi_mac_addr mac_addr;
3244 struct wmi_mac_addr mac_mask;
3245 u32 ie_bitmap[WMI_IE_BITMAP_SIZE];
3246 u32 num_vendor_oui;
3247 u32 scan_ctrl_flags_ext;
3248 u32 dwell_time_active_2g;
3249 u32 dwell_time_active_6g;
3250 u32 dwell_time_passive_6g;
3251 u32 scan_start_offset;
3252} __packed;
3253
3254#define WMI_SCAN_FLAG_PASSIVE 0x1
3255#define WMI_SCAN_ADD_BCAST_PROBE_REQ 0x2
3256#define WMI_SCAN_ADD_CCK_RATES 0x4
3257#define WMI_SCAN_ADD_OFDM_RATES 0x8
3258#define WMI_SCAN_CHAN_STAT_EVENT 0x10
3259#define WMI_SCAN_FILTER_PROBE_REQ 0x20
3260#define WMI_SCAN_BYPASS_DFS_CHN 0x40
3261#define WMI_SCAN_CONTINUE_ON_ERROR 0x80
3262#define WMI_SCAN_FILTER_PROMISCUOS 0x100
3263#define WMI_SCAN_FLAG_FORCE_ACTIVE_ON_DFS 0x200
3264#define WMI_SCAN_ADD_TPC_IE_IN_PROBE_REQ 0x400
3265#define WMI_SCAN_ADD_DS_IE_IN_PROBE_REQ 0x800
3266#define WMI_SCAN_ADD_SPOOF_MAC_IN_PROBE_REQ 0x1000
3267#define WMI_SCAN_OFFCHAN_MGMT_TX 0x2000
3268#define WMI_SCAN_OFFCHAN_DATA_TX 0x4000
3269#define WMI_SCAN_CAPTURE_PHY_ERROR 0x8000
3270#define WMI_SCAN_FLAG_STRICT_PASSIVE_ON_PCHN 0x10000
3271#define WMI_SCAN_FLAG_HALF_RATE_SUPPORT 0x20000
3272#define WMI_SCAN_FLAG_QUARTER_RATE_SUPPORT 0x40000
3273#define WMI_SCAN_RANDOM_SEQ_NO_IN_PROBE_REQ 0x80000
3274#define WMI_SCAN_ENABLE_IE_WHTELIST_IN_PROBE_REQ 0x100000
3275
3276#define WMI_SCAN_DWELL_MODE_MASK 0x00E00000
3277#define WMI_SCAN_DWELL_MODE_SHIFT 21
3278#define WMI_SCAN_FLAG_EXT_PASSIVE_SCAN_START_TIME_ENHANCE 0x00000800
3279
3280#define WMI_SCAN_CONFIG_PER_CHANNEL_MASK GENMASK(19, 0)
3281#define WMI_SCAN_CH_FLAG_SCAN_ONLY_IF_RNR_FOUND BIT(20)
3282
3283enum {
3284 WMI_SCAN_DWELL_MODE_DEFAULT = 0,
3285 WMI_SCAN_DWELL_MODE_CONSERVATIVE = 1,
3286 WMI_SCAN_DWELL_MODE_MODERATE = 2,
3287 WMI_SCAN_DWELL_MODE_AGGRESSIVE = 3,
3288 WMI_SCAN_DWELL_MODE_STATIC = 4,
3289};
3290
3291#define WMI_SCAN_SET_DWELL_MODE(flag, mode) \
3292 ((flag) |= (((mode) << WMI_SCAN_DWELL_MODE_SHIFT) & \
3293 WMI_SCAN_DWELL_MODE_MASK))
3294
3295struct hint_short_ssid {
3296 u32 freq_flags;
3297 u32 short_ssid;
3298};
3299
3300struct hint_bssid {
3301 u32 freq_flags;
3302 struct wmi_mac_addr bssid;
3303};
3304
3305struct scan_req_params {
3306 u32 scan_id;
3307 u32 scan_req_id;
3308 u32 vdev_id;
3309 u32 pdev_id;
3310 enum wmi_scan_priority scan_priority;
3311 union {
3312 struct {
3313 u32 scan_ev_started:1,
3314 scan_ev_completed:1,
3315 scan_ev_bss_chan:1,
3316 scan_ev_foreign_chan:1,
3317 scan_ev_dequeued:1,
3318 scan_ev_preempted:1,
3319 scan_ev_start_failed:1,
3320 scan_ev_restarted:1,
3321 scan_ev_foreign_chn_exit:1,
3322 scan_ev_invalid:1,
3323 scan_ev_gpio_timeout:1,
3324 scan_ev_suspended:1,
3325 scan_ev_resumed:1;
3326 };
3327 u32 scan_events;
3328 };
3329 u32 scan_ctrl_flags_ext;
3330 u32 dwell_time_active;
3331 u32 dwell_time_active_2g;
3332 u32 dwell_time_passive;
3333 u32 dwell_time_active_6g;
3334 u32 dwell_time_passive_6g;
3335 u32 min_rest_time;
3336 u32 max_rest_time;
3337 u32 repeat_probe_time;
3338 u32 probe_spacing_time;
3339 u32 idle_time;
3340 u32 max_scan_time;
3341 u32 probe_delay;
3342 union {
3343 struct {
3344 u32 scan_f_passive:1,
3345 scan_f_bcast_probe:1,
3346 scan_f_cck_rates:1,
3347 scan_f_ofdm_rates:1,
3348 scan_f_chan_stat_evnt:1,
3349 scan_f_filter_prb_req:1,
3350 scan_f_bypass_dfs_chn:1,
3351 scan_f_continue_on_err:1,
3352 scan_f_offchan_mgmt_tx:1,
3353 scan_f_offchan_data_tx:1,
3354 scan_f_promisc_mode:1,
3355 scan_f_capture_phy_err:1,
3356 scan_f_strict_passive_pch:1,
3357 scan_f_half_rate:1,
3358 scan_f_quarter_rate:1,
3359 scan_f_force_active_dfs_chn:1,
3360 scan_f_add_tpc_ie_in_probe:1,
3361 scan_f_add_ds_ie_in_probe:1,
3362 scan_f_add_spoofed_mac_in_probe:1,
3363 scan_f_add_rand_seq_in_probe:1,
3364 scan_f_en_ie_whitelist_in_probe:1,
3365 scan_f_forced:1,
3366 scan_f_2ghz:1,
3367 scan_f_5ghz:1,
3368 scan_f_80mhz:1;
3369 };
3370 u32 scan_flags;
3371 };
3372 enum scan_dwelltime_adaptive_mode adaptive_dwell_time_mode;
3373 u32 burst_duration;
3374 u32 num_chan;
3375 u32 num_bssid;
3376 u32 num_ssids;
3377 u32 n_probes;
3378 u32 *chan_list;
3379 u32 notify_scan_events;
3380 struct wlan_ssid ssid[WLAN_SCAN_PARAMS_MAX_SSID];
3381 struct wmi_mac_addr bssid_list[WLAN_SCAN_PARAMS_MAX_BSSID];
3382 struct element_info extraie;
3383 struct element_info htcap;
3384 struct element_info vhtcap;
3385 u32 num_hint_s_ssid;
3386 u32 num_hint_bssid;
3387 struct hint_short_ssid hint_s_ssid[WLAN_SCAN_MAX_HINT_S_SSID];
3388 struct hint_bssid hint_bssid[WLAN_SCAN_MAX_HINT_BSSID];
3389 struct wmi_mac_addr mac_addr;
3390 struct wmi_mac_addr mac_mask;
3391};
3392
3393struct wmi_ssid_arg {
3394 int len;
3395 const u8 *ssid;
3396};
3397
3398struct wmi_bssid_arg {
3399 const u8 *bssid;
3400};
3401
3402struct wmi_start_scan_arg {
3403 u32 scan_id;
3404 u32 scan_req_id;
3405 u32 vdev_id;
3406 u32 scan_priority;
3407 u32 notify_scan_events;
3408 u32 dwell_time_active;
3409 u32 dwell_time_passive;
3410 u32 min_rest_time;
3411 u32 max_rest_time;
3412 u32 repeat_probe_time;
3413 u32 probe_spacing_time;
3414 u32 idle_time;
3415 u32 max_scan_time;
3416 u32 probe_delay;
3417 u32 scan_ctrl_flags;
3418
3419 u32 ie_len;
3420 u32 n_channels;
3421 u32 n_ssids;
3422 u32 n_bssids;
3423
3424 u8 ie[WLAN_SCAN_PARAMS_MAX_IE_LEN];
3425 u32 channels[64];
3426 struct wmi_ssid_arg ssids[WLAN_SCAN_PARAMS_MAX_SSID];
3427 struct wmi_bssid_arg bssids[WLAN_SCAN_PARAMS_MAX_BSSID];
3428};
3429
3430#define WMI_SCAN_STOP_ONE 0x00000000
3431#define WMI_SCN_STOP_VAP_ALL 0x01000000
3432#define WMI_SCAN_STOP_ALL 0x04000000
3433
3434/* Prefix 0xA000 indicates that the scan request
3435 * is trigger by HOST
3436 */
3437#define ATH11K_SCAN_ID 0xA000
3438
3439enum scan_cancel_req_type {
3440 WLAN_SCAN_CANCEL_SINGLE = 1,
3441 WLAN_SCAN_CANCEL_VDEV_ALL,
3442 WLAN_SCAN_CANCEL_PDEV_ALL,
3443};
3444
3445struct scan_cancel_param {
3446 u32 requester;
3447 u32 scan_id;
3448 enum scan_cancel_req_type req_type;
3449 u32 vdev_id;
3450 u32 pdev_id;
3451};
3452
3453struct wmi_bcn_send_from_host_cmd {
3454 u32 tlv_header;
3455 u32 vdev_id;
3456 u32 data_len;
3457 union {
3458 u32 frag_ptr;
3459 u32 frag_ptr_lo;
3460 };
3461 u32 frame_ctrl;
3462 u32 dtim_flag;
3463 u32 bcn_antenna;
3464 u32 frag_ptr_hi;
3465};
3466
3467#define WMI_CHAN_INFO_MODE GENMASK(5, 0)
3468#define WMI_CHAN_INFO_HT40_PLUS BIT(6)
3469#define WMI_CHAN_INFO_PASSIVE BIT(7)
3470#define WMI_CHAN_INFO_ADHOC_ALLOWED BIT(8)
3471#define WMI_CHAN_INFO_AP_DISABLED BIT(9)
3472#define WMI_CHAN_INFO_DFS BIT(10)
3473#define WMI_CHAN_INFO_ALLOW_HT BIT(11)
3474#define WMI_CHAN_INFO_ALLOW_VHT BIT(12)
3475#define WMI_CHAN_INFO_CHAN_CHANGE_CAUSE_CSA BIT(13)
3476#define WMI_CHAN_INFO_HALF_RATE BIT(14)
3477#define WMI_CHAN_INFO_QUARTER_RATE BIT(15)
3478#define WMI_CHAN_INFO_DFS_FREQ2 BIT(16)
3479#define WMI_CHAN_INFO_ALLOW_HE BIT(17)
3480#define WMI_CHAN_INFO_PSC BIT(18)
3481
3482#define WMI_CHAN_REG_INFO1_MIN_PWR GENMASK(7, 0)
3483#define WMI_CHAN_REG_INFO1_MAX_PWR GENMASK(15, 8)
3484#define WMI_CHAN_REG_INFO1_MAX_REG_PWR GENMASK(23, 16)
3485#define WMI_CHAN_REG_INFO1_REG_CLS GENMASK(31, 24)
3486
3487#define WMI_CHAN_REG_INFO2_ANT_MAX GENMASK(7, 0)
3488#define WMI_CHAN_REG_INFO2_MAX_TX_PWR GENMASK(15, 8)
3489
3490struct wmi_channel {
3491 u32 tlv_header;
3492 u32 mhz;
3493 u32 band_center_freq1;
3494 u32 band_center_freq2;
3495 u32 info;
3496 u32 reg_info_1;
3497 u32 reg_info_2;
3498} __packed;
3499
3500struct wmi_mgmt_params {
3501 void *tx_frame;
3502 u16 frm_len;
3503 u8 vdev_id;
3504 u16 chanfreq;
3505 void *pdata;
3506 u16 desc_id;
3507 u8 *macaddr;
3508};
3509
3510enum wmi_sta_ps_mode {
3511 WMI_STA_PS_MODE_DISABLED = 0,
3512 WMI_STA_PS_MODE_ENABLED = 1,
3513};
3514
3515#define WMI_SMPS_MASK_LOWER_16BITS 0xFF
3516#define WMI_SMPS_MASK_UPPER_3BITS 0x7
3517#define WMI_SMPS_PARAM_VALUE_SHIFT 29
3518
3519#define ATH11K_WMI_FW_HANG_ASSERT_TYPE 1
3520#define ATH11K_WMI_FW_HANG_DELAY 0
3521
3522/* type, 0:unused 1: ASSERT 2: not respond detect command
3523 * delay_time_ms, the simulate will delay time
3524 */
3525
3526struct wmi_force_fw_hang_cmd {
3527 u32 tlv_header;
3528 u32 type;
3529 u32 delay_time_ms;
3530};
3531
3532struct wmi_vdev_set_param_cmd {
3533 u32 tlv_header;
3534 u32 vdev_id;
3535 u32 param_id;
3536 u32 param_value;
3537} __packed;
3538
3539enum wmi_stats_id {
3540 WMI_REQUEST_PEER_STAT = BIT(0),
3541 WMI_REQUEST_AP_STAT = BIT(1),
3542 WMI_REQUEST_PDEV_STAT = BIT(2),
3543 WMI_REQUEST_VDEV_STAT = BIT(3),
3544 WMI_REQUEST_BCNFLT_STAT = BIT(4),
3545 WMI_REQUEST_VDEV_RATE_STAT = BIT(5),
3546 WMI_REQUEST_INST_STAT = BIT(6),
3547 WMI_REQUEST_MIB_STAT = BIT(7),
3548 WMI_REQUEST_RSSI_PER_CHAIN_STAT = BIT(8),
3549 WMI_REQUEST_CONGESTION_STAT = BIT(9),
3550 WMI_REQUEST_PEER_EXTD_STAT = BIT(10),
3551 WMI_REQUEST_BCN_STAT = BIT(11),
3552 WMI_REQUEST_BCN_STAT_RESET = BIT(12),
3553 WMI_REQUEST_PEER_EXTD2_STAT = BIT(13),
3554};
3555
3556struct wmi_request_stats_cmd {
3557 u32 tlv_header;
3558 enum wmi_stats_id stats_id;
3559 u32 vdev_id;
3560 struct wmi_mac_addr peer_macaddr;
3561 u32 pdev_id;
3562} __packed;
3563
3564struct wmi_get_pdev_temperature_cmd {
3565 u32 tlv_header;
3566 u32 param;
3567 u32 pdev_id;
3568} __packed;
3569
3570struct wmi_ftm_seg_hdr {
3571 u32 len;
3572 u32 msgref;
3573 u32 segmentinfo;
3574 u32 pdev_id;
3575} __packed;
3576
3577struct wmi_ftm_cmd {
3578 u32 tlv_header;
3579 struct wmi_ftm_seg_hdr seg_hdr;
3580 u8 data[];
3581} __packed;
3582
3583struct wmi_ftm_event_msg {
3584 struct wmi_ftm_seg_hdr seg_hdr;
3585 u8 data[];
3586} __packed;
3587
3588#define WMI_BEACON_TX_BUFFER_SIZE 512
3589
3590#define WMI_EMA_TMPL_IDX_SHIFT 8
3591#define WMI_EMA_FIRST_TMPL_SHIFT 16
3592#define WMI_EMA_LAST_TMPL_SHIFT 24
3593
3594struct wmi_bcn_tmpl_cmd {
3595 u32 tlv_header;
3596 u32 vdev_id;
3597 u32 tim_ie_offset;
3598 u32 buf_len;
3599 u32 csa_switch_count_offset;
3600 u32 ext_csa_switch_count_offset;
3601 u32 csa_event_bitmap;
3602 u32 mbssid_ie_offset;
3603 u32 esp_ie_offset;
3604 u32 csc_switch_count_offset;
3605 u32 csc_event_bitmap;
3606 u32 mu_edca_ie_offset;
3607 u32 feature_enable_bitmap;
3608 u32 ema_params;
3609} __packed;
3610
3611struct wmi_key_seq_counter {
3612 u32 key_seq_counter_l;
3613 u32 key_seq_counter_h;
3614} __packed;
3615
3616struct wmi_vdev_install_key_cmd {
3617 u32 tlv_header;
3618 u32 vdev_id;
3619 struct wmi_mac_addr peer_macaddr;
3620 u32 key_idx;
3621 u32 key_flags;
3622 u32 key_cipher;
3623 struct wmi_key_seq_counter key_rsc_counter;
3624 struct wmi_key_seq_counter key_global_rsc_counter;
3625 struct wmi_key_seq_counter key_tsc_counter;
3626 u8 wpi_key_rsc_counter[16];
3627 u8 wpi_key_tsc_counter[16];
3628 u32 key_len;
3629 u32 key_txmic_len;
3630 u32 key_rxmic_len;
3631 u32 is_group_key_id_valid;
3632 u32 group_key_id;
3633
3634 /* Followed by key_data containing key followed by
3635 * tx mic and then rx mic
3636 */
3637} __packed;
3638
3639struct wmi_vdev_install_key_arg {
3640 u32 vdev_id;
3641 const u8 *macaddr;
3642 u32 key_idx;
3643 u32 key_flags;
3644 u32 key_cipher;
3645 u32 key_len;
3646 u32 key_txmic_len;
3647 u32 key_rxmic_len;
3648 u64 key_rsc_counter;
3649 const void *key_data;
3650};
3651
3652#define WMI_MAX_SUPPORTED_RATES 128
3653#define WMI_HOST_MAX_HECAP_PHY_SIZE 3
3654#define WMI_HOST_MAX_HE_RATE_SET 3
3655#define WMI_HECAP_TXRX_MCS_NSS_IDX_80 0
3656#define WMI_HECAP_TXRX_MCS_NSS_IDX_160 1
3657#define WMI_HECAP_TXRX_MCS_NSS_IDX_80_80 2
3658
3659struct wmi_rate_set_arg {
3660 u32 num_rates;
3661 u8 rates[WMI_MAX_SUPPORTED_RATES];
3662};
3663
3664struct peer_assoc_params {
3665 struct wmi_mac_addr peer_macaddr;
3666 u32 vdev_id;
3667 u32 peer_new_assoc;
3668 u32 peer_associd;
3669 u32 peer_flags;
3670 u32 peer_caps;
3671 u32 peer_listen_intval;
3672 u32 peer_ht_caps;
3673 u32 peer_max_mpdu;
3674 u32 peer_mpdu_density;
3675 u32 peer_rate_caps;
3676 u32 peer_nss;
3677 u32 peer_vht_caps;
3678 u32 peer_phymode;
3679 u32 peer_ht_info[2];
3680 struct wmi_rate_set_arg peer_legacy_rates;
3681 struct wmi_rate_set_arg peer_ht_rates;
3682 u32 rx_max_rate;
3683 u32 rx_mcs_set;
3684 u32 tx_max_rate;
3685 u32 tx_mcs_set;
3686 u8 vht_capable;
3687 u8 min_data_rate;
3688 u32 tx_max_mcs_nss;
3689 u32 peer_bw_rxnss_override;
3690 bool is_pmf_enabled;
3691 bool is_wme_set;
3692 bool qos_flag;
3693 bool apsd_flag;
3694 bool ht_flag;
3695 bool bw_40;
3696 bool bw_80;
3697 bool bw_160;
3698 bool stbc_flag;
3699 bool ldpc_flag;
3700 bool static_mimops_flag;
3701 bool dynamic_mimops_flag;
3702 bool spatial_mux_flag;
3703 bool vht_flag;
3704 bool vht_ng_flag;
3705 bool need_ptk_4_way;
3706 bool need_gtk_2_way;
3707 bool auth_flag;
3708 bool safe_mode_enabled;
3709 bool amsdu_disable;
3710 /* Use common structure */
3711 u8 peer_mac[ETH_ALEN];
3712
3713 bool he_flag;
3714 u32 peer_he_cap_macinfo[2];
3715 u32 peer_he_cap_macinfo_internal;
3716 u32 peer_he_caps_6ghz;
3717 u32 peer_he_ops;
3718 u32 peer_he_cap_phyinfo[WMI_HOST_MAX_HECAP_PHY_SIZE];
3719 u32 peer_he_mcs_count;
3720 u32 peer_he_rx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];
3721 u32 peer_he_tx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];
3722 bool twt_responder;
3723 bool twt_requester;
3724 bool is_assoc;
3725 struct ath11k_ppe_threshold peer_ppet;
3726};
3727
3728struct wmi_peer_assoc_complete_cmd {
3729 u32 tlv_header;
3730 struct wmi_mac_addr peer_macaddr;
3731 u32 vdev_id;
3732 u32 peer_new_assoc;
3733 u32 peer_associd;
3734 u32 peer_flags;
3735 u32 peer_caps;
3736 u32 peer_listen_intval;
3737 u32 peer_ht_caps;
3738 u32 peer_max_mpdu;
3739 u32 peer_mpdu_density;
3740 u32 peer_rate_caps;
3741 u32 peer_nss;
3742 u32 peer_vht_caps;
3743 u32 peer_phymode;
3744 u32 peer_ht_info[2];
3745 u32 num_peer_legacy_rates;
3746 u32 num_peer_ht_rates;
3747 u32 peer_bw_rxnss_override;
3748 struct wmi_ppe_threshold peer_ppet;
3749 u32 peer_he_cap_info;
3750 u32 peer_he_ops;
3751 u32 peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE];
3752 u32 peer_he_mcs;
3753 u32 peer_he_cap_info_ext;
3754 u32 peer_he_cap_info_internal;
3755 u32 min_data_rate;
3756 u32 peer_he_caps_6ghz;
3757} __packed;
3758
3759struct wmi_stop_scan_cmd {
3760 u32 tlv_header;
3761 u32 requestor;
3762 u32 scan_id;
3763 u32 req_type;
3764 u32 vdev_id;
3765 u32 pdev_id;
3766};
3767
3768struct scan_chan_list_params {
3769 u32 pdev_id;
3770 u16 nallchans;
3771 struct channel_param ch_param[];
3772};
3773
3774struct wmi_scan_chan_list_cmd {
3775 u32 tlv_header;
3776 u32 num_scan_chans;
3777 u32 flags;
3778 u32 pdev_id;
3779} __packed;
3780
3781struct wmi_scan_prob_req_oui_cmd {
3782 u32 tlv_header;
3783 u32 prob_req_oui;
3784} __packed;
3785
3786#define WMI_MGMT_SEND_DOWNLD_LEN 64
3787
3788#define WMI_TX_PARAMS_DWORD0_POWER GENMASK(7, 0)
3789#define WMI_TX_PARAMS_DWORD0_MCS_MASK GENMASK(19, 8)
3790#define WMI_TX_PARAMS_DWORD0_NSS_MASK GENMASK(27, 20)
3791#define WMI_TX_PARAMS_DWORD0_RETRY_LIMIT GENMASK(31, 28)
3792
3793#define WMI_TX_PARAMS_DWORD1_CHAIN_MASK GENMASK(7, 0)
3794#define WMI_TX_PARAMS_DWORD1_BW_MASK GENMASK(14, 8)
3795#define WMI_TX_PARAMS_DWORD1_PREAMBLE_TYPE GENMASK(19, 15)
3796#define WMI_TX_PARAMS_DWORD1_FRAME_TYPE BIT(20)
3797#define WMI_TX_PARAMS_DWORD1_RSVD GENMASK(31, 21)
3798
3799struct wmi_mgmt_send_params {
3800 u32 tlv_header;
3801 u32 tx_params_dword0;
3802 u32 tx_params_dword1;
3803};
3804
3805struct wmi_mgmt_send_cmd {
3806 u32 tlv_header;
3807 u32 vdev_id;
3808 u32 desc_id;
3809 u32 chanfreq;
3810 u32 paddr_lo;
3811 u32 paddr_hi;
3812 u32 frame_len;
3813 u32 buf_len;
3814 u32 tx_params_valid;
3815
3816 /* This TLV is followed by struct wmi_mgmt_frame */
3817
3818 /* Followed by struct wmi_mgmt_send_params */
3819} __packed;
3820
3821struct wmi_sta_powersave_mode_cmd {
3822 u32 tlv_header;
3823 u32 vdev_id;
3824 u32 sta_ps_mode;
3825};
3826
3827struct wmi_sta_smps_force_mode_cmd {
3828 u32 tlv_header;
3829 u32 vdev_id;
3830 u32 forced_mode;
3831};
3832
3833struct wmi_sta_smps_param_cmd {
3834 u32 tlv_header;
3835 u32 vdev_id;
3836 u32 param;
3837 u32 value;
3838};
3839
3840struct wmi_bcn_prb_info {
3841 u32 tlv_header;
3842 u32 caps;
3843 u32 erp;
3844} __packed;
3845
3846enum {
3847 WMI_PDEV_SUSPEND,
3848 WMI_PDEV_SUSPEND_AND_DISABLE_INTR,
3849};
3850
3851struct green_ap_ps_params {
3852 u32 value;
3853};
3854
3855struct wmi_pdev_green_ap_ps_enable_cmd_param {
3856 u32 tlv_header;
3857 u32 pdev_id;
3858 u32 enable;
3859};
3860
3861struct ap_ps_params {
3862 u32 vdev_id;
3863 u32 param;
3864 u32 value;
3865};
3866
3867struct vdev_set_params {
3868 u32 if_id;
3869 u32 param_id;
3870 u32 param_value;
3871};
3872
3873struct stats_request_params {
3874 u32 stats_id;
3875 u32 vdev_id;
3876 u32 pdev_id;
3877};
3878
3879struct wmi_set_current_country_params {
3880 u8 alpha2[3];
3881};
3882
3883struct wmi_set_current_country_cmd {
3884 u32 tlv_header;
3885 u32 pdev_id;
3886 u32 new_alpha2;
3887} __packed;
3888
3889enum set_init_cc_type {
3890 WMI_COUNTRY_INFO_TYPE_ALPHA,
3891 WMI_COUNTRY_INFO_TYPE_COUNTRY_CODE,
3892 WMI_COUNTRY_INFO_TYPE_REGDOMAIN,
3893};
3894
3895enum set_init_cc_flags {
3896 INVALID_CC,
3897 CC_IS_SET,
3898 REGDMN_IS_SET,
3899 ALPHA_IS_SET,
3900};
3901
3902struct wmi_init_country_params {
3903 union {
3904 u16 country_code;
3905 u16 regdom_id;
3906 u8 alpha2[3];
3907 } cc_info;
3908 enum set_init_cc_flags flags;
3909};
3910
3911struct wmi_init_country_cmd {
3912 u32 tlv_header;
3913 u32 pdev_id;
3914 u32 init_cc_type;
3915 union {
3916 u32 country_code;
3917 u32 regdom_id;
3918 u32 alpha2;
3919 } cc_info;
3920} __packed;
3921
3922struct wmi_11d_scan_start_params {
3923 u32 vdev_id;
3924 u32 scan_period_msec;
3925 u32 start_interval_msec;
3926};
3927
3928struct wmi_11d_scan_start_cmd {
3929 u32 tlv_header;
3930 u32 vdev_id;
3931 u32 scan_period_msec;
3932 u32 start_interval_msec;
3933} __packed;
3934
3935struct wmi_11d_scan_stop_cmd {
3936 u32 tlv_header;
3937 u32 vdev_id;
3938} __packed;
3939
3940struct wmi_11d_new_cc_ev {
3941 u32 new_alpha2;
3942} __packed;
3943
3944#define THERMAL_LEVELS 1
3945struct tt_level_config {
3946 u32 tmplwm;
3947 u32 tmphwm;
3948 u32 dcoffpercent;
3949 u32 priority;
3950};
3951
3952struct thermal_mitigation_params {
3953 u32 pdev_id;
3954 u32 enable;
3955 u32 dc;
3956 u32 dc_per_event;
3957 struct tt_level_config levelconf[THERMAL_LEVELS];
3958};
3959
3960struct wmi_therm_throt_config_request_cmd {
3961 u32 tlv_header;
3962 u32 pdev_id;
3963 u32 enable;
3964 u32 dc;
3965 u32 dc_per_event;
3966 u32 therm_throt_levels;
3967} __packed;
3968
3969struct wmi_therm_throt_level_config_info {
3970 u32 tlv_header;
3971 u32 temp_lwm;
3972 u32 temp_hwm;
3973 u32 dc_off_percent;
3974 u32 prio;
3975} __packed;
3976
3977struct wmi_delba_send_cmd {
3978 u32 tlv_header;
3979 u32 vdev_id;
3980 struct wmi_mac_addr peer_macaddr;
3981 u32 tid;
3982 u32 initiator;
3983 u32 reasoncode;
3984} __packed;
3985
3986struct wmi_addba_setresponse_cmd {
3987 u32 tlv_header;
3988 u32 vdev_id;
3989 struct wmi_mac_addr peer_macaddr;
3990 u32 tid;
3991 u32 statuscode;
3992} __packed;
3993
3994struct wmi_addba_send_cmd {
3995 u32 tlv_header;
3996 u32 vdev_id;
3997 struct wmi_mac_addr peer_macaddr;
3998 u32 tid;
3999 u32 buffersize;
4000} __packed;
4001
4002struct wmi_addba_clear_resp_cmd {
4003 u32 tlv_header;
4004 u32 vdev_id;
4005 struct wmi_mac_addr peer_macaddr;
4006} __packed;
4007
4008struct wmi_pdev_pktlog_filter_info {
4009 u32 tlv_header;
4010 struct wmi_mac_addr peer_macaddr;
4011} __packed;
4012
4013struct wmi_pdev_pktlog_filter_cmd {
4014 u32 tlv_header;
4015 u32 pdev_id;
4016 u32 enable;
4017 u32 filter_type;
4018 u32 num_mac;
4019} __packed;
4020
4021enum ath11k_wmi_pktlog_enable {
4022 ATH11K_WMI_PKTLOG_ENABLE_AUTO = 0,
4023 ATH11K_WMI_PKTLOG_ENABLE_FORCE = 1,
4024};
4025
4026struct wmi_pktlog_enable_cmd {
4027 u32 tlv_header;
4028 u32 pdev_id;
4029 u32 evlist; /* WMI_PKTLOG_EVENT */
4030 u32 enable;
4031} __packed;
4032
4033struct wmi_pktlog_disable_cmd {
4034 u32 tlv_header;
4035 u32 pdev_id;
4036} __packed;
4037
4038#define DFS_PHYERR_UNIT_TEST_CMD 0
4039#define DFS_UNIT_TEST_MODULE 0x2b
4040#define DFS_UNIT_TEST_TOKEN 0xAA
4041
4042enum dfs_test_args_idx {
4043 DFS_TEST_CMDID = 0,
4044 DFS_TEST_PDEV_ID,
4045 DFS_TEST_RADAR_PARAM,
4046 DFS_MAX_TEST_ARGS,
4047};
4048
4049struct wmi_dfs_unit_test_arg {
4050 u32 cmd_id;
4051 u32 pdev_id;
4052 u32 radar_param;
4053};
4054
4055struct wmi_unit_test_cmd {
4056 u32 tlv_header;
4057 u32 vdev_id;
4058 u32 module_id;
4059 u32 num_args;
4060 u32 diag_token;
4061 /* Followed by test args*/
4062} __packed;
4063
4064#define MAX_SUPPORTED_RATES 128
4065
4066struct beacon_tmpl_params {
4067 u8 vdev_id;
4068 u32 tim_ie_offset;
4069 u32 tmpl_len;
4070 u32 tmpl_len_aligned;
4071 u32 csa_switch_count_offset;
4072 u32 ext_csa_switch_count_offset;
4073 u8 *frm;
4074};
4075
4076struct wmi_rate_set {
4077 u32 num_rates;
4078 u32 rates[(MAX_SUPPORTED_RATES / 4) + 1];
4079};
4080
4081struct wmi_vht_rate_set {
4082 u32 tlv_header;
4083 u32 rx_max_rate;
4084 u32 rx_mcs_set;
4085 u32 tx_max_rate;
4086 u32 tx_mcs_set;
4087 u32 tx_max_mcs_nss;
4088} __packed;
4089
4090struct wmi_he_rate_set {
4091 u32 tlv_header;
4092
4093 /* MCS at which the peer can receive */
4094 u32 rx_mcs_set;
4095
4096 /* MCS at which the peer can transmit */
4097 u32 tx_mcs_set;
4098} __packed;
4099
4100#define MAX_REG_RULES 10
4101#define REG_ALPHA2_LEN 2
4102#define MAX_6GHZ_REG_RULES 5
4103
4104enum wmi_start_event_param {
4105 WMI_VDEV_START_RESP_EVENT = 0,
4106 WMI_VDEV_RESTART_RESP_EVENT,
4107};
4108
4109struct wmi_vdev_start_resp_event {
4110 u32 vdev_id;
4111 u32 requestor_id;
4112 enum wmi_start_event_param resp_type;
4113 u32 status;
4114 u32 chain_mask;
4115 u32 smps_mode;
4116 union {
4117 u32 mac_id;
4118 u32 pdev_id;
4119 };
4120 u32 cfgd_tx_streams;
4121 u32 cfgd_rx_streams;
4122} __packed;
4123
4124/* VDEV start response status codes */
4125enum wmi_vdev_start_resp_status_code {
4126 WMI_VDEV_START_RESPONSE_STATUS_SUCCESS = 0,
4127 WMI_VDEV_START_RESPONSE_INVALID_VDEVID = 1,
4128 WMI_VDEV_START_RESPONSE_NOT_SUPPORTED = 2,
4129 WMI_VDEV_START_RESPONSE_DFS_VIOLATION = 3,
4130 WMI_VDEV_START_RESPONSE_INVALID_REGDOMAIN = 4,
4131};
4132
4133/* Regaulatory Rule Flags Passed by FW */
4134#define REGULATORY_CHAN_DISABLED BIT(0)
4135#define REGULATORY_CHAN_NO_IR BIT(1)
4136#define REGULATORY_CHAN_RADAR BIT(3)
4137#define REGULATORY_CHAN_NO_OFDM BIT(6)
4138#define REGULATORY_CHAN_INDOOR_ONLY BIT(9)
4139
4140#define REGULATORY_CHAN_NO_HT40 BIT(4)
4141#define REGULATORY_CHAN_NO_80MHZ BIT(7)
4142#define REGULATORY_CHAN_NO_160MHZ BIT(8)
4143#define REGULATORY_CHAN_NO_20MHZ BIT(11)
4144#define REGULATORY_CHAN_NO_10MHZ BIT(12)
4145
4146enum wmi_reg_chan_list_cmd_type {
4147 WMI_REG_CHAN_LIST_CC_ID = 0,
4148 WMI_REG_CHAN_LIST_CC_EXT_ID = 1,
4149};
4150
4151enum wmi_reg_cc_setting_code {
4152 WMI_REG_SET_CC_STATUS_PASS = 0,
4153 WMI_REG_CURRENT_ALPHA2_NOT_FOUND = 1,
4154 WMI_REG_INIT_ALPHA2_NOT_FOUND = 2,
4155 WMI_REG_SET_CC_CHANGE_NOT_ALLOWED = 3,
4156 WMI_REG_SET_CC_STATUS_NO_MEMORY = 4,
4157 WMI_REG_SET_CC_STATUS_FAIL = 5,
4158
4159 /* add new setting code above, update in
4160 * @enum cc_setting_code as well.
4161 * Also handle it in ath11k_wmi_cc_setting_code_to_reg()
4162 */
4163};
4164
4165enum cc_setting_code {
4166 REG_SET_CC_STATUS_PASS = 0,
4167 REG_CURRENT_ALPHA2_NOT_FOUND = 1,
4168 REG_INIT_ALPHA2_NOT_FOUND = 2,
4169 REG_SET_CC_CHANGE_NOT_ALLOWED = 3,
4170 REG_SET_CC_STATUS_NO_MEMORY = 4,
4171 REG_SET_CC_STATUS_FAIL = 5,
4172
4173 /* add new setting code above, update in
4174 * @enum wmi_reg_cc_setting_code as well.
4175 * Also handle it in ath11k_cc_status_to_str()
4176 */
4177};
4178
4179static inline enum cc_setting_code
4180ath11k_wmi_cc_setting_code_to_reg(enum wmi_reg_cc_setting_code status_code)
4181{
4182 switch (status_code) {
4183 case WMI_REG_SET_CC_STATUS_PASS:
4184 return REG_SET_CC_STATUS_PASS;
4185 case WMI_REG_CURRENT_ALPHA2_NOT_FOUND:
4186 return REG_CURRENT_ALPHA2_NOT_FOUND;
4187 case WMI_REG_INIT_ALPHA2_NOT_FOUND:
4188 return REG_INIT_ALPHA2_NOT_FOUND;
4189 case WMI_REG_SET_CC_CHANGE_NOT_ALLOWED:
4190 return REG_SET_CC_CHANGE_NOT_ALLOWED;
4191 case WMI_REG_SET_CC_STATUS_NO_MEMORY:
4192 return REG_SET_CC_STATUS_NO_MEMORY;
4193 case WMI_REG_SET_CC_STATUS_FAIL:
4194 return REG_SET_CC_STATUS_FAIL;
4195 }
4196
4197 return REG_SET_CC_STATUS_FAIL;
4198}
4199
4200static inline const char *ath11k_cc_status_to_str(enum cc_setting_code code)
4201{
4202 switch (code) {
4203 case REG_SET_CC_STATUS_PASS:
4204 return "REG_SET_CC_STATUS_PASS";
4205 case REG_CURRENT_ALPHA2_NOT_FOUND:
4206 return "REG_CURRENT_ALPHA2_NOT_FOUND";
4207 case REG_INIT_ALPHA2_NOT_FOUND:
4208 return "REG_INIT_ALPHA2_NOT_FOUND";
4209 case REG_SET_CC_CHANGE_NOT_ALLOWED:
4210 return "REG_SET_CC_CHANGE_NOT_ALLOWED";
4211 case REG_SET_CC_STATUS_NO_MEMORY:
4212 return "REG_SET_CC_STATUS_NO_MEMORY";
4213 case REG_SET_CC_STATUS_FAIL:
4214 return "REG_SET_CC_STATUS_FAIL";
4215 }
4216
4217 return "Unknown CC status";
4218}
4219
4220enum wmi_reg_6ghz_ap_type {
4221 WMI_REG_INDOOR_AP = 0,
4222 WMI_REG_STANDARD_POWER_AP = 1,
4223 WMI_REG_VERY_LOW_POWER_AP = 2,
4224
4225 /* add AP type above, handle in ath11k_6ghz_ap_type_to_str()
4226 */
4227 WMI_REG_CURRENT_MAX_AP_TYPE,
4228 WMI_REG_MAX_AP_TYPE = 7,
4229};
4230
4231static inline const char *
4232ath11k_6ghz_ap_type_to_str(enum wmi_reg_6ghz_ap_type type)
4233{
4234 switch (type) {
4235 case WMI_REG_INDOOR_AP:
4236 return "INDOOR AP";
4237 case WMI_REG_STANDARD_POWER_AP:
4238 return "STANDARD POWER AP";
4239 case WMI_REG_VERY_LOW_POWER_AP:
4240 return "VERY LOW POWER AP";
4241 case WMI_REG_CURRENT_MAX_AP_TYPE:
4242 return "CURRENT_MAX_AP_TYPE";
4243 case WMI_REG_MAX_AP_TYPE:
4244 return "MAX_AP_TYPE";
4245 }
4246
4247 return "unknown 6 GHz AP type";
4248}
4249
4250enum wmi_reg_6ghz_client_type {
4251 WMI_REG_DEFAULT_CLIENT = 0,
4252 WMI_REG_SUBORDINATE_CLIENT = 1,
4253 WMI_REG_MAX_CLIENT_TYPE = 2,
4254
4255 /* add client type above, handle it in
4256 * ath11k_6ghz_client_type_to_str()
4257 */
4258};
4259
4260static inline const char *
4261ath11k_6ghz_client_type_to_str(enum wmi_reg_6ghz_client_type type)
4262{
4263 switch (type) {
4264 case WMI_REG_DEFAULT_CLIENT:
4265 return "DEFAULT CLIENT";
4266 case WMI_REG_SUBORDINATE_CLIENT:
4267 return "SUBORDINATE CLIENT";
4268 case WMI_REG_MAX_CLIENT_TYPE:
4269 return "MAX_CLIENT_TYPE";
4270 }
4271
4272 return "unknown 6 GHz client type";
4273}
4274
4275enum reg_subdomains_6ghz {
4276 EMPTY_6GHZ = 0x0,
4277 FCC1_CLIENT_LPI_REGULAR_6GHZ = 0x01,
4278 FCC1_CLIENT_SP_6GHZ = 0x02,
4279 FCC1_AP_LPI_6GHZ = 0x03,
4280 FCC1_CLIENT_LPI_SUBORDINATE = FCC1_AP_LPI_6GHZ,
4281 FCC1_AP_SP_6GHZ = 0x04,
4282 ETSI1_LPI_6GHZ = 0x10,
4283 ETSI1_VLP_6GHZ = 0x11,
4284 ETSI2_LPI_6GHZ = 0x12,
4285 ETSI2_VLP_6GHZ = 0x13,
4286 APL1_LPI_6GHZ = 0x20,
4287 APL1_VLP_6GHZ = 0x21,
4288
4289 /* add sub-domain above, handle it in
4290 * ath11k_sub_reg_6ghz_to_str()
4291 */
4292};
4293
4294static inline const char *
4295ath11k_sub_reg_6ghz_to_str(enum reg_subdomains_6ghz sub_id)
4296{
4297 switch (sub_id) {
4298 case EMPTY_6GHZ:
4299 return "N/A";
4300 case FCC1_CLIENT_LPI_REGULAR_6GHZ:
4301 return "FCC1_CLIENT_LPI_REGULAR_6GHZ";
4302 case FCC1_CLIENT_SP_6GHZ:
4303 return "FCC1_CLIENT_SP_6GHZ";
4304 case FCC1_AP_LPI_6GHZ:
4305 return "FCC1_AP_LPI_6GHZ/FCC1_CLIENT_LPI_SUBORDINATE";
4306 case FCC1_AP_SP_6GHZ:
4307 return "FCC1_AP_SP_6GHZ";
4308 case ETSI1_LPI_6GHZ:
4309 return "ETSI1_LPI_6GHZ";
4310 case ETSI1_VLP_6GHZ:
4311 return "ETSI1_VLP_6GHZ";
4312 case ETSI2_LPI_6GHZ:
4313 return "ETSI2_LPI_6GHZ";
4314 case ETSI2_VLP_6GHZ:
4315 return "ETSI2_VLP_6GHZ";
4316 case APL1_LPI_6GHZ:
4317 return "APL1_LPI_6GHZ";
4318 case APL1_VLP_6GHZ:
4319 return "APL1_VLP_6GHZ";
4320 }
4321
4322 return "unknown sub reg id";
4323}
4324
4325enum reg_super_domain_6ghz {
4326 FCC1_6GHZ = 0x01,
4327 ETSI1_6GHZ = 0x02,
4328 ETSI2_6GHZ = 0x03,
4329 APL1_6GHZ = 0x04,
4330 FCC1_6GHZ_CL = 0x05,
4331
4332 /* add super domain above, handle it in
4333 * ath11k_super_reg_6ghz_to_str()
4334 */
4335};
4336
4337static inline const char *
4338ath11k_super_reg_6ghz_to_str(enum reg_super_domain_6ghz domain_id)
4339{
4340 switch (domain_id) {
4341 case FCC1_6GHZ:
4342 return "FCC1_6GHZ";
4343 case ETSI1_6GHZ:
4344 return "ETSI1_6GHZ";
4345 case ETSI2_6GHZ:
4346 return "ETSI2_6GHZ";
4347 case APL1_6GHZ:
4348 return "APL1_6GHZ";
4349 case FCC1_6GHZ_CL:
4350 return "FCC1_6GHZ_CL";
4351 }
4352
4353 return "unknown domain id";
4354}
4355
4356struct cur_reg_rule {
4357 u16 start_freq;
4358 u16 end_freq;
4359 u16 max_bw;
4360 u8 reg_power;
4361 u8 ant_gain;
4362 u16 flags;
4363 bool psd_flag;
4364 s8 psd_eirp;
4365};
4366
4367struct cur_regulatory_info {
4368 enum cc_setting_code status_code;
4369 u8 num_phy;
4370 u8 phy_id;
4371 u16 reg_dmn_pair;
4372 u16 ctry_code;
4373 u8 alpha2[REG_ALPHA2_LEN + 1];
4374 u32 dfs_region;
4375 u32 phybitmap;
4376 u32 min_bw_2ghz;
4377 u32 max_bw_2ghz;
4378 u32 min_bw_5ghz;
4379 u32 max_bw_5ghz;
4380 u32 num_2ghz_reg_rules;
4381 u32 num_5ghz_reg_rules;
4382 struct cur_reg_rule *reg_rules_2ghz_ptr;
4383 struct cur_reg_rule *reg_rules_5ghz_ptr;
4384 bool is_ext_reg_event;
4385 enum wmi_reg_6ghz_client_type client_type;
4386 bool rnr_tpe_usable;
4387 bool unspecified_ap_usable;
4388 u8 domain_code_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
4389 u8 domain_code_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4390 u32 domain_code_6ghz_super_id;
4391 u32 min_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
4392 u32 max_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
4393 u32 min_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4394 u32 max_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4395 u32 num_6ghz_rules_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
4396 u32 num_6ghz_rules_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4397 struct cur_reg_rule *reg_rules_6ghz_ap_ptr[WMI_REG_CURRENT_MAX_AP_TYPE];
4398 struct cur_reg_rule *reg_rules_6ghz_client_ptr
4399 [WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4400};
4401
4402struct wmi_reg_chan_list_cc_event {
4403 u32 status_code;
4404 u32 phy_id;
4405 u32 alpha2;
4406 u32 num_phy;
4407 u32 country_id;
4408 u32 domain_code;
4409 u32 dfs_region;
4410 u32 phybitmap;
4411 u32 min_bw_2ghz;
4412 u32 max_bw_2ghz;
4413 u32 min_bw_5ghz;
4414 u32 max_bw_5ghz;
4415 u32 num_2ghz_reg_rules;
4416 u32 num_5ghz_reg_rules;
4417} __packed;
4418
4419struct wmi_regulatory_rule_struct {
4420 u32 tlv_header;
4421 u32 freq_info;
4422 u32 bw_pwr_info;
4423 u32 flag_info;
4424};
4425
4426#define WMI_REG_CLIENT_MAX 4
4427
4428struct wmi_reg_chan_list_cc_ext_event {
4429 u32 status_code;
4430 u32 phy_id;
4431 u32 alpha2;
4432 u32 num_phy;
4433 u32 country_id;
4434 u32 domain_code;
4435 u32 dfs_region;
4436 u32 phybitmap;
4437 u32 min_bw_2ghz;
4438 u32 max_bw_2ghz;
4439 u32 min_bw_5ghz;
4440 u32 max_bw_5ghz;
4441 u32 num_2ghz_reg_rules;
4442 u32 num_5ghz_reg_rules;
4443 u32 client_type;
4444 u32 rnr_tpe_usable;
4445 u32 unspecified_ap_usable;
4446 u32 domain_code_6ghz_ap_lpi;
4447 u32 domain_code_6ghz_ap_sp;
4448 u32 domain_code_6ghz_ap_vlp;
4449 u32 domain_code_6ghz_client_lpi[WMI_REG_CLIENT_MAX];
4450 u32 domain_code_6ghz_client_sp[WMI_REG_CLIENT_MAX];
4451 u32 domain_code_6ghz_client_vlp[WMI_REG_CLIENT_MAX];
4452 u32 domain_code_6ghz_super_id;
4453 u32 min_bw_6ghz_ap_sp;
4454 u32 max_bw_6ghz_ap_sp;
4455 u32 min_bw_6ghz_ap_lpi;
4456 u32 max_bw_6ghz_ap_lpi;
4457 u32 min_bw_6ghz_ap_vlp;
4458 u32 max_bw_6ghz_ap_vlp;
4459 u32 min_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX];
4460 u32 max_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX];
4461 u32 min_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX];
4462 u32 max_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX];
4463 u32 min_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX];
4464 u32 max_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX];
4465 u32 num_6ghz_reg_rules_ap_sp;
4466 u32 num_6ghz_reg_rules_ap_lpi;
4467 u32 num_6ghz_reg_rules_ap_vlp;
4468 u32 num_6ghz_reg_rules_client_sp[WMI_REG_CLIENT_MAX];
4469 u32 num_6ghz_reg_rules_client_lpi[WMI_REG_CLIENT_MAX];
4470 u32 num_6ghz_reg_rules_client_vlp[WMI_REG_CLIENT_MAX];
4471} __packed;
4472
4473struct wmi_regulatory_ext_rule {
4474 u32 tlv_header;
4475 u32 freq_info;
4476 u32 bw_pwr_info;
4477 u32 flag_info;
4478 u32 psd_power_info;
4479} __packed;
4480
4481struct wmi_vdev_delete_resp_event {
4482 u32 vdev_id;
4483} __packed;
4484
4485struct wmi_peer_delete_resp_event {
4486 u32 vdev_id;
4487 struct wmi_mac_addr peer_macaddr;
4488} __packed;
4489
4490struct wmi_bcn_tx_status_event {
4491 u32 vdev_id;
4492 u32 tx_status;
4493} __packed;
4494
4495struct wmi_vdev_stopped_event {
4496 u32 vdev_id;
4497} __packed;
4498
4499struct wmi_pdev_bss_chan_info_event {
4500 u32 freq; /* Units in MHz */
4501 u32 noise_floor; /* units are dBm */
4502 /* rx clear - how often the channel was unused */
4503 u32 rx_clear_count_low;
4504 u32 rx_clear_count_high;
4505 /* cycle count - elapsed time during measured period, in clock ticks */
4506 u32 cycle_count_low;
4507 u32 cycle_count_high;
4508 /* tx cycle count - elapsed time spent in tx, in clock ticks */
4509 u32 tx_cycle_count_low;
4510 u32 tx_cycle_count_high;
4511 /* rx cycle count - elapsed time spent in rx, in clock ticks */
4512 u32 rx_cycle_count_low;
4513 u32 rx_cycle_count_high;
4514 /*rx_cycle cnt for my bss in 64bits format */
4515 u32 rx_bss_cycle_count_low;
4516 u32 rx_bss_cycle_count_high;
4517 u32 pdev_id;
4518} __packed;
4519
4520#define WMI_VDEV_INSTALL_KEY_COMPL_STATUS_SUCCESS 0
4521
4522struct wmi_vdev_install_key_compl_event {
4523 u32 vdev_id;
4524 struct wmi_mac_addr peer_macaddr;
4525 u32 key_idx;
4526 u32 key_flags;
4527 u32 status;
4528} __packed;
4529
4530struct wmi_vdev_install_key_complete_arg {
4531 u32 vdev_id;
4532 const u8 *macaddr;
4533 u32 key_idx;
4534 u32 key_flags;
4535 u32 status;
4536};
4537
4538struct wmi_peer_assoc_conf_event {
4539 u32 vdev_id;
4540 struct wmi_mac_addr peer_macaddr;
4541} __packed;
4542
4543struct wmi_peer_assoc_conf_arg {
4544 u32 vdev_id;
4545 const u8 *macaddr;
4546};
4547
4548struct wmi_fils_discovery_event {
4549 u32 vdev_id;
4550 u32 fils_tt;
4551 u32 tbtt;
4552} __packed;
4553
4554struct wmi_probe_resp_tx_status_event {
4555 u32 vdev_id;
4556 u32 tx_status;
4557} __packed;
4558
4559/*
4560 * PDEV statistics
4561 */
4562struct wmi_pdev_stats_base {
4563 s32 chan_nf;
4564 u32 tx_frame_count; /* Cycles spent transmitting frames */
4565 u32 rx_frame_count; /* Cycles spent receiving frames */
4566 u32 rx_clear_count; /* Total channel busy time, evidently */
4567 u32 cycle_count; /* Total on-channel time */
4568 u32 phy_err_count;
4569 u32 chan_tx_pwr;
4570} __packed;
4571
4572struct wmi_pdev_stats_extra {
4573 u32 ack_rx_bad;
4574 u32 rts_bad;
4575 u32 rts_good;
4576 u32 fcs_bad;
4577 u32 no_beacons;
4578 u32 mib_int_count;
4579} __packed;
4580
4581struct wmi_pdev_stats_tx {
4582 /* Num HTT cookies queued to dispatch list */
4583 s32 comp_queued;
4584
4585 /* Num HTT cookies dispatched */
4586 s32 comp_delivered;
4587
4588 /* Num MSDU queued to WAL */
4589 s32 msdu_enqued;
4590
4591 /* Num MPDU queue to WAL */
4592 s32 mpdu_enqued;
4593
4594 /* Num MSDUs dropped by WMM limit */
4595 s32 wmm_drop;
4596
4597 /* Num Local frames queued */
4598 s32 local_enqued;
4599
4600 /* Num Local frames done */
4601 s32 local_freed;
4602
4603 /* Num queued to HW */
4604 s32 hw_queued;
4605
4606 /* Num PPDU reaped from HW */
4607 s32 hw_reaped;
4608
4609 /* Num underruns */
4610 s32 underrun;
4611
4612 /* Num hw paused */
4613 u32 hw_paused;
4614
4615 /* Num PPDUs cleaned up in TX abort */
4616 s32 tx_abort;
4617
4618 /* Num MPDUs requeued by SW */
4619 s32 mpdus_requeued;
4620
4621 /* excessive retries */
4622 u32 tx_ko;
4623
4624 u32 tx_xretry;
4625
4626 /* data hw rate code */
4627 u32 data_rc;
4628
4629 /* Scheduler self triggers */
4630 u32 self_triggers;
4631
4632 /* frames dropped due to excessive sw retries */
4633 u32 sw_retry_failure;
4634
4635 /* illegal rate phy errors */
4636 u32 illgl_rate_phy_err;
4637
4638 /* wal pdev continuous xretry */
4639 u32 pdev_cont_xretry;
4640
4641 /* wal pdev tx timeouts */
4642 u32 pdev_tx_timeout;
4643
4644 /* wal pdev resets */
4645 u32 pdev_resets;
4646
4647 /* frames dropped due to non-availability of stateless TIDs */
4648 u32 stateless_tid_alloc_failure;
4649
4650 /* PhY/BB underrun */
4651 u32 phy_underrun;
4652
4653 /* MPDU is more than txop limit */
4654 u32 txop_ovf;
4655
4656 /* Num sequences posted */
4657 u32 seq_posted;
4658
4659 /* Num sequences failed in queueing */
4660 u32 seq_failed_queueing;
4661
4662 /* Num sequences completed */
4663 u32 seq_completed;
4664
4665 /* Num sequences restarted */
4666 u32 seq_restarted;
4667
4668 /* Num of MU sequences posted */
4669 u32 mu_seq_posted;
4670
4671 /* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT
4672 * (Reset,channel change)
4673 */
4674 s32 mpdus_sw_flush;
4675
4676 /* Num MPDUs filtered by HW, all filter condition (TTL expired) */
4677 s32 mpdus_hw_filter;
4678
4679 /* Num MPDUs truncated by PDG (TXOP, TBTT,
4680 * PPDU_duration based on rate, dyn_bw)
4681 */
4682 s32 mpdus_truncated;
4683
4684 /* Num MPDUs that was tried but didn't receive ACK or BA */
4685 s32 mpdus_ack_failed;
4686
4687 /* Num MPDUs that was dropped du to expiry. */
4688 s32 mpdus_expired;
4689} __packed;
4690
4691struct wmi_pdev_stats_rx {
4692 /* Cnts any change in ring routing mid-ppdu */
4693 s32 mid_ppdu_route_change;
4694
4695 /* Total number of statuses processed */
4696 s32 status_rcvd;
4697
4698 /* Extra frags on rings 0-3 */
4699 s32 r0_frags;
4700 s32 r1_frags;
4701 s32 r2_frags;
4702 s32 r3_frags;
4703
4704 /* MSDUs / MPDUs delivered to HTT */
4705 s32 htt_msdus;
4706 s32 htt_mpdus;
4707
4708 /* MSDUs / MPDUs delivered to local stack */
4709 s32 loc_msdus;
4710 s32 loc_mpdus;
4711
4712 /* AMSDUs that have more MSDUs than the status ring size */
4713 s32 oversize_amsdu;
4714
4715 /* Number of PHY errors */
4716 s32 phy_errs;
4717
4718 /* Number of PHY errors drops */
4719 s32 phy_err_drop;
4720
4721 /* Number of mpdu errors - FCS, MIC, ENC etc. */
4722 s32 mpdu_errs;
4723
4724 /* Num overflow errors */
4725 s32 rx_ovfl_errs;
4726} __packed;
4727
4728struct wmi_pdev_stats {
4729 struct wmi_pdev_stats_base base;
4730 struct wmi_pdev_stats_tx tx;
4731 struct wmi_pdev_stats_rx rx;
4732} __packed;
4733
4734#define WLAN_MAX_AC 4
4735#define MAX_TX_RATE_VALUES 10
4736#define MAX_TX_RATE_VALUES 10
4737
4738struct wmi_vdev_stats {
4739 u32 vdev_id;
4740 u32 beacon_snr;
4741 u32 data_snr;
4742 u32 num_tx_frames[WLAN_MAX_AC];
4743 u32 num_rx_frames;
4744 u32 num_tx_frames_retries[WLAN_MAX_AC];
4745 u32 num_tx_frames_failures[WLAN_MAX_AC];
4746 u32 num_rts_fail;
4747 u32 num_rts_success;
4748 u32 num_rx_err;
4749 u32 num_rx_discard;
4750 u32 num_tx_not_acked;
4751 u32 tx_rate_history[MAX_TX_RATE_VALUES];
4752 u32 beacon_rssi_history[MAX_TX_RATE_VALUES];
4753} __packed;
4754
4755struct wmi_bcn_stats {
4756 u32 vdev_id;
4757 u32 tx_bcn_succ_cnt;
4758 u32 tx_bcn_outage_cnt;
4759} __packed;
4760
4761struct wmi_stats_event {
4762 u32 stats_id;
4763 u32 num_pdev_stats;
4764 u32 num_vdev_stats;
4765 u32 num_peer_stats;
4766 u32 num_bcnflt_stats;
4767 u32 num_chan_stats;
4768 u32 num_mib_stats;
4769 u32 pdev_id;
4770 u32 num_bcn_stats;
4771 u32 num_peer_extd_stats;
4772 u32 num_peer_extd2_stats;
4773} __packed;
4774
4775struct wmi_rssi_stats {
4776 u32 vdev_id;
4777 u32 rssi_avg_beacon[WMI_MAX_CHAINS];
4778 u32 rssi_avg_data[WMI_MAX_CHAINS];
4779 struct wmi_mac_addr peer_macaddr;
4780} __packed;
4781
4782struct wmi_per_chain_rssi_stats {
4783 u32 num_per_chain_rssi_stats;
4784} __packed;
4785
4786struct wmi_pdev_ctl_failsafe_chk_event {
4787 u32 pdev_id;
4788 u32 ctl_failsafe_status;
4789} __packed;
4790
4791struct wmi_pdev_csa_switch_ev {
4792 u32 pdev_id;
4793 u32 current_switch_count;
4794 u32 num_vdevs;
4795} __packed;
4796
4797struct wmi_pdev_radar_ev {
4798 u32 pdev_id;
4799 u32 detection_mode;
4800 u32 chan_freq;
4801 u32 chan_width;
4802 u32 detector_id;
4803 u32 segment_id;
4804 u32 timestamp;
4805 u32 is_chirp;
4806 s32 freq_offset;
4807 s32 sidx;
4808} __packed;
4809
4810struct wmi_pdev_temperature_event {
4811 /* temperature value in Celsius degree */
4812 s32 temp;
4813 u32 pdev_id;
4814} __packed;
4815
4816#define WMI_RX_STATUS_OK 0x00
4817#define WMI_RX_STATUS_ERR_CRC 0x01
4818#define WMI_RX_STATUS_ERR_DECRYPT 0x08
4819#define WMI_RX_STATUS_ERR_MIC 0x10
4820#define WMI_RX_STATUS_ERR_KEY_CACHE_MISS 0x20
4821
4822#define WLAN_MGMT_TXRX_HOST_MAX_ANTENNA 4
4823
4824struct mgmt_rx_event_params {
4825 u32 chan_freq;
4826 u32 channel;
4827 u32 snr;
4828 u8 rssi_ctl[WLAN_MGMT_TXRX_HOST_MAX_ANTENNA];
4829 u32 rate;
4830 enum wmi_phy_mode phy_mode;
4831 u32 buf_len;
4832 int status;
4833 u32 flags;
4834 int rssi;
4835 u32 tsf_delta;
4836 u8 pdev_id;
4837};
4838
4839#define ATH_MAX_ANTENNA 4
4840
4841struct wmi_mgmt_rx_hdr {
4842 u32 channel;
4843 u32 snr;
4844 u32 rate;
4845 u32 phy_mode;
4846 u32 buf_len;
4847 u32 status;
4848 u32 rssi_ctl[ATH_MAX_ANTENNA];
4849 u32 flags;
4850 int rssi;
4851 u32 tsf_delta;
4852 u32 rx_tsf_l32;
4853 u32 rx_tsf_u32;
4854 u32 pdev_id;
4855 u32 chan_freq;
4856} __packed;
4857
4858#define MAX_ANTENNA_EIGHT 8
4859
4860struct wmi_rssi_ctl_ext {
4861 u32 tlv_header;
4862 u32 rssi_ctl_ext[MAX_ANTENNA_EIGHT - ATH_MAX_ANTENNA];
4863};
4864
4865struct wmi_mgmt_tx_compl_event {
4866 u32 desc_id;
4867 u32 status;
4868 u32 pdev_id;
4869 u32 ppdu_id;
4870 u32 ack_rssi;
4871} __packed;
4872
4873struct wmi_scan_event {
4874 u32 event_type; /* %WMI_SCAN_EVENT_ */
4875 u32 reason; /* %WMI_SCAN_REASON_ */
4876 u32 channel_freq; /* only valid for WMI_SCAN_EVENT_FOREIGN_CHANNEL */
4877 u32 scan_req_id;
4878 u32 scan_id;
4879 u32 vdev_id;
4880 /* TSF Timestamp when the scan event (%WMI_SCAN_EVENT_) is completed
4881 * In case of AP it is TSF of the AP vdev
4882 * In case of STA connected state, this is the TSF of the AP
4883 * In case of STA not connected, it will be the free running HW timer
4884 */
4885 u32 tsf_timestamp;
4886} __packed;
4887
4888struct wmi_peer_sta_kickout_arg {
4889 const u8 *mac_addr;
4890};
4891
4892struct wmi_peer_sta_kickout_event {
4893 struct wmi_mac_addr peer_macaddr;
4894} __packed;
4895
4896enum wmi_roam_reason {
4897 WMI_ROAM_REASON_BETTER_AP = 1,
4898 WMI_ROAM_REASON_BEACON_MISS = 2,
4899 WMI_ROAM_REASON_LOW_RSSI = 3,
4900 WMI_ROAM_REASON_SUITABLE_AP_FOUND = 4,
4901 WMI_ROAM_REASON_HO_FAILED = 5,
4902
4903 /* keep last */
4904 WMI_ROAM_REASON_MAX,
4905};
4906
4907struct wmi_roam_event {
4908 u32 vdev_id;
4909 u32 reason;
4910 u32 rssi;
4911} __packed;
4912
4913#define WMI_CHAN_INFO_START_RESP 0
4914#define WMI_CHAN_INFO_END_RESP 1
4915
4916struct wmi_chan_info_event {
4917 u32 err_code;
4918 u32 freq;
4919 u32 cmd_flags;
4920 u32 noise_floor;
4921 u32 rx_clear_count;
4922 u32 cycle_count;
4923 u32 chan_tx_pwr_range;
4924 u32 chan_tx_pwr_tp;
4925 u32 rx_frame_count;
4926 u32 my_bss_rx_cycle_count;
4927 u32 rx_11b_mode_data_duration;
4928 u32 tx_frame_cnt;
4929 u32 mac_clk_mhz;
4930 u32 vdev_id;
4931} __packed;
4932
4933struct ath11k_targ_cap {
4934 u32 phy_capability;
4935 u32 max_frag_entry;
4936 u32 num_rf_chains;
4937 u32 ht_cap_info;
4938 u32 vht_cap_info;
4939 u32 vht_supp_mcs;
4940 u32 hw_min_tx_power;
4941 u32 hw_max_tx_power;
4942 u32 sys_cap_info;
4943 u32 min_pkt_size_enable;
4944 u32 max_bcn_ie_size;
4945 u32 max_num_scan_channels;
4946 u32 max_supported_macs;
4947 u32 wmi_fw_sub_feat_caps;
4948 u32 txrx_chainmask;
4949 u32 default_dbs_hw_mode_index;
4950 u32 num_msdu_desc;
4951};
4952
4953enum wmi_vdev_type {
4954 WMI_VDEV_TYPE_AP = 1,
4955 WMI_VDEV_TYPE_STA = 2,
4956 WMI_VDEV_TYPE_IBSS = 3,
4957 WMI_VDEV_TYPE_MONITOR = 4,
4958};
4959
4960enum wmi_vdev_subtype {
4961 WMI_VDEV_SUBTYPE_NONE,
4962 WMI_VDEV_SUBTYPE_P2P_DEVICE,
4963 WMI_VDEV_SUBTYPE_P2P_CLIENT,
4964 WMI_VDEV_SUBTYPE_P2P_GO,
4965 WMI_VDEV_SUBTYPE_PROXY_STA,
4966 WMI_VDEV_SUBTYPE_MESH_NON_11S,
4967 WMI_VDEV_SUBTYPE_MESH_11S,
4968};
4969
4970enum wmi_sta_powersave_param {
4971 WMI_STA_PS_PARAM_RX_WAKE_POLICY = 0,
4972 WMI_STA_PS_PARAM_TX_WAKE_THRESHOLD = 1,
4973 WMI_STA_PS_PARAM_PSPOLL_COUNT = 2,
4974 WMI_STA_PS_PARAM_INACTIVITY_TIME = 3,
4975 WMI_STA_PS_PARAM_UAPSD = 4,
4976};
4977
4978#define WMI_UAPSD_AC_TYPE_DELI 0
4979#define WMI_UAPSD_AC_TYPE_TRIG 1
4980
4981#define WMI_UAPSD_AC_BIT_MASK(ac, type) \
4982 ((type == WMI_UAPSD_AC_TYPE_DELI) ? \
4983 (1 << (ac << 1)) : (1 << ((ac << 1) + 1)))
4984
4985enum wmi_sta_ps_param_uapsd {
4986 WMI_STA_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0),
4987 WMI_STA_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1),
4988 WMI_STA_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2),
4989 WMI_STA_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3),
4990 WMI_STA_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4),
4991 WMI_STA_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5),
4992 WMI_STA_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6),
4993 WMI_STA_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7),
4994};
4995
4996#define WMI_STA_UAPSD_MAX_INTERVAL_MSEC UINT_MAX
4997
4998struct wmi_sta_uapsd_auto_trig_param {
4999 u32 wmm_ac;
5000 u32 user_priority;
5001 u32 service_interval;
5002 u32 suspend_interval;
5003 u32 delay_interval;
5004};
5005
5006struct wmi_sta_uapsd_auto_trig_cmd_fixed_param {
5007 u32 vdev_id;
5008 struct wmi_mac_addr peer_macaddr;
5009 u32 num_ac;
5010};
5011
5012struct wmi_sta_uapsd_auto_trig_arg {
5013 u32 wmm_ac;
5014 u32 user_priority;
5015 u32 service_interval;
5016 u32 suspend_interval;
5017 u32 delay_interval;
5018};
5019
5020enum wmi_sta_ps_param_tx_wake_threshold {
5021 WMI_STA_PS_TX_WAKE_THRESHOLD_NEVER = 0,
5022 WMI_STA_PS_TX_WAKE_THRESHOLD_ALWAYS = 1,
5023
5024 /* Values greater than one indicate that many TX attempts per beacon
5025 * interval before the STA will wake up
5026 */
5027};
5028
5029/* The maximum number of PS-Poll frames the FW will send in response to
5030 * traffic advertised in TIM before waking up (by sending a null frame with PS
5031 * = 0). Value 0 has a special meaning: there is no maximum count and the FW
5032 * will send as many PS-Poll as are necessary to retrieve buffered BU. This
5033 * parameter is used when the RX wake policy is
5034 * WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD and ignored when the RX wake
5035 * policy is WMI_STA_PS_RX_WAKE_POLICY_WAKE.
5036 */
5037enum wmi_sta_ps_param_pspoll_count {
5038 WMI_STA_PS_PSPOLL_COUNT_NO_MAX = 0,
5039 /* Values greater than 0 indicate the maximum number of PS-Poll frames
5040 * FW will send before waking up.
5041 */
5042};
5043
5044/* U-APSD configuration of peer station from (re)assoc request and TSPECs */
5045enum wmi_ap_ps_param_uapsd {
5046 WMI_AP_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0),
5047 WMI_AP_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1),
5048 WMI_AP_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2),
5049 WMI_AP_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3),
5050 WMI_AP_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4),
5051 WMI_AP_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5),
5052 WMI_AP_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6),
5053 WMI_AP_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7),
5054};
5055
5056/* U-APSD maximum service period of peer station */
5057enum wmi_ap_ps_peer_param_max_sp {
5058 WMI_AP_PS_PEER_PARAM_MAX_SP_UNLIMITED = 0,
5059 WMI_AP_PS_PEER_PARAM_MAX_SP_2 = 1,
5060 WMI_AP_PS_PEER_PARAM_MAX_SP_4 = 2,
5061 WMI_AP_PS_PEER_PARAM_MAX_SP_6 = 3,
5062 MAX_WMI_AP_PS_PEER_PARAM_MAX_SP,
5063};
5064
5065enum wmi_ap_ps_peer_param {
5066 /** Set uapsd configuration for a given peer.
5067 *
5068 * This include the delivery and trigger enabled state for each AC.
5069 * The host MLME needs to set this based on AP capability and stations
5070 * request Set in the association request received from the station.
5071 *
5072 * Lower 8 bits of the value specify the UAPSD configuration.
5073 *
5074 * (see enum wmi_ap_ps_param_uapsd)
5075 * The default value is 0.
5076 */
5077 WMI_AP_PS_PEER_PARAM_UAPSD = 0,
5078
5079 /**
5080 * Set the service period for a UAPSD capable station
5081 *
5082 * The service period from wme ie in the (re)assoc request frame.
5083 *
5084 * (see enum wmi_ap_ps_peer_param_max_sp)
5085 */
5086 WMI_AP_PS_PEER_PARAM_MAX_SP = 1,
5087
5088 /** Time in seconds for aging out buffered frames
5089 * for STA in power save
5090 */
5091 WMI_AP_PS_PEER_PARAM_AGEOUT_TIME = 2,
5092
5093 /** Specify frame types that are considered SIFS
5094 * RESP trigger frame
5095 */
5096 WMI_AP_PS_PEER_PARAM_SIFS_RESP_FRMTYPE = 3,
5097
5098 /** Specifies the trigger state of TID.
5099 * Valid only for UAPSD frame type
5100 */
5101 WMI_AP_PS_PEER_PARAM_SIFS_RESP_UAPSD = 4,
5102
5103 /* Specifies the WNM sleep state of a STA */
5104 WMI_AP_PS_PEER_PARAM_WNM_SLEEP = 5,
5105};
5106
5107#define DISABLE_SIFS_RESPONSE_TRIGGER 0
5108
5109#define WMI_MAX_KEY_INDEX 3
5110#define WMI_MAX_KEY_LEN 32
5111
5112#define WMI_KEY_PAIRWISE 0x00
5113#define WMI_KEY_GROUP 0x01
5114
5115#define WMI_CIPHER_NONE 0x0 /* clear key */
5116#define WMI_CIPHER_WEP 0x1
5117#define WMI_CIPHER_TKIP 0x2
5118#define WMI_CIPHER_AES_OCB 0x3
5119#define WMI_CIPHER_AES_CCM 0x4
5120#define WMI_CIPHER_WAPI 0x5
5121#define WMI_CIPHER_CKIP 0x6
5122#define WMI_CIPHER_AES_CMAC 0x7
5123#define WMI_CIPHER_ANY 0x8
5124#define WMI_CIPHER_AES_GCM 0x9
5125#define WMI_CIPHER_AES_GMAC 0xa
5126
5127/* Value to disable fixed rate setting */
5128#define WMI_FIXED_RATE_NONE (0xffff)
5129
5130#define ATH11K_RC_VERSION_OFFSET 28
5131#define ATH11K_RC_PREAMBLE_OFFSET 8
5132#define ATH11K_RC_NSS_OFFSET 5
5133
5134#define ATH11K_HW_RATE_CODE(rate, nss, preamble) \
5135 ((1 << ATH11K_RC_VERSION_OFFSET) | \
5136 ((nss) << ATH11K_RC_NSS_OFFSET) | \
5137 ((preamble) << ATH11K_RC_PREAMBLE_OFFSET) | \
5138 (rate))
5139
5140/* Preamble types to be used with VDEV fixed rate configuration */
5141enum wmi_rate_preamble {
5142 WMI_RATE_PREAMBLE_OFDM,
5143 WMI_RATE_PREAMBLE_CCK,
5144 WMI_RATE_PREAMBLE_HT,
5145 WMI_RATE_PREAMBLE_VHT,
5146 WMI_RATE_PREAMBLE_HE,
5147};
5148
5149/**
5150 * enum wmi_rtscts_prot_mode - Enable/Disable RTS/CTS and CTS2Self Protection.
5151 * @WMI_RTS_CTS_DISABLED: RTS/CTS protection is disabled.
5152 * @WMI_USE_RTS_CTS: RTS/CTS Enabled.
5153 * @WMI_USE_CTS2SELF: CTS to self protection Enabled.
5154 */
5155enum wmi_rtscts_prot_mode {
5156 WMI_RTS_CTS_DISABLED = 0,
5157 WMI_USE_RTS_CTS = 1,
5158 WMI_USE_CTS2SELF = 2,
5159};
5160
5161/**
5162 * enum wmi_rtscts_profile - Selection of RTS CTS profile along with enabling
5163 * protection mode.
5164 * @WMI_RTSCTS_FOR_NO_RATESERIES: Neither of rate-series should use RTS-CTS
5165 * @WMI_RTSCTS_FOR_SECOND_RATESERIES: Only second rate-series will use RTS-CTS
5166 * @WMI_RTSCTS_ACROSS_SW_RETRIES: Only the second rate-series will use RTS-CTS,
5167 * but if there's a sw retry, both the rate
5168 * series will use RTS-CTS.
5169 * @WMI_RTSCTS_ERP: RTS/CTS used for ERP protection for every PPDU.
5170 * @WMI_RTSCTS_FOR_ALL_RATESERIES: Enable RTS-CTS for all rate series.
5171 */
5172enum wmi_rtscts_profile {
5173 WMI_RTSCTS_FOR_NO_RATESERIES = 0,
5174 WMI_RTSCTS_FOR_SECOND_RATESERIES = 1,
5175 WMI_RTSCTS_ACROSS_SW_RETRIES = 2,
5176 WMI_RTSCTS_ERP = 3,
5177 WMI_RTSCTS_FOR_ALL_RATESERIES = 4,
5178};
5179
5180struct ath11k_hal_reg_cap {
5181 u32 eeprom_rd;
5182 u32 eeprom_rd_ext;
5183 u32 regcap1;
5184 u32 regcap2;
5185 u32 wireless_modes;
5186 u32 low_2ghz_chan;
5187 u32 high_2ghz_chan;
5188 u32 low_5ghz_chan;
5189 u32 high_5ghz_chan;
5190};
5191
5192struct ath11k_mem_chunk {
5193 void *vaddr;
5194 dma_addr_t paddr;
5195 u32 len;
5196 u32 req_id;
5197};
5198
5199#define WMI_SKB_HEADROOM sizeof(struct wmi_cmd_hdr)
5200
5201enum wmi_sta_ps_param_rx_wake_policy {
5202 WMI_STA_PS_RX_WAKE_POLICY_WAKE = 0,
5203 WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD = 1,
5204};
5205
5206/* Do not change existing values! Used by ath11k_frame_mode parameter
5207 * module parameter.
5208 */
5209enum ath11k_hw_txrx_mode {
5210 ATH11K_HW_TXRX_RAW = 0,
5211 ATH11K_HW_TXRX_NATIVE_WIFI = 1,
5212 ATH11K_HW_TXRX_ETHERNET = 2,
5213};
5214
5215struct wmi_wmm_params {
5216 u32 tlv_header;
5217 u32 cwmin;
5218 u32 cwmax;
5219 u32 aifs;
5220 u32 txoplimit;
5221 u32 acm;
5222 u32 no_ack;
5223} __packed;
5224
5225struct wmi_wmm_params_arg {
5226 u8 acm;
5227 u8 aifs;
5228 u16 cwmin;
5229 u16 cwmax;
5230 u16 txop;
5231 u8 no_ack;
5232};
5233
5234struct wmi_vdev_set_wmm_params_cmd {
5235 u32 tlv_header;
5236 u32 vdev_id;
5237 struct wmi_wmm_params wmm_params[4];
5238 u32 wmm_param_type;
5239} __packed;
5240
5241struct wmi_wmm_params_all_arg {
5242 struct wmi_wmm_params_arg ac_be;
5243 struct wmi_wmm_params_arg ac_bk;
5244 struct wmi_wmm_params_arg ac_vi;
5245 struct wmi_wmm_params_arg ac_vo;
5246};
5247
5248#define ATH11K_TWT_DEF_STA_CONG_TIMER_MS 5000
5249#define ATH11K_TWT_DEF_DEFAULT_SLOT_SIZE 10
5250#define ATH11K_TWT_DEF_CONGESTION_THRESH_SETUP 50
5251#define ATH11K_TWT_DEF_CONGESTION_THRESH_TEARDOWN 20
5252#define ATH11K_TWT_DEF_CONGESTION_THRESH_CRITICAL 100
5253#define ATH11K_TWT_DEF_INTERFERENCE_THRESH_TEARDOWN 80
5254#define ATH11K_TWT_DEF_INTERFERENCE_THRESH_SETUP 50
5255#define ATH11K_TWT_DEF_MIN_NO_STA_SETUP 10
5256#define ATH11K_TWT_DEF_MIN_NO_STA_TEARDOWN 2
5257#define ATH11K_TWT_DEF_NO_OF_BCAST_MCAST_SLOTS 2
5258#define ATH11K_TWT_DEF_MIN_NO_TWT_SLOTS 2
5259#define ATH11K_TWT_DEF_MAX_NO_STA_TWT 500
5260#define ATH11K_TWT_DEF_MODE_CHECK_INTERVAL 10000
5261#define ATH11K_TWT_DEF_ADD_STA_SLOT_INTERVAL 1000
5262#define ATH11K_TWT_DEF_REMOVE_STA_SLOT_INTERVAL 5000
5263
5264struct wmi_twt_enable_params {
5265 u32 sta_cong_timer_ms;
5266 u32 mbss_support;
5267 u32 default_slot_size;
5268 u32 congestion_thresh_setup;
5269 u32 congestion_thresh_teardown;
5270 u32 congestion_thresh_critical;
5271 u32 interference_thresh_teardown;
5272 u32 interference_thresh_setup;
5273 u32 min_no_sta_setup;
5274 u32 min_no_sta_teardown;
5275 u32 no_of_bcast_mcast_slots;
5276 u32 min_no_twt_slots;
5277 u32 max_no_sta_twt;
5278 u32 mode_check_interval;
5279 u32 add_sta_slot_interval;
5280 u32 remove_sta_slot_interval;
5281};
5282
5283struct wmi_twt_enable_params_cmd {
5284 u32 tlv_header;
5285 u32 pdev_id;
5286 u32 sta_cong_timer_ms;
5287 u32 mbss_support;
5288 u32 default_slot_size;
5289 u32 congestion_thresh_setup;
5290 u32 congestion_thresh_teardown;
5291 u32 congestion_thresh_critical;
5292 u32 interference_thresh_teardown;
5293 u32 interference_thresh_setup;
5294 u32 min_no_sta_setup;
5295 u32 min_no_sta_teardown;
5296 u32 no_of_bcast_mcast_slots;
5297 u32 min_no_twt_slots;
5298 u32 max_no_sta_twt;
5299 u32 mode_check_interval;
5300 u32 add_sta_slot_interval;
5301 u32 remove_sta_slot_interval;
5302} __packed;
5303
5304struct wmi_twt_disable_params_cmd {
5305 u32 tlv_header;
5306 u32 pdev_id;
5307} __packed;
5308
5309enum WMI_HOST_TWT_COMMAND {
5310 WMI_HOST_TWT_COMMAND_REQUEST_TWT = 0,
5311 WMI_HOST_TWT_COMMAND_SUGGEST_TWT,
5312 WMI_HOST_TWT_COMMAND_DEMAND_TWT,
5313 WMI_HOST_TWT_COMMAND_TWT_GROUPING,
5314 WMI_HOST_TWT_COMMAND_ACCEPT_TWT,
5315 WMI_HOST_TWT_COMMAND_ALTERNATE_TWT,
5316 WMI_HOST_TWT_COMMAND_DICTATE_TWT,
5317 WMI_HOST_TWT_COMMAND_REJECT_TWT,
5318};
5319
5320#define WMI_TWT_ADD_DIALOG_FLAG_BCAST BIT(8)
5321#define WMI_TWT_ADD_DIALOG_FLAG_TRIGGER BIT(9)
5322#define WMI_TWT_ADD_DIALOG_FLAG_FLOW_TYPE BIT(10)
5323#define WMI_TWT_ADD_DIALOG_FLAG_PROTECTION BIT(11)
5324
5325struct wmi_twt_add_dialog_params_cmd {
5326 u32 tlv_header;
5327 u32 vdev_id;
5328 struct wmi_mac_addr peer_macaddr;
5329 u32 dialog_id;
5330 u32 wake_intvl_us;
5331 u32 wake_intvl_mantis;
5332 u32 wake_dura_us;
5333 u32 sp_offset_us;
5334 u32 flags;
5335} __packed;
5336
5337struct wmi_twt_add_dialog_params {
5338 u32 vdev_id;
5339 u8 peer_macaddr[ETH_ALEN];
5340 u32 dialog_id;
5341 u32 wake_intvl_us;
5342 u32 wake_intvl_mantis;
5343 u32 wake_dura_us;
5344 u32 sp_offset_us;
5345 u8 twt_cmd;
5346 u8 flag_bcast;
5347 u8 flag_trigger;
5348 u8 flag_flow_type;
5349 u8 flag_protection;
5350} __packed;
5351
5352enum wmi_twt_add_dialog_status {
5353 WMI_ADD_TWT_STATUS_OK,
5354 WMI_ADD_TWT_STATUS_TWT_NOT_ENABLED,
5355 WMI_ADD_TWT_STATUS_USED_DIALOG_ID,
5356 WMI_ADD_TWT_STATUS_INVALID_PARAM,
5357 WMI_ADD_TWT_STATUS_NOT_READY,
5358 WMI_ADD_TWT_STATUS_NO_RESOURCE,
5359 WMI_ADD_TWT_STATUS_NO_ACK,
5360 WMI_ADD_TWT_STATUS_NO_RESPONSE,
5361 WMI_ADD_TWT_STATUS_DENIED,
5362 WMI_ADD_TWT_STATUS_UNKNOWN_ERROR,
5363};
5364
5365struct wmi_twt_add_dialog_event {
5366 u32 vdev_id;
5367 struct wmi_mac_addr peer_macaddr;
5368 u32 dialog_id;
5369 u32 status;
5370} __packed;
5371
5372struct wmi_twt_del_dialog_params {
5373 u32 vdev_id;
5374 u8 peer_macaddr[ETH_ALEN];
5375 u32 dialog_id;
5376} __packed;
5377
5378struct wmi_twt_del_dialog_params_cmd {
5379 u32 tlv_header;
5380 u32 vdev_id;
5381 struct wmi_mac_addr peer_macaddr;
5382 u32 dialog_id;
5383} __packed;
5384
5385struct wmi_twt_pause_dialog_params {
5386 u32 vdev_id;
5387 u8 peer_macaddr[ETH_ALEN];
5388 u32 dialog_id;
5389} __packed;
5390
5391struct wmi_twt_pause_dialog_params_cmd {
5392 u32 tlv_header;
5393 u32 vdev_id;
5394 struct wmi_mac_addr peer_macaddr;
5395 u32 dialog_id;
5396} __packed;
5397
5398struct wmi_twt_resume_dialog_params {
5399 u32 vdev_id;
5400 u8 peer_macaddr[ETH_ALEN];
5401 u32 dialog_id;
5402 u32 sp_offset_us;
5403 u32 next_twt_size;
5404} __packed;
5405
5406struct wmi_twt_resume_dialog_params_cmd {
5407 u32 tlv_header;
5408 u32 vdev_id;
5409 struct wmi_mac_addr peer_macaddr;
5410 u32 dialog_id;
5411 u32 sp_offset_us;
5412 u32 next_twt_size;
5413} __packed;
5414
5415struct wmi_obss_spatial_reuse_params_cmd {
5416 u32 tlv_header;
5417 u32 pdev_id;
5418 u32 enable;
5419 s32 obss_min;
5420 s32 obss_max;
5421 u32 vdev_id;
5422} __packed;
5423
5424struct wmi_pdev_obss_pd_bitmap_cmd {
5425 u32 tlv_header;
5426 u32 pdev_id;
5427 u32 bitmap[2];
5428} __packed;
5429
5430#define ATH11K_BSS_COLOR_COLLISION_SCAN_PERIOD_MS 200
5431#define ATH11K_OBSS_COLOR_COLLISION_DETECTION_DISABLE 0
5432#define ATH11K_OBSS_COLOR_COLLISION_DETECTION 1
5433
5434#define ATH11K_BSS_COLOR_COLLISION_DETECTION_STA_PERIOD_MS 10000
5435#define ATH11K_BSS_COLOR_COLLISION_DETECTION_AP_PERIOD_MS 5000
5436
5437enum wmi_bss_color_collision {
5438 WMI_BSS_COLOR_COLLISION_DISABLE = 0,
5439 WMI_BSS_COLOR_COLLISION_DETECTION,
5440 WMI_BSS_COLOR_FREE_SLOT_TIMER_EXPIRY,
5441 WMI_BSS_COLOR_FREE_SLOT_AVAILABLE,
5442};
5443
5444struct wmi_obss_color_collision_cfg_params_cmd {
5445 u32 tlv_header;
5446 u32 vdev_id;
5447 u32 flags;
5448 u32 evt_type;
5449 u32 current_bss_color;
5450 u32 detection_period_ms;
5451 u32 scan_period_ms;
5452 u32 free_slot_expiry_time_ms;
5453} __packed;
5454
5455struct wmi_bss_color_change_enable_params_cmd {
5456 u32 tlv_header;
5457 u32 vdev_id;
5458 u32 enable;
5459} __packed;
5460
5461struct wmi_obss_color_collision_event {
5462 u32 vdev_id;
5463 u32 evt_type;
5464 u64 obss_color_bitmap;
5465} __packed;
5466
5467#define ATH11K_IPV4_TH_SEED_SIZE 5
5468#define ATH11K_IPV6_TH_SEED_SIZE 11
5469
5470struct ath11k_wmi_pdev_lro_config_cmd {
5471 u32 tlv_header;
5472 u32 lro_enable;
5473 u32 res;
5474 u32 th_4[ATH11K_IPV4_TH_SEED_SIZE];
5475 u32 th_6[ATH11K_IPV6_TH_SEED_SIZE];
5476 u32 pdev_id;
5477} __packed;
5478
5479#define ATH11K_WMI_SPECTRAL_COUNT_DEFAULT 0
5480#define ATH11K_WMI_SPECTRAL_PERIOD_DEFAULT 224
5481#define ATH11K_WMI_SPECTRAL_PRIORITY_DEFAULT 1
5482#define ATH11K_WMI_SPECTRAL_FFT_SIZE_DEFAULT 7
5483#define ATH11K_WMI_SPECTRAL_GC_ENA_DEFAULT 1
5484#define ATH11K_WMI_SPECTRAL_RESTART_ENA_DEFAULT 0
5485#define ATH11K_WMI_SPECTRAL_NOISE_FLOOR_REF_DEFAULT -96
5486#define ATH11K_WMI_SPECTRAL_INIT_DELAY_DEFAULT 80
5487#define ATH11K_WMI_SPECTRAL_NB_TONE_THR_DEFAULT 12
5488#define ATH11K_WMI_SPECTRAL_STR_BIN_THR_DEFAULT 8
5489#define ATH11K_WMI_SPECTRAL_WB_RPT_MODE_DEFAULT 0
5490#define ATH11K_WMI_SPECTRAL_RSSI_RPT_MODE_DEFAULT 0
5491#define ATH11K_WMI_SPECTRAL_RSSI_THR_DEFAULT 0xf0
5492#define ATH11K_WMI_SPECTRAL_PWR_FORMAT_DEFAULT 0
5493#define ATH11K_WMI_SPECTRAL_RPT_MODE_DEFAULT 2
5494#define ATH11K_WMI_SPECTRAL_BIN_SCALE_DEFAULT 1
5495#define ATH11K_WMI_SPECTRAL_DBM_ADJ_DEFAULT 1
5496#define ATH11K_WMI_SPECTRAL_CHN_MASK_DEFAULT 1
5497
5498struct ath11k_wmi_vdev_spectral_conf_param {
5499 u32 vdev_id;
5500 u32 scan_count;
5501 u32 scan_period;
5502 u32 scan_priority;
5503 u32 scan_fft_size;
5504 u32 scan_gc_ena;
5505 u32 scan_restart_ena;
5506 u32 scan_noise_floor_ref;
5507 u32 scan_init_delay;
5508 u32 scan_nb_tone_thr;
5509 u32 scan_str_bin_thr;
5510 u32 scan_wb_rpt_mode;
5511 u32 scan_rssi_rpt_mode;
5512 u32 scan_rssi_thr;
5513 u32 scan_pwr_format;
5514 u32 scan_rpt_mode;
5515 u32 scan_bin_scale;
5516 u32 scan_dbm_adj;
5517 u32 scan_chn_mask;
5518} __packed;
5519
5520struct ath11k_wmi_vdev_spectral_conf_cmd {
5521 u32 tlv_header;
5522 struct ath11k_wmi_vdev_spectral_conf_param param;
5523} __packed;
5524
5525#define ATH11K_WMI_SPECTRAL_TRIGGER_CMD_TRIGGER 1
5526#define ATH11K_WMI_SPECTRAL_TRIGGER_CMD_CLEAR 2
5527#define ATH11K_WMI_SPECTRAL_ENABLE_CMD_ENABLE 1
5528#define ATH11K_WMI_SPECTRAL_ENABLE_CMD_DISABLE 2
5529
5530struct ath11k_wmi_vdev_spectral_enable_cmd {
5531 u32 tlv_header;
5532 u32 vdev_id;
5533 u32 trigger_cmd;
5534 u32 enable_cmd;
5535} __packed;
5536
5537struct ath11k_wmi_pdev_dma_ring_cfg_req_cmd {
5538 u32 tlv_header;
5539 u32 pdev_id;
5540 u32 module_id; /* see enum wmi_direct_buffer_module */
5541 u32 base_paddr_lo;
5542 u32 base_paddr_hi;
5543 u32 head_idx_paddr_lo;
5544 u32 head_idx_paddr_hi;
5545 u32 tail_idx_paddr_lo;
5546 u32 tail_idx_paddr_hi;
5547 u32 num_elems; /* Number of elems in the ring */
5548 u32 buf_size; /* size of allocated buffer in bytes */
5549
5550 /* Number of wmi_dma_buf_release_entry packed together */
5551 u32 num_resp_per_event;
5552
5553 /* Target should timeout and send whatever resp
5554 * it has if this time expires, units in milliseconds
5555 */
5556 u32 event_timeout_ms;
5557} __packed;
5558
5559struct ath11k_wmi_dma_buf_release_fixed_param {
5560 u32 pdev_id;
5561 u32 module_id;
5562 u32 num_buf_release_entry;
5563 u32 num_meta_data_entry;
5564} __packed;
5565
5566struct wmi_dma_buf_release_entry {
5567 u32 tlv_header;
5568 u32 paddr_lo;
5569
5570 /* Bits 11:0: address of data
5571 * Bits 31:12: host context data
5572 */
5573 u32 paddr_hi;
5574} __packed;
5575
5576#define WMI_SPECTRAL_META_INFO1_FREQ1 GENMASK(15, 0)
5577#define WMI_SPECTRAL_META_INFO1_FREQ2 GENMASK(31, 16)
5578
5579#define WMI_SPECTRAL_META_INFO2_CHN_WIDTH GENMASK(7, 0)
5580
5581struct wmi_dma_buf_release_meta_data {
5582 u32 tlv_header;
5583 s32 noise_floor[WMI_MAX_CHAINS];
5584 u32 reset_delay;
5585 u32 freq1;
5586 u32 freq2;
5587 u32 ch_width;
5588} __packed;
5589
5590enum wmi_fils_discovery_cmd_type {
5591 WMI_FILS_DISCOVERY_CMD,
5592 WMI_UNSOL_BCAST_PROBE_RESP,
5593};
5594
5595struct wmi_fils_discovery_cmd {
5596 u32 tlv_header;
5597 u32 vdev_id;
5598 u32 interval;
5599 u32 config; /* enum wmi_fils_discovery_cmd_type */
5600} __packed;
5601
5602struct wmi_fils_discovery_tmpl_cmd {
5603 u32 tlv_header;
5604 u32 vdev_id;
5605 u32 buf_len;
5606} __packed;
5607
5608struct wmi_probe_tmpl_cmd {
5609 u32 tlv_header;
5610 u32 vdev_id;
5611 u32 buf_len;
5612} __packed;
5613
5614struct target_resource_config {
5615 u32 num_vdevs;
5616 u32 num_peers;
5617 u32 num_active_peers;
5618 u32 num_offload_peers;
5619 u32 num_offload_reorder_buffs;
5620 u32 num_peer_keys;
5621 u32 num_tids;
5622 u32 ast_skid_limit;
5623 u32 tx_chain_mask;
5624 u32 rx_chain_mask;
5625 u32 rx_timeout_pri[4];
5626 u32 rx_decap_mode;
5627 u32 scan_max_pending_req;
5628 u32 bmiss_offload_max_vdev;
5629 u32 roam_offload_max_vdev;
5630 u32 roam_offload_max_ap_profiles;
5631 u32 num_mcast_groups;
5632 u32 num_mcast_table_elems;
5633 u32 mcast2ucast_mode;
5634 u32 tx_dbg_log_size;
5635 u32 num_wds_entries;
5636 u32 dma_burst_size;
5637 u32 mac_aggr_delim;
5638 u32 rx_skip_defrag_timeout_dup_detection_check;
5639 u32 vow_config;
5640 u32 gtk_offload_max_vdev;
5641 u32 num_msdu_desc;
5642 u32 max_frag_entries;
5643 u32 max_peer_ext_stats;
5644 u32 smart_ant_cap;
5645 u32 bk_minfree;
5646 u32 be_minfree;
5647 u32 vi_minfree;
5648 u32 vo_minfree;
5649 u32 rx_batchmode;
5650 u32 tt_support;
5651 u32 flag1;
5652 u32 iphdr_pad_config;
5653 u32 qwrap_config:16,
5654 alloc_frag_desc_for_data_pkt:16;
5655 u32 num_tdls_vdevs;
5656 u32 num_tdls_conn_table_entries;
5657 u32 beacon_tx_offload_max_vdev;
5658 u32 num_multicast_filter_entries;
5659 u32 num_wow_filters;
5660 u32 num_keep_alive_pattern;
5661 u32 keep_alive_pattern_size;
5662 u32 max_tdls_concurrent_sleep_sta;
5663 u32 max_tdls_concurrent_buffer_sta;
5664 u32 wmi_send_separate;
5665 u32 num_ocb_vdevs;
5666 u32 num_ocb_channels;
5667 u32 num_ocb_schedules;
5668 u32 num_ns_ext_tuples_cfg;
5669 u32 bpf_instruction_size;
5670 u32 max_bssid_rx_filters;
5671 u32 use_pdev_id;
5672 u32 peer_map_unmap_v2_support;
5673 u32 sched_params;
5674 u32 twt_ap_pdev_count;
5675 u32 twt_ap_sta_count;
5676 u8 is_reg_cc_ext_event_supported;
5677 u32 ema_max_vap_cnt;
5678 u32 ema_max_profile_period;
5679};
5680
5681enum wmi_debug_log_param {
5682 WMI_DEBUG_LOG_PARAM_LOG_LEVEL = 0x1,
5683 WMI_DEBUG_LOG_PARAM_VDEV_ENABLE,
5684 WMI_DEBUG_LOG_PARAM_VDEV_DISABLE,
5685 WMI_DEBUG_LOG_PARAM_VDEV_ENABLE_BITMAP,
5686 WMI_DEBUG_LOG_PARAM_MOD_ENABLE_BITMAP,
5687 WMI_DEBUG_LOG_PARAM_WOW_MOD_ENABLE_BITMAP,
5688};
5689
5690struct wmi_debug_log_config_cmd_fixed_param {
5691 u32 tlv_header;
5692 u32 dbg_log_param;
5693 u32 value;
5694} __packed;
5695
5696#define WMI_MAX_MEM_REQS 32
5697
5698#define MAX_RADIOS 3
5699
5700#define WMI_SERVICE_READY_TIMEOUT_HZ (5 * HZ)
5701#define WMI_SEND_TIMEOUT_HZ (3 * HZ)
5702
5703enum ath11k_wmi_peer_ps_state {
5704 WMI_PEER_PS_STATE_OFF,
5705 WMI_PEER_PS_STATE_ON,
5706 WMI_PEER_PS_STATE_DISABLED,
5707};
5708
5709enum wmi_peer_ps_supported_bitmap {
5710 /* Used to indicate that power save state change is valid */
5711 WMI_PEER_PS_VALID = 0x1,
5712 WMI_PEER_PS_STATE_TIMESTAMP = 0x2,
5713};
5714
5715struct wmi_peer_sta_ps_state_chg_event {
5716 struct wmi_mac_addr peer_macaddr;
5717 u32 peer_ps_state;
5718 u32 ps_supported_bitmap;
5719 u32 peer_ps_valid;
5720 u32 peer_ps_timestamp;
5721} __packed;
5722
5723struct ath11k_wmi_base {
5724 struct ath11k_base *ab;
5725 struct ath11k_pdev_wmi wmi[MAX_RADIOS];
5726 enum ath11k_htc_ep_id wmi_endpoint_id[MAX_RADIOS];
5727 u32 max_msg_len[MAX_RADIOS];
5728
5729 struct completion service_ready;
5730 struct completion unified_ready;
5731 DECLARE_BITMAP(svc_map, WMI_MAX_EXT2_SERVICE);
5732 wait_queue_head_t tx_credits_wq;
5733 u32 num_mem_chunks;
5734 u32 rx_decap_mode;
5735 struct wmi_host_mem_chunk mem_chunks[WMI_MAX_MEM_REQS];
5736
5737 enum wmi_host_hw_mode_config_type preferred_hw_mode;
5738 struct target_resource_config wlan_resource_config;
5739
5740 struct ath11k_targ_cap *targ_cap;
5741};
5742
5743/* Definition of HW data filtering */
5744enum hw_data_filter_type {
5745 WMI_HW_DATA_FILTER_DROP_NON_ARP_BC = BIT(0),
5746 WMI_HW_DATA_FILTER_DROP_NON_ICMPV6_MC = BIT(1),
5747};
5748
5749struct wmi_hw_data_filter_cmd {
5750 u32 tlv_header;
5751 u32 vdev_id;
5752 u32 enable;
5753 u32 hw_filter_bitmap;
5754} __packed;
5755
5756/* WOW structures */
5757enum wmi_wow_wakeup_event {
5758 WOW_BMISS_EVENT = 0,
5759 WOW_BETTER_AP_EVENT,
5760 WOW_DEAUTH_RECVD_EVENT,
5761 WOW_MAGIC_PKT_RECVD_EVENT,
5762 WOW_GTK_ERR_EVENT,
5763 WOW_FOURWAY_HSHAKE_EVENT,
5764 WOW_EAPOL_RECVD_EVENT,
5765 WOW_NLO_DETECTED_EVENT,
5766 WOW_DISASSOC_RECVD_EVENT,
5767 WOW_PATTERN_MATCH_EVENT,
5768 WOW_CSA_IE_EVENT,
5769 WOW_PROBE_REQ_WPS_IE_EVENT,
5770 WOW_AUTH_REQ_EVENT,
5771 WOW_ASSOC_REQ_EVENT,
5772 WOW_HTT_EVENT,
5773 WOW_RA_MATCH_EVENT,
5774 WOW_HOST_AUTO_SHUTDOWN_EVENT,
5775 WOW_IOAC_MAGIC_EVENT,
5776 WOW_IOAC_SHORT_EVENT,
5777 WOW_IOAC_EXTEND_EVENT,
5778 WOW_IOAC_TIMER_EVENT,
5779 WOW_DFS_PHYERR_RADAR_EVENT,
5780 WOW_BEACON_EVENT,
5781 WOW_CLIENT_KICKOUT_EVENT,
5782 WOW_EVENT_MAX,
5783};
5784
5785enum wmi_wow_interface_cfg {
5786 WOW_IFACE_PAUSE_ENABLED,
5787 WOW_IFACE_PAUSE_DISABLED
5788};
5789
5790#define C2S(x) case x: return #x
5791
5792static inline const char *wow_wakeup_event(enum wmi_wow_wakeup_event ev)
5793{
5794 switch (ev) {
5795 C2S(WOW_BMISS_EVENT);
5796 C2S(WOW_BETTER_AP_EVENT);
5797 C2S(WOW_DEAUTH_RECVD_EVENT);
5798 C2S(WOW_MAGIC_PKT_RECVD_EVENT);
5799 C2S(WOW_GTK_ERR_EVENT);
5800 C2S(WOW_FOURWAY_HSHAKE_EVENT);
5801 C2S(WOW_EAPOL_RECVD_EVENT);
5802 C2S(WOW_NLO_DETECTED_EVENT);
5803 C2S(WOW_DISASSOC_RECVD_EVENT);
5804 C2S(WOW_PATTERN_MATCH_EVENT);
5805 C2S(WOW_CSA_IE_EVENT);
5806 C2S(WOW_PROBE_REQ_WPS_IE_EVENT);
5807 C2S(WOW_AUTH_REQ_EVENT);
5808 C2S(WOW_ASSOC_REQ_EVENT);
5809 C2S(WOW_HTT_EVENT);
5810 C2S(WOW_RA_MATCH_EVENT);
5811 C2S(WOW_HOST_AUTO_SHUTDOWN_EVENT);
5812 C2S(WOW_IOAC_MAGIC_EVENT);
5813 C2S(WOW_IOAC_SHORT_EVENT);
5814 C2S(WOW_IOAC_EXTEND_EVENT);
5815 C2S(WOW_IOAC_TIMER_EVENT);
5816 C2S(WOW_DFS_PHYERR_RADAR_EVENT);
5817 C2S(WOW_BEACON_EVENT);
5818 C2S(WOW_CLIENT_KICKOUT_EVENT);
5819 C2S(WOW_EVENT_MAX);
5820 default:
5821 return NULL;
5822 }
5823}
5824
5825enum wmi_wow_wake_reason {
5826 WOW_REASON_UNSPECIFIED = -1,
5827 WOW_REASON_NLOD = 0,
5828 WOW_REASON_AP_ASSOC_LOST,
5829 WOW_REASON_LOW_RSSI,
5830 WOW_REASON_DEAUTH_RECVD,
5831 WOW_REASON_DISASSOC_RECVD,
5832 WOW_REASON_GTK_HS_ERR,
5833 WOW_REASON_EAP_REQ,
5834 WOW_REASON_FOURWAY_HS_RECV,
5835 WOW_REASON_TIMER_INTR_RECV,
5836 WOW_REASON_PATTERN_MATCH_FOUND,
5837 WOW_REASON_RECV_MAGIC_PATTERN,
5838 WOW_REASON_P2P_DISC,
5839 WOW_REASON_WLAN_HB,
5840 WOW_REASON_CSA_EVENT,
5841 WOW_REASON_PROBE_REQ_WPS_IE_RECV,
5842 WOW_REASON_AUTH_REQ_RECV,
5843 WOW_REASON_ASSOC_REQ_RECV,
5844 WOW_REASON_HTT_EVENT,
5845 WOW_REASON_RA_MATCH,
5846 WOW_REASON_HOST_AUTO_SHUTDOWN,
5847 WOW_REASON_IOAC_MAGIC_EVENT,
5848 WOW_REASON_IOAC_SHORT_EVENT,
5849 WOW_REASON_IOAC_EXTEND_EVENT,
5850 WOW_REASON_IOAC_TIMER_EVENT,
5851 WOW_REASON_ROAM_HO,
5852 WOW_REASON_DFS_PHYERR_RADADR_EVENT,
5853 WOW_REASON_BEACON_RECV,
5854 WOW_REASON_CLIENT_KICKOUT_EVENT,
5855 WOW_REASON_PAGE_FAULT = 0x3a,
5856 WOW_REASON_DEBUG_TEST = 0xFF,
5857};
5858
5859static inline const char *wow_reason(enum wmi_wow_wake_reason reason)
5860{
5861 switch (reason) {
5862 C2S(WOW_REASON_UNSPECIFIED);
5863 C2S(WOW_REASON_NLOD);
5864 C2S(WOW_REASON_AP_ASSOC_LOST);
5865 C2S(WOW_REASON_LOW_RSSI);
5866 C2S(WOW_REASON_DEAUTH_RECVD);
5867 C2S(WOW_REASON_DISASSOC_RECVD);
5868 C2S(WOW_REASON_GTK_HS_ERR);
5869 C2S(WOW_REASON_EAP_REQ);
5870 C2S(WOW_REASON_FOURWAY_HS_RECV);
5871 C2S(WOW_REASON_TIMER_INTR_RECV);
5872 C2S(WOW_REASON_PATTERN_MATCH_FOUND);
5873 C2S(WOW_REASON_RECV_MAGIC_PATTERN);
5874 C2S(WOW_REASON_P2P_DISC);
5875 C2S(WOW_REASON_WLAN_HB);
5876 C2S(WOW_REASON_CSA_EVENT);
5877 C2S(WOW_REASON_PROBE_REQ_WPS_IE_RECV);
5878 C2S(WOW_REASON_AUTH_REQ_RECV);
5879 C2S(WOW_REASON_ASSOC_REQ_RECV);
5880 C2S(WOW_REASON_HTT_EVENT);
5881 C2S(WOW_REASON_RA_MATCH);
5882 C2S(WOW_REASON_HOST_AUTO_SHUTDOWN);
5883 C2S(WOW_REASON_IOAC_MAGIC_EVENT);
5884 C2S(WOW_REASON_IOAC_SHORT_EVENT);
5885 C2S(WOW_REASON_IOAC_EXTEND_EVENT);
5886 C2S(WOW_REASON_IOAC_TIMER_EVENT);
5887 C2S(WOW_REASON_ROAM_HO);
5888 C2S(WOW_REASON_DFS_PHYERR_RADADR_EVENT);
5889 C2S(WOW_REASON_BEACON_RECV);
5890 C2S(WOW_REASON_CLIENT_KICKOUT_EVENT);
5891 C2S(WOW_REASON_PAGE_FAULT);
5892 C2S(WOW_REASON_DEBUG_TEST);
5893 default:
5894 return NULL;
5895 }
5896}
5897
5898#undef C2S
5899
5900struct wmi_wow_ev_arg {
5901 u32 vdev_id;
5902 u32 flag;
5903 enum wmi_wow_wake_reason wake_reason;
5904 u32 data_len;
5905};
5906
5907enum wmi_tlv_pattern_type {
5908 WOW_PATTERN_MIN = 0,
5909 WOW_BITMAP_PATTERN = WOW_PATTERN_MIN,
5910 WOW_IPV4_SYNC_PATTERN,
5911 WOW_IPV6_SYNC_PATTERN,
5912 WOW_WILD_CARD_PATTERN,
5913 WOW_TIMER_PATTERN,
5914 WOW_MAGIC_PATTERN,
5915 WOW_IPV6_RA_PATTERN,
5916 WOW_IOAC_PKT_PATTERN,
5917 WOW_IOAC_TMR_PATTERN,
5918 WOW_PATTERN_MAX
5919};
5920
5921#define WOW_DEFAULT_BITMAP_PATTERN_SIZE 148
5922#define WOW_DEFAULT_BITMASK_SIZE 148
5923
5924#define WOW_MIN_PATTERN_SIZE 1
5925#define WOW_MAX_PATTERN_SIZE 148
5926#define WOW_MAX_PKT_OFFSET 128
5927#define WOW_HDR_LEN (sizeof(struct ieee80211_hdr_3addr) + \
5928 sizeof(struct rfc1042_hdr))
5929#define WOW_MAX_REDUCE (WOW_HDR_LEN - sizeof(struct ethhdr) - \
5930 offsetof(struct ieee80211_hdr_3addr, addr1))
5931
5932struct wmi_wow_add_del_event_cmd {
5933 u32 tlv_header;
5934 u32 vdev_id;
5935 u32 is_add;
5936 u32 event_bitmap;
5937} __packed;
5938
5939struct wmi_wow_enable_cmd {
5940 u32 tlv_header;
5941 u32 enable;
5942 u32 pause_iface_config;
5943 u32 flags;
5944} __packed;
5945
5946struct wmi_wow_host_wakeup_ind {
5947 u32 tlv_header;
5948 u32 reserved;
5949} __packed;
5950
5951struct wmi_tlv_wow_event_info {
5952 u32 vdev_id;
5953 u32 flag;
5954 u32 wake_reason;
5955 u32 data_len;
5956} __packed;
5957
5958struct wmi_wow_bitmap_pattern {
5959 u32 tlv_header;
5960 u8 patternbuf[WOW_DEFAULT_BITMAP_PATTERN_SIZE];
5961 u8 bitmaskbuf[WOW_DEFAULT_BITMASK_SIZE];
5962 u32 pattern_offset;
5963 u32 pattern_len;
5964 u32 bitmask_len;
5965 u32 pattern_id;
5966} __packed;
5967
5968struct wmi_wow_add_pattern_cmd {
5969 u32 tlv_header;
5970 u32 vdev_id;
5971 u32 pattern_id;
5972 u32 pattern_type;
5973} __packed;
5974
5975struct wmi_wow_del_pattern_cmd {
5976 u32 tlv_header;
5977 u32 vdev_id;
5978 u32 pattern_id;
5979 u32 pattern_type;
5980} __packed;
5981
5982#define WMI_PNO_MAX_SCHED_SCAN_PLANS 2
5983#define WMI_PNO_MAX_SCHED_SCAN_PLAN_INT 7200
5984#define WMI_PNO_MAX_SCHED_SCAN_PLAN_ITRNS 100
5985#define WMI_PNO_MAX_NETW_CHANNELS 26
5986#define WMI_PNO_MAX_NETW_CHANNELS_EX 60
5987#define WMI_PNO_MAX_SUPP_NETWORKS WLAN_SCAN_PARAMS_MAX_SSID
5988#define WMI_PNO_MAX_IE_LENGTH WLAN_SCAN_PARAMS_MAX_IE_LEN
5989
5990/* size based of dot11 declaration without extra IEs as we will not carry those for PNO */
5991#define WMI_PNO_MAX_PB_REQ_SIZE 450
5992
5993#define WMI_PNO_24G_DEFAULT_CH 1
5994#define WMI_PNO_5G_DEFAULT_CH 36
5995
5996#define WMI_ACTIVE_MAX_CHANNEL_TIME 40
5997#define WMI_PASSIVE_MAX_CHANNEL_TIME 110
5998
5999/* SSID broadcast type */
6000enum wmi_ssid_bcast_type {
6001 BCAST_UNKNOWN = 0,
6002 BCAST_NORMAL = 1,
6003 BCAST_HIDDEN = 2,
6004};
6005
6006#define WMI_NLO_MAX_SSIDS 16
6007#define WMI_NLO_MAX_CHAN 48
6008
6009#define WMI_NLO_CONFIG_STOP BIT(0)
6010#define WMI_NLO_CONFIG_START BIT(1)
6011#define WMI_NLO_CONFIG_RESET BIT(2)
6012#define WMI_NLO_CONFIG_SLOW_SCAN BIT(4)
6013#define WMI_NLO_CONFIG_FAST_SCAN BIT(5)
6014#define WMI_NLO_CONFIG_SSID_HIDE_EN BIT(6)
6015
6016/* This bit is used to indicate if EPNO or supplicant PNO is enabled.
6017 * Only one of them can be enabled at a given time
6018 */
6019#define WMI_NLO_CONFIG_ENLO BIT(7)
6020#define WMI_NLO_CONFIG_SCAN_PASSIVE BIT(8)
6021#define WMI_NLO_CONFIG_ENLO_RESET BIT(9)
6022#define WMI_NLO_CONFIG_SPOOFED_MAC_IN_PROBE_REQ BIT(10)
6023#define WMI_NLO_CONFIG_RANDOM_SEQ_NO_IN_PROBE_REQ BIT(11)
6024#define WMI_NLO_CONFIG_ENABLE_IE_WHITELIST_IN_PROBE_REQ BIT(12)
6025#define WMI_NLO_CONFIG_ENABLE_CNLO_RSSI_CONFIG BIT(13)
6026
6027struct wmi_nlo_ssid_param {
6028 u32 valid;
6029 struct wmi_ssid ssid;
6030} __packed;
6031
6032struct wmi_nlo_enc_param {
6033 u32 valid;
6034 u32 enc_type;
6035} __packed;
6036
6037struct wmi_nlo_auth_param {
6038 u32 valid;
6039 u32 auth_type;
6040} __packed;
6041
6042struct wmi_nlo_bcast_nw_param {
6043 u32 valid;
6044 u32 bcast_nw_type;
6045} __packed;
6046
6047struct wmi_nlo_rssi_param {
6048 u32 valid;
6049 s32 rssi;
6050} __packed;
6051
6052struct nlo_configured_parameters {
6053 /* TLV tag and len;*/
6054 u32 tlv_header;
6055 struct wmi_nlo_ssid_param ssid;
6056 struct wmi_nlo_enc_param enc_type;
6057 struct wmi_nlo_auth_param auth_type;
6058 struct wmi_nlo_rssi_param rssi_cond;
6059
6060 /* indicates if the SSID is hidden or not */
6061 struct wmi_nlo_bcast_nw_param bcast_nw_type;
6062} __packed;
6063
6064struct wmi_network_type {
6065 struct wmi_ssid ssid;
6066 u32 authentication;
6067 u32 encryption;
6068 u32 bcast_nw_type;
6069 u8 channel_count;
6070 u16 channels[WMI_PNO_MAX_NETW_CHANNELS_EX];
6071 s32 rssi_threshold;
6072};
6073
6074struct wmi_pno_scan_req {
6075 u8 enable;
6076 u8 vdev_id;
6077 u8 uc_networks_count;
6078 struct wmi_network_type a_networks[WMI_PNO_MAX_SUPP_NETWORKS];
6079 u32 fast_scan_period;
6080 u32 slow_scan_period;
6081 u8 fast_scan_max_cycles;
6082
6083 bool do_passive_scan;
6084
6085 u32 delay_start_time;
6086 u32 active_min_time;
6087 u32 active_max_time;
6088 u32 passive_min_time;
6089 u32 passive_max_time;
6090
6091 /* mac address randomization attributes */
6092 u32 enable_pno_scan_randomization;
6093 u8 mac_addr[ETH_ALEN];
6094 u8 mac_addr_mask[ETH_ALEN];
6095};
6096
6097struct wmi_wow_nlo_config_cmd {
6098 u32 tlv_header;
6099 u32 flags;
6100 u32 vdev_id;
6101 u32 fast_scan_max_cycles;
6102 u32 active_dwell_time;
6103 u32 passive_dwell_time;
6104 u32 probe_bundle_size;
6105
6106 /* ART = IRT */
6107 u32 rest_time;
6108
6109 /* Max value that can be reached after SBM */
6110 u32 max_rest_time;
6111
6112 /* SBM */
6113 u32 scan_backoff_multiplier;
6114
6115 /* SCBM */
6116 u32 fast_scan_period;
6117
6118 /* specific to windows */
6119 u32 slow_scan_period;
6120
6121 u32 no_of_ssids;
6122
6123 u32 num_of_channels;
6124
6125 /* NLO scan start delay time in milliseconds */
6126 u32 delay_start_time;
6127
6128 /* MAC Address to use in Probe Req as SA */
6129 struct wmi_mac_addr mac_addr;
6130
6131 /* Mask on which MAC has to be randomized */
6132 struct wmi_mac_addr mac_mask;
6133
6134 /* IE bitmap to use in Probe Req */
6135 u32 ie_bitmap[8];
6136
6137 /* Number of vendor OUIs. In the TLV vendor_oui[] */
6138 u32 num_vendor_oui;
6139
6140 /* Number of connected NLO band preferences */
6141 u32 num_cnlo_band_pref;
6142
6143 /* The TLVs will follow.
6144 * nlo_configured_parameters nlo_list[];
6145 * u32 channel_list[num_of_channels];
6146 */
6147} __packed;
6148
6149#define WMI_MAX_NS_OFFLOADS 2
6150#define WMI_MAX_ARP_OFFLOADS 2
6151
6152#define WMI_ARPOL_FLAGS_VALID BIT(0)
6153#define WMI_ARPOL_FLAGS_MAC_VALID BIT(1)
6154#define WMI_ARPOL_FLAGS_REMOTE_IP_VALID BIT(2)
6155
6156struct wmi_arp_offload_tuple {
6157 u32 tlv_header;
6158 u32 flags;
6159 u8 target_ipaddr[4];
6160 u8 remote_ipaddr[4];
6161 struct wmi_mac_addr target_mac;
6162} __packed;
6163
6164#define WMI_NSOL_FLAGS_VALID BIT(0)
6165#define WMI_NSOL_FLAGS_MAC_VALID BIT(1)
6166#define WMI_NSOL_FLAGS_REMOTE_IP_VALID BIT(2)
6167#define WMI_NSOL_FLAGS_IS_IPV6_ANYCAST BIT(3)
6168
6169#define WMI_NSOL_MAX_TARGET_IPS 2
6170
6171struct wmi_ns_offload_tuple {
6172 u32 tlv_header;
6173 u32 flags;
6174 u8 target_ipaddr[WMI_NSOL_MAX_TARGET_IPS][16];
6175 u8 solicitation_ipaddr[16];
6176 u8 remote_ipaddr[16];
6177 struct wmi_mac_addr target_mac;
6178} __packed;
6179
6180struct wmi_set_arp_ns_offload_cmd {
6181 u32 tlv_header;
6182 u32 flags;
6183 u32 vdev_id;
6184 u32 num_ns_ext_tuples;
6185 /* The TLVs follow:
6186 * wmi_ns_offload_tuple ns_tuples[WMI_MAX_NS_OFFLOADS];
6187 * wmi_arp_offload_tuple arp_tuples[WMI_MAX_ARP_OFFLOADS];
6188 * wmi_ns_offload_tuple ns_ext_tuples[num_ns_ext_tuples];
6189 */
6190} __packed;
6191
6192#define GTK_OFFLOAD_OPCODE_MASK 0xFF000000
6193#define GTK_OFFLOAD_ENABLE_OPCODE 0x01000000
6194#define GTK_OFFLOAD_DISABLE_OPCODE 0x02000000
6195#define GTK_OFFLOAD_REQUEST_STATUS_OPCODE 0x04000000
6196
6197#define GTK_OFFLOAD_KEK_BYTES 16
6198#define GTK_OFFLOAD_KCK_BYTES 16
6199#define GTK_REPLAY_COUNTER_BYTES 8
6200#define WMI_MAX_KEY_LEN 32
6201#define IGTK_PN_SIZE 6
6202
6203struct wmi_replayc_cnt {
6204 union {
6205 u8 counter[GTK_REPLAY_COUNTER_BYTES];
6206 struct {
6207 u32 word0;
6208 u32 word1;
6209 } __packed;
6210 } __packed;
6211} __packed;
6212
6213struct wmi_gtk_offload_status_event {
6214 u32 vdev_id;
6215 u32 flags;
6216 u32 refresh_cnt;
6217 struct wmi_replayc_cnt replay_ctr;
6218 u8 igtk_key_index;
6219 u8 igtk_key_length;
6220 u8 igtk_key_rsc[IGTK_PN_SIZE];
6221 u8 igtk_key[WMI_MAX_KEY_LEN];
6222 u8 gtk_key_index;
6223 u8 gtk_key_length;
6224 u8 gtk_key_rsc[GTK_REPLAY_COUNTER_BYTES];
6225 u8 gtk_key[WMI_MAX_KEY_LEN];
6226} __packed;
6227
6228struct wmi_gtk_rekey_offload_cmd {
6229 u32 tlv_header;
6230 u32 vdev_id;
6231 u32 flags;
6232 u8 kek[GTK_OFFLOAD_KEK_BYTES];
6233 u8 kck[GTK_OFFLOAD_KCK_BYTES];
6234 u8 replay_ctr[GTK_REPLAY_COUNTER_BYTES];
6235} __packed;
6236
6237#define BIOS_SAR_TABLE_LEN (22)
6238#define BIOS_SAR_RSVD1_LEN (6)
6239#define BIOS_SAR_RSVD2_LEN (18)
6240
6241struct wmi_pdev_set_sar_table_cmd {
6242 u32 tlv_header;
6243 u32 pdev_id;
6244 u32 sar_len;
6245 u32 rsvd_len;
6246} __packed;
6247
6248struct wmi_pdev_set_geo_table_cmd {
6249 u32 tlv_header;
6250 u32 pdev_id;
6251 u32 rsvd_len;
6252} __packed;
6253
6254struct wmi_sta_keepalive_cmd {
6255 u32 tlv_header;
6256 u32 vdev_id;
6257 u32 enabled;
6258
6259 /* WMI_STA_KEEPALIVE_METHOD_ */
6260 u32 method;
6261
6262 /* in seconds */
6263 u32 interval;
6264
6265 /* following this structure is the TLV for struct
6266 * wmi_sta_keepalive_arp_resp
6267 */
6268} __packed;
6269
6270struct wmi_sta_keepalive_arp_resp {
6271 u32 tlv_header;
6272 u32 src_ip4_addr;
6273 u32 dest_ip4_addr;
6274 struct wmi_mac_addr dest_mac_addr;
6275} __packed;
6276
6277struct wmi_sta_keepalive_arg {
6278 u32 vdev_id;
6279 u32 enabled;
6280 u32 method;
6281 u32 interval;
6282 u32 src_ip4_addr;
6283 u32 dest_ip4_addr;
6284 const u8 dest_mac_addr[ETH_ALEN];
6285};
6286
6287enum wmi_sta_keepalive_method {
6288 WMI_STA_KEEPALIVE_METHOD_NULL_FRAME = 1,
6289 WMI_STA_KEEPALIVE_METHOD_UNSOLICITED_ARP_RESPONSE = 2,
6290 WMI_STA_KEEPALIVE_METHOD_ETHERNET_LOOPBACK = 3,
6291 WMI_STA_KEEPALIVE_METHOD_GRATUITOUS_ARP_REQUEST = 4,
6292 WMI_STA_KEEPALIVE_METHOD_MGMT_VENDOR_ACTION = 5,
6293};
6294
6295#define WMI_STA_KEEPALIVE_INTERVAL_DEFAULT 30
6296#define WMI_STA_KEEPALIVE_INTERVAL_DISABLE 0
6297
6298const void **ath11k_wmi_tlv_parse_alloc(struct ath11k_base *ab, const void *ptr,
6299 size_t len, gfp_t gfp);
6300int ath11k_wmi_cmd_send(struct ath11k_pdev_wmi *wmi, struct sk_buff *skb,
6301 u32 cmd_id);
6302struct sk_buff *ath11k_wmi_alloc_skb(struct ath11k_wmi_base *wmi_sc, u32 len);
6303int ath11k_wmi_mgmt_send(struct ath11k *ar, u32 vdev_id, u32 buf_id,
6304 struct sk_buff *frame);
6305int ath11k_wmi_bcn_tmpl(struct ath11k *ar, u32 vdev_id,
6306 struct ieee80211_mutable_offsets *offs,
6307 struct sk_buff *bcn, u32 ema_param);
6308int ath11k_wmi_vdev_down(struct ath11k *ar, u8 vdev_id);
6309int ath11k_wmi_vdev_up(struct ath11k *ar, u32 vdev_id, u32 aid,
6310 const u8 *bssid, u8 *tx_bssid, u32 nontx_profile_idx,
6311 u32 nontx_profile_cnt);
6312int ath11k_wmi_vdev_stop(struct ath11k *ar, u8 vdev_id);
6313int ath11k_wmi_vdev_start(struct ath11k *ar, struct wmi_vdev_start_req_arg *arg,
6314 bool restart);
6315int ath11k_wmi_set_peer_param(struct ath11k *ar, const u8 *peer_addr,
6316 u32 vdev_id, u32 param_id, u32 param_val);
6317int ath11k_wmi_pdev_set_param(struct ath11k *ar, u32 param_id,
6318 u32 param_value, u8 pdev_id);
6319int ath11k_wmi_pdev_set_ps_mode(struct ath11k *ar, int vdev_id,
6320 enum wmi_sta_ps_mode psmode);
6321int ath11k_wmi_wait_for_unified_ready(struct ath11k_base *ab);
6322int ath11k_wmi_cmd_init(struct ath11k_base *ab);
6323int ath11k_wmi_wait_for_service_ready(struct ath11k_base *ab);
6324int ath11k_wmi_connect(struct ath11k_base *ab);
6325int ath11k_wmi_pdev_attach(struct ath11k_base *ab,
6326 u8 pdev_id);
6327int ath11k_wmi_attach(struct ath11k_base *ab);
6328void ath11k_wmi_detach(struct ath11k_base *ab);
6329int ath11k_wmi_vdev_create(struct ath11k *ar, u8 *macaddr,
6330 struct vdev_create_params *param);
6331int ath11k_wmi_peer_rx_reorder_queue_setup(struct ath11k *ar, int vdev_id,
6332 const u8 *addr, dma_addr_t paddr,
6333 u8 tid, u8 ba_window_size_valid,
6334 u32 ba_window_size);
6335int ath11k_wmi_send_peer_create_cmd(struct ath11k *ar,
6336 struct peer_create_params *param);
6337int ath11k_wmi_vdev_set_param_cmd(struct ath11k *ar, u32 vdev_id,
6338 u32 param_id, u32 param_value);
6339
6340int ath11k_wmi_set_sta_ps_param(struct ath11k *ar, u32 vdev_id,
6341 u32 param, u32 param_value);
6342int ath11k_wmi_force_fw_hang_cmd(struct ath11k *ar, u32 type, u32 delay_time_ms);
6343int ath11k_wmi_send_peer_delete_cmd(struct ath11k *ar,
6344 const u8 *peer_addr, u8 vdev_id);
6345int ath11k_wmi_vdev_delete(struct ath11k *ar, u8 vdev_id);
6346void ath11k_wmi_start_scan_init(struct ath11k *ar, struct scan_req_params *arg);
6347int ath11k_wmi_send_scan_start_cmd(struct ath11k *ar,
6348 struct scan_req_params *params);
6349int ath11k_wmi_send_scan_stop_cmd(struct ath11k *ar,
6350 struct scan_cancel_param *param);
6351int ath11k_wmi_send_wmm_update_cmd_tlv(struct ath11k *ar, u32 vdev_id,
6352 struct wmi_wmm_params_all_arg *param);
6353int ath11k_wmi_pdev_suspend(struct ath11k *ar, u32 suspend_opt,
6354 u32 pdev_id);
6355int ath11k_wmi_pdev_resume(struct ath11k *ar, u32 pdev_id);
6356
6357int ath11k_wmi_send_peer_assoc_cmd(struct ath11k *ar,
6358 struct peer_assoc_params *param);
6359int ath11k_wmi_vdev_install_key(struct ath11k *ar,
6360 struct wmi_vdev_install_key_arg *arg);
6361int ath11k_wmi_pdev_bss_chan_info_request(struct ath11k *ar,
6362 enum wmi_bss_chan_info_req_type type);
6363int ath11k_wmi_send_stats_request_cmd(struct ath11k *ar,
6364 struct stats_request_params *param);
6365int ath11k_wmi_send_pdev_temperature_cmd(struct ath11k *ar);
6366int ath11k_wmi_send_peer_flush_tids_cmd(struct ath11k *ar,
6367 u8 peer_addr[ETH_ALEN],
6368 struct peer_flush_params *param);
6369int ath11k_wmi_send_set_ap_ps_param_cmd(struct ath11k *ar, u8 *peer_addr,
6370 struct ap_ps_params *param);
6371int ath11k_wmi_send_scan_chan_list_cmd(struct ath11k *ar,
6372 struct scan_chan_list_params *chan_list);
6373int ath11k_wmi_send_dfs_phyerr_offload_enable_cmd(struct ath11k *ar,
6374 u32 pdev_id);
6375int ath11k_wmi_addba_clear_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac);
6376int ath11k_wmi_addba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac,
6377 u32 tid, u32 buf_size);
6378int ath11k_wmi_addba_set_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac,
6379 u32 tid, u32 status);
6380int ath11k_wmi_delba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac,
6381 u32 tid, u32 initiator, u32 reason);
6382int ath11k_wmi_send_bcn_offload_control_cmd(struct ath11k *ar,
6383 u32 vdev_id, u32 bcn_ctrl_op);
6384int ath11k_wmi_send_set_current_country_cmd(struct ath11k *ar,
6385 struct wmi_set_current_country_params *param);
6386int
6387ath11k_wmi_send_init_country_cmd(struct ath11k *ar,
6388 struct wmi_init_country_params init_cc_param);
6389
6390int ath11k_wmi_send_11d_scan_start_cmd(struct ath11k *ar,
6391 struct wmi_11d_scan_start_params *param);
6392int ath11k_wmi_send_11d_scan_stop_cmd(struct ath11k *ar, u32 vdev_id);
6393
6394int
6395ath11k_wmi_send_thermal_mitigation_param_cmd(struct ath11k *ar,
6396 struct thermal_mitigation_params *param);
6397int ath11k_wmi_pdev_pktlog_enable(struct ath11k *ar, u32 pktlog_filter);
6398int ath11k_wmi_pdev_pktlog_disable(struct ath11k *ar);
6399int ath11k_wmi_pdev_peer_pktlog_filter(struct ath11k *ar, u8 *addr, u8 enable);
6400int
6401ath11k_wmi_rx_reord_queue_remove(struct ath11k *ar,
6402 struct rx_reorder_queue_remove_params *param);
6403int ath11k_wmi_send_pdev_set_regdomain(struct ath11k *ar,
6404 struct pdev_set_regdomain_params *param);
6405int ath11k_wmi_pull_fw_stats(struct ath11k_base *ab, struct sk_buff *skb,
6406 struct ath11k_fw_stats *stats);
6407void ath11k_wmi_fw_stats_fill(struct ath11k *ar,
6408 struct ath11k_fw_stats *fw_stats, u32 stats_id,
6409 char *buf);
6410int ath11k_wmi_simulate_radar(struct ath11k *ar);
6411void ath11k_wmi_fill_default_twt_params(struct wmi_twt_enable_params *twt_params);
6412int ath11k_wmi_send_twt_enable_cmd(struct ath11k *ar, u32 pdev_id,
6413 struct wmi_twt_enable_params *params);
6414int ath11k_wmi_send_twt_disable_cmd(struct ath11k *ar, u32 pdev_id);
6415int ath11k_wmi_send_twt_add_dialog_cmd(struct ath11k *ar,
6416 struct wmi_twt_add_dialog_params *params);
6417int ath11k_wmi_send_twt_del_dialog_cmd(struct ath11k *ar,
6418 struct wmi_twt_del_dialog_params *params);
6419int ath11k_wmi_send_twt_pause_dialog_cmd(struct ath11k *ar,
6420 struct wmi_twt_pause_dialog_params *params);
6421int ath11k_wmi_send_twt_resume_dialog_cmd(struct ath11k *ar,
6422 struct wmi_twt_resume_dialog_params *params);
6423int ath11k_wmi_send_obss_spr_cmd(struct ath11k *ar, u32 vdev_id,
6424 struct ieee80211_he_obss_pd *he_obss_pd);
6425int ath11k_wmi_pdev_set_srg_bss_color_bitmap(struct ath11k *ar, u32 *bitmap);
6426int ath11k_wmi_pdev_set_srg_patial_bssid_bitmap(struct ath11k *ar, u32 *bitmap);
6427int ath11k_wmi_pdev_srg_obss_color_enable_bitmap(struct ath11k *ar,
6428 u32 *bitmap);
6429int ath11k_wmi_pdev_srg_obss_bssid_enable_bitmap(struct ath11k *ar,
6430 u32 *bitmap);
6431int ath11k_wmi_pdev_non_srg_obss_color_enable_bitmap(struct ath11k *ar,
6432 u32 *bitmap);
6433int ath11k_wmi_pdev_non_srg_obss_bssid_enable_bitmap(struct ath11k *ar,
6434 u32 *bitmap);
6435int ath11k_wmi_send_obss_color_collision_cfg_cmd(struct ath11k *ar, u32 vdev_id,
6436 u8 bss_color, u32 period,
6437 bool enable);
6438int ath11k_wmi_send_bss_color_change_enable_cmd(struct ath11k *ar, u32 vdev_id,
6439 bool enable);
6440int ath11k_wmi_pdev_lro_cfg(struct ath11k *ar, int pdev_id);
6441int ath11k_wmi_pdev_dma_ring_cfg(struct ath11k *ar,
6442 struct ath11k_wmi_pdev_dma_ring_cfg_req_cmd *param);
6443int ath11k_wmi_vdev_spectral_enable(struct ath11k *ar, u32 vdev_id,
6444 u32 trigger, u32 enable);
6445int ath11k_wmi_vdev_spectral_conf(struct ath11k *ar,
6446 struct ath11k_wmi_vdev_spectral_conf_param *param);
6447int ath11k_wmi_fils_discovery_tmpl(struct ath11k *ar, u32 vdev_id,
6448 struct sk_buff *tmpl);
6449int ath11k_wmi_fils_discovery(struct ath11k *ar, u32 vdev_id, u32 interval,
6450 bool unsol_bcast_probe_resp_enabled);
6451int ath11k_wmi_probe_resp_tmpl(struct ath11k *ar, u32 vdev_id,
6452 struct sk_buff *tmpl);
6453int ath11k_wmi_set_hw_mode(struct ath11k_base *ab,
6454 enum wmi_host_hw_mode_config_type mode);
6455int ath11k_wmi_wow_host_wakeup_ind(struct ath11k *ar);
6456int ath11k_wmi_wow_enable(struct ath11k *ar);
6457int ath11k_wmi_scan_prob_req_oui(struct ath11k *ar,
6458 const u8 mac_addr[ETH_ALEN]);
6459int ath11k_wmi_fw_dbglog_cfg(struct ath11k *ar, u32 *module_id_bitmap,
6460 struct ath11k_fw_dbglog *dbglog);
6461int ath11k_wmi_wow_config_pno(struct ath11k *ar, u32 vdev_id,
6462 struct wmi_pno_scan_req *pno_scan);
6463int ath11k_wmi_wow_del_pattern(struct ath11k *ar, u32 vdev_id, u32 pattern_id);
6464int ath11k_wmi_wow_add_pattern(struct ath11k *ar, u32 vdev_id, u32 pattern_id,
6465 const u8 *pattern, const u8 *mask,
6466 int pattern_len, int pattern_offset);
6467int ath11k_wmi_wow_add_wakeup_event(struct ath11k *ar, u32 vdev_id,
6468 enum wmi_wow_wakeup_event event,
6469 u32 enable);
6470int ath11k_wmi_hw_data_filter_cmd(struct ath11k *ar, u32 vdev_id,
6471 u32 filter_bitmap, bool enable);
6472int ath11k_wmi_arp_ns_offload(struct ath11k *ar,
6473 struct ath11k_vif *arvif, bool enable);
6474int ath11k_wmi_gtk_rekey_offload(struct ath11k *ar,
6475 struct ath11k_vif *arvif, bool enable);
6476int ath11k_wmi_gtk_rekey_getinfo(struct ath11k *ar,
6477 struct ath11k_vif *arvif);
6478int ath11k_wmi_pdev_set_bios_sar_table_param(struct ath11k *ar, const u8 *sar_val);
6479int ath11k_wmi_pdev_set_bios_geo_table_param(struct ath11k *ar);
6480int ath11k_wmi_sta_keepalive(struct ath11k *ar,
6481 const struct wmi_sta_keepalive_arg *arg);
6482
6483#endif
1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
2/*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7#ifndef ATH11K_WMI_H
8#define ATH11K_WMI_H
9
10#include <net/mac80211.h>
11#include "htc.h"
12
13struct ath11k_base;
14struct ath11k;
15struct ath11k_fw_stats;
16struct ath11k_fw_dbglog;
17struct ath11k_vif;
18struct ath11k_reg_tpc_power_info;
19
20#define PSOC_HOST_MAX_NUM_SS (8)
21
22/* defines to set Packet extension values which can be 0 us, 8 usec or 16 usec */
23#define MAX_HE_NSS 8
24#define MAX_HE_MODULATION 8
25#define MAX_HE_RU 4
26#define HE_MODULATION_NONE 7
27#define HE_PET_0_USEC 0
28#define HE_PET_8_USEC 1
29#define HE_PET_16_USEC 2
30
31#define WMI_MAX_CHAINS 8
32
33#define WMI_MAX_NUM_SS MAX_HE_NSS
34#define WMI_MAX_NUM_RU MAX_HE_RU
35
36#define WMI_TLV_CMD(grp_id) (((grp_id) << 12) | 0x1)
37#define WMI_TLV_EV(grp_id) (((grp_id) << 12) | 0x1)
38#define WMI_TLV_CMD_UNSUPPORTED 0
39#define WMI_TLV_PDEV_PARAM_UNSUPPORTED 0
40#define WMI_TLV_VDEV_PARAM_UNSUPPORTED 0
41
42struct wmi_cmd_hdr {
43 u32 cmd_id;
44} __packed;
45
46struct wmi_tlv {
47 u32 header;
48 u8 value[];
49} __packed;
50
51#define WMI_TLV_LEN GENMASK(15, 0)
52#define WMI_TLV_TAG GENMASK(31, 16)
53#define TLV_HDR_SIZE sizeof_field(struct wmi_tlv, header)
54
55#define WMI_CMD_HDR_CMD_ID GENMASK(23, 0)
56#define WMI_MAX_MEM_REQS 32
57#define ATH11K_MAX_HW_LISTEN_INTERVAL 5
58
59#define WLAN_SCAN_MAX_HINT_S_SSID 10
60#define WLAN_SCAN_MAX_HINT_BSSID 10
61#define MAX_RNR_BSS 5
62
63#define WLAN_SCAN_MAX_HINT_S_SSID 10
64#define WLAN_SCAN_MAX_HINT_BSSID 10
65#define MAX_RNR_BSS 5
66
67#define WLAN_SCAN_PARAMS_MAX_SSID 16
68#define WLAN_SCAN_PARAMS_MAX_BSSID 4
69#define WLAN_SCAN_PARAMS_MAX_IE_LEN 256
70
71#define WMI_APPEND_TO_EXISTING_CHAN_LIST_FLAG 1
72
73#define MAX_WMI_UTF_LEN 252
74#define WMI_BA_MODE_BUFFER_SIZE_256 3
75/*
76 * HW mode config type replicated from FW header
77 * @WMI_HOST_HW_MODE_SINGLE: Only one PHY is active.
78 * @WMI_HOST_HW_MODE_DBS: Both PHYs are active in different bands,
79 * one in 2G and another in 5G.
80 * @WMI_HOST_HW_MODE_SBS_PASSIVE: Both PHYs are in passive mode (only rx) in
81 * same band; no tx allowed.
82 * @WMI_HOST_HW_MODE_SBS: Both PHYs are active in the same band.
83 * Support for both PHYs within one band is planned
84 * for 5G only(as indicated in WMI_MAC_PHY_CAPABILITIES),
85 * but could be extended to other bands in the future.
86 * The separation of the band between the two PHYs needs
87 * to be communicated separately.
88 * @WMI_HOST_HW_MODE_DBS_SBS: 3 PHYs, with 2 on the same band doing SBS
89 * as in WMI_HW_MODE_SBS, and 3rd on the other band
90 * @WMI_HOST_HW_MODE_DBS_OR_SBS: Two PHY with one PHY capabale of both 2G and
91 * 5G. It can support SBS (5G + 5G) OR DBS (5G + 2G).
92 * @WMI_HOST_HW_MODE_MAX: Max hw_mode_id. Used to indicate invalid mode.
93 */
94enum wmi_host_hw_mode_config_type {
95 WMI_HOST_HW_MODE_SINGLE = 0,
96 WMI_HOST_HW_MODE_DBS = 1,
97 WMI_HOST_HW_MODE_SBS_PASSIVE = 2,
98 WMI_HOST_HW_MODE_SBS = 3,
99 WMI_HOST_HW_MODE_DBS_SBS = 4,
100 WMI_HOST_HW_MODE_DBS_OR_SBS = 5,
101
102 /* keep last */
103 WMI_HOST_HW_MODE_MAX
104};
105
106/* HW mode priority values used to detect the preferred HW mode
107 * on the available modes.
108 */
109enum wmi_host_hw_mode_priority {
110 WMI_HOST_HW_MODE_DBS_SBS_PRI,
111 WMI_HOST_HW_MODE_DBS_PRI,
112 WMI_HOST_HW_MODE_DBS_OR_SBS_PRI,
113 WMI_HOST_HW_MODE_SBS_PRI,
114 WMI_HOST_HW_MODE_SBS_PASSIVE_PRI,
115 WMI_HOST_HW_MODE_SINGLE_PRI,
116
117 /* keep last the lowest priority */
118 WMI_HOST_HW_MODE_MAX_PRI
119};
120
121enum WMI_HOST_WLAN_BAND {
122 WMI_HOST_WLAN_2G_CAP = 0x1,
123 WMI_HOST_WLAN_5G_CAP = 0x2,
124 WMI_HOST_WLAN_2G_5G_CAP = WMI_HOST_WLAN_2G_CAP | WMI_HOST_WLAN_5G_CAP,
125};
126
127/* Parameters used for WMI_VDEV_PARAM_AUTORATE_MISC_CFG command.
128 * Used only for HE auto rate mode.
129 */
130enum {
131 /* HE LTF related configuration */
132 WMI_HE_AUTORATE_LTF_1X = BIT(0),
133 WMI_HE_AUTORATE_LTF_2X = BIT(1),
134 WMI_HE_AUTORATE_LTF_4X = BIT(2),
135
136 /* HE GI related configuration */
137 WMI_AUTORATE_400NS_GI = BIT(8),
138 WMI_AUTORATE_800NS_GI = BIT(9),
139 WMI_AUTORATE_1600NS_GI = BIT(10),
140 WMI_AUTORATE_3200NS_GI = BIT(11),
141};
142
143enum {
144 WMI_HOST_VDEV_FLAGS_NON_MBSSID_AP = 0x00000001,
145 WMI_HOST_VDEV_FLAGS_TRANSMIT_AP = 0x00000002,
146 WMI_HOST_VDEV_FLAGS_NON_TRANSMIT_AP = 0x00000004,
147 WMI_HOST_VDEV_FLAGS_EMA_MODE = 0x00000008,
148 WMI_HOST_VDEV_FLAGS_SCAN_MODE_VAP = 0x00000010,
149};
150
151/*
152 * wmi command groups.
153 */
154enum wmi_cmd_group {
155 /* 0 to 2 are reserved */
156 WMI_GRP_START = 0x3,
157 WMI_GRP_SCAN = WMI_GRP_START,
158 WMI_GRP_PDEV = 0x4,
159 WMI_GRP_VDEV = 0x5,
160 WMI_GRP_PEER = 0x6,
161 WMI_GRP_MGMT = 0x7,
162 WMI_GRP_BA_NEG = 0x8,
163 WMI_GRP_STA_PS = 0x9,
164 WMI_GRP_DFS = 0xa,
165 WMI_GRP_ROAM = 0xb,
166 WMI_GRP_OFL_SCAN = 0xc,
167 WMI_GRP_P2P = 0xd,
168 WMI_GRP_AP_PS = 0xe,
169 WMI_GRP_RATE_CTRL = 0xf,
170 WMI_GRP_PROFILE = 0x10,
171 WMI_GRP_SUSPEND = 0x11,
172 WMI_GRP_BCN_FILTER = 0x12,
173 WMI_GRP_WOW = 0x13,
174 WMI_GRP_RTT = 0x14,
175 WMI_GRP_SPECTRAL = 0x15,
176 WMI_GRP_STATS = 0x16,
177 WMI_GRP_ARP_NS_OFL = 0x17,
178 WMI_GRP_NLO_OFL = 0x18,
179 WMI_GRP_GTK_OFL = 0x19,
180 WMI_GRP_CSA_OFL = 0x1a,
181 WMI_GRP_CHATTER = 0x1b,
182 WMI_GRP_TID_ADDBA = 0x1c,
183 WMI_GRP_MISC = 0x1d,
184 WMI_GRP_GPIO = 0x1e,
185 WMI_GRP_FWTEST = 0x1f,
186 WMI_GRP_TDLS = 0x20,
187 WMI_GRP_RESMGR = 0x21,
188 WMI_GRP_STA_SMPS = 0x22,
189 WMI_GRP_WLAN_HB = 0x23,
190 WMI_GRP_RMC = 0x24,
191 WMI_GRP_MHF_OFL = 0x25,
192 WMI_GRP_LOCATION_SCAN = 0x26,
193 WMI_GRP_OEM = 0x27,
194 WMI_GRP_NAN = 0x28,
195 WMI_GRP_COEX = 0x29,
196 WMI_GRP_OBSS_OFL = 0x2a,
197 WMI_GRP_LPI = 0x2b,
198 WMI_GRP_EXTSCAN = 0x2c,
199 WMI_GRP_DHCP_OFL = 0x2d,
200 WMI_GRP_IPA = 0x2e,
201 WMI_GRP_MDNS_OFL = 0x2f,
202 WMI_GRP_SAP_OFL = 0x30,
203 WMI_GRP_OCB = 0x31,
204 WMI_GRP_SOC = 0x32,
205 WMI_GRP_PKT_FILTER = 0x33,
206 WMI_GRP_MAWC = 0x34,
207 WMI_GRP_PMF_OFFLOAD = 0x35,
208 WMI_GRP_BPF_OFFLOAD = 0x36,
209 WMI_GRP_NAN_DATA = 0x37,
210 WMI_GRP_PROTOTYPE = 0x38,
211 WMI_GRP_MONITOR = 0x39,
212 WMI_GRP_REGULATORY = 0x3a,
213 WMI_GRP_HW_DATA_FILTER = 0x3b,
214 WMI_GRP_WLM = 0x3c,
215 WMI_GRP_11K_OFFLOAD = 0x3d,
216 WMI_GRP_TWT = 0x3e,
217 WMI_GRP_MOTION_DET = 0x3f,
218 WMI_GRP_SPATIAL_REUSE = 0x40,
219};
220
221#define WMI_CMD_GRP(grp_id) (((grp_id) << 12) | 0x1)
222#define WMI_EVT_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1)
223
224#define WMI_CMD_UNSUPPORTED 0
225
226enum wmi_tlv_cmd_id {
227 WMI_INIT_CMDID = 0x1,
228 WMI_START_SCAN_CMDID = WMI_TLV_CMD(WMI_GRP_SCAN),
229 WMI_STOP_SCAN_CMDID,
230 WMI_SCAN_CHAN_LIST_CMDID,
231 WMI_SCAN_SCH_PRIO_TBL_CMDID,
232 WMI_SCAN_UPDATE_REQUEST_CMDID,
233 WMI_SCAN_PROB_REQ_OUI_CMDID,
234 WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID,
235 WMI_PDEV_SET_REGDOMAIN_CMDID = WMI_TLV_CMD(WMI_GRP_PDEV),
236 WMI_PDEV_SET_CHANNEL_CMDID,
237 WMI_PDEV_SET_PARAM_CMDID,
238 WMI_PDEV_PKTLOG_ENABLE_CMDID,
239 WMI_PDEV_PKTLOG_DISABLE_CMDID,
240 WMI_PDEV_SET_WMM_PARAMS_CMDID,
241 WMI_PDEV_SET_HT_CAP_IE_CMDID,
242 WMI_PDEV_SET_VHT_CAP_IE_CMDID,
243 WMI_PDEV_SET_DSCP_TID_MAP_CMDID,
244 WMI_PDEV_SET_QUIET_MODE_CMDID,
245 WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID,
246 WMI_PDEV_GET_TPC_CONFIG_CMDID,
247 WMI_PDEV_SET_BASE_MACADDR_CMDID,
248 WMI_PDEV_DUMP_CMDID,
249 WMI_PDEV_SET_LED_CONFIG_CMDID,
250 WMI_PDEV_GET_TEMPERATURE_CMDID,
251 WMI_PDEV_SET_LED_FLASHING_CMDID,
252 WMI_PDEV_SMART_ANT_ENABLE_CMDID,
253 WMI_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID,
254 WMI_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID,
255 WMI_PDEV_SET_CTL_TABLE_CMDID,
256 WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID,
257 WMI_PDEV_FIPS_CMDID,
258 WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID,
259 WMI_PDEV_GET_ANI_OFDM_CONFIG_CMDID,
260 WMI_PDEV_GET_NFCAL_POWER_CMDID,
261 WMI_PDEV_GET_TPC_CMDID,
262 WMI_MIB_STATS_ENABLE_CMDID,
263 WMI_PDEV_SET_PCL_CMDID,
264 WMI_PDEV_SET_HW_MODE_CMDID,
265 WMI_PDEV_SET_MAC_CONFIG_CMDID,
266 WMI_PDEV_SET_ANTENNA_MODE_CMDID,
267 WMI_SET_PERIODIC_CHANNEL_STATS_CONFIG_CMDID,
268 WMI_PDEV_WAL_POWER_DEBUG_CMDID,
269 WMI_PDEV_SET_REORDER_TIMEOUT_VAL_CMDID,
270 WMI_PDEV_SET_WAKEUP_CONFIG_CMDID,
271 WMI_PDEV_GET_ANTDIV_STATUS_CMDID,
272 WMI_PDEV_GET_CHIP_POWER_STATS_CMDID,
273 WMI_PDEV_SET_STATS_THRESHOLD_CMDID,
274 WMI_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMDID,
275 WMI_PDEV_UPDATE_PKT_ROUTING_CMDID,
276 WMI_PDEV_CHECK_CAL_VERSION_CMDID,
277 WMI_PDEV_SET_DIVERSITY_GAIN_CMDID,
278 WMI_PDEV_DIV_GET_RSSI_ANTID_CMDID,
279 WMI_PDEV_BSS_CHAN_INFO_REQUEST_CMDID,
280 WMI_PDEV_UPDATE_PMK_CACHE_CMDID,
281 WMI_PDEV_UPDATE_FILS_HLP_PKT_CMDID,
282 WMI_PDEV_UPDATE_CTLTABLE_REQUEST_CMDID,
283 WMI_PDEV_CONFIG_VENDOR_OUI_ACTION_CMDID,
284 WMI_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMDID,
285 WMI_PDEV_SET_RX_FILTER_PROMISCUOUS_CMDID,
286 WMI_PDEV_DMA_RING_CFG_REQ_CMDID,
287 WMI_PDEV_HE_TB_ACTION_FRM_CMDID,
288 WMI_PDEV_PKTLOG_FILTER_CMDID,
289 WMI_PDEV_SET_RAP_CONFIG_CMDID,
290 WMI_PDEV_DSM_FILTER_CMDID,
291 WMI_PDEV_FRAME_INJECT_CMDID,
292 WMI_PDEV_TBTT_OFFSET_SYNC_CMDID,
293 WMI_PDEV_SET_SRG_BSS_COLOR_BITMAP_CMDID,
294 WMI_PDEV_SET_SRG_PARTIAL_BSSID_BITMAP_CMDID,
295 WMI_PDEV_SET_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID,
296 WMI_PDEV_SET_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID,
297 WMI_PDEV_SET_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID,
298 WMI_PDEV_SET_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID,
299 WMI_PDEV_GET_TPC_STATS_CMDID,
300 WMI_PDEV_ENABLE_DURATION_BASED_TX_MODE_SELECTION_CMDID,
301 WMI_PDEV_GET_DPD_STATUS_CMDID,
302 WMI_PDEV_SET_BIOS_SAR_TABLE_CMDID,
303 WMI_PDEV_SET_BIOS_GEO_TABLE_CMDID,
304 WMI_VDEV_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_VDEV),
305 WMI_VDEV_DELETE_CMDID,
306 WMI_VDEV_START_REQUEST_CMDID,
307 WMI_VDEV_RESTART_REQUEST_CMDID,
308 WMI_VDEV_UP_CMDID,
309 WMI_VDEV_STOP_CMDID,
310 WMI_VDEV_DOWN_CMDID,
311 WMI_VDEV_SET_PARAM_CMDID,
312 WMI_VDEV_INSTALL_KEY_CMDID,
313 WMI_VDEV_WNM_SLEEPMODE_CMDID,
314 WMI_VDEV_WMM_ADDTS_CMDID,
315 WMI_VDEV_WMM_DELTS_CMDID,
316 WMI_VDEV_SET_WMM_PARAMS_CMDID,
317 WMI_VDEV_SET_GTX_PARAMS_CMDID,
318 WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID,
319 WMI_VDEV_PLMREQ_START_CMDID,
320 WMI_VDEV_PLMREQ_STOP_CMDID,
321 WMI_VDEV_TSF_TSTAMP_ACTION_CMDID,
322 WMI_VDEV_SET_IE_CMDID,
323 WMI_VDEV_RATEMASK_CMDID,
324 WMI_VDEV_ATF_REQUEST_CMDID,
325 WMI_VDEV_SET_DSCP_TID_MAP_CMDID,
326 WMI_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID,
327 WMI_VDEV_SET_QUIET_MODE_CMDID,
328 WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID,
329 WMI_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMDID,
330 WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMDID,
331 WMI_VDEV_SET_ARP_STAT_CMDID,
332 WMI_VDEV_GET_ARP_STAT_CMDID,
333 WMI_VDEV_GET_TX_POWER_CMDID,
334 WMI_VDEV_LIMIT_OFFCHAN_CMDID,
335 WMI_VDEV_SET_CUSTOM_SW_RETRY_TH_CMDID,
336 WMI_VDEV_CHAINMASK_CONFIG_CMDID,
337 WMI_VDEV_GET_BCN_RECEPTION_STATS_CMDID,
338 WMI_VDEV_GET_MWS_COEX_INFO_CMDID,
339 WMI_VDEV_DELETE_ALL_PEER_CMDID,
340 WMI_VDEV_BSS_MAX_IDLE_TIME_CMDID,
341 WMI_VDEV_AUDIO_SYNC_TRIGGER_CMDID,
342 WMI_VDEV_AUDIO_SYNC_QTIMER_CMDID,
343 WMI_VDEV_SET_PCL_CMDID,
344 WMI_VDEV_GET_BIG_DATA_CMDID,
345 WMI_VDEV_GET_BIG_DATA_P2_CMDID,
346 WMI_VDEV_SET_TPC_POWER_CMDID,
347 WMI_PEER_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_PEER),
348 WMI_PEER_DELETE_CMDID,
349 WMI_PEER_FLUSH_TIDS_CMDID,
350 WMI_PEER_SET_PARAM_CMDID,
351 WMI_PEER_ASSOC_CMDID,
352 WMI_PEER_ADD_WDS_ENTRY_CMDID,
353 WMI_PEER_REMOVE_WDS_ENTRY_CMDID,
354 WMI_PEER_MCAST_GROUP_CMDID,
355 WMI_PEER_INFO_REQ_CMDID,
356 WMI_PEER_GET_ESTIMATED_LINKSPEED_CMDID,
357 WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID,
358 WMI_PEER_UPDATE_WDS_ENTRY_CMDID,
359 WMI_PEER_ADD_PROXY_STA_ENTRY_CMDID,
360 WMI_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID,
361 WMI_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID,
362 WMI_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID,
363 WMI_PEER_ATF_REQUEST_CMDID,
364 WMI_PEER_BWF_REQUEST_CMDID,
365 WMI_PEER_REORDER_QUEUE_SETUP_CMDID,
366 WMI_PEER_REORDER_QUEUE_REMOVE_CMDID,
367 WMI_PEER_SET_RX_BLOCKSIZE_CMDID,
368 WMI_PEER_ANTDIV_INFO_REQ_CMDID,
369 WMI_BCN_TX_CMDID = WMI_TLV_CMD(WMI_GRP_MGMT),
370 WMI_PDEV_SEND_BCN_CMDID,
371 WMI_BCN_TMPL_CMDID,
372 WMI_BCN_FILTER_RX_CMDID,
373 WMI_PRB_REQ_FILTER_RX_CMDID,
374 WMI_MGMT_TX_CMDID,
375 WMI_PRB_TMPL_CMDID,
376 WMI_MGMT_TX_SEND_CMDID,
377 WMI_OFFCHAN_DATA_TX_SEND_CMDID,
378 WMI_PDEV_SEND_FD_CMDID,
379 WMI_BCN_OFFLOAD_CTRL_CMDID,
380 WMI_BSS_COLOR_CHANGE_ENABLE_CMDID,
381 WMI_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMDID,
382 WMI_FILS_DISCOVERY_TMPL_CMDID,
383 WMI_ADDBA_CLEAR_RESP_CMDID = WMI_TLV_CMD(WMI_GRP_BA_NEG),
384 WMI_ADDBA_SEND_CMDID,
385 WMI_ADDBA_STATUS_CMDID,
386 WMI_DELBA_SEND_CMDID,
387 WMI_ADDBA_SET_RESP_CMDID,
388 WMI_SEND_SINGLEAMSDU_CMDID,
389 WMI_STA_POWERSAVE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_PS),
390 WMI_STA_POWERSAVE_PARAM_CMDID,
391 WMI_STA_MIMO_PS_MODE_CMDID,
392 WMI_PDEV_DFS_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_DFS),
393 WMI_PDEV_DFS_DISABLE_CMDID,
394 WMI_DFS_PHYERR_FILTER_ENA_CMDID,
395 WMI_DFS_PHYERR_FILTER_DIS_CMDID,
396 WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMDID,
397 WMI_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMDID,
398 WMI_VDEV_ADFS_CH_CFG_CMDID,
399 WMI_VDEV_ADFS_OCAC_ABORT_CMDID,
400 WMI_ROAM_SCAN_MODE = WMI_TLV_CMD(WMI_GRP_ROAM),
401 WMI_ROAM_SCAN_RSSI_THRESHOLD,
402 WMI_ROAM_SCAN_PERIOD,
403 WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD,
404 WMI_ROAM_AP_PROFILE,
405 WMI_ROAM_CHAN_LIST,
406 WMI_ROAM_SCAN_CMD,
407 WMI_ROAM_SYNCH_COMPLETE,
408 WMI_ROAM_SET_RIC_REQUEST_CMDID,
409 WMI_ROAM_INVOKE_CMDID,
410 WMI_ROAM_FILTER_CMDID,
411 WMI_ROAM_SUBNET_CHANGE_CONFIG_CMDID,
412 WMI_ROAM_CONFIGURE_MAWC_CMDID,
413 WMI_ROAM_SET_MBO_PARAM_CMDID,
414 WMI_ROAM_PER_CONFIG_CMDID,
415 WMI_ROAM_BTM_CONFIG_CMDID,
416 WMI_ENABLE_FILS_CMDID,
417 WMI_OFL_SCAN_ADD_AP_PROFILE = WMI_TLV_CMD(WMI_GRP_OFL_SCAN),
418 WMI_OFL_SCAN_REMOVE_AP_PROFILE,
419 WMI_OFL_SCAN_PERIOD,
420 WMI_P2P_DEV_SET_DEVICE_INFO = WMI_TLV_CMD(WMI_GRP_P2P),
421 WMI_P2P_DEV_SET_DISCOVERABILITY,
422 WMI_P2P_GO_SET_BEACON_IE,
423 WMI_P2P_GO_SET_PROBE_RESP_IE,
424 WMI_P2P_SET_VENDOR_IE_DATA_CMDID,
425 WMI_P2P_DISC_OFFLOAD_CONFIG_CMDID,
426 WMI_P2P_DISC_OFFLOAD_APPIE_CMDID,
427 WMI_P2P_DISC_OFFLOAD_PATTERN_CMDID,
428 WMI_P2P_SET_OPPPS_PARAM_CMDID,
429 WMI_P2P_LISTEN_OFFLOAD_START_CMDID,
430 WMI_P2P_LISTEN_OFFLOAD_STOP_CMDID,
431 WMI_AP_PS_PEER_PARAM_CMDID = WMI_TLV_CMD(WMI_GRP_AP_PS),
432 WMI_AP_PS_PEER_UAPSD_COEX_CMDID,
433 WMI_AP_PS_EGAP_PARAM_CMDID,
434 WMI_PEER_RATE_RETRY_SCHED_CMDID = WMI_TLV_CMD(WMI_GRP_RATE_CTRL),
435 WMI_WLAN_PROFILE_TRIGGER_CMDID = WMI_TLV_CMD(WMI_GRP_PROFILE),
436 WMI_WLAN_PROFILE_SET_HIST_INTVL_CMDID,
437 WMI_WLAN_PROFILE_GET_PROFILE_DATA_CMDID,
438 WMI_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID,
439 WMI_WLAN_PROFILE_LIST_PROFILE_ID_CMDID,
440 WMI_PDEV_SUSPEND_CMDID = WMI_TLV_CMD(WMI_GRP_SUSPEND),
441 WMI_PDEV_RESUME_CMDID,
442 WMI_ADD_BCN_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_BCN_FILTER),
443 WMI_RMV_BCN_FILTER_CMDID,
444 WMI_WOW_ADD_WAKE_PATTERN_CMDID = WMI_TLV_CMD(WMI_GRP_WOW),
445 WMI_WOW_DEL_WAKE_PATTERN_CMDID,
446 WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID,
447 WMI_WOW_ENABLE_CMDID,
448 WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID,
449 WMI_WOW_IOAC_ADD_KEEPALIVE_CMDID,
450 WMI_WOW_IOAC_DEL_KEEPALIVE_CMDID,
451 WMI_WOW_IOAC_ADD_WAKE_PATTERN_CMDID,
452 WMI_WOW_IOAC_DEL_WAKE_PATTERN_CMDID,
453 WMI_D0_WOW_ENABLE_DISABLE_CMDID,
454 WMI_EXTWOW_ENABLE_CMDID,
455 WMI_EXTWOW_SET_APP_TYPE1_PARAMS_CMDID,
456 WMI_EXTWOW_SET_APP_TYPE2_PARAMS_CMDID,
457 WMI_WOW_ENABLE_ICMPV6_NA_FLT_CMDID,
458 WMI_WOW_UDP_SVC_OFLD_CMDID,
459 WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMDID,
460 WMI_WOW_SET_ACTION_WAKE_UP_CMDID,
461 WMI_RTT_MEASREQ_CMDID = WMI_TLV_CMD(WMI_GRP_RTT),
462 WMI_RTT_TSF_CMDID,
463 WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID = WMI_TLV_CMD(WMI_GRP_SPECTRAL),
464 WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID,
465 WMI_REQUEST_STATS_CMDID = WMI_TLV_CMD(WMI_GRP_STATS),
466 WMI_MCC_SCHED_TRAFFIC_STATS_CMDID,
467 WMI_REQUEST_STATS_EXT_CMDID,
468 WMI_REQUEST_LINK_STATS_CMDID,
469 WMI_START_LINK_STATS_CMDID,
470 WMI_CLEAR_LINK_STATS_CMDID,
471 WMI_GET_FW_MEM_DUMP_CMDID,
472 WMI_DEBUG_MESG_FLUSH_CMDID,
473 WMI_DIAG_EVENT_LOG_CONFIG_CMDID,
474 WMI_REQUEST_WLAN_STATS_CMDID,
475 WMI_REQUEST_RCPI_CMDID,
476 WMI_REQUEST_PEER_STATS_INFO_CMDID,
477 WMI_REQUEST_RADIO_CHAN_STATS_CMDID,
478 WMI_SET_ARP_NS_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_ARP_NS_OFL),
479 WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMDID,
480 WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMDID,
481 WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_NLO_OFL),
482 WMI_APFIND_CMDID,
483 WMI_PASSPOINT_LIST_CONFIG_CMDID,
484 WMI_NLO_CONFIGURE_MAWC_CMDID,
485 WMI_GTK_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_GTK_OFL),
486 WMI_CSA_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_CSA_OFL),
487 WMI_CSA_OFFLOAD_CHANSWITCH_CMDID,
488 WMI_CHATTER_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_CHATTER),
489 WMI_CHATTER_ADD_COALESCING_FILTER_CMDID,
490 WMI_CHATTER_DELETE_COALESCING_FILTER_CMDID,
491 WMI_CHATTER_COALESCING_QUERY_CMDID,
492 WMI_PEER_TID_ADDBA_CMDID = WMI_TLV_CMD(WMI_GRP_TID_ADDBA),
493 WMI_PEER_TID_DELBA_CMDID,
494 WMI_STA_DTIM_PS_METHOD_CMDID,
495 WMI_STA_UAPSD_AUTO_TRIG_CMDID,
496 WMI_STA_KEEPALIVE_CMDID,
497 WMI_BA_REQ_SSN_CMDID,
498 WMI_ECHO_CMDID = WMI_TLV_CMD(WMI_GRP_MISC),
499 WMI_PDEV_UTF_CMDID,
500 WMI_DBGLOG_CFG_CMDID,
501 WMI_PDEV_QVIT_CMDID,
502 WMI_PDEV_FTM_INTG_CMDID,
503 WMI_VDEV_SET_KEEPALIVE_CMDID,
504 WMI_VDEV_GET_KEEPALIVE_CMDID,
505 WMI_FORCE_FW_HANG_CMDID,
506 WMI_SET_MCASTBCAST_FILTER_CMDID,
507 WMI_THERMAL_MGMT_CMDID,
508 WMI_HOST_AUTO_SHUTDOWN_CFG_CMDID,
509 WMI_TPC_CHAINMASK_CONFIG_CMDID,
510 WMI_SET_ANTENNA_DIVERSITY_CMDID,
511 WMI_OCB_SET_SCHED_CMDID,
512 WMI_RSSI_BREACH_MONITOR_CONFIG_CMDID,
513 WMI_LRO_CONFIG_CMDID,
514 WMI_TRANSFER_DATA_TO_FLASH_CMDID,
515 WMI_CONFIG_ENHANCED_MCAST_FILTER_CMDID,
516 WMI_VDEV_WISA_CMDID,
517 WMI_DBGLOG_TIME_STAMP_SYNC_CMDID,
518 WMI_SET_MULTIPLE_MCAST_FILTER_CMDID,
519 WMI_READ_DATA_FROM_FLASH_CMDID,
520 WMI_THERM_THROT_SET_CONF_CMDID,
521 WMI_RUNTIME_DPD_RECAL_CMDID,
522 WMI_GET_TPC_POWER_CMDID,
523 WMI_IDLE_TRIGGER_MONITOR_CMDID,
524 WMI_GPIO_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_GPIO),
525 WMI_GPIO_OUTPUT_CMDID,
526 WMI_TXBF_CMDID,
527 WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_FWTEST),
528 WMI_FWTEST_P2P_SET_NOA_PARAM_CMDID,
529 WMI_UNIT_TEST_CMDID,
530 WMI_FWTEST_CMDID,
531 WMI_QBOOST_CFG_CMDID,
532 WMI_TDLS_SET_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_TDLS),
533 WMI_TDLS_PEER_UPDATE_CMDID,
534 WMI_TDLS_SET_OFFCHAN_MODE_CMDID,
535 WMI_RESMGR_ADAPTIVE_OCS_EN_DIS_CMDID = WMI_TLV_CMD(WMI_GRP_RESMGR),
536 WMI_RESMGR_SET_CHAN_TIME_QUOTA_CMDID,
537 WMI_RESMGR_SET_CHAN_LATENCY_CMDID,
538 WMI_STA_SMPS_FORCE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_SMPS),
539 WMI_STA_SMPS_PARAM_CMDID,
540 WMI_HB_SET_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_WLAN_HB),
541 WMI_HB_SET_TCP_PARAMS_CMDID,
542 WMI_HB_SET_TCP_PKT_FILTER_CMDID,
543 WMI_HB_SET_UDP_PARAMS_CMDID,
544 WMI_HB_SET_UDP_PKT_FILTER_CMDID,
545 WMI_RMC_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_RMC),
546 WMI_RMC_SET_ACTION_PERIOD_CMDID,
547 WMI_RMC_CONFIG_CMDID,
548 WMI_RMC_SET_MANUAL_LEADER_CMDID,
549 WMI_MHF_OFFLOAD_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_MHF_OFL),
550 WMI_MHF_OFFLOAD_PLUMB_ROUTING_TBL_CMDID,
551 WMI_BATCH_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN),
552 WMI_BATCH_SCAN_DISABLE_CMDID,
553 WMI_BATCH_SCAN_TRIGGER_RESULT_CMDID,
554 WMI_OEM_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_OEM),
555 WMI_OEM_REQUEST_CMDID,
556 WMI_LPI_OEM_REQ_CMDID,
557 WMI_NAN_CMDID = WMI_TLV_CMD(WMI_GRP_NAN),
558 WMI_MODEM_POWER_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_COEX),
559 WMI_CHAN_AVOID_UPDATE_CMDID,
560 WMI_COEX_CONFIG_CMDID,
561 WMI_CHAN_AVOID_RPT_ALLOW_CMDID,
562 WMI_COEX_GET_ANTENNA_ISOLATION_CMDID,
563 WMI_SAR_LIMITS_CMDID,
564 WMI_OBSS_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_OBSS_OFL),
565 WMI_OBSS_SCAN_DISABLE_CMDID,
566 WMI_OBSS_COLOR_COLLISION_DET_CONFIG_CMDID,
567 WMI_LPI_MGMT_SNOOPING_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_LPI),
568 WMI_LPI_START_SCAN_CMDID,
569 WMI_LPI_STOP_SCAN_CMDID,
570 WMI_EXTSCAN_START_CMDID = WMI_TLV_CMD(WMI_GRP_EXTSCAN),
571 WMI_EXTSCAN_STOP_CMDID,
572 WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID,
573 WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID,
574 WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID,
575 WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID,
576 WMI_EXTSCAN_SET_CAPABILITIES_CMDID,
577 WMI_EXTSCAN_GET_CAPABILITIES_CMDID,
578 WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID,
579 WMI_EXTSCAN_CONFIGURE_MAWC_CMDID,
580 WMI_SET_DHCP_SERVER_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_DHCP_OFL),
581 WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID = WMI_TLV_CMD(WMI_GRP_IPA),
582 WMI_MDNS_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL),
583 WMI_MDNS_SET_FQDN_CMDID,
584 WMI_MDNS_SET_RESPONSE_CMDID,
585 WMI_MDNS_GET_STATS_CMDID,
586 WMI_SAP_OFL_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_SAP_OFL),
587 WMI_SAP_SET_BLACKLIST_PARAM_CMDID,
588 WMI_OCB_SET_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_OCB),
589 WMI_OCB_SET_UTC_TIME_CMDID,
590 WMI_OCB_START_TIMING_ADVERT_CMDID,
591 WMI_OCB_STOP_TIMING_ADVERT_CMDID,
592 WMI_OCB_GET_TSF_TIMER_CMDID,
593 WMI_DCC_GET_STATS_CMDID,
594 WMI_DCC_CLEAR_STATS_CMDID,
595 WMI_DCC_UPDATE_NDL_CMDID,
596 WMI_SOC_SET_PCL_CMDID = WMI_TLV_CMD(WMI_GRP_SOC),
597 WMI_SOC_SET_HW_MODE_CMDID,
598 WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID,
599 WMI_SOC_SET_ANTENNA_MODE_CMDID,
600 WMI_PACKET_FILTER_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_PKT_FILTER),
601 WMI_PACKET_FILTER_ENABLE_CMDID,
602 WMI_MAWC_SENSOR_REPORT_IND_CMDID = WMI_TLV_CMD(WMI_GRP_MAWC),
603 WMI_PMF_OFFLOAD_SET_SA_QUERY_CMDID = WMI_TLV_CMD(WMI_GRP_PMF_OFFLOAD),
604 WMI_BPF_GET_CAPABILITY_CMDID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD),
605 WMI_BPF_GET_VDEV_STATS_CMDID,
606 WMI_BPF_SET_VDEV_INSTRUCTIONS_CMDID,
607 WMI_BPF_DEL_VDEV_INSTRUCTIONS_CMDID,
608 WMI_BPF_SET_VDEV_ACTIVE_MODE_CMDID,
609 WMI_MNT_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_MONITOR),
610 WMI_SET_CURRENT_COUNTRY_CMDID = WMI_TLV_CMD(WMI_GRP_REGULATORY),
611 WMI_11D_SCAN_START_CMDID,
612 WMI_11D_SCAN_STOP_CMDID,
613 WMI_SET_INIT_COUNTRY_CMDID,
614 WMI_NDI_GET_CAP_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE),
615 WMI_NDP_INITIATOR_REQ_CMDID,
616 WMI_NDP_RESPONDER_REQ_CMDID,
617 WMI_NDP_END_REQ_CMDID,
618 WMI_HW_DATA_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_HW_DATA_FILTER),
619 WMI_TWT_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_TWT),
620 WMI_TWT_DISABLE_CMDID,
621 WMI_TWT_ADD_DIALOG_CMDID,
622 WMI_TWT_DEL_DIALOG_CMDID,
623 WMI_TWT_PAUSE_DIALOG_CMDID,
624 WMI_TWT_RESUME_DIALOG_CMDID,
625 WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID =
626 WMI_TLV_CMD(WMI_GRP_SPATIAL_REUSE),
627 WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID,
628};
629
630enum wmi_tlv_event_id {
631 WMI_SERVICE_READY_EVENTID = 0x1,
632 WMI_READY_EVENTID,
633 WMI_SERVICE_AVAILABLE_EVENTID,
634 WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN),
635 WMI_PDEV_TPC_CONFIG_EVENTID = WMI_TLV_CMD(WMI_GRP_PDEV),
636 WMI_CHAN_INFO_EVENTID,
637 WMI_PHYERR_EVENTID,
638 WMI_PDEV_DUMP_EVENTID,
639 WMI_TX_PAUSE_EVENTID,
640 WMI_DFS_RADAR_EVENTID,
641 WMI_PDEV_L1SS_TRACK_EVENTID,
642 WMI_PDEV_TEMPERATURE_EVENTID,
643 WMI_SERVICE_READY_EXT_EVENTID,
644 WMI_PDEV_FIPS_EVENTID,
645 WMI_PDEV_CHANNEL_HOPPING_EVENTID,
646 WMI_PDEV_ANI_CCK_LEVEL_EVENTID,
647 WMI_PDEV_ANI_OFDM_LEVEL_EVENTID,
648 WMI_PDEV_TPC_EVENTID,
649 WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID,
650 WMI_PDEV_SET_HW_MODE_RESP_EVENTID,
651 WMI_PDEV_HW_MODE_TRANSITION_EVENTID,
652 WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID,
653 WMI_PDEV_ANTDIV_STATUS_EVENTID,
654 WMI_PDEV_CHIP_POWER_STATS_EVENTID,
655 WMI_PDEV_CHIP_POWER_SAVE_FAILURE_DETECTED_EVENTID,
656 WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID,
657 WMI_PDEV_CHECK_CAL_VERSION_EVENTID,
658 WMI_PDEV_DIV_RSSI_ANTID_EVENTID,
659 WMI_PDEV_BSS_CHAN_INFO_EVENTID,
660 WMI_PDEV_UPDATE_CTLTABLE_EVENTID,
661 WMI_PDEV_DMA_RING_CFG_RSP_EVENTID,
662 WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID,
663 WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID,
664 WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID,
665 WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID,
666 WMI_PDEV_RAP_INFO_EVENTID,
667 WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID,
668 WMI_SERVICE_READY_EXT2_EVENTID,
669 WMI_VDEV_START_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_VDEV),
670 WMI_VDEV_STOPPED_EVENTID,
671 WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID,
672 WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID,
673 WMI_VDEV_TSF_REPORT_EVENTID,
674 WMI_VDEV_DELETE_RESP_EVENTID,
675 WMI_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENTID,
676 WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENTID,
677 WMI_PEER_STA_KICKOUT_EVENTID = WMI_TLV_CMD(WMI_GRP_PEER),
678 WMI_PEER_INFO_EVENTID,
679 WMI_PEER_TX_FAIL_CNT_THR_EVENTID,
680 WMI_PEER_ESTIMATED_LINKSPEED_EVENTID,
681 WMI_PEER_STATE_EVENTID,
682 WMI_PEER_ASSOC_CONF_EVENTID,
683 WMI_PEER_DELETE_RESP_EVENTID,
684 WMI_PEER_RATECODE_LIST_EVENTID,
685 WMI_WDS_PEER_EVENTID,
686 WMI_PEER_STA_PS_STATECHG_EVENTID,
687 WMI_PEER_ANTDIV_INFO_EVENTID,
688 WMI_PEER_RESERVED0_EVENTID,
689 WMI_PEER_RESERVED1_EVENTID,
690 WMI_PEER_RESERVED2_EVENTID,
691 WMI_PEER_RESERVED3_EVENTID,
692 WMI_PEER_RESERVED4_EVENTID,
693 WMI_PEER_RESERVED5_EVENTID,
694 WMI_PEER_RESERVED6_EVENTID,
695 WMI_PEER_RESERVED7_EVENTID,
696 WMI_PEER_RESERVED8_EVENTID,
697 WMI_PEER_RESERVED9_EVENTID,
698 WMI_PEER_RESERVED10_EVENTID,
699 WMI_PEER_OPER_MODE_CHANGE_EVENTID,
700 WMI_PEER_TX_PN_RESPONSE_EVENTID,
701 WMI_PEER_CFR_CAPTURE_EVENTID,
702 WMI_PEER_CREATE_CONF_EVENTID,
703 WMI_MGMT_RX_EVENTID = WMI_TLV_CMD(WMI_GRP_MGMT),
704 WMI_HOST_SWBA_EVENTID,
705 WMI_TBTTOFFSET_UPDATE_EVENTID,
706 WMI_OFFLOAD_BCN_TX_STATUS_EVENTID,
707 WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID,
708 WMI_MGMT_TX_COMPLETION_EVENTID,
709 WMI_MGMT_TX_BUNDLE_COMPLETION_EVENTID,
710 WMI_TBTTOFFSET_EXT_UPDATE_EVENTID,
711 WMI_OFFCHAN_DATA_TX_COMPLETION_EVENTID,
712 WMI_HOST_FILS_DISCOVERY_EVENTID,
713 WMI_TX_DELBA_COMPLETE_EVENTID = WMI_TLV_CMD(WMI_GRP_BA_NEG),
714 WMI_TX_ADDBA_COMPLETE_EVENTID,
715 WMI_BA_RSP_SSN_EVENTID,
716 WMI_AGGR_STATE_TRIG_EVENTID,
717 WMI_ROAM_EVENTID = WMI_TLV_CMD(WMI_GRP_ROAM),
718 WMI_PROFILE_MATCH,
719 WMI_ROAM_SYNCH_EVENTID,
720 WMI_P2P_DISC_EVENTID = WMI_TLV_CMD(WMI_GRP_P2P),
721 WMI_P2P_NOA_EVENTID,
722 WMI_P2P_LISTEN_OFFLOAD_STOPPED_EVENTID,
723 WMI_AP_PS_EGAP_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_AP_PS),
724 WMI_PDEV_RESUME_EVENTID = WMI_TLV_CMD(WMI_GRP_SUSPEND),
725 WMI_WOW_WAKEUP_HOST_EVENTID = WMI_TLV_CMD(WMI_GRP_WOW),
726 WMI_D0_WOW_DISABLE_ACK_EVENTID,
727 WMI_WOW_INITIAL_WAKEUP_EVENTID,
728 WMI_RTT_MEASUREMENT_REPORT_EVENTID = WMI_TLV_CMD(WMI_GRP_RTT),
729 WMI_TSF_MEASUREMENT_REPORT_EVENTID,
730 WMI_RTT_ERROR_REPORT_EVENTID,
731 WMI_STATS_EXT_EVENTID = WMI_TLV_CMD(WMI_GRP_STATS),
732 WMI_IFACE_LINK_STATS_EVENTID,
733 WMI_PEER_LINK_STATS_EVENTID,
734 WMI_RADIO_LINK_STATS_EVENTID,
735 WMI_UPDATE_FW_MEM_DUMP_EVENTID,
736 WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID,
737 WMI_INST_RSSI_STATS_EVENTID,
738 WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID,
739 WMI_REPORT_STATS_EVENTID,
740 WMI_UPDATE_RCPI_EVENTID,
741 WMI_PEER_STATS_INFO_EVENTID,
742 WMI_RADIO_CHAN_STATS_EVENTID,
743 WMI_NLO_MATCH_EVENTID = WMI_TLV_CMD(WMI_GRP_NLO_OFL),
744 WMI_NLO_SCAN_COMPLETE_EVENTID,
745 WMI_APFIND_EVENTID,
746 WMI_PASSPOINT_MATCH_EVENTID,
747 WMI_GTK_OFFLOAD_STATUS_EVENTID = WMI_TLV_CMD(WMI_GRP_GTK_OFL),
748 WMI_GTK_REKEY_FAIL_EVENTID,
749 WMI_CSA_HANDLING_EVENTID = WMI_TLV_CMD(WMI_GRP_CSA_OFL),
750 WMI_CHATTER_PC_QUERY_EVENTID = WMI_TLV_CMD(WMI_GRP_CHATTER),
751 WMI_PDEV_DFS_RADAR_DETECTION_EVENTID = WMI_TLV_CMD(WMI_GRP_DFS),
752 WMI_VDEV_DFS_CAC_COMPLETE_EVENTID,
753 WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID,
754 WMI_ECHO_EVENTID = WMI_TLV_CMD(WMI_GRP_MISC),
755 WMI_PDEV_UTF_EVENTID,
756 WMI_DEBUG_MESG_EVENTID,
757 WMI_UPDATE_STATS_EVENTID,
758 WMI_DEBUG_PRINT_EVENTID,
759 WMI_DCS_INTERFERENCE_EVENTID,
760 WMI_PDEV_QVIT_EVENTID,
761 WMI_WLAN_PROFILE_DATA_EVENTID,
762 WMI_PDEV_FTM_INTG_EVENTID,
763 WMI_WLAN_FREQ_AVOID_EVENTID,
764 WMI_VDEV_GET_KEEPALIVE_EVENTID,
765 WMI_THERMAL_MGMT_EVENTID,
766 WMI_DIAG_DATA_CONTAINER_EVENTID,
767 WMI_HOST_AUTO_SHUTDOWN_EVENTID,
768 WMI_UPDATE_WHAL_MIB_STATS_EVENTID,
769 WMI_UPDATE_VDEV_RATE_STATS_EVENTID,
770 WMI_DIAG_EVENTID,
771 WMI_OCB_SET_SCHED_EVENTID,
772 WMI_DEBUG_MESG_FLUSH_COMPLETE_EVENTID,
773 WMI_RSSI_BREACH_EVENTID,
774 WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID,
775 WMI_PDEV_UTF_SCPC_EVENTID,
776 WMI_READ_DATA_FROM_FLASH_EVENTID,
777 WMI_REPORT_RX_AGGR_FAILURE_EVENTID,
778 WMI_PKGID_EVENTID,
779 WMI_GPIO_INPUT_EVENTID = WMI_TLV_CMD(WMI_GRP_GPIO),
780 WMI_UPLOADH_EVENTID,
781 WMI_CAPTUREH_EVENTID,
782 WMI_RFKILL_STATE_CHANGE_EVENTID,
783 WMI_TDLS_PEER_EVENTID = WMI_TLV_CMD(WMI_GRP_TDLS),
784 WMI_STA_SMPS_FORCE_MODE_COMPL_EVENTID = WMI_TLV_CMD(WMI_GRP_STA_SMPS),
785 WMI_BATCH_SCAN_ENABLED_EVENTID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN),
786 WMI_BATCH_SCAN_RESULT_EVENTID,
787 WMI_OEM_CAPABILITY_EVENTID = WMI_TLV_CMD(WMI_GRP_OEM),
788 WMI_OEM_MEASUREMENT_REPORT_EVENTID,
789 WMI_OEM_ERROR_REPORT_EVENTID,
790 WMI_OEM_RESPONSE_EVENTID,
791 WMI_NAN_EVENTID = WMI_TLV_CMD(WMI_GRP_NAN),
792 WMI_NAN_DISC_IFACE_CREATED_EVENTID,
793 WMI_NAN_DISC_IFACE_DELETED_EVENTID,
794 WMI_NAN_STARTED_CLUSTER_EVENTID,
795 WMI_NAN_JOINED_CLUSTER_EVENTID,
796 WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_TLV_CMD(WMI_GRP_COEX),
797 WMI_LPI_RESULT_EVENTID = WMI_TLV_CMD(WMI_GRP_LPI),
798 WMI_LPI_STATUS_EVENTID,
799 WMI_LPI_HANDOFF_EVENTID,
800 WMI_EXTSCAN_START_STOP_EVENTID = WMI_TLV_CMD(WMI_GRP_EXTSCAN),
801 WMI_EXTSCAN_OPERATION_EVENTID,
802 WMI_EXTSCAN_TABLE_USAGE_EVENTID,
803 WMI_EXTSCAN_CACHED_RESULTS_EVENTID,
804 WMI_EXTSCAN_WLAN_CHANGE_RESULTS_EVENTID,
805 WMI_EXTSCAN_HOTLIST_MATCH_EVENTID,
806 WMI_EXTSCAN_CAPABILITIES_EVENTID,
807 WMI_EXTSCAN_HOTLIST_SSID_MATCH_EVENTID,
808 WMI_MDNS_STATS_EVENTID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL),
809 WMI_SAP_OFL_ADD_STA_EVENTID = WMI_TLV_CMD(WMI_GRP_SAP_OFL),
810 WMI_SAP_OFL_DEL_STA_EVENTID,
811 WMI_OBSS_COLOR_COLLISION_DETECTION_EVENTID =
812 WMI_EVT_GRP_START_ID(WMI_GRP_OBSS_OFL),
813 WMI_OCB_SET_CONFIG_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_OCB),
814 WMI_OCB_GET_TSF_TIMER_RESP_EVENTID,
815 WMI_DCC_GET_STATS_RESP_EVENTID,
816 WMI_DCC_UPDATE_NDL_RESP_EVENTID,
817 WMI_DCC_STATS_EVENTID,
818 WMI_SOC_SET_HW_MODE_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_SOC),
819 WMI_SOC_HW_MODE_TRANSITION_EVENTID,
820 WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID,
821 WMI_MAWC_ENABLE_SENSOR_EVENTID = WMI_TLV_CMD(WMI_GRP_MAWC),
822 WMI_BPF_CAPABILIY_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD),
823 WMI_BPF_VDEV_STATS_INFO_EVENTID,
824 WMI_RMC_NEW_LEADER_EVENTID = WMI_TLV_CMD(WMI_GRP_RMC),
825 WMI_REG_CHAN_LIST_CC_EVENTID = WMI_TLV_CMD(WMI_GRP_REGULATORY),
826 WMI_11D_NEW_COUNTRY_EVENTID,
827 WMI_REG_CHAN_LIST_CC_EXT_EVENTID,
828 WMI_NDI_CAP_RSP_EVENTID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE),
829 WMI_NDP_INITIATOR_RSP_EVENTID,
830 WMI_NDP_RESPONDER_RSP_EVENTID,
831 WMI_NDP_END_RSP_EVENTID,
832 WMI_NDP_INDICATION_EVENTID,
833 WMI_NDP_CONFIRM_EVENTID,
834 WMI_NDP_END_INDICATION_EVENTID,
835
836 WMI_TWT_ENABLE_EVENTID = WMI_TLV_CMD(WMI_GRP_TWT),
837 WMI_TWT_DISABLE_EVENTID,
838 WMI_TWT_ADD_DIALOG_EVENTID,
839 WMI_TWT_DEL_DIALOG_EVENTID,
840 WMI_TWT_PAUSE_DIALOG_EVENTID,
841 WMI_TWT_RESUME_DIALOG_EVENTID,
842};
843
844enum wmi_tlv_pdev_param {
845 WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1,
846 WMI_PDEV_PARAM_RX_CHAIN_MASK,
847 WMI_PDEV_PARAM_TXPOWER_LIMIT2G,
848 WMI_PDEV_PARAM_TXPOWER_LIMIT5G,
849 WMI_PDEV_PARAM_TXPOWER_SCALE,
850 WMI_PDEV_PARAM_BEACON_GEN_MODE,
851 WMI_PDEV_PARAM_BEACON_TX_MODE,
852 WMI_PDEV_PARAM_RESMGR_OFFCHAN_MODE,
853 WMI_PDEV_PARAM_PROTECTION_MODE,
854 WMI_PDEV_PARAM_DYNAMIC_BW,
855 WMI_PDEV_PARAM_NON_AGG_SW_RETRY_TH,
856 WMI_PDEV_PARAM_AGG_SW_RETRY_TH,
857 WMI_PDEV_PARAM_STA_KICKOUT_TH,
858 WMI_PDEV_PARAM_AC_AGGRSIZE_SCALING,
859 WMI_PDEV_PARAM_LTR_ENABLE,
860 WMI_PDEV_PARAM_LTR_AC_LATENCY_BE,
861 WMI_PDEV_PARAM_LTR_AC_LATENCY_BK,
862 WMI_PDEV_PARAM_LTR_AC_LATENCY_VI,
863 WMI_PDEV_PARAM_LTR_AC_LATENCY_VO,
864 WMI_PDEV_PARAM_LTR_AC_LATENCY_TIMEOUT,
865 WMI_PDEV_PARAM_LTR_SLEEP_OVERRIDE,
866 WMI_PDEV_PARAM_LTR_RX_OVERRIDE,
867 WMI_PDEV_PARAM_LTR_TX_ACTIVITY_TIMEOUT,
868 WMI_PDEV_PARAM_L1SS_ENABLE,
869 WMI_PDEV_PARAM_DSLEEP_ENABLE,
870 WMI_PDEV_PARAM_PCIELP_TXBUF_FLUSH,
871 WMI_PDEV_PARAM_PCIELP_TXBUF_WATERMARK,
872 WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_EN,
873 WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_VALUE,
874 WMI_PDEV_PARAM_PDEV_STATS_UPDATE_PERIOD,
875 WMI_PDEV_PARAM_VDEV_STATS_UPDATE_PERIOD,
876 WMI_PDEV_PARAM_PEER_STATS_UPDATE_PERIOD,
877 WMI_PDEV_PARAM_BCNFLT_STATS_UPDATE_PERIOD,
878 WMI_PDEV_PARAM_PMF_QOS,
879 WMI_PDEV_PARAM_ARP_AC_OVERRIDE,
880 WMI_PDEV_PARAM_DCS,
881 WMI_PDEV_PARAM_ANI_ENABLE,
882 WMI_PDEV_PARAM_ANI_POLL_PERIOD,
883 WMI_PDEV_PARAM_ANI_LISTEN_PERIOD,
884 WMI_PDEV_PARAM_ANI_OFDM_LEVEL,
885 WMI_PDEV_PARAM_ANI_CCK_LEVEL,
886 WMI_PDEV_PARAM_DYNTXCHAIN,
887 WMI_PDEV_PARAM_PROXY_STA,
888 WMI_PDEV_PARAM_IDLE_PS_CONFIG,
889 WMI_PDEV_PARAM_POWER_GATING_SLEEP,
890 WMI_PDEV_PARAM_RFKILL_ENABLE,
891 WMI_PDEV_PARAM_BURST_DUR,
892 WMI_PDEV_PARAM_BURST_ENABLE,
893 WMI_PDEV_PARAM_HW_RFKILL_CONFIG,
894 WMI_PDEV_PARAM_LOW_POWER_RF_ENABLE,
895 WMI_PDEV_PARAM_L1SS_TRACK,
896 WMI_PDEV_PARAM_HYST_EN,
897 WMI_PDEV_PARAM_POWER_COLLAPSE_ENABLE,
898 WMI_PDEV_PARAM_LED_SYS_STATE,
899 WMI_PDEV_PARAM_LED_ENABLE,
900 WMI_PDEV_PARAM_AUDIO_OVER_WLAN_LATENCY,
901 WMI_PDEV_PARAM_AUDIO_OVER_WLAN_ENABLE,
902 WMI_PDEV_PARAM_WHAL_MIB_STATS_UPDATE_ENABLE,
903 WMI_PDEV_PARAM_VDEV_RATE_STATS_UPDATE_PERIOD,
904 WMI_PDEV_PARAM_CTS_CBW,
905 WMI_PDEV_PARAM_WNTS_CONFIG,
906 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_ENABLE,
907 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_MIN_SLEEP_SLOP,
908 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_INC_DEC_STEP,
909 WMI_PDEV_PARAM_EARLY_RX_FIX_SLEEP_SLOP,
910 WMI_PDEV_PARAM_BMISS_BASED_ADAPTIVE_BTO_ENABLE,
911 WMI_PDEV_PARAM_BMISS_BTO_MIN_BCN_TIMEOUT,
912 WMI_PDEV_PARAM_BMISS_BTO_INC_DEC_STEP,
913 WMI_PDEV_PARAM_BTO_FIX_BCN_TIMEOUT,
914 WMI_PDEV_PARAM_CE_BASED_ADAPTIVE_BTO_ENABLE,
915 WMI_PDEV_PARAM_CE_BTO_COMBO_CE_VALUE,
916 WMI_PDEV_PARAM_TX_CHAIN_MASK_2G,
917 WMI_PDEV_PARAM_RX_CHAIN_MASK_2G,
918 WMI_PDEV_PARAM_TX_CHAIN_MASK_5G,
919 WMI_PDEV_PARAM_RX_CHAIN_MASK_5G,
920 WMI_PDEV_PARAM_TX_CHAIN_MASK_CCK,
921 WMI_PDEV_PARAM_TX_CHAIN_MASK_1SS,
922 WMI_PDEV_PARAM_CTS2SELF_FOR_P2P_GO_CONFIG,
923 WMI_PDEV_PARAM_TXPOWER_DECR_DB,
924 WMI_PDEV_PARAM_AGGR_BURST,
925 WMI_PDEV_PARAM_RX_DECAP_MODE,
926 WMI_PDEV_PARAM_FAST_CHANNEL_RESET,
927 WMI_PDEV_PARAM_SMART_ANTENNA_DEFAULT_ANTENNA,
928 WMI_PDEV_PARAM_ANTENNA_GAIN,
929 WMI_PDEV_PARAM_RX_FILTER,
930 WMI_PDEV_SET_MCAST_TO_UCAST_TID,
931 WMI_PDEV_PARAM_PROXY_STA_MODE,
932 WMI_PDEV_PARAM_SET_MCAST2UCAST_MODE,
933 WMI_PDEV_PARAM_SET_MCAST2UCAST_BUFFER,
934 WMI_PDEV_PARAM_REMOVE_MCAST2UCAST_BUFFER,
935 WMI_PDEV_PEER_STA_PS_STATECHG_ENABLE,
936 WMI_PDEV_PARAM_IGMPMLD_AC_OVERRIDE,
937 WMI_PDEV_PARAM_BLOCK_INTERBSS,
938 WMI_PDEV_PARAM_SET_DISABLE_RESET_CMDID,
939 WMI_PDEV_PARAM_SET_MSDU_TTL_CMDID,
940 WMI_PDEV_PARAM_SET_PPDU_DURATION_CMDID,
941 WMI_PDEV_PARAM_TXBF_SOUND_PERIOD_CMDID,
942 WMI_PDEV_PARAM_SET_PROMISC_MODE_CMDID,
943 WMI_PDEV_PARAM_SET_BURST_MODE_CMDID,
944 WMI_PDEV_PARAM_EN_STATS,
945 WMI_PDEV_PARAM_MU_GROUP_POLICY,
946 WMI_PDEV_PARAM_NOISE_DETECTION,
947 WMI_PDEV_PARAM_NOISE_THRESHOLD,
948 WMI_PDEV_PARAM_DPD_ENABLE,
949 WMI_PDEV_PARAM_SET_MCAST_BCAST_ECHO,
950 WMI_PDEV_PARAM_ATF_STRICT_SCH,
951 WMI_PDEV_PARAM_ATF_SCHED_DURATION,
952 WMI_PDEV_PARAM_ANT_PLZN,
953 WMI_PDEV_PARAM_MGMT_RETRY_LIMIT,
954 WMI_PDEV_PARAM_SENSITIVITY_LEVEL,
955 WMI_PDEV_PARAM_SIGNED_TXPOWER_2G,
956 WMI_PDEV_PARAM_SIGNED_TXPOWER_5G,
957 WMI_PDEV_PARAM_ENABLE_PER_TID_AMSDU,
958 WMI_PDEV_PARAM_ENABLE_PER_TID_AMPDU,
959 WMI_PDEV_PARAM_CCA_THRESHOLD,
960 WMI_PDEV_PARAM_RTS_FIXED_RATE,
961 WMI_PDEV_PARAM_PDEV_RESET,
962 WMI_PDEV_PARAM_WAPI_MBSSID_OFFSET,
963 WMI_PDEV_PARAM_ARP_DBG_SRCADDR,
964 WMI_PDEV_PARAM_ARP_DBG_DSTADDR,
965 WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCH,
966 WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCALING_FACTOR,
967 WMI_PDEV_PARAM_CUST_TXPOWER_SCALE,
968 WMI_PDEV_PARAM_ATF_DYNAMIC_ENABLE,
969 WMI_PDEV_PARAM_CTRL_RETRY_LIMIT,
970 WMI_PDEV_PARAM_PROPAGATION_DELAY,
971 WMI_PDEV_PARAM_ENA_ANT_DIV,
972 WMI_PDEV_PARAM_FORCE_CHAIN_ANT,
973 WMI_PDEV_PARAM_ANT_DIV_SELFTEST,
974 WMI_PDEV_PARAM_ANT_DIV_SELFTEST_INTVL,
975 WMI_PDEV_PARAM_STATS_OBSERVATION_PERIOD,
976 WMI_PDEV_PARAM_TX_PPDU_DELAY_BIN_SIZE_MS,
977 WMI_PDEV_PARAM_TX_PPDU_DELAY_ARRAY_LEN,
978 WMI_PDEV_PARAM_TX_MPDU_AGGR_ARRAY_LEN,
979 WMI_PDEV_PARAM_RX_MPDU_AGGR_ARRAY_LEN,
980 WMI_PDEV_PARAM_TX_SCH_DELAY,
981 WMI_PDEV_PARAM_ENABLE_RTS_SIFS_BURSTING,
982 WMI_PDEV_PARAM_MAX_MPDUS_IN_AMPDU,
983 WMI_PDEV_PARAM_PEER_STATS_INFO_ENABLE,
984 WMI_PDEV_PARAM_FAST_PWR_TRANSITION,
985 WMI_PDEV_PARAM_RADIO_CHAN_STATS_ENABLE,
986 WMI_PDEV_PARAM_RADIO_DIAGNOSIS_ENABLE,
987 WMI_PDEV_PARAM_MESH_MCAST_ENABLE,
988 WMI_PDEV_PARAM_SET_CMD_OBSS_PD_THRESHOLD = 0xbc,
989 WMI_PDEV_PARAM_SET_CMD_OBSS_PD_PER_AC = 0xbe,
990 WMI_PDEV_PARAM_ENABLE_SR_PROHIBIT = 0xc6,
991};
992
993enum wmi_tlv_vdev_param {
994 WMI_VDEV_PARAM_RTS_THRESHOLD = 0x1,
995 WMI_VDEV_PARAM_FRAGMENTATION_THRESHOLD,
996 WMI_VDEV_PARAM_BEACON_INTERVAL,
997 WMI_VDEV_PARAM_LISTEN_INTERVAL,
998 WMI_VDEV_PARAM_MULTICAST_RATE,
999 WMI_VDEV_PARAM_MGMT_TX_RATE,
1000 WMI_VDEV_PARAM_SLOT_TIME,
1001 WMI_VDEV_PARAM_PREAMBLE,
1002 WMI_VDEV_PARAM_SWBA_TIME,
1003 WMI_VDEV_STATS_UPDATE_PERIOD,
1004 WMI_VDEV_PWRSAVE_AGEOUT_TIME,
1005 WMI_VDEV_HOST_SWBA_INTERVAL,
1006 WMI_VDEV_PARAM_DTIM_PERIOD,
1007 WMI_VDEV_OC_SCHEDULER_AIR_TIME_LIMIT,
1008 WMI_VDEV_PARAM_WDS,
1009 WMI_VDEV_PARAM_ATIM_WINDOW,
1010 WMI_VDEV_PARAM_BMISS_COUNT_MAX,
1011 WMI_VDEV_PARAM_BMISS_FIRST_BCNT,
1012 WMI_VDEV_PARAM_BMISS_FINAL_BCNT,
1013 WMI_VDEV_PARAM_FEATURE_WMM,
1014 WMI_VDEV_PARAM_CHWIDTH,
1015 WMI_VDEV_PARAM_CHEXTOFFSET,
1016 WMI_VDEV_PARAM_DISABLE_HTPROTECTION,
1017 WMI_VDEV_PARAM_STA_QUICKKICKOUT,
1018 WMI_VDEV_PARAM_MGMT_RATE,
1019 WMI_VDEV_PARAM_PROTECTION_MODE,
1020 WMI_VDEV_PARAM_FIXED_RATE,
1021 WMI_VDEV_PARAM_SGI,
1022 WMI_VDEV_PARAM_LDPC,
1023 WMI_VDEV_PARAM_TX_STBC,
1024 WMI_VDEV_PARAM_RX_STBC,
1025 WMI_VDEV_PARAM_INTRA_BSS_FWD,
1026 WMI_VDEV_PARAM_DEF_KEYID,
1027 WMI_VDEV_PARAM_NSS,
1028 WMI_VDEV_PARAM_BCAST_DATA_RATE,
1029 WMI_VDEV_PARAM_MCAST_DATA_RATE,
1030 WMI_VDEV_PARAM_MCAST_INDICATE,
1031 WMI_VDEV_PARAM_DHCP_INDICATE,
1032 WMI_VDEV_PARAM_UNKNOWN_DEST_INDICATE,
1033 WMI_VDEV_PARAM_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS,
1034 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS,
1035 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS,
1036 WMI_VDEV_PARAM_AP_ENABLE_NAWDS,
1037 WMI_VDEV_PARAM_ENABLE_RTSCTS,
1038 WMI_VDEV_PARAM_TXBF,
1039 WMI_VDEV_PARAM_PACKET_POWERSAVE,
1040 WMI_VDEV_PARAM_DROP_UNENCRY,
1041 WMI_VDEV_PARAM_TX_ENCAP_TYPE,
1042 WMI_VDEV_PARAM_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS,
1043 WMI_VDEV_PARAM_EARLY_RX_ADJUST_ENABLE,
1044 WMI_VDEV_PARAM_EARLY_RX_TGT_BMISS_NUM,
1045 WMI_VDEV_PARAM_EARLY_RX_BMISS_SAMPLE_CYCLE,
1046 WMI_VDEV_PARAM_EARLY_RX_SLOP_STEP,
1047 WMI_VDEV_PARAM_EARLY_RX_INIT_SLOP,
1048 WMI_VDEV_PARAM_EARLY_RX_ADJUST_PAUSE,
1049 WMI_VDEV_PARAM_TX_PWRLIMIT,
1050 WMI_VDEV_PARAM_SNR_NUM_FOR_CAL,
1051 WMI_VDEV_PARAM_ROAM_FW_OFFLOAD,
1052 WMI_VDEV_PARAM_ENABLE_RMC,
1053 WMI_VDEV_PARAM_IBSS_MAX_BCN_LOST_MS,
1054 WMI_VDEV_PARAM_MAX_RATE,
1055 WMI_VDEV_PARAM_EARLY_RX_DRIFT_SAMPLE,
1056 WMI_VDEV_PARAM_SET_IBSS_TX_FAIL_CNT_THR,
1057 WMI_VDEV_PARAM_EBT_RESYNC_TIMEOUT,
1058 WMI_VDEV_PARAM_AGGR_TRIG_EVENT_ENABLE,
1059 WMI_VDEV_PARAM_IS_IBSS_POWER_SAVE_ALLOWED,
1060 WMI_VDEV_PARAM_IS_POWER_COLLAPSE_ALLOWED,
1061 WMI_VDEV_PARAM_IS_AWAKE_ON_TXRX_ENABLED,
1062 WMI_VDEV_PARAM_INACTIVITY_CNT,
1063 WMI_VDEV_PARAM_TXSP_END_INACTIVITY_TIME_MS,
1064 WMI_VDEV_PARAM_DTIM_POLICY,
1065 WMI_VDEV_PARAM_IBSS_PS_WARMUP_TIME_SECS,
1066 WMI_VDEV_PARAM_IBSS_PS_1RX_CHAIN_IN_ATIM_WINDOW_ENABLE,
1067 WMI_VDEV_PARAM_RX_LEAK_WINDOW,
1068 WMI_VDEV_PARAM_STATS_AVG_FACTOR,
1069 WMI_VDEV_PARAM_DISCONNECT_TH,
1070 WMI_VDEV_PARAM_RTSCTS_RATE,
1071 WMI_VDEV_PARAM_MCC_RTSCTS_PROTECTION_ENABLE,
1072 WMI_VDEV_PARAM_MCC_BROADCAST_PROBE_ENABLE,
1073 WMI_VDEV_PARAM_TXPOWER_SCALE,
1074 WMI_VDEV_PARAM_TXPOWER_SCALE_DECR_DB,
1075 WMI_VDEV_PARAM_MCAST2UCAST_SET,
1076 WMI_VDEV_PARAM_RC_NUM_RETRIES,
1077 WMI_VDEV_PARAM_CABQ_MAXDUR,
1078 WMI_VDEV_PARAM_MFPTEST_SET,
1079 WMI_VDEV_PARAM_RTS_FIXED_RATE,
1080 WMI_VDEV_PARAM_VHT_SGIMASK,
1081 WMI_VDEV_PARAM_VHT80_RATEMASK,
1082 WMI_VDEV_PARAM_PROXY_STA,
1083 WMI_VDEV_PARAM_VIRTUAL_CELL_MODE,
1084 WMI_VDEV_PARAM_RX_DECAP_TYPE,
1085 WMI_VDEV_PARAM_BW_NSS_RATEMASK,
1086 WMI_VDEV_PARAM_SENSOR_AP,
1087 WMI_VDEV_PARAM_BEACON_RATE,
1088 WMI_VDEV_PARAM_DTIM_ENABLE_CTS,
1089 WMI_VDEV_PARAM_STA_KICKOUT,
1090 WMI_VDEV_PARAM_CAPABILITIES,
1091 WMI_VDEV_PARAM_TSF_INCREMENT,
1092 WMI_VDEV_PARAM_AMPDU_PER_AC,
1093 WMI_VDEV_PARAM_RX_FILTER,
1094 WMI_VDEV_PARAM_MGMT_TX_POWER,
1095 WMI_VDEV_PARAM_NON_AGG_SW_RETRY_TH,
1096 WMI_VDEV_PARAM_AGG_SW_RETRY_TH,
1097 WMI_VDEV_PARAM_DISABLE_DYN_BW_RTS,
1098 WMI_VDEV_PARAM_ATF_SSID_SCHED_POLICY,
1099 WMI_VDEV_PARAM_HE_DCM,
1100 WMI_VDEV_PARAM_HE_RANGE_EXT,
1101 WMI_VDEV_PARAM_ENABLE_BCAST_PROBE_RESPONSE,
1102 WMI_VDEV_PARAM_FILS_MAX_CHANNEL_GUARD_TIME,
1103 WMI_VDEV_PARAM_HE_LTF = 0x74,
1104 WMI_VDEV_PARAM_ENABLE_DISABLE_RTT_RESPONDER_ROLE = 0x7d,
1105 WMI_VDEV_PARAM_BA_MODE = 0x7e,
1106 WMI_VDEV_PARAM_AUTORATE_MISC_CFG = 0x80,
1107 WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE = 0x87,
1108 WMI_VDEV_PARAM_6GHZ_PARAMS = 0x99,
1109 WMI_VDEV_PARAM_PROTOTYPE = 0x8000,
1110 WMI_VDEV_PARAM_BSS_COLOR,
1111 WMI_VDEV_PARAM_SET_HEMU_MODE,
1112 WMI_VDEV_PARAM_HEOPS_0_31 = 0x8003,
1113};
1114
1115enum wmi_tlv_peer_flags {
1116 WMI_PEER_AUTH = 0x00000001,
1117 WMI_PEER_QOS = 0x00000002,
1118 WMI_PEER_NEED_PTK_4_WAY = 0x00000004,
1119 WMI_PEER_NEED_GTK_2_WAY = 0x00000010,
1120 WMI_PEER_HE = 0x00000400,
1121 WMI_PEER_APSD = 0x00000800,
1122 WMI_PEER_HT = 0x00001000,
1123 WMI_PEER_40MHZ = 0x00002000,
1124 WMI_PEER_STBC = 0x00008000,
1125 WMI_PEER_LDPC = 0x00010000,
1126 WMI_PEER_DYN_MIMOPS = 0x00020000,
1127 WMI_PEER_STATIC_MIMOPS = 0x00040000,
1128 WMI_PEER_SPATIAL_MUX = 0x00200000,
1129 WMI_PEER_TWT_REQ = 0x00400000,
1130 WMI_PEER_TWT_RESP = 0x00800000,
1131 WMI_PEER_VHT = 0x02000000,
1132 WMI_PEER_80MHZ = 0x04000000,
1133 WMI_PEER_PMF = 0x08000000,
1134 WMI_PEER_IS_P2P_CAPABLE = 0x20000000,
1135 WMI_PEER_160MHZ = 0x40000000,
1136 WMI_PEER_SAFEMODE_EN = 0x80000000,
1137};
1138
1139/** Enum list of TLV Tags for each parameter structure type. */
1140enum wmi_tlv_tag {
1141 WMI_TAG_LAST_RESERVED = 15,
1142 WMI_TAG_FIRST_ARRAY_ENUM,
1143 WMI_TAG_ARRAY_UINT32 = WMI_TAG_FIRST_ARRAY_ENUM,
1144 WMI_TAG_ARRAY_BYTE,
1145 WMI_TAG_ARRAY_STRUCT,
1146 WMI_TAG_ARRAY_FIXED_STRUCT,
1147 WMI_TAG_LAST_ARRAY_ENUM = 31,
1148 WMI_TAG_SERVICE_READY_EVENT,
1149 WMI_TAG_HAL_REG_CAPABILITIES,
1150 WMI_TAG_WLAN_HOST_MEM_REQ,
1151 WMI_TAG_READY_EVENT,
1152 WMI_TAG_SCAN_EVENT,
1153 WMI_TAG_PDEV_TPC_CONFIG_EVENT,
1154 WMI_TAG_CHAN_INFO_EVENT,
1155 WMI_TAG_COMB_PHYERR_RX_HDR,
1156 WMI_TAG_VDEV_START_RESPONSE_EVENT,
1157 WMI_TAG_VDEV_STOPPED_EVENT,
1158 WMI_TAG_VDEV_INSTALL_KEY_COMPLETE_EVENT,
1159 WMI_TAG_PEER_STA_KICKOUT_EVENT,
1160 WMI_TAG_MGMT_RX_HDR,
1161 WMI_TAG_TBTT_OFFSET_EVENT,
1162 WMI_TAG_TX_DELBA_COMPLETE_EVENT,
1163 WMI_TAG_TX_ADDBA_COMPLETE_EVENT,
1164 WMI_TAG_ROAM_EVENT,
1165 WMI_TAG_WOW_EVENT_INFO,
1166 WMI_TAG_WOW_EVENT_INFO_SECTION_BITMAP,
1167 WMI_TAG_RTT_EVENT_HEADER,
1168 WMI_TAG_RTT_ERROR_REPORT_EVENT,
1169 WMI_TAG_RTT_MEAS_EVENT,
1170 WMI_TAG_ECHO_EVENT,
1171 WMI_TAG_FTM_INTG_EVENT,
1172 WMI_TAG_VDEV_GET_KEEPALIVE_EVENT,
1173 WMI_TAG_GPIO_INPUT_EVENT,
1174 WMI_TAG_CSA_EVENT,
1175 WMI_TAG_GTK_OFFLOAD_STATUS_EVENT,
1176 WMI_TAG_IGTK_INFO,
1177 WMI_TAG_DCS_INTERFERENCE_EVENT,
1178 WMI_TAG_ATH_DCS_CW_INT,
1179 WMI_TAG_WLAN_DCS_CW_INT = /* ALIAS */
1180 WMI_TAG_ATH_DCS_CW_INT,
1181 WMI_TAG_ATH_DCS_WLAN_INT_STAT,
1182 WMI_TAG_WLAN_DCS_IM_TGT_STATS_T = /* ALIAS */
1183 WMI_TAG_ATH_DCS_WLAN_INT_STAT,
1184 WMI_TAG_WLAN_PROFILE_CTX_T,
1185 WMI_TAG_WLAN_PROFILE_T,
1186 WMI_TAG_PDEV_QVIT_EVENT,
1187 WMI_TAG_HOST_SWBA_EVENT,
1188 WMI_TAG_TIM_INFO,
1189 WMI_TAG_P2P_NOA_INFO,
1190 WMI_TAG_STATS_EVENT,
1191 WMI_TAG_AVOID_FREQ_RANGES_EVENT,
1192 WMI_TAG_AVOID_FREQ_RANGE_DESC,
1193 WMI_TAG_GTK_REKEY_FAIL_EVENT,
1194 WMI_TAG_INIT_CMD,
1195 WMI_TAG_RESOURCE_CONFIG,
1196 WMI_TAG_WLAN_HOST_MEMORY_CHUNK,
1197 WMI_TAG_START_SCAN_CMD,
1198 WMI_TAG_STOP_SCAN_CMD,
1199 WMI_TAG_SCAN_CHAN_LIST_CMD,
1200 WMI_TAG_CHANNEL,
1201 WMI_TAG_PDEV_SET_REGDOMAIN_CMD,
1202 WMI_TAG_PDEV_SET_PARAM_CMD,
1203 WMI_TAG_PDEV_SET_WMM_PARAMS_CMD,
1204 WMI_TAG_WMM_PARAMS,
1205 WMI_TAG_PDEV_SET_QUIET_CMD,
1206 WMI_TAG_VDEV_CREATE_CMD,
1207 WMI_TAG_VDEV_DELETE_CMD,
1208 WMI_TAG_VDEV_START_REQUEST_CMD,
1209 WMI_TAG_P2P_NOA_DESCRIPTOR,
1210 WMI_TAG_P2P_GO_SET_BEACON_IE,
1211 WMI_TAG_GTK_OFFLOAD_CMD,
1212 WMI_TAG_VDEV_UP_CMD,
1213 WMI_TAG_VDEV_STOP_CMD,
1214 WMI_TAG_VDEV_DOWN_CMD,
1215 WMI_TAG_VDEV_SET_PARAM_CMD,
1216 WMI_TAG_VDEV_INSTALL_KEY_CMD,
1217 WMI_TAG_PEER_CREATE_CMD,
1218 WMI_TAG_PEER_DELETE_CMD,
1219 WMI_TAG_PEER_FLUSH_TIDS_CMD,
1220 WMI_TAG_PEER_SET_PARAM_CMD,
1221 WMI_TAG_PEER_ASSOC_COMPLETE_CMD,
1222 WMI_TAG_VHT_RATE_SET,
1223 WMI_TAG_BCN_TMPL_CMD,
1224 WMI_TAG_PRB_TMPL_CMD,
1225 WMI_TAG_BCN_PRB_INFO,
1226 WMI_TAG_PEER_TID_ADDBA_CMD,
1227 WMI_TAG_PEER_TID_DELBA_CMD,
1228 WMI_TAG_STA_POWERSAVE_MODE_CMD,
1229 WMI_TAG_STA_POWERSAVE_PARAM_CMD,
1230 WMI_TAG_STA_DTIM_PS_METHOD_CMD,
1231 WMI_TAG_ROAM_SCAN_MODE,
1232 WMI_TAG_ROAM_SCAN_RSSI_THRESHOLD,
1233 WMI_TAG_ROAM_SCAN_PERIOD,
1234 WMI_TAG_ROAM_SCAN_RSSI_CHANGE_THRESHOLD,
1235 WMI_TAG_PDEV_SUSPEND_CMD,
1236 WMI_TAG_PDEV_RESUME_CMD,
1237 WMI_TAG_ADD_BCN_FILTER_CMD,
1238 WMI_TAG_RMV_BCN_FILTER_CMD,
1239 WMI_TAG_WOW_ENABLE_CMD,
1240 WMI_TAG_WOW_HOSTWAKEUP_FROM_SLEEP_CMD,
1241 WMI_TAG_STA_UAPSD_AUTO_TRIG_CMD,
1242 WMI_TAG_STA_UAPSD_AUTO_TRIG_PARAM,
1243 WMI_TAG_SET_ARP_NS_OFFLOAD_CMD,
1244 WMI_TAG_ARP_OFFLOAD_TUPLE,
1245 WMI_TAG_NS_OFFLOAD_TUPLE,
1246 WMI_TAG_FTM_INTG_CMD,
1247 WMI_TAG_STA_KEEPALIVE_CMD,
1248 WMI_TAG_STA_KEEPALIVE_ARP_RESPONSE,
1249 WMI_TAG_P2P_SET_VENDOR_IE_DATA_CMD,
1250 WMI_TAG_AP_PS_PEER_CMD,
1251 WMI_TAG_PEER_RATE_RETRY_SCHED_CMD,
1252 WMI_TAG_WLAN_PROFILE_TRIGGER_CMD,
1253 WMI_TAG_WLAN_PROFILE_SET_HIST_INTVL_CMD,
1254 WMI_TAG_WLAN_PROFILE_GET_PROF_DATA_CMD,
1255 WMI_TAG_WLAN_PROFILE_ENABLE_PROFILE_ID_CMD,
1256 WMI_TAG_WOW_DEL_PATTERN_CMD,
1257 WMI_TAG_WOW_ADD_DEL_EVT_CMD,
1258 WMI_TAG_RTT_MEASREQ_HEAD,
1259 WMI_TAG_RTT_MEASREQ_BODY,
1260 WMI_TAG_RTT_TSF_CMD,
1261 WMI_TAG_VDEV_SPECTRAL_CONFIGURE_CMD,
1262 WMI_TAG_VDEV_SPECTRAL_ENABLE_CMD,
1263 WMI_TAG_REQUEST_STATS_CMD,
1264 WMI_TAG_NLO_CONFIG_CMD,
1265 WMI_TAG_NLO_CONFIGURED_PARAMETERS,
1266 WMI_TAG_CSA_OFFLOAD_ENABLE_CMD,
1267 WMI_TAG_CSA_OFFLOAD_CHANSWITCH_CMD,
1268 WMI_TAG_CHATTER_SET_MODE_CMD,
1269 WMI_TAG_ECHO_CMD,
1270 WMI_TAG_VDEV_SET_KEEPALIVE_CMD,
1271 WMI_TAG_VDEV_GET_KEEPALIVE_CMD,
1272 WMI_TAG_FORCE_FW_HANG_CMD,
1273 WMI_TAG_GPIO_CONFIG_CMD,
1274 WMI_TAG_GPIO_OUTPUT_CMD,
1275 WMI_TAG_PEER_ADD_WDS_ENTRY_CMD,
1276 WMI_TAG_PEER_REMOVE_WDS_ENTRY_CMD,
1277 WMI_TAG_BCN_TX_HDR,
1278 WMI_TAG_BCN_SEND_FROM_HOST_CMD,
1279 WMI_TAG_MGMT_TX_HDR,
1280 WMI_TAG_ADDBA_CLEAR_RESP_CMD,
1281 WMI_TAG_ADDBA_SEND_CMD,
1282 WMI_TAG_DELBA_SEND_CMD,
1283 WMI_TAG_ADDBA_SETRESPONSE_CMD,
1284 WMI_TAG_SEND_SINGLEAMSDU_CMD,
1285 WMI_TAG_PDEV_PKTLOG_ENABLE_CMD,
1286 WMI_TAG_PDEV_PKTLOG_DISABLE_CMD,
1287 WMI_TAG_PDEV_SET_HT_IE_CMD,
1288 WMI_TAG_PDEV_SET_VHT_IE_CMD,
1289 WMI_TAG_PDEV_SET_DSCP_TID_MAP_CMD,
1290 WMI_TAG_PDEV_GREEN_AP_PS_ENABLE_CMD,
1291 WMI_TAG_PDEV_GET_TPC_CONFIG_CMD,
1292 WMI_TAG_PDEV_SET_BASE_MACADDR_CMD,
1293 WMI_TAG_PEER_MCAST_GROUP_CMD,
1294 WMI_TAG_ROAM_AP_PROFILE,
1295 WMI_TAG_AP_PROFILE,
1296 WMI_TAG_SCAN_SCH_PRIORITY_TABLE_CMD,
1297 WMI_TAG_PDEV_DFS_ENABLE_CMD,
1298 WMI_TAG_PDEV_DFS_DISABLE_CMD,
1299 WMI_TAG_WOW_ADD_PATTERN_CMD,
1300 WMI_TAG_WOW_BITMAP_PATTERN_T,
1301 WMI_TAG_WOW_IPV4_SYNC_PATTERN_T,
1302 WMI_TAG_WOW_IPV6_SYNC_PATTERN_T,
1303 WMI_TAG_WOW_MAGIC_PATTERN_CMD,
1304 WMI_TAG_SCAN_UPDATE_REQUEST_CMD,
1305 WMI_TAG_CHATTER_PKT_COALESCING_FILTER,
1306 WMI_TAG_CHATTER_COALESCING_ADD_FILTER_CMD,
1307 WMI_TAG_CHATTER_COALESCING_DELETE_FILTER_CMD,
1308 WMI_TAG_CHATTER_COALESCING_QUERY_CMD,
1309 WMI_TAG_TXBF_CMD,
1310 WMI_TAG_DEBUG_LOG_CONFIG_CMD,
1311 WMI_TAG_NLO_EVENT,
1312 WMI_TAG_CHATTER_QUERY_REPLY_EVENT,
1313 WMI_TAG_UPLOAD_H_HDR,
1314 WMI_TAG_CAPTURE_H_EVENT_HDR,
1315 WMI_TAG_VDEV_WNM_SLEEPMODE_CMD,
1316 WMI_TAG_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD,
1317 WMI_TAG_VDEV_WMM_ADDTS_CMD,
1318 WMI_TAG_VDEV_WMM_DELTS_CMD,
1319 WMI_TAG_VDEV_SET_WMM_PARAMS_CMD,
1320 WMI_TAG_TDLS_SET_STATE_CMD,
1321 WMI_TAG_TDLS_PEER_UPDATE_CMD,
1322 WMI_TAG_TDLS_PEER_EVENT,
1323 WMI_TAG_TDLS_PEER_CAPABILITIES,
1324 WMI_TAG_VDEV_MCC_SET_TBTT_MODE_CMD,
1325 WMI_TAG_ROAM_CHAN_LIST,
1326 WMI_TAG_VDEV_MCC_BCN_INTVL_CHANGE_EVENT,
1327 WMI_TAG_RESMGR_ADAPTIVE_OCS_ENABLE_DISABLE_CMD,
1328 WMI_TAG_RESMGR_SET_CHAN_TIME_QUOTA_CMD,
1329 WMI_TAG_RESMGR_SET_CHAN_LATENCY_CMD,
1330 WMI_TAG_BA_REQ_SSN_CMD,
1331 WMI_TAG_BA_RSP_SSN_EVENT,
1332 WMI_TAG_STA_SMPS_FORCE_MODE_CMD,
1333 WMI_TAG_SET_MCASTBCAST_FILTER_CMD,
1334 WMI_TAG_P2P_SET_OPPPS_CMD,
1335 WMI_TAG_P2P_SET_NOA_CMD,
1336 WMI_TAG_BA_REQ_SSN_CMD_SUB_STRUCT_PARAM,
1337 WMI_TAG_BA_REQ_SSN_EVENT_SUB_STRUCT_PARAM,
1338 WMI_TAG_STA_SMPS_PARAM_CMD,
1339 WMI_TAG_VDEV_SET_GTX_PARAMS_CMD,
1340 WMI_TAG_MCC_SCHED_TRAFFIC_STATS_CMD,
1341 WMI_TAG_MCC_SCHED_STA_TRAFFIC_STATS,
1342 WMI_TAG_OFFLOAD_BCN_TX_STATUS_EVENT,
1343 WMI_TAG_P2P_NOA_EVENT,
1344 WMI_TAG_HB_SET_ENABLE_CMD,
1345 WMI_TAG_HB_SET_TCP_PARAMS_CMD,
1346 WMI_TAG_HB_SET_TCP_PKT_FILTER_CMD,
1347 WMI_TAG_HB_SET_UDP_PARAMS_CMD,
1348 WMI_TAG_HB_SET_UDP_PKT_FILTER_CMD,
1349 WMI_TAG_HB_IND_EVENT,
1350 WMI_TAG_TX_PAUSE_EVENT,
1351 WMI_TAG_RFKILL_EVENT,
1352 WMI_TAG_DFS_RADAR_EVENT,
1353 WMI_TAG_DFS_PHYERR_FILTER_ENA_CMD,
1354 WMI_TAG_DFS_PHYERR_FILTER_DIS_CMD,
1355 WMI_TAG_BATCH_SCAN_RESULT_SCAN_LIST,
1356 WMI_TAG_BATCH_SCAN_RESULT_NETWORK_INFO,
1357 WMI_TAG_BATCH_SCAN_ENABLE_CMD,
1358 WMI_TAG_BATCH_SCAN_DISABLE_CMD,
1359 WMI_TAG_BATCH_SCAN_TRIGGER_RESULT_CMD,
1360 WMI_TAG_BATCH_SCAN_ENABLED_EVENT,
1361 WMI_TAG_BATCH_SCAN_RESULT_EVENT,
1362 WMI_TAG_VDEV_PLMREQ_START_CMD,
1363 WMI_TAG_VDEV_PLMREQ_STOP_CMD,
1364 WMI_TAG_THERMAL_MGMT_CMD,
1365 WMI_TAG_THERMAL_MGMT_EVENT,
1366 WMI_TAG_PEER_INFO_REQ_CMD,
1367 WMI_TAG_PEER_INFO_EVENT,
1368 WMI_TAG_PEER_INFO,
1369 WMI_TAG_PEER_TX_FAIL_CNT_THR_EVENT,
1370 WMI_TAG_RMC_SET_MODE_CMD,
1371 WMI_TAG_RMC_SET_ACTION_PERIOD_CMD,
1372 WMI_TAG_RMC_CONFIG_CMD,
1373 WMI_TAG_MHF_OFFLOAD_SET_MODE_CMD,
1374 WMI_TAG_MHF_OFFLOAD_PLUMB_ROUTING_TABLE_CMD,
1375 WMI_TAG_ADD_PROACTIVE_ARP_RSP_PATTERN_CMD,
1376 WMI_TAG_DEL_PROACTIVE_ARP_RSP_PATTERN_CMD,
1377 WMI_TAG_NAN_CMD_PARAM,
1378 WMI_TAG_NAN_EVENT_HDR,
1379 WMI_TAG_PDEV_L1SS_TRACK_EVENT,
1380 WMI_TAG_DIAG_DATA_CONTAINER_EVENT,
1381 WMI_TAG_MODEM_POWER_STATE_CMD_PARAM,
1382 WMI_TAG_PEER_GET_ESTIMATED_LINKSPEED_CMD,
1383 WMI_TAG_PEER_ESTIMATED_LINKSPEED_EVENT,
1384 WMI_TAG_AGGR_STATE_TRIG_EVENT,
1385 WMI_TAG_MHF_OFFLOAD_ROUTING_TABLE_ENTRY,
1386 WMI_TAG_ROAM_SCAN_CMD,
1387 WMI_TAG_REQ_STATS_EXT_CMD,
1388 WMI_TAG_STATS_EXT_EVENT,
1389 WMI_TAG_OBSS_SCAN_ENABLE_CMD,
1390 WMI_TAG_OBSS_SCAN_DISABLE_CMD,
1391 WMI_TAG_OFFLOAD_PRB_RSP_TX_STATUS_EVENT,
1392 WMI_TAG_PDEV_SET_LED_CONFIG_CMD,
1393 WMI_TAG_HOST_AUTO_SHUTDOWN_CFG_CMD,
1394 WMI_TAG_HOST_AUTO_SHUTDOWN_EVENT,
1395 WMI_TAG_UPDATE_WHAL_MIB_STATS_EVENT,
1396 WMI_TAG_CHAN_AVOID_UPDATE_CMD_PARAM,
1397 WMI_TAG_WOW_IOAC_PKT_PATTERN_T,
1398 WMI_TAG_WOW_IOAC_TMR_PATTERN_T,
1399 WMI_TAG_WOW_IOAC_ADD_KEEPALIVE_CMD,
1400 WMI_TAG_WOW_IOAC_DEL_KEEPALIVE_CMD,
1401 WMI_TAG_WOW_IOAC_KEEPALIVE_T,
1402 WMI_TAG_WOW_IOAC_ADD_PATTERN_CMD,
1403 WMI_TAG_WOW_IOAC_DEL_PATTERN_CMD,
1404 WMI_TAG_START_LINK_STATS_CMD,
1405 WMI_TAG_CLEAR_LINK_STATS_CMD,
1406 WMI_TAG_REQUEST_LINK_STATS_CMD,
1407 WMI_TAG_IFACE_LINK_STATS_EVENT,
1408 WMI_TAG_RADIO_LINK_STATS_EVENT,
1409 WMI_TAG_PEER_STATS_EVENT,
1410 WMI_TAG_CHANNEL_STATS,
1411 WMI_TAG_RADIO_LINK_STATS,
1412 WMI_TAG_RATE_STATS,
1413 WMI_TAG_PEER_LINK_STATS,
1414 WMI_TAG_WMM_AC_STATS,
1415 WMI_TAG_IFACE_LINK_STATS,
1416 WMI_TAG_LPI_MGMT_SNOOPING_CONFIG_CMD,
1417 WMI_TAG_LPI_START_SCAN_CMD,
1418 WMI_TAG_LPI_STOP_SCAN_CMD,
1419 WMI_TAG_LPI_RESULT_EVENT,
1420 WMI_TAG_PEER_STATE_EVENT,
1421 WMI_TAG_EXTSCAN_BUCKET_CMD,
1422 WMI_TAG_EXTSCAN_BUCKET_CHANNEL_EVENT,
1423 WMI_TAG_EXTSCAN_START_CMD,
1424 WMI_TAG_EXTSCAN_STOP_CMD,
1425 WMI_TAG_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMD,
1426 WMI_TAG_EXTSCAN_WLAN_CHANGE_BSSID_PARAM_CMD,
1427 WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMD,
1428 WMI_TAG_EXTSCAN_GET_CACHED_RESULTS_CMD,
1429 WMI_TAG_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMD,
1430 WMI_TAG_EXTSCAN_SET_CAPABILITIES_CMD,
1431 WMI_TAG_EXTSCAN_GET_CAPABILITIES_CMD,
1432 WMI_TAG_EXTSCAN_OPERATION_EVENT,
1433 WMI_TAG_EXTSCAN_START_STOP_EVENT,
1434 WMI_TAG_EXTSCAN_TABLE_USAGE_EVENT,
1435 WMI_TAG_EXTSCAN_WLAN_DESCRIPTOR_EVENT,
1436 WMI_TAG_EXTSCAN_RSSI_INFO_EVENT,
1437 WMI_TAG_EXTSCAN_CACHED_RESULTS_EVENT,
1438 WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULTS_EVENT,
1439 WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULT_BSSID_EVENT,
1440 WMI_TAG_EXTSCAN_HOTLIST_MATCH_EVENT,
1441 WMI_TAG_EXTSCAN_CAPABILITIES_EVENT,
1442 WMI_TAG_EXTSCAN_CACHE_CAPABILITIES_EVENT,
1443 WMI_TAG_EXTSCAN_WLAN_CHANGE_MONITOR_CAPABILITIES_EVENT,
1444 WMI_TAG_EXTSCAN_HOTLIST_MONITOR_CAPABILITIES_EVENT,
1445 WMI_TAG_D0_WOW_ENABLE_DISABLE_CMD,
1446 WMI_TAG_D0_WOW_DISABLE_ACK_EVENT,
1447 WMI_TAG_UNIT_TEST_CMD,
1448 WMI_TAG_ROAM_OFFLOAD_TLV_PARAM,
1449 WMI_TAG_ROAM_11I_OFFLOAD_TLV_PARAM,
1450 WMI_TAG_ROAM_11R_OFFLOAD_TLV_PARAM,
1451 WMI_TAG_ROAM_ESE_OFFLOAD_TLV_PARAM,
1452 WMI_TAG_ROAM_SYNCH_EVENT,
1453 WMI_TAG_ROAM_SYNCH_COMPLETE,
1454 WMI_TAG_EXTWOW_ENABLE_CMD,
1455 WMI_TAG_EXTWOW_SET_APP_TYPE1_PARAMS_CMD,
1456 WMI_TAG_EXTWOW_SET_APP_TYPE2_PARAMS_CMD,
1457 WMI_TAG_LPI_STATUS_EVENT,
1458 WMI_TAG_LPI_HANDOFF_EVENT,
1459 WMI_TAG_VDEV_RATE_STATS_EVENT,
1460 WMI_TAG_VDEV_RATE_HT_INFO,
1461 WMI_TAG_RIC_REQUEST,
1462 WMI_TAG_PDEV_GET_TEMPERATURE_CMD,
1463 WMI_TAG_PDEV_TEMPERATURE_EVENT,
1464 WMI_TAG_SET_DHCP_SERVER_OFFLOAD_CMD,
1465 WMI_TAG_TPC_CHAINMASK_CONFIG_CMD,
1466 WMI_TAG_RIC_TSPEC,
1467 WMI_TAG_TPC_CHAINMASK_CONFIG,
1468 WMI_TAG_IPA_OFFLOAD_ENABLE_DISABLE_CMD,
1469 WMI_TAG_SCAN_PROB_REQ_OUI_CMD,
1470 WMI_TAG_KEY_MATERIAL,
1471 WMI_TAG_TDLS_SET_OFFCHAN_MODE_CMD,
1472 WMI_TAG_SET_LED_FLASHING_CMD,
1473 WMI_TAG_MDNS_OFFLOAD_CMD,
1474 WMI_TAG_MDNS_SET_FQDN_CMD,
1475 WMI_TAG_MDNS_SET_RESP_CMD,
1476 WMI_TAG_MDNS_GET_STATS_CMD,
1477 WMI_TAG_MDNS_STATS_EVENT,
1478 WMI_TAG_ROAM_INVOKE_CMD,
1479 WMI_TAG_PDEV_RESUME_EVENT,
1480 WMI_TAG_PDEV_SET_ANTENNA_DIVERSITY_CMD,
1481 WMI_TAG_SAP_OFL_ENABLE_CMD,
1482 WMI_TAG_SAP_OFL_ADD_STA_EVENT,
1483 WMI_TAG_SAP_OFL_DEL_STA_EVENT,
1484 WMI_TAG_APFIND_CMD_PARAM,
1485 WMI_TAG_APFIND_EVENT_HDR,
1486 WMI_TAG_OCB_SET_SCHED_CMD,
1487 WMI_TAG_OCB_SET_SCHED_EVENT,
1488 WMI_TAG_OCB_SET_CONFIG_CMD,
1489 WMI_TAG_OCB_SET_CONFIG_RESP_EVENT,
1490 WMI_TAG_OCB_SET_UTC_TIME_CMD,
1491 WMI_TAG_OCB_START_TIMING_ADVERT_CMD,
1492 WMI_TAG_OCB_STOP_TIMING_ADVERT_CMD,
1493 WMI_TAG_OCB_GET_TSF_TIMER_CMD,
1494 WMI_TAG_OCB_GET_TSF_TIMER_RESP_EVENT,
1495 WMI_TAG_DCC_GET_STATS_CMD,
1496 WMI_TAG_DCC_CHANNEL_STATS_REQUEST,
1497 WMI_TAG_DCC_GET_STATS_RESP_EVENT,
1498 WMI_TAG_DCC_CLEAR_STATS_CMD,
1499 WMI_TAG_DCC_UPDATE_NDL_CMD,
1500 WMI_TAG_DCC_UPDATE_NDL_RESP_EVENT,
1501 WMI_TAG_DCC_STATS_EVENT,
1502 WMI_TAG_OCB_CHANNEL,
1503 WMI_TAG_OCB_SCHEDULE_ELEMENT,
1504 WMI_TAG_DCC_NDL_STATS_PER_CHANNEL,
1505 WMI_TAG_DCC_NDL_CHAN,
1506 WMI_TAG_QOS_PARAMETER,
1507 WMI_TAG_DCC_NDL_ACTIVE_STATE_CONFIG,
1508 WMI_TAG_ROAM_SCAN_EXTENDED_THRESHOLD_PARAM,
1509 WMI_TAG_ROAM_FILTER,
1510 WMI_TAG_PASSPOINT_CONFIG_CMD,
1511 WMI_TAG_PASSPOINT_EVENT_HDR,
1512 WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMD,
1513 WMI_TAG_EXTSCAN_HOTLIST_SSID_MATCH_EVENT,
1514 WMI_TAG_VDEV_TSF_TSTAMP_ACTION_CMD,
1515 WMI_TAG_VDEV_TSF_REPORT_EVENT,
1516 WMI_TAG_GET_FW_MEM_DUMP,
1517 WMI_TAG_UPDATE_FW_MEM_DUMP,
1518 WMI_TAG_FW_MEM_DUMP_PARAMS,
1519 WMI_TAG_DEBUG_MESG_FLUSH,
1520 WMI_TAG_DEBUG_MESG_FLUSH_COMPLETE,
1521 WMI_TAG_PEER_SET_RATE_REPORT_CONDITION,
1522 WMI_TAG_ROAM_SUBNET_CHANGE_CONFIG,
1523 WMI_TAG_VDEV_SET_IE_CMD,
1524 WMI_TAG_RSSI_BREACH_MONITOR_CONFIG,
1525 WMI_TAG_RSSI_BREACH_EVENT,
1526 WMI_TAG_WOW_EVENT_INITIAL_WAKEUP,
1527 WMI_TAG_SOC_SET_PCL_CMD,
1528 WMI_TAG_SOC_SET_HW_MODE_CMD,
1529 WMI_TAG_SOC_SET_HW_MODE_RESPONSE_EVENT,
1530 WMI_TAG_SOC_HW_MODE_TRANSITION_EVENT,
1531 WMI_TAG_VDEV_TXRX_STREAMS,
1532 WMI_TAG_SOC_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY,
1533 WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_CMD,
1534 WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_RESPONSE_EVENT,
1535 WMI_TAG_WOW_IOAC_SOCK_PATTERN_T,
1536 WMI_TAG_WOW_ENABLE_ICMPV6_NA_FLT_CMD,
1537 WMI_TAG_DIAG_EVENT_LOG_CONFIG,
1538 WMI_TAG_DIAG_EVENT_LOG_SUPPORTED_EVENT_FIXED_PARAMS,
1539 WMI_TAG_PACKET_FILTER_CONFIG,
1540 WMI_TAG_PACKET_FILTER_ENABLE,
1541 WMI_TAG_SAP_SET_BLACKLIST_PARAM_CMD,
1542 WMI_TAG_MGMT_TX_SEND_CMD,
1543 WMI_TAG_MGMT_TX_COMPL_EVENT,
1544 WMI_TAG_SOC_SET_ANTENNA_MODE_CMD,
1545 WMI_TAG_WOW_UDP_SVC_OFLD_CMD,
1546 WMI_TAG_LRO_INFO_CMD,
1547 WMI_TAG_ROAM_EARLYSTOP_RSSI_THRES_PARAM,
1548 WMI_TAG_SERVICE_READY_EXT_EVENT,
1549 WMI_TAG_MAWC_SENSOR_REPORT_IND_CMD,
1550 WMI_TAG_MAWC_ENABLE_SENSOR_EVENT,
1551 WMI_TAG_ROAM_CONFIGURE_MAWC_CMD,
1552 WMI_TAG_NLO_CONFIGURE_MAWC_CMD,
1553 WMI_TAG_EXTSCAN_CONFIGURE_MAWC_CMD,
1554 WMI_TAG_PEER_ASSOC_CONF_EVENT,
1555 WMI_TAG_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMD,
1556 WMI_TAG_AP_PS_EGAP_PARAM_CMD,
1557 WMI_TAG_AP_PS_EGAP_INFO_EVENT,
1558 WMI_TAG_PMF_OFFLOAD_SET_SA_QUERY_CMD,
1559 WMI_TAG_TRANSFER_DATA_TO_FLASH_CMD,
1560 WMI_TAG_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENT,
1561 WMI_TAG_SCPC_EVENT,
1562 WMI_TAG_AP_PS_EGAP_INFO_CHAINMASK_LIST,
1563 WMI_TAG_STA_SMPS_FORCE_MODE_COMPLETE_EVENT,
1564 WMI_TAG_BPF_GET_CAPABILITY_CMD,
1565 WMI_TAG_BPF_CAPABILITY_INFO_EVT,
1566 WMI_TAG_BPF_GET_VDEV_STATS_CMD,
1567 WMI_TAG_BPF_VDEV_STATS_INFO_EVT,
1568 WMI_TAG_BPF_SET_VDEV_INSTRUCTIONS_CMD,
1569 WMI_TAG_BPF_DEL_VDEV_INSTRUCTIONS_CMD,
1570 WMI_TAG_VDEV_DELETE_RESP_EVENT,
1571 WMI_TAG_PEER_DELETE_RESP_EVENT,
1572 WMI_TAG_ROAM_DENSE_THRES_PARAM,
1573 WMI_TAG_ENLO_CANDIDATE_SCORE_PARAM,
1574 WMI_TAG_PEER_UPDATE_WDS_ENTRY_CMD,
1575 WMI_TAG_VDEV_CONFIG_RATEMASK,
1576 WMI_TAG_PDEV_FIPS_CMD,
1577 WMI_TAG_PDEV_SMART_ANT_ENABLE_CMD,
1578 WMI_TAG_PDEV_SMART_ANT_SET_RX_ANTENNA_CMD,
1579 WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_CMD,
1580 WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_CMD,
1581 WMI_TAG_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMD,
1582 WMI_TAG_PDEV_SET_ANT_SWITCH_TBL_CMD,
1583 WMI_TAG_PDEV_SET_CTL_TABLE_CMD,
1584 WMI_TAG_PDEV_SET_MIMOGAIN_TABLE_CMD,
1585 WMI_TAG_FWTEST_SET_PARAM_CMD,
1586 WMI_TAG_PEER_ATF_REQUEST,
1587 WMI_TAG_VDEV_ATF_REQUEST,
1588 WMI_TAG_PDEV_GET_ANI_CCK_CONFIG_CMD,
1589 WMI_TAG_PDEV_GET_ANI_OFDM_CONFIG_CMD,
1590 WMI_TAG_INST_RSSI_STATS_RESP,
1591 WMI_TAG_MED_UTIL_REPORT_EVENT,
1592 WMI_TAG_PEER_STA_PS_STATECHANGE_EVENT,
1593 WMI_TAG_WDS_ADDR_EVENT,
1594 WMI_TAG_PEER_RATECODE_LIST_EVENT,
1595 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENT,
1596 WMI_TAG_PDEV_TPC_EVENT,
1597 WMI_TAG_ANI_OFDM_EVENT,
1598 WMI_TAG_ANI_CCK_EVENT,
1599 WMI_TAG_PDEV_CHANNEL_HOPPING_EVENT,
1600 WMI_TAG_PDEV_FIPS_EVENT,
1601 WMI_TAG_ATF_PEER_INFO,
1602 WMI_TAG_PDEV_GET_TPC_CMD,
1603 WMI_TAG_VDEV_FILTER_NRP_CONFIG_CMD,
1604 WMI_TAG_QBOOST_CFG_CMD,
1605 WMI_TAG_PDEV_SMART_ANT_GPIO_HANDLE,
1606 WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_SERIES,
1607 WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_PARAM,
1608 WMI_TAG_PDEV_SET_ANT_CTRL_CHAIN,
1609 WMI_TAG_PEER_CCK_OFDM_RATE_INFO,
1610 WMI_TAG_PEER_MCS_RATE_INFO,
1611 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBR,
1612 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBM,
1613 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_FREQNUM,
1614 WMI_TAG_MU_REPORT_TOTAL_MU,
1615 WMI_TAG_VDEV_SET_DSCP_TID_MAP_CMD,
1616 WMI_TAG_ROAM_SET_MBO,
1617 WMI_TAG_MIB_STATS_ENABLE_CMD,
1618 WMI_TAG_NAN_DISC_IFACE_CREATED_EVENT,
1619 WMI_TAG_NAN_DISC_IFACE_DELETED_EVENT,
1620 WMI_TAG_NAN_STARTED_CLUSTER_EVENT,
1621 WMI_TAG_NAN_JOINED_CLUSTER_EVENT,
1622 WMI_TAG_NDI_GET_CAP_REQ,
1623 WMI_TAG_NDP_INITIATOR_REQ,
1624 WMI_TAG_NDP_RESPONDER_REQ,
1625 WMI_TAG_NDP_END_REQ,
1626 WMI_TAG_NDI_CAP_RSP_EVENT,
1627 WMI_TAG_NDP_INITIATOR_RSP_EVENT,
1628 WMI_TAG_NDP_RESPONDER_RSP_EVENT,
1629 WMI_TAG_NDP_END_RSP_EVENT,
1630 WMI_TAG_NDP_INDICATION_EVENT,
1631 WMI_TAG_NDP_CONFIRM_EVENT,
1632 WMI_TAG_NDP_END_INDICATION_EVENT,
1633 WMI_TAG_VDEV_SET_QUIET_CMD,
1634 WMI_TAG_PDEV_SET_PCL_CMD,
1635 WMI_TAG_PDEV_SET_HW_MODE_CMD,
1636 WMI_TAG_PDEV_SET_MAC_CONFIG_CMD,
1637 WMI_TAG_PDEV_SET_ANTENNA_MODE_CMD,
1638 WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_EVENT,
1639 WMI_TAG_PDEV_HW_MODE_TRANSITION_EVENT,
1640 WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY,
1641 WMI_TAG_PDEV_SET_MAC_CONFIG_RESPONSE_EVENT,
1642 WMI_TAG_COEX_CONFIG_CMD,
1643 WMI_TAG_CONFIG_ENHANCED_MCAST_FILTER,
1644 WMI_TAG_CHAN_AVOID_RPT_ALLOW_CMD,
1645 WMI_TAG_SET_PERIODIC_CHANNEL_STATS_CONFIG,
1646 WMI_TAG_VDEV_SET_CUSTOM_AGGR_SIZE_CMD,
1647 WMI_TAG_PDEV_WAL_POWER_DEBUG_CMD,
1648 WMI_TAG_MAC_PHY_CAPABILITIES,
1649 WMI_TAG_HW_MODE_CAPABILITIES,
1650 WMI_TAG_SOC_MAC_PHY_HW_MODE_CAPS,
1651 WMI_TAG_HAL_REG_CAPABILITIES_EXT,
1652 WMI_TAG_SOC_HAL_REG_CAPABILITIES,
1653 WMI_TAG_VDEV_WISA_CMD,
1654 WMI_TAG_TX_POWER_LEVEL_STATS_EVT,
1655 WMI_TAG_SCAN_ADAPTIVE_DWELL_PARAMETERS_TLV,
1656 WMI_TAG_SCAN_ADAPTIVE_DWELL_CONFIG,
1657 WMI_TAG_WOW_SET_ACTION_WAKE_UP_CMD,
1658 WMI_TAG_NDP_END_RSP_PER_NDI,
1659 WMI_TAG_PEER_BWF_REQUEST,
1660 WMI_TAG_BWF_PEER_INFO,
1661 WMI_TAG_DBGLOG_TIME_STAMP_SYNC_CMD,
1662 WMI_TAG_RMC_SET_LEADER_CMD,
1663 WMI_TAG_RMC_MANUAL_LEADER_EVENT,
1664 WMI_TAG_PER_CHAIN_RSSI_STATS,
1665 WMI_TAG_RSSI_STATS,
1666 WMI_TAG_P2P_LO_START_CMD,
1667 WMI_TAG_P2P_LO_STOP_CMD,
1668 WMI_TAG_P2P_LO_STOPPED_EVENT,
1669 WMI_TAG_REORDER_QUEUE_SETUP_CMD,
1670 WMI_TAG_REORDER_QUEUE_REMOVE_CMD,
1671 WMI_TAG_SET_MULTIPLE_MCAST_FILTER_CMD,
1672 WMI_TAG_MGMT_TX_COMPL_BUNDLE_EVENT,
1673 WMI_TAG_READ_DATA_FROM_FLASH_CMD,
1674 WMI_TAG_READ_DATA_FROM_FLASH_EVENT,
1675 WMI_TAG_PDEV_SET_REORDER_TIMEOUT_VAL_CMD,
1676 WMI_TAG_PEER_SET_RX_BLOCKSIZE_CMD,
1677 WMI_TAG_PDEV_SET_WAKEUP_CONFIG_CMDID,
1678 WMI_TAG_TLV_BUF_LEN_PARAM,
1679 WMI_TAG_SERVICE_AVAILABLE_EVENT,
1680 WMI_TAG_PEER_ANTDIV_INFO_REQ_CMD,
1681 WMI_TAG_PEER_ANTDIV_INFO_EVENT,
1682 WMI_TAG_PEER_ANTDIV_INFO,
1683 WMI_TAG_PDEV_GET_ANTDIV_STATUS_CMD,
1684 WMI_TAG_PDEV_ANTDIV_STATUS_EVENT,
1685 WMI_TAG_MNT_FILTER_CMD,
1686 WMI_TAG_GET_CHIP_POWER_STATS_CMD,
1687 WMI_TAG_PDEV_CHIP_POWER_STATS_EVENT,
1688 WMI_TAG_COEX_GET_ANTENNA_ISOLATION_CMD,
1689 WMI_TAG_COEX_REPORT_ISOLATION_EVENT,
1690 WMI_TAG_CHAN_CCA_STATS,
1691 WMI_TAG_PEER_SIGNAL_STATS,
1692 WMI_TAG_TX_STATS,
1693 WMI_TAG_PEER_AC_TX_STATS,
1694 WMI_TAG_RX_STATS,
1695 WMI_TAG_PEER_AC_RX_STATS,
1696 WMI_TAG_REPORT_STATS_EVENT,
1697 WMI_TAG_CHAN_CCA_STATS_THRESH,
1698 WMI_TAG_PEER_SIGNAL_STATS_THRESH,
1699 WMI_TAG_TX_STATS_THRESH,
1700 WMI_TAG_RX_STATS_THRESH,
1701 WMI_TAG_PDEV_SET_STATS_THRESHOLD_CMD,
1702 WMI_TAG_REQUEST_WLAN_STATS_CMD,
1703 WMI_TAG_RX_AGGR_FAILURE_EVENT,
1704 WMI_TAG_RX_AGGR_FAILURE_INFO,
1705 WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMD,
1706 WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENT,
1707 WMI_TAG_PDEV_BAND_TO_MAC,
1708 WMI_TAG_TBTT_OFFSET_INFO,
1709 WMI_TAG_TBTT_OFFSET_EXT_EVENT,
1710 WMI_TAG_SAR_LIMITS_CMD,
1711 WMI_TAG_SAR_LIMIT_CMD_ROW,
1712 WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMD,
1713 WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMD,
1714 WMI_TAG_VDEV_ADFS_CH_CFG_CMD,
1715 WMI_TAG_VDEV_ADFS_OCAC_ABORT_CMD,
1716 WMI_TAG_PDEV_DFS_RADAR_DETECTION_EVENT,
1717 WMI_TAG_VDEV_ADFS_OCAC_COMPLETE_EVENT,
1718 WMI_TAG_VDEV_DFS_CAC_COMPLETE_EVENT,
1719 WMI_TAG_VENDOR_OUI,
1720 WMI_TAG_REQUEST_RCPI_CMD,
1721 WMI_TAG_UPDATE_RCPI_EVENT,
1722 WMI_TAG_REQUEST_PEER_STATS_INFO_CMD,
1723 WMI_TAG_PEER_STATS_INFO,
1724 WMI_TAG_PEER_STATS_INFO_EVENT,
1725 WMI_TAG_PKGID_EVENT,
1726 WMI_TAG_CONNECTED_NLO_RSSI_PARAMS,
1727 WMI_TAG_SET_CURRENT_COUNTRY_CMD,
1728 WMI_TAG_REGULATORY_RULE_STRUCT,
1729 WMI_TAG_REG_CHAN_LIST_CC_EVENT,
1730 WMI_TAG_11D_SCAN_START_CMD,
1731 WMI_TAG_11D_SCAN_STOP_CMD,
1732 WMI_TAG_11D_NEW_COUNTRY_EVENT,
1733 WMI_TAG_REQUEST_RADIO_CHAN_STATS_CMD,
1734 WMI_TAG_RADIO_CHAN_STATS,
1735 WMI_TAG_RADIO_CHAN_STATS_EVENT,
1736 WMI_TAG_ROAM_PER_CONFIG,
1737 WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMD,
1738 WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENT,
1739 WMI_TAG_BPF_SET_VDEV_ACTIVE_MODE_CMD,
1740 WMI_TAG_HW_DATA_FILTER_CMD,
1741 WMI_TAG_CONNECTED_NLO_BSS_BAND_RSSI_PREF,
1742 WMI_TAG_PEER_OPER_MODE_CHANGE_EVENT,
1743 WMI_TAG_CHIP_POWER_SAVE_FAILURE_DETECTED,
1744 WMI_TAG_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMD,
1745 WMI_TAG_PDEV_CSA_SWITCH_COUNT_STATUS_EVENT,
1746 WMI_TAG_PDEV_UPDATE_PKT_ROUTING_CMD,
1747 WMI_TAG_PDEV_CHECK_CAL_VERSION_CMD,
1748 WMI_TAG_PDEV_CHECK_CAL_VERSION_EVENT,
1749 WMI_TAG_PDEV_SET_DIVERSITY_GAIN_CMD,
1750 WMI_TAG_MAC_PHY_CHAINMASK_COMBO,
1751 WMI_TAG_MAC_PHY_CHAINMASK_CAPABILITY,
1752 WMI_TAG_VDEV_SET_ARP_STATS_CMD,
1753 WMI_TAG_VDEV_GET_ARP_STATS_CMD,
1754 WMI_TAG_VDEV_GET_ARP_STATS_EVENT,
1755 WMI_TAG_IFACE_OFFLOAD_STATS,
1756 WMI_TAG_REQUEST_STATS_CMD_SUB_STRUCT_PARAM,
1757 WMI_TAG_RSSI_CTL_EXT,
1758 WMI_TAG_SINGLE_PHYERR_EXT_RX_HDR,
1759 WMI_TAG_COEX_BT_ACTIVITY_EVENT,
1760 WMI_TAG_VDEV_GET_TX_POWER_CMD,
1761 WMI_TAG_VDEV_TX_POWER_EVENT,
1762 WMI_TAG_OFFCHAN_DATA_TX_COMPL_EVENT,
1763 WMI_TAG_OFFCHAN_DATA_TX_SEND_CMD,
1764 WMI_TAG_TX_SEND_PARAMS,
1765 WMI_TAG_HE_RATE_SET,
1766 WMI_TAG_CONGESTION_STATS,
1767 WMI_TAG_SET_INIT_COUNTRY_CMD,
1768 WMI_TAG_SCAN_DBS_DUTY_CYCLE,
1769 WMI_TAG_SCAN_DBS_DUTY_CYCLE_PARAM_TLV,
1770 WMI_TAG_PDEV_DIV_GET_RSSI_ANTID,
1771 WMI_TAG_THERM_THROT_CONFIG_REQUEST,
1772 WMI_TAG_THERM_THROT_LEVEL_CONFIG_INFO,
1773 WMI_TAG_THERM_THROT_STATS_EVENT,
1774 WMI_TAG_THERM_THROT_LEVEL_STATS_INFO,
1775 WMI_TAG_PDEV_DIV_RSSI_ANTID_EVENT,
1776 WMI_TAG_OEM_DMA_RING_CAPABILITIES,
1777 WMI_TAG_OEM_DMA_RING_CFG_REQ,
1778 WMI_TAG_OEM_DMA_RING_CFG_RSP,
1779 WMI_TAG_OEM_INDIRECT_DATA,
1780 WMI_TAG_OEM_DMA_BUF_RELEASE,
1781 WMI_TAG_OEM_DMA_BUF_RELEASE_ENTRY,
1782 WMI_TAG_PDEV_BSS_CHAN_INFO_REQUEST,
1783 WMI_TAG_PDEV_BSS_CHAN_INFO_EVENT,
1784 WMI_TAG_ROAM_LCA_DISALLOW_CONFIG,
1785 WMI_TAG_VDEV_LIMIT_OFFCHAN_CMD,
1786 WMI_TAG_ROAM_RSSI_REJECTION_OCE_CONFIG,
1787 WMI_TAG_UNIT_TEST_EVENT,
1788 WMI_TAG_ROAM_FILS_OFFLOAD,
1789 WMI_TAG_PDEV_UPDATE_PMK_CACHE_CMD,
1790 WMI_TAG_PMK_CACHE,
1791 WMI_TAG_PDEV_UPDATE_FILS_HLP_PKT_CMD,
1792 WMI_TAG_ROAM_FILS_SYNCH,
1793 WMI_TAG_GTK_OFFLOAD_EXTENDED,
1794 WMI_TAG_ROAM_BG_SCAN_ROAMING,
1795 WMI_TAG_OIC_PING_OFFLOAD_PARAMS_CMD,
1796 WMI_TAG_OIC_PING_OFFLOAD_SET_ENABLE_CMD,
1797 WMI_TAG_OIC_PING_HANDOFF_EVENT,
1798 WMI_TAG_DHCP_LEASE_RENEW_OFFLOAD_CMD,
1799 WMI_TAG_DHCP_LEASE_RENEW_EVENT,
1800 WMI_TAG_BTM_CONFIG,
1801 WMI_TAG_DEBUG_MESG_FW_DATA_STALL,
1802 WMI_TAG_WLM_CONFIG_CMD,
1803 WMI_TAG_PDEV_UPDATE_CTLTABLE_REQUEST,
1804 WMI_TAG_PDEV_UPDATE_CTLTABLE_EVENT,
1805 WMI_TAG_ROAM_CND_SCORING_PARAM,
1806 WMI_TAG_PDEV_CONFIG_VENDOR_OUI_ACTION,
1807 WMI_TAG_VENDOR_OUI_EXT,
1808 WMI_TAG_ROAM_SYNCH_FRAME_EVENT,
1809 WMI_TAG_FD_SEND_FROM_HOST_CMD,
1810 WMI_TAG_ENABLE_FILS_CMD,
1811 WMI_TAG_HOST_SWFDA_EVENT,
1812 WMI_TAG_BCN_OFFLOAD_CTRL_CMD,
1813 WMI_TAG_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMD,
1814 WMI_TAG_STATS_PERIOD,
1815 WMI_TAG_NDL_SCHEDULE_UPDATE,
1816 WMI_TAG_PEER_TID_MSDUQ_QDEPTH_THRESH_UPDATE_CMD,
1817 WMI_TAG_MSDUQ_QDEPTH_THRESH_UPDATE,
1818 WMI_TAG_PDEV_SET_RX_FILTER_PROMISCUOUS_CMD,
1819 WMI_TAG_SAR2_RESULT_EVENT,
1820 WMI_TAG_SAR_CAPABILITIES,
1821 WMI_TAG_SAP_OBSS_DETECTION_CFG_CMD,
1822 WMI_TAG_SAP_OBSS_DETECTION_INFO_EVT,
1823 WMI_TAG_DMA_RING_CAPABILITIES,
1824 WMI_TAG_DMA_RING_CFG_REQ,
1825 WMI_TAG_DMA_RING_CFG_RSP,
1826 WMI_TAG_DMA_BUF_RELEASE,
1827 WMI_TAG_DMA_BUF_RELEASE_ENTRY,
1828 WMI_TAG_SAR_GET_LIMITS_CMD,
1829 WMI_TAG_SAR_GET_LIMITS_EVENT,
1830 WMI_TAG_SAR_GET_LIMITS_EVENT_ROW,
1831 WMI_TAG_OFFLOAD_11K_REPORT,
1832 WMI_TAG_INVOKE_NEIGHBOR_REPORT,
1833 WMI_TAG_NEIGHBOR_REPORT_OFFLOAD,
1834 WMI_TAG_VDEV_SET_CONNECTIVITY_CHECK_STATS,
1835 WMI_TAG_VDEV_GET_CONNECTIVITY_CHECK_STATS,
1836 WMI_TAG_BPF_SET_VDEV_ENABLE_CMD,
1837 WMI_TAG_BPF_SET_VDEV_WORK_MEMORY_CMD,
1838 WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_CMD,
1839 WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_RESP_EVT,
1840 WMI_TAG_PDEV_GET_NFCAL_POWER,
1841 WMI_TAG_BSS_COLOR_CHANGE_ENABLE,
1842 WMI_TAG_OBSS_COLOR_COLLISION_DET_CONFIG,
1843 WMI_TAG_OBSS_COLOR_COLLISION_EVT,
1844 WMI_TAG_RUNTIME_DPD_RECAL_CMD,
1845 WMI_TAG_TWT_ENABLE_CMD,
1846 WMI_TAG_TWT_DISABLE_CMD,
1847 WMI_TAG_TWT_ADD_DIALOG_CMD,
1848 WMI_TAG_TWT_DEL_DIALOG_CMD,
1849 WMI_TAG_TWT_PAUSE_DIALOG_CMD,
1850 WMI_TAG_TWT_RESUME_DIALOG_CMD,
1851 WMI_TAG_TWT_ENABLE_COMPLETE_EVENT,
1852 WMI_TAG_TWT_DISABLE_COMPLETE_EVENT,
1853 WMI_TAG_TWT_ADD_DIALOG_COMPLETE_EVENT,
1854 WMI_TAG_TWT_DEL_DIALOG_COMPLETE_EVENT,
1855 WMI_TAG_TWT_PAUSE_DIALOG_COMPLETE_EVENT,
1856 WMI_TAG_TWT_RESUME_DIALOG_COMPLETE_EVENT,
1857 WMI_TAG_REQUEST_ROAM_SCAN_STATS_CMD,
1858 WMI_TAG_ROAM_SCAN_STATS_EVENT,
1859 WMI_TAG_PEER_TID_CONFIGURATIONS_CMD,
1860 WMI_TAG_VDEV_SET_CUSTOM_SW_RETRY_TH_CMD,
1861 WMI_TAG_GET_TPC_POWER_CMD,
1862 WMI_TAG_GET_TPC_POWER_EVENT,
1863 WMI_TAG_DMA_BUF_RELEASE_SPECTRAL_META_DATA,
1864 WMI_TAG_MOTION_DET_CONFIG_PARAMS_CMD,
1865 WMI_TAG_MOTION_DET_BASE_LINE_CONFIG_PARAMS_CMD,
1866 WMI_TAG_MOTION_DET_START_STOP_CMD,
1867 WMI_TAG_MOTION_DET_BASE_LINE_START_STOP_CMD,
1868 WMI_TAG_MOTION_DET_EVENT,
1869 WMI_TAG_MOTION_DET_BASE_LINE_EVENT,
1870 WMI_TAG_NDP_TRANSPORT_IP,
1871 WMI_TAG_OBSS_SPATIAL_REUSE_SET_CMD,
1872 WMI_TAG_ESP_ESTIMATE_EVENT,
1873 WMI_TAG_NAN_HOST_CONFIG,
1874 WMI_TAG_SPECTRAL_BIN_SCALING_PARAMS,
1875 WMI_TAG_PEER_CFR_CAPTURE_CMD,
1876 WMI_TAG_PEER_CHAN_WIDTH_SWITCH_CMD,
1877 WMI_TAG_CHAN_WIDTH_PEER_LIST,
1878 WMI_TAG_OBSS_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMD,
1879 WMI_TAG_PDEV_HE_TB_ACTION_FRM_CMD,
1880 WMI_TAG_PEER_EXTD2_STATS,
1881 WMI_TAG_HPCS_PULSE_START_CMD,
1882 WMI_TAG_PDEV_CTL_FAILSAFE_CHECK_EVENT,
1883 WMI_TAG_VDEV_CHAINMASK_CONFIG_CMD,
1884 WMI_TAG_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMD,
1885 WMI_TAG_NAN_EVENT_INFO,
1886 WMI_TAG_NDP_CHANNEL_INFO,
1887 WMI_TAG_NDP_CMD,
1888 WMI_TAG_NDP_EVENT,
1889 WMI_TAG_PDEV_PEER_PKTLOG_FILTER_CMD = 0x301,
1890 WMI_TAG_PDEV_PEER_PKTLOG_FILTER_INFO,
1891 WMI_TAG_FILS_DISCOVERY_TMPL_CMD = 0x344,
1892 WMI_TAG_PDEV_SRG_BSS_COLOR_BITMAP_CMD = 0x37b,
1893 WMI_TAG_PDEV_SRG_PARTIAL_BSSID_BITMAP_CMD,
1894 WMI_TAG_PDEV_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD = 0x381,
1895 WMI_TAG_PDEV_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD,
1896 WMI_TAG_PDEV_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD,
1897 WMI_TAG_PDEV_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD,
1898 WMI_TAG_REGULATORY_RULE_EXT_STRUCT = 0x3A9,
1899 WMI_TAG_REG_CHAN_LIST_CC_EXT_EVENT,
1900 WMI_TAG_VDEV_SET_TPC_POWER_CMD = 0x3B5,
1901 WMI_TAG_VDEV_CH_POWER_INFO,
1902 WMI_TAG_PDEV_SET_BIOS_SAR_TABLE_CMD = 0x3D8,
1903 WMI_TAG_PDEV_SET_BIOS_GEO_TABLE_CMD,
1904 WMI_TAG_MAX
1905};
1906
1907enum wmi_tlv_service {
1908 WMI_TLV_SERVICE_BEACON_OFFLOAD = 0,
1909 WMI_TLV_SERVICE_SCAN_OFFLOAD = 1,
1910 WMI_TLV_SERVICE_ROAM_SCAN_OFFLOAD = 2,
1911 WMI_TLV_SERVICE_BCN_MISS_OFFLOAD = 3,
1912 WMI_TLV_SERVICE_STA_PWRSAVE = 4,
1913 WMI_TLV_SERVICE_STA_ADVANCED_PWRSAVE = 5,
1914 WMI_TLV_SERVICE_AP_UAPSD = 6,
1915 WMI_TLV_SERVICE_AP_DFS = 7,
1916 WMI_TLV_SERVICE_11AC = 8,
1917 WMI_TLV_SERVICE_BLOCKACK = 9,
1918 WMI_TLV_SERVICE_PHYERR = 10,
1919 WMI_TLV_SERVICE_BCN_FILTER = 11,
1920 WMI_TLV_SERVICE_RTT = 12,
1921 WMI_TLV_SERVICE_WOW = 13,
1922 WMI_TLV_SERVICE_RATECTRL_CACHE = 14,
1923 WMI_TLV_SERVICE_IRAM_TIDS = 15,
1924 WMI_TLV_SERVICE_ARPNS_OFFLOAD = 16,
1925 WMI_TLV_SERVICE_NLO = 17,
1926 WMI_TLV_SERVICE_GTK_OFFLOAD = 18,
1927 WMI_TLV_SERVICE_SCAN_SCH = 19,
1928 WMI_TLV_SERVICE_CSA_OFFLOAD = 20,
1929 WMI_TLV_SERVICE_CHATTER = 21,
1930 WMI_TLV_SERVICE_COEX_FREQAVOID = 22,
1931 WMI_TLV_SERVICE_PACKET_POWER_SAVE = 23,
1932 WMI_TLV_SERVICE_FORCE_FW_HANG = 24,
1933 WMI_TLV_SERVICE_GPIO = 25,
1934 WMI_TLV_SERVICE_STA_DTIM_PS_MODULATED_DTIM = 26,
1935 WMI_STA_UAPSD_BASIC_AUTO_TRIG = 27,
1936 WMI_STA_UAPSD_VAR_AUTO_TRIG = 28,
1937 WMI_TLV_SERVICE_STA_KEEP_ALIVE = 29,
1938 WMI_TLV_SERVICE_TX_ENCAP = 30,
1939 WMI_TLV_SERVICE_AP_PS_DETECT_OUT_OF_SYNC = 31,
1940 WMI_TLV_SERVICE_EARLY_RX = 32,
1941 WMI_TLV_SERVICE_STA_SMPS = 33,
1942 WMI_TLV_SERVICE_FWTEST = 34,
1943 WMI_TLV_SERVICE_STA_WMMAC = 35,
1944 WMI_TLV_SERVICE_TDLS = 36,
1945 WMI_TLV_SERVICE_BURST = 37,
1946 WMI_TLV_SERVICE_MCC_BCN_INTERVAL_CHANGE = 38,
1947 WMI_TLV_SERVICE_ADAPTIVE_OCS = 39,
1948 WMI_TLV_SERVICE_BA_SSN_SUPPORT = 40,
1949 WMI_TLV_SERVICE_FILTER_IPSEC_NATKEEPALIVE = 41,
1950 WMI_TLV_SERVICE_WLAN_HB = 42,
1951 WMI_TLV_SERVICE_LTE_ANT_SHARE_SUPPORT = 43,
1952 WMI_TLV_SERVICE_BATCH_SCAN = 44,
1953 WMI_TLV_SERVICE_QPOWER = 45,
1954 WMI_TLV_SERVICE_PLMREQ = 46,
1955 WMI_TLV_SERVICE_THERMAL_MGMT = 47,
1956 WMI_TLV_SERVICE_RMC = 48,
1957 WMI_TLV_SERVICE_MHF_OFFLOAD = 49,
1958 WMI_TLV_SERVICE_COEX_SAR = 50,
1959 WMI_TLV_SERVICE_BCN_TXRATE_OVERRIDE = 51,
1960 WMI_TLV_SERVICE_NAN = 52,
1961 WMI_TLV_SERVICE_L1SS_STAT = 53,
1962 WMI_TLV_SERVICE_ESTIMATE_LINKSPEED = 54,
1963 WMI_TLV_SERVICE_OBSS_SCAN = 55,
1964 WMI_TLV_SERVICE_TDLS_OFFCHAN = 56,
1965 WMI_TLV_SERVICE_TDLS_UAPSD_BUFFER_STA = 57,
1966 WMI_TLV_SERVICE_TDLS_UAPSD_SLEEP_STA = 58,
1967 WMI_TLV_SERVICE_IBSS_PWRSAVE = 59,
1968 WMI_TLV_SERVICE_LPASS = 60,
1969 WMI_TLV_SERVICE_EXTSCAN = 61,
1970 WMI_TLV_SERVICE_D0WOW = 62,
1971 WMI_TLV_SERVICE_HSOFFLOAD = 63,
1972 WMI_TLV_SERVICE_ROAM_HO_OFFLOAD = 64,
1973 WMI_TLV_SERVICE_RX_FULL_REORDER = 65,
1974 WMI_TLV_SERVICE_DHCP_OFFLOAD = 66,
1975 WMI_TLV_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT = 67,
1976 WMI_TLV_SERVICE_MDNS_OFFLOAD = 68,
1977 WMI_TLV_SERVICE_SAP_AUTH_OFFLOAD = 69,
1978 WMI_TLV_SERVICE_DUAL_BAND_SIMULTANEOUS_SUPPORT = 70,
1979 WMI_TLV_SERVICE_OCB = 71,
1980 WMI_TLV_SERVICE_AP_ARPNS_OFFLOAD = 72,
1981 WMI_TLV_SERVICE_PER_BAND_CHAINMASK_SUPPORT = 73,
1982 WMI_TLV_SERVICE_PACKET_FILTER_OFFLOAD = 74,
1983 WMI_TLV_SERVICE_MGMT_TX_HTT = 75,
1984 WMI_TLV_SERVICE_MGMT_TX_WMI = 76,
1985 WMI_TLV_SERVICE_EXT_MSG = 77,
1986 WMI_TLV_SERVICE_MAWC = 78,
1987 WMI_TLV_SERVICE_PEER_ASSOC_CONF = 79,
1988 WMI_TLV_SERVICE_EGAP = 80,
1989 WMI_TLV_SERVICE_STA_PMF_OFFLOAD = 81,
1990 WMI_TLV_SERVICE_UNIFIED_WOW_CAPABILITY = 82,
1991 WMI_TLV_SERVICE_ENHANCED_PROXY_STA = 83,
1992 WMI_TLV_SERVICE_ATF = 84,
1993 WMI_TLV_SERVICE_COEX_GPIO = 85,
1994 WMI_TLV_SERVICE_AUX_SPECTRAL_INTF = 86,
1995 WMI_TLV_SERVICE_AUX_CHAN_LOAD_INTF = 87,
1996 WMI_TLV_SERVICE_BSS_CHANNEL_INFO_64 = 88,
1997 WMI_TLV_SERVICE_ENTERPRISE_MESH = 89,
1998 WMI_TLV_SERVICE_RESTRT_CHNL_SUPPORT = 90,
1999 WMI_TLV_SERVICE_BPF_OFFLOAD = 91,
2000 WMI_TLV_SERVICE_SYNC_DELETE_CMDS = 92,
2001 WMI_TLV_SERVICE_SMART_ANTENNA_SW_SUPPORT = 93,
2002 WMI_TLV_SERVICE_SMART_ANTENNA_HW_SUPPORT = 94,
2003 WMI_TLV_SERVICE_RATECTRL_LIMIT_MAX_MIN_RATES = 95,
2004 WMI_TLV_SERVICE_NAN_DATA = 96,
2005 WMI_TLV_SERVICE_NAN_RTT = 97,
2006 WMI_TLV_SERVICE_11AX = 98,
2007 WMI_TLV_SERVICE_DEPRECATED_REPLACE = 99,
2008 WMI_TLV_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE = 100,
2009 WMI_TLV_SERVICE_ENHANCED_MCAST_FILTER = 101,
2010 WMI_TLV_SERVICE_PERIODIC_CHAN_STAT_SUPPORT = 102,
2011 WMI_TLV_SERVICE_MESH_11S = 103,
2012 WMI_TLV_SERVICE_HALF_RATE_QUARTER_RATE_SUPPORT = 104,
2013 WMI_TLV_SERVICE_VDEV_RX_FILTER = 105,
2014 WMI_TLV_SERVICE_P2P_LISTEN_OFFLOAD_SUPPORT = 106,
2015 WMI_TLV_SERVICE_MARK_FIRST_WAKEUP_PACKET = 107,
2016 WMI_TLV_SERVICE_MULTIPLE_MCAST_FILTER_SET = 108,
2017 WMI_TLV_SERVICE_HOST_MANAGED_RX_REORDER = 109,
2018 WMI_TLV_SERVICE_FLASH_RDWR_SUPPORT = 110,
2019 WMI_TLV_SERVICE_WLAN_STATS_REPORT = 111,
2020 WMI_TLV_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT = 112,
2021 WMI_TLV_SERVICE_DFS_PHYERR_OFFLOAD = 113,
2022 WMI_TLV_SERVICE_RCPI_SUPPORT = 114,
2023 WMI_TLV_SERVICE_FW_MEM_DUMP_SUPPORT = 115,
2024 WMI_TLV_SERVICE_PEER_STATS_INFO = 116,
2025 WMI_TLV_SERVICE_REGULATORY_DB = 117,
2026 WMI_TLV_SERVICE_11D_OFFLOAD = 118,
2027 WMI_TLV_SERVICE_HW_DATA_FILTERING = 119,
2028 WMI_TLV_SERVICE_MULTIPLE_VDEV_RESTART = 120,
2029 WMI_TLV_SERVICE_PKT_ROUTING = 121,
2030 WMI_TLV_SERVICE_CHECK_CAL_VERSION = 122,
2031 WMI_TLV_SERVICE_OFFCHAN_TX_WMI = 123,
2032 WMI_TLV_SERVICE_8SS_TX_BFEE = 124,
2033 WMI_TLV_SERVICE_EXTENDED_NSS_SUPPORT = 125,
2034 WMI_TLV_SERVICE_ACK_TIMEOUT = 126,
2035 WMI_TLV_SERVICE_PDEV_BSS_CHANNEL_INFO_64 = 127,
2036
2037 /* The first 128 bits */
2038 WMI_MAX_SERVICE = 128,
2039
2040 WMI_TLV_SERVICE_CHAN_LOAD_INFO = 128,
2041 WMI_TLV_SERVICE_TX_PPDU_INFO_STATS_SUPPORT = 129,
2042 WMI_TLV_SERVICE_VDEV_LIMIT_OFFCHAN_SUPPORT = 130,
2043 WMI_TLV_SERVICE_FILS_SUPPORT = 131,
2044 WMI_TLV_SERVICE_WLAN_OIC_PING_OFFLOAD = 132,
2045 WMI_TLV_SERVICE_WLAN_DHCP_RENEW = 133,
2046 WMI_TLV_SERVICE_MAWC_SUPPORT = 134,
2047 WMI_TLV_SERVICE_VDEV_LATENCY_CONFIG = 135,
2048 WMI_TLV_SERVICE_PDEV_UPDATE_CTLTABLE_SUPPORT = 136,
2049 WMI_TLV_SERVICE_PKTLOG_SUPPORT_OVER_HTT = 137,
2050 WMI_TLV_SERVICE_VDEV_MULTI_GROUP_KEY_SUPPORT = 138,
2051 WMI_TLV_SERVICE_SCAN_PHYMODE_SUPPORT = 139,
2052 WMI_TLV_SERVICE_THERM_THROT = 140,
2053 WMI_TLV_SERVICE_BCN_OFFLOAD_START_STOP_SUPPORT = 141,
2054 WMI_TLV_SERVICE_WOW_WAKEUP_BY_TIMER_PATTERN = 142,
2055 WMI_TLV_SERVICE_PEER_MAP_UNMAP_V2_SUPPORT = 143,
2056 WMI_TLV_SERVICE_OFFCHAN_DATA_TID_SUPPORT = 144,
2057 WMI_TLV_SERVICE_RX_PROMISC_ENABLE_SUPPORT = 145,
2058 WMI_TLV_SERVICE_SUPPORT_DIRECT_DMA = 146,
2059 WMI_TLV_SERVICE_AP_OBSS_DETECTION_OFFLOAD = 147,
2060 WMI_TLV_SERVICE_11K_NEIGHBOUR_REPORT_SUPPORT = 148,
2061 WMI_TLV_SERVICE_LISTEN_INTERVAL_OFFLOAD_SUPPORT = 149,
2062 WMI_TLV_SERVICE_BSS_COLOR_OFFLOAD = 150,
2063 WMI_TLV_SERVICE_RUNTIME_DPD_RECAL = 151,
2064 WMI_TLV_SERVICE_STA_TWT = 152,
2065 WMI_TLV_SERVICE_AP_TWT = 153,
2066 WMI_TLV_SERVICE_GMAC_OFFLOAD_SUPPORT = 154,
2067 WMI_TLV_SERVICE_SPOOF_MAC_SUPPORT = 155,
2068 WMI_TLV_SERVICE_PEER_TID_CONFIGS_SUPPORT = 156,
2069 WMI_TLV_SERVICE_VDEV_SWRETRY_PER_AC_CONFIG_SUPPORT = 157,
2070 WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_SCC_SUPPORT = 158,
2071 WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_MCC_SUPPORT = 159,
2072 WMI_TLV_SERVICE_MOTION_DET = 160,
2073 WMI_TLV_SERVICE_INFRA_MBSSID = 161,
2074 WMI_TLV_SERVICE_OBSS_SPATIAL_REUSE = 162,
2075 WMI_TLV_SERVICE_VDEV_DIFFERENT_BEACON_INTERVAL_SUPPORT = 163,
2076 WMI_TLV_SERVICE_NAN_DBS_SUPPORT = 164,
2077 WMI_TLV_SERVICE_NDI_DBS_SUPPORT = 165,
2078 WMI_TLV_SERVICE_NAN_SAP_SUPPORT = 166,
2079 WMI_TLV_SERVICE_NDI_SAP_SUPPORT = 167,
2080 WMI_TLV_SERVICE_CFR_CAPTURE_SUPPORT = 168,
2081 WMI_TLV_SERVICE_CFR_CAPTURE_IND_MSG_TYPE_1 = 169,
2082 WMI_TLV_SERVICE_ESP_SUPPORT = 170,
2083 WMI_TLV_SERVICE_PEER_CHWIDTH_CHANGE = 171,
2084 WMI_TLV_SERVICE_WLAN_HPCS_PULSE = 172,
2085 WMI_TLV_SERVICE_PER_VDEV_CHAINMASK_CONFIG_SUPPORT = 173,
2086 WMI_TLV_SERVICE_TX_DATA_MGMT_ACK_RSSI = 174,
2087 WMI_TLV_SERVICE_NAN_DISABLE_SUPPORT = 175,
2088 WMI_TLV_SERVICE_HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN = 176,
2089 WMI_TLV_SERVICE_COEX_SUPPORT_UNEQUAL_ISOLATION = 177,
2090 WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT = 178,
2091 WMI_TLV_SERVICE_SUPPORT_EXTEND_ADDRESS = 179,
2092 WMI_TLV_SERVICE_BEACON_RECEPTION_STATS = 180,
2093 WMI_TLV_SERVICE_FETCH_TX_PN = 181,
2094 WMI_TLV_SERVICE_PEER_UNMAP_RESPONSE_SUPPORT = 182,
2095 WMI_TLV_SERVICE_TX_PER_PEER_AMPDU_SIZE = 183,
2096 WMI_TLV_SERVICE_BSS_COLOR_SWITCH_COUNT = 184,
2097 WMI_TLV_SERVICE_HTT_PEER_STATS_SUPPORT = 185,
2098 WMI_TLV_SERVICE_UL_RU26_ALLOWED = 186,
2099 WMI_TLV_SERVICE_GET_MWS_COEX_STATE = 187,
2100 WMI_TLV_SERVICE_GET_MWS_DPWB_STATE = 188,
2101 WMI_TLV_SERVICE_GET_MWS_TDM_STATE = 189,
2102 WMI_TLV_SERVICE_GET_MWS_IDRX_STATE = 190,
2103 WMI_TLV_SERVICE_GET_MWS_ANTENNA_SHARING_STATE = 191,
2104 WMI_TLV_SERVICE_ENHANCED_TPC_CONFIG_EVENT = 192,
2105 WMI_TLV_SERVICE_WLM_STATS_REQUEST = 193,
2106 WMI_TLV_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT = 194,
2107 WMI_TLV_SERVICE_WPA3_FT_SAE_SUPPORT = 195,
2108 WMI_TLV_SERVICE_WPA3_FT_SUITE_B_SUPPORT = 196,
2109 WMI_TLV_SERVICE_VOW_ENABLE = 197,
2110 WMI_TLV_SERVICE_CFR_CAPTURE_IND_EVT_TYPE_1 = 198,
2111 WMI_TLV_SERVICE_BROADCAST_TWT = 199,
2112 WMI_TLV_SERVICE_RAP_DETECTION_SUPPORT = 200,
2113 WMI_TLV_SERVICE_PS_TDCC = 201,
2114 WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_LEGACY = 202,
2115 WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_OVERRIDE = 203,
2116 WMI_TLV_SERVICE_TX_PWR_PER_PEER = 204,
2117 WMI_TLV_SERVICE_STA_PLUS_STA_SUPPORT = 205,
2118 WMI_TLV_SERVICE_WPA3_FT_FILS = 206,
2119 WMI_TLV_SERVICE_ADAPTIVE_11R_ROAM = 207,
2120 WMI_TLV_SERVICE_CHAN_RF_CHARACTERIZATION_INFO = 208,
2121 WMI_TLV_SERVICE_FW_IFACE_COMBINATION_SUPPORT = 209,
2122 WMI_TLV_SERVICE_TX_COMPL_TSF64 = 210,
2123 WMI_TLV_SERVICE_DSM_ROAM_FILTER = 211,
2124 WMI_TLV_SERVICE_PACKET_CAPTURE_SUPPORT = 212,
2125 WMI_TLV_SERVICE_PER_PEER_HTT_STATS_RESET = 213,
2126 WMI_TLV_SERVICE_FREQINFO_IN_METADATA = 219,
2127 WMI_TLV_SERVICE_EXT2_MSG = 220,
2128 WMI_TLV_SERVICE_PEER_POWER_SAVE_DURATION_SUPPORT = 246,
2129 WMI_TLV_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT = 249,
2130 WMI_TLV_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT = 253,
2131 WMI_TLV_SERVICE_PASSIVE_SCAN_START_TIME_ENHANCE = 263,
2132
2133 /* The second 128 bits */
2134 WMI_MAX_EXT_SERVICE = 256,
2135 WMI_TLV_SERVICE_SCAN_CONFIG_PER_CHANNEL = 265,
2136 WMI_TLV_SERVICE_EXT_TPC_REG_SUPPORT = 280,
2137 WMI_TLV_SERVICE_REG_CC_EXT_EVENT_SUPPORT = 281,
2138 WMI_TLV_SERVICE_BIOS_SAR_SUPPORT = 326,
2139 WMI_TLV_SERVICE_SUPPORT_11D_FOR_HOST_SCAN = 357,
2140
2141 /* The third 128 bits */
2142 WMI_MAX_EXT2_SERVICE = 384
2143};
2144
2145enum {
2146 WMI_SMPS_FORCED_MODE_NONE = 0,
2147 WMI_SMPS_FORCED_MODE_DISABLED,
2148 WMI_SMPS_FORCED_MODE_STATIC,
2149 WMI_SMPS_FORCED_MODE_DYNAMIC
2150};
2151
2152#define WMI_TPC_CHAINMASK_CONFIG_BAND_2G 0
2153#define WMI_TPC_CHAINMASK_CONFIG_BAND_5G 1
2154#define WMI_NUM_SUPPORTED_BAND_MAX 2
2155
2156#define WMI_PEER_MIMO_PS_STATE 0x1
2157#define WMI_PEER_AMPDU 0x2
2158#define WMI_PEER_AUTHORIZE 0x3
2159#define WMI_PEER_CHWIDTH 0x4
2160#define WMI_PEER_NSS 0x5
2161#define WMI_PEER_USE_4ADDR 0x6
2162#define WMI_PEER_MEMBERSHIP 0x7
2163#define WMI_PEER_USERPOS 0x8
2164#define WMI_PEER_CRIT_PROTO_HINT_ENABLED 0x9
2165#define WMI_PEER_TX_FAIL_CNT_THR 0xA
2166#define WMI_PEER_SET_HW_RETRY_CTS2S 0xB
2167#define WMI_PEER_IBSS_ATIM_WINDOW_LENGTH 0xC
2168#define WMI_PEER_PHYMODE 0xD
2169#define WMI_PEER_USE_FIXED_PWR 0xE
2170#define WMI_PEER_PARAM_FIXED_RATE 0xF
2171#define WMI_PEER_SET_MU_WHITELIST 0x10
2172#define WMI_PEER_SET_MAX_TX_RATE 0x11
2173#define WMI_PEER_SET_MIN_TX_RATE 0x12
2174#define WMI_PEER_SET_DEFAULT_ROUTING 0x13
2175
2176/* slot time long */
2177#define WMI_VDEV_SLOT_TIME_LONG 0x1
2178/* slot time short */
2179#define WMI_VDEV_SLOT_TIME_SHORT 0x2
2180/* preablbe long */
2181#define WMI_VDEV_PREAMBLE_LONG 0x1
2182/* preablbe short */
2183#define WMI_VDEV_PREAMBLE_SHORT 0x2
2184
2185enum wmi_peer_smps_state {
2186 WMI_PEER_SMPS_PS_NONE = 0x0,
2187 WMI_PEER_SMPS_STATIC = 0x1,
2188 WMI_PEER_SMPS_DYNAMIC = 0x2
2189};
2190
2191enum wmi_peer_chwidth {
2192 WMI_PEER_CHWIDTH_20MHZ = 0,
2193 WMI_PEER_CHWIDTH_40MHZ = 1,
2194 WMI_PEER_CHWIDTH_80MHZ = 2,
2195 WMI_PEER_CHWIDTH_160MHZ = 3,
2196};
2197
2198enum wmi_beacon_gen_mode {
2199 WMI_BEACON_STAGGERED_MODE = 0,
2200 WMI_BEACON_BURST_MODE = 1
2201};
2202
2203enum wmi_direct_buffer_module {
2204 WMI_DIRECT_BUF_SPECTRAL = 0,
2205 WMI_DIRECT_BUF_CFR = 1,
2206
2207 /* keep it last */
2208 WMI_DIRECT_BUF_MAX
2209};
2210
2211/* enum wmi_nss_ratio - NSS ratio received from FW during service ready ext
2212 * event
2213 * WMI_NSS_RATIO_1BY2_NSS -Max nss of 160MHz is equals to half of the max nss
2214 * of 80MHz
2215 * WMI_NSS_RATIO_3BY4_NSS - Max nss of 160MHz is equals to 3/4 of the max nss
2216 * of 80MHz
2217 * WMI_NSS_RATIO_1_NSS - Max nss of 160MHz is equals to the max nss of 80MHz
2218 * WMI_NSS_RATIO_2_NSS - Max nss of 160MHz is equals to two times the max
2219 * nss of 80MHz
2220 */
2221
2222enum wmi_nss_ratio {
2223 WMI_NSS_RATIO_1BY2_NSS = 0x0,
2224 WMI_NSS_RATIO_3BY4_NSS = 0x1,
2225 WMI_NSS_RATIO_1_NSS = 0x2,
2226 WMI_NSS_RATIO_2_NSS = 0x3,
2227};
2228
2229enum wmi_dtim_policy {
2230 WMI_DTIM_POLICY_IGNORE = 1,
2231 WMI_DTIM_POLICY_NORMAL = 2,
2232 WMI_DTIM_POLICY_STICK = 3,
2233 WMI_DTIM_POLICY_AUTO = 4,
2234};
2235
2236struct wmi_host_pdev_band_to_mac {
2237 u32 pdev_id;
2238 u32 start_freq;
2239 u32 end_freq;
2240};
2241
2242struct ath11k_ppe_threshold {
2243 u32 numss_m1;
2244 u32 ru_bit_mask;
2245 u32 ppet16_ppet8_ru3_ru0[PSOC_HOST_MAX_NUM_SS];
2246};
2247
2248struct ath11k_service_ext_param {
2249 u32 default_conc_scan_config_bits;
2250 u32 default_fw_config_bits;
2251 struct ath11k_ppe_threshold ppet;
2252 u32 he_cap_info;
2253 u32 mpdu_density;
2254 u32 max_bssid_rx_filters;
2255 u32 num_hw_modes;
2256 u32 num_phy;
2257};
2258
2259struct ath11k_hw_mode_caps {
2260 u32 hw_mode_id;
2261 u32 phy_id_map;
2262 u32 hw_mode_config_type;
2263};
2264
2265#define PSOC_HOST_MAX_PHY_SIZE (3)
2266#define ATH11K_11B_SUPPORT BIT(0)
2267#define ATH11K_11G_SUPPORT BIT(1)
2268#define ATH11K_11A_SUPPORT BIT(2)
2269#define ATH11K_11N_SUPPORT BIT(3)
2270#define ATH11K_11AC_SUPPORT BIT(4)
2271#define ATH11K_11AX_SUPPORT BIT(5)
2272
2273struct ath11k_hal_reg_capabilities_ext {
2274 u32 phy_id;
2275 u32 eeprom_reg_domain;
2276 u32 eeprom_reg_domain_ext;
2277 u32 regcap1;
2278 u32 regcap2;
2279 u32 wireless_modes;
2280 u32 low_2ghz_chan;
2281 u32 high_2ghz_chan;
2282 u32 low_5ghz_chan;
2283 u32 high_5ghz_chan;
2284};
2285
2286#define WMI_HOST_MAX_PDEV 3
2287
2288struct wlan_host_mem_chunk {
2289 u32 tlv_header;
2290 u32 req_id;
2291 u32 ptr;
2292 u32 size;
2293} __packed;
2294
2295struct wmi_host_mem_chunk {
2296 void *vaddr;
2297 dma_addr_t paddr;
2298 u32 len;
2299 u32 req_id;
2300};
2301
2302struct wmi_init_cmd_param {
2303 u32 tlv_header;
2304 struct target_resource_config *res_cfg;
2305 u8 num_mem_chunks;
2306 struct wmi_host_mem_chunk *mem_chunks;
2307 u32 hw_mode_id;
2308 u32 num_band_to_mac;
2309 struct wmi_host_pdev_band_to_mac band_to_mac[WMI_HOST_MAX_PDEV];
2310};
2311
2312struct wmi_pdev_band_to_mac {
2313 u32 tlv_header;
2314 u32 pdev_id;
2315 u32 start_freq;
2316 u32 end_freq;
2317} __packed;
2318
2319struct wmi_pdev_set_hw_mode_cmd_param {
2320 u32 tlv_header;
2321 u32 pdev_id;
2322 u32 hw_mode_index;
2323 u32 num_band_to_mac;
2324} __packed;
2325
2326struct wmi_ppe_threshold {
2327 u32 numss_m1; /** NSS - 1*/
2328 union {
2329 u32 ru_count;
2330 u32 ru_mask;
2331 } __packed;
2332 u32 ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS];
2333} __packed;
2334
2335#define HW_BD_INFO_SIZE 5
2336
2337struct wmi_abi_version {
2338 u32 abi_version_0;
2339 u32 abi_version_1;
2340 u32 abi_version_ns_0;
2341 u32 abi_version_ns_1;
2342 u32 abi_version_ns_2;
2343 u32 abi_version_ns_3;
2344} __packed;
2345
2346struct wmi_init_cmd {
2347 u32 tlv_header;
2348 struct wmi_abi_version host_abi_vers;
2349 u32 num_host_mem_chunks;
2350} __packed;
2351
2352#define WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64 BIT(5)
2353#define WMI_RSRC_CFG_FLAG2_CALC_NEXT_DTIM_COUNT_SET BIT(9)
2354#define WMI_RSRC_CFG_FLAG1_ACK_RSSI BIT(18)
2355
2356#define WMI_CFG_HOST_SERVICE_FLAG_REG_CC_EXT 4
2357
2358struct wmi_resource_config {
2359 u32 tlv_header;
2360 u32 num_vdevs;
2361 u32 num_peers;
2362 u32 num_offload_peers;
2363 u32 num_offload_reorder_buffs;
2364 u32 num_peer_keys;
2365 u32 num_tids;
2366 u32 ast_skid_limit;
2367 u32 tx_chain_mask;
2368 u32 rx_chain_mask;
2369 u32 rx_timeout_pri[4];
2370 u32 rx_decap_mode;
2371 u32 scan_max_pending_req;
2372 u32 bmiss_offload_max_vdev;
2373 u32 roam_offload_max_vdev;
2374 u32 roam_offload_max_ap_profiles;
2375 u32 num_mcast_groups;
2376 u32 num_mcast_table_elems;
2377 u32 mcast2ucast_mode;
2378 u32 tx_dbg_log_size;
2379 u32 num_wds_entries;
2380 u32 dma_burst_size;
2381 u32 mac_aggr_delim;
2382 u32 rx_skip_defrag_timeout_dup_detection_check;
2383 u32 vow_config;
2384 u32 gtk_offload_max_vdev;
2385 u32 num_msdu_desc;
2386 u32 max_frag_entries;
2387 u32 num_tdls_vdevs;
2388 u32 num_tdls_conn_table_entries;
2389 u32 beacon_tx_offload_max_vdev;
2390 u32 num_multicast_filter_entries;
2391 u32 num_wow_filters;
2392 u32 num_keep_alive_pattern;
2393 u32 keep_alive_pattern_size;
2394 u32 max_tdls_concurrent_sleep_sta;
2395 u32 max_tdls_concurrent_buffer_sta;
2396 u32 wmi_send_separate;
2397 u32 num_ocb_vdevs;
2398 u32 num_ocb_channels;
2399 u32 num_ocb_schedules;
2400 u32 flag1;
2401 u32 smart_ant_cap;
2402 u32 bk_minfree;
2403 u32 be_minfree;
2404 u32 vi_minfree;
2405 u32 vo_minfree;
2406 u32 alloc_frag_desc_for_data_pkt;
2407 u32 num_ns_ext_tuples_cfg;
2408 u32 bpf_instruction_size;
2409 u32 max_bssid_rx_filters;
2410 u32 use_pdev_id;
2411 u32 max_num_dbs_scan_duty_cycle;
2412 u32 max_num_group_keys;
2413 u32 peer_map_unmap_v2_support;
2414 u32 sched_params;
2415 u32 twt_ap_pdev_count;
2416 u32 twt_ap_sta_count;
2417 u32 max_nlo_ssids;
2418 u32 num_pkt_filters;
2419 u32 num_max_sta_vdevs;
2420 u32 max_bssid_indicator;
2421 u32 ul_resp_config;
2422 u32 msdu_flow_override_config0;
2423 u32 msdu_flow_override_config1;
2424 u32 flags2;
2425 u32 host_service_flags;
2426 u32 max_rnr_neighbours;
2427 u32 ema_max_vap_cnt;
2428 u32 ema_max_profile_period;
2429} __packed;
2430
2431struct wmi_service_ready_event {
2432 u32 fw_build_vers;
2433 struct wmi_abi_version fw_abi_vers;
2434 u32 phy_capability;
2435 u32 max_frag_entry;
2436 u32 num_rf_chains;
2437 u32 ht_cap_info;
2438 u32 vht_cap_info;
2439 u32 vht_supp_mcs;
2440 u32 hw_min_tx_power;
2441 u32 hw_max_tx_power;
2442 u32 sys_cap_info;
2443 u32 min_pkt_size_enable;
2444 u32 max_bcn_ie_size;
2445 u32 num_mem_reqs;
2446 u32 max_num_scan_channels;
2447 u32 hw_bd_id;
2448 u32 hw_bd_info[HW_BD_INFO_SIZE];
2449 u32 max_supported_macs;
2450 u32 wmi_fw_sub_feat_caps;
2451 u32 num_dbs_hw_modes;
2452 /* txrx_chainmask
2453 * [7:0] - 2G band tx chain mask
2454 * [15:8] - 2G band rx chain mask
2455 * [23:16] - 5G band tx chain mask
2456 * [31:24] - 5G band rx chain mask
2457 */
2458 u32 txrx_chainmask;
2459 u32 default_dbs_hw_mode_index;
2460 u32 num_msdu_desc;
2461} __packed;
2462
2463#define WMI_SERVICE_BM_SIZE ((WMI_MAX_SERVICE + sizeof(u32) - 1) / sizeof(u32))
2464
2465#define WMI_SERVICE_SEGMENT_BM_SIZE32 4 /* 4x u32 = 128 bits */
2466#define WMI_SERVICE_EXT_BM_SIZE (WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(u32))
2467#define WMI_AVAIL_SERVICE_BITS_IN_SIZE32 32
2468#define WMI_SERVICE_BITS_IN_SIZE32 4
2469
2470struct wmi_service_ready_ext_event {
2471 u32 default_conc_scan_config_bits;
2472 u32 default_fw_config_bits;
2473 struct wmi_ppe_threshold ppet;
2474 u32 he_cap_info;
2475 u32 mpdu_density;
2476 u32 max_bssid_rx_filters;
2477 u32 fw_build_vers_ext;
2478 u32 max_nlo_ssids;
2479 u32 max_bssid_indicator;
2480 u32 he_cap_info_ext;
2481} __packed;
2482
2483struct wmi_soc_mac_phy_hw_mode_caps {
2484 u32 num_hw_modes;
2485 u32 num_chainmask_tables;
2486} __packed;
2487
2488struct wmi_hw_mode_capabilities {
2489 u32 tlv_header;
2490 u32 hw_mode_id;
2491 u32 phy_id_map;
2492 u32 hw_mode_config_type;
2493} __packed;
2494
2495#define WMI_MAX_HECAP_PHY_SIZE (3)
2496#define WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS BIT(0)
2497#define WMI_NSS_RATIO_ENABLE_DISABLE_GET(_val) \
2498 FIELD_GET(WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS, _val)
2499#define WMI_NSS_RATIO_INFO_BITPOS GENMASK(4, 1)
2500#define WMI_NSS_RATIO_INFO_GET(_val) \
2501 FIELD_GET(WMI_NSS_RATIO_INFO_BITPOS, _val)
2502
2503struct wmi_mac_phy_capabilities {
2504 u32 hw_mode_id;
2505 u32 pdev_id;
2506 u32 phy_id;
2507 u32 supported_flags;
2508 u32 supported_bands;
2509 u32 ampdu_density;
2510 u32 max_bw_supported_2g;
2511 u32 ht_cap_info_2g;
2512 u32 vht_cap_info_2g;
2513 u32 vht_supp_mcs_2g;
2514 u32 he_cap_info_2g;
2515 u32 he_supp_mcs_2g;
2516 u32 tx_chain_mask_2g;
2517 u32 rx_chain_mask_2g;
2518 u32 max_bw_supported_5g;
2519 u32 ht_cap_info_5g;
2520 u32 vht_cap_info_5g;
2521 u32 vht_supp_mcs_5g;
2522 u32 he_cap_info_5g;
2523 u32 he_supp_mcs_5g;
2524 u32 tx_chain_mask_5g;
2525 u32 rx_chain_mask_5g;
2526 u32 he_cap_phy_info_2g[WMI_MAX_HECAP_PHY_SIZE];
2527 u32 he_cap_phy_info_5g[WMI_MAX_HECAP_PHY_SIZE];
2528 struct wmi_ppe_threshold he_ppet2g;
2529 struct wmi_ppe_threshold he_ppet5g;
2530 u32 chainmask_table_id;
2531 u32 lmac_id;
2532 u32 he_cap_info_2g_ext;
2533 u32 he_cap_info_5g_ext;
2534 u32 he_cap_info_internal;
2535 u32 wireless_modes;
2536 u32 low_2ghz_chan_freq;
2537 u32 high_2ghz_chan_freq;
2538 u32 low_5ghz_chan_freq;
2539 u32 high_5ghz_chan_freq;
2540 u32 nss_ratio;
2541} __packed;
2542
2543struct wmi_hal_reg_capabilities_ext {
2544 u32 tlv_header;
2545 u32 phy_id;
2546 u32 eeprom_reg_domain;
2547 u32 eeprom_reg_domain_ext;
2548 u32 regcap1;
2549 u32 regcap2;
2550 u32 wireless_modes;
2551 u32 low_2ghz_chan;
2552 u32 high_2ghz_chan;
2553 u32 low_5ghz_chan;
2554 u32 high_5ghz_chan;
2555} __packed;
2556
2557struct wmi_soc_hal_reg_capabilities {
2558 u32 num_phy;
2559} __packed;
2560
2561/* 2 word representation of MAC addr */
2562struct wmi_mac_addr {
2563 union {
2564 u8 addr[6];
2565 struct {
2566 u32 word0;
2567 u32 word1;
2568 } __packed;
2569 } __packed;
2570} __packed;
2571
2572struct wmi_dma_ring_capabilities {
2573 u32 tlv_header;
2574 u32 pdev_id;
2575 u32 module_id;
2576 u32 min_elem;
2577 u32 min_buf_sz;
2578 u32 min_buf_align;
2579} __packed;
2580
2581struct wmi_ready_event_min {
2582 struct wmi_abi_version fw_abi_vers;
2583 struct wmi_mac_addr mac_addr;
2584 u32 status;
2585 u32 num_dscp_table;
2586 u32 num_extra_mac_addr;
2587 u32 num_total_peers;
2588 u32 num_extra_peers;
2589} __packed;
2590
2591struct wmi_ready_event {
2592 struct wmi_ready_event_min ready_event_min;
2593 u32 max_ast_index;
2594 u32 pktlog_defs_checksum;
2595} __packed;
2596
2597struct wmi_service_available_event {
2598 u32 wmi_service_segment_offset;
2599 u32 wmi_service_segment_bitmap[WMI_SERVICE_SEGMENT_BM_SIZE32];
2600} __packed;
2601
2602struct ath11k_pdev_wmi {
2603 struct ath11k_wmi_base *wmi_ab;
2604 enum ath11k_htc_ep_id eid;
2605 u32 rx_decap_mode;
2606 wait_queue_head_t tx_ce_desc_wq;
2607};
2608
2609struct vdev_create_params {
2610 u8 if_id;
2611 u32 type;
2612 u32 subtype;
2613 struct {
2614 u8 tx;
2615 u8 rx;
2616 } chains[NUM_NL80211_BANDS];
2617 u32 pdev_id;
2618 u32 mbssid_flags;
2619 u32 mbssid_tx_vdev_id;
2620};
2621
2622struct wmi_vdev_create_cmd {
2623 u32 tlv_header;
2624 u32 vdev_id;
2625 u32 vdev_type;
2626 u32 vdev_subtype;
2627 struct wmi_mac_addr vdev_macaddr;
2628 u32 num_cfg_txrx_streams;
2629 u32 pdev_id;
2630 u32 mbssid_flags;
2631 u32 mbssid_tx_vdev_id;
2632} __packed;
2633
2634struct wmi_vdev_txrx_streams {
2635 u32 tlv_header;
2636 u32 band;
2637 u32 supported_tx_streams;
2638 u32 supported_rx_streams;
2639} __packed;
2640
2641struct wmi_vdev_delete_cmd {
2642 u32 tlv_header;
2643 u32 vdev_id;
2644} __packed;
2645
2646struct wmi_vdev_up_cmd {
2647 u32 tlv_header;
2648 u32 vdev_id;
2649 u32 vdev_assoc_id;
2650 struct wmi_mac_addr vdev_bssid;
2651 struct wmi_mac_addr tx_vdev_bssid;
2652 u32 nontx_profile_idx;
2653 u32 nontx_profile_cnt;
2654} __packed;
2655
2656struct wmi_vdev_stop_cmd {
2657 u32 tlv_header;
2658 u32 vdev_id;
2659} __packed;
2660
2661struct wmi_vdev_down_cmd {
2662 u32 tlv_header;
2663 u32 vdev_id;
2664} __packed;
2665
2666#define WMI_VDEV_START_HIDDEN_SSID BIT(0)
2667#define WMI_VDEV_START_PMF_ENABLED BIT(1)
2668#define WMI_VDEV_START_LDPC_RX_ENABLED BIT(3)
2669#define WMI_VDEV_START_HW_ENCRYPTION_DISABLED BIT(4)
2670
2671struct wmi_ssid {
2672 u32 ssid_len;
2673 u32 ssid[8];
2674} __packed;
2675
2676#define ATH11K_VDEV_SETUP_TIMEOUT_HZ (1 * HZ)
2677
2678struct wmi_vdev_start_request_cmd {
2679 u32 tlv_header;
2680 u32 vdev_id;
2681 u32 requestor_id;
2682 u32 beacon_interval;
2683 u32 dtim_period;
2684 u32 flags;
2685 struct wmi_ssid ssid;
2686 u32 bcn_tx_rate;
2687 u32 bcn_txpower;
2688 u32 num_noa_descriptors;
2689 u32 disable_hw_ack;
2690 u32 preferred_tx_streams;
2691 u32 preferred_rx_streams;
2692 u32 he_ops;
2693 u32 cac_duration_ms;
2694 u32 regdomain;
2695 u32 min_data_rate;
2696 u32 mbssid_flags;
2697 u32 mbssid_tx_vdev_id;
2698} __packed;
2699
2700#define MGMT_TX_DL_FRM_LEN 64
2701#define WMI_MAC_MAX_SSID_LENGTH 32
2702struct mac_ssid {
2703 u8 length;
2704 u8 mac_ssid[WMI_MAC_MAX_SSID_LENGTH];
2705} __packed;
2706
2707struct wmi_p2p_noa_descriptor {
2708 u32 type_count;
2709 u32 duration;
2710 u32 interval;
2711 u32 start_time;
2712};
2713
2714struct channel_param {
2715 u8 chan_id;
2716 u8 pwr;
2717 u32 mhz;
2718 u32 half_rate:1,
2719 quarter_rate:1,
2720 dfs_set:1,
2721 dfs_set_cfreq2:1,
2722 is_chan_passive:1,
2723 allow_ht:1,
2724 allow_vht:1,
2725 allow_he:1,
2726 set_agile:1,
2727 psc_channel:1;
2728 u32 phy_mode;
2729 u32 cfreq1;
2730 u32 cfreq2;
2731 char maxpower;
2732 char minpower;
2733 char maxregpower;
2734 u8 antennamax;
2735 u8 reg_class_id;
2736} __packed;
2737
2738enum wmi_phy_mode {
2739 MODE_11A = 0,
2740 MODE_11G = 1, /* 11b/g Mode */
2741 MODE_11B = 2, /* 11b Mode */
2742 MODE_11GONLY = 3, /* 11g only Mode */
2743 MODE_11NA_HT20 = 4,
2744 MODE_11NG_HT20 = 5,
2745 MODE_11NA_HT40 = 6,
2746 MODE_11NG_HT40 = 7,
2747 MODE_11AC_VHT20 = 8,
2748 MODE_11AC_VHT40 = 9,
2749 MODE_11AC_VHT80 = 10,
2750 MODE_11AC_VHT20_2G = 11,
2751 MODE_11AC_VHT40_2G = 12,
2752 MODE_11AC_VHT80_2G = 13,
2753 MODE_11AC_VHT80_80 = 14,
2754 MODE_11AC_VHT160 = 15,
2755 MODE_11AX_HE20 = 16,
2756 MODE_11AX_HE40 = 17,
2757 MODE_11AX_HE80 = 18,
2758 MODE_11AX_HE80_80 = 19,
2759 MODE_11AX_HE160 = 20,
2760 MODE_11AX_HE20_2G = 21,
2761 MODE_11AX_HE40_2G = 22,
2762 MODE_11AX_HE80_2G = 23,
2763 MODE_UNKNOWN = 24,
2764 MODE_MAX = 24
2765};
2766
2767static inline const char *ath11k_wmi_phymode_str(enum wmi_phy_mode mode)
2768{
2769 switch (mode) {
2770 case MODE_11A:
2771 return "11a";
2772 case MODE_11G:
2773 return "11g";
2774 case MODE_11B:
2775 return "11b";
2776 case MODE_11GONLY:
2777 return "11gonly";
2778 case MODE_11NA_HT20:
2779 return "11na-ht20";
2780 case MODE_11NG_HT20:
2781 return "11ng-ht20";
2782 case MODE_11NA_HT40:
2783 return "11na-ht40";
2784 case MODE_11NG_HT40:
2785 return "11ng-ht40";
2786 case MODE_11AC_VHT20:
2787 return "11ac-vht20";
2788 case MODE_11AC_VHT40:
2789 return "11ac-vht40";
2790 case MODE_11AC_VHT80:
2791 return "11ac-vht80";
2792 case MODE_11AC_VHT160:
2793 return "11ac-vht160";
2794 case MODE_11AC_VHT80_80:
2795 return "11ac-vht80+80";
2796 case MODE_11AC_VHT20_2G:
2797 return "11ac-vht20-2g";
2798 case MODE_11AC_VHT40_2G:
2799 return "11ac-vht40-2g";
2800 case MODE_11AC_VHT80_2G:
2801 return "11ac-vht80-2g";
2802 case MODE_11AX_HE20:
2803 return "11ax-he20";
2804 case MODE_11AX_HE40:
2805 return "11ax-he40";
2806 case MODE_11AX_HE80:
2807 return "11ax-he80";
2808 case MODE_11AX_HE80_80:
2809 return "11ax-he80+80";
2810 case MODE_11AX_HE160:
2811 return "11ax-he160";
2812 case MODE_11AX_HE20_2G:
2813 return "11ax-he20-2g";
2814 case MODE_11AX_HE40_2G:
2815 return "11ax-he40-2g";
2816 case MODE_11AX_HE80_2G:
2817 return "11ax-he80-2g";
2818 case MODE_UNKNOWN:
2819 /* skip */
2820 break;
2821
2822 /* no default handler to allow compiler to check that the
2823 * enum is fully handled
2824 */
2825 }
2826
2827 return "<unknown>";
2828}
2829
2830struct wmi_channel_arg {
2831 u32 freq;
2832 u32 band_center_freq1;
2833 u32 band_center_freq2;
2834 bool passive;
2835 bool allow_ibss;
2836 bool allow_ht;
2837 bool allow_vht;
2838 bool ht40plus;
2839 bool chan_radar;
2840 bool freq2_radar;
2841 bool allow_he;
2842 u32 min_power;
2843 u32 max_power;
2844 u32 max_reg_power;
2845 u32 max_antenna_gain;
2846 enum wmi_phy_mode mode;
2847};
2848
2849struct wmi_vdev_start_req_arg {
2850 u32 vdev_id;
2851 struct wmi_channel_arg channel;
2852 u32 bcn_intval;
2853 u32 dtim_period;
2854 u8 *ssid;
2855 u32 ssid_len;
2856 u32 bcn_tx_rate;
2857 u32 bcn_tx_power;
2858 bool disable_hw_ack;
2859 bool hidden_ssid;
2860 bool pmf_enabled;
2861 u32 he_ops;
2862 u32 cac_duration_ms;
2863 u32 regdomain;
2864 u32 pref_rx_streams;
2865 u32 pref_tx_streams;
2866 u32 num_noa_descriptors;
2867 u32 min_data_rate;
2868 u32 mbssid_flags;
2869 u32 mbssid_tx_vdev_id;
2870};
2871
2872struct peer_create_params {
2873 const u8 *peer_addr;
2874 u32 peer_type;
2875 u32 vdev_id;
2876};
2877
2878struct peer_delete_params {
2879 u8 vdev_id;
2880};
2881
2882struct peer_flush_params {
2883 u32 peer_tid_bitmap;
2884 u8 vdev_id;
2885};
2886
2887struct pdev_set_regdomain_params {
2888 u16 current_rd_in_use;
2889 u16 current_rd_2g;
2890 u16 current_rd_5g;
2891 u32 ctl_2g;
2892 u32 ctl_5g;
2893 u8 dfs_domain;
2894 u32 pdev_id;
2895};
2896
2897struct rx_reorder_queue_remove_params {
2898 u8 *peer_macaddr;
2899 u16 vdev_id;
2900 u32 peer_tid_bitmap;
2901};
2902
2903#define WMI_HOST_PDEV_ID_SOC 0xFF
2904#define WMI_HOST_PDEV_ID_0 0
2905#define WMI_HOST_PDEV_ID_1 1
2906#define WMI_HOST_PDEV_ID_2 2
2907
2908#define WMI_PDEV_ID_SOC 0
2909#define WMI_PDEV_ID_1ST 1
2910#define WMI_PDEV_ID_2ND 2
2911#define WMI_PDEV_ID_3RD 3
2912
2913/* Freq units in MHz */
2914#define REG_RULE_START_FREQ 0x0000ffff
2915#define REG_RULE_END_FREQ 0xffff0000
2916#define REG_RULE_FLAGS 0x0000ffff
2917#define REG_RULE_MAX_BW 0x0000ffff
2918#define REG_RULE_REG_PWR 0x00ff0000
2919#define REG_RULE_ANT_GAIN 0xff000000
2920#define REG_RULE_PSD_INFO BIT(0)
2921#define REG_RULE_PSD_EIRP 0xff0000
2922
2923#define WMI_VDEV_PARAM_TXBF_SU_TX_BFEE BIT(0)
2924#define WMI_VDEV_PARAM_TXBF_MU_TX_BFEE BIT(1)
2925#define WMI_VDEV_PARAM_TXBF_SU_TX_BFER BIT(2)
2926#define WMI_VDEV_PARAM_TXBF_MU_TX_BFER BIT(3)
2927
2928#define HE_PHYCAP_BYTE_0 0
2929#define HE_PHYCAP_BYTE_1 1
2930#define HE_PHYCAP_BYTE_2 2
2931#define HE_PHYCAP_BYTE_3 3
2932#define HE_PHYCAP_BYTE_4 4
2933
2934#define HECAP_PHY_SU_BFER BIT(7)
2935#define HECAP_PHY_SU_BFEE BIT(0)
2936#define HECAP_PHY_MU_BFER BIT(1)
2937#define HECAP_PHY_UL_MUMIMO BIT(6)
2938#define HECAP_PHY_UL_MUOFDMA BIT(7)
2939
2940#define HECAP_PHY_SUBFMR_GET(hecap_phy) \
2941 FIELD_GET(HECAP_PHY_SU_BFER, hecap_phy[HE_PHYCAP_BYTE_3])
2942
2943#define HECAP_PHY_SUBFME_GET(hecap_phy) \
2944 FIELD_GET(HECAP_PHY_SU_BFEE, hecap_phy[HE_PHYCAP_BYTE_4])
2945
2946#define HECAP_PHY_MUBFMR_GET(hecap_phy) \
2947 FIELD_GET(HECAP_PHY_MU_BFER, hecap_phy[HE_PHYCAP_BYTE_4])
2948
2949#define HECAP_PHY_ULMUMIMO_GET(hecap_phy) \
2950 FIELD_GET(HECAP_PHY_UL_MUMIMO, hecap_phy[HE_PHYCAP_BYTE_2])
2951
2952#define HECAP_PHY_ULOFDMA_GET(hecap_phy) \
2953 FIELD_GET(HECAP_PHY_UL_MUOFDMA, hecap_phy[HE_PHYCAP_BYTE_2])
2954
2955#define HE_MODE_SU_TX_BFEE BIT(0)
2956#define HE_MODE_SU_TX_BFER BIT(1)
2957#define HE_MODE_MU_TX_BFEE BIT(2)
2958#define HE_MODE_MU_TX_BFER BIT(3)
2959#define HE_MODE_DL_OFDMA BIT(4)
2960#define HE_MODE_UL_OFDMA BIT(5)
2961#define HE_MODE_UL_MUMIMO BIT(6)
2962
2963#define HE_DL_MUOFDMA_ENABLE 1
2964#define HE_UL_MUOFDMA_ENABLE 1
2965#define HE_DL_MUMIMO_ENABLE 1
2966#define HE_UL_MUMIMO_ENABLE 1
2967#define HE_MU_BFEE_ENABLE 1
2968#define HE_SU_BFEE_ENABLE 1
2969#define HE_MU_BFER_ENABLE 1
2970#define HE_SU_BFER_ENABLE 1
2971
2972#define HE_VHT_SOUNDING_MODE_ENABLE 1
2973#define HE_SU_MU_SOUNDING_MODE_ENABLE 1
2974#define HE_TRIG_NONTRIG_SOUNDING_MODE_ENABLE 1
2975
2976/* HE or VHT Sounding */
2977#define HE_VHT_SOUNDING_MODE BIT(0)
2978/* SU or MU Sounding */
2979#define HE_SU_MU_SOUNDING_MODE BIT(2)
2980/* Trig or Non-Trig Sounding */
2981#define HE_TRIG_NONTRIG_SOUNDING_MODE BIT(3)
2982
2983#define WMI_TXBF_STS_CAP_OFFSET_LSB 4
2984#define WMI_TXBF_STS_CAP_OFFSET_MASK 0x70
2985#define WMI_BF_SOUND_DIM_OFFSET_LSB 8
2986#define WMI_BF_SOUND_DIM_OFFSET_MASK 0x700
2987
2988struct pdev_params {
2989 u32 param_id;
2990 u32 param_value;
2991};
2992
2993enum wmi_peer_type {
2994 WMI_PEER_TYPE_DEFAULT = 0,
2995 WMI_PEER_TYPE_BSS = 1,
2996 WMI_PEER_TYPE_TDLS = 2,
2997};
2998
2999struct wmi_peer_create_cmd {
3000 u32 tlv_header;
3001 u32 vdev_id;
3002 struct wmi_mac_addr peer_macaddr;
3003 u32 peer_type;
3004} __packed;
3005
3006struct wmi_peer_delete_cmd {
3007 u32 tlv_header;
3008 u32 vdev_id;
3009 struct wmi_mac_addr peer_macaddr;
3010} __packed;
3011
3012struct wmi_peer_reorder_queue_setup_cmd {
3013 u32 tlv_header;
3014 u32 vdev_id;
3015 struct wmi_mac_addr peer_macaddr;
3016 u32 tid;
3017 u32 queue_ptr_lo;
3018 u32 queue_ptr_hi;
3019 u32 queue_no;
3020 u32 ba_window_size_valid;
3021 u32 ba_window_size;
3022} __packed;
3023
3024struct wmi_peer_reorder_queue_remove_cmd {
3025 u32 tlv_header;
3026 u32 vdev_id;
3027 struct wmi_mac_addr peer_macaddr;
3028 u32 tid_mask;
3029} __packed;
3030
3031struct gpio_config_params {
3032 u32 gpio_num;
3033 u32 input;
3034 u32 pull_type;
3035 u32 intr_mode;
3036};
3037
3038enum wmi_gpio_type {
3039 WMI_GPIO_PULL_NONE,
3040 WMI_GPIO_PULL_UP,
3041 WMI_GPIO_PULL_DOWN
3042};
3043
3044enum wmi_gpio_intr_type {
3045 WMI_GPIO_INTTYPE_DISABLE,
3046 WMI_GPIO_INTTYPE_RISING_EDGE,
3047 WMI_GPIO_INTTYPE_FALLING_EDGE,
3048 WMI_GPIO_INTTYPE_BOTH_EDGE,
3049 WMI_GPIO_INTTYPE_LEVEL_LOW,
3050 WMI_GPIO_INTTYPE_LEVEL_HIGH
3051};
3052
3053enum wmi_bss_chan_info_req_type {
3054 WMI_BSS_SURVEY_REQ_TYPE_READ = 1,
3055 WMI_BSS_SURVEY_REQ_TYPE_READ_CLEAR,
3056};
3057
3058struct wmi_gpio_config_cmd_param {
3059 u32 tlv_header;
3060 u32 gpio_num;
3061 u32 input;
3062 u32 pull_type;
3063 u32 intr_mode;
3064};
3065
3066struct gpio_output_params {
3067 u32 gpio_num;
3068 u32 set;
3069};
3070
3071struct wmi_gpio_output_cmd_param {
3072 u32 tlv_header;
3073 u32 gpio_num;
3074 u32 set;
3075};
3076
3077struct set_fwtest_params {
3078 u32 arg;
3079 u32 value;
3080};
3081
3082struct wmi_fwtest_set_param_cmd_param {
3083 u32 tlv_header;
3084 u32 param_id;
3085 u32 param_value;
3086};
3087
3088struct wmi_pdev_set_param_cmd {
3089 u32 tlv_header;
3090 u32 pdev_id;
3091 u32 param_id;
3092 u32 param_value;
3093} __packed;
3094
3095struct wmi_pdev_set_ps_mode_cmd {
3096 u32 tlv_header;
3097 u32 vdev_id;
3098 u32 sta_ps_mode;
3099} __packed;
3100
3101struct wmi_pdev_suspend_cmd {
3102 u32 tlv_header;
3103 u32 pdev_id;
3104 u32 suspend_opt;
3105} __packed;
3106
3107struct wmi_pdev_resume_cmd {
3108 u32 tlv_header;
3109 u32 pdev_id;
3110} __packed;
3111
3112struct wmi_pdev_bss_chan_info_req_cmd {
3113 u32 tlv_header;
3114 /* ref wmi_bss_chan_info_req_type */
3115 u32 req_type;
3116 u32 pdev_id;
3117} __packed;
3118
3119struct wmi_ap_ps_peer_cmd {
3120 u32 tlv_header;
3121 u32 vdev_id;
3122 struct wmi_mac_addr peer_macaddr;
3123 u32 param;
3124 u32 value;
3125} __packed;
3126
3127struct wmi_sta_powersave_param_cmd {
3128 u32 tlv_header;
3129 u32 vdev_id;
3130 u32 param;
3131 u32 value;
3132} __packed;
3133
3134struct wmi_pdev_set_regdomain_cmd {
3135 u32 tlv_header;
3136 u32 pdev_id;
3137 u32 reg_domain;
3138 u32 reg_domain_2g;
3139 u32 reg_domain_5g;
3140 u32 conformance_test_limit_2g;
3141 u32 conformance_test_limit_5g;
3142 u32 dfs_domain;
3143} __packed;
3144
3145struct wmi_peer_set_param_cmd {
3146 u32 tlv_header;
3147 u32 vdev_id;
3148 struct wmi_mac_addr peer_macaddr;
3149 u32 param_id;
3150 u32 param_value;
3151} __packed;
3152
3153struct wmi_peer_flush_tids_cmd {
3154 u32 tlv_header;
3155 u32 vdev_id;
3156 struct wmi_mac_addr peer_macaddr;
3157 u32 peer_tid_bitmap;
3158} __packed;
3159
3160struct wmi_dfs_phyerr_offload_cmd {
3161 u32 tlv_header;
3162 u32 pdev_id;
3163} __packed;
3164
3165struct wmi_bcn_offload_ctrl_cmd {
3166 u32 tlv_header;
3167 u32 vdev_id;
3168 u32 bcn_ctrl_op;
3169} __packed;
3170
3171enum scan_dwelltime_adaptive_mode {
3172 SCAN_DWELL_MODE_DEFAULT = 0,
3173 SCAN_DWELL_MODE_CONSERVATIVE = 1,
3174 SCAN_DWELL_MODE_MODERATE = 2,
3175 SCAN_DWELL_MODE_AGGRESSIVE = 3,
3176 SCAN_DWELL_MODE_STATIC = 4
3177};
3178
3179#define WLAN_SSID_MAX_LEN 32
3180
3181struct element_info {
3182 u32 len;
3183 u8 *ptr;
3184};
3185
3186struct wlan_ssid {
3187 u8 length;
3188 u8 ssid[WLAN_SSID_MAX_LEN];
3189};
3190
3191struct wmi_vdev_ch_power_info {
3192 u32 tlv_header;
3193
3194 /* Channel center frequency (MHz) */
3195 u32 chan_cfreq;
3196
3197 /* Unit: dBm, either PSD/EIRP power for this frequency or
3198 * incremental for non-PSD BW
3199 */
3200 u32 tx_power;
3201} __packed;
3202
3203struct wmi_vdev_set_tpc_power_cmd {
3204 u32 tlv_header;
3205 u32 vdev_id;
3206
3207 /* Value: 0 or 1, is PSD power or not */
3208 u32 psd_power;
3209
3210 /* Maximum EIRP power (dBm units), valid only if power is PSD */
3211 u32 eirp_power;
3212
3213 /* Type: WMI_6GHZ_REG_TYPE, used for halphy CTL lookup */
3214 u32 power_type_6ghz;
3215
3216 /* This fixed_param TLV is followed by the below TLVs:
3217 * num_pwr_levels of wmi_vdev_ch_power_info
3218 * For PSD power, it is the PSD/EIRP power of the frequency (20 MHz chunks).
3219 * For non-PSD power, the power values are for 20, 40, and till
3220 * BSS BW power levels.
3221 * The num_pwr_levels will be checked by sw how many elements present
3222 * in the variable-length array.
3223 */
3224} __packed;
3225
3226#define WMI_IE_BITMAP_SIZE 8
3227
3228/* prefix used by scan requestor ids on the host */
3229#define WMI_HOST_SCAN_REQUESTOR_ID_PREFIX 0xA000
3230
3231/* prefix used by scan request ids generated on the host */
3232/* host cycles through the lower 12 bits to generate ids */
3233#define WMI_HOST_SCAN_REQ_ID_PREFIX 0xA000
3234
3235/* Values lower than this may be refused by some firmware revisions with a scan
3236 * completion with a timedout reason.
3237 */
3238#define WMI_SCAN_CHAN_MIN_TIME_MSEC 40
3239
3240/* Scan priority numbers must be sequential, starting with 0 */
3241enum wmi_scan_priority {
3242 WMI_SCAN_PRIORITY_VERY_LOW = 0,
3243 WMI_SCAN_PRIORITY_LOW,
3244 WMI_SCAN_PRIORITY_MEDIUM,
3245 WMI_SCAN_PRIORITY_HIGH,
3246 WMI_SCAN_PRIORITY_VERY_HIGH,
3247 WMI_SCAN_PRIORITY_COUNT /* number of priorities supported */
3248};
3249
3250enum wmi_scan_event_type {
3251 WMI_SCAN_EVENT_STARTED = BIT(0),
3252 WMI_SCAN_EVENT_COMPLETED = BIT(1),
3253 WMI_SCAN_EVENT_BSS_CHANNEL = BIT(2),
3254 WMI_SCAN_EVENT_FOREIGN_CHAN = BIT(3),
3255 WMI_SCAN_EVENT_DEQUEUED = BIT(4),
3256 /* possibly by high-prio scan */
3257 WMI_SCAN_EVENT_PREEMPTED = BIT(5),
3258 WMI_SCAN_EVENT_START_FAILED = BIT(6),
3259 WMI_SCAN_EVENT_RESTARTED = BIT(7),
3260 WMI_SCAN_EVENT_FOREIGN_CHAN_EXIT = BIT(8),
3261 WMI_SCAN_EVENT_SUSPENDED = BIT(9),
3262 WMI_SCAN_EVENT_RESUMED = BIT(10),
3263 WMI_SCAN_EVENT_MAX = BIT(15),
3264};
3265
3266enum wmi_scan_completion_reason {
3267 WMI_SCAN_REASON_COMPLETED,
3268 WMI_SCAN_REASON_CANCELLED,
3269 WMI_SCAN_REASON_PREEMPTED,
3270 WMI_SCAN_REASON_TIMEDOUT,
3271 WMI_SCAN_REASON_INTERNAL_FAILURE,
3272 WMI_SCAN_REASON_MAX,
3273};
3274
3275struct wmi_start_scan_cmd {
3276 u32 tlv_header;
3277 u32 scan_id;
3278 u32 scan_req_id;
3279 u32 vdev_id;
3280 u32 scan_priority;
3281 u32 notify_scan_events;
3282 u32 dwell_time_active;
3283 u32 dwell_time_passive;
3284 u32 min_rest_time;
3285 u32 max_rest_time;
3286 u32 repeat_probe_time;
3287 u32 probe_spacing_time;
3288 u32 idle_time;
3289 u32 max_scan_time;
3290 u32 probe_delay;
3291 u32 scan_ctrl_flags;
3292 u32 burst_duration;
3293 u32 num_chan;
3294 u32 num_bssid;
3295 u32 num_ssids;
3296 u32 ie_len;
3297 u32 n_probes;
3298 struct wmi_mac_addr mac_addr;
3299 struct wmi_mac_addr mac_mask;
3300 u32 ie_bitmap[WMI_IE_BITMAP_SIZE];
3301 u32 num_vendor_oui;
3302 u32 scan_ctrl_flags_ext;
3303 u32 dwell_time_active_2g;
3304 u32 dwell_time_active_6g;
3305 u32 dwell_time_passive_6g;
3306 u32 scan_start_offset;
3307} __packed;
3308
3309#define WMI_SCAN_FLAG_PASSIVE 0x1
3310#define WMI_SCAN_ADD_BCAST_PROBE_REQ 0x2
3311#define WMI_SCAN_ADD_CCK_RATES 0x4
3312#define WMI_SCAN_ADD_OFDM_RATES 0x8
3313#define WMI_SCAN_CHAN_STAT_EVENT 0x10
3314#define WMI_SCAN_FILTER_PROBE_REQ 0x20
3315#define WMI_SCAN_BYPASS_DFS_CHN 0x40
3316#define WMI_SCAN_CONTINUE_ON_ERROR 0x80
3317#define WMI_SCAN_FILTER_PROMISCUOS 0x100
3318#define WMI_SCAN_FLAG_FORCE_ACTIVE_ON_DFS 0x200
3319#define WMI_SCAN_ADD_TPC_IE_IN_PROBE_REQ 0x400
3320#define WMI_SCAN_ADD_DS_IE_IN_PROBE_REQ 0x800
3321#define WMI_SCAN_ADD_SPOOF_MAC_IN_PROBE_REQ 0x1000
3322#define WMI_SCAN_OFFCHAN_MGMT_TX 0x2000
3323#define WMI_SCAN_OFFCHAN_DATA_TX 0x4000
3324#define WMI_SCAN_CAPTURE_PHY_ERROR 0x8000
3325#define WMI_SCAN_FLAG_STRICT_PASSIVE_ON_PCHN 0x10000
3326#define WMI_SCAN_FLAG_HALF_RATE_SUPPORT 0x20000
3327#define WMI_SCAN_FLAG_QUARTER_RATE_SUPPORT 0x40000
3328#define WMI_SCAN_RANDOM_SEQ_NO_IN_PROBE_REQ 0x80000
3329#define WMI_SCAN_ENABLE_IE_WHTELIST_IN_PROBE_REQ 0x100000
3330
3331#define WMI_SCAN_DWELL_MODE_MASK 0x00E00000
3332#define WMI_SCAN_DWELL_MODE_SHIFT 21
3333#define WMI_SCAN_FLAG_EXT_PASSIVE_SCAN_START_TIME_ENHANCE 0x00000800
3334
3335#define WMI_SCAN_CONFIG_PER_CHANNEL_MASK GENMASK(19, 0)
3336#define WMI_SCAN_CH_FLAG_SCAN_ONLY_IF_RNR_FOUND BIT(20)
3337
3338enum {
3339 WMI_SCAN_DWELL_MODE_DEFAULT = 0,
3340 WMI_SCAN_DWELL_MODE_CONSERVATIVE = 1,
3341 WMI_SCAN_DWELL_MODE_MODERATE = 2,
3342 WMI_SCAN_DWELL_MODE_AGGRESSIVE = 3,
3343 WMI_SCAN_DWELL_MODE_STATIC = 4,
3344};
3345
3346#define WMI_SCAN_SET_DWELL_MODE(flag, mode) \
3347 ((flag) |= (((mode) << WMI_SCAN_DWELL_MODE_SHIFT) & \
3348 WMI_SCAN_DWELL_MODE_MASK))
3349
3350struct hint_short_ssid {
3351 u32 freq_flags;
3352 u32 short_ssid;
3353};
3354
3355struct hint_bssid {
3356 u32 freq_flags;
3357 struct wmi_mac_addr bssid;
3358};
3359
3360struct scan_req_params {
3361 u32 scan_id;
3362 u32 scan_req_id;
3363 u32 vdev_id;
3364 u32 pdev_id;
3365 enum wmi_scan_priority scan_priority;
3366 u32 scan_ev_started:1,
3367 scan_ev_completed:1,
3368 scan_ev_bss_chan:1,
3369 scan_ev_foreign_chan:1,
3370 scan_ev_dequeued:1,
3371 scan_ev_preempted:1,
3372 scan_ev_start_failed:1,
3373 scan_ev_restarted:1,
3374 scan_ev_foreign_chn_exit:1,
3375 scan_ev_invalid:1,
3376 scan_ev_gpio_timeout:1,
3377 scan_ev_suspended:1,
3378 scan_ev_resumed:1;
3379 u32 scan_ctrl_flags_ext;
3380 u32 dwell_time_active;
3381 u32 dwell_time_active_2g;
3382 u32 dwell_time_passive;
3383 u32 dwell_time_active_6g;
3384 u32 dwell_time_passive_6g;
3385 u32 min_rest_time;
3386 u32 max_rest_time;
3387 u32 repeat_probe_time;
3388 u32 probe_spacing_time;
3389 u32 idle_time;
3390 u32 max_scan_time;
3391 u32 probe_delay;
3392 u32 scan_f_passive:1,
3393 scan_f_bcast_probe:1,
3394 scan_f_cck_rates:1,
3395 scan_f_ofdm_rates:1,
3396 scan_f_chan_stat_evnt:1,
3397 scan_f_filter_prb_req:1,
3398 scan_f_bypass_dfs_chn:1,
3399 scan_f_continue_on_err:1,
3400 scan_f_offchan_mgmt_tx:1,
3401 scan_f_offchan_data_tx:1,
3402 scan_f_promisc_mode:1,
3403 scan_f_capture_phy_err:1,
3404 scan_f_strict_passive_pch:1,
3405 scan_f_half_rate:1,
3406 scan_f_quarter_rate:1,
3407 scan_f_force_active_dfs_chn:1,
3408 scan_f_add_tpc_ie_in_probe:1,
3409 scan_f_add_ds_ie_in_probe:1,
3410 scan_f_add_spoofed_mac_in_probe:1,
3411 scan_f_add_rand_seq_in_probe:1,
3412 scan_f_en_ie_whitelist_in_probe:1,
3413 scan_f_forced:1,
3414 scan_f_2ghz:1,
3415 scan_f_5ghz:1,
3416 scan_f_80mhz:1;
3417 enum scan_dwelltime_adaptive_mode adaptive_dwell_time_mode;
3418 u32 burst_duration;
3419 u32 num_chan;
3420 u32 num_bssid;
3421 u32 num_ssids;
3422 u32 n_probes;
3423 u32 *chan_list;
3424 u32 notify_scan_events;
3425 struct wlan_ssid ssid[WLAN_SCAN_PARAMS_MAX_SSID];
3426 struct wmi_mac_addr bssid_list[WLAN_SCAN_PARAMS_MAX_BSSID];
3427 struct element_info extraie;
3428 struct element_info htcap;
3429 struct element_info vhtcap;
3430 u32 num_hint_s_ssid;
3431 u32 num_hint_bssid;
3432 struct hint_short_ssid hint_s_ssid[WLAN_SCAN_MAX_HINT_S_SSID];
3433 struct hint_bssid hint_bssid[WLAN_SCAN_MAX_HINT_BSSID];
3434 struct wmi_mac_addr mac_addr;
3435 struct wmi_mac_addr mac_mask;
3436};
3437
3438struct wmi_ssid_arg {
3439 int len;
3440 const u8 *ssid;
3441};
3442
3443struct wmi_bssid_arg {
3444 const u8 *bssid;
3445};
3446
3447struct wmi_start_scan_arg {
3448 u32 scan_id;
3449 u32 scan_req_id;
3450 u32 vdev_id;
3451 u32 scan_priority;
3452 u32 notify_scan_events;
3453 u32 dwell_time_active;
3454 u32 dwell_time_passive;
3455 u32 min_rest_time;
3456 u32 max_rest_time;
3457 u32 repeat_probe_time;
3458 u32 probe_spacing_time;
3459 u32 idle_time;
3460 u32 max_scan_time;
3461 u32 probe_delay;
3462 u32 scan_ctrl_flags;
3463
3464 u32 ie_len;
3465 u32 n_channels;
3466 u32 n_ssids;
3467 u32 n_bssids;
3468
3469 u8 ie[WLAN_SCAN_PARAMS_MAX_IE_LEN];
3470 u32 channels[64];
3471 struct wmi_ssid_arg ssids[WLAN_SCAN_PARAMS_MAX_SSID];
3472 struct wmi_bssid_arg bssids[WLAN_SCAN_PARAMS_MAX_BSSID];
3473};
3474
3475#define WMI_SCAN_STOP_ONE 0x00000000
3476#define WMI_SCN_STOP_VAP_ALL 0x01000000
3477#define WMI_SCAN_STOP_ALL 0x04000000
3478
3479/* Prefix 0xA000 indicates that the scan request
3480 * is trigger by HOST
3481 */
3482#define ATH11K_SCAN_ID 0xA000
3483
3484enum scan_cancel_req_type {
3485 WLAN_SCAN_CANCEL_SINGLE = 1,
3486 WLAN_SCAN_CANCEL_VDEV_ALL,
3487 WLAN_SCAN_CANCEL_PDEV_ALL,
3488};
3489
3490struct scan_cancel_param {
3491 u32 requester;
3492 u32 scan_id;
3493 enum scan_cancel_req_type req_type;
3494 u32 vdev_id;
3495 u32 pdev_id;
3496};
3497
3498struct wmi_bcn_send_from_host_cmd {
3499 u32 tlv_header;
3500 u32 vdev_id;
3501 u32 data_len;
3502 union {
3503 u32 frag_ptr;
3504 u32 frag_ptr_lo;
3505 };
3506 u32 frame_ctrl;
3507 u32 dtim_flag;
3508 u32 bcn_antenna;
3509 u32 frag_ptr_hi;
3510};
3511
3512#define WMI_CHAN_INFO_MODE GENMASK(5, 0)
3513#define WMI_CHAN_INFO_HT40_PLUS BIT(6)
3514#define WMI_CHAN_INFO_PASSIVE BIT(7)
3515#define WMI_CHAN_INFO_ADHOC_ALLOWED BIT(8)
3516#define WMI_CHAN_INFO_AP_DISABLED BIT(9)
3517#define WMI_CHAN_INFO_DFS BIT(10)
3518#define WMI_CHAN_INFO_ALLOW_HT BIT(11)
3519#define WMI_CHAN_INFO_ALLOW_VHT BIT(12)
3520#define WMI_CHAN_INFO_CHAN_CHANGE_CAUSE_CSA BIT(13)
3521#define WMI_CHAN_INFO_HALF_RATE BIT(14)
3522#define WMI_CHAN_INFO_QUARTER_RATE BIT(15)
3523#define WMI_CHAN_INFO_DFS_FREQ2 BIT(16)
3524#define WMI_CHAN_INFO_ALLOW_HE BIT(17)
3525#define WMI_CHAN_INFO_PSC BIT(18)
3526
3527#define WMI_CHAN_REG_INFO1_MIN_PWR GENMASK(7, 0)
3528#define WMI_CHAN_REG_INFO1_MAX_PWR GENMASK(15, 8)
3529#define WMI_CHAN_REG_INFO1_MAX_REG_PWR GENMASK(23, 16)
3530#define WMI_CHAN_REG_INFO1_REG_CLS GENMASK(31, 24)
3531
3532#define WMI_CHAN_REG_INFO2_ANT_MAX GENMASK(7, 0)
3533#define WMI_CHAN_REG_INFO2_MAX_TX_PWR GENMASK(15, 8)
3534
3535struct wmi_channel {
3536 u32 tlv_header;
3537 u32 mhz;
3538 u32 band_center_freq1;
3539 u32 band_center_freq2;
3540 u32 info;
3541 u32 reg_info_1;
3542 u32 reg_info_2;
3543} __packed;
3544
3545struct wmi_mgmt_params {
3546 void *tx_frame;
3547 u16 frm_len;
3548 u8 vdev_id;
3549 u16 chanfreq;
3550 void *pdata;
3551 u16 desc_id;
3552 u8 *macaddr;
3553};
3554
3555enum wmi_sta_ps_mode {
3556 WMI_STA_PS_MODE_DISABLED = 0,
3557 WMI_STA_PS_MODE_ENABLED = 1,
3558};
3559
3560#define WMI_SMPS_MASK_LOWER_16BITS 0xFF
3561#define WMI_SMPS_MASK_UPPER_3BITS 0x7
3562#define WMI_SMPS_PARAM_VALUE_SHIFT 29
3563
3564#define ATH11K_WMI_FW_HANG_ASSERT_TYPE 1
3565#define ATH11K_WMI_FW_HANG_DELAY 0
3566
3567/* type, 0:unused 1: ASSERT 2: not respond detect command
3568 * delay_time_ms, the simulate will delay time
3569 */
3570
3571struct wmi_force_fw_hang_cmd {
3572 u32 tlv_header;
3573 u32 type;
3574 u32 delay_time_ms;
3575};
3576
3577struct wmi_vdev_set_param_cmd {
3578 u32 tlv_header;
3579 u32 vdev_id;
3580 u32 param_id;
3581 u32 param_value;
3582} __packed;
3583
3584enum wmi_stats_id {
3585 WMI_REQUEST_PEER_STAT = BIT(0),
3586 WMI_REQUEST_AP_STAT = BIT(1),
3587 WMI_REQUEST_PDEV_STAT = BIT(2),
3588 WMI_REQUEST_VDEV_STAT = BIT(3),
3589 WMI_REQUEST_BCNFLT_STAT = BIT(4),
3590 WMI_REQUEST_VDEV_RATE_STAT = BIT(5),
3591 WMI_REQUEST_INST_STAT = BIT(6),
3592 WMI_REQUEST_MIB_STAT = BIT(7),
3593 WMI_REQUEST_RSSI_PER_CHAIN_STAT = BIT(8),
3594 WMI_REQUEST_CONGESTION_STAT = BIT(9),
3595 WMI_REQUEST_PEER_EXTD_STAT = BIT(10),
3596 WMI_REQUEST_BCN_STAT = BIT(11),
3597 WMI_REQUEST_BCN_STAT_RESET = BIT(12),
3598 WMI_REQUEST_PEER_EXTD2_STAT = BIT(13),
3599};
3600
3601struct wmi_request_stats_cmd {
3602 u32 tlv_header;
3603 enum wmi_stats_id stats_id;
3604 u32 vdev_id;
3605 struct wmi_mac_addr peer_macaddr;
3606 u32 pdev_id;
3607} __packed;
3608
3609struct wmi_get_pdev_temperature_cmd {
3610 u32 tlv_header;
3611 u32 param;
3612 u32 pdev_id;
3613} __packed;
3614
3615struct wmi_ftm_seg_hdr {
3616 u32 len;
3617 u32 msgref;
3618 u32 segmentinfo;
3619 u32 pdev_id;
3620} __packed;
3621
3622struct wmi_ftm_cmd {
3623 u32 tlv_header;
3624 struct wmi_ftm_seg_hdr seg_hdr;
3625 u8 data[];
3626} __packed;
3627
3628struct wmi_ftm_event_msg {
3629 struct wmi_ftm_seg_hdr seg_hdr;
3630 u8 data[];
3631} __packed;
3632
3633#define WMI_BEACON_TX_BUFFER_SIZE 512
3634
3635#define WMI_EMA_TMPL_IDX_SHIFT 8
3636#define WMI_EMA_FIRST_TMPL_SHIFT 16
3637#define WMI_EMA_LAST_TMPL_SHIFT 24
3638
3639struct wmi_bcn_tmpl_cmd {
3640 u32 tlv_header;
3641 u32 vdev_id;
3642 u32 tim_ie_offset;
3643 u32 buf_len;
3644 u32 csa_switch_count_offset;
3645 u32 ext_csa_switch_count_offset;
3646 u32 csa_event_bitmap;
3647 u32 mbssid_ie_offset;
3648 u32 esp_ie_offset;
3649 u32 csc_switch_count_offset;
3650 u32 csc_event_bitmap;
3651 u32 mu_edca_ie_offset;
3652 u32 feature_enable_bitmap;
3653 u32 ema_params;
3654} __packed;
3655
3656struct wmi_key_seq_counter {
3657 u32 key_seq_counter_l;
3658 u32 key_seq_counter_h;
3659} __packed;
3660
3661struct wmi_vdev_install_key_cmd {
3662 u32 tlv_header;
3663 u32 vdev_id;
3664 struct wmi_mac_addr peer_macaddr;
3665 u32 key_idx;
3666 u32 key_flags;
3667 u32 key_cipher;
3668 struct wmi_key_seq_counter key_rsc_counter;
3669 struct wmi_key_seq_counter key_global_rsc_counter;
3670 struct wmi_key_seq_counter key_tsc_counter;
3671 u8 wpi_key_rsc_counter[16];
3672 u8 wpi_key_tsc_counter[16];
3673 u32 key_len;
3674 u32 key_txmic_len;
3675 u32 key_rxmic_len;
3676 u32 is_group_key_id_valid;
3677 u32 group_key_id;
3678
3679 /* Followed by key_data containing key followed by
3680 * tx mic and then rx mic
3681 */
3682} __packed;
3683
3684struct wmi_vdev_install_key_arg {
3685 u32 vdev_id;
3686 const u8 *macaddr;
3687 u32 key_idx;
3688 u32 key_flags;
3689 u32 key_cipher;
3690 u32 key_len;
3691 u32 key_txmic_len;
3692 u32 key_rxmic_len;
3693 u64 key_rsc_counter;
3694 const void *key_data;
3695};
3696
3697#define WMI_MAX_SUPPORTED_RATES 128
3698#define WMI_HOST_MAX_HECAP_PHY_SIZE 3
3699#define WMI_HOST_MAX_HE_RATE_SET 3
3700#define WMI_HECAP_TXRX_MCS_NSS_IDX_80 0
3701#define WMI_HECAP_TXRX_MCS_NSS_IDX_160 1
3702#define WMI_HECAP_TXRX_MCS_NSS_IDX_80_80 2
3703
3704struct wmi_rate_set_arg {
3705 u32 num_rates;
3706 u8 rates[WMI_MAX_SUPPORTED_RATES];
3707};
3708
3709struct peer_assoc_params {
3710 struct wmi_mac_addr peer_macaddr;
3711 u32 vdev_id;
3712 u32 peer_new_assoc;
3713 u32 peer_associd;
3714 u32 peer_flags;
3715 u32 peer_caps;
3716 u32 peer_listen_intval;
3717 u32 peer_ht_caps;
3718 u32 peer_max_mpdu;
3719 u32 peer_mpdu_density;
3720 u32 peer_rate_caps;
3721 u32 peer_nss;
3722 u32 peer_vht_caps;
3723 u32 peer_phymode;
3724 u32 peer_ht_info[2];
3725 struct wmi_rate_set_arg peer_legacy_rates;
3726 struct wmi_rate_set_arg peer_ht_rates;
3727 u32 rx_max_rate;
3728 u32 rx_mcs_set;
3729 u32 tx_max_rate;
3730 u32 tx_mcs_set;
3731 u8 vht_capable;
3732 u8 min_data_rate;
3733 u32 tx_max_mcs_nss;
3734 u32 peer_bw_rxnss_override;
3735 bool is_pmf_enabled;
3736 bool is_wme_set;
3737 bool qos_flag;
3738 bool apsd_flag;
3739 bool ht_flag;
3740 bool bw_40;
3741 bool bw_80;
3742 bool bw_160;
3743 bool stbc_flag;
3744 bool ldpc_flag;
3745 bool static_mimops_flag;
3746 bool dynamic_mimops_flag;
3747 bool spatial_mux_flag;
3748 bool vht_flag;
3749 bool vht_ng_flag;
3750 bool need_ptk_4_way;
3751 bool need_gtk_2_way;
3752 bool auth_flag;
3753 bool safe_mode_enabled;
3754 bool amsdu_disable;
3755 /* Use common structure */
3756 u8 peer_mac[ETH_ALEN];
3757
3758 bool he_flag;
3759 u32 peer_he_cap_macinfo[2];
3760 u32 peer_he_cap_macinfo_internal;
3761 u32 peer_he_caps_6ghz;
3762 u32 peer_he_ops;
3763 u32 peer_he_cap_phyinfo[WMI_HOST_MAX_HECAP_PHY_SIZE];
3764 u32 peer_he_mcs_count;
3765 u32 peer_he_rx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];
3766 u32 peer_he_tx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];
3767 bool twt_responder;
3768 bool twt_requester;
3769 bool is_assoc;
3770 struct ath11k_ppe_threshold peer_ppet;
3771};
3772
3773struct wmi_peer_assoc_complete_cmd {
3774 u32 tlv_header;
3775 struct wmi_mac_addr peer_macaddr;
3776 u32 vdev_id;
3777 u32 peer_new_assoc;
3778 u32 peer_associd;
3779 u32 peer_flags;
3780 u32 peer_caps;
3781 u32 peer_listen_intval;
3782 u32 peer_ht_caps;
3783 u32 peer_max_mpdu;
3784 u32 peer_mpdu_density;
3785 u32 peer_rate_caps;
3786 u32 peer_nss;
3787 u32 peer_vht_caps;
3788 u32 peer_phymode;
3789 u32 peer_ht_info[2];
3790 u32 num_peer_legacy_rates;
3791 u32 num_peer_ht_rates;
3792 u32 peer_bw_rxnss_override;
3793 struct wmi_ppe_threshold peer_ppet;
3794 u32 peer_he_cap_info;
3795 u32 peer_he_ops;
3796 u32 peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE];
3797 u32 peer_he_mcs;
3798 u32 peer_he_cap_info_ext;
3799 u32 peer_he_cap_info_internal;
3800 u32 min_data_rate;
3801 u32 peer_he_caps_6ghz;
3802} __packed;
3803
3804struct wmi_stop_scan_cmd {
3805 u32 tlv_header;
3806 u32 requestor;
3807 u32 scan_id;
3808 u32 req_type;
3809 u32 vdev_id;
3810 u32 pdev_id;
3811};
3812
3813struct scan_chan_list_params {
3814 u32 pdev_id;
3815 u16 nallchans;
3816 struct channel_param ch_param[];
3817};
3818
3819struct wmi_scan_chan_list_cmd {
3820 u32 tlv_header;
3821 u32 num_scan_chans;
3822 u32 flags;
3823 u32 pdev_id;
3824} __packed;
3825
3826struct wmi_scan_prob_req_oui_cmd {
3827 u32 tlv_header;
3828 u32 prob_req_oui;
3829} __packed;
3830
3831#define WMI_MGMT_SEND_DOWNLD_LEN 64
3832
3833#define WMI_TX_PARAMS_DWORD0_POWER GENMASK(7, 0)
3834#define WMI_TX_PARAMS_DWORD0_MCS_MASK GENMASK(19, 8)
3835#define WMI_TX_PARAMS_DWORD0_NSS_MASK GENMASK(27, 20)
3836#define WMI_TX_PARAMS_DWORD0_RETRY_LIMIT GENMASK(31, 28)
3837
3838#define WMI_TX_PARAMS_DWORD1_CHAIN_MASK GENMASK(7, 0)
3839#define WMI_TX_PARAMS_DWORD1_BW_MASK GENMASK(14, 8)
3840#define WMI_TX_PARAMS_DWORD1_PREAMBLE_TYPE GENMASK(19, 15)
3841#define WMI_TX_PARAMS_DWORD1_FRAME_TYPE BIT(20)
3842#define WMI_TX_PARAMS_DWORD1_RSVD GENMASK(31, 21)
3843
3844struct wmi_mgmt_send_params {
3845 u32 tlv_header;
3846 u32 tx_params_dword0;
3847 u32 tx_params_dword1;
3848};
3849
3850struct wmi_mgmt_send_cmd {
3851 u32 tlv_header;
3852 u32 vdev_id;
3853 u32 desc_id;
3854 u32 chanfreq;
3855 u32 paddr_lo;
3856 u32 paddr_hi;
3857 u32 frame_len;
3858 u32 buf_len;
3859 u32 tx_params_valid;
3860
3861 /* This TLV is followed by struct wmi_mgmt_frame */
3862
3863 /* Followed by struct wmi_mgmt_send_params */
3864} __packed;
3865
3866struct wmi_sta_powersave_mode_cmd {
3867 u32 tlv_header;
3868 u32 vdev_id;
3869 u32 sta_ps_mode;
3870};
3871
3872struct wmi_sta_smps_force_mode_cmd {
3873 u32 tlv_header;
3874 u32 vdev_id;
3875 u32 forced_mode;
3876};
3877
3878struct wmi_sta_smps_param_cmd {
3879 u32 tlv_header;
3880 u32 vdev_id;
3881 u32 param;
3882 u32 value;
3883};
3884
3885struct wmi_bcn_prb_info {
3886 u32 tlv_header;
3887 u32 caps;
3888 u32 erp;
3889} __packed;
3890
3891enum {
3892 WMI_PDEV_SUSPEND,
3893 WMI_PDEV_SUSPEND_AND_DISABLE_INTR,
3894};
3895
3896struct green_ap_ps_params {
3897 u32 value;
3898};
3899
3900struct wmi_pdev_green_ap_ps_enable_cmd_param {
3901 u32 tlv_header;
3902 u32 pdev_id;
3903 u32 enable;
3904};
3905
3906struct ap_ps_params {
3907 u32 vdev_id;
3908 u32 param;
3909 u32 value;
3910};
3911
3912struct vdev_set_params {
3913 u32 if_id;
3914 u32 param_id;
3915 u32 param_value;
3916};
3917
3918struct stats_request_params {
3919 u32 stats_id;
3920 u32 vdev_id;
3921 u32 pdev_id;
3922};
3923
3924struct wmi_set_current_country_params {
3925 u8 alpha2[3];
3926};
3927
3928struct wmi_set_current_country_cmd {
3929 u32 tlv_header;
3930 u32 pdev_id;
3931 u32 new_alpha2;
3932} __packed;
3933
3934enum set_init_cc_type {
3935 WMI_COUNTRY_INFO_TYPE_ALPHA,
3936 WMI_COUNTRY_INFO_TYPE_COUNTRY_CODE,
3937 WMI_COUNTRY_INFO_TYPE_REGDOMAIN,
3938};
3939
3940enum set_init_cc_flags {
3941 INVALID_CC,
3942 CC_IS_SET,
3943 REGDMN_IS_SET,
3944 ALPHA_IS_SET,
3945};
3946
3947struct wmi_init_country_params {
3948 union {
3949 u16 country_code;
3950 u16 regdom_id;
3951 u8 alpha2[3];
3952 } cc_info;
3953 enum set_init_cc_flags flags;
3954};
3955
3956struct wmi_init_country_cmd {
3957 u32 tlv_header;
3958 u32 pdev_id;
3959 u32 init_cc_type;
3960 union {
3961 u32 country_code;
3962 u32 regdom_id;
3963 u32 alpha2;
3964 } cc_info;
3965} __packed;
3966
3967struct wmi_11d_scan_start_params {
3968 u32 vdev_id;
3969 u32 scan_period_msec;
3970 u32 start_interval_msec;
3971};
3972
3973struct wmi_11d_scan_start_cmd {
3974 u32 tlv_header;
3975 u32 vdev_id;
3976 u32 scan_period_msec;
3977 u32 start_interval_msec;
3978} __packed;
3979
3980struct wmi_11d_scan_stop_cmd {
3981 u32 tlv_header;
3982 u32 vdev_id;
3983} __packed;
3984
3985struct wmi_11d_new_cc_ev {
3986 u32 new_alpha2;
3987} __packed;
3988
3989#define THERMAL_LEVELS 1
3990struct tt_level_config {
3991 u32 tmplwm;
3992 u32 tmphwm;
3993 u32 dcoffpercent;
3994 u32 priority;
3995};
3996
3997struct thermal_mitigation_params {
3998 u32 pdev_id;
3999 u32 enable;
4000 u32 dc;
4001 u32 dc_per_event;
4002 struct tt_level_config levelconf[THERMAL_LEVELS];
4003};
4004
4005struct wmi_therm_throt_config_request_cmd {
4006 u32 tlv_header;
4007 u32 pdev_id;
4008 u32 enable;
4009 u32 dc;
4010 u32 dc_per_event;
4011 u32 therm_throt_levels;
4012} __packed;
4013
4014struct wmi_therm_throt_level_config_info {
4015 u32 tlv_header;
4016 u32 temp_lwm;
4017 u32 temp_hwm;
4018 u32 dc_off_percent;
4019 u32 prio;
4020} __packed;
4021
4022struct wmi_delba_send_cmd {
4023 u32 tlv_header;
4024 u32 vdev_id;
4025 struct wmi_mac_addr peer_macaddr;
4026 u32 tid;
4027 u32 initiator;
4028 u32 reasoncode;
4029} __packed;
4030
4031struct wmi_addba_setresponse_cmd {
4032 u32 tlv_header;
4033 u32 vdev_id;
4034 struct wmi_mac_addr peer_macaddr;
4035 u32 tid;
4036 u32 statuscode;
4037} __packed;
4038
4039struct wmi_addba_send_cmd {
4040 u32 tlv_header;
4041 u32 vdev_id;
4042 struct wmi_mac_addr peer_macaddr;
4043 u32 tid;
4044 u32 buffersize;
4045} __packed;
4046
4047struct wmi_addba_clear_resp_cmd {
4048 u32 tlv_header;
4049 u32 vdev_id;
4050 struct wmi_mac_addr peer_macaddr;
4051} __packed;
4052
4053struct wmi_pdev_pktlog_filter_info {
4054 u32 tlv_header;
4055 struct wmi_mac_addr peer_macaddr;
4056} __packed;
4057
4058struct wmi_pdev_pktlog_filter_cmd {
4059 u32 tlv_header;
4060 u32 pdev_id;
4061 u32 enable;
4062 u32 filter_type;
4063 u32 num_mac;
4064} __packed;
4065
4066enum ath11k_wmi_pktlog_enable {
4067 ATH11K_WMI_PKTLOG_ENABLE_AUTO = 0,
4068 ATH11K_WMI_PKTLOG_ENABLE_FORCE = 1,
4069};
4070
4071struct wmi_pktlog_enable_cmd {
4072 u32 tlv_header;
4073 u32 pdev_id;
4074 u32 evlist; /* WMI_PKTLOG_EVENT */
4075 u32 enable;
4076} __packed;
4077
4078struct wmi_pktlog_disable_cmd {
4079 u32 tlv_header;
4080 u32 pdev_id;
4081} __packed;
4082
4083#define DFS_PHYERR_UNIT_TEST_CMD 0
4084#define DFS_UNIT_TEST_MODULE 0x2b
4085#define DFS_UNIT_TEST_TOKEN 0xAA
4086
4087enum dfs_test_args_idx {
4088 DFS_TEST_CMDID = 0,
4089 DFS_TEST_PDEV_ID,
4090 DFS_TEST_RADAR_PARAM,
4091 DFS_MAX_TEST_ARGS,
4092};
4093
4094struct wmi_dfs_unit_test_arg {
4095 u32 cmd_id;
4096 u32 pdev_id;
4097 u32 radar_param;
4098};
4099
4100struct wmi_unit_test_cmd {
4101 u32 tlv_header;
4102 u32 vdev_id;
4103 u32 module_id;
4104 u32 num_args;
4105 u32 diag_token;
4106 /* Followed by test args*/
4107} __packed;
4108
4109#define MAX_SUPPORTED_RATES 128
4110
4111struct beacon_tmpl_params {
4112 u8 vdev_id;
4113 u32 tim_ie_offset;
4114 u32 tmpl_len;
4115 u32 tmpl_len_aligned;
4116 u32 csa_switch_count_offset;
4117 u32 ext_csa_switch_count_offset;
4118 u8 *frm;
4119};
4120
4121struct wmi_rate_set {
4122 u32 num_rates;
4123 u32 rates[(MAX_SUPPORTED_RATES / 4) + 1];
4124};
4125
4126struct wmi_vht_rate_set {
4127 u32 tlv_header;
4128 u32 rx_max_rate;
4129 u32 rx_mcs_set;
4130 u32 tx_max_rate;
4131 u32 tx_mcs_set;
4132 u32 tx_max_mcs_nss;
4133} __packed;
4134
4135struct wmi_he_rate_set {
4136 u32 tlv_header;
4137
4138 /* MCS at which the peer can receive */
4139 u32 rx_mcs_set;
4140
4141 /* MCS at which the peer can transmit */
4142 u32 tx_mcs_set;
4143} __packed;
4144
4145#define MAX_REG_RULES 10
4146#define REG_ALPHA2_LEN 2
4147#define MAX_6GHZ_REG_RULES 5
4148
4149enum wmi_start_event_param {
4150 WMI_VDEV_START_RESP_EVENT = 0,
4151 WMI_VDEV_RESTART_RESP_EVENT,
4152};
4153
4154struct wmi_vdev_start_resp_event {
4155 u32 vdev_id;
4156 u32 requestor_id;
4157 enum wmi_start_event_param resp_type;
4158 u32 status;
4159 u32 chain_mask;
4160 u32 smps_mode;
4161 union {
4162 u32 mac_id;
4163 u32 pdev_id;
4164 };
4165 u32 cfgd_tx_streams;
4166 u32 cfgd_rx_streams;
4167 s32 max_allowed_tx_power;
4168} __packed;
4169
4170/* VDEV start response status codes */
4171enum wmi_vdev_start_resp_status_code {
4172 WMI_VDEV_START_RESPONSE_STATUS_SUCCESS = 0,
4173 WMI_VDEV_START_RESPONSE_INVALID_VDEVID = 1,
4174 WMI_VDEV_START_RESPONSE_NOT_SUPPORTED = 2,
4175 WMI_VDEV_START_RESPONSE_DFS_VIOLATION = 3,
4176 WMI_VDEV_START_RESPONSE_INVALID_REGDOMAIN = 4,
4177};
4178
4179/* Regaulatory Rule Flags Passed by FW */
4180#define REGULATORY_CHAN_DISABLED BIT(0)
4181#define REGULATORY_CHAN_NO_IR BIT(1)
4182#define REGULATORY_CHAN_RADAR BIT(3)
4183#define REGULATORY_CHAN_NO_OFDM BIT(6)
4184#define REGULATORY_CHAN_INDOOR_ONLY BIT(9)
4185
4186#define REGULATORY_CHAN_NO_HT40 BIT(4)
4187#define REGULATORY_CHAN_NO_80MHZ BIT(7)
4188#define REGULATORY_CHAN_NO_160MHZ BIT(8)
4189#define REGULATORY_CHAN_NO_20MHZ BIT(11)
4190#define REGULATORY_CHAN_NO_10MHZ BIT(12)
4191
4192enum wmi_reg_chan_list_cmd_type {
4193 WMI_REG_CHAN_LIST_CC_ID = 0,
4194 WMI_REG_CHAN_LIST_CC_EXT_ID = 1,
4195};
4196
4197enum wmi_reg_cc_setting_code {
4198 WMI_REG_SET_CC_STATUS_PASS = 0,
4199 WMI_REG_CURRENT_ALPHA2_NOT_FOUND = 1,
4200 WMI_REG_INIT_ALPHA2_NOT_FOUND = 2,
4201 WMI_REG_SET_CC_CHANGE_NOT_ALLOWED = 3,
4202 WMI_REG_SET_CC_STATUS_NO_MEMORY = 4,
4203 WMI_REG_SET_CC_STATUS_FAIL = 5,
4204
4205 /* add new setting code above, update in
4206 * @enum cc_setting_code as well.
4207 * Also handle it in ath11k_wmi_cc_setting_code_to_reg()
4208 */
4209};
4210
4211enum cc_setting_code {
4212 REG_SET_CC_STATUS_PASS = 0,
4213 REG_CURRENT_ALPHA2_NOT_FOUND = 1,
4214 REG_INIT_ALPHA2_NOT_FOUND = 2,
4215 REG_SET_CC_CHANGE_NOT_ALLOWED = 3,
4216 REG_SET_CC_STATUS_NO_MEMORY = 4,
4217 REG_SET_CC_STATUS_FAIL = 5,
4218
4219 /* add new setting code above, update in
4220 * @enum wmi_reg_cc_setting_code as well.
4221 * Also handle it in ath11k_cc_status_to_str()
4222 */
4223};
4224
4225static inline enum cc_setting_code
4226ath11k_wmi_cc_setting_code_to_reg(enum wmi_reg_cc_setting_code status_code)
4227{
4228 switch (status_code) {
4229 case WMI_REG_SET_CC_STATUS_PASS:
4230 return REG_SET_CC_STATUS_PASS;
4231 case WMI_REG_CURRENT_ALPHA2_NOT_FOUND:
4232 return REG_CURRENT_ALPHA2_NOT_FOUND;
4233 case WMI_REG_INIT_ALPHA2_NOT_FOUND:
4234 return REG_INIT_ALPHA2_NOT_FOUND;
4235 case WMI_REG_SET_CC_CHANGE_NOT_ALLOWED:
4236 return REG_SET_CC_CHANGE_NOT_ALLOWED;
4237 case WMI_REG_SET_CC_STATUS_NO_MEMORY:
4238 return REG_SET_CC_STATUS_NO_MEMORY;
4239 case WMI_REG_SET_CC_STATUS_FAIL:
4240 return REG_SET_CC_STATUS_FAIL;
4241 }
4242
4243 return REG_SET_CC_STATUS_FAIL;
4244}
4245
4246static inline const char *ath11k_cc_status_to_str(enum cc_setting_code code)
4247{
4248 switch (code) {
4249 case REG_SET_CC_STATUS_PASS:
4250 return "REG_SET_CC_STATUS_PASS";
4251 case REG_CURRENT_ALPHA2_NOT_FOUND:
4252 return "REG_CURRENT_ALPHA2_NOT_FOUND";
4253 case REG_INIT_ALPHA2_NOT_FOUND:
4254 return "REG_INIT_ALPHA2_NOT_FOUND";
4255 case REG_SET_CC_CHANGE_NOT_ALLOWED:
4256 return "REG_SET_CC_CHANGE_NOT_ALLOWED";
4257 case REG_SET_CC_STATUS_NO_MEMORY:
4258 return "REG_SET_CC_STATUS_NO_MEMORY";
4259 case REG_SET_CC_STATUS_FAIL:
4260 return "REG_SET_CC_STATUS_FAIL";
4261 }
4262
4263 return "Unknown CC status";
4264}
4265
4266enum wmi_reg_6ghz_ap_type {
4267 WMI_REG_INDOOR_AP = 0,
4268 WMI_REG_STANDARD_POWER_AP = 1,
4269 WMI_REG_VERY_LOW_POWER_AP = 2,
4270
4271 /* add AP type above, handle in ath11k_6ghz_ap_type_to_str()
4272 */
4273 WMI_REG_CURRENT_MAX_AP_TYPE,
4274 WMI_REG_MAX_AP_TYPE = 7,
4275};
4276
4277static inline const char *
4278ath11k_6ghz_ap_type_to_str(enum wmi_reg_6ghz_ap_type type)
4279{
4280 switch (type) {
4281 case WMI_REG_INDOOR_AP:
4282 return "INDOOR AP";
4283 case WMI_REG_STANDARD_POWER_AP:
4284 return "STANDARD POWER AP";
4285 case WMI_REG_VERY_LOW_POWER_AP:
4286 return "VERY LOW POWER AP";
4287 case WMI_REG_CURRENT_MAX_AP_TYPE:
4288 return "CURRENT_MAX_AP_TYPE";
4289 case WMI_REG_MAX_AP_TYPE:
4290 return "MAX_AP_TYPE";
4291 }
4292
4293 return "unknown 6 GHz AP type";
4294}
4295
4296enum wmi_reg_6ghz_client_type {
4297 WMI_REG_DEFAULT_CLIENT = 0,
4298 WMI_REG_SUBORDINATE_CLIENT = 1,
4299 WMI_REG_MAX_CLIENT_TYPE = 2,
4300
4301 /* add client type above, handle it in
4302 * ath11k_6ghz_client_type_to_str()
4303 */
4304};
4305
4306static inline const char *
4307ath11k_6ghz_client_type_to_str(enum wmi_reg_6ghz_client_type type)
4308{
4309 switch (type) {
4310 case WMI_REG_DEFAULT_CLIENT:
4311 return "DEFAULT CLIENT";
4312 case WMI_REG_SUBORDINATE_CLIENT:
4313 return "SUBORDINATE CLIENT";
4314 case WMI_REG_MAX_CLIENT_TYPE:
4315 return "MAX_CLIENT_TYPE";
4316 }
4317
4318 return "unknown 6 GHz client type";
4319}
4320
4321enum reg_subdomains_6ghz {
4322 EMPTY_6GHZ = 0x0,
4323 FCC1_CLIENT_LPI_REGULAR_6GHZ = 0x01,
4324 FCC1_CLIENT_SP_6GHZ = 0x02,
4325 FCC1_AP_LPI_6GHZ = 0x03,
4326 FCC1_CLIENT_LPI_SUBORDINATE = FCC1_AP_LPI_6GHZ,
4327 FCC1_AP_SP_6GHZ = 0x04,
4328 ETSI1_LPI_6GHZ = 0x10,
4329 ETSI1_VLP_6GHZ = 0x11,
4330 ETSI2_LPI_6GHZ = 0x12,
4331 ETSI2_VLP_6GHZ = 0x13,
4332 APL1_LPI_6GHZ = 0x20,
4333 APL1_VLP_6GHZ = 0x21,
4334
4335 /* add sub-domain above, handle it in
4336 * ath11k_sub_reg_6ghz_to_str()
4337 */
4338};
4339
4340static inline const char *
4341ath11k_sub_reg_6ghz_to_str(enum reg_subdomains_6ghz sub_id)
4342{
4343 switch (sub_id) {
4344 case EMPTY_6GHZ:
4345 return "N/A";
4346 case FCC1_CLIENT_LPI_REGULAR_6GHZ:
4347 return "FCC1_CLIENT_LPI_REGULAR_6GHZ";
4348 case FCC1_CLIENT_SP_6GHZ:
4349 return "FCC1_CLIENT_SP_6GHZ";
4350 case FCC1_AP_LPI_6GHZ:
4351 return "FCC1_AP_LPI_6GHZ/FCC1_CLIENT_LPI_SUBORDINATE";
4352 case FCC1_AP_SP_6GHZ:
4353 return "FCC1_AP_SP_6GHZ";
4354 case ETSI1_LPI_6GHZ:
4355 return "ETSI1_LPI_6GHZ";
4356 case ETSI1_VLP_6GHZ:
4357 return "ETSI1_VLP_6GHZ";
4358 case ETSI2_LPI_6GHZ:
4359 return "ETSI2_LPI_6GHZ";
4360 case ETSI2_VLP_6GHZ:
4361 return "ETSI2_VLP_6GHZ";
4362 case APL1_LPI_6GHZ:
4363 return "APL1_LPI_6GHZ";
4364 case APL1_VLP_6GHZ:
4365 return "APL1_VLP_6GHZ";
4366 }
4367
4368 return "unknown sub reg id";
4369}
4370
4371enum reg_super_domain_6ghz {
4372 FCC1_6GHZ = 0x01,
4373 ETSI1_6GHZ = 0x02,
4374 ETSI2_6GHZ = 0x03,
4375 APL1_6GHZ = 0x04,
4376 FCC1_6GHZ_CL = 0x05,
4377
4378 /* add super domain above, handle it in
4379 * ath11k_super_reg_6ghz_to_str()
4380 */
4381};
4382
4383static inline const char *
4384ath11k_super_reg_6ghz_to_str(enum reg_super_domain_6ghz domain_id)
4385{
4386 switch (domain_id) {
4387 case FCC1_6GHZ:
4388 return "FCC1_6GHZ";
4389 case ETSI1_6GHZ:
4390 return "ETSI1_6GHZ";
4391 case ETSI2_6GHZ:
4392 return "ETSI2_6GHZ";
4393 case APL1_6GHZ:
4394 return "APL1_6GHZ";
4395 case FCC1_6GHZ_CL:
4396 return "FCC1_6GHZ_CL";
4397 }
4398
4399 return "unknown domain id";
4400}
4401
4402struct cur_reg_rule {
4403 u16 start_freq;
4404 u16 end_freq;
4405 u16 max_bw;
4406 u8 reg_power;
4407 u8 ant_gain;
4408 u16 flags;
4409 bool psd_flag;
4410 s8 psd_eirp;
4411};
4412
4413struct cur_regulatory_info {
4414 enum cc_setting_code status_code;
4415 u8 num_phy;
4416 u8 phy_id;
4417 u16 reg_dmn_pair;
4418 u16 ctry_code;
4419 u8 alpha2[REG_ALPHA2_LEN + 1];
4420 u32 dfs_region;
4421 u32 phybitmap;
4422 u32 min_bw_2ghz;
4423 u32 max_bw_2ghz;
4424 u32 min_bw_5ghz;
4425 u32 max_bw_5ghz;
4426 u32 num_2ghz_reg_rules;
4427 u32 num_5ghz_reg_rules;
4428 struct cur_reg_rule *reg_rules_2ghz_ptr;
4429 struct cur_reg_rule *reg_rules_5ghz_ptr;
4430 bool is_ext_reg_event;
4431 enum wmi_reg_6ghz_client_type client_type;
4432 bool rnr_tpe_usable;
4433 bool unspecified_ap_usable;
4434 u8 domain_code_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
4435 u8 domain_code_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4436 u32 domain_code_6ghz_super_id;
4437 u32 min_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
4438 u32 max_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
4439 u32 min_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4440 u32 max_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4441 u32 num_6ghz_rules_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
4442 u32 num_6ghz_rules_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4443 struct cur_reg_rule *reg_rules_6ghz_ap_ptr[WMI_REG_CURRENT_MAX_AP_TYPE];
4444 struct cur_reg_rule *reg_rules_6ghz_client_ptr
4445 [WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4446};
4447
4448struct wmi_reg_chan_list_cc_event {
4449 u32 status_code;
4450 u32 phy_id;
4451 u32 alpha2;
4452 u32 num_phy;
4453 u32 country_id;
4454 u32 domain_code;
4455 u32 dfs_region;
4456 u32 phybitmap;
4457 u32 min_bw_2ghz;
4458 u32 max_bw_2ghz;
4459 u32 min_bw_5ghz;
4460 u32 max_bw_5ghz;
4461 u32 num_2ghz_reg_rules;
4462 u32 num_5ghz_reg_rules;
4463} __packed;
4464
4465struct wmi_regulatory_rule_struct {
4466 u32 tlv_header;
4467 u32 freq_info;
4468 u32 bw_pwr_info;
4469 u32 flag_info;
4470};
4471
4472#define WMI_REG_CLIENT_MAX 4
4473
4474struct wmi_reg_chan_list_cc_ext_event {
4475 u32 status_code;
4476 u32 phy_id;
4477 u32 alpha2;
4478 u32 num_phy;
4479 u32 country_id;
4480 u32 domain_code;
4481 u32 dfs_region;
4482 u32 phybitmap;
4483 u32 min_bw_2ghz;
4484 u32 max_bw_2ghz;
4485 u32 min_bw_5ghz;
4486 u32 max_bw_5ghz;
4487 u32 num_2ghz_reg_rules;
4488 u32 num_5ghz_reg_rules;
4489 u32 client_type;
4490 u32 rnr_tpe_usable;
4491 u32 unspecified_ap_usable;
4492 u32 domain_code_6ghz_ap_lpi;
4493 u32 domain_code_6ghz_ap_sp;
4494 u32 domain_code_6ghz_ap_vlp;
4495 u32 domain_code_6ghz_client_lpi[WMI_REG_CLIENT_MAX];
4496 u32 domain_code_6ghz_client_sp[WMI_REG_CLIENT_MAX];
4497 u32 domain_code_6ghz_client_vlp[WMI_REG_CLIENT_MAX];
4498 u32 domain_code_6ghz_super_id;
4499 u32 min_bw_6ghz_ap_sp;
4500 u32 max_bw_6ghz_ap_sp;
4501 u32 min_bw_6ghz_ap_lpi;
4502 u32 max_bw_6ghz_ap_lpi;
4503 u32 min_bw_6ghz_ap_vlp;
4504 u32 max_bw_6ghz_ap_vlp;
4505 u32 min_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX];
4506 u32 max_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX];
4507 u32 min_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX];
4508 u32 max_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX];
4509 u32 min_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX];
4510 u32 max_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX];
4511 u32 num_6ghz_reg_rules_ap_sp;
4512 u32 num_6ghz_reg_rules_ap_lpi;
4513 u32 num_6ghz_reg_rules_ap_vlp;
4514 u32 num_6ghz_reg_rules_client_sp[WMI_REG_CLIENT_MAX];
4515 u32 num_6ghz_reg_rules_client_lpi[WMI_REG_CLIENT_MAX];
4516 u32 num_6ghz_reg_rules_client_vlp[WMI_REG_CLIENT_MAX];
4517} __packed;
4518
4519struct wmi_regulatory_ext_rule {
4520 u32 tlv_header;
4521 u32 freq_info;
4522 u32 bw_pwr_info;
4523 u32 flag_info;
4524 u32 psd_power_info;
4525} __packed;
4526
4527struct wmi_vdev_delete_resp_event {
4528 u32 vdev_id;
4529} __packed;
4530
4531struct wmi_peer_delete_resp_event {
4532 u32 vdev_id;
4533 struct wmi_mac_addr peer_macaddr;
4534} __packed;
4535
4536struct wmi_bcn_tx_status_event {
4537 u32 vdev_id;
4538 u32 tx_status;
4539} __packed;
4540
4541struct wmi_vdev_stopped_event {
4542 u32 vdev_id;
4543} __packed;
4544
4545struct wmi_pdev_bss_chan_info_event {
4546 u32 freq; /* Units in MHz */
4547 u32 noise_floor; /* units are dBm */
4548 /* rx clear - how often the channel was unused */
4549 u32 rx_clear_count_low;
4550 u32 rx_clear_count_high;
4551 /* cycle count - elapsed time during measured period, in clock ticks */
4552 u32 cycle_count_low;
4553 u32 cycle_count_high;
4554 /* tx cycle count - elapsed time spent in tx, in clock ticks */
4555 u32 tx_cycle_count_low;
4556 u32 tx_cycle_count_high;
4557 /* rx cycle count - elapsed time spent in rx, in clock ticks */
4558 u32 rx_cycle_count_low;
4559 u32 rx_cycle_count_high;
4560 /*rx_cycle cnt for my bss in 64bits format */
4561 u32 rx_bss_cycle_count_low;
4562 u32 rx_bss_cycle_count_high;
4563 u32 pdev_id;
4564} __packed;
4565
4566#define WMI_VDEV_INSTALL_KEY_COMPL_STATUS_SUCCESS 0
4567
4568struct wmi_vdev_install_key_compl_event {
4569 u32 vdev_id;
4570 struct wmi_mac_addr peer_macaddr;
4571 u32 key_idx;
4572 u32 key_flags;
4573 u32 status;
4574} __packed;
4575
4576struct wmi_vdev_install_key_complete_arg {
4577 u32 vdev_id;
4578 const u8 *macaddr;
4579 u32 key_idx;
4580 u32 key_flags;
4581 u32 status;
4582};
4583
4584struct wmi_peer_assoc_conf_event {
4585 u32 vdev_id;
4586 struct wmi_mac_addr peer_macaddr;
4587} __packed;
4588
4589struct wmi_peer_assoc_conf_arg {
4590 u32 vdev_id;
4591 const u8 *macaddr;
4592};
4593
4594struct wmi_fils_discovery_event {
4595 u32 vdev_id;
4596 u32 fils_tt;
4597 u32 tbtt;
4598} __packed;
4599
4600struct wmi_probe_resp_tx_status_event {
4601 u32 vdev_id;
4602 u32 tx_status;
4603} __packed;
4604
4605/*
4606 * PDEV statistics
4607 */
4608struct wmi_pdev_stats_base {
4609 s32 chan_nf;
4610 u32 tx_frame_count; /* Cycles spent transmitting frames */
4611 u32 rx_frame_count; /* Cycles spent receiving frames */
4612 u32 rx_clear_count; /* Total channel busy time, evidently */
4613 u32 cycle_count; /* Total on-channel time */
4614 u32 phy_err_count;
4615 u32 chan_tx_pwr;
4616} __packed;
4617
4618struct wmi_pdev_stats_extra {
4619 u32 ack_rx_bad;
4620 u32 rts_bad;
4621 u32 rts_good;
4622 u32 fcs_bad;
4623 u32 no_beacons;
4624 u32 mib_int_count;
4625} __packed;
4626
4627struct wmi_pdev_stats_tx {
4628 /* Num HTT cookies queued to dispatch list */
4629 s32 comp_queued;
4630
4631 /* Num HTT cookies dispatched */
4632 s32 comp_delivered;
4633
4634 /* Num MSDU queued to WAL */
4635 s32 msdu_enqued;
4636
4637 /* Num MPDU queue to WAL */
4638 s32 mpdu_enqued;
4639
4640 /* Num MSDUs dropped by WMM limit */
4641 s32 wmm_drop;
4642
4643 /* Num Local frames queued */
4644 s32 local_enqued;
4645
4646 /* Num Local frames done */
4647 s32 local_freed;
4648
4649 /* Num queued to HW */
4650 s32 hw_queued;
4651
4652 /* Num PPDU reaped from HW */
4653 s32 hw_reaped;
4654
4655 /* Num underruns */
4656 s32 underrun;
4657
4658 /* Num hw paused */
4659 u32 hw_paused;
4660
4661 /* Num PPDUs cleaned up in TX abort */
4662 s32 tx_abort;
4663
4664 /* Num MPDUs requeued by SW */
4665 s32 mpdus_requeued;
4666
4667 /* excessive retries */
4668 u32 tx_ko;
4669
4670 u32 tx_xretry;
4671
4672 /* data hw rate code */
4673 u32 data_rc;
4674
4675 /* Scheduler self triggers */
4676 u32 self_triggers;
4677
4678 /* frames dropped due to excessive sw retries */
4679 u32 sw_retry_failure;
4680
4681 /* illegal rate phy errors */
4682 u32 illgl_rate_phy_err;
4683
4684 /* wal pdev continuous xretry */
4685 u32 pdev_cont_xretry;
4686
4687 /* wal pdev tx timeouts */
4688 u32 pdev_tx_timeout;
4689
4690 /* wal pdev resets */
4691 u32 pdev_resets;
4692
4693 /* frames dropped due to non-availability of stateless TIDs */
4694 u32 stateless_tid_alloc_failure;
4695
4696 /* PhY/BB underrun */
4697 u32 phy_underrun;
4698
4699 /* MPDU is more than txop limit */
4700 u32 txop_ovf;
4701
4702 /* Num sequences posted */
4703 u32 seq_posted;
4704
4705 /* Num sequences failed in queueing */
4706 u32 seq_failed_queueing;
4707
4708 /* Num sequences completed */
4709 u32 seq_completed;
4710
4711 /* Num sequences restarted */
4712 u32 seq_restarted;
4713
4714 /* Num of MU sequences posted */
4715 u32 mu_seq_posted;
4716
4717 /* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT
4718 * (Reset,channel change)
4719 */
4720 s32 mpdus_sw_flush;
4721
4722 /* Num MPDUs filtered by HW, all filter condition (TTL expired) */
4723 s32 mpdus_hw_filter;
4724
4725 /* Num MPDUs truncated by PDG (TXOP, TBTT,
4726 * PPDU_duration based on rate, dyn_bw)
4727 */
4728 s32 mpdus_truncated;
4729
4730 /* Num MPDUs that was tried but didn't receive ACK or BA */
4731 s32 mpdus_ack_failed;
4732
4733 /* Num MPDUs that was dropped du to expiry. */
4734 s32 mpdus_expired;
4735} __packed;
4736
4737struct wmi_pdev_stats_rx {
4738 /* Cnts any change in ring routing mid-ppdu */
4739 s32 mid_ppdu_route_change;
4740
4741 /* Total number of statuses processed */
4742 s32 status_rcvd;
4743
4744 /* Extra frags on rings 0-3 */
4745 s32 r0_frags;
4746 s32 r1_frags;
4747 s32 r2_frags;
4748 s32 r3_frags;
4749
4750 /* MSDUs / MPDUs delivered to HTT */
4751 s32 htt_msdus;
4752 s32 htt_mpdus;
4753
4754 /* MSDUs / MPDUs delivered to local stack */
4755 s32 loc_msdus;
4756 s32 loc_mpdus;
4757
4758 /* AMSDUs that have more MSDUs than the status ring size */
4759 s32 oversize_amsdu;
4760
4761 /* Number of PHY errors */
4762 s32 phy_errs;
4763
4764 /* Number of PHY errors drops */
4765 s32 phy_err_drop;
4766
4767 /* Number of mpdu errors - FCS, MIC, ENC etc. */
4768 s32 mpdu_errs;
4769
4770 /* Num overflow errors */
4771 s32 rx_ovfl_errs;
4772} __packed;
4773
4774struct wmi_pdev_stats {
4775 struct wmi_pdev_stats_base base;
4776 struct wmi_pdev_stats_tx tx;
4777 struct wmi_pdev_stats_rx rx;
4778} __packed;
4779
4780#define WLAN_MAX_AC 4
4781#define MAX_TX_RATE_VALUES 10
4782#define MAX_TX_RATE_VALUES 10
4783
4784struct wmi_vdev_stats {
4785 u32 vdev_id;
4786 u32 beacon_snr;
4787 u32 data_snr;
4788 u32 num_tx_frames[WLAN_MAX_AC];
4789 u32 num_rx_frames;
4790 u32 num_tx_frames_retries[WLAN_MAX_AC];
4791 u32 num_tx_frames_failures[WLAN_MAX_AC];
4792 u32 num_rts_fail;
4793 u32 num_rts_success;
4794 u32 num_rx_err;
4795 u32 num_rx_discard;
4796 u32 num_tx_not_acked;
4797 u32 tx_rate_history[MAX_TX_RATE_VALUES];
4798 u32 beacon_rssi_history[MAX_TX_RATE_VALUES];
4799} __packed;
4800
4801struct wmi_bcn_stats {
4802 u32 vdev_id;
4803 u32 tx_bcn_succ_cnt;
4804 u32 tx_bcn_outage_cnt;
4805} __packed;
4806
4807struct wmi_stats_event {
4808 u32 stats_id;
4809 u32 num_pdev_stats;
4810 u32 num_vdev_stats;
4811 u32 num_peer_stats;
4812 u32 num_bcnflt_stats;
4813 u32 num_chan_stats;
4814 u32 num_mib_stats;
4815 u32 pdev_id;
4816 u32 num_bcn_stats;
4817 u32 num_peer_extd_stats;
4818 u32 num_peer_extd2_stats;
4819} __packed;
4820
4821struct wmi_rssi_stats {
4822 u32 vdev_id;
4823 u32 rssi_avg_beacon[WMI_MAX_CHAINS];
4824 u32 rssi_avg_data[WMI_MAX_CHAINS];
4825 struct wmi_mac_addr peer_macaddr;
4826} __packed;
4827
4828struct wmi_per_chain_rssi_stats {
4829 u32 num_per_chain_rssi_stats;
4830} __packed;
4831
4832struct wmi_pdev_ctl_failsafe_chk_event {
4833 u32 pdev_id;
4834 u32 ctl_failsafe_status;
4835} __packed;
4836
4837struct wmi_pdev_csa_switch_ev {
4838 u32 pdev_id;
4839 u32 current_switch_count;
4840 u32 num_vdevs;
4841} __packed;
4842
4843struct wmi_pdev_radar_ev {
4844 u32 pdev_id;
4845 u32 detection_mode;
4846 u32 chan_freq;
4847 u32 chan_width;
4848 u32 detector_id;
4849 u32 segment_id;
4850 u32 timestamp;
4851 u32 is_chirp;
4852 s32 freq_offset;
4853 s32 sidx;
4854} __packed;
4855
4856struct wmi_pdev_temperature_event {
4857 /* temperature value in Celsius degree */
4858 s32 temp;
4859 u32 pdev_id;
4860} __packed;
4861
4862#define WMI_RX_STATUS_OK 0x00
4863#define WMI_RX_STATUS_ERR_CRC 0x01
4864#define WMI_RX_STATUS_ERR_DECRYPT 0x08
4865#define WMI_RX_STATUS_ERR_MIC 0x10
4866#define WMI_RX_STATUS_ERR_KEY_CACHE_MISS 0x20
4867
4868#define WLAN_MGMT_TXRX_HOST_MAX_ANTENNA 4
4869
4870struct mgmt_rx_event_params {
4871 u32 chan_freq;
4872 u32 channel;
4873 u32 snr;
4874 u8 rssi_ctl[WLAN_MGMT_TXRX_HOST_MAX_ANTENNA];
4875 u32 rate;
4876 enum wmi_phy_mode phy_mode;
4877 u32 buf_len;
4878 int status;
4879 u32 flags;
4880 int rssi;
4881 u32 tsf_delta;
4882 u8 pdev_id;
4883};
4884
4885#define ATH_MAX_ANTENNA 4
4886
4887struct wmi_mgmt_rx_hdr {
4888 u32 channel;
4889 u32 snr;
4890 u32 rate;
4891 u32 phy_mode;
4892 u32 buf_len;
4893 u32 status;
4894 u32 rssi_ctl[ATH_MAX_ANTENNA];
4895 u32 flags;
4896 int rssi;
4897 u32 tsf_delta;
4898 u32 rx_tsf_l32;
4899 u32 rx_tsf_u32;
4900 u32 pdev_id;
4901 u32 chan_freq;
4902} __packed;
4903
4904#define MAX_ANTENNA_EIGHT 8
4905
4906struct wmi_rssi_ctl_ext {
4907 u32 tlv_header;
4908 u32 rssi_ctl_ext[MAX_ANTENNA_EIGHT - ATH_MAX_ANTENNA];
4909};
4910
4911struct wmi_mgmt_tx_compl_event {
4912 u32 desc_id;
4913 u32 status;
4914 u32 pdev_id;
4915 u32 ppdu_id;
4916 u32 ack_rssi;
4917} __packed;
4918
4919struct wmi_scan_event {
4920 u32 event_type; /* %WMI_SCAN_EVENT_ */
4921 u32 reason; /* %WMI_SCAN_REASON_ */
4922 u32 channel_freq; /* only valid for WMI_SCAN_EVENT_FOREIGN_CHANNEL */
4923 u32 scan_req_id;
4924 u32 scan_id;
4925 u32 vdev_id;
4926 /* TSF Timestamp when the scan event (%WMI_SCAN_EVENT_) is completed
4927 * In case of AP it is TSF of the AP vdev
4928 * In case of STA connected state, this is the TSF of the AP
4929 * In case of STA not connected, it will be the free running HW timer
4930 */
4931 u32 tsf_timestamp;
4932} __packed;
4933
4934struct wmi_peer_sta_kickout_arg {
4935 const u8 *mac_addr;
4936};
4937
4938struct wmi_peer_sta_kickout_event {
4939 struct wmi_mac_addr peer_macaddr;
4940} __packed;
4941
4942enum wmi_roam_reason {
4943 WMI_ROAM_REASON_BETTER_AP = 1,
4944 WMI_ROAM_REASON_BEACON_MISS = 2,
4945 WMI_ROAM_REASON_LOW_RSSI = 3,
4946 WMI_ROAM_REASON_SUITABLE_AP_FOUND = 4,
4947 WMI_ROAM_REASON_HO_FAILED = 5,
4948
4949 /* keep last */
4950 WMI_ROAM_REASON_MAX,
4951};
4952
4953struct wmi_roam_event {
4954 u32 vdev_id;
4955 u32 reason;
4956 u32 rssi;
4957} __packed;
4958
4959#define WMI_CHAN_INFO_START_RESP 0
4960#define WMI_CHAN_INFO_END_RESP 1
4961
4962struct wmi_chan_info_event {
4963 u32 err_code;
4964 u32 freq;
4965 u32 cmd_flags;
4966 u32 noise_floor;
4967 u32 rx_clear_count;
4968 u32 cycle_count;
4969 u32 chan_tx_pwr_range;
4970 u32 chan_tx_pwr_tp;
4971 u32 rx_frame_count;
4972 u32 my_bss_rx_cycle_count;
4973 u32 rx_11b_mode_data_duration;
4974 u32 tx_frame_cnt;
4975 u32 mac_clk_mhz;
4976 u32 vdev_id;
4977} __packed;
4978
4979struct ath11k_targ_cap {
4980 u32 phy_capability;
4981 u32 max_frag_entry;
4982 u32 num_rf_chains;
4983 u32 ht_cap_info;
4984 u32 vht_cap_info;
4985 u32 vht_supp_mcs;
4986 u32 hw_min_tx_power;
4987 u32 hw_max_tx_power;
4988 u32 sys_cap_info;
4989 u32 min_pkt_size_enable;
4990 u32 max_bcn_ie_size;
4991 u32 max_num_scan_channels;
4992 u32 max_supported_macs;
4993 u32 wmi_fw_sub_feat_caps;
4994 u32 txrx_chainmask;
4995 u32 default_dbs_hw_mode_index;
4996 u32 num_msdu_desc;
4997};
4998
4999enum wmi_vdev_type {
5000 WMI_VDEV_TYPE_UNSPEC = 0,
5001 WMI_VDEV_TYPE_AP = 1,
5002 WMI_VDEV_TYPE_STA = 2,
5003 WMI_VDEV_TYPE_IBSS = 3,
5004 WMI_VDEV_TYPE_MONITOR = 4,
5005};
5006
5007enum wmi_vdev_subtype {
5008 WMI_VDEV_SUBTYPE_NONE,
5009 WMI_VDEV_SUBTYPE_P2P_DEVICE,
5010 WMI_VDEV_SUBTYPE_P2P_CLIENT,
5011 WMI_VDEV_SUBTYPE_P2P_GO,
5012 WMI_VDEV_SUBTYPE_PROXY_STA,
5013 WMI_VDEV_SUBTYPE_MESH_NON_11S,
5014 WMI_VDEV_SUBTYPE_MESH_11S,
5015};
5016
5017enum wmi_sta_powersave_param {
5018 WMI_STA_PS_PARAM_RX_WAKE_POLICY = 0,
5019 WMI_STA_PS_PARAM_TX_WAKE_THRESHOLD = 1,
5020 WMI_STA_PS_PARAM_PSPOLL_COUNT = 2,
5021 WMI_STA_PS_PARAM_INACTIVITY_TIME = 3,
5022 WMI_STA_PS_PARAM_UAPSD = 4,
5023};
5024
5025#define WMI_UAPSD_AC_TYPE_DELI 0
5026#define WMI_UAPSD_AC_TYPE_TRIG 1
5027
5028#define WMI_UAPSD_AC_BIT_MASK(ac, type) \
5029 ((type == WMI_UAPSD_AC_TYPE_DELI) ? \
5030 (1 << (ac << 1)) : (1 << ((ac << 1) + 1)))
5031
5032enum wmi_sta_ps_param_uapsd {
5033 WMI_STA_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0),
5034 WMI_STA_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1),
5035 WMI_STA_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2),
5036 WMI_STA_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3),
5037 WMI_STA_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4),
5038 WMI_STA_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5),
5039 WMI_STA_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6),
5040 WMI_STA_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7),
5041};
5042
5043#define WMI_STA_UAPSD_MAX_INTERVAL_MSEC UINT_MAX
5044
5045struct wmi_sta_uapsd_auto_trig_param {
5046 u32 wmm_ac;
5047 u32 user_priority;
5048 u32 service_interval;
5049 u32 suspend_interval;
5050 u32 delay_interval;
5051};
5052
5053struct wmi_sta_uapsd_auto_trig_cmd_fixed_param {
5054 u32 vdev_id;
5055 struct wmi_mac_addr peer_macaddr;
5056 u32 num_ac;
5057};
5058
5059struct wmi_sta_uapsd_auto_trig_arg {
5060 u32 wmm_ac;
5061 u32 user_priority;
5062 u32 service_interval;
5063 u32 suspend_interval;
5064 u32 delay_interval;
5065};
5066
5067enum wmi_sta_ps_param_tx_wake_threshold {
5068 WMI_STA_PS_TX_WAKE_THRESHOLD_NEVER = 0,
5069 WMI_STA_PS_TX_WAKE_THRESHOLD_ALWAYS = 1,
5070
5071 /* Values greater than one indicate that many TX attempts per beacon
5072 * interval before the STA will wake up
5073 */
5074};
5075
5076/* The maximum number of PS-Poll frames the FW will send in response to
5077 * traffic advertised in TIM before waking up (by sending a null frame with PS
5078 * = 0). Value 0 has a special meaning: there is no maximum count and the FW
5079 * will send as many PS-Poll as are necessary to retrieve buffered BU. This
5080 * parameter is used when the RX wake policy is
5081 * WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD and ignored when the RX wake
5082 * policy is WMI_STA_PS_RX_WAKE_POLICY_WAKE.
5083 */
5084enum wmi_sta_ps_param_pspoll_count {
5085 WMI_STA_PS_PSPOLL_COUNT_NO_MAX = 0,
5086 /* Values greater than 0 indicate the maximum number of PS-Poll frames
5087 * FW will send before waking up.
5088 */
5089};
5090
5091/* U-APSD configuration of peer station from (re)assoc request and TSPECs */
5092enum wmi_ap_ps_param_uapsd {
5093 WMI_AP_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0),
5094 WMI_AP_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1),
5095 WMI_AP_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2),
5096 WMI_AP_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3),
5097 WMI_AP_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4),
5098 WMI_AP_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5),
5099 WMI_AP_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6),
5100 WMI_AP_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7),
5101};
5102
5103/* U-APSD maximum service period of peer station */
5104enum wmi_ap_ps_peer_param_max_sp {
5105 WMI_AP_PS_PEER_PARAM_MAX_SP_UNLIMITED = 0,
5106 WMI_AP_PS_PEER_PARAM_MAX_SP_2 = 1,
5107 WMI_AP_PS_PEER_PARAM_MAX_SP_4 = 2,
5108 WMI_AP_PS_PEER_PARAM_MAX_SP_6 = 3,
5109 MAX_WMI_AP_PS_PEER_PARAM_MAX_SP,
5110};
5111
5112enum wmi_ap_ps_peer_param {
5113 /** Set uapsd configuration for a given peer.
5114 *
5115 * This include the delivery and trigger enabled state for each AC.
5116 * The host MLME needs to set this based on AP capability and stations
5117 * request Set in the association request received from the station.
5118 *
5119 * Lower 8 bits of the value specify the UAPSD configuration.
5120 *
5121 * (see enum wmi_ap_ps_param_uapsd)
5122 * The default value is 0.
5123 */
5124 WMI_AP_PS_PEER_PARAM_UAPSD = 0,
5125
5126 /**
5127 * Set the service period for a UAPSD capable station
5128 *
5129 * The service period from wme ie in the (re)assoc request frame.
5130 *
5131 * (see enum wmi_ap_ps_peer_param_max_sp)
5132 */
5133 WMI_AP_PS_PEER_PARAM_MAX_SP = 1,
5134
5135 /** Time in seconds for aging out buffered frames
5136 * for STA in power save
5137 */
5138 WMI_AP_PS_PEER_PARAM_AGEOUT_TIME = 2,
5139
5140 /** Specify frame types that are considered SIFS
5141 * RESP trigger frame
5142 */
5143 WMI_AP_PS_PEER_PARAM_SIFS_RESP_FRMTYPE = 3,
5144
5145 /** Specifies the trigger state of TID.
5146 * Valid only for UAPSD frame type
5147 */
5148 WMI_AP_PS_PEER_PARAM_SIFS_RESP_UAPSD = 4,
5149
5150 /* Specifies the WNM sleep state of a STA */
5151 WMI_AP_PS_PEER_PARAM_WNM_SLEEP = 5,
5152};
5153
5154#define DISABLE_SIFS_RESPONSE_TRIGGER 0
5155
5156#define WMI_MAX_KEY_INDEX 3
5157#define WMI_MAX_KEY_LEN 32
5158
5159#define WMI_KEY_PAIRWISE 0x00
5160#define WMI_KEY_GROUP 0x01
5161
5162#define WMI_CIPHER_NONE 0x0 /* clear key */
5163#define WMI_CIPHER_WEP 0x1
5164#define WMI_CIPHER_TKIP 0x2
5165#define WMI_CIPHER_AES_OCB 0x3
5166#define WMI_CIPHER_AES_CCM 0x4
5167#define WMI_CIPHER_WAPI 0x5
5168#define WMI_CIPHER_CKIP 0x6
5169#define WMI_CIPHER_AES_CMAC 0x7
5170#define WMI_CIPHER_ANY 0x8
5171#define WMI_CIPHER_AES_GCM 0x9
5172#define WMI_CIPHER_AES_GMAC 0xa
5173
5174/* Value to disable fixed rate setting */
5175#define WMI_FIXED_RATE_NONE (0xffff)
5176
5177#define ATH11K_RC_VERSION_OFFSET 28
5178#define ATH11K_RC_PREAMBLE_OFFSET 8
5179#define ATH11K_RC_NSS_OFFSET 5
5180
5181#define ATH11K_HW_RATE_CODE(rate, nss, preamble) \
5182 ((1 << ATH11K_RC_VERSION_OFFSET) | \
5183 ((nss) << ATH11K_RC_NSS_OFFSET) | \
5184 ((preamble) << ATH11K_RC_PREAMBLE_OFFSET) | \
5185 (rate))
5186
5187/* Preamble types to be used with VDEV fixed rate configuration */
5188enum wmi_rate_preamble {
5189 WMI_RATE_PREAMBLE_OFDM,
5190 WMI_RATE_PREAMBLE_CCK,
5191 WMI_RATE_PREAMBLE_HT,
5192 WMI_RATE_PREAMBLE_VHT,
5193 WMI_RATE_PREAMBLE_HE,
5194};
5195
5196/**
5197 * enum wmi_rtscts_prot_mode - Enable/Disable RTS/CTS and CTS2Self Protection.
5198 * @WMI_RTS_CTS_DISABLED: RTS/CTS protection is disabled.
5199 * @WMI_USE_RTS_CTS: RTS/CTS Enabled.
5200 * @WMI_USE_CTS2SELF: CTS to self protection Enabled.
5201 */
5202enum wmi_rtscts_prot_mode {
5203 WMI_RTS_CTS_DISABLED = 0,
5204 WMI_USE_RTS_CTS = 1,
5205 WMI_USE_CTS2SELF = 2,
5206};
5207
5208/**
5209 * enum wmi_rtscts_profile - Selection of RTS CTS profile along with enabling
5210 * protection mode.
5211 * @WMI_RTSCTS_FOR_NO_RATESERIES: Neither of rate-series should use RTS-CTS
5212 * @WMI_RTSCTS_FOR_SECOND_RATESERIES: Only second rate-series will use RTS-CTS
5213 * @WMI_RTSCTS_ACROSS_SW_RETRIES: Only the second rate-series will use RTS-CTS,
5214 * but if there's a sw retry, both the rate
5215 * series will use RTS-CTS.
5216 * @WMI_RTSCTS_ERP: RTS/CTS used for ERP protection for every PPDU.
5217 * @WMI_RTSCTS_FOR_ALL_RATESERIES: Enable RTS-CTS for all rate series.
5218 */
5219enum wmi_rtscts_profile {
5220 WMI_RTSCTS_FOR_NO_RATESERIES = 0,
5221 WMI_RTSCTS_FOR_SECOND_RATESERIES = 1,
5222 WMI_RTSCTS_ACROSS_SW_RETRIES = 2,
5223 WMI_RTSCTS_ERP = 3,
5224 WMI_RTSCTS_FOR_ALL_RATESERIES = 4,
5225};
5226
5227struct ath11k_hal_reg_cap {
5228 u32 eeprom_rd;
5229 u32 eeprom_rd_ext;
5230 u32 regcap1;
5231 u32 regcap2;
5232 u32 wireless_modes;
5233 u32 low_2ghz_chan;
5234 u32 high_2ghz_chan;
5235 u32 low_5ghz_chan;
5236 u32 high_5ghz_chan;
5237};
5238
5239struct ath11k_mem_chunk {
5240 void *vaddr;
5241 dma_addr_t paddr;
5242 u32 len;
5243 u32 req_id;
5244};
5245
5246#define WMI_SKB_HEADROOM sizeof(struct wmi_cmd_hdr)
5247
5248enum wmi_sta_ps_param_rx_wake_policy {
5249 WMI_STA_PS_RX_WAKE_POLICY_WAKE = 0,
5250 WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD = 1,
5251};
5252
5253/* Do not change existing values! Used by ath11k_frame_mode parameter
5254 * module parameter.
5255 */
5256enum ath11k_hw_txrx_mode {
5257 ATH11K_HW_TXRX_RAW = 0,
5258 ATH11K_HW_TXRX_NATIVE_WIFI = 1,
5259 ATH11K_HW_TXRX_ETHERNET = 2,
5260};
5261
5262struct wmi_wmm_params {
5263 u32 tlv_header;
5264 u32 cwmin;
5265 u32 cwmax;
5266 u32 aifs;
5267 u32 txoplimit;
5268 u32 acm;
5269 u32 no_ack;
5270} __packed;
5271
5272struct wmi_wmm_params_arg {
5273 u8 acm;
5274 u8 aifs;
5275 u16 cwmin;
5276 u16 cwmax;
5277 u16 txop;
5278 u8 no_ack;
5279};
5280
5281struct wmi_vdev_set_wmm_params_cmd {
5282 u32 tlv_header;
5283 u32 vdev_id;
5284 struct wmi_wmm_params wmm_params[4];
5285 u32 wmm_param_type;
5286} __packed;
5287
5288struct wmi_wmm_params_all_arg {
5289 struct wmi_wmm_params_arg ac_be;
5290 struct wmi_wmm_params_arg ac_bk;
5291 struct wmi_wmm_params_arg ac_vi;
5292 struct wmi_wmm_params_arg ac_vo;
5293};
5294
5295#define ATH11K_TWT_DEF_STA_CONG_TIMER_MS 5000
5296#define ATH11K_TWT_DEF_DEFAULT_SLOT_SIZE 10
5297#define ATH11K_TWT_DEF_CONGESTION_THRESH_SETUP 50
5298#define ATH11K_TWT_DEF_CONGESTION_THRESH_TEARDOWN 20
5299#define ATH11K_TWT_DEF_CONGESTION_THRESH_CRITICAL 100
5300#define ATH11K_TWT_DEF_INTERFERENCE_THRESH_TEARDOWN 80
5301#define ATH11K_TWT_DEF_INTERFERENCE_THRESH_SETUP 50
5302#define ATH11K_TWT_DEF_MIN_NO_STA_SETUP 10
5303#define ATH11K_TWT_DEF_MIN_NO_STA_TEARDOWN 2
5304#define ATH11K_TWT_DEF_NO_OF_BCAST_MCAST_SLOTS 2
5305#define ATH11K_TWT_DEF_MIN_NO_TWT_SLOTS 2
5306#define ATH11K_TWT_DEF_MAX_NO_STA_TWT 500
5307#define ATH11K_TWT_DEF_MODE_CHECK_INTERVAL 10000
5308#define ATH11K_TWT_DEF_ADD_STA_SLOT_INTERVAL 1000
5309#define ATH11K_TWT_DEF_REMOVE_STA_SLOT_INTERVAL 5000
5310
5311struct wmi_twt_enable_params {
5312 u32 sta_cong_timer_ms;
5313 u32 mbss_support;
5314 u32 default_slot_size;
5315 u32 congestion_thresh_setup;
5316 u32 congestion_thresh_teardown;
5317 u32 congestion_thresh_critical;
5318 u32 interference_thresh_teardown;
5319 u32 interference_thresh_setup;
5320 u32 min_no_sta_setup;
5321 u32 min_no_sta_teardown;
5322 u32 no_of_bcast_mcast_slots;
5323 u32 min_no_twt_slots;
5324 u32 max_no_sta_twt;
5325 u32 mode_check_interval;
5326 u32 add_sta_slot_interval;
5327 u32 remove_sta_slot_interval;
5328};
5329
5330struct wmi_twt_enable_params_cmd {
5331 u32 tlv_header;
5332 u32 pdev_id;
5333 u32 sta_cong_timer_ms;
5334 u32 mbss_support;
5335 u32 default_slot_size;
5336 u32 congestion_thresh_setup;
5337 u32 congestion_thresh_teardown;
5338 u32 congestion_thresh_critical;
5339 u32 interference_thresh_teardown;
5340 u32 interference_thresh_setup;
5341 u32 min_no_sta_setup;
5342 u32 min_no_sta_teardown;
5343 u32 no_of_bcast_mcast_slots;
5344 u32 min_no_twt_slots;
5345 u32 max_no_sta_twt;
5346 u32 mode_check_interval;
5347 u32 add_sta_slot_interval;
5348 u32 remove_sta_slot_interval;
5349} __packed;
5350
5351struct wmi_twt_disable_params_cmd {
5352 u32 tlv_header;
5353 u32 pdev_id;
5354} __packed;
5355
5356enum WMI_HOST_TWT_COMMAND {
5357 WMI_HOST_TWT_COMMAND_REQUEST_TWT = 0,
5358 WMI_HOST_TWT_COMMAND_SUGGEST_TWT,
5359 WMI_HOST_TWT_COMMAND_DEMAND_TWT,
5360 WMI_HOST_TWT_COMMAND_TWT_GROUPING,
5361 WMI_HOST_TWT_COMMAND_ACCEPT_TWT,
5362 WMI_HOST_TWT_COMMAND_ALTERNATE_TWT,
5363 WMI_HOST_TWT_COMMAND_DICTATE_TWT,
5364 WMI_HOST_TWT_COMMAND_REJECT_TWT,
5365};
5366
5367#define WMI_TWT_ADD_DIALOG_FLAG_BCAST BIT(8)
5368#define WMI_TWT_ADD_DIALOG_FLAG_TRIGGER BIT(9)
5369#define WMI_TWT_ADD_DIALOG_FLAG_FLOW_TYPE BIT(10)
5370#define WMI_TWT_ADD_DIALOG_FLAG_PROTECTION BIT(11)
5371
5372struct wmi_twt_add_dialog_params_cmd {
5373 u32 tlv_header;
5374 u32 vdev_id;
5375 struct wmi_mac_addr peer_macaddr;
5376 u32 dialog_id;
5377 u32 wake_intvl_us;
5378 u32 wake_intvl_mantis;
5379 u32 wake_dura_us;
5380 u32 sp_offset_us;
5381 u32 flags;
5382} __packed;
5383
5384struct wmi_twt_add_dialog_params {
5385 u32 vdev_id;
5386 u8 peer_macaddr[ETH_ALEN];
5387 u32 dialog_id;
5388 u32 wake_intvl_us;
5389 u32 wake_intvl_mantis;
5390 u32 wake_dura_us;
5391 u32 sp_offset_us;
5392 u8 twt_cmd;
5393 u8 flag_bcast;
5394 u8 flag_trigger;
5395 u8 flag_flow_type;
5396 u8 flag_protection;
5397} __packed;
5398
5399enum wmi_twt_add_dialog_status {
5400 WMI_ADD_TWT_STATUS_OK,
5401 WMI_ADD_TWT_STATUS_TWT_NOT_ENABLED,
5402 WMI_ADD_TWT_STATUS_USED_DIALOG_ID,
5403 WMI_ADD_TWT_STATUS_INVALID_PARAM,
5404 WMI_ADD_TWT_STATUS_NOT_READY,
5405 WMI_ADD_TWT_STATUS_NO_RESOURCE,
5406 WMI_ADD_TWT_STATUS_NO_ACK,
5407 WMI_ADD_TWT_STATUS_NO_RESPONSE,
5408 WMI_ADD_TWT_STATUS_DENIED,
5409 WMI_ADD_TWT_STATUS_UNKNOWN_ERROR,
5410};
5411
5412struct wmi_twt_add_dialog_event {
5413 u32 vdev_id;
5414 struct wmi_mac_addr peer_macaddr;
5415 u32 dialog_id;
5416 u32 status;
5417} __packed;
5418
5419struct wmi_twt_del_dialog_params {
5420 u32 vdev_id;
5421 u8 peer_macaddr[ETH_ALEN];
5422 u32 dialog_id;
5423} __packed;
5424
5425struct wmi_twt_del_dialog_params_cmd {
5426 u32 tlv_header;
5427 u32 vdev_id;
5428 struct wmi_mac_addr peer_macaddr;
5429 u32 dialog_id;
5430} __packed;
5431
5432struct wmi_twt_pause_dialog_params {
5433 u32 vdev_id;
5434 u8 peer_macaddr[ETH_ALEN];
5435 u32 dialog_id;
5436} __packed;
5437
5438struct wmi_twt_pause_dialog_params_cmd {
5439 u32 tlv_header;
5440 u32 vdev_id;
5441 struct wmi_mac_addr peer_macaddr;
5442 u32 dialog_id;
5443} __packed;
5444
5445struct wmi_twt_resume_dialog_params {
5446 u32 vdev_id;
5447 u8 peer_macaddr[ETH_ALEN];
5448 u32 dialog_id;
5449 u32 sp_offset_us;
5450 u32 next_twt_size;
5451} __packed;
5452
5453struct wmi_twt_resume_dialog_params_cmd {
5454 u32 tlv_header;
5455 u32 vdev_id;
5456 struct wmi_mac_addr peer_macaddr;
5457 u32 dialog_id;
5458 u32 sp_offset_us;
5459 u32 next_twt_size;
5460} __packed;
5461
5462struct wmi_obss_spatial_reuse_params_cmd {
5463 u32 tlv_header;
5464 u32 pdev_id;
5465 u32 enable;
5466 s32 obss_min;
5467 s32 obss_max;
5468 u32 vdev_id;
5469} __packed;
5470
5471struct wmi_pdev_obss_pd_bitmap_cmd {
5472 u32 tlv_header;
5473 u32 pdev_id;
5474 u32 bitmap[2];
5475} __packed;
5476
5477#define ATH11K_BSS_COLOR_COLLISION_SCAN_PERIOD_MS 200
5478#define ATH11K_OBSS_COLOR_COLLISION_DETECTION_DISABLE 0
5479#define ATH11K_OBSS_COLOR_COLLISION_DETECTION 1
5480
5481#define ATH11K_BSS_COLOR_COLLISION_DETECTION_STA_PERIOD_MS 10000
5482#define ATH11K_BSS_COLOR_COLLISION_DETECTION_AP_PERIOD_MS 5000
5483
5484enum wmi_bss_color_collision {
5485 WMI_BSS_COLOR_COLLISION_DISABLE = 0,
5486 WMI_BSS_COLOR_COLLISION_DETECTION,
5487 WMI_BSS_COLOR_FREE_SLOT_TIMER_EXPIRY,
5488 WMI_BSS_COLOR_FREE_SLOT_AVAILABLE,
5489};
5490
5491struct wmi_obss_color_collision_cfg_params_cmd {
5492 u32 tlv_header;
5493 u32 vdev_id;
5494 u32 flags;
5495 u32 evt_type;
5496 u32 current_bss_color;
5497 u32 detection_period_ms;
5498 u32 scan_period_ms;
5499 u32 free_slot_expiry_time_ms;
5500} __packed;
5501
5502struct wmi_bss_color_change_enable_params_cmd {
5503 u32 tlv_header;
5504 u32 vdev_id;
5505 u32 enable;
5506} __packed;
5507
5508struct wmi_obss_color_collision_event {
5509 u32 vdev_id;
5510 u32 evt_type;
5511 u64 obss_color_bitmap;
5512} __packed;
5513
5514#define ATH11K_IPV4_TH_SEED_SIZE 5
5515#define ATH11K_IPV6_TH_SEED_SIZE 11
5516
5517struct ath11k_wmi_pdev_lro_config_cmd {
5518 u32 tlv_header;
5519 u32 lro_enable;
5520 u32 res;
5521 u32 th_4[ATH11K_IPV4_TH_SEED_SIZE];
5522 u32 th_6[ATH11K_IPV6_TH_SEED_SIZE];
5523 u32 pdev_id;
5524} __packed;
5525
5526#define ATH11K_WMI_SPECTRAL_COUNT_DEFAULT 0
5527#define ATH11K_WMI_SPECTRAL_PERIOD_DEFAULT 224
5528#define ATH11K_WMI_SPECTRAL_PRIORITY_DEFAULT 1
5529#define ATH11K_WMI_SPECTRAL_FFT_SIZE_DEFAULT 7
5530#define ATH11K_WMI_SPECTRAL_GC_ENA_DEFAULT 1
5531#define ATH11K_WMI_SPECTRAL_RESTART_ENA_DEFAULT 0
5532#define ATH11K_WMI_SPECTRAL_NOISE_FLOOR_REF_DEFAULT -96
5533#define ATH11K_WMI_SPECTRAL_INIT_DELAY_DEFAULT 80
5534#define ATH11K_WMI_SPECTRAL_NB_TONE_THR_DEFAULT 12
5535#define ATH11K_WMI_SPECTRAL_STR_BIN_THR_DEFAULT 8
5536#define ATH11K_WMI_SPECTRAL_WB_RPT_MODE_DEFAULT 0
5537#define ATH11K_WMI_SPECTRAL_RSSI_RPT_MODE_DEFAULT 0
5538#define ATH11K_WMI_SPECTRAL_RSSI_THR_DEFAULT 0xf0
5539#define ATH11K_WMI_SPECTRAL_PWR_FORMAT_DEFAULT 0
5540#define ATH11K_WMI_SPECTRAL_RPT_MODE_DEFAULT 2
5541#define ATH11K_WMI_SPECTRAL_BIN_SCALE_DEFAULT 1
5542#define ATH11K_WMI_SPECTRAL_DBM_ADJ_DEFAULT 1
5543#define ATH11K_WMI_SPECTRAL_CHN_MASK_DEFAULT 1
5544
5545struct ath11k_wmi_vdev_spectral_conf_param {
5546 u32 vdev_id;
5547 u32 scan_count;
5548 u32 scan_period;
5549 u32 scan_priority;
5550 u32 scan_fft_size;
5551 u32 scan_gc_ena;
5552 u32 scan_restart_ena;
5553 u32 scan_noise_floor_ref;
5554 u32 scan_init_delay;
5555 u32 scan_nb_tone_thr;
5556 u32 scan_str_bin_thr;
5557 u32 scan_wb_rpt_mode;
5558 u32 scan_rssi_rpt_mode;
5559 u32 scan_rssi_thr;
5560 u32 scan_pwr_format;
5561 u32 scan_rpt_mode;
5562 u32 scan_bin_scale;
5563 u32 scan_dbm_adj;
5564 u32 scan_chn_mask;
5565} __packed;
5566
5567struct ath11k_wmi_vdev_spectral_conf_cmd {
5568 u32 tlv_header;
5569 struct ath11k_wmi_vdev_spectral_conf_param param;
5570} __packed;
5571
5572#define ATH11K_WMI_SPECTRAL_TRIGGER_CMD_TRIGGER 1
5573#define ATH11K_WMI_SPECTRAL_TRIGGER_CMD_CLEAR 2
5574#define ATH11K_WMI_SPECTRAL_ENABLE_CMD_ENABLE 1
5575#define ATH11K_WMI_SPECTRAL_ENABLE_CMD_DISABLE 2
5576
5577struct ath11k_wmi_vdev_spectral_enable_cmd {
5578 u32 tlv_header;
5579 u32 vdev_id;
5580 u32 trigger_cmd;
5581 u32 enable_cmd;
5582} __packed;
5583
5584struct ath11k_wmi_pdev_dma_ring_cfg_req_cmd {
5585 u32 tlv_header;
5586 u32 pdev_id;
5587 u32 module_id; /* see enum wmi_direct_buffer_module */
5588 u32 base_paddr_lo;
5589 u32 base_paddr_hi;
5590 u32 head_idx_paddr_lo;
5591 u32 head_idx_paddr_hi;
5592 u32 tail_idx_paddr_lo;
5593 u32 tail_idx_paddr_hi;
5594 u32 num_elems; /* Number of elems in the ring */
5595 u32 buf_size; /* size of allocated buffer in bytes */
5596
5597 /* Number of wmi_dma_buf_release_entry packed together */
5598 u32 num_resp_per_event;
5599
5600 /* Target should timeout and send whatever resp
5601 * it has if this time expires, units in milliseconds
5602 */
5603 u32 event_timeout_ms;
5604} __packed;
5605
5606struct ath11k_wmi_dma_buf_release_fixed_param {
5607 u32 pdev_id;
5608 u32 module_id;
5609 u32 num_buf_release_entry;
5610 u32 num_meta_data_entry;
5611} __packed;
5612
5613struct wmi_dma_buf_release_entry {
5614 u32 tlv_header;
5615 u32 paddr_lo;
5616
5617 /* Bits 11:0: address of data
5618 * Bits 31:12: host context data
5619 */
5620 u32 paddr_hi;
5621} __packed;
5622
5623#define WMI_SPECTRAL_META_INFO1_FREQ1 GENMASK(15, 0)
5624#define WMI_SPECTRAL_META_INFO1_FREQ2 GENMASK(31, 16)
5625
5626#define WMI_SPECTRAL_META_INFO2_CHN_WIDTH GENMASK(7, 0)
5627
5628struct wmi_dma_buf_release_meta_data {
5629 u32 tlv_header;
5630 s32 noise_floor[WMI_MAX_CHAINS];
5631 u32 reset_delay;
5632 u32 freq1;
5633 u32 freq2;
5634 u32 ch_width;
5635} __packed;
5636
5637enum wmi_fils_discovery_cmd_type {
5638 WMI_FILS_DISCOVERY_CMD,
5639 WMI_UNSOL_BCAST_PROBE_RESP,
5640};
5641
5642struct wmi_fils_discovery_cmd {
5643 u32 tlv_header;
5644 u32 vdev_id;
5645 u32 interval;
5646 u32 config; /* enum wmi_fils_discovery_cmd_type */
5647} __packed;
5648
5649struct wmi_fils_discovery_tmpl_cmd {
5650 u32 tlv_header;
5651 u32 vdev_id;
5652 u32 buf_len;
5653} __packed;
5654
5655struct wmi_probe_tmpl_cmd {
5656 u32 tlv_header;
5657 u32 vdev_id;
5658 u32 buf_len;
5659} __packed;
5660
5661struct target_resource_config {
5662 u32 num_vdevs;
5663 u32 num_peers;
5664 u32 num_active_peers;
5665 u32 num_offload_peers;
5666 u32 num_offload_reorder_buffs;
5667 u32 num_peer_keys;
5668 u32 num_tids;
5669 u32 ast_skid_limit;
5670 u32 tx_chain_mask;
5671 u32 rx_chain_mask;
5672 u32 rx_timeout_pri[4];
5673 u32 rx_decap_mode;
5674 u32 scan_max_pending_req;
5675 u32 bmiss_offload_max_vdev;
5676 u32 roam_offload_max_vdev;
5677 u32 roam_offload_max_ap_profiles;
5678 u32 num_mcast_groups;
5679 u32 num_mcast_table_elems;
5680 u32 mcast2ucast_mode;
5681 u32 tx_dbg_log_size;
5682 u32 num_wds_entries;
5683 u32 dma_burst_size;
5684 u32 mac_aggr_delim;
5685 u32 rx_skip_defrag_timeout_dup_detection_check;
5686 u32 vow_config;
5687 u32 gtk_offload_max_vdev;
5688 u32 num_msdu_desc;
5689 u32 max_frag_entries;
5690 u32 max_peer_ext_stats;
5691 u32 smart_ant_cap;
5692 u32 bk_minfree;
5693 u32 be_minfree;
5694 u32 vi_minfree;
5695 u32 vo_minfree;
5696 u32 rx_batchmode;
5697 u32 tt_support;
5698 u32 flag1;
5699 u32 iphdr_pad_config;
5700 u32 qwrap_config:16,
5701 alloc_frag_desc_for_data_pkt:16;
5702 u32 num_tdls_vdevs;
5703 u32 num_tdls_conn_table_entries;
5704 u32 beacon_tx_offload_max_vdev;
5705 u32 num_multicast_filter_entries;
5706 u32 num_wow_filters;
5707 u32 num_keep_alive_pattern;
5708 u32 keep_alive_pattern_size;
5709 u32 max_tdls_concurrent_sleep_sta;
5710 u32 max_tdls_concurrent_buffer_sta;
5711 u32 wmi_send_separate;
5712 u32 num_ocb_vdevs;
5713 u32 num_ocb_channels;
5714 u32 num_ocb_schedules;
5715 u32 num_ns_ext_tuples_cfg;
5716 u32 bpf_instruction_size;
5717 u32 max_bssid_rx_filters;
5718 u32 use_pdev_id;
5719 u32 peer_map_unmap_v2_support;
5720 u32 sched_params;
5721 u32 twt_ap_pdev_count;
5722 u32 twt_ap_sta_count;
5723 u8 is_reg_cc_ext_event_supported;
5724 u32 ema_max_vap_cnt;
5725 u32 ema_max_profile_period;
5726};
5727
5728enum wmi_debug_log_param {
5729 WMI_DEBUG_LOG_PARAM_LOG_LEVEL = 0x1,
5730 WMI_DEBUG_LOG_PARAM_VDEV_ENABLE,
5731 WMI_DEBUG_LOG_PARAM_VDEV_DISABLE,
5732 WMI_DEBUG_LOG_PARAM_VDEV_ENABLE_BITMAP,
5733 WMI_DEBUG_LOG_PARAM_MOD_ENABLE_BITMAP,
5734 WMI_DEBUG_LOG_PARAM_WOW_MOD_ENABLE_BITMAP,
5735};
5736
5737struct wmi_debug_log_config_cmd_fixed_param {
5738 u32 tlv_header;
5739 u32 dbg_log_param;
5740 u32 value;
5741} __packed;
5742
5743#define WMI_MAX_MEM_REQS 32
5744
5745#define MAX_RADIOS 3
5746
5747#define WMI_SERVICE_READY_TIMEOUT_HZ (5 * HZ)
5748#define WMI_SEND_TIMEOUT_HZ (3 * HZ)
5749
5750enum ath11k_wmi_peer_ps_state {
5751 WMI_PEER_PS_STATE_OFF,
5752 WMI_PEER_PS_STATE_ON,
5753 WMI_PEER_PS_STATE_DISABLED,
5754};
5755
5756enum wmi_peer_ps_supported_bitmap {
5757 /* Used to indicate that power save state change is valid */
5758 WMI_PEER_PS_VALID = 0x1,
5759 WMI_PEER_PS_STATE_TIMESTAMP = 0x2,
5760};
5761
5762struct wmi_peer_sta_ps_state_chg_event {
5763 struct wmi_mac_addr peer_macaddr;
5764 u32 peer_ps_state;
5765 u32 ps_supported_bitmap;
5766 u32 peer_ps_valid;
5767 u32 peer_ps_timestamp;
5768} __packed;
5769
5770struct ath11k_wmi_base {
5771 struct ath11k_base *ab;
5772 struct ath11k_pdev_wmi wmi[MAX_RADIOS];
5773 enum ath11k_htc_ep_id wmi_endpoint_id[MAX_RADIOS];
5774 u32 max_msg_len[MAX_RADIOS];
5775
5776 struct completion service_ready;
5777 struct completion unified_ready;
5778 DECLARE_BITMAP(svc_map, WMI_MAX_EXT2_SERVICE);
5779 wait_queue_head_t tx_credits_wq;
5780 u32 num_mem_chunks;
5781 u32 rx_decap_mode;
5782 struct wmi_host_mem_chunk mem_chunks[WMI_MAX_MEM_REQS];
5783
5784 enum wmi_host_hw_mode_config_type preferred_hw_mode;
5785 struct target_resource_config wlan_resource_config;
5786
5787 struct ath11k_targ_cap *targ_cap;
5788};
5789
5790/* Definition of HW data filtering */
5791enum hw_data_filter_type {
5792 WMI_HW_DATA_FILTER_DROP_NON_ARP_BC = BIT(0),
5793 WMI_HW_DATA_FILTER_DROP_NON_ICMPV6_MC = BIT(1),
5794};
5795
5796struct wmi_hw_data_filter_cmd {
5797 u32 tlv_header;
5798 u32 vdev_id;
5799 u32 enable;
5800 u32 hw_filter_bitmap;
5801} __packed;
5802
5803/* WOW structures */
5804enum wmi_wow_wakeup_event {
5805 WOW_BMISS_EVENT = 0,
5806 WOW_BETTER_AP_EVENT,
5807 WOW_DEAUTH_RECVD_EVENT,
5808 WOW_MAGIC_PKT_RECVD_EVENT,
5809 WOW_GTK_ERR_EVENT,
5810 WOW_FOURWAY_HSHAKE_EVENT,
5811 WOW_EAPOL_RECVD_EVENT,
5812 WOW_NLO_DETECTED_EVENT,
5813 WOW_DISASSOC_RECVD_EVENT,
5814 WOW_PATTERN_MATCH_EVENT,
5815 WOW_CSA_IE_EVENT,
5816 WOW_PROBE_REQ_WPS_IE_EVENT,
5817 WOW_AUTH_REQ_EVENT,
5818 WOW_ASSOC_REQ_EVENT,
5819 WOW_HTT_EVENT,
5820 WOW_RA_MATCH_EVENT,
5821 WOW_HOST_AUTO_SHUTDOWN_EVENT,
5822 WOW_IOAC_MAGIC_EVENT,
5823 WOW_IOAC_SHORT_EVENT,
5824 WOW_IOAC_EXTEND_EVENT,
5825 WOW_IOAC_TIMER_EVENT,
5826 WOW_DFS_PHYERR_RADAR_EVENT,
5827 WOW_BEACON_EVENT,
5828 WOW_CLIENT_KICKOUT_EVENT,
5829 WOW_EVENT_MAX,
5830};
5831
5832enum wmi_wow_interface_cfg {
5833 WOW_IFACE_PAUSE_ENABLED,
5834 WOW_IFACE_PAUSE_DISABLED
5835};
5836
5837#define C2S(x) case x: return #x
5838
5839static inline const char *wow_wakeup_event(enum wmi_wow_wakeup_event ev)
5840{
5841 switch (ev) {
5842 C2S(WOW_BMISS_EVENT);
5843 C2S(WOW_BETTER_AP_EVENT);
5844 C2S(WOW_DEAUTH_RECVD_EVENT);
5845 C2S(WOW_MAGIC_PKT_RECVD_EVENT);
5846 C2S(WOW_GTK_ERR_EVENT);
5847 C2S(WOW_FOURWAY_HSHAKE_EVENT);
5848 C2S(WOW_EAPOL_RECVD_EVENT);
5849 C2S(WOW_NLO_DETECTED_EVENT);
5850 C2S(WOW_DISASSOC_RECVD_EVENT);
5851 C2S(WOW_PATTERN_MATCH_EVENT);
5852 C2S(WOW_CSA_IE_EVENT);
5853 C2S(WOW_PROBE_REQ_WPS_IE_EVENT);
5854 C2S(WOW_AUTH_REQ_EVENT);
5855 C2S(WOW_ASSOC_REQ_EVENT);
5856 C2S(WOW_HTT_EVENT);
5857 C2S(WOW_RA_MATCH_EVENT);
5858 C2S(WOW_HOST_AUTO_SHUTDOWN_EVENT);
5859 C2S(WOW_IOAC_MAGIC_EVENT);
5860 C2S(WOW_IOAC_SHORT_EVENT);
5861 C2S(WOW_IOAC_EXTEND_EVENT);
5862 C2S(WOW_IOAC_TIMER_EVENT);
5863 C2S(WOW_DFS_PHYERR_RADAR_EVENT);
5864 C2S(WOW_BEACON_EVENT);
5865 C2S(WOW_CLIENT_KICKOUT_EVENT);
5866 C2S(WOW_EVENT_MAX);
5867 default:
5868 return NULL;
5869 }
5870}
5871
5872enum wmi_wow_wake_reason {
5873 WOW_REASON_UNSPECIFIED = -1,
5874 WOW_REASON_NLOD = 0,
5875 WOW_REASON_AP_ASSOC_LOST,
5876 WOW_REASON_LOW_RSSI,
5877 WOW_REASON_DEAUTH_RECVD,
5878 WOW_REASON_DISASSOC_RECVD,
5879 WOW_REASON_GTK_HS_ERR,
5880 WOW_REASON_EAP_REQ,
5881 WOW_REASON_FOURWAY_HS_RECV,
5882 WOW_REASON_TIMER_INTR_RECV,
5883 WOW_REASON_PATTERN_MATCH_FOUND,
5884 WOW_REASON_RECV_MAGIC_PATTERN,
5885 WOW_REASON_P2P_DISC,
5886 WOW_REASON_WLAN_HB,
5887 WOW_REASON_CSA_EVENT,
5888 WOW_REASON_PROBE_REQ_WPS_IE_RECV,
5889 WOW_REASON_AUTH_REQ_RECV,
5890 WOW_REASON_ASSOC_REQ_RECV,
5891 WOW_REASON_HTT_EVENT,
5892 WOW_REASON_RA_MATCH,
5893 WOW_REASON_HOST_AUTO_SHUTDOWN,
5894 WOW_REASON_IOAC_MAGIC_EVENT,
5895 WOW_REASON_IOAC_SHORT_EVENT,
5896 WOW_REASON_IOAC_EXTEND_EVENT,
5897 WOW_REASON_IOAC_TIMER_EVENT,
5898 WOW_REASON_ROAM_HO,
5899 WOW_REASON_DFS_PHYERR_RADADR_EVENT,
5900 WOW_REASON_BEACON_RECV,
5901 WOW_REASON_CLIENT_KICKOUT_EVENT,
5902 WOW_REASON_PAGE_FAULT = 0x3a,
5903 WOW_REASON_DEBUG_TEST = 0xFF,
5904};
5905
5906static inline const char *wow_reason(enum wmi_wow_wake_reason reason)
5907{
5908 switch (reason) {
5909 C2S(WOW_REASON_UNSPECIFIED);
5910 C2S(WOW_REASON_NLOD);
5911 C2S(WOW_REASON_AP_ASSOC_LOST);
5912 C2S(WOW_REASON_LOW_RSSI);
5913 C2S(WOW_REASON_DEAUTH_RECVD);
5914 C2S(WOW_REASON_DISASSOC_RECVD);
5915 C2S(WOW_REASON_GTK_HS_ERR);
5916 C2S(WOW_REASON_EAP_REQ);
5917 C2S(WOW_REASON_FOURWAY_HS_RECV);
5918 C2S(WOW_REASON_TIMER_INTR_RECV);
5919 C2S(WOW_REASON_PATTERN_MATCH_FOUND);
5920 C2S(WOW_REASON_RECV_MAGIC_PATTERN);
5921 C2S(WOW_REASON_P2P_DISC);
5922 C2S(WOW_REASON_WLAN_HB);
5923 C2S(WOW_REASON_CSA_EVENT);
5924 C2S(WOW_REASON_PROBE_REQ_WPS_IE_RECV);
5925 C2S(WOW_REASON_AUTH_REQ_RECV);
5926 C2S(WOW_REASON_ASSOC_REQ_RECV);
5927 C2S(WOW_REASON_HTT_EVENT);
5928 C2S(WOW_REASON_RA_MATCH);
5929 C2S(WOW_REASON_HOST_AUTO_SHUTDOWN);
5930 C2S(WOW_REASON_IOAC_MAGIC_EVENT);
5931 C2S(WOW_REASON_IOAC_SHORT_EVENT);
5932 C2S(WOW_REASON_IOAC_EXTEND_EVENT);
5933 C2S(WOW_REASON_IOAC_TIMER_EVENT);
5934 C2S(WOW_REASON_ROAM_HO);
5935 C2S(WOW_REASON_DFS_PHYERR_RADADR_EVENT);
5936 C2S(WOW_REASON_BEACON_RECV);
5937 C2S(WOW_REASON_CLIENT_KICKOUT_EVENT);
5938 C2S(WOW_REASON_PAGE_FAULT);
5939 C2S(WOW_REASON_DEBUG_TEST);
5940 default:
5941 return NULL;
5942 }
5943}
5944
5945#undef C2S
5946
5947struct wmi_wow_ev_arg {
5948 u32 vdev_id;
5949 u32 flag;
5950 enum wmi_wow_wake_reason wake_reason;
5951 u32 data_len;
5952};
5953
5954enum wmi_tlv_pattern_type {
5955 WOW_PATTERN_MIN = 0,
5956 WOW_BITMAP_PATTERN = WOW_PATTERN_MIN,
5957 WOW_IPV4_SYNC_PATTERN,
5958 WOW_IPV6_SYNC_PATTERN,
5959 WOW_WILD_CARD_PATTERN,
5960 WOW_TIMER_PATTERN,
5961 WOW_MAGIC_PATTERN,
5962 WOW_IPV6_RA_PATTERN,
5963 WOW_IOAC_PKT_PATTERN,
5964 WOW_IOAC_TMR_PATTERN,
5965 WOW_PATTERN_MAX
5966};
5967
5968#define WOW_DEFAULT_BITMAP_PATTERN_SIZE 148
5969#define WOW_DEFAULT_BITMASK_SIZE 148
5970
5971#define WOW_MIN_PATTERN_SIZE 1
5972#define WOW_MAX_PATTERN_SIZE 148
5973#define WOW_MAX_PKT_OFFSET 128
5974#define WOW_HDR_LEN (sizeof(struct ieee80211_hdr_3addr) + \
5975 sizeof(struct rfc1042_hdr))
5976#define WOW_MAX_REDUCE (WOW_HDR_LEN - sizeof(struct ethhdr) - \
5977 offsetof(struct ieee80211_hdr_3addr, addr1))
5978
5979struct wmi_wow_add_del_event_cmd {
5980 u32 tlv_header;
5981 u32 vdev_id;
5982 u32 is_add;
5983 u32 event_bitmap;
5984} __packed;
5985
5986struct wmi_wow_enable_cmd {
5987 u32 tlv_header;
5988 u32 enable;
5989 u32 pause_iface_config;
5990 u32 flags;
5991} __packed;
5992
5993struct wmi_wow_host_wakeup_ind {
5994 u32 tlv_header;
5995 u32 reserved;
5996} __packed;
5997
5998struct wmi_tlv_wow_event_info {
5999 u32 vdev_id;
6000 u32 flag;
6001 u32 wake_reason;
6002 u32 data_len;
6003} __packed;
6004
6005struct wmi_wow_bitmap_pattern {
6006 u32 tlv_header;
6007 u8 patternbuf[WOW_DEFAULT_BITMAP_PATTERN_SIZE];
6008 u8 bitmaskbuf[WOW_DEFAULT_BITMASK_SIZE];
6009 u32 pattern_offset;
6010 u32 pattern_len;
6011 u32 bitmask_len;
6012 u32 pattern_id;
6013} __packed;
6014
6015struct wmi_wow_add_pattern_cmd {
6016 u32 tlv_header;
6017 u32 vdev_id;
6018 u32 pattern_id;
6019 u32 pattern_type;
6020} __packed;
6021
6022struct wmi_wow_del_pattern_cmd {
6023 u32 tlv_header;
6024 u32 vdev_id;
6025 u32 pattern_id;
6026 u32 pattern_type;
6027} __packed;
6028
6029#define WMI_PNO_MAX_SCHED_SCAN_PLANS 2
6030#define WMI_PNO_MAX_SCHED_SCAN_PLAN_INT 7200
6031#define WMI_PNO_MAX_SCHED_SCAN_PLAN_ITRNS 100
6032#define WMI_PNO_MAX_NETW_CHANNELS 26
6033#define WMI_PNO_MAX_NETW_CHANNELS_EX 60
6034#define WMI_PNO_MAX_SUPP_NETWORKS WLAN_SCAN_PARAMS_MAX_SSID
6035#define WMI_PNO_MAX_IE_LENGTH WLAN_SCAN_PARAMS_MAX_IE_LEN
6036
6037/* size based of dot11 declaration without extra IEs as we will not carry those for PNO */
6038#define WMI_PNO_MAX_PB_REQ_SIZE 450
6039
6040#define WMI_PNO_24G_DEFAULT_CH 1
6041#define WMI_PNO_5G_DEFAULT_CH 36
6042
6043#define WMI_ACTIVE_MAX_CHANNEL_TIME 40
6044#define WMI_PASSIVE_MAX_CHANNEL_TIME 110
6045
6046/* SSID broadcast type */
6047enum wmi_ssid_bcast_type {
6048 BCAST_UNKNOWN = 0,
6049 BCAST_NORMAL = 1,
6050 BCAST_HIDDEN = 2,
6051};
6052
6053#define WMI_NLO_MAX_SSIDS 16
6054#define WMI_NLO_MAX_CHAN 48
6055
6056#define WMI_NLO_CONFIG_STOP BIT(0)
6057#define WMI_NLO_CONFIG_START BIT(1)
6058#define WMI_NLO_CONFIG_RESET BIT(2)
6059#define WMI_NLO_CONFIG_SLOW_SCAN BIT(4)
6060#define WMI_NLO_CONFIG_FAST_SCAN BIT(5)
6061#define WMI_NLO_CONFIG_SSID_HIDE_EN BIT(6)
6062
6063/* This bit is used to indicate if EPNO or supplicant PNO is enabled.
6064 * Only one of them can be enabled at a given time
6065 */
6066#define WMI_NLO_CONFIG_ENLO BIT(7)
6067#define WMI_NLO_CONFIG_SCAN_PASSIVE BIT(8)
6068#define WMI_NLO_CONFIG_ENLO_RESET BIT(9)
6069#define WMI_NLO_CONFIG_SPOOFED_MAC_IN_PROBE_REQ BIT(10)
6070#define WMI_NLO_CONFIG_RANDOM_SEQ_NO_IN_PROBE_REQ BIT(11)
6071#define WMI_NLO_CONFIG_ENABLE_IE_WHITELIST_IN_PROBE_REQ BIT(12)
6072#define WMI_NLO_CONFIG_ENABLE_CNLO_RSSI_CONFIG BIT(13)
6073
6074struct wmi_nlo_ssid_param {
6075 u32 valid;
6076 struct wmi_ssid ssid;
6077} __packed;
6078
6079struct wmi_nlo_enc_param {
6080 u32 valid;
6081 u32 enc_type;
6082} __packed;
6083
6084struct wmi_nlo_auth_param {
6085 u32 valid;
6086 u32 auth_type;
6087} __packed;
6088
6089struct wmi_nlo_bcast_nw_param {
6090 u32 valid;
6091 u32 bcast_nw_type;
6092} __packed;
6093
6094struct wmi_nlo_rssi_param {
6095 u32 valid;
6096 s32 rssi;
6097} __packed;
6098
6099struct nlo_configured_parameters {
6100 /* TLV tag and len;*/
6101 u32 tlv_header;
6102 struct wmi_nlo_ssid_param ssid;
6103 struct wmi_nlo_enc_param enc_type;
6104 struct wmi_nlo_auth_param auth_type;
6105 struct wmi_nlo_rssi_param rssi_cond;
6106
6107 /* indicates if the SSID is hidden or not */
6108 struct wmi_nlo_bcast_nw_param bcast_nw_type;
6109} __packed;
6110
6111struct wmi_network_type {
6112 struct wmi_ssid ssid;
6113 u32 authentication;
6114 u32 encryption;
6115 u32 bcast_nw_type;
6116 u8 channel_count;
6117 u16 channels[WMI_PNO_MAX_NETW_CHANNELS_EX];
6118 s32 rssi_threshold;
6119};
6120
6121struct wmi_pno_scan_req {
6122 u8 enable;
6123 u8 vdev_id;
6124 u8 uc_networks_count;
6125 struct wmi_network_type a_networks[WMI_PNO_MAX_SUPP_NETWORKS];
6126 u32 fast_scan_period;
6127 u32 slow_scan_period;
6128 u8 fast_scan_max_cycles;
6129
6130 bool do_passive_scan;
6131
6132 u32 delay_start_time;
6133 u32 active_min_time;
6134 u32 active_max_time;
6135 u32 passive_min_time;
6136 u32 passive_max_time;
6137
6138 /* mac address randomization attributes */
6139 u32 enable_pno_scan_randomization;
6140 u8 mac_addr[ETH_ALEN];
6141 u8 mac_addr_mask[ETH_ALEN];
6142};
6143
6144struct wmi_wow_nlo_config_cmd {
6145 u32 tlv_header;
6146 u32 flags;
6147 u32 vdev_id;
6148 u32 fast_scan_max_cycles;
6149 u32 active_dwell_time;
6150 u32 passive_dwell_time;
6151 u32 probe_bundle_size;
6152
6153 /* ART = IRT */
6154 u32 rest_time;
6155
6156 /* Max value that can be reached after SBM */
6157 u32 max_rest_time;
6158
6159 /* SBM */
6160 u32 scan_backoff_multiplier;
6161
6162 /* SCBM */
6163 u32 fast_scan_period;
6164
6165 /* specific to windows */
6166 u32 slow_scan_period;
6167
6168 u32 no_of_ssids;
6169
6170 u32 num_of_channels;
6171
6172 /* NLO scan start delay time in milliseconds */
6173 u32 delay_start_time;
6174
6175 /* MAC Address to use in Probe Req as SA */
6176 struct wmi_mac_addr mac_addr;
6177
6178 /* Mask on which MAC has to be randomized */
6179 struct wmi_mac_addr mac_mask;
6180
6181 /* IE bitmap to use in Probe Req */
6182 u32 ie_bitmap[8];
6183
6184 /* Number of vendor OUIs. In the TLV vendor_oui[] */
6185 u32 num_vendor_oui;
6186
6187 /* Number of connected NLO band preferences */
6188 u32 num_cnlo_band_pref;
6189
6190 /* The TLVs will follow.
6191 * nlo_configured_parameters nlo_list[];
6192 * u32 channel_list[num_of_channels];
6193 */
6194} __packed;
6195
6196#define WMI_MAX_NS_OFFLOADS 2
6197#define WMI_MAX_ARP_OFFLOADS 2
6198
6199#define WMI_ARPOL_FLAGS_VALID BIT(0)
6200#define WMI_ARPOL_FLAGS_MAC_VALID BIT(1)
6201#define WMI_ARPOL_FLAGS_REMOTE_IP_VALID BIT(2)
6202
6203struct wmi_arp_offload_tuple {
6204 u32 tlv_header;
6205 u32 flags;
6206 u8 target_ipaddr[4];
6207 u8 remote_ipaddr[4];
6208 struct wmi_mac_addr target_mac;
6209} __packed;
6210
6211#define WMI_NSOL_FLAGS_VALID BIT(0)
6212#define WMI_NSOL_FLAGS_MAC_VALID BIT(1)
6213#define WMI_NSOL_FLAGS_REMOTE_IP_VALID BIT(2)
6214#define WMI_NSOL_FLAGS_IS_IPV6_ANYCAST BIT(3)
6215
6216#define WMI_NSOL_MAX_TARGET_IPS 2
6217
6218struct wmi_ns_offload_tuple {
6219 u32 tlv_header;
6220 u32 flags;
6221 u8 target_ipaddr[WMI_NSOL_MAX_TARGET_IPS][16];
6222 u8 solicitation_ipaddr[16];
6223 u8 remote_ipaddr[16];
6224 struct wmi_mac_addr target_mac;
6225} __packed;
6226
6227struct wmi_set_arp_ns_offload_cmd {
6228 u32 tlv_header;
6229 u32 flags;
6230 u32 vdev_id;
6231 u32 num_ns_ext_tuples;
6232 /* The TLVs follow:
6233 * wmi_ns_offload_tuple ns_tuples[WMI_MAX_NS_OFFLOADS];
6234 * wmi_arp_offload_tuple arp_tuples[WMI_MAX_ARP_OFFLOADS];
6235 * wmi_ns_offload_tuple ns_ext_tuples[num_ns_ext_tuples];
6236 */
6237} __packed;
6238
6239#define GTK_OFFLOAD_OPCODE_MASK 0xFF000000
6240#define GTK_OFFLOAD_ENABLE_OPCODE 0x01000000
6241#define GTK_OFFLOAD_DISABLE_OPCODE 0x02000000
6242#define GTK_OFFLOAD_REQUEST_STATUS_OPCODE 0x04000000
6243
6244#define GTK_OFFLOAD_KEK_BYTES 16
6245#define GTK_OFFLOAD_KCK_BYTES 16
6246#define GTK_REPLAY_COUNTER_BYTES 8
6247#define WMI_MAX_KEY_LEN 32
6248#define IGTK_PN_SIZE 6
6249
6250struct wmi_replayc_cnt {
6251 union {
6252 u8 counter[GTK_REPLAY_COUNTER_BYTES];
6253 struct {
6254 u32 word0;
6255 u32 word1;
6256 } __packed;
6257 } __packed;
6258} __packed;
6259
6260struct wmi_gtk_offload_status_event {
6261 u32 vdev_id;
6262 u32 flags;
6263 u32 refresh_cnt;
6264 struct wmi_replayc_cnt replay_ctr;
6265 u8 igtk_key_index;
6266 u8 igtk_key_length;
6267 u8 igtk_key_rsc[IGTK_PN_SIZE];
6268 u8 igtk_key[WMI_MAX_KEY_LEN];
6269 u8 gtk_key_index;
6270 u8 gtk_key_length;
6271 u8 gtk_key_rsc[GTK_REPLAY_COUNTER_BYTES];
6272 u8 gtk_key[WMI_MAX_KEY_LEN];
6273} __packed;
6274
6275struct wmi_gtk_rekey_offload_cmd {
6276 u32 tlv_header;
6277 u32 vdev_id;
6278 u32 flags;
6279 u8 kek[GTK_OFFLOAD_KEK_BYTES];
6280 u8 kck[GTK_OFFLOAD_KCK_BYTES];
6281 u8 replay_ctr[GTK_REPLAY_COUNTER_BYTES];
6282} __packed;
6283
6284#define BIOS_SAR_TABLE_LEN (22)
6285#define BIOS_SAR_RSVD1_LEN (6)
6286#define BIOS_SAR_RSVD2_LEN (18)
6287
6288struct wmi_pdev_set_sar_table_cmd {
6289 u32 tlv_header;
6290 u32 pdev_id;
6291 u32 sar_len;
6292 u32 rsvd_len;
6293} __packed;
6294
6295struct wmi_pdev_set_geo_table_cmd {
6296 u32 tlv_header;
6297 u32 pdev_id;
6298 u32 rsvd_len;
6299} __packed;
6300
6301struct wmi_sta_keepalive_cmd {
6302 u32 tlv_header;
6303 u32 vdev_id;
6304 u32 enabled;
6305
6306 /* WMI_STA_KEEPALIVE_METHOD_ */
6307 u32 method;
6308
6309 /* in seconds */
6310 u32 interval;
6311
6312 /* following this structure is the TLV for struct
6313 * wmi_sta_keepalive_arp_resp
6314 */
6315} __packed;
6316
6317struct wmi_sta_keepalive_arp_resp {
6318 u32 tlv_header;
6319 u32 src_ip4_addr;
6320 u32 dest_ip4_addr;
6321 struct wmi_mac_addr dest_mac_addr;
6322} __packed;
6323
6324struct wmi_sta_keepalive_arg {
6325 u32 vdev_id;
6326 u32 enabled;
6327 u32 method;
6328 u32 interval;
6329 u32 src_ip4_addr;
6330 u32 dest_ip4_addr;
6331 const u8 dest_mac_addr[ETH_ALEN];
6332};
6333
6334enum wmi_sta_keepalive_method {
6335 WMI_STA_KEEPALIVE_METHOD_NULL_FRAME = 1,
6336 WMI_STA_KEEPALIVE_METHOD_UNSOLICITED_ARP_RESPONSE = 2,
6337 WMI_STA_KEEPALIVE_METHOD_ETHERNET_LOOPBACK = 3,
6338 WMI_STA_KEEPALIVE_METHOD_GRATUITOUS_ARP_REQUEST = 4,
6339 WMI_STA_KEEPALIVE_METHOD_MGMT_VENDOR_ACTION = 5,
6340};
6341
6342#define WMI_STA_KEEPALIVE_INTERVAL_DEFAULT 30
6343#define WMI_STA_KEEPALIVE_INTERVAL_DISABLE 0
6344
6345const void **ath11k_wmi_tlv_parse_alloc(struct ath11k_base *ab,
6346 struct sk_buff *skb, gfp_t gfp);
6347int ath11k_wmi_cmd_send(struct ath11k_pdev_wmi *wmi, struct sk_buff *skb,
6348 u32 cmd_id);
6349struct sk_buff *ath11k_wmi_alloc_skb(struct ath11k_wmi_base *wmi_sc, u32 len);
6350int ath11k_wmi_mgmt_send(struct ath11k *ar, u32 vdev_id, u32 buf_id,
6351 struct sk_buff *frame);
6352int ath11k_wmi_bcn_tmpl(struct ath11k *ar, u32 vdev_id,
6353 struct ieee80211_mutable_offsets *offs,
6354 struct sk_buff *bcn, u32 ema_param);
6355int ath11k_wmi_vdev_down(struct ath11k *ar, u8 vdev_id);
6356int ath11k_wmi_vdev_up(struct ath11k *ar, u32 vdev_id, u32 aid,
6357 const u8 *bssid, u8 *tx_bssid, u32 nontx_profile_idx,
6358 u32 nontx_profile_cnt);
6359int ath11k_wmi_vdev_stop(struct ath11k *ar, u8 vdev_id);
6360int ath11k_wmi_vdev_start(struct ath11k *ar, struct wmi_vdev_start_req_arg *arg,
6361 bool restart);
6362int ath11k_wmi_set_peer_param(struct ath11k *ar, const u8 *peer_addr,
6363 u32 vdev_id, u32 param_id, u32 param_val);
6364int ath11k_wmi_pdev_set_param(struct ath11k *ar, u32 param_id,
6365 u32 param_value, u8 pdev_id);
6366int ath11k_wmi_pdev_set_ps_mode(struct ath11k *ar, int vdev_id,
6367 enum wmi_sta_ps_mode psmode);
6368int ath11k_wmi_wait_for_unified_ready(struct ath11k_base *ab);
6369int ath11k_wmi_cmd_init(struct ath11k_base *ab);
6370int ath11k_wmi_wait_for_service_ready(struct ath11k_base *ab);
6371int ath11k_wmi_connect(struct ath11k_base *ab);
6372int ath11k_wmi_pdev_attach(struct ath11k_base *ab,
6373 u8 pdev_id);
6374int ath11k_wmi_attach(struct ath11k_base *ab);
6375void ath11k_wmi_detach(struct ath11k_base *ab);
6376int ath11k_wmi_vdev_create(struct ath11k *ar, u8 *macaddr,
6377 struct vdev_create_params *param);
6378int ath11k_wmi_peer_rx_reorder_queue_setup(struct ath11k *ar, int vdev_id,
6379 const u8 *addr, dma_addr_t paddr,
6380 u8 tid, u8 ba_window_size_valid,
6381 u32 ba_window_size);
6382int ath11k_wmi_send_peer_create_cmd(struct ath11k *ar,
6383 struct peer_create_params *param);
6384int ath11k_wmi_vdev_set_param_cmd(struct ath11k *ar, u32 vdev_id,
6385 u32 param_id, u32 param_value);
6386
6387int ath11k_wmi_set_sta_ps_param(struct ath11k *ar, u32 vdev_id,
6388 u32 param, u32 param_value);
6389int ath11k_wmi_force_fw_hang_cmd(struct ath11k *ar, u32 type, u32 delay_time_ms);
6390int ath11k_wmi_send_peer_delete_cmd(struct ath11k *ar,
6391 const u8 *peer_addr, u8 vdev_id);
6392int ath11k_wmi_vdev_delete(struct ath11k *ar, u8 vdev_id);
6393void ath11k_wmi_start_scan_init(struct ath11k *ar, struct scan_req_params *arg);
6394int ath11k_wmi_send_scan_start_cmd(struct ath11k *ar,
6395 struct scan_req_params *params);
6396int ath11k_wmi_send_scan_stop_cmd(struct ath11k *ar,
6397 struct scan_cancel_param *param);
6398int ath11k_wmi_send_wmm_update_cmd_tlv(struct ath11k *ar, u32 vdev_id,
6399 struct wmi_wmm_params_all_arg *param);
6400int ath11k_wmi_pdev_suspend(struct ath11k *ar, u32 suspend_opt,
6401 u32 pdev_id);
6402int ath11k_wmi_pdev_resume(struct ath11k *ar, u32 pdev_id);
6403
6404int ath11k_wmi_send_peer_assoc_cmd(struct ath11k *ar,
6405 struct peer_assoc_params *param);
6406int ath11k_wmi_vdev_install_key(struct ath11k *ar,
6407 struct wmi_vdev_install_key_arg *arg);
6408int ath11k_wmi_pdev_bss_chan_info_request(struct ath11k *ar,
6409 enum wmi_bss_chan_info_req_type type);
6410int ath11k_wmi_send_stats_request_cmd(struct ath11k *ar,
6411 struct stats_request_params *param);
6412int ath11k_wmi_send_pdev_temperature_cmd(struct ath11k *ar);
6413int ath11k_wmi_send_peer_flush_tids_cmd(struct ath11k *ar,
6414 u8 peer_addr[ETH_ALEN],
6415 struct peer_flush_params *param);
6416int ath11k_wmi_send_set_ap_ps_param_cmd(struct ath11k *ar, u8 *peer_addr,
6417 struct ap_ps_params *param);
6418int ath11k_wmi_send_scan_chan_list_cmd(struct ath11k *ar,
6419 struct scan_chan_list_params *chan_list);
6420int ath11k_wmi_send_dfs_phyerr_offload_enable_cmd(struct ath11k *ar,
6421 u32 pdev_id);
6422int ath11k_wmi_addba_clear_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac);
6423int ath11k_wmi_addba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac,
6424 u32 tid, u32 buf_size);
6425int ath11k_wmi_addba_set_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac,
6426 u32 tid, u32 status);
6427int ath11k_wmi_delba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac,
6428 u32 tid, u32 initiator, u32 reason);
6429int ath11k_wmi_send_bcn_offload_control_cmd(struct ath11k *ar,
6430 u32 vdev_id, u32 bcn_ctrl_op);
6431int ath11k_wmi_send_set_current_country_cmd(struct ath11k *ar,
6432 struct wmi_set_current_country_params *param);
6433int
6434ath11k_wmi_send_init_country_cmd(struct ath11k *ar,
6435 struct wmi_init_country_params init_cc_param);
6436
6437int ath11k_wmi_send_11d_scan_start_cmd(struct ath11k *ar,
6438 struct wmi_11d_scan_start_params *param);
6439int ath11k_wmi_send_11d_scan_stop_cmd(struct ath11k *ar, u32 vdev_id);
6440
6441int
6442ath11k_wmi_send_thermal_mitigation_param_cmd(struct ath11k *ar,
6443 struct thermal_mitigation_params *param);
6444int ath11k_wmi_pdev_pktlog_enable(struct ath11k *ar, u32 pktlog_filter);
6445int ath11k_wmi_pdev_pktlog_disable(struct ath11k *ar);
6446int ath11k_wmi_pdev_peer_pktlog_filter(struct ath11k *ar, u8 *addr, u8 enable);
6447int
6448ath11k_wmi_rx_reord_queue_remove(struct ath11k *ar,
6449 struct rx_reorder_queue_remove_params *param);
6450int ath11k_wmi_send_pdev_set_regdomain(struct ath11k *ar,
6451 struct pdev_set_regdomain_params *param);
6452int ath11k_wmi_pull_fw_stats(struct ath11k_base *ab, struct sk_buff *skb,
6453 struct ath11k_fw_stats *stats);
6454void ath11k_wmi_fw_stats_fill(struct ath11k *ar,
6455 struct ath11k_fw_stats *fw_stats, u32 stats_id,
6456 char *buf);
6457int ath11k_wmi_simulate_radar(struct ath11k *ar);
6458void ath11k_wmi_fill_default_twt_params(struct wmi_twt_enable_params *twt_params);
6459int ath11k_wmi_send_twt_enable_cmd(struct ath11k *ar, u32 pdev_id,
6460 struct wmi_twt_enable_params *params);
6461int ath11k_wmi_send_twt_disable_cmd(struct ath11k *ar, u32 pdev_id);
6462int ath11k_wmi_send_twt_add_dialog_cmd(struct ath11k *ar,
6463 struct wmi_twt_add_dialog_params *params);
6464int ath11k_wmi_send_twt_del_dialog_cmd(struct ath11k *ar,
6465 struct wmi_twt_del_dialog_params *params);
6466int ath11k_wmi_send_twt_pause_dialog_cmd(struct ath11k *ar,
6467 struct wmi_twt_pause_dialog_params *params);
6468int ath11k_wmi_send_twt_resume_dialog_cmd(struct ath11k *ar,
6469 struct wmi_twt_resume_dialog_params *params);
6470int ath11k_wmi_send_obss_spr_cmd(struct ath11k *ar, u32 vdev_id,
6471 struct ieee80211_he_obss_pd *he_obss_pd);
6472int ath11k_wmi_pdev_set_srg_bss_color_bitmap(struct ath11k *ar, u32 *bitmap);
6473int ath11k_wmi_pdev_set_srg_patial_bssid_bitmap(struct ath11k *ar, u32 *bitmap);
6474int ath11k_wmi_pdev_srg_obss_color_enable_bitmap(struct ath11k *ar,
6475 u32 *bitmap);
6476int ath11k_wmi_pdev_srg_obss_bssid_enable_bitmap(struct ath11k *ar,
6477 u32 *bitmap);
6478int ath11k_wmi_pdev_non_srg_obss_color_enable_bitmap(struct ath11k *ar,
6479 u32 *bitmap);
6480int ath11k_wmi_pdev_non_srg_obss_bssid_enable_bitmap(struct ath11k *ar,
6481 u32 *bitmap);
6482int ath11k_wmi_send_obss_color_collision_cfg_cmd(struct ath11k *ar, u32 vdev_id,
6483 u8 bss_color, u32 period,
6484 bool enable);
6485int ath11k_wmi_send_bss_color_change_enable_cmd(struct ath11k *ar, u32 vdev_id,
6486 bool enable);
6487int ath11k_wmi_pdev_lro_cfg(struct ath11k *ar, int pdev_id);
6488int ath11k_wmi_pdev_dma_ring_cfg(struct ath11k *ar,
6489 struct ath11k_wmi_pdev_dma_ring_cfg_req_cmd *param);
6490int ath11k_wmi_vdev_spectral_enable(struct ath11k *ar, u32 vdev_id,
6491 u32 trigger, u32 enable);
6492int ath11k_wmi_vdev_spectral_conf(struct ath11k *ar,
6493 struct ath11k_wmi_vdev_spectral_conf_param *param);
6494int ath11k_wmi_fils_discovery_tmpl(struct ath11k *ar, u32 vdev_id,
6495 struct sk_buff *tmpl);
6496int ath11k_wmi_fils_discovery(struct ath11k *ar, u32 vdev_id, u32 interval,
6497 bool unsol_bcast_probe_resp_enabled);
6498int ath11k_wmi_probe_resp_tmpl(struct ath11k *ar, u32 vdev_id,
6499 struct sk_buff *tmpl);
6500int ath11k_wmi_set_hw_mode(struct ath11k_base *ab,
6501 enum wmi_host_hw_mode_config_type mode);
6502int ath11k_wmi_wow_host_wakeup_ind(struct ath11k *ar);
6503int ath11k_wmi_wow_enable(struct ath11k *ar);
6504int ath11k_wmi_scan_prob_req_oui(struct ath11k *ar,
6505 const u8 mac_addr[ETH_ALEN]);
6506int ath11k_wmi_fw_dbglog_cfg(struct ath11k *ar, u32 *module_id_bitmap,
6507 struct ath11k_fw_dbglog *dbglog);
6508int ath11k_wmi_wow_config_pno(struct ath11k *ar, u32 vdev_id,
6509 struct wmi_pno_scan_req *pno_scan);
6510int ath11k_wmi_wow_del_pattern(struct ath11k *ar, u32 vdev_id, u32 pattern_id);
6511int ath11k_wmi_wow_add_pattern(struct ath11k *ar, u32 vdev_id, u32 pattern_id,
6512 const u8 *pattern, const u8 *mask,
6513 int pattern_len, int pattern_offset);
6514int ath11k_wmi_wow_add_wakeup_event(struct ath11k *ar, u32 vdev_id,
6515 enum wmi_wow_wakeup_event event,
6516 u32 enable);
6517int ath11k_wmi_hw_data_filter_cmd(struct ath11k *ar, u32 vdev_id,
6518 u32 filter_bitmap, bool enable);
6519int ath11k_wmi_arp_ns_offload(struct ath11k *ar,
6520 struct ath11k_vif *arvif, bool enable);
6521int ath11k_wmi_gtk_rekey_offload(struct ath11k *ar,
6522 struct ath11k_vif *arvif, bool enable);
6523int ath11k_wmi_gtk_rekey_getinfo(struct ath11k *ar,
6524 struct ath11k_vif *arvif);
6525int ath11k_wmi_pdev_set_bios_sar_table_param(struct ath11k *ar, const u8 *sar_val);
6526int ath11k_wmi_pdev_set_bios_geo_table_param(struct ath11k *ar);
6527int ath11k_wmi_sta_keepalive(struct ath11k *ar,
6528 const struct wmi_sta_keepalive_arg *arg);
6529bool ath11k_wmi_supports_6ghz_cc_ext(struct ath11k *ar);
6530int ath11k_wmi_send_vdev_set_tpc_power(struct ath11k *ar,
6531 u32 vdev_id,
6532 struct ath11k_reg_tpc_power_info *param);
6533
6534#endif