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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Renesas RZ/G2L WDT Watchdog Driver
4 *
5 * Copyright (C) 2021 Renesas Electronics Corporation
6 */
7#include <linux/bitops.h>
8#include <linux/clk.h>
9#include <linux/delay.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/reset.h>
18#include <linux/units.h>
19#include <linux/watchdog.h>
20
21#define WDTCNT 0x00
22#define WDTSET 0x04
23#define WDTTIM 0x08
24#define WDTINT 0x0C
25#define PECR 0x10
26#define PEEN 0x14
27#define WDTCNT_WDTEN BIT(0)
28#define WDTINT_INTDISP BIT(0)
29#define PEEN_FORCE BIT(0)
30
31#define WDT_DEFAULT_TIMEOUT 60U
32
33/* Setting period time register only 12 bit set in WDTSET[31:20] */
34#define WDTSET_COUNTER_MASK (0xFFF00000)
35#define WDTSET_COUNTER_VAL(f) ((f) << 20)
36
37#define F2CYCLE_NSEC(f) (1000000000 / (f))
38
39#define RZV2M_A_NSEC 730
40
41static bool nowayout = WATCHDOG_NOWAYOUT;
42module_param(nowayout, bool, 0);
43MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
44 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
45
46enum rz_wdt_type {
47 WDT_RZG2L,
48 WDT_RZV2M,
49};
50
51struct rzg2l_wdt_priv {
52 void __iomem *base;
53 struct watchdog_device wdev;
54 struct reset_control *rstc;
55 unsigned long osc_clk_rate;
56 unsigned long delay;
57 unsigned long minimum_assertion_period;
58 struct clk *pclk;
59 struct clk *osc_clk;
60 enum rz_wdt_type devtype;
61};
62
63static int rzg2l_wdt_reset(struct rzg2l_wdt_priv *priv)
64{
65 int err, status;
66
67 if (priv->devtype == WDT_RZV2M) {
68 /* WDT needs TYPE-B reset control */
69 err = reset_control_assert(priv->rstc);
70 if (err)
71 return err;
72 ndelay(priv->minimum_assertion_period);
73 err = reset_control_deassert(priv->rstc);
74 if (err)
75 return err;
76 err = read_poll_timeout(reset_control_status, status,
77 status != 1, 0, 1000, false,
78 priv->rstc);
79 } else {
80 err = reset_control_reset(priv->rstc);
81 }
82
83 return err;
84}
85
86static void rzg2l_wdt_wait_delay(struct rzg2l_wdt_priv *priv)
87{
88 /* delay timer when change the setting register */
89 ndelay(priv->delay);
90}
91
92static u32 rzg2l_wdt_get_cycle_usec(unsigned long cycle, u32 wdttime)
93{
94 u64 timer_cycle_us = 1024 * 1024ULL * (wdttime + 1) * MICRO;
95
96 return div64_ul(timer_cycle_us, cycle);
97}
98
99static void rzg2l_wdt_write(struct rzg2l_wdt_priv *priv, u32 val, unsigned int reg)
100{
101 if (reg == WDTSET)
102 val &= WDTSET_COUNTER_MASK;
103
104 writel_relaxed(val, priv->base + reg);
105 /* Registers other than the WDTINT is always synchronized with WDT_CLK */
106 if (reg != WDTINT)
107 rzg2l_wdt_wait_delay(priv);
108}
109
110static void rzg2l_wdt_init_timeout(struct watchdog_device *wdev)
111{
112 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
113 u32 time_out;
114
115 /* Clear Lapsed Time Register and clear Interrupt */
116 rzg2l_wdt_write(priv, WDTINT_INTDISP, WDTINT);
117 /* 2 consecutive overflow cycle needed to trigger reset */
118 time_out = (wdev->timeout * (MICRO / 2)) /
119 rzg2l_wdt_get_cycle_usec(priv->osc_clk_rate, 0);
120 rzg2l_wdt_write(priv, WDTSET_COUNTER_VAL(time_out), WDTSET);
121}
122
123static int rzg2l_wdt_start(struct watchdog_device *wdev)
124{
125 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
126
127 pm_runtime_get_sync(wdev->parent);
128
129 /* Initialize time out */
130 rzg2l_wdt_init_timeout(wdev);
131
132 /* Initialize watchdog counter register */
133 rzg2l_wdt_write(priv, 0, WDTTIM);
134
135 /* Enable watchdog timer*/
136 rzg2l_wdt_write(priv, WDTCNT_WDTEN, WDTCNT);
137
138 return 0;
139}
140
141static int rzg2l_wdt_stop(struct watchdog_device *wdev)
142{
143 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
144
145 rzg2l_wdt_reset(priv);
146 pm_runtime_put(wdev->parent);
147
148 return 0;
149}
150
151static int rzg2l_wdt_set_timeout(struct watchdog_device *wdev, unsigned int timeout)
152{
153 wdev->timeout = timeout;
154
155 /*
156 * If the watchdog is active, reset the module for updating the WDTSET
157 * register by calling rzg2l_wdt_stop() (which internally calls reset_control_reset()
158 * to reset the module) so that it is updated with new timeout values.
159 */
160 if (watchdog_active(wdev)) {
161 rzg2l_wdt_stop(wdev);
162 rzg2l_wdt_start(wdev);
163 }
164
165 return 0;
166}
167
168static int rzg2l_wdt_restart(struct watchdog_device *wdev,
169 unsigned long action, void *data)
170{
171 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
172
173 clk_prepare_enable(priv->pclk);
174 clk_prepare_enable(priv->osc_clk);
175
176 if (priv->devtype == WDT_RZG2L) {
177 /* Generate Reset (WDTRSTB) Signal on parity error */
178 rzg2l_wdt_write(priv, 0, PECR);
179
180 /* Force parity error */
181 rzg2l_wdt_write(priv, PEEN_FORCE, PEEN);
182 } else {
183 /* RZ/V2M doesn't have parity error registers */
184 rzg2l_wdt_reset(priv);
185
186 wdev->timeout = 0;
187
188 /* Initialize time out */
189 rzg2l_wdt_init_timeout(wdev);
190
191 /* Initialize watchdog counter register */
192 rzg2l_wdt_write(priv, 0, WDTTIM);
193
194 /* Enable watchdog timer*/
195 rzg2l_wdt_write(priv, WDTCNT_WDTEN, WDTCNT);
196
197 /* Wait 2 consecutive overflow cycles for reset */
198 mdelay(DIV_ROUND_UP(2 * 0xFFFFF * 1000, priv->osc_clk_rate));
199 }
200
201 return 0;
202}
203
204static const struct watchdog_info rzg2l_wdt_ident = {
205 .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
206 .identity = "Renesas RZ/G2L WDT Watchdog",
207};
208
209static int rzg2l_wdt_ping(struct watchdog_device *wdev)
210{
211 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
212
213 rzg2l_wdt_write(priv, WDTINT_INTDISP, WDTINT);
214
215 return 0;
216}
217
218static const struct watchdog_ops rzg2l_wdt_ops = {
219 .owner = THIS_MODULE,
220 .start = rzg2l_wdt_start,
221 .stop = rzg2l_wdt_stop,
222 .ping = rzg2l_wdt_ping,
223 .set_timeout = rzg2l_wdt_set_timeout,
224 .restart = rzg2l_wdt_restart,
225};
226
227static void rzg2l_wdt_reset_assert_pm_disable(void *data)
228{
229 struct watchdog_device *wdev = data;
230 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
231
232 pm_runtime_disable(wdev->parent);
233 reset_control_assert(priv->rstc);
234}
235
236static int rzg2l_wdt_probe(struct platform_device *pdev)
237{
238 struct device *dev = &pdev->dev;
239 struct rzg2l_wdt_priv *priv;
240 unsigned long pclk_rate;
241 int ret;
242
243 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
244 if (!priv)
245 return -ENOMEM;
246
247 priv->base = devm_platform_ioremap_resource(pdev, 0);
248 if (IS_ERR(priv->base))
249 return PTR_ERR(priv->base);
250
251 /* Get watchdog main clock */
252 priv->osc_clk = devm_clk_get(&pdev->dev, "oscclk");
253 if (IS_ERR(priv->osc_clk))
254 return dev_err_probe(&pdev->dev, PTR_ERR(priv->osc_clk), "no oscclk");
255
256 priv->osc_clk_rate = clk_get_rate(priv->osc_clk);
257 if (!priv->osc_clk_rate)
258 return dev_err_probe(&pdev->dev, -EINVAL, "oscclk rate is 0");
259
260 /* Get Peripheral clock */
261 priv->pclk = devm_clk_get(&pdev->dev, "pclk");
262 if (IS_ERR(priv->pclk))
263 return dev_err_probe(&pdev->dev, PTR_ERR(priv->pclk), "no pclk");
264
265 pclk_rate = clk_get_rate(priv->pclk);
266 if (!pclk_rate)
267 return dev_err_probe(&pdev->dev, -EINVAL, "pclk rate is 0");
268
269 priv->delay = F2CYCLE_NSEC(priv->osc_clk_rate) * 6 + F2CYCLE_NSEC(pclk_rate) * 9;
270
271 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
272 if (IS_ERR(priv->rstc))
273 return dev_err_probe(&pdev->dev, PTR_ERR(priv->rstc),
274 "failed to get cpg reset");
275
276 ret = reset_control_deassert(priv->rstc);
277 if (ret)
278 return dev_err_probe(dev, ret, "failed to deassert");
279
280 priv->devtype = (uintptr_t)of_device_get_match_data(dev);
281
282 if (priv->devtype == WDT_RZV2M) {
283 priv->minimum_assertion_period = RZV2M_A_NSEC +
284 3 * F2CYCLE_NSEC(pclk_rate) + 5 *
285 max(F2CYCLE_NSEC(priv->osc_clk_rate),
286 F2CYCLE_NSEC(pclk_rate));
287 }
288
289 pm_runtime_enable(&pdev->dev);
290
291 priv->wdev.info = &rzg2l_wdt_ident;
292 priv->wdev.ops = &rzg2l_wdt_ops;
293 priv->wdev.parent = dev;
294 priv->wdev.min_timeout = 1;
295 priv->wdev.max_timeout = rzg2l_wdt_get_cycle_usec(priv->osc_clk_rate, 0xfff) /
296 USEC_PER_SEC;
297 priv->wdev.timeout = WDT_DEFAULT_TIMEOUT;
298
299 watchdog_set_drvdata(&priv->wdev, priv);
300 ret = devm_add_action_or_reset(&pdev->dev,
301 rzg2l_wdt_reset_assert_pm_disable,
302 &priv->wdev);
303 if (ret < 0)
304 return ret;
305
306 watchdog_set_nowayout(&priv->wdev, nowayout);
307 watchdog_stop_on_unregister(&priv->wdev);
308
309 ret = watchdog_init_timeout(&priv->wdev, 0, dev);
310 if (ret)
311 dev_warn(dev, "Specified timeout invalid, using default");
312
313 return devm_watchdog_register_device(&pdev->dev, &priv->wdev);
314}
315
316static const struct of_device_id rzg2l_wdt_ids[] = {
317 { .compatible = "renesas,rzg2l-wdt", .data = (void *)WDT_RZG2L },
318 { .compatible = "renesas,rzv2m-wdt", .data = (void *)WDT_RZV2M },
319 { /* sentinel */ }
320};
321MODULE_DEVICE_TABLE(of, rzg2l_wdt_ids);
322
323static struct platform_driver rzg2l_wdt_driver = {
324 .driver = {
325 .name = "rzg2l_wdt",
326 .of_match_table = rzg2l_wdt_ids,
327 },
328 .probe = rzg2l_wdt_probe,
329};
330module_platform_driver(rzg2l_wdt_driver);
331
332MODULE_DESCRIPTION("Renesas RZ/G2L WDT Watchdog Driver");
333MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
334MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Renesas RZ/G2L WDT Watchdog Driver
4 *
5 * Copyright (C) 2021 Renesas Electronics Corporation
6 */
7#include <linux/bitops.h>
8#include <linux/clk.h>
9#include <linux/delay.h>
10#include <linux/io.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/of_device.h>
14#include <linux/platform_device.h>
15#include <linux/pm_runtime.h>
16#include <linux/reset.h>
17#include <linux/units.h>
18#include <linux/watchdog.h>
19
20#define WDTCNT 0x00
21#define WDTSET 0x04
22#define WDTTIM 0x08
23#define WDTINT 0x0C
24#define PECR 0x10
25#define PEEN 0x14
26#define WDTCNT_WDTEN BIT(0)
27#define WDTINT_INTDISP BIT(0)
28#define PEEN_FORCE BIT(0)
29
30#define WDT_DEFAULT_TIMEOUT 60U
31
32/* Setting period time register only 12 bit set in WDTSET[31:20] */
33#define WDTSET_COUNTER_MASK (0xFFF00000)
34#define WDTSET_COUNTER_VAL(f) ((f) << 20)
35
36#define F2CYCLE_NSEC(f) (1000000000 / (f))
37
38static bool nowayout = WATCHDOG_NOWAYOUT;
39module_param(nowayout, bool, 0);
40MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
41 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
42
43enum rz_wdt_type {
44 WDT_RZG2L,
45 WDT_RZV2M,
46};
47
48struct rzg2l_wdt_priv {
49 void __iomem *base;
50 struct watchdog_device wdev;
51 struct reset_control *rstc;
52 unsigned long osc_clk_rate;
53 unsigned long delay;
54 struct clk *pclk;
55 struct clk *osc_clk;
56 enum rz_wdt_type devtype;
57};
58
59static void rzg2l_wdt_wait_delay(struct rzg2l_wdt_priv *priv)
60{
61 /* delay timer when change the setting register */
62 ndelay(priv->delay);
63}
64
65static u32 rzg2l_wdt_get_cycle_usec(unsigned long cycle, u32 wdttime)
66{
67 u64 timer_cycle_us = 1024 * 1024ULL * (wdttime + 1) * MICRO;
68
69 return div64_ul(timer_cycle_us, cycle);
70}
71
72static void rzg2l_wdt_write(struct rzg2l_wdt_priv *priv, u32 val, unsigned int reg)
73{
74 if (reg == WDTSET)
75 val &= WDTSET_COUNTER_MASK;
76
77 writel_relaxed(val, priv->base + reg);
78 /* Registers other than the WDTINT is always synchronized with WDT_CLK */
79 if (reg != WDTINT)
80 rzg2l_wdt_wait_delay(priv);
81}
82
83static void rzg2l_wdt_init_timeout(struct watchdog_device *wdev)
84{
85 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
86 u32 time_out;
87
88 /* Clear Lapsed Time Register and clear Interrupt */
89 rzg2l_wdt_write(priv, WDTINT_INTDISP, WDTINT);
90 /* 2 consecutive overflow cycle needed to trigger reset */
91 time_out = (wdev->timeout * (MICRO / 2)) /
92 rzg2l_wdt_get_cycle_usec(priv->osc_clk_rate, 0);
93 rzg2l_wdt_write(priv, WDTSET_COUNTER_VAL(time_out), WDTSET);
94}
95
96static int rzg2l_wdt_start(struct watchdog_device *wdev)
97{
98 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
99
100 pm_runtime_get_sync(wdev->parent);
101
102 /* Initialize time out */
103 rzg2l_wdt_init_timeout(wdev);
104
105 /* Initialize watchdog counter register */
106 rzg2l_wdt_write(priv, 0, WDTTIM);
107
108 /* Enable watchdog timer*/
109 rzg2l_wdt_write(priv, WDTCNT_WDTEN, WDTCNT);
110
111 return 0;
112}
113
114static int rzg2l_wdt_stop(struct watchdog_device *wdev)
115{
116 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
117
118 pm_runtime_put(wdev->parent);
119 reset_control_reset(priv->rstc);
120
121 return 0;
122}
123
124static int rzg2l_wdt_set_timeout(struct watchdog_device *wdev, unsigned int timeout)
125{
126 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
127
128 wdev->timeout = timeout;
129
130 /*
131 * If the watchdog is active, reset the module for updating the WDTSET
132 * register so that it is updated with new timeout values.
133 */
134 if (watchdog_active(wdev)) {
135 pm_runtime_put(wdev->parent);
136 reset_control_reset(priv->rstc);
137 rzg2l_wdt_start(wdev);
138 }
139
140 return 0;
141}
142
143static int rzg2l_wdt_restart(struct watchdog_device *wdev,
144 unsigned long action, void *data)
145{
146 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
147
148 clk_prepare_enable(priv->pclk);
149 clk_prepare_enable(priv->osc_clk);
150
151 if (priv->devtype == WDT_RZG2L) {
152 /* Generate Reset (WDTRSTB) Signal on parity error */
153 rzg2l_wdt_write(priv, 0, PECR);
154
155 /* Force parity error */
156 rzg2l_wdt_write(priv, PEEN_FORCE, PEEN);
157 } else {
158 /* RZ/V2M doesn't have parity error registers */
159
160 wdev->timeout = 0;
161
162 /* Initialize time out */
163 rzg2l_wdt_init_timeout(wdev);
164
165 /* Initialize watchdog counter register */
166 rzg2l_wdt_write(priv, 0, WDTTIM);
167
168 /* Enable watchdog timer*/
169 rzg2l_wdt_write(priv, WDTCNT_WDTEN, WDTCNT);
170
171 /* Wait 2 consecutive overflow cycles for reset */
172 mdelay(DIV_ROUND_UP(2 * 0xFFFFF * 1000, priv->osc_clk_rate));
173 }
174
175 return 0;
176}
177
178static const struct watchdog_info rzg2l_wdt_ident = {
179 .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
180 .identity = "Renesas RZ/G2L WDT Watchdog",
181};
182
183static int rzg2l_wdt_ping(struct watchdog_device *wdev)
184{
185 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
186
187 rzg2l_wdt_write(priv, WDTINT_INTDISP, WDTINT);
188
189 return 0;
190}
191
192static const struct watchdog_ops rzg2l_wdt_ops = {
193 .owner = THIS_MODULE,
194 .start = rzg2l_wdt_start,
195 .stop = rzg2l_wdt_stop,
196 .ping = rzg2l_wdt_ping,
197 .set_timeout = rzg2l_wdt_set_timeout,
198 .restart = rzg2l_wdt_restart,
199};
200
201static void rzg2l_wdt_reset_assert_pm_disable(void *data)
202{
203 struct watchdog_device *wdev = data;
204 struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
205
206 pm_runtime_disable(wdev->parent);
207 reset_control_assert(priv->rstc);
208}
209
210static int rzg2l_wdt_probe(struct platform_device *pdev)
211{
212 struct device *dev = &pdev->dev;
213 struct rzg2l_wdt_priv *priv;
214 unsigned long pclk_rate;
215 int ret;
216
217 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
218 if (!priv)
219 return -ENOMEM;
220
221 priv->base = devm_platform_ioremap_resource(pdev, 0);
222 if (IS_ERR(priv->base))
223 return PTR_ERR(priv->base);
224
225 /* Get watchdog main clock */
226 priv->osc_clk = devm_clk_get(&pdev->dev, "oscclk");
227 if (IS_ERR(priv->osc_clk))
228 return dev_err_probe(&pdev->dev, PTR_ERR(priv->osc_clk), "no oscclk");
229
230 priv->osc_clk_rate = clk_get_rate(priv->osc_clk);
231 if (!priv->osc_clk_rate)
232 return dev_err_probe(&pdev->dev, -EINVAL, "oscclk rate is 0");
233
234 /* Get Peripheral clock */
235 priv->pclk = devm_clk_get(&pdev->dev, "pclk");
236 if (IS_ERR(priv->pclk))
237 return dev_err_probe(&pdev->dev, PTR_ERR(priv->pclk), "no pclk");
238
239 pclk_rate = clk_get_rate(priv->pclk);
240 if (!pclk_rate)
241 return dev_err_probe(&pdev->dev, -EINVAL, "pclk rate is 0");
242
243 priv->delay = F2CYCLE_NSEC(priv->osc_clk_rate) * 6 + F2CYCLE_NSEC(pclk_rate) * 9;
244
245 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
246 if (IS_ERR(priv->rstc))
247 return dev_err_probe(&pdev->dev, PTR_ERR(priv->rstc),
248 "failed to get cpg reset");
249
250 ret = reset_control_deassert(priv->rstc);
251 if (ret)
252 return dev_err_probe(dev, ret, "failed to deassert");
253
254 priv->devtype = (uintptr_t)of_device_get_match_data(dev);
255
256 pm_runtime_enable(&pdev->dev);
257
258 priv->wdev.info = &rzg2l_wdt_ident;
259 priv->wdev.ops = &rzg2l_wdt_ops;
260 priv->wdev.parent = dev;
261 priv->wdev.min_timeout = 1;
262 priv->wdev.max_timeout = rzg2l_wdt_get_cycle_usec(priv->osc_clk_rate, 0xfff) /
263 USEC_PER_SEC;
264 priv->wdev.timeout = WDT_DEFAULT_TIMEOUT;
265
266 watchdog_set_drvdata(&priv->wdev, priv);
267 ret = devm_add_action_or_reset(&pdev->dev,
268 rzg2l_wdt_reset_assert_pm_disable,
269 &priv->wdev);
270 if (ret < 0)
271 return ret;
272
273 watchdog_set_nowayout(&priv->wdev, nowayout);
274 watchdog_stop_on_unregister(&priv->wdev);
275
276 ret = watchdog_init_timeout(&priv->wdev, 0, dev);
277 if (ret)
278 dev_warn(dev, "Specified timeout invalid, using default");
279
280 return devm_watchdog_register_device(&pdev->dev, &priv->wdev);
281}
282
283static const struct of_device_id rzg2l_wdt_ids[] = {
284 { .compatible = "renesas,rzg2l-wdt", .data = (void *)WDT_RZG2L },
285 { .compatible = "renesas,rzv2m-wdt", .data = (void *)WDT_RZV2M },
286 { /* sentinel */ }
287};
288MODULE_DEVICE_TABLE(of, rzg2l_wdt_ids);
289
290static struct platform_driver rzg2l_wdt_driver = {
291 .driver = {
292 .name = "rzg2l_wdt",
293 .of_match_table = rzg2l_wdt_ids,
294 },
295 .probe = rzg2l_wdt_probe,
296};
297module_platform_driver(rzg2l_wdt_driver);
298
299MODULE_DESCRIPTION("Renesas RZ/G2L WDT Watchdog Driver");
300MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
301MODULE_LICENSE("GPL v2");