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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * xHCI host controller driver
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11/*
12 * Ring initialization rules:
13 * 1. Each segment is initialized to zero, except for link TRBs.
14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
15 * Consumer Cycle State (CCS), depending on ring function.
16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
17 *
18 * Ring behavior rules:
19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
20 * least one free TRB in the ring. This is useful if you want to turn that
21 * into a link TRB and expand the ring.
22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
23 * link TRB, then load the pointer with the address in the link TRB. If the
24 * link TRB had its toggle bit set, you may need to update the ring cycle
25 * state (see cycle bit rules). You may have to do this multiple times
26 * until you reach a non-link TRB.
27 * 3. A ring is full if enqueue++ (for the definition of increment above)
28 * equals the dequeue pointer.
29 *
30 * Cycle bit rules:
31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
32 * in a link TRB, it must toggle the ring cycle state.
33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
34 * in a link TRB, it must toggle the ring cycle state.
35 *
36 * Producer rules:
37 * 1. Check if ring is full before you enqueue.
38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
39 * Update enqueue pointer between each write (which may update the ring
40 * cycle state).
41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
42 * and endpoint rings. If HC is the producer for the event ring,
43 * and it generates an interrupt according to interrupt modulation rules.
44 *
45 * Consumer rules:
46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
47 * the TRB is owned by the consumer.
48 * 2. Update dequeue pointer (which may update the ring cycle state) and
49 * continue processing TRBs until you reach a TRB which is not owned by you.
50 * 3. Notify the producer. SW is the consumer for the event ring, and it
51 * updates event ring dequeue pointer. HC is the consumer for the command and
52 * endpoint rings; it generates events on the event ring for these.
53 */
54
55#include <linux/scatterlist.h>
56#include <linux/slab.h>
57#include <linux/dma-mapping.h>
58#include "xhci.h"
59#include "xhci-trace.h"
60
61static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
62 u32 field1, u32 field2,
63 u32 field3, u32 field4, bool command_must_succeed);
64
65/*
66 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
67 * address of the TRB.
68 */
69dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
70 union xhci_trb *trb)
71{
72 unsigned long segment_offset;
73
74 if (!seg || !trb || trb < seg->trbs)
75 return 0;
76 /* offset in TRBs */
77 segment_offset = trb - seg->trbs;
78 if (segment_offset >= TRBS_PER_SEGMENT)
79 return 0;
80 return seg->dma + (segment_offset * sizeof(*trb));
81}
82
83static bool trb_is_noop(union xhci_trb *trb)
84{
85 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
86}
87
88static bool trb_is_link(union xhci_trb *trb)
89{
90 return TRB_TYPE_LINK_LE32(trb->link.control);
91}
92
93static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
94{
95 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
96}
97
98static bool last_trb_on_ring(struct xhci_ring *ring,
99 struct xhci_segment *seg, union xhci_trb *trb)
100{
101 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
102}
103
104static bool link_trb_toggles_cycle(union xhci_trb *trb)
105{
106 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
107}
108
109static bool last_td_in_urb(struct xhci_td *td)
110{
111 struct urb_priv *urb_priv = td->urb->hcpriv;
112
113 return urb_priv->num_tds_done == urb_priv->num_tds;
114}
115
116static void inc_td_cnt(struct urb *urb)
117{
118 struct urb_priv *urb_priv = urb->hcpriv;
119
120 urb_priv->num_tds_done++;
121}
122
123static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
124{
125 if (trb_is_link(trb)) {
126 /* unchain chained link TRBs */
127 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
128 } else {
129 trb->generic.field[0] = 0;
130 trb->generic.field[1] = 0;
131 trb->generic.field[2] = 0;
132 /* Preserve only the cycle bit of this TRB */
133 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
134 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
135 }
136}
137
138/* Updates trb to point to the next TRB in the ring, and updates seg if the next
139 * TRB is in a new segment. This does not skip over link TRBs, and it does not
140 * effect the ring dequeue or enqueue pointers.
141 */
142static void next_trb(struct xhci_hcd *xhci,
143 struct xhci_ring *ring,
144 struct xhci_segment **seg,
145 union xhci_trb **trb)
146{
147 if (trb_is_link(*trb) || last_trb_on_seg(*seg, *trb)) {
148 *seg = (*seg)->next;
149 *trb = ((*seg)->trbs);
150 } else {
151 (*trb)++;
152 }
153}
154
155/*
156 * See Cycle bit rules. SW is the consumer for the event ring only.
157 */
158void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
159{
160 unsigned int link_trb_count = 0;
161
162 /* event ring doesn't have link trbs, check for last trb */
163 if (ring->type == TYPE_EVENT) {
164 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
165 ring->dequeue++;
166 goto out;
167 }
168 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
169 ring->cycle_state ^= 1;
170 ring->deq_seg = ring->deq_seg->next;
171 ring->dequeue = ring->deq_seg->trbs;
172 goto out;
173 }
174
175 /* All other rings have link trbs */
176 if (!trb_is_link(ring->dequeue)) {
177 if (last_trb_on_seg(ring->deq_seg, ring->dequeue))
178 xhci_warn(xhci, "Missing link TRB at end of segment\n");
179 else
180 ring->dequeue++;
181 }
182
183 while (trb_is_link(ring->dequeue)) {
184 ring->deq_seg = ring->deq_seg->next;
185 ring->dequeue = ring->deq_seg->trbs;
186
187 if (link_trb_count++ > ring->num_segs) {
188 xhci_warn(xhci, "Ring is an endless link TRB loop\n");
189 break;
190 }
191 }
192out:
193 trace_xhci_inc_deq(ring);
194
195 return;
196}
197
198/*
199 * See Cycle bit rules. SW is the consumer for the event ring only.
200 *
201 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
202 * chain bit is set), then set the chain bit in all the following link TRBs.
203 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
204 * have their chain bit cleared (so that each Link TRB is a separate TD).
205 *
206 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
207 * set, but other sections talk about dealing with the chain bit set. This was
208 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
209 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
210 *
211 * @more_trbs_coming: Will you enqueue more TRBs before calling
212 * prepare_transfer()?
213 */
214static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
215 bool more_trbs_coming)
216{
217 u32 chain;
218 union xhci_trb *next;
219 unsigned int link_trb_count = 0;
220
221 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
222
223 if (last_trb_on_seg(ring->enq_seg, ring->enqueue)) {
224 xhci_err(xhci, "Tried to move enqueue past ring segment\n");
225 return;
226 }
227
228 next = ++(ring->enqueue);
229
230 /* Update the dequeue pointer further if that was a link TRB */
231 while (trb_is_link(next)) {
232
233 /*
234 * If the caller doesn't plan on enqueueing more TDs before
235 * ringing the doorbell, then we don't want to give the link TRB
236 * to the hardware just yet. We'll give the link TRB back in
237 * prepare_ring() just before we enqueue the TD at the top of
238 * the ring.
239 */
240 if (!chain && !more_trbs_coming)
241 break;
242
243 /* If we're not dealing with 0.95 hardware or isoc rings on
244 * AMD 0.96 host, carry over the chain bit of the previous TRB
245 * (which may mean the chain bit is cleared).
246 */
247 if (!(ring->type == TYPE_ISOC &&
248 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
249 !xhci_link_trb_quirk(xhci)) {
250 next->link.control &= cpu_to_le32(~TRB_CHAIN);
251 next->link.control |= cpu_to_le32(chain);
252 }
253 /* Give this link TRB to the hardware */
254 wmb();
255 next->link.control ^= cpu_to_le32(TRB_CYCLE);
256
257 /* Toggle the cycle bit after the last ring segment. */
258 if (link_trb_toggles_cycle(next))
259 ring->cycle_state ^= 1;
260
261 ring->enq_seg = ring->enq_seg->next;
262 ring->enqueue = ring->enq_seg->trbs;
263 next = ring->enqueue;
264
265 if (link_trb_count++ > ring->num_segs) {
266 xhci_warn(xhci, "%s: Ring link TRB loop\n", __func__);
267 break;
268 }
269 }
270
271 trace_xhci_inc_enq(ring);
272}
273
274/*
275 * Return number of free normal TRBs from enqueue to dequeue pointer on ring.
276 * Not counting an assumed link TRB at end of each TRBS_PER_SEGMENT sized segment.
277 * Only for transfer and command rings where driver is the producer, not for
278 * event rings.
279 */
280static unsigned int xhci_num_trbs_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
281{
282 struct xhci_segment *enq_seg = ring->enq_seg;
283 union xhci_trb *enq = ring->enqueue;
284 union xhci_trb *last_on_seg;
285 unsigned int free = 0;
286 int i = 0;
287
288 /* Ring might be empty even if enq != deq if enq is left on a link trb */
289 if (trb_is_link(enq)) {
290 enq_seg = enq_seg->next;
291 enq = enq_seg->trbs;
292 }
293
294 /* Empty ring, common case, don't walk the segments */
295 if (enq == ring->dequeue)
296 return ring->num_segs * (TRBS_PER_SEGMENT - 1);
297
298 do {
299 if (ring->deq_seg == enq_seg && ring->dequeue >= enq)
300 return free + (ring->dequeue - enq);
301 last_on_seg = &enq_seg->trbs[TRBS_PER_SEGMENT - 1];
302 free += last_on_seg - enq;
303 enq_seg = enq_seg->next;
304 enq = enq_seg->trbs;
305 } while (i++ <= ring->num_segs);
306
307 return free;
308}
309
310/*
311 * Check to see if there's room to enqueue num_trbs on the ring and make sure
312 * enqueue pointer will not advance into dequeue segment. See rules above.
313 * return number of new segments needed to ensure this.
314 */
315
316static unsigned int xhci_ring_expansion_needed(struct xhci_hcd *xhci, struct xhci_ring *ring,
317 unsigned int num_trbs)
318{
319 struct xhci_segment *seg;
320 int trbs_past_seg;
321 int enq_used;
322 int new_segs;
323
324 enq_used = ring->enqueue - ring->enq_seg->trbs;
325
326 /* how many trbs will be queued past the enqueue segment? */
327 trbs_past_seg = enq_used + num_trbs - (TRBS_PER_SEGMENT - 1);
328
329 /*
330 * Consider expanding the ring already if num_trbs fills the current
331 * segment (i.e. trbs_past_seg == 0), not only when num_trbs goes into
332 * the next segment. Avoids confusing full ring with special empty ring
333 * case below
334 */
335 if (trbs_past_seg < 0)
336 return 0;
337
338 /* Empty ring special case, enqueue stuck on link trb while dequeue advanced */
339 if (trb_is_link(ring->enqueue) && ring->enq_seg->next->trbs == ring->dequeue)
340 return 0;
341
342 new_segs = 1 + (trbs_past_seg / (TRBS_PER_SEGMENT - 1));
343 seg = ring->enq_seg;
344
345 while (new_segs > 0) {
346 seg = seg->next;
347 if (seg == ring->deq_seg) {
348 xhci_dbg(xhci, "Ring expansion by %d segments needed\n",
349 new_segs);
350 xhci_dbg(xhci, "Adding %d trbs moves enq %d trbs into deq seg\n",
351 num_trbs, trbs_past_seg % TRBS_PER_SEGMENT);
352 return new_segs;
353 }
354 new_segs--;
355 }
356
357 return 0;
358}
359
360/* Ring the host controller doorbell after placing a command on the ring */
361void xhci_ring_cmd_db(struct xhci_hcd *xhci)
362{
363 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
364 return;
365
366 xhci_dbg(xhci, "// Ding dong!\n");
367
368 trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST);
369
370 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
371 /* Flush PCI posted writes */
372 readl(&xhci->dba->doorbell[0]);
373}
374
375static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci)
376{
377 return mod_delayed_work(system_wq, &xhci->cmd_timer,
378 msecs_to_jiffies(xhci->current_cmd->timeout_ms));
379}
380
381static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
382{
383 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
384 cmd_list);
385}
386
387/*
388 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
389 * If there are other commands waiting then restart the ring and kick the timer.
390 * This must be called with command ring stopped and xhci->lock held.
391 */
392static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
393 struct xhci_command *cur_cmd)
394{
395 struct xhci_command *i_cmd;
396
397 /* Turn all aborted commands in list to no-ops, then restart */
398 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
399
400 if (i_cmd->status != COMP_COMMAND_ABORTED)
401 continue;
402
403 i_cmd->status = COMP_COMMAND_RING_STOPPED;
404
405 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
406 i_cmd->command_trb);
407
408 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
409
410 /*
411 * caller waiting for completion is called when command
412 * completion event is received for these no-op commands
413 */
414 }
415
416 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
417
418 /* ring command ring doorbell to restart the command ring */
419 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
420 !(xhci->xhc_state & XHCI_STATE_DYING)) {
421 xhci->current_cmd = cur_cmd;
422 xhci_mod_cmd_timer(xhci);
423 xhci_ring_cmd_db(xhci);
424 }
425}
426
427/* Must be called with xhci->lock held, releases and aquires lock back */
428static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
429{
430 struct xhci_segment *new_seg = xhci->cmd_ring->deq_seg;
431 union xhci_trb *new_deq = xhci->cmd_ring->dequeue;
432 u64 crcr;
433 int ret;
434
435 xhci_dbg(xhci, "Abort command ring\n");
436
437 reinit_completion(&xhci->cmd_ring_stop_completion);
438
439 /*
440 * The control bits like command stop, abort are located in lower
441 * dword of the command ring control register.
442 * Some controllers require all 64 bits to be written to abort the ring.
443 * Make sure the upper dword is valid, pointing to the next command,
444 * avoiding corrupting the command ring pointer in case the command ring
445 * is stopped by the time the upper dword is written.
446 */
447 next_trb(xhci, NULL, &new_seg, &new_deq);
448 if (trb_is_link(new_deq))
449 next_trb(xhci, NULL, &new_seg, &new_deq);
450
451 crcr = xhci_trb_virt_to_dma(new_seg, new_deq);
452 xhci_write_64(xhci, crcr | CMD_RING_ABORT, &xhci->op_regs->cmd_ring);
453
454 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
455 * completion of the Command Abort operation. If CRR is not negated in 5
456 * seconds then driver handles it as if host died (-ENODEV).
457 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
458 * and try to recover a -ETIMEDOUT with a host controller reset.
459 */
460 ret = xhci_handshake_check_state(xhci, &xhci->op_regs->cmd_ring,
461 CMD_RING_RUNNING, 0, 5 * 1000 * 1000,
462 XHCI_STATE_REMOVING);
463 if (ret < 0) {
464 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
465 xhci_halt(xhci);
466 xhci_hc_died(xhci);
467 return ret;
468 }
469 /*
470 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
471 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
472 * but the completion event in never sent. Wait 2 secs (arbitrary
473 * number) to handle those cases after negation of CMD_RING_RUNNING.
474 */
475 spin_unlock_irqrestore(&xhci->lock, flags);
476 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
477 msecs_to_jiffies(2000));
478 spin_lock_irqsave(&xhci->lock, flags);
479 if (!ret) {
480 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
481 xhci_cleanup_command_queue(xhci);
482 } else {
483 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
484 }
485 return 0;
486}
487
488void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
489 unsigned int slot_id,
490 unsigned int ep_index,
491 unsigned int stream_id)
492{
493 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
494 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
495 unsigned int ep_state = ep->ep_state;
496
497 /* Don't ring the doorbell for this endpoint if there are pending
498 * cancellations because we don't want to interrupt processing.
499 * We don't want to restart any stream rings if there's a set dequeue
500 * pointer command pending because the device can choose to start any
501 * stream once the endpoint is on the HW schedule.
502 */
503 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
504 (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT))
505 return;
506
507 trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id));
508
509 writel(DB_VALUE(ep_index, stream_id), db_addr);
510 /* flush the write */
511 readl(db_addr);
512}
513
514/* Ring the doorbell for any rings with pending URBs */
515static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
516 unsigned int slot_id,
517 unsigned int ep_index)
518{
519 unsigned int stream_id;
520 struct xhci_virt_ep *ep;
521
522 ep = &xhci->devs[slot_id]->eps[ep_index];
523
524 /* A ring has pending URBs if its TD list is not empty */
525 if (!(ep->ep_state & EP_HAS_STREAMS)) {
526 if (ep->ring && !(list_empty(&ep->ring->td_list)))
527 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
528 return;
529 }
530
531 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
532 stream_id++) {
533 struct xhci_stream_info *stream_info = ep->stream_info;
534 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
535 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
536 stream_id);
537 }
538}
539
540void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
541 unsigned int slot_id,
542 unsigned int ep_index)
543{
544 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
545}
546
547static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci,
548 unsigned int slot_id,
549 unsigned int ep_index)
550{
551 if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) {
552 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
553 return NULL;
554 }
555 if (ep_index >= EP_CTX_PER_DEV) {
556 xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index);
557 return NULL;
558 }
559 if (!xhci->devs[slot_id]) {
560 xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id);
561 return NULL;
562 }
563
564 return &xhci->devs[slot_id]->eps[ep_index];
565}
566
567static struct xhci_ring *xhci_virt_ep_to_ring(struct xhci_hcd *xhci,
568 struct xhci_virt_ep *ep,
569 unsigned int stream_id)
570{
571 /* common case, no streams */
572 if (!(ep->ep_state & EP_HAS_STREAMS))
573 return ep->ring;
574
575 if (!ep->stream_info)
576 return NULL;
577
578 if (stream_id == 0 || stream_id >= ep->stream_info->num_streams) {
579 xhci_warn(xhci, "Invalid stream_id %u request for slot_id %u ep_index %u\n",
580 stream_id, ep->vdev->slot_id, ep->ep_index);
581 return NULL;
582 }
583
584 return ep->stream_info->stream_rings[stream_id];
585}
586
587/* Get the right ring for the given slot_id, ep_index and stream_id.
588 * If the endpoint supports streams, boundary check the URB's stream ID.
589 * If the endpoint doesn't support streams, return the singular endpoint ring.
590 */
591struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
592 unsigned int slot_id, unsigned int ep_index,
593 unsigned int stream_id)
594{
595 struct xhci_virt_ep *ep;
596
597 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
598 if (!ep)
599 return NULL;
600
601 return xhci_virt_ep_to_ring(xhci, ep, stream_id);
602}
603
604
605/*
606 * Get the hw dequeue pointer xHC stopped on, either directly from the
607 * endpoint context, or if streams are in use from the stream context.
608 * The returned hw_dequeue contains the lowest four bits with cycle state
609 * and possbile stream context type.
610 */
611static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
612 unsigned int ep_index, unsigned int stream_id)
613{
614 struct xhci_ep_ctx *ep_ctx;
615 struct xhci_stream_ctx *st_ctx;
616 struct xhci_virt_ep *ep;
617
618 ep = &vdev->eps[ep_index];
619
620 if (ep->ep_state & EP_HAS_STREAMS) {
621 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
622 return le64_to_cpu(st_ctx->stream_ring);
623 }
624 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
625 return le64_to_cpu(ep_ctx->deq);
626}
627
628static int xhci_move_dequeue_past_td(struct xhci_hcd *xhci,
629 unsigned int slot_id, unsigned int ep_index,
630 unsigned int stream_id, struct xhci_td *td)
631{
632 struct xhci_virt_device *dev = xhci->devs[slot_id];
633 struct xhci_virt_ep *ep = &dev->eps[ep_index];
634 struct xhci_ring *ep_ring;
635 struct xhci_command *cmd;
636 struct xhci_segment *new_seg;
637 union xhci_trb *new_deq;
638 int new_cycle;
639 dma_addr_t addr;
640 u64 hw_dequeue;
641 bool cycle_found = false;
642 bool td_last_trb_found = false;
643 u32 trb_sct = 0;
644 int ret;
645
646 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
647 ep_index, stream_id);
648 if (!ep_ring) {
649 xhci_warn(xhci, "WARN can't find new dequeue, invalid stream ID %u\n",
650 stream_id);
651 return -ENODEV;
652 }
653 /*
654 * A cancelled TD can complete with a stall if HW cached the trb.
655 * In this case driver can't find td, but if the ring is empty we
656 * can move the dequeue pointer to the current enqueue position.
657 * We shouldn't hit this anymore as cached cancelled TRBs are given back
658 * after clearing the cache, but be on the safe side and keep it anyway
659 */
660 if (!td) {
661 if (list_empty(&ep_ring->td_list)) {
662 new_seg = ep_ring->enq_seg;
663 new_deq = ep_ring->enqueue;
664 new_cycle = ep_ring->cycle_state;
665 xhci_dbg(xhci, "ep ring empty, Set new dequeue = enqueue");
666 goto deq_found;
667 } else {
668 xhci_warn(xhci, "Can't find new dequeue state, missing td\n");
669 return -EINVAL;
670 }
671 }
672
673 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
674 new_seg = ep_ring->deq_seg;
675 new_deq = ep_ring->dequeue;
676 new_cycle = hw_dequeue & 0x1;
677
678 /*
679 * We want to find the pointer, segment and cycle state of the new trb
680 * (the one after current TD's last_trb). We know the cycle state at
681 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
682 * found.
683 */
684 do {
685 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
686 == (dma_addr_t)(hw_dequeue & ~0xf)) {
687 cycle_found = true;
688 if (td_last_trb_found)
689 break;
690 }
691 if (new_deq == td->last_trb)
692 td_last_trb_found = true;
693
694 if (cycle_found && trb_is_link(new_deq) &&
695 link_trb_toggles_cycle(new_deq))
696 new_cycle ^= 0x1;
697
698 next_trb(xhci, ep_ring, &new_seg, &new_deq);
699
700 /* Search wrapped around, bail out */
701 if (new_deq == ep->ring->dequeue) {
702 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
703 return -EINVAL;
704 }
705
706 } while (!cycle_found || !td_last_trb_found);
707
708deq_found:
709
710 /* Don't update the ring cycle state for the producer (us). */
711 addr = xhci_trb_virt_to_dma(new_seg, new_deq);
712 if (addr == 0) {
713 xhci_warn(xhci, "Can't find dma of new dequeue ptr\n");
714 xhci_warn(xhci, "deq seg = %p, deq ptr = %p\n", new_seg, new_deq);
715 return -EINVAL;
716 }
717
718 if ((ep->ep_state & SET_DEQ_PENDING)) {
719 xhci_warn(xhci, "Set TR Deq already pending, don't submit for 0x%pad\n",
720 &addr);
721 return -EBUSY;
722 }
723
724 /* This function gets called from contexts where it cannot sleep */
725 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
726 if (!cmd) {
727 xhci_warn(xhci, "Can't alloc Set TR Deq cmd 0x%pad\n", &addr);
728 return -ENOMEM;
729 }
730
731 if (stream_id)
732 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
733 ret = queue_command(xhci, cmd,
734 lower_32_bits(addr) | trb_sct | new_cycle,
735 upper_32_bits(addr),
736 STREAM_ID_FOR_TRB(stream_id), SLOT_ID_FOR_TRB(slot_id) |
737 EP_ID_FOR_TRB(ep_index) | TRB_TYPE(TRB_SET_DEQ), false);
738 if (ret < 0) {
739 xhci_free_command(xhci, cmd);
740 return ret;
741 }
742 ep->queued_deq_seg = new_seg;
743 ep->queued_deq_ptr = new_deq;
744
745 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
746 "Set TR Deq ptr 0x%llx, cycle %u\n", addr, new_cycle);
747
748 /* Stop the TD queueing code from ringing the doorbell until
749 * this command completes. The HC won't set the dequeue pointer
750 * if the ring is running, and ringing the doorbell starts the
751 * ring running.
752 */
753 ep->ep_state |= SET_DEQ_PENDING;
754 xhci_ring_cmd_db(xhci);
755 return 0;
756}
757
758/* flip_cycle means flip the cycle bit of all but the first and last TRB.
759 * (The last TRB actually points to the ring enqueue pointer, which is not part
760 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
761 */
762static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
763 struct xhci_td *td, bool flip_cycle)
764{
765 struct xhci_segment *seg = td->start_seg;
766 union xhci_trb *trb = td->first_trb;
767
768 while (1) {
769 trb_to_noop(trb, TRB_TR_NOOP);
770
771 /* flip cycle if asked to */
772 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
773 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
774
775 if (trb == td->last_trb)
776 break;
777
778 next_trb(xhci, ep_ring, &seg, &trb);
779 }
780}
781
782/*
783 * Must be called with xhci->lock held in interrupt context,
784 * releases and re-acquires xhci->lock
785 */
786static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
787 struct xhci_td *cur_td, int status)
788{
789 struct urb *urb = cur_td->urb;
790 struct urb_priv *urb_priv = urb->hcpriv;
791 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
792
793 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
794 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
795 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
796 if (xhci->quirks & XHCI_AMD_PLL_FIX)
797 usb_amd_quirk_pll_enable();
798 }
799 }
800 xhci_urb_free_priv(urb_priv);
801 usb_hcd_unlink_urb_from_ep(hcd, urb);
802 trace_xhci_urb_giveback(urb);
803 usb_hcd_giveback_urb(hcd, urb, status);
804}
805
806static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
807 struct xhci_ring *ring, struct xhci_td *td)
808{
809 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
810 struct xhci_segment *seg = td->bounce_seg;
811 struct urb *urb = td->urb;
812 size_t len;
813
814 if (!ring || !seg || !urb)
815 return;
816
817 if (usb_urb_dir_out(urb)) {
818 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
819 DMA_TO_DEVICE);
820 return;
821 }
822
823 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
824 DMA_FROM_DEVICE);
825 /* for in tranfers we need to copy the data from bounce to sg */
826 if (urb->num_sgs) {
827 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
828 seg->bounce_len, seg->bounce_offs);
829 if (len != seg->bounce_len)
830 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
831 len, seg->bounce_len);
832 } else {
833 memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf,
834 seg->bounce_len);
835 }
836 seg->bounce_len = 0;
837 seg->bounce_offs = 0;
838}
839
840static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
841 struct xhci_ring *ep_ring, int status)
842{
843 struct urb *urb = NULL;
844
845 /* Clean up the endpoint's TD list */
846 urb = td->urb;
847
848 /* if a bounce buffer was used to align this td then unmap it */
849 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
850
851 /* Do one last check of the actual transfer length.
852 * If the host controller said we transferred more data than the buffer
853 * length, urb->actual_length will be a very big number (since it's
854 * unsigned). Play it safe and say we didn't transfer anything.
855 */
856 if (urb->actual_length > urb->transfer_buffer_length) {
857 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
858 urb->transfer_buffer_length, urb->actual_length);
859 urb->actual_length = 0;
860 status = 0;
861 }
862 /* TD might be removed from td_list if we are giving back a cancelled URB */
863 if (!list_empty(&td->td_list))
864 list_del_init(&td->td_list);
865 /* Giving back a cancelled URB, or if a slated TD completed anyway */
866 if (!list_empty(&td->cancelled_td_list))
867 list_del_init(&td->cancelled_td_list);
868
869 inc_td_cnt(urb);
870 /* Giveback the urb when all the tds are completed */
871 if (last_td_in_urb(td)) {
872 if ((urb->actual_length != urb->transfer_buffer_length &&
873 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
874 (status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
875 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
876 urb, urb->actual_length,
877 urb->transfer_buffer_length, status);
878
879 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
880 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
881 status = 0;
882 xhci_giveback_urb_in_irq(xhci, td, status);
883 }
884
885 return 0;
886}
887
888
889/* Complete the cancelled URBs we unlinked from td_list. */
890static void xhci_giveback_invalidated_tds(struct xhci_virt_ep *ep)
891{
892 struct xhci_ring *ring;
893 struct xhci_td *td, *tmp_td;
894
895 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
896 cancelled_td_list) {
897
898 ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
899
900 if (td->cancel_status == TD_CLEARED) {
901 xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n",
902 __func__, td->urb);
903 xhci_td_cleanup(ep->xhci, td, ring, td->status);
904 } else {
905 xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
906 __func__, td->urb, td->cancel_status);
907 }
908 if (ep->xhci->xhc_state & XHCI_STATE_DYING)
909 return;
910 }
911}
912
913static int xhci_reset_halted_ep(struct xhci_hcd *xhci, unsigned int slot_id,
914 unsigned int ep_index, enum xhci_ep_reset_type reset_type)
915{
916 struct xhci_command *command;
917 int ret = 0;
918
919 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
920 if (!command) {
921 ret = -ENOMEM;
922 goto done;
923 }
924
925 xhci_dbg(xhci, "%s-reset ep %u, slot %u\n",
926 (reset_type == EP_HARD_RESET) ? "Hard" : "Soft",
927 ep_index, slot_id);
928
929 ret = xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
930done:
931 if (ret)
932 xhci_err(xhci, "ERROR queuing reset endpoint for slot %d ep_index %d, %d\n",
933 slot_id, ep_index, ret);
934 return ret;
935}
936
937static int xhci_handle_halted_endpoint(struct xhci_hcd *xhci,
938 struct xhci_virt_ep *ep,
939 struct xhci_td *td,
940 enum xhci_ep_reset_type reset_type)
941{
942 unsigned int slot_id = ep->vdev->slot_id;
943 int err;
944
945 /*
946 * Avoid resetting endpoint if link is inactive. Can cause host hang.
947 * Device will be reset soon to recover the link so don't do anything
948 */
949 if (ep->vdev->flags & VDEV_PORT_ERROR)
950 return -ENODEV;
951
952 /* add td to cancelled list and let reset ep handler take care of it */
953 if (reset_type == EP_HARD_RESET) {
954 ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
955 if (td && list_empty(&td->cancelled_td_list)) {
956 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
957 td->cancel_status = TD_HALTED;
958 }
959 }
960
961 if (ep->ep_state & EP_HALTED) {
962 xhci_dbg(xhci, "Reset ep command for ep_index %d already pending\n",
963 ep->ep_index);
964 return 0;
965 }
966
967 err = xhci_reset_halted_ep(xhci, slot_id, ep->ep_index, reset_type);
968 if (err)
969 return err;
970
971 ep->ep_state |= EP_HALTED;
972
973 xhci_ring_cmd_db(xhci);
974
975 return 0;
976}
977
978/*
979 * Fix up the ep ring first, so HW stops executing cancelled TDs.
980 * We have the xHCI lock, so nothing can modify this list until we drop it.
981 * We're also in the event handler, so we can't get re-interrupted if another
982 * Stop Endpoint command completes.
983 *
984 * only call this when ring is not in a running state
985 */
986
987static int xhci_invalidate_cancelled_tds(struct xhci_virt_ep *ep)
988{
989 struct xhci_hcd *xhci;
990 struct xhci_td *td = NULL;
991 struct xhci_td *tmp_td = NULL;
992 struct xhci_td *cached_td = NULL;
993 struct xhci_ring *ring;
994 u64 hw_deq;
995 unsigned int slot_id = ep->vdev->slot_id;
996 int err;
997
998 xhci = ep->xhci;
999
1000 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
1001 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1002 "Removing canceled TD starting at 0x%llx (dma) in stream %u URB %p",
1003 (unsigned long long)xhci_trb_virt_to_dma(
1004 td->start_seg, td->first_trb),
1005 td->urb->stream_id, td->urb);
1006 list_del_init(&td->td_list);
1007 ring = xhci_urb_to_transfer_ring(xhci, td->urb);
1008 if (!ring) {
1009 xhci_warn(xhci, "WARN Cancelled URB %p has invalid stream ID %u.\n",
1010 td->urb, td->urb->stream_id);
1011 continue;
1012 }
1013 /*
1014 * If a ring stopped on the TD we need to cancel then we have to
1015 * move the xHC endpoint ring dequeue pointer past this TD.
1016 * Rings halted due to STALL may show hw_deq is past the stalled
1017 * TD, but still require a set TR Deq command to flush xHC cache.
1018 */
1019 hw_deq = xhci_get_hw_deq(xhci, ep->vdev, ep->ep_index,
1020 td->urb->stream_id);
1021 hw_deq &= ~0xf;
1022
1023 if (td->cancel_status == TD_HALTED ||
1024 trb_in_td(xhci, td->start_seg, td->first_trb, td->last_trb, hw_deq, false)) {
1025 switch (td->cancel_status) {
1026 case TD_CLEARED: /* TD is already no-op */
1027 case TD_CLEARING_CACHE: /* set TR deq command already queued */
1028 break;
1029 case TD_DIRTY: /* TD is cached, clear it */
1030 case TD_HALTED:
1031 td->cancel_status = TD_CLEARING_CACHE;
1032 if (cached_td)
1033 /* FIXME stream case, several stopped rings */
1034 xhci_dbg(xhci,
1035 "Move dq past stream %u URB %p instead of stream %u URB %p\n",
1036 td->urb->stream_id, td->urb,
1037 cached_td->urb->stream_id, cached_td->urb);
1038 cached_td = td;
1039 break;
1040 }
1041 } else {
1042 td_to_noop(xhci, ring, td, false);
1043 td->cancel_status = TD_CLEARED;
1044 }
1045 }
1046
1047 /* If there's no need to move the dequeue pointer then we're done */
1048 if (!cached_td)
1049 return 0;
1050
1051 err = xhci_move_dequeue_past_td(xhci, slot_id, ep->ep_index,
1052 cached_td->urb->stream_id,
1053 cached_td);
1054 if (err) {
1055 /* Failed to move past cached td, just set cached TDs to no-op */
1056 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
1057 if (td->cancel_status != TD_CLEARING_CACHE)
1058 continue;
1059 xhci_dbg(xhci, "Failed to clear cancelled cached URB %p, mark clear anyway\n",
1060 td->urb);
1061 td_to_noop(xhci, ring, td, false);
1062 td->cancel_status = TD_CLEARED;
1063 }
1064 }
1065 return 0;
1066}
1067
1068/*
1069 * Returns the TD the endpoint ring halted on.
1070 * Only call for non-running rings without streams.
1071 */
1072static struct xhci_td *find_halted_td(struct xhci_virt_ep *ep)
1073{
1074 struct xhci_td *td;
1075 u64 hw_deq;
1076
1077 if (!list_empty(&ep->ring->td_list)) { /* Not streams compatible */
1078 hw_deq = xhci_get_hw_deq(ep->xhci, ep->vdev, ep->ep_index, 0);
1079 hw_deq &= ~0xf;
1080 td = list_first_entry(&ep->ring->td_list, struct xhci_td, td_list);
1081 if (trb_in_td(ep->xhci, td->start_seg, td->first_trb,
1082 td->last_trb, hw_deq, false))
1083 return td;
1084 }
1085 return NULL;
1086}
1087
1088/*
1089 * When we get a command completion for a Stop Endpoint Command, we need to
1090 * unlink any cancelled TDs from the ring. There are two ways to do that:
1091 *
1092 * 1. If the HW was in the middle of processing the TD that needs to be
1093 * cancelled, then we must move the ring's dequeue pointer past the last TRB
1094 * in the TD with a Set Dequeue Pointer Command.
1095 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
1096 * bit cleared) so that the HW will skip over them.
1097 */
1098static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
1099 union xhci_trb *trb, u32 comp_code)
1100{
1101 unsigned int ep_index;
1102 struct xhci_virt_ep *ep;
1103 struct xhci_ep_ctx *ep_ctx;
1104 struct xhci_td *td = NULL;
1105 enum xhci_ep_reset_type reset_type;
1106 struct xhci_command *command;
1107 int err;
1108
1109 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
1110 if (!xhci->devs[slot_id])
1111 xhci_warn(xhci, "Stop endpoint command completion for disabled slot %u\n",
1112 slot_id);
1113 return;
1114 }
1115
1116 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1117 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1118 if (!ep)
1119 return;
1120
1121 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1122
1123 trace_xhci_handle_cmd_stop_ep(ep_ctx);
1124
1125 if (comp_code == COMP_CONTEXT_STATE_ERROR) {
1126 /*
1127 * If stop endpoint command raced with a halting endpoint we need to
1128 * reset the host side endpoint first.
1129 * If the TD we halted on isn't cancelled the TD should be given back
1130 * with a proper error code, and the ring dequeue moved past the TD.
1131 * If streams case we can't find hw_deq, or the TD we halted on so do a
1132 * soft reset.
1133 *
1134 * Proper error code is unknown here, it would be -EPIPE if device side
1135 * of enadpoit halted (aka STALL), and -EPROTO if not (transaction error)
1136 * We use -EPROTO, if device is stalled it should return a stall error on
1137 * next transfer, which then will return -EPIPE, and device side stall is
1138 * noted and cleared by class driver.
1139 */
1140 switch (GET_EP_CTX_STATE(ep_ctx)) {
1141 case EP_STATE_HALTED:
1142 xhci_dbg(xhci, "Stop ep completion raced with stall, reset ep\n");
1143 if (ep->ep_state & EP_HAS_STREAMS) {
1144 reset_type = EP_SOFT_RESET;
1145 } else {
1146 reset_type = EP_HARD_RESET;
1147 td = find_halted_td(ep);
1148 if (td)
1149 td->status = -EPROTO;
1150 }
1151 /* reset ep, reset handler cleans up cancelled tds */
1152 err = xhci_handle_halted_endpoint(xhci, ep, td, reset_type);
1153 if (err)
1154 break;
1155 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1156 return;
1157 case EP_STATE_RUNNING:
1158 /* Race, HW handled stop ep cmd before ep was running */
1159 xhci_dbg(xhci, "Stop ep completion ctx error, ep is running\n");
1160
1161 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1162 if (!command) {
1163 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1164 return;
1165 }
1166 xhci_queue_stop_endpoint(xhci, command, slot_id, ep_index, 0);
1167 xhci_ring_cmd_db(xhci);
1168
1169 return;
1170 default:
1171 break;
1172 }
1173 }
1174
1175 /* will queue a set TR deq if stopped on a cancelled, uncleared TD */
1176 xhci_invalidate_cancelled_tds(ep);
1177 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1178
1179 /* Otherwise ring the doorbell(s) to restart queued transfers */
1180 xhci_giveback_invalidated_tds(ep);
1181 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1182}
1183
1184static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
1185{
1186 struct xhci_td *cur_td;
1187 struct xhci_td *tmp;
1188
1189 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
1190 list_del_init(&cur_td->td_list);
1191
1192 if (!list_empty(&cur_td->cancelled_td_list))
1193 list_del_init(&cur_td->cancelled_td_list);
1194
1195 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
1196
1197 inc_td_cnt(cur_td->urb);
1198 if (last_td_in_urb(cur_td))
1199 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1200 }
1201}
1202
1203static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
1204 int slot_id, int ep_index)
1205{
1206 struct xhci_td *cur_td;
1207 struct xhci_td *tmp;
1208 struct xhci_virt_ep *ep;
1209 struct xhci_ring *ring;
1210
1211 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1212 if (!ep)
1213 return;
1214
1215 if ((ep->ep_state & EP_HAS_STREAMS) ||
1216 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
1217 int stream_id;
1218
1219 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
1220 stream_id++) {
1221 ring = ep->stream_info->stream_rings[stream_id];
1222 if (!ring)
1223 continue;
1224
1225 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1226 "Killing URBs for slot ID %u, ep index %u, stream %u",
1227 slot_id, ep_index, stream_id);
1228 xhci_kill_ring_urbs(xhci, ring);
1229 }
1230 } else {
1231 ring = ep->ring;
1232 if (!ring)
1233 return;
1234 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1235 "Killing URBs for slot ID %u, ep index %u",
1236 slot_id, ep_index);
1237 xhci_kill_ring_urbs(xhci, ring);
1238 }
1239
1240 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
1241 cancelled_td_list) {
1242 list_del_init(&cur_td->cancelled_td_list);
1243 inc_td_cnt(cur_td->urb);
1244
1245 if (last_td_in_urb(cur_td))
1246 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1247 }
1248}
1249
1250/*
1251 * host controller died, register read returns 0xffffffff
1252 * Complete pending commands, mark them ABORTED.
1253 * URBs need to be given back as usb core might be waiting with device locks
1254 * held for the URBs to finish during device disconnect, blocking host remove.
1255 *
1256 * Call with xhci->lock held.
1257 * lock is relased and re-acquired while giving back urb.
1258 */
1259void xhci_hc_died(struct xhci_hcd *xhci)
1260{
1261 int i, j;
1262
1263 if (xhci->xhc_state & XHCI_STATE_DYING)
1264 return;
1265
1266 xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
1267 xhci->xhc_state |= XHCI_STATE_DYING;
1268
1269 xhci_cleanup_command_queue(xhci);
1270
1271 /* return any pending urbs, remove may be waiting for them */
1272 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
1273 if (!xhci->devs[i])
1274 continue;
1275 for (j = 0; j < 31; j++)
1276 xhci_kill_endpoint_urbs(xhci, i, j);
1277 }
1278
1279 /* inform usb core hc died if PCI remove isn't already handling it */
1280 if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
1281 usb_hc_died(xhci_to_hcd(xhci));
1282}
1283
1284static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1285 struct xhci_virt_device *dev,
1286 struct xhci_ring *ep_ring,
1287 unsigned int ep_index)
1288{
1289 union xhci_trb *dequeue_temp;
1290
1291 dequeue_temp = ep_ring->dequeue;
1292
1293 /* If we get two back-to-back stalls, and the first stalled transfer
1294 * ends just before a link TRB, the dequeue pointer will be left on
1295 * the link TRB by the code in the while loop. So we have to update
1296 * the dequeue pointer one segment further, or we'll jump off
1297 * the segment into la-la-land.
1298 */
1299 if (trb_is_link(ep_ring->dequeue)) {
1300 ep_ring->deq_seg = ep_ring->deq_seg->next;
1301 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1302 }
1303
1304 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1305 /* We have more usable TRBs */
1306 ep_ring->dequeue++;
1307 if (trb_is_link(ep_ring->dequeue)) {
1308 if (ep_ring->dequeue ==
1309 dev->eps[ep_index].queued_deq_ptr)
1310 break;
1311 ep_ring->deq_seg = ep_ring->deq_seg->next;
1312 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1313 }
1314 if (ep_ring->dequeue == dequeue_temp) {
1315 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1316 break;
1317 }
1318 }
1319}
1320
1321/*
1322 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1323 * we need to clear the set deq pending flag in the endpoint ring state, so that
1324 * the TD queueing code can ring the doorbell again. We also need to ring the
1325 * endpoint doorbell to restart the ring, but only if there aren't more
1326 * cancellations pending.
1327 */
1328static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1329 union xhci_trb *trb, u32 cmd_comp_code)
1330{
1331 unsigned int ep_index;
1332 unsigned int stream_id;
1333 struct xhci_ring *ep_ring;
1334 struct xhci_virt_ep *ep;
1335 struct xhci_ep_ctx *ep_ctx;
1336 struct xhci_slot_ctx *slot_ctx;
1337 struct xhci_td *td, *tmp_td;
1338
1339 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1340 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1341 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1342 if (!ep)
1343 return;
1344
1345 ep_ring = xhci_virt_ep_to_ring(xhci, ep, stream_id);
1346 if (!ep_ring) {
1347 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1348 stream_id);
1349 /* XXX: Harmless??? */
1350 goto cleanup;
1351 }
1352
1353 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1354 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
1355 trace_xhci_handle_cmd_set_deq(slot_ctx);
1356 trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1357
1358 if (cmd_comp_code != COMP_SUCCESS) {
1359 unsigned int ep_state;
1360 unsigned int slot_state;
1361
1362 switch (cmd_comp_code) {
1363 case COMP_TRB_ERROR:
1364 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1365 break;
1366 case COMP_CONTEXT_STATE_ERROR:
1367 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1368 ep_state = GET_EP_CTX_STATE(ep_ctx);
1369 slot_state = le32_to_cpu(slot_ctx->dev_state);
1370 slot_state = GET_SLOT_STATE(slot_state);
1371 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1372 "Slot state = %u, EP state = %u",
1373 slot_state, ep_state);
1374 break;
1375 case COMP_SLOT_NOT_ENABLED_ERROR:
1376 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1377 slot_id);
1378 break;
1379 default:
1380 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1381 cmd_comp_code);
1382 break;
1383 }
1384 /* OK what do we do now? The endpoint state is hosed, and we
1385 * should never get to this point if the synchronization between
1386 * queueing, and endpoint state are correct. This might happen
1387 * if the device gets disconnected after we've finished
1388 * cancelling URBs, which might not be an error...
1389 */
1390 } else {
1391 u64 deq;
1392 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1393 if (ep->ep_state & EP_HAS_STREAMS) {
1394 struct xhci_stream_ctx *ctx =
1395 &ep->stream_info->stream_ctx_array[stream_id];
1396 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1397 } else {
1398 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1399 }
1400 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1401 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1402 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1403 ep->queued_deq_ptr) == deq) {
1404 /* Update the ring's dequeue segment and dequeue pointer
1405 * to reflect the new position.
1406 */
1407 update_ring_for_set_deq_completion(xhci, ep->vdev,
1408 ep_ring, ep_index);
1409 } else {
1410 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1411 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1412 ep->queued_deq_seg, ep->queued_deq_ptr);
1413 }
1414 }
1415 /* HW cached TDs cleared from cache, give them back */
1416 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
1417 cancelled_td_list) {
1418 ep_ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
1419 if (td->cancel_status == TD_CLEARING_CACHE) {
1420 td->cancel_status = TD_CLEARED;
1421 xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n",
1422 __func__, td->urb);
1423 xhci_td_cleanup(ep->xhci, td, ep_ring, td->status);
1424 } else {
1425 xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
1426 __func__, td->urb, td->cancel_status);
1427 }
1428 }
1429cleanup:
1430 ep->ep_state &= ~SET_DEQ_PENDING;
1431 ep->queued_deq_seg = NULL;
1432 ep->queued_deq_ptr = NULL;
1433 /* Restart any rings with pending URBs */
1434 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1435}
1436
1437static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1438 union xhci_trb *trb, u32 cmd_comp_code)
1439{
1440 struct xhci_virt_ep *ep;
1441 struct xhci_ep_ctx *ep_ctx;
1442 unsigned int ep_index;
1443
1444 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1445 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1446 if (!ep)
1447 return;
1448
1449 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1450 trace_xhci_handle_cmd_reset_ep(ep_ctx);
1451
1452 /* This command will only fail if the endpoint wasn't halted,
1453 * but we don't care.
1454 */
1455 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1456 "Ignoring reset ep completion code of %u", cmd_comp_code);
1457
1458 /* Cleanup cancelled TDs as ep is stopped. May queue a Set TR Deq cmd */
1459 xhci_invalidate_cancelled_tds(ep);
1460
1461 /* Clear our internal halted state */
1462 ep->ep_state &= ~EP_HALTED;
1463
1464 xhci_giveback_invalidated_tds(ep);
1465
1466 /* if this was a soft reset, then restart */
1467 if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP)
1468 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1469}
1470
1471static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1472 struct xhci_command *command, u32 cmd_comp_code)
1473{
1474 if (cmd_comp_code == COMP_SUCCESS)
1475 command->slot_id = slot_id;
1476 else
1477 command->slot_id = 0;
1478}
1479
1480static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1481{
1482 struct xhci_virt_device *virt_dev;
1483 struct xhci_slot_ctx *slot_ctx;
1484
1485 virt_dev = xhci->devs[slot_id];
1486 if (!virt_dev)
1487 return;
1488
1489 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1490 trace_xhci_handle_cmd_disable_slot(slot_ctx);
1491
1492 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1493 /* Delete default control endpoint resources */
1494 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1495}
1496
1497static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1498 u32 cmd_comp_code)
1499{
1500 struct xhci_virt_device *virt_dev;
1501 struct xhci_input_control_ctx *ctrl_ctx;
1502 struct xhci_ep_ctx *ep_ctx;
1503 unsigned int ep_index;
1504 u32 add_flags;
1505
1506 /*
1507 * Configure endpoint commands can come from the USB core configuration
1508 * or alt setting changes, or when streams were being configured.
1509 */
1510
1511 virt_dev = xhci->devs[slot_id];
1512 if (!virt_dev)
1513 return;
1514 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1515 if (!ctrl_ctx) {
1516 xhci_warn(xhci, "Could not get input context, bad type.\n");
1517 return;
1518 }
1519
1520 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1521
1522 /* Input ctx add_flags are the endpoint index plus one */
1523 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1524
1525 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1526 trace_xhci_handle_cmd_config_ep(ep_ctx);
1527
1528 return;
1529}
1530
1531static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1532{
1533 struct xhci_virt_device *vdev;
1534 struct xhci_slot_ctx *slot_ctx;
1535
1536 vdev = xhci->devs[slot_id];
1537 if (!vdev)
1538 return;
1539 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1540 trace_xhci_handle_cmd_addr_dev(slot_ctx);
1541}
1542
1543static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id)
1544{
1545 struct xhci_virt_device *vdev;
1546 struct xhci_slot_ctx *slot_ctx;
1547
1548 vdev = xhci->devs[slot_id];
1549 if (!vdev) {
1550 xhci_warn(xhci, "Reset device command completion for disabled slot %u\n",
1551 slot_id);
1552 return;
1553 }
1554 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1555 trace_xhci_handle_cmd_reset_dev(slot_ctx);
1556
1557 xhci_dbg(xhci, "Completed reset device command.\n");
1558}
1559
1560static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1561 struct xhci_event_cmd *event)
1562{
1563 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1564 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1565 return;
1566 }
1567 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1568 "NEC firmware version %2x.%02x",
1569 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1570 NEC_FW_MINOR(le32_to_cpu(event->status)));
1571}
1572
1573static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1574{
1575 list_del(&cmd->cmd_list);
1576
1577 if (cmd->completion) {
1578 cmd->status = status;
1579 complete(cmd->completion);
1580 } else {
1581 kfree(cmd);
1582 }
1583}
1584
1585void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1586{
1587 struct xhci_command *cur_cmd, *tmp_cmd;
1588 xhci->current_cmd = NULL;
1589 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1590 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1591}
1592
1593void xhci_handle_command_timeout(struct work_struct *work)
1594{
1595 struct xhci_hcd *xhci;
1596 unsigned long flags;
1597 char str[XHCI_MSG_MAX];
1598 u64 hw_ring_state;
1599 u32 cmd_field3;
1600 u32 usbsts;
1601
1602 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1603
1604 spin_lock_irqsave(&xhci->lock, flags);
1605
1606 /*
1607 * If timeout work is pending, or current_cmd is NULL, it means we
1608 * raced with command completion. Command is handled so just return.
1609 */
1610 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1611 spin_unlock_irqrestore(&xhci->lock, flags);
1612 return;
1613 }
1614
1615 cmd_field3 = le32_to_cpu(xhci->current_cmd->command_trb->generic.field[3]);
1616 usbsts = readl(&xhci->op_regs->status);
1617 xhci_dbg(xhci, "Command timeout, USBSTS:%s\n", xhci_decode_usbsts(str, usbsts));
1618
1619 /* Bail out and tear down xhci if a stop endpoint command failed */
1620 if (TRB_FIELD_TO_TYPE(cmd_field3) == TRB_STOP_RING) {
1621 struct xhci_virt_ep *ep;
1622
1623 xhci_warn(xhci, "xHCI host not responding to stop endpoint command\n");
1624
1625 ep = xhci_get_virt_ep(xhci, TRB_TO_SLOT_ID(cmd_field3),
1626 TRB_TO_EP_INDEX(cmd_field3));
1627 if (ep)
1628 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1629
1630 xhci_halt(xhci);
1631 xhci_hc_died(xhci);
1632 goto time_out_completed;
1633 }
1634
1635 /* mark this command to be cancelled */
1636 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1637
1638 /* Make sure command ring is running before aborting it */
1639 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1640 if (hw_ring_state == ~(u64)0) {
1641 xhci_hc_died(xhci);
1642 goto time_out_completed;
1643 }
1644
1645 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1646 (hw_ring_state & CMD_RING_RUNNING)) {
1647 /* Prevent new doorbell, and start command abort */
1648 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1649 xhci_dbg(xhci, "Command timeout\n");
1650 xhci_abort_cmd_ring(xhci, flags);
1651 goto time_out_completed;
1652 }
1653
1654 /* host removed. Bail out */
1655 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1656 xhci_dbg(xhci, "host removed, ring start fail?\n");
1657 xhci_cleanup_command_queue(xhci);
1658
1659 goto time_out_completed;
1660 }
1661
1662 /* command timeout on stopped ring, ring can't be aborted */
1663 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1664 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1665
1666time_out_completed:
1667 spin_unlock_irqrestore(&xhci->lock, flags);
1668 return;
1669}
1670
1671static void handle_cmd_completion(struct xhci_hcd *xhci,
1672 struct xhci_event_cmd *event)
1673{
1674 unsigned int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1675 u64 cmd_dma;
1676 dma_addr_t cmd_dequeue_dma;
1677 u32 cmd_comp_code;
1678 union xhci_trb *cmd_trb;
1679 struct xhci_command *cmd;
1680 u32 cmd_type;
1681
1682 if (slot_id >= MAX_HC_SLOTS) {
1683 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
1684 return;
1685 }
1686
1687 cmd_dma = le64_to_cpu(event->cmd_trb);
1688 cmd_trb = xhci->cmd_ring->dequeue;
1689
1690 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1691
1692 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1693 cmd_trb);
1694 /*
1695 * Check whether the completion event is for our internal kept
1696 * command.
1697 */
1698 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1699 xhci_warn(xhci,
1700 "ERROR mismatched command completion event\n");
1701 return;
1702 }
1703
1704 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1705
1706 cancel_delayed_work(&xhci->cmd_timer);
1707
1708 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1709
1710 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1711 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1712 complete_all(&xhci->cmd_ring_stop_completion);
1713 return;
1714 }
1715
1716 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1717 xhci_err(xhci,
1718 "Command completion event does not match command\n");
1719 return;
1720 }
1721
1722 /*
1723 * Host aborted the command ring, check if the current command was
1724 * supposed to be aborted, otherwise continue normally.
1725 * The command ring is stopped now, but the xHC will issue a Command
1726 * Ring Stopped event which will cause us to restart it.
1727 */
1728 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1729 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1730 if (cmd->status == COMP_COMMAND_ABORTED) {
1731 if (xhci->current_cmd == cmd)
1732 xhci->current_cmd = NULL;
1733 goto event_handled;
1734 }
1735 }
1736
1737 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1738 switch (cmd_type) {
1739 case TRB_ENABLE_SLOT:
1740 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1741 break;
1742 case TRB_DISABLE_SLOT:
1743 xhci_handle_cmd_disable_slot(xhci, slot_id);
1744 break;
1745 case TRB_CONFIG_EP:
1746 if (!cmd->completion)
1747 xhci_handle_cmd_config_ep(xhci, slot_id, cmd_comp_code);
1748 break;
1749 case TRB_EVAL_CONTEXT:
1750 break;
1751 case TRB_ADDR_DEV:
1752 xhci_handle_cmd_addr_dev(xhci, slot_id);
1753 break;
1754 case TRB_STOP_RING:
1755 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1756 le32_to_cpu(cmd_trb->generic.field[3])));
1757 if (!cmd->completion)
1758 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb,
1759 cmd_comp_code);
1760 break;
1761 case TRB_SET_DEQ:
1762 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1763 le32_to_cpu(cmd_trb->generic.field[3])));
1764 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1765 break;
1766 case TRB_CMD_NOOP:
1767 /* Is this an aborted command turned to NO-OP? */
1768 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1769 cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1770 break;
1771 case TRB_RESET_EP:
1772 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1773 le32_to_cpu(cmd_trb->generic.field[3])));
1774 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1775 break;
1776 case TRB_RESET_DEV:
1777 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1778 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1779 */
1780 slot_id = TRB_TO_SLOT_ID(
1781 le32_to_cpu(cmd_trb->generic.field[3]));
1782 xhci_handle_cmd_reset_dev(xhci, slot_id);
1783 break;
1784 case TRB_NEC_GET_FW:
1785 xhci_handle_cmd_nec_get_fw(xhci, event);
1786 break;
1787 default:
1788 /* Skip over unknown commands on the event ring */
1789 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1790 break;
1791 }
1792
1793 /* restart timer if this wasn't the last command */
1794 if (!list_is_singular(&xhci->cmd_list)) {
1795 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1796 struct xhci_command, cmd_list);
1797 xhci_mod_cmd_timer(xhci);
1798 } else if (xhci->current_cmd == cmd) {
1799 xhci->current_cmd = NULL;
1800 }
1801
1802event_handled:
1803 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1804
1805 inc_deq(xhci, xhci->cmd_ring);
1806}
1807
1808static void handle_vendor_event(struct xhci_hcd *xhci,
1809 union xhci_trb *event, u32 trb_type)
1810{
1811 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1812 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1813 handle_cmd_completion(xhci, &event->event_cmd);
1814}
1815
1816static void handle_device_notification(struct xhci_hcd *xhci,
1817 union xhci_trb *event)
1818{
1819 u32 slot_id;
1820 struct usb_device *udev;
1821
1822 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1823 if (!xhci->devs[slot_id]) {
1824 xhci_warn(xhci, "Device Notification event for "
1825 "unused slot %u\n", slot_id);
1826 return;
1827 }
1828
1829 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1830 slot_id);
1831 udev = xhci->devs[slot_id]->udev;
1832 if (udev && udev->parent)
1833 usb_wakeup_notification(udev->parent, udev->portnum);
1834}
1835
1836/*
1837 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1838 * Controller.
1839 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1840 * If a connection to a USB 1 device is followed by another connection
1841 * to a USB 2 device.
1842 *
1843 * Reset the PHY after the USB device is disconnected if device speed
1844 * is less than HCD_USB3.
1845 * Retry the reset sequence max of 4 times checking the PLL lock status.
1846 *
1847 */
1848static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1849{
1850 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1851 u32 pll_lock_check;
1852 u32 retry_count = 4;
1853
1854 do {
1855 /* Assert PHY reset */
1856 writel(0x6F, hcd->regs + 0x1048);
1857 udelay(10);
1858 /* De-assert the PHY reset */
1859 writel(0x7F, hcd->regs + 0x1048);
1860 udelay(200);
1861 pll_lock_check = readl(hcd->regs + 0x1070);
1862 } while (!(pll_lock_check & 0x1) && --retry_count);
1863}
1864
1865static void handle_port_status(struct xhci_hcd *xhci,
1866 struct xhci_interrupter *ir,
1867 union xhci_trb *event)
1868{
1869 struct usb_hcd *hcd;
1870 u32 port_id;
1871 u32 portsc, cmd_reg;
1872 int max_ports;
1873 int slot_id;
1874 unsigned int hcd_portnum;
1875 struct xhci_bus_state *bus_state;
1876 bool bogus_port_status = false;
1877 struct xhci_port *port;
1878
1879 /* Port status change events always have a successful completion code */
1880 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1881 xhci_warn(xhci,
1882 "WARN: xHC returned failed port status event\n");
1883
1884 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1885 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1886
1887 if ((port_id <= 0) || (port_id > max_ports)) {
1888 xhci_warn(xhci, "Port change event with invalid port ID %d\n",
1889 port_id);
1890 return;
1891 }
1892
1893 port = &xhci->hw_ports[port_id - 1];
1894 if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1895 xhci_warn(xhci, "Port change event, no port for port ID %u\n",
1896 port_id);
1897 bogus_port_status = true;
1898 goto cleanup;
1899 }
1900
1901 /* We might get interrupts after shared_hcd is removed */
1902 if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
1903 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
1904 bogus_port_status = true;
1905 goto cleanup;
1906 }
1907
1908 hcd = port->rhub->hcd;
1909 bus_state = &port->rhub->bus_state;
1910 hcd_portnum = port->hcd_portnum;
1911 portsc = readl(port->addr);
1912
1913 xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n",
1914 hcd->self.busnum, hcd_portnum + 1, port_id, portsc);
1915
1916 trace_xhci_handle_port_status(port, portsc);
1917
1918 if (hcd->state == HC_STATE_SUSPENDED) {
1919 xhci_dbg(xhci, "resume root hub\n");
1920 usb_hcd_resume_root_hub(hcd);
1921 }
1922
1923 if (hcd->speed >= HCD_USB3 &&
1924 (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
1925 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1926 if (slot_id && xhci->devs[slot_id])
1927 xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR;
1928 }
1929
1930 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1931 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1932
1933 cmd_reg = readl(&xhci->op_regs->command);
1934 if (!(cmd_reg & CMD_RUN)) {
1935 xhci_warn(xhci, "xHC is not running.\n");
1936 goto cleanup;
1937 }
1938
1939 if (DEV_SUPERSPEED_ANY(portsc)) {
1940 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1941 /* Set a flag to say the port signaled remote wakeup,
1942 * so we can tell the difference between the end of
1943 * device and host initiated resume.
1944 */
1945 bus_state->port_remote_wakeup |= 1 << hcd_portnum;
1946 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1947 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1948 xhci_set_link_state(xhci, port, XDEV_U0);
1949 /* Need to wait until the next link state change
1950 * indicates the device is actually in U0.
1951 */
1952 bogus_port_status = true;
1953 goto cleanup;
1954 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
1955 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1956 port->resume_timestamp = jiffies +
1957 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1958 set_bit(hcd_portnum, &bus_state->resuming_ports);
1959 /* Do the rest in GetPortStatus after resume time delay.
1960 * Avoid polling roothub status before that so that a
1961 * usb device auto-resume latency around ~40ms.
1962 */
1963 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1964 mod_timer(&hcd->rh_timer,
1965 port->resume_timestamp);
1966 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1967 bogus_port_status = true;
1968 }
1969 }
1970
1971 if ((portsc & PORT_PLC) &&
1972 DEV_SUPERSPEED_ANY(portsc) &&
1973 ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
1974 (portsc & PORT_PLS_MASK) == XDEV_U1 ||
1975 (portsc & PORT_PLS_MASK) == XDEV_U2)) {
1976 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1977 complete(&port->u3exit_done);
1978 /* We've just brought the device into U0/1/2 through either the
1979 * Resume state after a device remote wakeup, or through the
1980 * U3Exit state after a host-initiated resume. If it's a device
1981 * initiated remote wake, don't pass up the link state change,
1982 * so the roothub behavior is consistent with external
1983 * USB 3.0 hub behavior.
1984 */
1985 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1986 if (slot_id && xhci->devs[slot_id])
1987 xhci_ring_device(xhci, slot_id);
1988 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
1989 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1990 usb_wakeup_notification(hcd->self.root_hub,
1991 hcd_portnum + 1);
1992 bogus_port_status = true;
1993 goto cleanup;
1994 }
1995 }
1996
1997 /*
1998 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1999 * RExit to a disconnect state). If so, let the driver know it's
2000 * out of the RExit state.
2001 */
2002 if (hcd->speed < HCD_USB3 && port->rexit_active) {
2003 complete(&port->rexit_done);
2004 port->rexit_active = false;
2005 bogus_port_status = true;
2006 goto cleanup;
2007 }
2008
2009 if (hcd->speed < HCD_USB3) {
2010 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
2011 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
2012 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
2013 xhci_cavium_reset_phy_quirk(xhci);
2014 }
2015
2016cleanup:
2017
2018 /* Don't make the USB core poll the roothub if we got a bad port status
2019 * change event. Besides, at that point we can't tell which roothub
2020 * (USB 2.0 or USB 3.0) to kick.
2021 */
2022 if (bogus_port_status)
2023 return;
2024
2025 /*
2026 * xHCI port-status-change events occur when the "or" of all the
2027 * status-change bits in the portsc register changes from 0 to 1.
2028 * New status changes won't cause an event if any other change
2029 * bits are still set. When an event occurs, switch over to
2030 * polling to avoid losing status changes.
2031 */
2032 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
2033 __func__, hcd->self.busnum);
2034 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
2035 spin_unlock(&xhci->lock);
2036 /* Pass this up to the core */
2037 usb_hcd_poll_rh_status(hcd);
2038 spin_lock(&xhci->lock);
2039}
2040
2041/*
2042 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
2043 * at end_trb, which may be in another segment. If the suspect DMA address is a
2044 * TRB in this TD, this function returns that TRB's segment. Otherwise it
2045 * returns 0.
2046 */
2047struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2048 struct xhci_segment *start_seg,
2049 union xhci_trb *start_trb,
2050 union xhci_trb *end_trb,
2051 dma_addr_t suspect_dma,
2052 bool debug)
2053{
2054 dma_addr_t start_dma;
2055 dma_addr_t end_seg_dma;
2056 dma_addr_t end_trb_dma;
2057 struct xhci_segment *cur_seg;
2058
2059 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
2060 cur_seg = start_seg;
2061
2062 do {
2063 if (start_dma == 0)
2064 return NULL;
2065 /* We may get an event for a Link TRB in the middle of a TD */
2066 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
2067 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
2068 /* If the end TRB isn't in this segment, this is set to 0 */
2069 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
2070
2071 if (debug)
2072 xhci_warn(xhci,
2073 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
2074 (unsigned long long)suspect_dma,
2075 (unsigned long long)start_dma,
2076 (unsigned long long)end_trb_dma,
2077 (unsigned long long)cur_seg->dma,
2078 (unsigned long long)end_seg_dma);
2079
2080 if (end_trb_dma > 0) {
2081 /* The end TRB is in this segment, so suspect should be here */
2082 if (start_dma <= end_trb_dma) {
2083 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
2084 return cur_seg;
2085 } else {
2086 /* Case for one segment with
2087 * a TD wrapped around to the top
2088 */
2089 if ((suspect_dma >= start_dma &&
2090 suspect_dma <= end_seg_dma) ||
2091 (suspect_dma >= cur_seg->dma &&
2092 suspect_dma <= end_trb_dma))
2093 return cur_seg;
2094 }
2095 return NULL;
2096 } else {
2097 /* Might still be somewhere in this segment */
2098 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
2099 return cur_seg;
2100 }
2101 cur_seg = cur_seg->next;
2102 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
2103 } while (cur_seg != start_seg);
2104
2105 return NULL;
2106}
2107
2108static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td,
2109 struct xhci_virt_ep *ep)
2110{
2111 /*
2112 * As part of low/full-speed endpoint-halt processing
2113 * we must clear the TT buffer (USB 2.0 specification 11.17.5).
2114 */
2115 if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) &&
2116 (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) &&
2117 !(ep->ep_state & EP_CLEARING_TT)) {
2118 ep->ep_state |= EP_CLEARING_TT;
2119 td->urb->ep->hcpriv = td->urb->dev;
2120 if (usb_hub_clear_tt_buffer(td->urb))
2121 ep->ep_state &= ~EP_CLEARING_TT;
2122 }
2123}
2124
2125/* Check if an error has halted the endpoint ring. The class driver will
2126 * cleanup the halt for a non-default control endpoint if we indicate a stall.
2127 * However, a babble and other errors also halt the endpoint ring, and the class
2128 * driver won't clear the halt in that case, so we need to issue a Set Transfer
2129 * Ring Dequeue Pointer command manually.
2130 */
2131static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
2132 struct xhci_ep_ctx *ep_ctx,
2133 unsigned int trb_comp_code)
2134{
2135 /* TRB completion codes that may require a manual halt cleanup */
2136 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
2137 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
2138 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
2139 /* The 0.95 spec says a babbling control endpoint
2140 * is not halted. The 0.96 spec says it is. Some HW
2141 * claims to be 0.95 compliant, but it halts the control
2142 * endpoint anyway. Check if a babble halted the
2143 * endpoint.
2144 */
2145 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
2146 return 1;
2147
2148 return 0;
2149}
2150
2151int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
2152{
2153 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
2154 /* Vendor defined "informational" completion code,
2155 * treat as not-an-error.
2156 */
2157 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
2158 trb_comp_code);
2159 xhci_dbg(xhci, "Treating code as success.\n");
2160 return 1;
2161 }
2162 return 0;
2163}
2164
2165static int finish_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2166 struct xhci_ring *ep_ring, struct xhci_td *td,
2167 u32 trb_comp_code)
2168{
2169 struct xhci_ep_ctx *ep_ctx;
2170
2171 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2172
2173 switch (trb_comp_code) {
2174 case COMP_STOPPED_LENGTH_INVALID:
2175 case COMP_STOPPED_SHORT_PACKET:
2176 case COMP_STOPPED:
2177 /*
2178 * The "Stop Endpoint" completion will take care of any
2179 * stopped TDs. A stopped TD may be restarted, so don't update
2180 * the ring dequeue pointer or take this TD off any lists yet.
2181 */
2182 return 0;
2183 case COMP_USB_TRANSACTION_ERROR:
2184 case COMP_BABBLE_DETECTED_ERROR:
2185 case COMP_SPLIT_TRANSACTION_ERROR:
2186 /*
2187 * If endpoint context state is not halted we might be
2188 * racing with a reset endpoint command issued by a unsuccessful
2189 * stop endpoint completion (context error). In that case the
2190 * td should be on the cancelled list, and EP_HALTED flag set.
2191 *
2192 * Or then it's not halted due to the 0.95 spec stating that a
2193 * babbling control endpoint should not halt. The 0.96 spec
2194 * again says it should. Some HW claims to be 0.95 compliant,
2195 * but it halts the control endpoint anyway.
2196 */
2197 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_HALTED) {
2198 /*
2199 * If EP_HALTED is set and TD is on the cancelled list
2200 * the TD and dequeue pointer will be handled by reset
2201 * ep command completion
2202 */
2203 if ((ep->ep_state & EP_HALTED) &&
2204 !list_empty(&td->cancelled_td_list)) {
2205 xhci_dbg(xhci, "Already resolving halted ep for 0x%llx\n",
2206 (unsigned long long)xhci_trb_virt_to_dma(
2207 td->start_seg, td->first_trb));
2208 return 0;
2209 }
2210 /* endpoint not halted, don't reset it */
2211 break;
2212 }
2213 /* Almost same procedure as for STALL_ERROR below */
2214 xhci_clear_hub_tt_buffer(xhci, td, ep);
2215 xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET);
2216 return 0;
2217 case COMP_STALL_ERROR:
2218 /*
2219 * xhci internal endpoint state will go to a "halt" state for
2220 * any stall, including default control pipe protocol stall.
2221 * To clear the host side halt we need to issue a reset endpoint
2222 * command, followed by a set dequeue command to move past the
2223 * TD.
2224 * Class drivers clear the device side halt from a functional
2225 * stall later. Hub TT buffer should only be cleared for FS/LS
2226 * devices behind HS hubs for functional stalls.
2227 */
2228 if (ep->ep_index != 0)
2229 xhci_clear_hub_tt_buffer(xhci, td, ep);
2230
2231 xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET);
2232
2233 return 0; /* xhci_handle_halted_endpoint marked td cancelled */
2234 default:
2235 break;
2236 }
2237
2238 /* Update ring dequeue pointer */
2239 ep_ring->dequeue = td->last_trb;
2240 ep_ring->deq_seg = td->last_trb_seg;
2241 inc_deq(xhci, ep_ring);
2242
2243 return xhci_td_cleanup(xhci, td, ep_ring, td->status);
2244}
2245
2246/* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
2247static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
2248 union xhci_trb *stop_trb)
2249{
2250 u32 sum;
2251 union xhci_trb *trb = ring->dequeue;
2252 struct xhci_segment *seg = ring->deq_seg;
2253
2254 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
2255 if (!trb_is_noop(trb) && !trb_is_link(trb))
2256 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2257 }
2258 return sum;
2259}
2260
2261/*
2262 * Process control tds, update urb status and actual_length.
2263 */
2264static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2265 struct xhci_ring *ep_ring, struct xhci_td *td,
2266 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2267{
2268 struct xhci_ep_ctx *ep_ctx;
2269 u32 trb_comp_code;
2270 u32 remaining, requested;
2271 u32 trb_type;
2272
2273 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2274 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2275 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2276 requested = td->urb->transfer_buffer_length;
2277 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2278
2279 switch (trb_comp_code) {
2280 case COMP_SUCCESS:
2281 if (trb_type != TRB_STATUS) {
2282 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2283 (trb_type == TRB_DATA) ? "data" : "setup");
2284 td->status = -ESHUTDOWN;
2285 break;
2286 }
2287 td->status = 0;
2288 break;
2289 case COMP_SHORT_PACKET:
2290 td->status = 0;
2291 break;
2292 case COMP_STOPPED_SHORT_PACKET:
2293 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2294 td->urb->actual_length = remaining;
2295 else
2296 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2297 goto finish_td;
2298 case COMP_STOPPED:
2299 switch (trb_type) {
2300 case TRB_SETUP:
2301 td->urb->actual_length = 0;
2302 goto finish_td;
2303 case TRB_DATA:
2304 case TRB_NORMAL:
2305 td->urb->actual_length = requested - remaining;
2306 goto finish_td;
2307 case TRB_STATUS:
2308 td->urb->actual_length = requested;
2309 goto finish_td;
2310 default:
2311 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2312 trb_type);
2313 goto finish_td;
2314 }
2315 case COMP_STOPPED_LENGTH_INVALID:
2316 goto finish_td;
2317 default:
2318 if (!xhci_requires_manual_halt_cleanup(xhci,
2319 ep_ctx, trb_comp_code))
2320 break;
2321 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2322 trb_comp_code, ep->ep_index);
2323 fallthrough;
2324 case COMP_STALL_ERROR:
2325 /* Did we transfer part of the data (middle) phase? */
2326 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2327 td->urb->actual_length = requested - remaining;
2328 else if (!td->urb_length_set)
2329 td->urb->actual_length = 0;
2330 goto finish_td;
2331 }
2332
2333 /* stopped at setup stage, no data transferred */
2334 if (trb_type == TRB_SETUP)
2335 goto finish_td;
2336
2337 /*
2338 * if on data stage then update the actual_length of the URB and flag it
2339 * as set, so it won't be overwritten in the event for the last TRB.
2340 */
2341 if (trb_type == TRB_DATA ||
2342 trb_type == TRB_NORMAL) {
2343 td->urb_length_set = true;
2344 td->urb->actual_length = requested - remaining;
2345 xhci_dbg(xhci, "Waiting for status stage event\n");
2346 return 0;
2347 }
2348
2349 /* at status stage */
2350 if (!td->urb_length_set)
2351 td->urb->actual_length = requested;
2352
2353finish_td:
2354 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2355}
2356
2357/*
2358 * Process isochronous tds, update urb packet status and actual_length.
2359 */
2360static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2361 struct xhci_ring *ep_ring, struct xhci_td *td,
2362 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2363{
2364 struct urb_priv *urb_priv;
2365 int idx;
2366 struct usb_iso_packet_descriptor *frame;
2367 u32 trb_comp_code;
2368 bool sum_trbs_for_length = false;
2369 u32 remaining, requested, ep_trb_len;
2370 int short_framestatus;
2371
2372 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2373 urb_priv = td->urb->hcpriv;
2374 idx = urb_priv->num_tds_done;
2375 frame = &td->urb->iso_frame_desc[idx];
2376 requested = frame->length;
2377 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2378 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2379 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2380 -EREMOTEIO : 0;
2381
2382 /* handle completion code */
2383 switch (trb_comp_code) {
2384 case COMP_SUCCESS:
2385 /* Don't overwrite status if TD had an error, see xHCI 4.9.1 */
2386 if (td->error_mid_td)
2387 break;
2388 if (remaining) {
2389 frame->status = short_framestatus;
2390 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2391 sum_trbs_for_length = true;
2392 break;
2393 }
2394 frame->status = 0;
2395 break;
2396 case COMP_SHORT_PACKET:
2397 frame->status = short_framestatus;
2398 sum_trbs_for_length = true;
2399 break;
2400 case COMP_BANDWIDTH_OVERRUN_ERROR:
2401 frame->status = -ECOMM;
2402 break;
2403 case COMP_BABBLE_DETECTED_ERROR:
2404 sum_trbs_for_length = true;
2405 fallthrough;
2406 case COMP_ISOCH_BUFFER_OVERRUN:
2407 frame->status = -EOVERFLOW;
2408 if (ep_trb != td->last_trb)
2409 td->error_mid_td = true;
2410 break;
2411 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2412 case COMP_STALL_ERROR:
2413 frame->status = -EPROTO;
2414 break;
2415 case COMP_USB_TRANSACTION_ERROR:
2416 frame->status = -EPROTO;
2417 sum_trbs_for_length = true;
2418 if (ep_trb != td->last_trb)
2419 td->error_mid_td = true;
2420 break;
2421 case COMP_STOPPED:
2422 sum_trbs_for_length = true;
2423 break;
2424 case COMP_STOPPED_SHORT_PACKET:
2425 /* field normally containing residue now contains tranferred */
2426 frame->status = short_framestatus;
2427 requested = remaining;
2428 break;
2429 case COMP_STOPPED_LENGTH_INVALID:
2430 requested = 0;
2431 remaining = 0;
2432 break;
2433 default:
2434 sum_trbs_for_length = true;
2435 frame->status = -1;
2436 break;
2437 }
2438
2439 if (td->urb_length_set)
2440 goto finish_td;
2441
2442 if (sum_trbs_for_length)
2443 frame->actual_length = sum_trb_lengths(xhci, ep->ring, ep_trb) +
2444 ep_trb_len - remaining;
2445 else
2446 frame->actual_length = requested;
2447
2448 td->urb->actual_length += frame->actual_length;
2449
2450finish_td:
2451 /* Don't give back TD yet if we encountered an error mid TD */
2452 if (td->error_mid_td && ep_trb != td->last_trb) {
2453 xhci_dbg(xhci, "Error mid isoc TD, wait for final completion event\n");
2454 td->urb_length_set = true;
2455 return 0;
2456 }
2457
2458 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2459}
2460
2461static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2462 struct xhci_virt_ep *ep, int status)
2463{
2464 struct urb_priv *urb_priv;
2465 struct usb_iso_packet_descriptor *frame;
2466 int idx;
2467
2468 urb_priv = td->urb->hcpriv;
2469 idx = urb_priv->num_tds_done;
2470 frame = &td->urb->iso_frame_desc[idx];
2471
2472 /* The transfer is partly done. */
2473 frame->status = -EXDEV;
2474
2475 /* calc actual length */
2476 frame->actual_length = 0;
2477
2478 /* Update ring dequeue pointer */
2479 ep->ring->dequeue = td->last_trb;
2480 ep->ring->deq_seg = td->last_trb_seg;
2481 inc_deq(xhci, ep->ring);
2482
2483 return xhci_td_cleanup(xhci, td, ep->ring, status);
2484}
2485
2486/*
2487 * Process bulk and interrupt tds, update urb status and actual_length.
2488 */
2489static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2490 struct xhci_ring *ep_ring, struct xhci_td *td,
2491 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2492{
2493 struct xhci_slot_ctx *slot_ctx;
2494 u32 trb_comp_code;
2495 u32 remaining, requested, ep_trb_len;
2496
2497 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
2498 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2499 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2500 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2501 requested = td->urb->transfer_buffer_length;
2502
2503 switch (trb_comp_code) {
2504 case COMP_SUCCESS:
2505 ep->err_count = 0;
2506 /* handle success with untransferred data as short packet */
2507 if (ep_trb != td->last_trb || remaining) {
2508 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2509 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2510 td->urb->ep->desc.bEndpointAddress,
2511 requested, remaining);
2512 }
2513 td->status = 0;
2514 break;
2515 case COMP_SHORT_PACKET:
2516 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2517 td->urb->ep->desc.bEndpointAddress,
2518 requested, remaining);
2519 td->status = 0;
2520 break;
2521 case COMP_STOPPED_SHORT_PACKET:
2522 td->urb->actual_length = remaining;
2523 goto finish_td;
2524 case COMP_STOPPED_LENGTH_INVALID:
2525 /* stopped on ep trb with invalid length, exclude it */
2526 ep_trb_len = 0;
2527 remaining = 0;
2528 break;
2529 case COMP_USB_TRANSACTION_ERROR:
2530 if (xhci->quirks & XHCI_NO_SOFT_RETRY ||
2531 (ep->err_count++ > MAX_SOFT_RETRY) ||
2532 le32_to_cpu(slot_ctx->tt_info) & TT_SLOT)
2533 break;
2534
2535 td->status = 0;
2536
2537 xhci_handle_halted_endpoint(xhci, ep, td, EP_SOFT_RESET);
2538 return 0;
2539 default:
2540 /* do nothing */
2541 break;
2542 }
2543
2544 if (ep_trb == td->last_trb)
2545 td->urb->actual_length = requested - remaining;
2546 else
2547 td->urb->actual_length =
2548 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2549 ep_trb_len - remaining;
2550finish_td:
2551 if (remaining > requested) {
2552 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2553 remaining);
2554 td->urb->actual_length = 0;
2555 }
2556
2557 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2558}
2559
2560/*
2561 * If this function returns an error condition, it means it got a Transfer
2562 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2563 * At this point, the host controller is probably hosed and should be reset.
2564 */
2565static int handle_tx_event(struct xhci_hcd *xhci,
2566 struct xhci_interrupter *ir,
2567 struct xhci_transfer_event *event)
2568{
2569 struct xhci_virt_ep *ep;
2570 struct xhci_ring *ep_ring;
2571 unsigned int slot_id;
2572 int ep_index;
2573 struct xhci_td *td = NULL;
2574 dma_addr_t ep_trb_dma;
2575 struct xhci_segment *ep_seg;
2576 union xhci_trb *ep_trb;
2577 int status = -EINPROGRESS;
2578 struct xhci_ep_ctx *ep_ctx;
2579 u32 trb_comp_code;
2580 int td_num = 0;
2581 bool handling_skipped_tds = false;
2582
2583 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2584 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2585 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2586 ep_trb_dma = le64_to_cpu(event->buffer);
2587
2588 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
2589 if (!ep) {
2590 xhci_err(xhci, "ERROR Invalid Transfer event\n");
2591 goto err_out;
2592 }
2593
2594 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2595 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
2596
2597 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2598 xhci_err(xhci,
2599 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2600 slot_id, ep_index);
2601 goto err_out;
2602 }
2603
2604 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2605 if (!ep_ring) {
2606 switch (trb_comp_code) {
2607 case COMP_STALL_ERROR:
2608 case COMP_USB_TRANSACTION_ERROR:
2609 case COMP_INVALID_STREAM_TYPE_ERROR:
2610 case COMP_INVALID_STREAM_ID_ERROR:
2611 xhci_dbg(xhci, "Stream transaction error ep %u no id\n",
2612 ep_index);
2613 if (ep->err_count++ > MAX_SOFT_RETRY)
2614 xhci_handle_halted_endpoint(xhci, ep, NULL,
2615 EP_HARD_RESET);
2616 else
2617 xhci_handle_halted_endpoint(xhci, ep, NULL,
2618 EP_SOFT_RESET);
2619 goto cleanup;
2620 case COMP_RING_UNDERRUN:
2621 case COMP_RING_OVERRUN:
2622 case COMP_STOPPED_LENGTH_INVALID:
2623 goto cleanup;
2624 default:
2625 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2626 slot_id, ep_index);
2627 goto err_out;
2628 }
2629 }
2630
2631 /* Count current td numbers if ep->skip is set */
2632 if (ep->skip)
2633 td_num += list_count_nodes(&ep_ring->td_list);
2634
2635 /* Look for common error cases */
2636 switch (trb_comp_code) {
2637 /* Skip codes that require special handling depending on
2638 * transfer type
2639 */
2640 case COMP_SUCCESS:
2641 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2642 break;
2643 if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
2644 ep_ring->last_td_was_short)
2645 trb_comp_code = COMP_SHORT_PACKET;
2646 else
2647 xhci_warn_ratelimited(xhci,
2648 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2649 slot_id, ep_index);
2650 break;
2651 case COMP_SHORT_PACKET:
2652 break;
2653 /* Completion codes for endpoint stopped state */
2654 case COMP_STOPPED:
2655 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2656 slot_id, ep_index);
2657 break;
2658 case COMP_STOPPED_LENGTH_INVALID:
2659 xhci_dbg(xhci,
2660 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2661 slot_id, ep_index);
2662 break;
2663 case COMP_STOPPED_SHORT_PACKET:
2664 xhci_dbg(xhci,
2665 "Stopped with short packet transfer detected for slot %u ep %u\n",
2666 slot_id, ep_index);
2667 break;
2668 /* Completion codes for endpoint halted state */
2669 case COMP_STALL_ERROR:
2670 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2671 ep_index);
2672 status = -EPIPE;
2673 break;
2674 case COMP_SPLIT_TRANSACTION_ERROR:
2675 xhci_dbg(xhci, "Split transaction error for slot %u ep %u\n",
2676 slot_id, ep_index);
2677 status = -EPROTO;
2678 break;
2679 case COMP_USB_TRANSACTION_ERROR:
2680 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2681 slot_id, ep_index);
2682 status = -EPROTO;
2683 break;
2684 case COMP_BABBLE_DETECTED_ERROR:
2685 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2686 slot_id, ep_index);
2687 status = -EOVERFLOW;
2688 break;
2689 /* Completion codes for endpoint error state */
2690 case COMP_TRB_ERROR:
2691 xhci_warn(xhci,
2692 "WARN: TRB error for slot %u ep %u on endpoint\n",
2693 slot_id, ep_index);
2694 status = -EILSEQ;
2695 break;
2696 /* completion codes not indicating endpoint state change */
2697 case COMP_DATA_BUFFER_ERROR:
2698 xhci_warn(xhci,
2699 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2700 slot_id, ep_index);
2701 status = -ENOSR;
2702 break;
2703 case COMP_BANDWIDTH_OVERRUN_ERROR:
2704 xhci_warn(xhci,
2705 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2706 slot_id, ep_index);
2707 break;
2708 case COMP_ISOCH_BUFFER_OVERRUN:
2709 xhci_warn(xhci,
2710 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2711 slot_id, ep_index);
2712 break;
2713 case COMP_RING_UNDERRUN:
2714 /*
2715 * When the Isoch ring is empty, the xHC will generate
2716 * a Ring Overrun Event for IN Isoch endpoint or Ring
2717 * Underrun Event for OUT Isoch endpoint.
2718 */
2719 xhci_dbg(xhci, "underrun event on endpoint\n");
2720 if (!list_empty(&ep_ring->td_list))
2721 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2722 "still with TDs queued?\n",
2723 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2724 ep_index);
2725 goto cleanup;
2726 case COMP_RING_OVERRUN:
2727 xhci_dbg(xhci, "overrun event on endpoint\n");
2728 if (!list_empty(&ep_ring->td_list))
2729 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2730 "still with TDs queued?\n",
2731 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2732 ep_index);
2733 goto cleanup;
2734 case COMP_MISSED_SERVICE_ERROR:
2735 /*
2736 * When encounter missed service error, one or more isoc tds
2737 * may be missed by xHC.
2738 * Set skip flag of the ep_ring; Complete the missed tds as
2739 * short transfer when process the ep_ring next time.
2740 */
2741 ep->skip = true;
2742 xhci_dbg(xhci,
2743 "Miss service interval error for slot %u ep %u, set skip flag\n",
2744 slot_id, ep_index);
2745 goto cleanup;
2746 case COMP_NO_PING_RESPONSE_ERROR:
2747 ep->skip = true;
2748 xhci_dbg(xhci,
2749 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2750 slot_id, ep_index);
2751 goto cleanup;
2752
2753 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2754 /* needs disable slot command to recover */
2755 xhci_warn(xhci,
2756 "WARN: detect an incompatible device for slot %u ep %u",
2757 slot_id, ep_index);
2758 status = -EPROTO;
2759 break;
2760 default:
2761 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2762 status = 0;
2763 break;
2764 }
2765 xhci_warn(xhci,
2766 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2767 trb_comp_code, slot_id, ep_index);
2768 goto cleanup;
2769 }
2770
2771 do {
2772 /* This TRB should be in the TD at the head of this ring's
2773 * TD list.
2774 */
2775 if (list_empty(&ep_ring->td_list)) {
2776 /*
2777 * Don't print wanings if it's due to a stopped endpoint
2778 * generating an extra completion event if the device
2779 * was suspended. Or, a event for the last TRB of a
2780 * short TD we already got a short event for.
2781 * The short TD is already removed from the TD list.
2782 */
2783
2784 if (!(trb_comp_code == COMP_STOPPED ||
2785 trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2786 ep_ring->last_td_was_short)) {
2787 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2788 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2789 ep_index);
2790 }
2791 if (ep->skip) {
2792 ep->skip = false;
2793 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2794 slot_id, ep_index);
2795 }
2796 if (trb_comp_code == COMP_STALL_ERROR ||
2797 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2798 trb_comp_code)) {
2799 xhci_handle_halted_endpoint(xhci, ep, NULL,
2800 EP_HARD_RESET);
2801 }
2802 goto cleanup;
2803 }
2804
2805 /* We've skipped all the TDs on the ep ring when ep->skip set */
2806 if (ep->skip && td_num == 0) {
2807 ep->skip = false;
2808 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2809 slot_id, ep_index);
2810 goto cleanup;
2811 }
2812
2813 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2814 td_list);
2815 if (ep->skip)
2816 td_num--;
2817
2818 /* Is this a TRB in the currently executing TD? */
2819 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2820 td->last_trb, ep_trb_dma, false);
2821
2822 /*
2823 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2824 * is not in the current TD pointed by ep_ring->dequeue because
2825 * that the hardware dequeue pointer still at the previous TRB
2826 * of the current TD. The previous TRB maybe a Link TD or the
2827 * last TRB of the previous TD. The command completion handle
2828 * will take care the rest.
2829 */
2830 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2831 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2832 goto cleanup;
2833 }
2834
2835 if (!ep_seg) {
2836
2837 if (ep->skip && usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2838 skip_isoc_td(xhci, td, ep, status);
2839 goto cleanup;
2840 }
2841
2842 /*
2843 * Some hosts give a spurious success event after a short
2844 * transfer. Ignore it.
2845 */
2846 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2847 ep_ring->last_td_was_short) {
2848 ep_ring->last_td_was_short = false;
2849 goto cleanup;
2850 }
2851
2852 /*
2853 * xhci 4.10.2 states isoc endpoints should continue
2854 * processing the next TD if there was an error mid TD.
2855 * So host like NEC don't generate an event for the last
2856 * isoc TRB even if the IOC flag is set.
2857 * xhci 4.9.1 states that if there are errors in mult-TRB
2858 * TDs xHC should generate an error for that TRB, and if xHC
2859 * proceeds to the next TD it should genete an event for
2860 * any TRB with IOC flag on the way. Other host follow this.
2861 * So this event might be for the next TD.
2862 */
2863 if (td->error_mid_td &&
2864 !list_is_last(&td->td_list, &ep_ring->td_list)) {
2865 struct xhci_td *td_next = list_next_entry(td, td_list);
2866
2867 ep_seg = trb_in_td(xhci, td_next->start_seg, td_next->first_trb,
2868 td_next->last_trb, ep_trb_dma, false);
2869 if (ep_seg) {
2870 /* give back previous TD, start handling new */
2871 xhci_dbg(xhci, "Missing TD completion event after mid TD error\n");
2872 ep_ring->dequeue = td->last_trb;
2873 ep_ring->deq_seg = td->last_trb_seg;
2874 inc_deq(xhci, ep_ring);
2875 xhci_td_cleanup(xhci, td, ep_ring, td->status);
2876 td = td_next;
2877 }
2878 }
2879
2880 if (!ep_seg) {
2881 /* HC is busted, give up! */
2882 xhci_err(xhci,
2883 "ERROR Transfer event TRB DMA ptr not "
2884 "part of current TD ep_index %d "
2885 "comp_code %u\n", ep_index,
2886 trb_comp_code);
2887 trb_in_td(xhci, ep_ring->deq_seg,
2888 ep_ring->dequeue, td->last_trb,
2889 ep_trb_dma, true);
2890 return -ESHUTDOWN;
2891 }
2892 }
2893 if (trb_comp_code == COMP_SHORT_PACKET)
2894 ep_ring->last_td_was_short = true;
2895 else
2896 ep_ring->last_td_was_short = false;
2897
2898 if (ep->skip) {
2899 xhci_dbg(xhci,
2900 "Found td. Clear skip flag for slot %u ep %u.\n",
2901 slot_id, ep_index);
2902 ep->skip = false;
2903 }
2904
2905 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2906 sizeof(*ep_trb)];
2907
2908 trace_xhci_handle_transfer(ep_ring,
2909 (struct xhci_generic_trb *) ep_trb);
2910
2911 /*
2912 * No-op TRB could trigger interrupts in a case where
2913 * a URB was killed and a STALL_ERROR happens right
2914 * after the endpoint ring stopped. Reset the halted
2915 * endpoint. Otherwise, the endpoint remains stalled
2916 * indefinitely.
2917 */
2918
2919 if (trb_is_noop(ep_trb)) {
2920 if (trb_comp_code == COMP_STALL_ERROR ||
2921 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2922 trb_comp_code))
2923 xhci_handle_halted_endpoint(xhci, ep, td,
2924 EP_HARD_RESET);
2925 goto cleanup;
2926 }
2927
2928 td->status = status;
2929
2930 /* update the urb's actual_length and give back to the core */
2931 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2932 process_ctrl_td(xhci, ep, ep_ring, td, ep_trb, event);
2933 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2934 process_isoc_td(xhci, ep, ep_ring, td, ep_trb, event);
2935 else
2936 process_bulk_intr_td(xhci, ep, ep_ring, td, ep_trb, event);
2937cleanup:
2938 handling_skipped_tds = ep->skip &&
2939 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2940 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2941
2942 /*
2943 * If ep->skip is set, it means there are missed tds on the
2944 * endpoint ring need to take care of.
2945 * Process them as short transfer until reach the td pointed by
2946 * the event.
2947 */
2948 } while (handling_skipped_tds);
2949
2950 return 0;
2951
2952err_out:
2953 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2954 (unsigned long long) xhci_trb_virt_to_dma(
2955 ir->event_ring->deq_seg,
2956 ir->event_ring->dequeue),
2957 lower_32_bits(le64_to_cpu(event->buffer)),
2958 upper_32_bits(le64_to_cpu(event->buffer)),
2959 le32_to_cpu(event->transfer_len),
2960 le32_to_cpu(event->flags));
2961 return -ENODEV;
2962}
2963
2964/*
2965 * This function handles all OS-owned events on the event ring. It may drop
2966 * xhci->lock between event processing (e.g. to pass up port status changes).
2967 * Returns >0 for "possibly more events to process" (caller should call again),
2968 * otherwise 0 if done. In future, <0 returns should indicate error code.
2969 */
2970static int xhci_handle_event(struct xhci_hcd *xhci, struct xhci_interrupter *ir)
2971{
2972 union xhci_trb *event;
2973 u32 trb_type;
2974
2975 /* Event ring hasn't been allocated yet. */
2976 if (!ir || !ir->event_ring || !ir->event_ring->dequeue) {
2977 xhci_err(xhci, "ERROR interrupter not ready\n");
2978 return -ENOMEM;
2979 }
2980
2981 event = ir->event_ring->dequeue;
2982 /* Does the HC or OS own the TRB? */
2983 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2984 ir->event_ring->cycle_state)
2985 return 0;
2986
2987 trace_xhci_handle_event(ir->event_ring, &event->generic);
2988
2989 /*
2990 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2991 * speculative reads of the event's flags/data below.
2992 */
2993 rmb();
2994 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
2995 /* FIXME: Handle more event types. */
2996
2997 switch (trb_type) {
2998 case TRB_COMPLETION:
2999 handle_cmd_completion(xhci, &event->event_cmd);
3000 break;
3001 case TRB_PORT_STATUS:
3002 handle_port_status(xhci, ir, event);
3003 break;
3004 case TRB_TRANSFER:
3005 handle_tx_event(xhci, ir, &event->trans_event);
3006 break;
3007 case TRB_DEV_NOTE:
3008 handle_device_notification(xhci, event);
3009 break;
3010 default:
3011 if (trb_type >= TRB_VENDOR_DEFINED_LOW)
3012 handle_vendor_event(xhci, event, trb_type);
3013 else
3014 xhci_warn(xhci, "ERROR unknown event type %d\n", trb_type);
3015 }
3016 /* Any of the above functions may drop and re-acquire the lock, so check
3017 * to make sure a watchdog timer didn't mark the host as non-responsive.
3018 */
3019 if (xhci->xhc_state & XHCI_STATE_DYING) {
3020 xhci_dbg(xhci, "xHCI host dying, returning from "
3021 "event handler.\n");
3022 return 0;
3023 }
3024
3025 /* Update SW event ring dequeue pointer */
3026 inc_deq(xhci, ir->event_ring);
3027
3028 /* Are there more items on the event ring? Caller will call us again to
3029 * check.
3030 */
3031 return 1;
3032}
3033
3034/*
3035 * Update Event Ring Dequeue Pointer:
3036 * - When all events have finished
3037 * - To avoid "Event Ring Full Error" condition
3038 */
3039static void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
3040 struct xhci_interrupter *ir,
3041 union xhci_trb *event_ring_deq,
3042 bool clear_ehb)
3043{
3044 u64 temp_64;
3045 dma_addr_t deq;
3046
3047 temp_64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
3048 /* If necessary, update the HW's version of the event ring deq ptr. */
3049 if (event_ring_deq != ir->event_ring->dequeue) {
3050 deq = xhci_trb_virt_to_dma(ir->event_ring->deq_seg,
3051 ir->event_ring->dequeue);
3052 if (deq == 0)
3053 xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n");
3054 /*
3055 * Per 4.9.4, Software writes to the ERDP register shall
3056 * always advance the Event Ring Dequeue Pointer value.
3057 */
3058 if ((temp_64 & ERST_PTR_MASK) == (deq & ERST_PTR_MASK))
3059 return;
3060
3061 /* Update HC event ring dequeue pointer */
3062 temp_64 = ir->event_ring->deq_seg->num & ERST_DESI_MASK;
3063 temp_64 |= deq & ERST_PTR_MASK;
3064 }
3065
3066 /* Clear the event handler busy flag (RW1C) */
3067 if (clear_ehb)
3068 temp_64 |= ERST_EHB;
3069 xhci_write_64(xhci, temp_64, &ir->ir_set->erst_dequeue);
3070}
3071
3072/*
3073 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
3074 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
3075 * indicators of an event TRB error, but we check the status *first* to be safe.
3076 */
3077irqreturn_t xhci_irq(struct usb_hcd *hcd)
3078{
3079 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3080 union xhci_trb *event_ring_deq;
3081 struct xhci_interrupter *ir;
3082 irqreturn_t ret = IRQ_NONE;
3083 u64 temp_64;
3084 u32 status;
3085 int event_loop = 0;
3086
3087 spin_lock(&xhci->lock);
3088 /* Check if the xHC generated the interrupt, or the irq is shared */
3089 status = readl(&xhci->op_regs->status);
3090 if (status == ~(u32)0) {
3091 xhci_hc_died(xhci);
3092 ret = IRQ_HANDLED;
3093 goto out;
3094 }
3095
3096 if (!(status & STS_EINT))
3097 goto out;
3098
3099 if (status & STS_HCE) {
3100 xhci_warn(xhci, "WARNING: Host Controller Error\n");
3101 goto out;
3102 }
3103
3104 if (status & STS_FATAL) {
3105 xhci_warn(xhci, "WARNING: Host System Error\n");
3106 xhci_halt(xhci);
3107 ret = IRQ_HANDLED;
3108 goto out;
3109 }
3110
3111 /*
3112 * Clear the op reg interrupt status first,
3113 * so we can receive interrupts from other MSI-X interrupters.
3114 * Write 1 to clear the interrupt status.
3115 */
3116 status |= STS_EINT;
3117 writel(status, &xhci->op_regs->status);
3118
3119 /* This is the handler of the primary interrupter */
3120 ir = xhci->interrupters[0];
3121 if (!hcd->msi_enabled) {
3122 u32 irq_pending;
3123 irq_pending = readl(&ir->ir_set->irq_pending);
3124 irq_pending |= IMAN_IP;
3125 writel(irq_pending, &ir->ir_set->irq_pending);
3126 }
3127
3128 if (xhci->xhc_state & XHCI_STATE_DYING ||
3129 xhci->xhc_state & XHCI_STATE_HALTED) {
3130 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
3131 "Shouldn't IRQs be disabled?\n");
3132 /* Clear the event handler busy flag (RW1C);
3133 * the event ring should be empty.
3134 */
3135 temp_64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
3136 xhci_write_64(xhci, temp_64 | ERST_EHB,
3137 &ir->ir_set->erst_dequeue);
3138 ret = IRQ_HANDLED;
3139 goto out;
3140 }
3141
3142 event_ring_deq = ir->event_ring->dequeue;
3143 /* FIXME this should be a delayed service routine
3144 * that clears the EHB.
3145 */
3146 while (xhci_handle_event(xhci, ir) > 0) {
3147 if (event_loop++ < TRBS_PER_SEGMENT / 2)
3148 continue;
3149 xhci_update_erst_dequeue(xhci, ir, event_ring_deq, false);
3150 event_ring_deq = ir->event_ring->dequeue;
3151
3152 /* ring is half-full, force isoc trbs to interrupt more often */
3153 if (xhci->isoc_bei_interval > AVOID_BEI_INTERVAL_MIN)
3154 xhci->isoc_bei_interval = xhci->isoc_bei_interval / 2;
3155
3156 event_loop = 0;
3157 }
3158
3159 xhci_update_erst_dequeue(xhci, ir, event_ring_deq, true);
3160 ret = IRQ_HANDLED;
3161
3162out:
3163 spin_unlock(&xhci->lock);
3164
3165 return ret;
3166}
3167
3168irqreturn_t xhci_msi_irq(int irq, void *hcd)
3169{
3170 return xhci_irq(hcd);
3171}
3172EXPORT_SYMBOL_GPL(xhci_msi_irq);
3173
3174/**** Endpoint Ring Operations ****/
3175
3176/*
3177 * Generic function for queueing a TRB on a ring.
3178 * The caller must have checked to make sure there's room on the ring.
3179 *
3180 * @more_trbs_coming: Will you enqueue more TRBs before calling
3181 * prepare_transfer()?
3182 */
3183static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
3184 bool more_trbs_coming,
3185 u32 field1, u32 field2, u32 field3, u32 field4)
3186{
3187 struct xhci_generic_trb *trb;
3188
3189 trb = &ring->enqueue->generic;
3190 trb->field[0] = cpu_to_le32(field1);
3191 trb->field[1] = cpu_to_le32(field2);
3192 trb->field[2] = cpu_to_le32(field3);
3193 /* make sure TRB is fully written before giving it to the controller */
3194 wmb();
3195 trb->field[3] = cpu_to_le32(field4);
3196
3197 trace_xhci_queue_trb(ring, trb);
3198
3199 inc_enq(xhci, ring, more_trbs_coming);
3200}
3201
3202/*
3203 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
3204 * expand ring if it start to be full.
3205 */
3206static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
3207 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
3208{
3209 unsigned int link_trb_count = 0;
3210 unsigned int new_segs = 0;
3211
3212 /* Make sure the endpoint has been added to xHC schedule */
3213 switch (ep_state) {
3214 case EP_STATE_DISABLED:
3215 /*
3216 * USB core changed config/interfaces without notifying us,
3217 * or hardware is reporting the wrong state.
3218 */
3219 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
3220 return -ENOENT;
3221 case EP_STATE_ERROR:
3222 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
3223 /* FIXME event handling code for error needs to clear it */
3224 /* XXX not sure if this should be -ENOENT or not */
3225 return -EINVAL;
3226 case EP_STATE_HALTED:
3227 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
3228 break;
3229 case EP_STATE_STOPPED:
3230 case EP_STATE_RUNNING:
3231 break;
3232 default:
3233 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
3234 /*
3235 * FIXME issue Configure Endpoint command to try to get the HC
3236 * back into a known state.
3237 */
3238 return -EINVAL;
3239 }
3240
3241 if (ep_ring != xhci->cmd_ring) {
3242 new_segs = xhci_ring_expansion_needed(xhci, ep_ring, num_trbs);
3243 } else if (xhci_num_trbs_free(xhci, ep_ring) <= num_trbs) {
3244 xhci_err(xhci, "Do not support expand command ring\n");
3245 return -ENOMEM;
3246 }
3247
3248 if (new_segs) {
3249 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
3250 "ERROR no room on ep ring, try ring expansion");
3251 if (xhci_ring_expansion(xhci, ep_ring, new_segs, mem_flags)) {
3252 xhci_err(xhci, "Ring expansion failed\n");
3253 return -ENOMEM;
3254 }
3255 }
3256
3257 while (trb_is_link(ep_ring->enqueue)) {
3258 /* If we're not dealing with 0.95 hardware or isoc rings
3259 * on AMD 0.96 host, clear the chain bit.
3260 */
3261 if (!xhci_link_trb_quirk(xhci) &&
3262 !(ep_ring->type == TYPE_ISOC &&
3263 (xhci->quirks & XHCI_AMD_0x96_HOST)))
3264 ep_ring->enqueue->link.control &=
3265 cpu_to_le32(~TRB_CHAIN);
3266 else
3267 ep_ring->enqueue->link.control |=
3268 cpu_to_le32(TRB_CHAIN);
3269
3270 wmb();
3271 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
3272
3273 /* Toggle the cycle bit after the last ring segment. */
3274 if (link_trb_toggles_cycle(ep_ring->enqueue))
3275 ep_ring->cycle_state ^= 1;
3276
3277 ep_ring->enq_seg = ep_ring->enq_seg->next;
3278 ep_ring->enqueue = ep_ring->enq_seg->trbs;
3279
3280 /* prevent infinite loop if all first trbs are link trbs */
3281 if (link_trb_count++ > ep_ring->num_segs) {
3282 xhci_warn(xhci, "Ring is an endless link TRB loop\n");
3283 return -EINVAL;
3284 }
3285 }
3286
3287 if (last_trb_on_seg(ep_ring->enq_seg, ep_ring->enqueue)) {
3288 xhci_warn(xhci, "Missing link TRB at end of ring segment\n");
3289 return -EINVAL;
3290 }
3291
3292 return 0;
3293}
3294
3295static int prepare_transfer(struct xhci_hcd *xhci,
3296 struct xhci_virt_device *xdev,
3297 unsigned int ep_index,
3298 unsigned int stream_id,
3299 unsigned int num_trbs,
3300 struct urb *urb,
3301 unsigned int td_index,
3302 gfp_t mem_flags)
3303{
3304 int ret;
3305 struct urb_priv *urb_priv;
3306 struct xhci_td *td;
3307 struct xhci_ring *ep_ring;
3308 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3309
3310 ep_ring = xhci_triad_to_transfer_ring(xhci, xdev->slot_id, ep_index,
3311 stream_id);
3312 if (!ep_ring) {
3313 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3314 stream_id);
3315 return -EINVAL;
3316 }
3317
3318 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3319 num_trbs, mem_flags);
3320 if (ret)
3321 return ret;
3322
3323 urb_priv = urb->hcpriv;
3324 td = &urb_priv->td[td_index];
3325
3326 INIT_LIST_HEAD(&td->td_list);
3327 INIT_LIST_HEAD(&td->cancelled_td_list);
3328
3329 if (td_index == 0) {
3330 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3331 if (unlikely(ret))
3332 return ret;
3333 }
3334
3335 td->urb = urb;
3336 /* Add this TD to the tail of the endpoint ring's TD list */
3337 list_add_tail(&td->td_list, &ep_ring->td_list);
3338 td->start_seg = ep_ring->enq_seg;
3339 td->first_trb = ep_ring->enqueue;
3340
3341 return 0;
3342}
3343
3344unsigned int count_trbs(u64 addr, u64 len)
3345{
3346 unsigned int num_trbs;
3347
3348 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3349 TRB_MAX_BUFF_SIZE);
3350 if (num_trbs == 0)
3351 num_trbs++;
3352
3353 return num_trbs;
3354}
3355
3356static inline unsigned int count_trbs_needed(struct urb *urb)
3357{
3358 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3359}
3360
3361static unsigned int count_sg_trbs_needed(struct urb *urb)
3362{
3363 struct scatterlist *sg;
3364 unsigned int i, len, full_len, num_trbs = 0;
3365
3366 full_len = urb->transfer_buffer_length;
3367
3368 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3369 len = sg_dma_len(sg);
3370 num_trbs += count_trbs(sg_dma_address(sg), len);
3371 len = min_t(unsigned int, len, full_len);
3372 full_len -= len;
3373 if (full_len == 0)
3374 break;
3375 }
3376
3377 return num_trbs;
3378}
3379
3380static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3381{
3382 u64 addr, len;
3383
3384 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3385 len = urb->iso_frame_desc[i].length;
3386
3387 return count_trbs(addr, len);
3388}
3389
3390static void check_trb_math(struct urb *urb, int running_total)
3391{
3392 if (unlikely(running_total != urb->transfer_buffer_length))
3393 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3394 "queued %#x (%d), asked for %#x (%d)\n",
3395 __func__,
3396 urb->ep->desc.bEndpointAddress,
3397 running_total, running_total,
3398 urb->transfer_buffer_length,
3399 urb->transfer_buffer_length);
3400}
3401
3402static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3403 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3404 struct xhci_generic_trb *start_trb)
3405{
3406 /*
3407 * Pass all the TRBs to the hardware at once and make sure this write
3408 * isn't reordered.
3409 */
3410 wmb();
3411 if (start_cycle)
3412 start_trb->field[3] |= cpu_to_le32(start_cycle);
3413 else
3414 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3415 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3416}
3417
3418static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3419 struct xhci_ep_ctx *ep_ctx)
3420{
3421 int xhci_interval;
3422 int ep_interval;
3423
3424 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3425 ep_interval = urb->interval;
3426
3427 /* Convert to microframes */
3428 if (urb->dev->speed == USB_SPEED_LOW ||
3429 urb->dev->speed == USB_SPEED_FULL)
3430 ep_interval *= 8;
3431
3432 /* FIXME change this to a warning and a suggestion to use the new API
3433 * to set the polling interval (once the API is added).
3434 */
3435 if (xhci_interval != ep_interval) {
3436 dev_dbg_ratelimited(&urb->dev->dev,
3437 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3438 ep_interval, ep_interval == 1 ? "" : "s",
3439 xhci_interval, xhci_interval == 1 ? "" : "s");
3440 urb->interval = xhci_interval;
3441 /* Convert back to frames for LS/FS devices */
3442 if (urb->dev->speed == USB_SPEED_LOW ||
3443 urb->dev->speed == USB_SPEED_FULL)
3444 urb->interval /= 8;
3445 }
3446}
3447
3448/*
3449 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3450 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3451 * (comprised of sg list entries) can take several service intervals to
3452 * transmit.
3453 */
3454int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3455 struct urb *urb, int slot_id, unsigned int ep_index)
3456{
3457 struct xhci_ep_ctx *ep_ctx;
3458
3459 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3460 check_interval(xhci, urb, ep_ctx);
3461
3462 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3463}
3464
3465/*
3466 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3467 * packets remaining in the TD (*not* including this TRB).
3468 *
3469 * Total TD packet count = total_packet_count =
3470 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3471 *
3472 * Packets transferred up to and including this TRB = packets_transferred =
3473 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3474 *
3475 * TD size = total_packet_count - packets_transferred
3476 *
3477 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3478 * including this TRB, right shifted by 10
3479 *
3480 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3481 * This is taken care of in the TRB_TD_SIZE() macro
3482 *
3483 * The last TRB in a TD must have the TD size set to zero.
3484 */
3485static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3486 int trb_buff_len, unsigned int td_total_len,
3487 struct urb *urb, bool more_trbs_coming)
3488{
3489 u32 maxp, total_packet_count;
3490
3491 /* MTK xHCI 0.96 contains some features from 1.0 */
3492 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3493 return ((td_total_len - transferred) >> 10);
3494
3495 /* One TRB with a zero-length data packet. */
3496 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3497 trb_buff_len == td_total_len)
3498 return 0;
3499
3500 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3501 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3502 trb_buff_len = 0;
3503
3504 maxp = usb_endpoint_maxp(&urb->ep->desc);
3505 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3506
3507 /* Queueing functions don't count the current TRB into transferred */
3508 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3509}
3510
3511
3512static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3513 u32 *trb_buff_len, struct xhci_segment *seg)
3514{
3515 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
3516 unsigned int unalign;
3517 unsigned int max_pkt;
3518 u32 new_buff_len;
3519 size_t len;
3520
3521 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3522 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3523
3524 /* we got lucky, last normal TRB data on segment is packet aligned */
3525 if (unalign == 0)
3526 return 0;
3527
3528 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3529 unalign, *trb_buff_len);
3530
3531 /* is the last nornal TRB alignable by splitting it */
3532 if (*trb_buff_len > unalign) {
3533 *trb_buff_len -= unalign;
3534 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3535 return 0;
3536 }
3537
3538 /*
3539 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3540 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3541 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3542 */
3543 new_buff_len = max_pkt - (enqd_len % max_pkt);
3544
3545 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3546 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3547
3548 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3549 if (usb_urb_dir_out(urb)) {
3550 if (urb->num_sgs) {
3551 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3552 seg->bounce_buf, new_buff_len, enqd_len);
3553 if (len != new_buff_len)
3554 xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n",
3555 len, new_buff_len);
3556 } else {
3557 memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len);
3558 }
3559
3560 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3561 max_pkt, DMA_TO_DEVICE);
3562 } else {
3563 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3564 max_pkt, DMA_FROM_DEVICE);
3565 }
3566
3567 if (dma_mapping_error(dev, seg->bounce_dma)) {
3568 /* try without aligning. Some host controllers survive */
3569 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3570 return 0;
3571 }
3572 *trb_buff_len = new_buff_len;
3573 seg->bounce_len = new_buff_len;
3574 seg->bounce_offs = enqd_len;
3575
3576 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3577
3578 return 1;
3579}
3580
3581/* This is very similar to what ehci-q.c qtd_fill() does */
3582int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3583 struct urb *urb, int slot_id, unsigned int ep_index)
3584{
3585 struct xhci_ring *ring;
3586 struct urb_priv *urb_priv;
3587 struct xhci_td *td;
3588 struct xhci_generic_trb *start_trb;
3589 struct scatterlist *sg = NULL;
3590 bool more_trbs_coming = true;
3591 bool need_zero_pkt = false;
3592 bool first_trb = true;
3593 unsigned int num_trbs;
3594 unsigned int start_cycle, num_sgs = 0;
3595 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3596 int sent_len, ret;
3597 u32 field, length_field, remainder;
3598 u64 addr, send_addr;
3599
3600 ring = xhci_urb_to_transfer_ring(xhci, urb);
3601 if (!ring)
3602 return -EINVAL;
3603
3604 full_len = urb->transfer_buffer_length;
3605 /* If we have scatter/gather list, we use it. */
3606 if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) {
3607 num_sgs = urb->num_mapped_sgs;
3608 sg = urb->sg;
3609 addr = (u64) sg_dma_address(sg);
3610 block_len = sg_dma_len(sg);
3611 num_trbs = count_sg_trbs_needed(urb);
3612 } else {
3613 num_trbs = count_trbs_needed(urb);
3614 addr = (u64) urb->transfer_dma;
3615 block_len = full_len;
3616 }
3617 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3618 ep_index, urb->stream_id,
3619 num_trbs, urb, 0, mem_flags);
3620 if (unlikely(ret < 0))
3621 return ret;
3622
3623 urb_priv = urb->hcpriv;
3624
3625 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3626 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3627 need_zero_pkt = true;
3628
3629 td = &urb_priv->td[0];
3630
3631 /*
3632 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3633 * until we've finished creating all the other TRBs. The ring's cycle
3634 * state may change as we enqueue the other TRBs, so save it too.
3635 */
3636 start_trb = &ring->enqueue->generic;
3637 start_cycle = ring->cycle_state;
3638 send_addr = addr;
3639
3640 /* Queue the TRBs, even if they are zero-length */
3641 for (enqd_len = 0; first_trb || enqd_len < full_len;
3642 enqd_len += trb_buff_len) {
3643 field = TRB_TYPE(TRB_NORMAL);
3644
3645 /* TRB buffer should not cross 64KB boundaries */
3646 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3647 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3648
3649 if (enqd_len + trb_buff_len > full_len)
3650 trb_buff_len = full_len - enqd_len;
3651
3652 /* Don't change the cycle bit of the first TRB until later */
3653 if (first_trb) {
3654 first_trb = false;
3655 if (start_cycle == 0)
3656 field |= TRB_CYCLE;
3657 } else
3658 field |= ring->cycle_state;
3659
3660 /* Chain all the TRBs together; clear the chain bit in the last
3661 * TRB to indicate it's the last TRB in the chain.
3662 */
3663 if (enqd_len + trb_buff_len < full_len) {
3664 field |= TRB_CHAIN;
3665 if (trb_is_link(ring->enqueue + 1)) {
3666 if (xhci_align_td(xhci, urb, enqd_len,
3667 &trb_buff_len,
3668 ring->enq_seg)) {
3669 send_addr = ring->enq_seg->bounce_dma;
3670 /* assuming TD won't span 2 segs */
3671 td->bounce_seg = ring->enq_seg;
3672 }
3673 }
3674 }
3675 if (enqd_len + trb_buff_len >= full_len) {
3676 field &= ~TRB_CHAIN;
3677 field |= TRB_IOC;
3678 more_trbs_coming = false;
3679 td->last_trb = ring->enqueue;
3680 td->last_trb_seg = ring->enq_seg;
3681 if (xhci_urb_suitable_for_idt(urb)) {
3682 memcpy(&send_addr, urb->transfer_buffer,
3683 trb_buff_len);
3684 le64_to_cpus(&send_addr);
3685 field |= TRB_IDT;
3686 }
3687 }
3688
3689 /* Only set interrupt on short packet for IN endpoints */
3690 if (usb_urb_dir_in(urb))
3691 field |= TRB_ISP;
3692
3693 /* Set the TRB length, TD size, and interrupter fields. */
3694 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3695 full_len, urb, more_trbs_coming);
3696
3697 length_field = TRB_LEN(trb_buff_len) |
3698 TRB_TD_SIZE(remainder) |
3699 TRB_INTR_TARGET(0);
3700
3701 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3702 lower_32_bits(send_addr),
3703 upper_32_bits(send_addr),
3704 length_field,
3705 field);
3706 td->num_trbs++;
3707 addr += trb_buff_len;
3708 sent_len = trb_buff_len;
3709
3710 while (sg && sent_len >= block_len) {
3711 /* New sg entry */
3712 --num_sgs;
3713 sent_len -= block_len;
3714 sg = sg_next(sg);
3715 if (num_sgs != 0 && sg) {
3716 block_len = sg_dma_len(sg);
3717 addr = (u64) sg_dma_address(sg);
3718 addr += sent_len;
3719 }
3720 }
3721 block_len -= sent_len;
3722 send_addr = addr;
3723 }
3724
3725 if (need_zero_pkt) {
3726 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3727 ep_index, urb->stream_id,
3728 1, urb, 1, mem_flags);
3729 urb_priv->td[1].last_trb = ring->enqueue;
3730 urb_priv->td[1].last_trb_seg = ring->enq_seg;
3731 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3732 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3733 urb_priv->td[1].num_trbs++;
3734 }
3735
3736 check_trb_math(urb, enqd_len);
3737 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3738 start_cycle, start_trb);
3739 return 0;
3740}
3741
3742/* Caller must have locked xhci->lock */
3743int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3744 struct urb *urb, int slot_id, unsigned int ep_index)
3745{
3746 struct xhci_ring *ep_ring;
3747 int num_trbs;
3748 int ret;
3749 struct usb_ctrlrequest *setup;
3750 struct xhci_generic_trb *start_trb;
3751 int start_cycle;
3752 u32 field;
3753 struct urb_priv *urb_priv;
3754 struct xhci_td *td;
3755
3756 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3757 if (!ep_ring)
3758 return -EINVAL;
3759
3760 /*
3761 * Need to copy setup packet into setup TRB, so we can't use the setup
3762 * DMA address.
3763 */
3764 if (!urb->setup_packet)
3765 return -EINVAL;
3766
3767 /* 1 TRB for setup, 1 for status */
3768 num_trbs = 2;
3769 /*
3770 * Don't need to check if we need additional event data and normal TRBs,
3771 * since data in control transfers will never get bigger than 16MB
3772 * XXX: can we get a buffer that crosses 64KB boundaries?
3773 */
3774 if (urb->transfer_buffer_length > 0)
3775 num_trbs++;
3776 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3777 ep_index, urb->stream_id,
3778 num_trbs, urb, 0, mem_flags);
3779 if (ret < 0)
3780 return ret;
3781
3782 urb_priv = urb->hcpriv;
3783 td = &urb_priv->td[0];
3784 td->num_trbs = num_trbs;
3785
3786 /*
3787 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3788 * until we've finished creating all the other TRBs. The ring's cycle
3789 * state may change as we enqueue the other TRBs, so save it too.
3790 */
3791 start_trb = &ep_ring->enqueue->generic;
3792 start_cycle = ep_ring->cycle_state;
3793
3794 /* Queue setup TRB - see section 6.4.1.2.1 */
3795 /* FIXME better way to translate setup_packet into two u32 fields? */
3796 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3797 field = 0;
3798 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3799 if (start_cycle == 0)
3800 field |= 0x1;
3801
3802 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3803 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3804 if (urb->transfer_buffer_length > 0) {
3805 if (setup->bRequestType & USB_DIR_IN)
3806 field |= TRB_TX_TYPE(TRB_DATA_IN);
3807 else
3808 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3809 }
3810 }
3811
3812 queue_trb(xhci, ep_ring, true,
3813 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3814 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3815 TRB_LEN(8) | TRB_INTR_TARGET(0),
3816 /* Immediate data in pointer */
3817 field);
3818
3819 /* If there's data, queue data TRBs */
3820 /* Only set interrupt on short packet for IN endpoints */
3821 if (usb_urb_dir_in(urb))
3822 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3823 else
3824 field = TRB_TYPE(TRB_DATA);
3825
3826 if (urb->transfer_buffer_length > 0) {
3827 u32 length_field, remainder;
3828 u64 addr;
3829
3830 if (xhci_urb_suitable_for_idt(urb)) {
3831 memcpy(&addr, urb->transfer_buffer,
3832 urb->transfer_buffer_length);
3833 le64_to_cpus(&addr);
3834 field |= TRB_IDT;
3835 } else {
3836 addr = (u64) urb->transfer_dma;
3837 }
3838
3839 remainder = xhci_td_remainder(xhci, 0,
3840 urb->transfer_buffer_length,
3841 urb->transfer_buffer_length,
3842 urb, 1);
3843 length_field = TRB_LEN(urb->transfer_buffer_length) |
3844 TRB_TD_SIZE(remainder) |
3845 TRB_INTR_TARGET(0);
3846 if (setup->bRequestType & USB_DIR_IN)
3847 field |= TRB_DIR_IN;
3848 queue_trb(xhci, ep_ring, true,
3849 lower_32_bits(addr),
3850 upper_32_bits(addr),
3851 length_field,
3852 field | ep_ring->cycle_state);
3853 }
3854
3855 /* Save the DMA address of the last TRB in the TD */
3856 td->last_trb = ep_ring->enqueue;
3857 td->last_trb_seg = ep_ring->enq_seg;
3858
3859 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3860 /* If the device sent data, the status stage is an OUT transfer */
3861 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3862 field = 0;
3863 else
3864 field = TRB_DIR_IN;
3865 queue_trb(xhci, ep_ring, false,
3866 0,
3867 0,
3868 TRB_INTR_TARGET(0),
3869 /* Event on completion */
3870 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3871
3872 giveback_first_trb(xhci, slot_id, ep_index, 0,
3873 start_cycle, start_trb);
3874 return 0;
3875}
3876
3877/*
3878 * The transfer burst count field of the isochronous TRB defines the number of
3879 * bursts that are required to move all packets in this TD. Only SuperSpeed
3880 * devices can burst up to bMaxBurst number of packets per service interval.
3881 * This field is zero based, meaning a value of zero in the field means one
3882 * burst. Basically, for everything but SuperSpeed devices, this field will be
3883 * zero. Only xHCI 1.0 host controllers support this field.
3884 */
3885static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3886 struct urb *urb, unsigned int total_packet_count)
3887{
3888 unsigned int max_burst;
3889
3890 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3891 return 0;
3892
3893 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3894 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3895}
3896
3897/*
3898 * Returns the number of packets in the last "burst" of packets. This field is
3899 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3900 * the last burst packet count is equal to the total number of packets in the
3901 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3902 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3903 * contain 1 to (bMaxBurst + 1) packets.
3904 */
3905static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3906 struct urb *urb, unsigned int total_packet_count)
3907{
3908 unsigned int max_burst;
3909 unsigned int residue;
3910
3911 if (xhci->hci_version < 0x100)
3912 return 0;
3913
3914 if (urb->dev->speed >= USB_SPEED_SUPER) {
3915 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3916 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3917 residue = total_packet_count % (max_burst + 1);
3918 /* If residue is zero, the last burst contains (max_burst + 1)
3919 * number of packets, but the TLBPC field is zero-based.
3920 */
3921 if (residue == 0)
3922 return max_burst;
3923 return residue - 1;
3924 }
3925 if (total_packet_count == 0)
3926 return 0;
3927 return total_packet_count - 1;
3928}
3929
3930/*
3931 * Calculates Frame ID field of the isochronous TRB identifies the
3932 * target frame that the Interval associated with this Isochronous
3933 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3934 *
3935 * Returns actual frame id on success, negative value on error.
3936 */
3937static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3938 struct urb *urb, int index)
3939{
3940 int start_frame, ist, ret = 0;
3941 int start_frame_id, end_frame_id, current_frame_id;
3942
3943 if (urb->dev->speed == USB_SPEED_LOW ||
3944 urb->dev->speed == USB_SPEED_FULL)
3945 start_frame = urb->start_frame + index * urb->interval;
3946 else
3947 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3948
3949 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3950 *
3951 * If bit [3] of IST is cleared to '0', software can add a TRB no
3952 * later than IST[2:0] Microframes before that TRB is scheduled to
3953 * be executed.
3954 * If bit [3] of IST is set to '1', software can add a TRB no later
3955 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3956 */
3957 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3958 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3959 ist <<= 3;
3960
3961 /* Software shall not schedule an Isoch TD with a Frame ID value that
3962 * is less than the Start Frame ID or greater than the End Frame ID,
3963 * where:
3964 *
3965 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3966 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3967 *
3968 * Both the End Frame ID and Start Frame ID values are calculated
3969 * in microframes. When software determines the valid Frame ID value;
3970 * The End Frame ID value should be rounded down to the nearest Frame
3971 * boundary, and the Start Frame ID value should be rounded up to the
3972 * nearest Frame boundary.
3973 */
3974 current_frame_id = readl(&xhci->run_regs->microframe_index);
3975 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3976 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3977
3978 start_frame &= 0x7ff;
3979 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3980 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3981
3982 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3983 __func__, index, readl(&xhci->run_regs->microframe_index),
3984 start_frame_id, end_frame_id, start_frame);
3985
3986 if (start_frame_id < end_frame_id) {
3987 if (start_frame > end_frame_id ||
3988 start_frame < start_frame_id)
3989 ret = -EINVAL;
3990 } else if (start_frame_id > end_frame_id) {
3991 if ((start_frame > end_frame_id &&
3992 start_frame < start_frame_id))
3993 ret = -EINVAL;
3994 } else {
3995 ret = -EINVAL;
3996 }
3997
3998 if (index == 0) {
3999 if (ret == -EINVAL || start_frame == start_frame_id) {
4000 start_frame = start_frame_id + 1;
4001 if (urb->dev->speed == USB_SPEED_LOW ||
4002 urb->dev->speed == USB_SPEED_FULL)
4003 urb->start_frame = start_frame;
4004 else
4005 urb->start_frame = start_frame << 3;
4006 ret = 0;
4007 }
4008 }
4009
4010 if (ret) {
4011 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
4012 start_frame, current_frame_id, index,
4013 start_frame_id, end_frame_id);
4014 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
4015 return ret;
4016 }
4017
4018 return start_frame;
4019}
4020
4021/* Check if we should generate event interrupt for a TD in an isoc URB */
4022static bool trb_block_event_intr(struct xhci_hcd *xhci, int num_tds, int i)
4023{
4024 if (xhci->hci_version < 0x100)
4025 return false;
4026 /* always generate an event interrupt for the last TD */
4027 if (i == num_tds - 1)
4028 return false;
4029 /*
4030 * If AVOID_BEI is set the host handles full event rings poorly,
4031 * generate an event at least every 8th TD to clear the event ring
4032 */
4033 if (i && xhci->quirks & XHCI_AVOID_BEI)
4034 return !!(i % xhci->isoc_bei_interval);
4035
4036 return true;
4037}
4038
4039/* This is for isoc transfer */
4040static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
4041 struct urb *urb, int slot_id, unsigned int ep_index)
4042{
4043 struct xhci_ring *ep_ring;
4044 struct urb_priv *urb_priv;
4045 struct xhci_td *td;
4046 int num_tds, trbs_per_td;
4047 struct xhci_generic_trb *start_trb;
4048 bool first_trb;
4049 int start_cycle;
4050 u32 field, length_field;
4051 int running_total, trb_buff_len, td_len, td_remain_len, ret;
4052 u64 start_addr, addr;
4053 int i, j;
4054 bool more_trbs_coming;
4055 struct xhci_virt_ep *xep;
4056 int frame_id;
4057
4058 xep = &xhci->devs[slot_id]->eps[ep_index];
4059 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
4060
4061 num_tds = urb->number_of_packets;
4062 if (num_tds < 1) {
4063 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
4064 return -EINVAL;
4065 }
4066 start_addr = (u64) urb->transfer_dma;
4067 start_trb = &ep_ring->enqueue->generic;
4068 start_cycle = ep_ring->cycle_state;
4069
4070 urb_priv = urb->hcpriv;
4071 /* Queue the TRBs for each TD, even if they are zero-length */
4072 for (i = 0; i < num_tds; i++) {
4073 unsigned int total_pkt_count, max_pkt;
4074 unsigned int burst_count, last_burst_pkt_count;
4075 u32 sia_frame_id;
4076
4077 first_trb = true;
4078 running_total = 0;
4079 addr = start_addr + urb->iso_frame_desc[i].offset;
4080 td_len = urb->iso_frame_desc[i].length;
4081 td_remain_len = td_len;
4082 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
4083 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
4084
4085 /* A zero-length transfer still involves at least one packet. */
4086 if (total_pkt_count == 0)
4087 total_pkt_count++;
4088 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
4089 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
4090 urb, total_pkt_count);
4091
4092 trbs_per_td = count_isoc_trbs_needed(urb, i);
4093
4094 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
4095 urb->stream_id, trbs_per_td, urb, i, mem_flags);
4096 if (ret < 0) {
4097 if (i == 0)
4098 return ret;
4099 goto cleanup;
4100 }
4101 td = &urb_priv->td[i];
4102 td->num_trbs = trbs_per_td;
4103 /* use SIA as default, if frame id is used overwrite it */
4104 sia_frame_id = TRB_SIA;
4105 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
4106 HCC_CFC(xhci->hcc_params)) {
4107 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
4108 if (frame_id >= 0)
4109 sia_frame_id = TRB_FRAME_ID(frame_id);
4110 }
4111 /*
4112 * Set isoc specific data for the first TRB in a TD.
4113 * Prevent HW from getting the TRBs by keeping the cycle state
4114 * inverted in the first TDs isoc TRB.
4115 */
4116 field = TRB_TYPE(TRB_ISOC) |
4117 TRB_TLBPC(last_burst_pkt_count) |
4118 sia_frame_id |
4119 (i ? ep_ring->cycle_state : !start_cycle);
4120
4121 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
4122 if (!xep->use_extended_tbc)
4123 field |= TRB_TBC(burst_count);
4124
4125 /* fill the rest of the TRB fields, and remaining normal TRBs */
4126 for (j = 0; j < trbs_per_td; j++) {
4127 u32 remainder = 0;
4128
4129 /* only first TRB is isoc, overwrite otherwise */
4130 if (!first_trb)
4131 field = TRB_TYPE(TRB_NORMAL) |
4132 ep_ring->cycle_state;
4133
4134 /* Only set interrupt on short packet for IN EPs */
4135 if (usb_urb_dir_in(urb))
4136 field |= TRB_ISP;
4137
4138 /* Set the chain bit for all except the last TRB */
4139 if (j < trbs_per_td - 1) {
4140 more_trbs_coming = true;
4141 field |= TRB_CHAIN;
4142 } else {
4143 more_trbs_coming = false;
4144 td->last_trb = ep_ring->enqueue;
4145 td->last_trb_seg = ep_ring->enq_seg;
4146 field |= TRB_IOC;
4147 if (trb_block_event_intr(xhci, num_tds, i))
4148 field |= TRB_BEI;
4149 }
4150 /* Calculate TRB length */
4151 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
4152 if (trb_buff_len > td_remain_len)
4153 trb_buff_len = td_remain_len;
4154
4155 /* Set the TRB length, TD size, & interrupter fields. */
4156 remainder = xhci_td_remainder(xhci, running_total,
4157 trb_buff_len, td_len,
4158 urb, more_trbs_coming);
4159
4160 length_field = TRB_LEN(trb_buff_len) |
4161 TRB_INTR_TARGET(0);
4162
4163 /* xhci 1.1 with ETE uses TD Size field for TBC */
4164 if (first_trb && xep->use_extended_tbc)
4165 length_field |= TRB_TD_SIZE_TBC(burst_count);
4166 else
4167 length_field |= TRB_TD_SIZE(remainder);
4168 first_trb = false;
4169
4170 queue_trb(xhci, ep_ring, more_trbs_coming,
4171 lower_32_bits(addr),
4172 upper_32_bits(addr),
4173 length_field,
4174 field);
4175 running_total += trb_buff_len;
4176
4177 addr += trb_buff_len;
4178 td_remain_len -= trb_buff_len;
4179 }
4180
4181 /* Check TD length */
4182 if (running_total != td_len) {
4183 xhci_err(xhci, "ISOC TD length unmatch\n");
4184 ret = -EINVAL;
4185 goto cleanup;
4186 }
4187 }
4188
4189 /* store the next frame id */
4190 if (HCC_CFC(xhci->hcc_params))
4191 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
4192
4193 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
4194 if (xhci->quirks & XHCI_AMD_PLL_FIX)
4195 usb_amd_quirk_pll_disable();
4196 }
4197 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
4198
4199 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
4200 start_cycle, start_trb);
4201 return 0;
4202cleanup:
4203 /* Clean up a partially enqueued isoc transfer. */
4204
4205 for (i--; i >= 0; i--)
4206 list_del_init(&urb_priv->td[i].td_list);
4207
4208 /* Use the first TD as a temporary variable to turn the TDs we've queued
4209 * into No-ops with a software-owned cycle bit. That way the hardware
4210 * won't accidentally start executing bogus TDs when we partially
4211 * overwrite them. td->first_trb and td->start_seg are already set.
4212 */
4213 urb_priv->td[0].last_trb = ep_ring->enqueue;
4214 /* Every TRB except the first & last will have its cycle bit flipped. */
4215 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
4216
4217 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
4218 ep_ring->enqueue = urb_priv->td[0].first_trb;
4219 ep_ring->enq_seg = urb_priv->td[0].start_seg;
4220 ep_ring->cycle_state = start_cycle;
4221 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
4222 return ret;
4223}
4224
4225/*
4226 * Check transfer ring to guarantee there is enough room for the urb.
4227 * Update ISO URB start_frame and interval.
4228 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
4229 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
4230 * Contiguous Frame ID is not supported by HC.
4231 */
4232int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
4233 struct urb *urb, int slot_id, unsigned int ep_index)
4234{
4235 struct xhci_virt_device *xdev;
4236 struct xhci_ring *ep_ring;
4237 struct xhci_ep_ctx *ep_ctx;
4238 int start_frame;
4239 int num_tds, num_trbs, i;
4240 int ret;
4241 struct xhci_virt_ep *xep;
4242 int ist;
4243
4244 xdev = xhci->devs[slot_id];
4245 xep = &xhci->devs[slot_id]->eps[ep_index];
4246 ep_ring = xdev->eps[ep_index].ring;
4247 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
4248
4249 num_trbs = 0;
4250 num_tds = urb->number_of_packets;
4251 for (i = 0; i < num_tds; i++)
4252 num_trbs += count_isoc_trbs_needed(urb, i);
4253
4254 /* Check the ring to guarantee there is enough room for the whole urb.
4255 * Do not insert any td of the urb to the ring if the check failed.
4256 */
4257 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
4258 num_trbs, mem_flags);
4259 if (ret)
4260 return ret;
4261
4262 /*
4263 * Check interval value. This should be done before we start to
4264 * calculate the start frame value.
4265 */
4266 check_interval(xhci, urb, ep_ctx);
4267
4268 /* Calculate the start frame and put it in urb->start_frame. */
4269 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
4270 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
4271 urb->start_frame = xep->next_frame_id;
4272 goto skip_start_over;
4273 }
4274 }
4275
4276 start_frame = readl(&xhci->run_regs->microframe_index);
4277 start_frame &= 0x3fff;
4278 /*
4279 * Round up to the next frame and consider the time before trb really
4280 * gets scheduled by hardare.
4281 */
4282 ist = HCS_IST(xhci->hcs_params2) & 0x7;
4283 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
4284 ist <<= 3;
4285 start_frame += ist + XHCI_CFC_DELAY;
4286 start_frame = roundup(start_frame, 8);
4287
4288 /*
4289 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4290 * is greate than 8 microframes.
4291 */
4292 if (urb->dev->speed == USB_SPEED_LOW ||
4293 urb->dev->speed == USB_SPEED_FULL) {
4294 start_frame = roundup(start_frame, urb->interval << 3);
4295 urb->start_frame = start_frame >> 3;
4296 } else {
4297 start_frame = roundup(start_frame, urb->interval);
4298 urb->start_frame = start_frame;
4299 }
4300
4301skip_start_over:
4302
4303 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4304}
4305
4306/**** Command Ring Operations ****/
4307
4308/* Generic function for queueing a command TRB on the command ring.
4309 * Check to make sure there's room on the command ring for one command TRB.
4310 * Also check that there's room reserved for commands that must not fail.
4311 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4312 * then only check for the number of reserved spots.
4313 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4314 * because the command event handler may want to resubmit a failed command.
4315 */
4316static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4317 u32 field1, u32 field2,
4318 u32 field3, u32 field4, bool command_must_succeed)
4319{
4320 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4321 int ret;
4322
4323 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
4324 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4325 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
4326 return -ESHUTDOWN;
4327 }
4328
4329 if (!command_must_succeed)
4330 reserved_trbs++;
4331
4332 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4333 reserved_trbs, GFP_ATOMIC);
4334 if (ret < 0) {
4335 xhci_err(xhci, "ERR: No room for command on command ring\n");
4336 if (command_must_succeed)
4337 xhci_err(xhci, "ERR: Reserved TRB counting for "
4338 "unfailable commands failed.\n");
4339 return ret;
4340 }
4341
4342 cmd->command_trb = xhci->cmd_ring->enqueue;
4343
4344 /* if there are no other commands queued we start the timeout timer */
4345 if (list_empty(&xhci->cmd_list)) {
4346 xhci->current_cmd = cmd;
4347 xhci_mod_cmd_timer(xhci);
4348 }
4349
4350 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4351
4352 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4353 field4 | xhci->cmd_ring->cycle_state);
4354 return 0;
4355}
4356
4357/* Queue a slot enable or disable request on the command ring */
4358int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4359 u32 trb_type, u32 slot_id)
4360{
4361 return queue_command(xhci, cmd, 0, 0, 0,
4362 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4363}
4364
4365/* Queue an address device command TRB */
4366int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4367 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4368{
4369 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4370 upper_32_bits(in_ctx_ptr), 0,
4371 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4372 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4373}
4374
4375int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4376 u32 field1, u32 field2, u32 field3, u32 field4)
4377{
4378 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4379}
4380
4381/* Queue a reset device command TRB */
4382int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4383 u32 slot_id)
4384{
4385 return queue_command(xhci, cmd, 0, 0, 0,
4386 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4387 false);
4388}
4389
4390/* Queue a configure endpoint command TRB */
4391int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4392 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4393 u32 slot_id, bool command_must_succeed)
4394{
4395 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4396 upper_32_bits(in_ctx_ptr), 0,
4397 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4398 command_must_succeed);
4399}
4400
4401/* Queue an evaluate context command TRB */
4402int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4403 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4404{
4405 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4406 upper_32_bits(in_ctx_ptr), 0,
4407 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4408 command_must_succeed);
4409}
4410
4411/*
4412 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4413 * activity on an endpoint that is about to be suspended.
4414 */
4415int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4416 int slot_id, unsigned int ep_index, int suspend)
4417{
4418 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4419 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4420 u32 type = TRB_TYPE(TRB_STOP_RING);
4421 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4422
4423 return queue_command(xhci, cmd, 0, 0, 0,
4424 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4425}
4426
4427int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4428 int slot_id, unsigned int ep_index,
4429 enum xhci_ep_reset_type reset_type)
4430{
4431 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4432 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4433 u32 type = TRB_TYPE(TRB_RESET_EP);
4434
4435 if (reset_type == EP_SOFT_RESET)
4436 type |= TRB_TSP;
4437
4438 return queue_command(xhci, cmd, 0, 0, 0,
4439 trb_slot_id | trb_ep_index | type, false);
4440}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * xHCI host controller driver
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11/*
12 * Ring initialization rules:
13 * 1. Each segment is initialized to zero, except for link TRBs.
14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
15 * Consumer Cycle State (CCS), depending on ring function.
16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
17 *
18 * Ring behavior rules:
19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
20 * least one free TRB in the ring. This is useful if you want to turn that
21 * into a link TRB and expand the ring.
22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
23 * link TRB, then load the pointer with the address in the link TRB. If the
24 * link TRB had its toggle bit set, you may need to update the ring cycle
25 * state (see cycle bit rules). You may have to do this multiple times
26 * until you reach a non-link TRB.
27 * 3. A ring is full if enqueue++ (for the definition of increment above)
28 * equals the dequeue pointer.
29 *
30 * Cycle bit rules:
31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
32 * in a link TRB, it must toggle the ring cycle state.
33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
34 * in a link TRB, it must toggle the ring cycle state.
35 *
36 * Producer rules:
37 * 1. Check if ring is full before you enqueue.
38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
39 * Update enqueue pointer between each write (which may update the ring
40 * cycle state).
41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
42 * and endpoint rings. If HC is the producer for the event ring,
43 * and it generates an interrupt according to interrupt modulation rules.
44 *
45 * Consumer rules:
46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
47 * the TRB is owned by the consumer.
48 * 2. Update dequeue pointer (which may update the ring cycle state) and
49 * continue processing TRBs until you reach a TRB which is not owned by you.
50 * 3. Notify the producer. SW is the consumer for the event ring, and it
51 * updates event ring dequeue pointer. HC is the consumer for the command and
52 * endpoint rings; it generates events on the event ring for these.
53 */
54
55#include <linux/scatterlist.h>
56#include <linux/slab.h>
57#include <linux/dma-mapping.h>
58#include "xhci.h"
59#include "xhci-trace.h"
60
61static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
62 u32 field1, u32 field2,
63 u32 field3, u32 field4, bool command_must_succeed);
64
65/*
66 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
67 * address of the TRB.
68 */
69dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
70 union xhci_trb *trb)
71{
72 unsigned long segment_offset;
73
74 if (!seg || !trb || trb < seg->trbs)
75 return 0;
76 /* offset in TRBs */
77 segment_offset = trb - seg->trbs;
78 if (segment_offset >= TRBS_PER_SEGMENT)
79 return 0;
80 return seg->dma + (segment_offset * sizeof(*trb));
81}
82
83static bool trb_is_noop(union xhci_trb *trb)
84{
85 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
86}
87
88static bool trb_is_link(union xhci_trb *trb)
89{
90 return TRB_TYPE_LINK_LE32(trb->link.control);
91}
92
93static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
94{
95 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
96}
97
98static bool last_trb_on_ring(struct xhci_ring *ring,
99 struct xhci_segment *seg, union xhci_trb *trb)
100{
101 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
102}
103
104static bool link_trb_toggles_cycle(union xhci_trb *trb)
105{
106 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
107}
108
109static bool last_td_in_urb(struct xhci_td *td)
110{
111 struct urb_priv *urb_priv = td->urb->hcpriv;
112
113 return urb_priv->num_tds_done == urb_priv->num_tds;
114}
115
116static void inc_td_cnt(struct urb *urb)
117{
118 struct urb_priv *urb_priv = urb->hcpriv;
119
120 urb_priv->num_tds_done++;
121}
122
123static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
124{
125 if (trb_is_link(trb)) {
126 /* unchain chained link TRBs */
127 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
128 } else {
129 trb->generic.field[0] = 0;
130 trb->generic.field[1] = 0;
131 trb->generic.field[2] = 0;
132 /* Preserve only the cycle bit of this TRB */
133 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
134 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
135 }
136}
137
138/* Updates trb to point to the next TRB in the ring, and updates seg if the next
139 * TRB is in a new segment. This does not skip over link TRBs, and it does not
140 * effect the ring dequeue or enqueue pointers.
141 */
142static void next_trb(struct xhci_hcd *xhci,
143 struct xhci_ring *ring,
144 struct xhci_segment **seg,
145 union xhci_trb **trb)
146{
147 if (trb_is_link(*trb)) {
148 *seg = (*seg)->next;
149 *trb = ((*seg)->trbs);
150 } else {
151 (*trb)++;
152 }
153}
154
155/*
156 * See Cycle bit rules. SW is the consumer for the event ring only.
157 */
158void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
159{
160 unsigned int link_trb_count = 0;
161
162 /* event ring doesn't have link trbs, check for last trb */
163 if (ring->type == TYPE_EVENT) {
164 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
165 ring->dequeue++;
166 goto out;
167 }
168 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
169 ring->cycle_state ^= 1;
170 ring->deq_seg = ring->deq_seg->next;
171 ring->dequeue = ring->deq_seg->trbs;
172 goto out;
173 }
174
175 /* All other rings have link trbs */
176 if (!trb_is_link(ring->dequeue)) {
177 if (last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
178 xhci_warn(xhci, "Missing link TRB at end of segment\n");
179 } else {
180 ring->dequeue++;
181 ring->num_trbs_free++;
182 }
183 }
184
185 while (trb_is_link(ring->dequeue)) {
186 ring->deq_seg = ring->deq_seg->next;
187 ring->dequeue = ring->deq_seg->trbs;
188
189 if (link_trb_count++ > ring->num_segs) {
190 xhci_warn(xhci, "Ring is an endless link TRB loop\n");
191 break;
192 }
193 }
194out:
195 trace_xhci_inc_deq(ring);
196
197 return;
198}
199
200/*
201 * See Cycle bit rules. SW is the consumer for the event ring only.
202 *
203 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
204 * chain bit is set), then set the chain bit in all the following link TRBs.
205 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
206 * have their chain bit cleared (so that each Link TRB is a separate TD).
207 *
208 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
209 * set, but other sections talk about dealing with the chain bit set. This was
210 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
211 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
212 *
213 * @more_trbs_coming: Will you enqueue more TRBs before calling
214 * prepare_transfer()?
215 */
216static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
217 bool more_trbs_coming)
218{
219 u32 chain;
220 union xhci_trb *next;
221 unsigned int link_trb_count = 0;
222
223 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
224 /* If this is not event ring, there is one less usable TRB */
225 if (!trb_is_link(ring->enqueue))
226 ring->num_trbs_free--;
227
228 if (last_trb_on_seg(ring->enq_seg, ring->enqueue)) {
229 xhci_err(xhci, "Tried to move enqueue past ring segment\n");
230 return;
231 }
232
233 next = ++(ring->enqueue);
234
235 /* Update the dequeue pointer further if that was a link TRB */
236 while (trb_is_link(next)) {
237
238 /*
239 * If the caller doesn't plan on enqueueing more TDs before
240 * ringing the doorbell, then we don't want to give the link TRB
241 * to the hardware just yet. We'll give the link TRB back in
242 * prepare_ring() just before we enqueue the TD at the top of
243 * the ring.
244 */
245 if (!chain && !more_trbs_coming)
246 break;
247
248 /* If we're not dealing with 0.95 hardware or isoc rings on
249 * AMD 0.96 host, carry over the chain bit of the previous TRB
250 * (which may mean the chain bit is cleared).
251 */
252 if (!(ring->type == TYPE_ISOC &&
253 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
254 !xhci_link_trb_quirk(xhci)) {
255 next->link.control &= cpu_to_le32(~TRB_CHAIN);
256 next->link.control |= cpu_to_le32(chain);
257 }
258 /* Give this link TRB to the hardware */
259 wmb();
260 next->link.control ^= cpu_to_le32(TRB_CYCLE);
261
262 /* Toggle the cycle bit after the last ring segment. */
263 if (link_trb_toggles_cycle(next))
264 ring->cycle_state ^= 1;
265
266 ring->enq_seg = ring->enq_seg->next;
267 ring->enqueue = ring->enq_seg->trbs;
268 next = ring->enqueue;
269
270 if (link_trb_count++ > ring->num_segs) {
271 xhci_warn(xhci, "%s: Ring link TRB loop\n", __func__);
272 break;
273 }
274 }
275
276 trace_xhci_inc_enq(ring);
277}
278
279/*
280 * Check to see if there's room to enqueue num_trbs on the ring and make sure
281 * enqueue pointer will not advance into dequeue segment. See rules above.
282 */
283static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
284 unsigned int num_trbs)
285{
286 int num_trbs_in_deq_seg;
287
288 if (ring->num_trbs_free < num_trbs)
289 return 0;
290
291 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
292 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
293 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
294 return 0;
295 }
296
297 return 1;
298}
299
300/* Ring the host controller doorbell after placing a command on the ring */
301void xhci_ring_cmd_db(struct xhci_hcd *xhci)
302{
303 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
304 return;
305
306 xhci_dbg(xhci, "// Ding dong!\n");
307
308 trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST);
309
310 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
311 /* Flush PCI posted writes */
312 readl(&xhci->dba->doorbell[0]);
313}
314
315static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
316{
317 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
318}
319
320static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
321{
322 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
323 cmd_list);
324}
325
326/*
327 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
328 * If there are other commands waiting then restart the ring and kick the timer.
329 * This must be called with command ring stopped and xhci->lock held.
330 */
331static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
332 struct xhci_command *cur_cmd)
333{
334 struct xhci_command *i_cmd;
335
336 /* Turn all aborted commands in list to no-ops, then restart */
337 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
338
339 if (i_cmd->status != COMP_COMMAND_ABORTED)
340 continue;
341
342 i_cmd->status = COMP_COMMAND_RING_STOPPED;
343
344 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
345 i_cmd->command_trb);
346
347 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
348
349 /*
350 * caller waiting for completion is called when command
351 * completion event is received for these no-op commands
352 */
353 }
354
355 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
356
357 /* ring command ring doorbell to restart the command ring */
358 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
359 !(xhci->xhc_state & XHCI_STATE_DYING)) {
360 xhci->current_cmd = cur_cmd;
361 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
362 xhci_ring_cmd_db(xhci);
363 }
364}
365
366/* Must be called with xhci->lock held, releases and aquires lock back */
367static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
368{
369 struct xhci_segment *new_seg = xhci->cmd_ring->deq_seg;
370 union xhci_trb *new_deq = xhci->cmd_ring->dequeue;
371 u64 crcr;
372 int ret;
373
374 xhci_dbg(xhci, "Abort command ring\n");
375
376 reinit_completion(&xhci->cmd_ring_stop_completion);
377
378 /*
379 * The control bits like command stop, abort are located in lower
380 * dword of the command ring control register.
381 * Some controllers require all 64 bits to be written to abort the ring.
382 * Make sure the upper dword is valid, pointing to the next command,
383 * avoiding corrupting the command ring pointer in case the command ring
384 * is stopped by the time the upper dword is written.
385 */
386 next_trb(xhci, NULL, &new_seg, &new_deq);
387 if (trb_is_link(new_deq))
388 next_trb(xhci, NULL, &new_seg, &new_deq);
389
390 crcr = xhci_trb_virt_to_dma(new_seg, new_deq);
391 xhci_write_64(xhci, crcr | CMD_RING_ABORT, &xhci->op_regs->cmd_ring);
392
393 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
394 * completion of the Command Abort operation. If CRR is not negated in 5
395 * seconds then driver handles it as if host died (-ENODEV).
396 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
397 * and try to recover a -ETIMEDOUT with a host controller reset.
398 */
399 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
400 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
401 if (ret < 0) {
402 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
403 xhci_halt(xhci);
404 xhci_hc_died(xhci);
405 return ret;
406 }
407 /*
408 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
409 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
410 * but the completion event in never sent. Wait 2 secs (arbitrary
411 * number) to handle those cases after negation of CMD_RING_RUNNING.
412 */
413 spin_unlock_irqrestore(&xhci->lock, flags);
414 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
415 msecs_to_jiffies(2000));
416 spin_lock_irqsave(&xhci->lock, flags);
417 if (!ret) {
418 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
419 xhci_cleanup_command_queue(xhci);
420 } else {
421 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
422 }
423 return 0;
424}
425
426void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
427 unsigned int slot_id,
428 unsigned int ep_index,
429 unsigned int stream_id)
430{
431 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
432 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
433 unsigned int ep_state = ep->ep_state;
434
435 /* Don't ring the doorbell for this endpoint if there are pending
436 * cancellations because we don't want to interrupt processing.
437 * We don't want to restart any stream rings if there's a set dequeue
438 * pointer command pending because the device can choose to start any
439 * stream once the endpoint is on the HW schedule.
440 */
441 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
442 (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT))
443 return;
444
445 trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id));
446
447 writel(DB_VALUE(ep_index, stream_id), db_addr);
448 /* flush the write */
449 readl(db_addr);
450}
451
452/* Ring the doorbell for any rings with pending URBs */
453static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
454 unsigned int slot_id,
455 unsigned int ep_index)
456{
457 unsigned int stream_id;
458 struct xhci_virt_ep *ep;
459
460 ep = &xhci->devs[slot_id]->eps[ep_index];
461
462 /* A ring has pending URBs if its TD list is not empty */
463 if (!(ep->ep_state & EP_HAS_STREAMS)) {
464 if (ep->ring && !(list_empty(&ep->ring->td_list)))
465 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
466 return;
467 }
468
469 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
470 stream_id++) {
471 struct xhci_stream_info *stream_info = ep->stream_info;
472 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
473 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
474 stream_id);
475 }
476}
477
478void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
479 unsigned int slot_id,
480 unsigned int ep_index)
481{
482 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
483}
484
485static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci,
486 unsigned int slot_id,
487 unsigned int ep_index)
488{
489 if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) {
490 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
491 return NULL;
492 }
493 if (ep_index >= EP_CTX_PER_DEV) {
494 xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index);
495 return NULL;
496 }
497 if (!xhci->devs[slot_id]) {
498 xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id);
499 return NULL;
500 }
501
502 return &xhci->devs[slot_id]->eps[ep_index];
503}
504
505static struct xhci_ring *xhci_virt_ep_to_ring(struct xhci_hcd *xhci,
506 struct xhci_virt_ep *ep,
507 unsigned int stream_id)
508{
509 /* common case, no streams */
510 if (!(ep->ep_state & EP_HAS_STREAMS))
511 return ep->ring;
512
513 if (!ep->stream_info)
514 return NULL;
515
516 if (stream_id == 0 || stream_id >= ep->stream_info->num_streams) {
517 xhci_warn(xhci, "Invalid stream_id %u request for slot_id %u ep_index %u\n",
518 stream_id, ep->vdev->slot_id, ep->ep_index);
519 return NULL;
520 }
521
522 return ep->stream_info->stream_rings[stream_id];
523}
524
525/* Get the right ring for the given slot_id, ep_index and stream_id.
526 * If the endpoint supports streams, boundary check the URB's stream ID.
527 * If the endpoint doesn't support streams, return the singular endpoint ring.
528 */
529struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
530 unsigned int slot_id, unsigned int ep_index,
531 unsigned int stream_id)
532{
533 struct xhci_virt_ep *ep;
534
535 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
536 if (!ep)
537 return NULL;
538
539 return xhci_virt_ep_to_ring(xhci, ep, stream_id);
540}
541
542
543/*
544 * Get the hw dequeue pointer xHC stopped on, either directly from the
545 * endpoint context, or if streams are in use from the stream context.
546 * The returned hw_dequeue contains the lowest four bits with cycle state
547 * and possbile stream context type.
548 */
549static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
550 unsigned int ep_index, unsigned int stream_id)
551{
552 struct xhci_ep_ctx *ep_ctx;
553 struct xhci_stream_ctx *st_ctx;
554 struct xhci_virt_ep *ep;
555
556 ep = &vdev->eps[ep_index];
557
558 if (ep->ep_state & EP_HAS_STREAMS) {
559 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
560 return le64_to_cpu(st_ctx->stream_ring);
561 }
562 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
563 return le64_to_cpu(ep_ctx->deq);
564}
565
566static int xhci_move_dequeue_past_td(struct xhci_hcd *xhci,
567 unsigned int slot_id, unsigned int ep_index,
568 unsigned int stream_id, struct xhci_td *td)
569{
570 struct xhci_virt_device *dev = xhci->devs[slot_id];
571 struct xhci_virt_ep *ep = &dev->eps[ep_index];
572 struct xhci_ring *ep_ring;
573 struct xhci_command *cmd;
574 struct xhci_segment *new_seg;
575 struct xhci_segment *halted_seg = NULL;
576 union xhci_trb *new_deq;
577 int new_cycle;
578 union xhci_trb *halted_trb;
579 int index = 0;
580 dma_addr_t addr;
581 u64 hw_dequeue;
582 bool cycle_found = false;
583 bool td_last_trb_found = false;
584 u32 trb_sct = 0;
585 int ret;
586
587 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
588 ep_index, stream_id);
589 if (!ep_ring) {
590 xhci_warn(xhci, "WARN can't find new dequeue, invalid stream ID %u\n",
591 stream_id);
592 return -ENODEV;
593 }
594 /*
595 * A cancelled TD can complete with a stall if HW cached the trb.
596 * In this case driver can't find td, but if the ring is empty we
597 * can move the dequeue pointer to the current enqueue position.
598 * We shouldn't hit this anymore as cached cancelled TRBs are given back
599 * after clearing the cache, but be on the safe side and keep it anyway
600 */
601 if (!td) {
602 if (list_empty(&ep_ring->td_list)) {
603 new_seg = ep_ring->enq_seg;
604 new_deq = ep_ring->enqueue;
605 new_cycle = ep_ring->cycle_state;
606 xhci_dbg(xhci, "ep ring empty, Set new dequeue = enqueue");
607 goto deq_found;
608 } else {
609 xhci_warn(xhci, "Can't find new dequeue state, missing td\n");
610 return -EINVAL;
611 }
612 }
613
614 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
615 new_seg = ep_ring->deq_seg;
616 new_deq = ep_ring->dequeue;
617
618 /*
619 * Quirk: xHC write-back of the DCS field in the hardware dequeue
620 * pointer is wrong - use the cycle state of the TRB pointed to by
621 * the dequeue pointer.
622 */
623 if (xhci->quirks & XHCI_EP_CTX_BROKEN_DCS &&
624 !(ep->ep_state & EP_HAS_STREAMS))
625 halted_seg = trb_in_td(xhci, td->start_seg,
626 td->first_trb, td->last_trb,
627 hw_dequeue & ~0xf, false);
628 if (halted_seg) {
629 index = ((dma_addr_t)(hw_dequeue & ~0xf) - halted_seg->dma) /
630 sizeof(*halted_trb);
631 halted_trb = &halted_seg->trbs[index];
632 new_cycle = halted_trb->generic.field[3] & 0x1;
633 xhci_dbg(xhci, "Endpoint DCS = %d TRB index = %d cycle = %d\n",
634 (u8)(hw_dequeue & 0x1), index, new_cycle);
635 } else {
636 new_cycle = hw_dequeue & 0x1;
637 }
638
639 /*
640 * We want to find the pointer, segment and cycle state of the new trb
641 * (the one after current TD's last_trb). We know the cycle state at
642 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
643 * found.
644 */
645 do {
646 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
647 == (dma_addr_t)(hw_dequeue & ~0xf)) {
648 cycle_found = true;
649 if (td_last_trb_found)
650 break;
651 }
652 if (new_deq == td->last_trb)
653 td_last_trb_found = true;
654
655 if (cycle_found && trb_is_link(new_deq) &&
656 link_trb_toggles_cycle(new_deq))
657 new_cycle ^= 0x1;
658
659 next_trb(xhci, ep_ring, &new_seg, &new_deq);
660
661 /* Search wrapped around, bail out */
662 if (new_deq == ep->ring->dequeue) {
663 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
664 return -EINVAL;
665 }
666
667 } while (!cycle_found || !td_last_trb_found);
668
669deq_found:
670
671 /* Don't update the ring cycle state for the producer (us). */
672 addr = xhci_trb_virt_to_dma(new_seg, new_deq);
673 if (addr == 0) {
674 xhci_warn(xhci, "Can't find dma of new dequeue ptr\n");
675 xhci_warn(xhci, "deq seg = %p, deq ptr = %p\n", new_seg, new_deq);
676 return -EINVAL;
677 }
678
679 if ((ep->ep_state & SET_DEQ_PENDING)) {
680 xhci_warn(xhci, "Set TR Deq already pending, don't submit for 0x%pad\n",
681 &addr);
682 return -EBUSY;
683 }
684
685 /* This function gets called from contexts where it cannot sleep */
686 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
687 if (!cmd) {
688 xhci_warn(xhci, "Can't alloc Set TR Deq cmd 0x%pad\n", &addr);
689 return -ENOMEM;
690 }
691
692 if (stream_id)
693 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
694 ret = queue_command(xhci, cmd,
695 lower_32_bits(addr) | trb_sct | new_cycle,
696 upper_32_bits(addr),
697 STREAM_ID_FOR_TRB(stream_id), SLOT_ID_FOR_TRB(slot_id) |
698 EP_ID_FOR_TRB(ep_index) | TRB_TYPE(TRB_SET_DEQ), false);
699 if (ret < 0) {
700 xhci_free_command(xhci, cmd);
701 return ret;
702 }
703 ep->queued_deq_seg = new_seg;
704 ep->queued_deq_ptr = new_deq;
705
706 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
707 "Set TR Deq ptr 0x%llx, cycle %u\n", addr, new_cycle);
708
709 /* Stop the TD queueing code from ringing the doorbell until
710 * this command completes. The HC won't set the dequeue pointer
711 * if the ring is running, and ringing the doorbell starts the
712 * ring running.
713 */
714 ep->ep_state |= SET_DEQ_PENDING;
715 xhci_ring_cmd_db(xhci);
716 return 0;
717}
718
719/* flip_cycle means flip the cycle bit of all but the first and last TRB.
720 * (The last TRB actually points to the ring enqueue pointer, which is not part
721 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
722 */
723static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
724 struct xhci_td *td, bool flip_cycle)
725{
726 struct xhci_segment *seg = td->start_seg;
727 union xhci_trb *trb = td->first_trb;
728
729 while (1) {
730 trb_to_noop(trb, TRB_TR_NOOP);
731
732 /* flip cycle if asked to */
733 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
734 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
735
736 if (trb == td->last_trb)
737 break;
738
739 next_trb(xhci, ep_ring, &seg, &trb);
740 }
741}
742
743/*
744 * Must be called with xhci->lock held in interrupt context,
745 * releases and re-acquires xhci->lock
746 */
747static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
748 struct xhci_td *cur_td, int status)
749{
750 struct urb *urb = cur_td->urb;
751 struct urb_priv *urb_priv = urb->hcpriv;
752 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
753
754 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
755 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
756 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
757 if (xhci->quirks & XHCI_AMD_PLL_FIX)
758 usb_amd_quirk_pll_enable();
759 }
760 }
761 xhci_urb_free_priv(urb_priv);
762 usb_hcd_unlink_urb_from_ep(hcd, urb);
763 trace_xhci_urb_giveback(urb);
764 usb_hcd_giveback_urb(hcd, urb, status);
765}
766
767static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
768 struct xhci_ring *ring, struct xhci_td *td)
769{
770 struct device *dev = xhci_to_hcd(xhci)->self.controller;
771 struct xhci_segment *seg = td->bounce_seg;
772 struct urb *urb = td->urb;
773 size_t len;
774
775 if (!ring || !seg || !urb)
776 return;
777
778 if (usb_urb_dir_out(urb)) {
779 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
780 DMA_TO_DEVICE);
781 return;
782 }
783
784 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
785 DMA_FROM_DEVICE);
786 /* for in tranfers we need to copy the data from bounce to sg */
787 if (urb->num_sgs) {
788 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
789 seg->bounce_len, seg->bounce_offs);
790 if (len != seg->bounce_len)
791 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
792 len, seg->bounce_len);
793 } else {
794 memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf,
795 seg->bounce_len);
796 }
797 seg->bounce_len = 0;
798 seg->bounce_offs = 0;
799}
800
801static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
802 struct xhci_ring *ep_ring, int status)
803{
804 struct urb *urb = NULL;
805
806 /* Clean up the endpoint's TD list */
807 urb = td->urb;
808
809 /* if a bounce buffer was used to align this td then unmap it */
810 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
811
812 /* Do one last check of the actual transfer length.
813 * If the host controller said we transferred more data than the buffer
814 * length, urb->actual_length will be a very big number (since it's
815 * unsigned). Play it safe and say we didn't transfer anything.
816 */
817 if (urb->actual_length > urb->transfer_buffer_length) {
818 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
819 urb->transfer_buffer_length, urb->actual_length);
820 urb->actual_length = 0;
821 status = 0;
822 }
823 /* TD might be removed from td_list if we are giving back a cancelled URB */
824 if (!list_empty(&td->td_list))
825 list_del_init(&td->td_list);
826 /* Giving back a cancelled URB, or if a slated TD completed anyway */
827 if (!list_empty(&td->cancelled_td_list))
828 list_del_init(&td->cancelled_td_list);
829
830 inc_td_cnt(urb);
831 /* Giveback the urb when all the tds are completed */
832 if (last_td_in_urb(td)) {
833 if ((urb->actual_length != urb->transfer_buffer_length &&
834 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
835 (status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
836 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
837 urb, urb->actual_length,
838 urb->transfer_buffer_length, status);
839
840 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
841 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
842 status = 0;
843 xhci_giveback_urb_in_irq(xhci, td, status);
844 }
845
846 return 0;
847}
848
849
850/* Complete the cancelled URBs we unlinked from td_list. */
851static void xhci_giveback_invalidated_tds(struct xhci_virt_ep *ep)
852{
853 struct xhci_ring *ring;
854 struct xhci_td *td, *tmp_td;
855
856 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
857 cancelled_td_list) {
858
859 ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
860
861 if (td->cancel_status == TD_CLEARED) {
862 xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n",
863 __func__, td->urb);
864 xhci_td_cleanup(ep->xhci, td, ring, td->status);
865 } else {
866 xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
867 __func__, td->urb, td->cancel_status);
868 }
869 if (ep->xhci->xhc_state & XHCI_STATE_DYING)
870 return;
871 }
872}
873
874static int xhci_reset_halted_ep(struct xhci_hcd *xhci, unsigned int slot_id,
875 unsigned int ep_index, enum xhci_ep_reset_type reset_type)
876{
877 struct xhci_command *command;
878 int ret = 0;
879
880 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
881 if (!command) {
882 ret = -ENOMEM;
883 goto done;
884 }
885
886 xhci_dbg(xhci, "%s-reset ep %u, slot %u\n",
887 (reset_type == EP_HARD_RESET) ? "Hard" : "Soft",
888 ep_index, slot_id);
889
890 ret = xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
891done:
892 if (ret)
893 xhci_err(xhci, "ERROR queuing reset endpoint for slot %d ep_index %d, %d\n",
894 slot_id, ep_index, ret);
895 return ret;
896}
897
898static int xhci_handle_halted_endpoint(struct xhci_hcd *xhci,
899 struct xhci_virt_ep *ep,
900 struct xhci_td *td,
901 enum xhci_ep_reset_type reset_type)
902{
903 unsigned int slot_id = ep->vdev->slot_id;
904 int err;
905
906 /*
907 * Avoid resetting endpoint if link is inactive. Can cause host hang.
908 * Device will be reset soon to recover the link so don't do anything
909 */
910 if (ep->vdev->flags & VDEV_PORT_ERROR)
911 return -ENODEV;
912
913 /* add td to cancelled list and let reset ep handler take care of it */
914 if (reset_type == EP_HARD_RESET) {
915 ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
916 if (td && list_empty(&td->cancelled_td_list)) {
917 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
918 td->cancel_status = TD_HALTED;
919 }
920 }
921
922 if (ep->ep_state & EP_HALTED) {
923 xhci_dbg(xhci, "Reset ep command for ep_index %d already pending\n",
924 ep->ep_index);
925 return 0;
926 }
927
928 err = xhci_reset_halted_ep(xhci, slot_id, ep->ep_index, reset_type);
929 if (err)
930 return err;
931
932 ep->ep_state |= EP_HALTED;
933
934 xhci_ring_cmd_db(xhci);
935
936 return 0;
937}
938
939/*
940 * Fix up the ep ring first, so HW stops executing cancelled TDs.
941 * We have the xHCI lock, so nothing can modify this list until we drop it.
942 * We're also in the event handler, so we can't get re-interrupted if another
943 * Stop Endpoint command completes.
944 *
945 * only call this when ring is not in a running state
946 */
947
948static int xhci_invalidate_cancelled_tds(struct xhci_virt_ep *ep)
949{
950 struct xhci_hcd *xhci;
951 struct xhci_td *td = NULL;
952 struct xhci_td *tmp_td = NULL;
953 struct xhci_td *cached_td = NULL;
954 struct xhci_ring *ring;
955 u64 hw_deq;
956 unsigned int slot_id = ep->vdev->slot_id;
957 int err;
958
959 xhci = ep->xhci;
960
961 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
962 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
963 "Removing canceled TD starting at 0x%llx (dma) in stream %u URB %p",
964 (unsigned long long)xhci_trb_virt_to_dma(
965 td->start_seg, td->first_trb),
966 td->urb->stream_id, td->urb);
967 list_del_init(&td->td_list);
968 ring = xhci_urb_to_transfer_ring(xhci, td->urb);
969 if (!ring) {
970 xhci_warn(xhci, "WARN Cancelled URB %p has invalid stream ID %u.\n",
971 td->urb, td->urb->stream_id);
972 continue;
973 }
974 /*
975 * If a ring stopped on the TD we need to cancel then we have to
976 * move the xHC endpoint ring dequeue pointer past this TD.
977 * Rings halted due to STALL may show hw_deq is past the stalled
978 * TD, but still require a set TR Deq command to flush xHC cache.
979 */
980 hw_deq = xhci_get_hw_deq(xhci, ep->vdev, ep->ep_index,
981 td->urb->stream_id);
982 hw_deq &= ~0xf;
983
984 if (td->cancel_status == TD_HALTED ||
985 trb_in_td(xhci, td->start_seg, td->first_trb, td->last_trb, hw_deq, false)) {
986 switch (td->cancel_status) {
987 case TD_CLEARED: /* TD is already no-op */
988 case TD_CLEARING_CACHE: /* set TR deq command already queued */
989 break;
990 case TD_DIRTY: /* TD is cached, clear it */
991 case TD_HALTED:
992 td->cancel_status = TD_CLEARING_CACHE;
993 if (cached_td)
994 /* FIXME stream case, several stopped rings */
995 xhci_dbg(xhci,
996 "Move dq past stream %u URB %p instead of stream %u URB %p\n",
997 td->urb->stream_id, td->urb,
998 cached_td->urb->stream_id, cached_td->urb);
999 cached_td = td;
1000 break;
1001 }
1002 } else {
1003 td_to_noop(xhci, ring, td, false);
1004 td->cancel_status = TD_CLEARED;
1005 }
1006 }
1007
1008 /* If there's no need to move the dequeue pointer then we're done */
1009 if (!cached_td)
1010 return 0;
1011
1012 err = xhci_move_dequeue_past_td(xhci, slot_id, ep->ep_index,
1013 cached_td->urb->stream_id,
1014 cached_td);
1015 if (err) {
1016 /* Failed to move past cached td, just set cached TDs to no-op */
1017 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
1018 if (td->cancel_status != TD_CLEARING_CACHE)
1019 continue;
1020 xhci_dbg(xhci, "Failed to clear cancelled cached URB %p, mark clear anyway\n",
1021 td->urb);
1022 td_to_noop(xhci, ring, td, false);
1023 td->cancel_status = TD_CLEARED;
1024 }
1025 }
1026 return 0;
1027}
1028
1029/*
1030 * Returns the TD the endpoint ring halted on.
1031 * Only call for non-running rings without streams.
1032 */
1033static struct xhci_td *find_halted_td(struct xhci_virt_ep *ep)
1034{
1035 struct xhci_td *td;
1036 u64 hw_deq;
1037
1038 if (!list_empty(&ep->ring->td_list)) { /* Not streams compatible */
1039 hw_deq = xhci_get_hw_deq(ep->xhci, ep->vdev, ep->ep_index, 0);
1040 hw_deq &= ~0xf;
1041 td = list_first_entry(&ep->ring->td_list, struct xhci_td, td_list);
1042 if (trb_in_td(ep->xhci, td->start_seg, td->first_trb,
1043 td->last_trb, hw_deq, false))
1044 return td;
1045 }
1046 return NULL;
1047}
1048
1049/*
1050 * When we get a command completion for a Stop Endpoint Command, we need to
1051 * unlink any cancelled TDs from the ring. There are two ways to do that:
1052 *
1053 * 1. If the HW was in the middle of processing the TD that needs to be
1054 * cancelled, then we must move the ring's dequeue pointer past the last TRB
1055 * in the TD with a Set Dequeue Pointer Command.
1056 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
1057 * bit cleared) so that the HW will skip over them.
1058 */
1059static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
1060 union xhci_trb *trb, u32 comp_code)
1061{
1062 unsigned int ep_index;
1063 struct xhci_virt_ep *ep;
1064 struct xhci_ep_ctx *ep_ctx;
1065 struct xhci_td *td = NULL;
1066 enum xhci_ep_reset_type reset_type;
1067 struct xhci_command *command;
1068 int err;
1069
1070 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
1071 if (!xhci->devs[slot_id])
1072 xhci_warn(xhci, "Stop endpoint command completion for disabled slot %u\n",
1073 slot_id);
1074 return;
1075 }
1076
1077 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1078 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1079 if (!ep)
1080 return;
1081
1082 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1083
1084 trace_xhci_handle_cmd_stop_ep(ep_ctx);
1085
1086 if (comp_code == COMP_CONTEXT_STATE_ERROR) {
1087 /*
1088 * If stop endpoint command raced with a halting endpoint we need to
1089 * reset the host side endpoint first.
1090 * If the TD we halted on isn't cancelled the TD should be given back
1091 * with a proper error code, and the ring dequeue moved past the TD.
1092 * If streams case we can't find hw_deq, or the TD we halted on so do a
1093 * soft reset.
1094 *
1095 * Proper error code is unknown here, it would be -EPIPE if device side
1096 * of enadpoit halted (aka STALL), and -EPROTO if not (transaction error)
1097 * We use -EPROTO, if device is stalled it should return a stall error on
1098 * next transfer, which then will return -EPIPE, and device side stall is
1099 * noted and cleared by class driver.
1100 */
1101 switch (GET_EP_CTX_STATE(ep_ctx)) {
1102 case EP_STATE_HALTED:
1103 xhci_dbg(xhci, "Stop ep completion raced with stall, reset ep\n");
1104 if (ep->ep_state & EP_HAS_STREAMS) {
1105 reset_type = EP_SOFT_RESET;
1106 } else {
1107 reset_type = EP_HARD_RESET;
1108 td = find_halted_td(ep);
1109 if (td)
1110 td->status = -EPROTO;
1111 }
1112 /* reset ep, reset handler cleans up cancelled tds */
1113 err = xhci_handle_halted_endpoint(xhci, ep, td, reset_type);
1114 if (err)
1115 break;
1116 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1117 return;
1118 case EP_STATE_RUNNING:
1119 /* Race, HW handled stop ep cmd before ep was running */
1120 xhci_dbg(xhci, "Stop ep completion ctx error, ep is running\n");
1121
1122 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1123 if (!command) {
1124 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1125 return;
1126 }
1127 xhci_queue_stop_endpoint(xhci, command, slot_id, ep_index, 0);
1128 xhci_ring_cmd_db(xhci);
1129
1130 return;
1131 default:
1132 break;
1133 }
1134 }
1135
1136 /* will queue a set TR deq if stopped on a cancelled, uncleared TD */
1137 xhci_invalidate_cancelled_tds(ep);
1138 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1139
1140 /* Otherwise ring the doorbell(s) to restart queued transfers */
1141 xhci_giveback_invalidated_tds(ep);
1142 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1143}
1144
1145static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
1146{
1147 struct xhci_td *cur_td;
1148 struct xhci_td *tmp;
1149
1150 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
1151 list_del_init(&cur_td->td_list);
1152
1153 if (!list_empty(&cur_td->cancelled_td_list))
1154 list_del_init(&cur_td->cancelled_td_list);
1155
1156 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
1157
1158 inc_td_cnt(cur_td->urb);
1159 if (last_td_in_urb(cur_td))
1160 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1161 }
1162}
1163
1164static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
1165 int slot_id, int ep_index)
1166{
1167 struct xhci_td *cur_td;
1168 struct xhci_td *tmp;
1169 struct xhci_virt_ep *ep;
1170 struct xhci_ring *ring;
1171
1172 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1173 if (!ep)
1174 return;
1175
1176 if ((ep->ep_state & EP_HAS_STREAMS) ||
1177 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
1178 int stream_id;
1179
1180 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
1181 stream_id++) {
1182 ring = ep->stream_info->stream_rings[stream_id];
1183 if (!ring)
1184 continue;
1185
1186 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1187 "Killing URBs for slot ID %u, ep index %u, stream %u",
1188 slot_id, ep_index, stream_id);
1189 xhci_kill_ring_urbs(xhci, ring);
1190 }
1191 } else {
1192 ring = ep->ring;
1193 if (!ring)
1194 return;
1195 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1196 "Killing URBs for slot ID %u, ep index %u",
1197 slot_id, ep_index);
1198 xhci_kill_ring_urbs(xhci, ring);
1199 }
1200
1201 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
1202 cancelled_td_list) {
1203 list_del_init(&cur_td->cancelled_td_list);
1204 inc_td_cnt(cur_td->urb);
1205
1206 if (last_td_in_urb(cur_td))
1207 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1208 }
1209}
1210
1211/*
1212 * host controller died, register read returns 0xffffffff
1213 * Complete pending commands, mark them ABORTED.
1214 * URBs need to be given back as usb core might be waiting with device locks
1215 * held for the URBs to finish during device disconnect, blocking host remove.
1216 *
1217 * Call with xhci->lock held.
1218 * lock is relased and re-acquired while giving back urb.
1219 */
1220void xhci_hc_died(struct xhci_hcd *xhci)
1221{
1222 int i, j;
1223
1224 if (xhci->xhc_state & XHCI_STATE_DYING)
1225 return;
1226
1227 xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
1228 xhci->xhc_state |= XHCI_STATE_DYING;
1229
1230 xhci_cleanup_command_queue(xhci);
1231
1232 /* return any pending urbs, remove may be waiting for them */
1233 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
1234 if (!xhci->devs[i])
1235 continue;
1236 for (j = 0; j < 31; j++)
1237 xhci_kill_endpoint_urbs(xhci, i, j);
1238 }
1239
1240 /* inform usb core hc died if PCI remove isn't already handling it */
1241 if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
1242 usb_hc_died(xhci_to_hcd(xhci));
1243}
1244
1245static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1246 struct xhci_virt_device *dev,
1247 struct xhci_ring *ep_ring,
1248 unsigned int ep_index)
1249{
1250 union xhci_trb *dequeue_temp;
1251 int num_trbs_free_temp;
1252 bool revert = false;
1253
1254 num_trbs_free_temp = ep_ring->num_trbs_free;
1255 dequeue_temp = ep_ring->dequeue;
1256
1257 /* If we get two back-to-back stalls, and the first stalled transfer
1258 * ends just before a link TRB, the dequeue pointer will be left on
1259 * the link TRB by the code in the while loop. So we have to update
1260 * the dequeue pointer one segment further, or we'll jump off
1261 * the segment into la-la-land.
1262 */
1263 if (trb_is_link(ep_ring->dequeue)) {
1264 ep_ring->deq_seg = ep_ring->deq_seg->next;
1265 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1266 }
1267
1268 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1269 /* We have more usable TRBs */
1270 ep_ring->num_trbs_free++;
1271 ep_ring->dequeue++;
1272 if (trb_is_link(ep_ring->dequeue)) {
1273 if (ep_ring->dequeue ==
1274 dev->eps[ep_index].queued_deq_ptr)
1275 break;
1276 ep_ring->deq_seg = ep_ring->deq_seg->next;
1277 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1278 }
1279 if (ep_ring->dequeue == dequeue_temp) {
1280 revert = true;
1281 break;
1282 }
1283 }
1284
1285 if (revert) {
1286 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1287 ep_ring->num_trbs_free = num_trbs_free_temp;
1288 }
1289}
1290
1291/*
1292 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1293 * we need to clear the set deq pending flag in the endpoint ring state, so that
1294 * the TD queueing code can ring the doorbell again. We also need to ring the
1295 * endpoint doorbell to restart the ring, but only if there aren't more
1296 * cancellations pending.
1297 */
1298static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1299 union xhci_trb *trb, u32 cmd_comp_code)
1300{
1301 unsigned int ep_index;
1302 unsigned int stream_id;
1303 struct xhci_ring *ep_ring;
1304 struct xhci_virt_ep *ep;
1305 struct xhci_ep_ctx *ep_ctx;
1306 struct xhci_slot_ctx *slot_ctx;
1307 struct xhci_td *td, *tmp_td;
1308
1309 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1310 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1311 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1312 if (!ep)
1313 return;
1314
1315 ep_ring = xhci_virt_ep_to_ring(xhci, ep, stream_id);
1316 if (!ep_ring) {
1317 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1318 stream_id);
1319 /* XXX: Harmless??? */
1320 goto cleanup;
1321 }
1322
1323 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1324 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
1325 trace_xhci_handle_cmd_set_deq(slot_ctx);
1326 trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1327
1328 if (cmd_comp_code != COMP_SUCCESS) {
1329 unsigned int ep_state;
1330 unsigned int slot_state;
1331
1332 switch (cmd_comp_code) {
1333 case COMP_TRB_ERROR:
1334 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1335 break;
1336 case COMP_CONTEXT_STATE_ERROR:
1337 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1338 ep_state = GET_EP_CTX_STATE(ep_ctx);
1339 slot_state = le32_to_cpu(slot_ctx->dev_state);
1340 slot_state = GET_SLOT_STATE(slot_state);
1341 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1342 "Slot state = %u, EP state = %u",
1343 slot_state, ep_state);
1344 break;
1345 case COMP_SLOT_NOT_ENABLED_ERROR:
1346 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1347 slot_id);
1348 break;
1349 default:
1350 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1351 cmd_comp_code);
1352 break;
1353 }
1354 /* OK what do we do now? The endpoint state is hosed, and we
1355 * should never get to this point if the synchronization between
1356 * queueing, and endpoint state are correct. This might happen
1357 * if the device gets disconnected after we've finished
1358 * cancelling URBs, which might not be an error...
1359 */
1360 } else {
1361 u64 deq;
1362 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1363 if (ep->ep_state & EP_HAS_STREAMS) {
1364 struct xhci_stream_ctx *ctx =
1365 &ep->stream_info->stream_ctx_array[stream_id];
1366 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1367 } else {
1368 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1369 }
1370 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1371 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1372 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1373 ep->queued_deq_ptr) == deq) {
1374 /* Update the ring's dequeue segment and dequeue pointer
1375 * to reflect the new position.
1376 */
1377 update_ring_for_set_deq_completion(xhci, ep->vdev,
1378 ep_ring, ep_index);
1379 } else {
1380 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1381 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1382 ep->queued_deq_seg, ep->queued_deq_ptr);
1383 }
1384 }
1385 /* HW cached TDs cleared from cache, give them back */
1386 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
1387 cancelled_td_list) {
1388 ep_ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
1389 if (td->cancel_status == TD_CLEARING_CACHE) {
1390 td->cancel_status = TD_CLEARED;
1391 xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n",
1392 __func__, td->urb);
1393 xhci_td_cleanup(ep->xhci, td, ep_ring, td->status);
1394 } else {
1395 xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
1396 __func__, td->urb, td->cancel_status);
1397 }
1398 }
1399cleanup:
1400 ep->ep_state &= ~SET_DEQ_PENDING;
1401 ep->queued_deq_seg = NULL;
1402 ep->queued_deq_ptr = NULL;
1403 /* Restart any rings with pending URBs */
1404 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1405}
1406
1407static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1408 union xhci_trb *trb, u32 cmd_comp_code)
1409{
1410 struct xhci_virt_ep *ep;
1411 struct xhci_ep_ctx *ep_ctx;
1412 unsigned int ep_index;
1413
1414 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1415 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1416 if (!ep)
1417 return;
1418
1419 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1420 trace_xhci_handle_cmd_reset_ep(ep_ctx);
1421
1422 /* This command will only fail if the endpoint wasn't halted,
1423 * but we don't care.
1424 */
1425 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1426 "Ignoring reset ep completion code of %u", cmd_comp_code);
1427
1428 /* Cleanup cancelled TDs as ep is stopped. May queue a Set TR Deq cmd */
1429 xhci_invalidate_cancelled_tds(ep);
1430
1431 /* Clear our internal halted state */
1432 ep->ep_state &= ~EP_HALTED;
1433
1434 xhci_giveback_invalidated_tds(ep);
1435
1436 /* if this was a soft reset, then restart */
1437 if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP)
1438 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1439}
1440
1441static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1442 struct xhci_command *command, u32 cmd_comp_code)
1443{
1444 if (cmd_comp_code == COMP_SUCCESS)
1445 command->slot_id = slot_id;
1446 else
1447 command->slot_id = 0;
1448}
1449
1450static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1451{
1452 struct xhci_virt_device *virt_dev;
1453 struct xhci_slot_ctx *slot_ctx;
1454
1455 virt_dev = xhci->devs[slot_id];
1456 if (!virt_dev)
1457 return;
1458
1459 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1460 trace_xhci_handle_cmd_disable_slot(slot_ctx);
1461
1462 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1463 /* Delete default control endpoint resources */
1464 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1465}
1466
1467static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1468 u32 cmd_comp_code)
1469{
1470 struct xhci_virt_device *virt_dev;
1471 struct xhci_input_control_ctx *ctrl_ctx;
1472 struct xhci_ep_ctx *ep_ctx;
1473 unsigned int ep_index;
1474 u32 add_flags;
1475
1476 /*
1477 * Configure endpoint commands can come from the USB core configuration
1478 * or alt setting changes, or when streams were being configured.
1479 */
1480
1481 virt_dev = xhci->devs[slot_id];
1482 if (!virt_dev)
1483 return;
1484 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1485 if (!ctrl_ctx) {
1486 xhci_warn(xhci, "Could not get input context, bad type.\n");
1487 return;
1488 }
1489
1490 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1491
1492 /* Input ctx add_flags are the endpoint index plus one */
1493 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1494
1495 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1496 trace_xhci_handle_cmd_config_ep(ep_ctx);
1497
1498 return;
1499}
1500
1501static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1502{
1503 struct xhci_virt_device *vdev;
1504 struct xhci_slot_ctx *slot_ctx;
1505
1506 vdev = xhci->devs[slot_id];
1507 if (!vdev)
1508 return;
1509 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1510 trace_xhci_handle_cmd_addr_dev(slot_ctx);
1511}
1512
1513static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id)
1514{
1515 struct xhci_virt_device *vdev;
1516 struct xhci_slot_ctx *slot_ctx;
1517
1518 vdev = xhci->devs[slot_id];
1519 if (!vdev) {
1520 xhci_warn(xhci, "Reset device command completion for disabled slot %u\n",
1521 slot_id);
1522 return;
1523 }
1524 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1525 trace_xhci_handle_cmd_reset_dev(slot_ctx);
1526
1527 xhci_dbg(xhci, "Completed reset device command.\n");
1528}
1529
1530static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1531 struct xhci_event_cmd *event)
1532{
1533 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1534 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1535 return;
1536 }
1537 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1538 "NEC firmware version %2x.%02x",
1539 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1540 NEC_FW_MINOR(le32_to_cpu(event->status)));
1541}
1542
1543static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1544{
1545 list_del(&cmd->cmd_list);
1546
1547 if (cmd->completion) {
1548 cmd->status = status;
1549 complete(cmd->completion);
1550 } else {
1551 kfree(cmd);
1552 }
1553}
1554
1555void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1556{
1557 struct xhci_command *cur_cmd, *tmp_cmd;
1558 xhci->current_cmd = NULL;
1559 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1560 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1561}
1562
1563void xhci_handle_command_timeout(struct work_struct *work)
1564{
1565 struct xhci_hcd *xhci;
1566 unsigned long flags;
1567 char str[XHCI_MSG_MAX];
1568 u64 hw_ring_state;
1569 u32 cmd_field3;
1570 u32 usbsts;
1571
1572 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1573
1574 spin_lock_irqsave(&xhci->lock, flags);
1575
1576 /*
1577 * If timeout work is pending, or current_cmd is NULL, it means we
1578 * raced with command completion. Command is handled so just return.
1579 */
1580 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1581 spin_unlock_irqrestore(&xhci->lock, flags);
1582 return;
1583 }
1584
1585 cmd_field3 = le32_to_cpu(xhci->current_cmd->command_trb->generic.field[3]);
1586 usbsts = readl(&xhci->op_regs->status);
1587 xhci_dbg(xhci, "Command timeout, USBSTS:%s\n", xhci_decode_usbsts(str, usbsts));
1588
1589 /* Bail out and tear down xhci if a stop endpoint command failed */
1590 if (TRB_FIELD_TO_TYPE(cmd_field3) == TRB_STOP_RING) {
1591 struct xhci_virt_ep *ep;
1592
1593 xhci_warn(xhci, "xHCI host not responding to stop endpoint command\n");
1594
1595 ep = xhci_get_virt_ep(xhci, TRB_TO_SLOT_ID(cmd_field3),
1596 TRB_TO_EP_INDEX(cmd_field3));
1597 if (ep)
1598 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1599
1600 xhci_halt(xhci);
1601 xhci_hc_died(xhci);
1602 goto time_out_completed;
1603 }
1604
1605 /* mark this command to be cancelled */
1606 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1607
1608 /* Make sure command ring is running before aborting it */
1609 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1610 if (hw_ring_state == ~(u64)0) {
1611 xhci_hc_died(xhci);
1612 goto time_out_completed;
1613 }
1614
1615 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1616 (hw_ring_state & CMD_RING_RUNNING)) {
1617 /* Prevent new doorbell, and start command abort */
1618 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1619 xhci_dbg(xhci, "Command timeout\n");
1620 xhci_abort_cmd_ring(xhci, flags);
1621 goto time_out_completed;
1622 }
1623
1624 /* host removed. Bail out */
1625 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1626 xhci_dbg(xhci, "host removed, ring start fail?\n");
1627 xhci_cleanup_command_queue(xhci);
1628
1629 goto time_out_completed;
1630 }
1631
1632 /* command timeout on stopped ring, ring can't be aborted */
1633 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1634 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1635
1636time_out_completed:
1637 spin_unlock_irqrestore(&xhci->lock, flags);
1638 return;
1639}
1640
1641static void handle_cmd_completion(struct xhci_hcd *xhci,
1642 struct xhci_event_cmd *event)
1643{
1644 unsigned int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1645 u64 cmd_dma;
1646 dma_addr_t cmd_dequeue_dma;
1647 u32 cmd_comp_code;
1648 union xhci_trb *cmd_trb;
1649 struct xhci_command *cmd;
1650 u32 cmd_type;
1651
1652 if (slot_id >= MAX_HC_SLOTS) {
1653 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
1654 return;
1655 }
1656
1657 cmd_dma = le64_to_cpu(event->cmd_trb);
1658 cmd_trb = xhci->cmd_ring->dequeue;
1659
1660 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1661
1662 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1663 cmd_trb);
1664 /*
1665 * Check whether the completion event is for our internal kept
1666 * command.
1667 */
1668 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1669 xhci_warn(xhci,
1670 "ERROR mismatched command completion event\n");
1671 return;
1672 }
1673
1674 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1675
1676 cancel_delayed_work(&xhci->cmd_timer);
1677
1678 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1679
1680 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1681 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1682 complete_all(&xhci->cmd_ring_stop_completion);
1683 return;
1684 }
1685
1686 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1687 xhci_err(xhci,
1688 "Command completion event does not match command\n");
1689 return;
1690 }
1691
1692 /*
1693 * Host aborted the command ring, check if the current command was
1694 * supposed to be aborted, otherwise continue normally.
1695 * The command ring is stopped now, but the xHC will issue a Command
1696 * Ring Stopped event which will cause us to restart it.
1697 */
1698 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1699 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1700 if (cmd->status == COMP_COMMAND_ABORTED) {
1701 if (xhci->current_cmd == cmd)
1702 xhci->current_cmd = NULL;
1703 goto event_handled;
1704 }
1705 }
1706
1707 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1708 switch (cmd_type) {
1709 case TRB_ENABLE_SLOT:
1710 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1711 break;
1712 case TRB_DISABLE_SLOT:
1713 xhci_handle_cmd_disable_slot(xhci, slot_id);
1714 break;
1715 case TRB_CONFIG_EP:
1716 if (!cmd->completion)
1717 xhci_handle_cmd_config_ep(xhci, slot_id, cmd_comp_code);
1718 break;
1719 case TRB_EVAL_CONTEXT:
1720 break;
1721 case TRB_ADDR_DEV:
1722 xhci_handle_cmd_addr_dev(xhci, slot_id);
1723 break;
1724 case TRB_STOP_RING:
1725 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1726 le32_to_cpu(cmd_trb->generic.field[3])));
1727 if (!cmd->completion)
1728 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb,
1729 cmd_comp_code);
1730 break;
1731 case TRB_SET_DEQ:
1732 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1733 le32_to_cpu(cmd_trb->generic.field[3])));
1734 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1735 break;
1736 case TRB_CMD_NOOP:
1737 /* Is this an aborted command turned to NO-OP? */
1738 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1739 cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1740 break;
1741 case TRB_RESET_EP:
1742 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1743 le32_to_cpu(cmd_trb->generic.field[3])));
1744 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1745 break;
1746 case TRB_RESET_DEV:
1747 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1748 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1749 */
1750 slot_id = TRB_TO_SLOT_ID(
1751 le32_to_cpu(cmd_trb->generic.field[3]));
1752 xhci_handle_cmd_reset_dev(xhci, slot_id);
1753 break;
1754 case TRB_NEC_GET_FW:
1755 xhci_handle_cmd_nec_get_fw(xhci, event);
1756 break;
1757 default:
1758 /* Skip over unknown commands on the event ring */
1759 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1760 break;
1761 }
1762
1763 /* restart timer if this wasn't the last command */
1764 if (!list_is_singular(&xhci->cmd_list)) {
1765 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1766 struct xhci_command, cmd_list);
1767 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1768 } else if (xhci->current_cmd == cmd) {
1769 xhci->current_cmd = NULL;
1770 }
1771
1772event_handled:
1773 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1774
1775 inc_deq(xhci, xhci->cmd_ring);
1776}
1777
1778static void handle_vendor_event(struct xhci_hcd *xhci,
1779 union xhci_trb *event, u32 trb_type)
1780{
1781 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1782 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1783 handle_cmd_completion(xhci, &event->event_cmd);
1784}
1785
1786static void handle_device_notification(struct xhci_hcd *xhci,
1787 union xhci_trb *event)
1788{
1789 u32 slot_id;
1790 struct usb_device *udev;
1791
1792 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1793 if (!xhci->devs[slot_id]) {
1794 xhci_warn(xhci, "Device Notification event for "
1795 "unused slot %u\n", slot_id);
1796 return;
1797 }
1798
1799 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1800 slot_id);
1801 udev = xhci->devs[slot_id]->udev;
1802 if (udev && udev->parent)
1803 usb_wakeup_notification(udev->parent, udev->portnum);
1804}
1805
1806/*
1807 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1808 * Controller.
1809 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1810 * If a connection to a USB 1 device is followed by another connection
1811 * to a USB 2 device.
1812 *
1813 * Reset the PHY after the USB device is disconnected if device speed
1814 * is less than HCD_USB3.
1815 * Retry the reset sequence max of 4 times checking the PLL lock status.
1816 *
1817 */
1818static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1819{
1820 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1821 u32 pll_lock_check;
1822 u32 retry_count = 4;
1823
1824 do {
1825 /* Assert PHY reset */
1826 writel(0x6F, hcd->regs + 0x1048);
1827 udelay(10);
1828 /* De-assert the PHY reset */
1829 writel(0x7F, hcd->regs + 0x1048);
1830 udelay(200);
1831 pll_lock_check = readl(hcd->regs + 0x1070);
1832 } while (!(pll_lock_check & 0x1) && --retry_count);
1833}
1834
1835static void handle_port_status(struct xhci_hcd *xhci,
1836 union xhci_trb *event)
1837{
1838 struct usb_hcd *hcd;
1839 u32 port_id;
1840 u32 portsc, cmd_reg;
1841 int max_ports;
1842 int slot_id;
1843 unsigned int hcd_portnum;
1844 struct xhci_bus_state *bus_state;
1845 bool bogus_port_status = false;
1846 struct xhci_port *port;
1847
1848 /* Port status change events always have a successful completion code */
1849 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1850 xhci_warn(xhci,
1851 "WARN: xHC returned failed port status event\n");
1852
1853 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1854 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1855
1856 if ((port_id <= 0) || (port_id > max_ports)) {
1857 xhci_warn(xhci, "Port change event with invalid port ID %d\n",
1858 port_id);
1859 inc_deq(xhci, xhci->event_ring);
1860 return;
1861 }
1862
1863 port = &xhci->hw_ports[port_id - 1];
1864 if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1865 xhci_warn(xhci, "Port change event, no port for port ID %u\n",
1866 port_id);
1867 bogus_port_status = true;
1868 goto cleanup;
1869 }
1870
1871 /* We might get interrupts after shared_hcd is removed */
1872 if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
1873 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
1874 bogus_port_status = true;
1875 goto cleanup;
1876 }
1877
1878 hcd = port->rhub->hcd;
1879 bus_state = &port->rhub->bus_state;
1880 hcd_portnum = port->hcd_portnum;
1881 portsc = readl(port->addr);
1882
1883 xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n",
1884 hcd->self.busnum, hcd_portnum + 1, port_id, portsc);
1885
1886 trace_xhci_handle_port_status(hcd_portnum, portsc);
1887
1888 if (hcd->state == HC_STATE_SUSPENDED) {
1889 xhci_dbg(xhci, "resume root hub\n");
1890 usb_hcd_resume_root_hub(hcd);
1891 }
1892
1893 if (hcd->speed >= HCD_USB3 &&
1894 (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
1895 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1896 if (slot_id && xhci->devs[slot_id])
1897 xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR;
1898 }
1899
1900 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1901 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1902
1903 cmd_reg = readl(&xhci->op_regs->command);
1904 if (!(cmd_reg & CMD_RUN)) {
1905 xhci_warn(xhci, "xHC is not running.\n");
1906 goto cleanup;
1907 }
1908
1909 if (DEV_SUPERSPEED_ANY(portsc)) {
1910 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1911 /* Set a flag to say the port signaled remote wakeup,
1912 * so we can tell the difference between the end of
1913 * device and host initiated resume.
1914 */
1915 bus_state->port_remote_wakeup |= 1 << hcd_portnum;
1916 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1917 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1918 xhci_set_link_state(xhci, port, XDEV_U0);
1919 /* Need to wait until the next link state change
1920 * indicates the device is actually in U0.
1921 */
1922 bogus_port_status = true;
1923 goto cleanup;
1924 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
1925 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1926 bus_state->resume_done[hcd_portnum] = jiffies +
1927 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1928 set_bit(hcd_portnum, &bus_state->resuming_ports);
1929 /* Do the rest in GetPortStatus after resume time delay.
1930 * Avoid polling roothub status before that so that a
1931 * usb device auto-resume latency around ~40ms.
1932 */
1933 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1934 mod_timer(&hcd->rh_timer,
1935 bus_state->resume_done[hcd_portnum]);
1936 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1937 bogus_port_status = true;
1938 }
1939 }
1940
1941 if ((portsc & PORT_PLC) &&
1942 DEV_SUPERSPEED_ANY(portsc) &&
1943 ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
1944 (portsc & PORT_PLS_MASK) == XDEV_U1 ||
1945 (portsc & PORT_PLS_MASK) == XDEV_U2)) {
1946 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1947 complete(&bus_state->u3exit_done[hcd_portnum]);
1948 /* We've just brought the device into U0/1/2 through either the
1949 * Resume state after a device remote wakeup, or through the
1950 * U3Exit state after a host-initiated resume. If it's a device
1951 * initiated remote wake, don't pass up the link state change,
1952 * so the roothub behavior is consistent with external
1953 * USB 3.0 hub behavior.
1954 */
1955 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1956 if (slot_id && xhci->devs[slot_id])
1957 xhci_ring_device(xhci, slot_id);
1958 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
1959 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1960 usb_wakeup_notification(hcd->self.root_hub,
1961 hcd_portnum + 1);
1962 bogus_port_status = true;
1963 goto cleanup;
1964 }
1965 }
1966
1967 /*
1968 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1969 * RExit to a disconnect state). If so, let the driver know it's
1970 * out of the RExit state.
1971 */
1972 if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 &&
1973 test_and_clear_bit(hcd_portnum,
1974 &bus_state->rexit_ports)) {
1975 complete(&bus_state->rexit_done[hcd_portnum]);
1976 bogus_port_status = true;
1977 goto cleanup;
1978 }
1979
1980 if (hcd->speed < HCD_USB3) {
1981 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1982 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
1983 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
1984 xhci_cavium_reset_phy_quirk(xhci);
1985 }
1986
1987cleanup:
1988 /* Update event ring dequeue pointer before dropping the lock */
1989 inc_deq(xhci, xhci->event_ring);
1990
1991 /* Don't make the USB core poll the roothub if we got a bad port status
1992 * change event. Besides, at that point we can't tell which roothub
1993 * (USB 2.0 or USB 3.0) to kick.
1994 */
1995 if (bogus_port_status)
1996 return;
1997
1998 /*
1999 * xHCI port-status-change events occur when the "or" of all the
2000 * status-change bits in the portsc register changes from 0 to 1.
2001 * New status changes won't cause an event if any other change
2002 * bits are still set. When an event occurs, switch over to
2003 * polling to avoid losing status changes.
2004 */
2005 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
2006 __func__, hcd->self.busnum);
2007 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
2008 spin_unlock(&xhci->lock);
2009 /* Pass this up to the core */
2010 usb_hcd_poll_rh_status(hcd);
2011 spin_lock(&xhci->lock);
2012}
2013
2014/*
2015 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
2016 * at end_trb, which may be in another segment. If the suspect DMA address is a
2017 * TRB in this TD, this function returns that TRB's segment. Otherwise it
2018 * returns 0.
2019 */
2020struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2021 struct xhci_segment *start_seg,
2022 union xhci_trb *start_trb,
2023 union xhci_trb *end_trb,
2024 dma_addr_t suspect_dma,
2025 bool debug)
2026{
2027 dma_addr_t start_dma;
2028 dma_addr_t end_seg_dma;
2029 dma_addr_t end_trb_dma;
2030 struct xhci_segment *cur_seg;
2031
2032 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
2033 cur_seg = start_seg;
2034
2035 do {
2036 if (start_dma == 0)
2037 return NULL;
2038 /* We may get an event for a Link TRB in the middle of a TD */
2039 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
2040 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
2041 /* If the end TRB isn't in this segment, this is set to 0 */
2042 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
2043
2044 if (debug)
2045 xhci_warn(xhci,
2046 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
2047 (unsigned long long)suspect_dma,
2048 (unsigned long long)start_dma,
2049 (unsigned long long)end_trb_dma,
2050 (unsigned long long)cur_seg->dma,
2051 (unsigned long long)end_seg_dma);
2052
2053 if (end_trb_dma > 0) {
2054 /* The end TRB is in this segment, so suspect should be here */
2055 if (start_dma <= end_trb_dma) {
2056 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
2057 return cur_seg;
2058 } else {
2059 /* Case for one segment with
2060 * a TD wrapped around to the top
2061 */
2062 if ((suspect_dma >= start_dma &&
2063 suspect_dma <= end_seg_dma) ||
2064 (suspect_dma >= cur_seg->dma &&
2065 suspect_dma <= end_trb_dma))
2066 return cur_seg;
2067 }
2068 return NULL;
2069 } else {
2070 /* Might still be somewhere in this segment */
2071 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
2072 return cur_seg;
2073 }
2074 cur_seg = cur_seg->next;
2075 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
2076 } while (cur_seg != start_seg);
2077
2078 return NULL;
2079}
2080
2081static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td,
2082 struct xhci_virt_ep *ep)
2083{
2084 /*
2085 * As part of low/full-speed endpoint-halt processing
2086 * we must clear the TT buffer (USB 2.0 specification 11.17.5).
2087 */
2088 if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) &&
2089 (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) &&
2090 !(ep->ep_state & EP_CLEARING_TT)) {
2091 ep->ep_state |= EP_CLEARING_TT;
2092 td->urb->ep->hcpriv = td->urb->dev;
2093 if (usb_hub_clear_tt_buffer(td->urb))
2094 ep->ep_state &= ~EP_CLEARING_TT;
2095 }
2096}
2097
2098/* Check if an error has halted the endpoint ring. The class driver will
2099 * cleanup the halt for a non-default control endpoint if we indicate a stall.
2100 * However, a babble and other errors also halt the endpoint ring, and the class
2101 * driver won't clear the halt in that case, so we need to issue a Set Transfer
2102 * Ring Dequeue Pointer command manually.
2103 */
2104static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
2105 struct xhci_ep_ctx *ep_ctx,
2106 unsigned int trb_comp_code)
2107{
2108 /* TRB completion codes that may require a manual halt cleanup */
2109 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
2110 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
2111 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
2112 /* The 0.95 spec says a babbling control endpoint
2113 * is not halted. The 0.96 spec says it is. Some HW
2114 * claims to be 0.95 compliant, but it halts the control
2115 * endpoint anyway. Check if a babble halted the
2116 * endpoint.
2117 */
2118 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
2119 return 1;
2120
2121 return 0;
2122}
2123
2124int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
2125{
2126 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
2127 /* Vendor defined "informational" completion code,
2128 * treat as not-an-error.
2129 */
2130 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
2131 trb_comp_code);
2132 xhci_dbg(xhci, "Treating code as success.\n");
2133 return 1;
2134 }
2135 return 0;
2136}
2137
2138static int finish_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2139 struct xhci_ring *ep_ring, struct xhci_td *td,
2140 u32 trb_comp_code)
2141{
2142 struct xhci_ep_ctx *ep_ctx;
2143
2144 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2145
2146 switch (trb_comp_code) {
2147 case COMP_STOPPED_LENGTH_INVALID:
2148 case COMP_STOPPED_SHORT_PACKET:
2149 case COMP_STOPPED:
2150 /*
2151 * The "Stop Endpoint" completion will take care of any
2152 * stopped TDs. A stopped TD may be restarted, so don't update
2153 * the ring dequeue pointer or take this TD off any lists yet.
2154 */
2155 return 0;
2156 case COMP_USB_TRANSACTION_ERROR:
2157 case COMP_BABBLE_DETECTED_ERROR:
2158 case COMP_SPLIT_TRANSACTION_ERROR:
2159 /*
2160 * If endpoint context state is not halted we might be
2161 * racing with a reset endpoint command issued by a unsuccessful
2162 * stop endpoint completion (context error). In that case the
2163 * td should be on the cancelled list, and EP_HALTED flag set.
2164 *
2165 * Or then it's not halted due to the 0.95 spec stating that a
2166 * babbling control endpoint should not halt. The 0.96 spec
2167 * again says it should. Some HW claims to be 0.95 compliant,
2168 * but it halts the control endpoint anyway.
2169 */
2170 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_HALTED) {
2171 /*
2172 * If EP_HALTED is set and TD is on the cancelled list
2173 * the TD and dequeue pointer will be handled by reset
2174 * ep command completion
2175 */
2176 if ((ep->ep_state & EP_HALTED) &&
2177 !list_empty(&td->cancelled_td_list)) {
2178 xhci_dbg(xhci, "Already resolving halted ep for 0x%llx\n",
2179 (unsigned long long)xhci_trb_virt_to_dma(
2180 td->start_seg, td->first_trb));
2181 return 0;
2182 }
2183 /* endpoint not halted, don't reset it */
2184 break;
2185 }
2186 /* Almost same procedure as for STALL_ERROR below */
2187 xhci_clear_hub_tt_buffer(xhci, td, ep);
2188 xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET);
2189 return 0;
2190 case COMP_STALL_ERROR:
2191 /*
2192 * xhci internal endpoint state will go to a "halt" state for
2193 * any stall, including default control pipe protocol stall.
2194 * To clear the host side halt we need to issue a reset endpoint
2195 * command, followed by a set dequeue command to move past the
2196 * TD.
2197 * Class drivers clear the device side halt from a functional
2198 * stall later. Hub TT buffer should only be cleared for FS/LS
2199 * devices behind HS hubs for functional stalls.
2200 */
2201 if (ep->ep_index != 0)
2202 xhci_clear_hub_tt_buffer(xhci, td, ep);
2203
2204 xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET);
2205
2206 return 0; /* xhci_handle_halted_endpoint marked td cancelled */
2207 default:
2208 break;
2209 }
2210
2211 /* Update ring dequeue pointer */
2212 ep_ring->dequeue = td->last_trb;
2213 ep_ring->deq_seg = td->last_trb_seg;
2214 ep_ring->num_trbs_free += td->num_trbs - 1;
2215 inc_deq(xhci, ep_ring);
2216
2217 return xhci_td_cleanup(xhci, td, ep_ring, td->status);
2218}
2219
2220/* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
2221static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
2222 union xhci_trb *stop_trb)
2223{
2224 u32 sum;
2225 union xhci_trb *trb = ring->dequeue;
2226 struct xhci_segment *seg = ring->deq_seg;
2227
2228 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
2229 if (!trb_is_noop(trb) && !trb_is_link(trb))
2230 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2231 }
2232 return sum;
2233}
2234
2235/*
2236 * Process control tds, update urb status and actual_length.
2237 */
2238static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2239 struct xhci_ring *ep_ring, struct xhci_td *td,
2240 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2241{
2242 struct xhci_ep_ctx *ep_ctx;
2243 u32 trb_comp_code;
2244 u32 remaining, requested;
2245 u32 trb_type;
2246
2247 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2248 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2249 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2250 requested = td->urb->transfer_buffer_length;
2251 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2252
2253 switch (trb_comp_code) {
2254 case COMP_SUCCESS:
2255 if (trb_type != TRB_STATUS) {
2256 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2257 (trb_type == TRB_DATA) ? "data" : "setup");
2258 td->status = -ESHUTDOWN;
2259 break;
2260 }
2261 td->status = 0;
2262 break;
2263 case COMP_SHORT_PACKET:
2264 td->status = 0;
2265 break;
2266 case COMP_STOPPED_SHORT_PACKET:
2267 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2268 td->urb->actual_length = remaining;
2269 else
2270 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2271 goto finish_td;
2272 case COMP_STOPPED:
2273 switch (trb_type) {
2274 case TRB_SETUP:
2275 td->urb->actual_length = 0;
2276 goto finish_td;
2277 case TRB_DATA:
2278 case TRB_NORMAL:
2279 td->urb->actual_length = requested - remaining;
2280 goto finish_td;
2281 case TRB_STATUS:
2282 td->urb->actual_length = requested;
2283 goto finish_td;
2284 default:
2285 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2286 trb_type);
2287 goto finish_td;
2288 }
2289 case COMP_STOPPED_LENGTH_INVALID:
2290 goto finish_td;
2291 default:
2292 if (!xhci_requires_manual_halt_cleanup(xhci,
2293 ep_ctx, trb_comp_code))
2294 break;
2295 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2296 trb_comp_code, ep->ep_index);
2297 fallthrough;
2298 case COMP_STALL_ERROR:
2299 /* Did we transfer part of the data (middle) phase? */
2300 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2301 td->urb->actual_length = requested - remaining;
2302 else if (!td->urb_length_set)
2303 td->urb->actual_length = 0;
2304 goto finish_td;
2305 }
2306
2307 /* stopped at setup stage, no data transferred */
2308 if (trb_type == TRB_SETUP)
2309 goto finish_td;
2310
2311 /*
2312 * if on data stage then update the actual_length of the URB and flag it
2313 * as set, so it won't be overwritten in the event for the last TRB.
2314 */
2315 if (trb_type == TRB_DATA ||
2316 trb_type == TRB_NORMAL) {
2317 td->urb_length_set = true;
2318 td->urb->actual_length = requested - remaining;
2319 xhci_dbg(xhci, "Waiting for status stage event\n");
2320 return 0;
2321 }
2322
2323 /* at status stage */
2324 if (!td->urb_length_set)
2325 td->urb->actual_length = requested;
2326
2327finish_td:
2328 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2329}
2330
2331/*
2332 * Process isochronous tds, update urb packet status and actual_length.
2333 */
2334static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2335 struct xhci_ring *ep_ring, struct xhci_td *td,
2336 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2337{
2338 struct urb_priv *urb_priv;
2339 int idx;
2340 struct usb_iso_packet_descriptor *frame;
2341 u32 trb_comp_code;
2342 bool sum_trbs_for_length = false;
2343 u32 remaining, requested, ep_trb_len;
2344 int short_framestatus;
2345
2346 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2347 urb_priv = td->urb->hcpriv;
2348 idx = urb_priv->num_tds_done;
2349 frame = &td->urb->iso_frame_desc[idx];
2350 requested = frame->length;
2351 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2352 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2353 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2354 -EREMOTEIO : 0;
2355
2356 /* handle completion code */
2357 switch (trb_comp_code) {
2358 case COMP_SUCCESS:
2359 if (remaining) {
2360 frame->status = short_framestatus;
2361 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2362 sum_trbs_for_length = true;
2363 break;
2364 }
2365 frame->status = 0;
2366 break;
2367 case COMP_SHORT_PACKET:
2368 frame->status = short_framestatus;
2369 sum_trbs_for_length = true;
2370 break;
2371 case COMP_BANDWIDTH_OVERRUN_ERROR:
2372 frame->status = -ECOMM;
2373 break;
2374 case COMP_ISOCH_BUFFER_OVERRUN:
2375 case COMP_BABBLE_DETECTED_ERROR:
2376 frame->status = -EOVERFLOW;
2377 break;
2378 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2379 case COMP_STALL_ERROR:
2380 frame->status = -EPROTO;
2381 break;
2382 case COMP_USB_TRANSACTION_ERROR:
2383 frame->status = -EPROTO;
2384 if (ep_trb != td->last_trb)
2385 return 0;
2386 break;
2387 case COMP_STOPPED:
2388 sum_trbs_for_length = true;
2389 break;
2390 case COMP_STOPPED_SHORT_PACKET:
2391 /* field normally containing residue now contains tranferred */
2392 frame->status = short_framestatus;
2393 requested = remaining;
2394 break;
2395 case COMP_STOPPED_LENGTH_INVALID:
2396 requested = 0;
2397 remaining = 0;
2398 break;
2399 default:
2400 sum_trbs_for_length = true;
2401 frame->status = -1;
2402 break;
2403 }
2404
2405 if (sum_trbs_for_length)
2406 frame->actual_length = sum_trb_lengths(xhci, ep->ring, ep_trb) +
2407 ep_trb_len - remaining;
2408 else
2409 frame->actual_length = requested;
2410
2411 td->urb->actual_length += frame->actual_length;
2412
2413 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2414}
2415
2416static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2417 struct xhci_virt_ep *ep, int status)
2418{
2419 struct urb_priv *urb_priv;
2420 struct usb_iso_packet_descriptor *frame;
2421 int idx;
2422
2423 urb_priv = td->urb->hcpriv;
2424 idx = urb_priv->num_tds_done;
2425 frame = &td->urb->iso_frame_desc[idx];
2426
2427 /* The transfer is partly done. */
2428 frame->status = -EXDEV;
2429
2430 /* calc actual length */
2431 frame->actual_length = 0;
2432
2433 /* Update ring dequeue pointer */
2434 ep->ring->dequeue = td->last_trb;
2435 ep->ring->deq_seg = td->last_trb_seg;
2436 ep->ring->num_trbs_free += td->num_trbs - 1;
2437 inc_deq(xhci, ep->ring);
2438
2439 return xhci_td_cleanup(xhci, td, ep->ring, status);
2440}
2441
2442/*
2443 * Process bulk and interrupt tds, update urb status and actual_length.
2444 */
2445static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2446 struct xhci_ring *ep_ring, struct xhci_td *td,
2447 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2448{
2449 struct xhci_slot_ctx *slot_ctx;
2450 u32 trb_comp_code;
2451 u32 remaining, requested, ep_trb_len;
2452
2453 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
2454 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2455 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2456 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2457 requested = td->urb->transfer_buffer_length;
2458
2459 switch (trb_comp_code) {
2460 case COMP_SUCCESS:
2461 ep->err_count = 0;
2462 /* handle success with untransferred data as short packet */
2463 if (ep_trb != td->last_trb || remaining) {
2464 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2465 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2466 td->urb->ep->desc.bEndpointAddress,
2467 requested, remaining);
2468 }
2469 td->status = 0;
2470 break;
2471 case COMP_SHORT_PACKET:
2472 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2473 td->urb->ep->desc.bEndpointAddress,
2474 requested, remaining);
2475 td->status = 0;
2476 break;
2477 case COMP_STOPPED_SHORT_PACKET:
2478 td->urb->actual_length = remaining;
2479 goto finish_td;
2480 case COMP_STOPPED_LENGTH_INVALID:
2481 /* stopped on ep trb with invalid length, exclude it */
2482 ep_trb_len = 0;
2483 remaining = 0;
2484 break;
2485 case COMP_USB_TRANSACTION_ERROR:
2486 if (xhci->quirks & XHCI_NO_SOFT_RETRY ||
2487 (ep->err_count++ > MAX_SOFT_RETRY) ||
2488 le32_to_cpu(slot_ctx->tt_info) & TT_SLOT)
2489 break;
2490
2491 td->status = 0;
2492
2493 xhci_handle_halted_endpoint(xhci, ep, td, EP_SOFT_RESET);
2494 return 0;
2495 default:
2496 /* do nothing */
2497 break;
2498 }
2499
2500 if (ep_trb == td->last_trb)
2501 td->urb->actual_length = requested - remaining;
2502 else
2503 td->urb->actual_length =
2504 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2505 ep_trb_len - remaining;
2506finish_td:
2507 if (remaining > requested) {
2508 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2509 remaining);
2510 td->urb->actual_length = 0;
2511 }
2512
2513 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2514}
2515
2516/*
2517 * If this function returns an error condition, it means it got a Transfer
2518 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2519 * At this point, the host controller is probably hosed and should be reset.
2520 */
2521static int handle_tx_event(struct xhci_hcd *xhci,
2522 struct xhci_transfer_event *event)
2523{
2524 struct xhci_virt_ep *ep;
2525 struct xhci_ring *ep_ring;
2526 unsigned int slot_id;
2527 int ep_index;
2528 struct xhci_td *td = NULL;
2529 dma_addr_t ep_trb_dma;
2530 struct xhci_segment *ep_seg;
2531 union xhci_trb *ep_trb;
2532 int status = -EINPROGRESS;
2533 struct xhci_ep_ctx *ep_ctx;
2534 struct list_head *tmp;
2535 u32 trb_comp_code;
2536 int td_num = 0;
2537 bool handling_skipped_tds = false;
2538
2539 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2540 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2541 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2542 ep_trb_dma = le64_to_cpu(event->buffer);
2543
2544 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
2545 if (!ep) {
2546 xhci_err(xhci, "ERROR Invalid Transfer event\n");
2547 goto err_out;
2548 }
2549
2550 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2551 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
2552
2553 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2554 xhci_err(xhci,
2555 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2556 slot_id, ep_index);
2557 goto err_out;
2558 }
2559
2560 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2561 if (!ep_ring) {
2562 switch (trb_comp_code) {
2563 case COMP_STALL_ERROR:
2564 case COMP_USB_TRANSACTION_ERROR:
2565 case COMP_INVALID_STREAM_TYPE_ERROR:
2566 case COMP_INVALID_STREAM_ID_ERROR:
2567 xhci_dbg(xhci, "Stream transaction error ep %u no id\n",
2568 ep_index);
2569 if (ep->err_count++ > MAX_SOFT_RETRY)
2570 xhci_handle_halted_endpoint(xhci, ep, NULL,
2571 EP_HARD_RESET);
2572 else
2573 xhci_handle_halted_endpoint(xhci, ep, NULL,
2574 EP_SOFT_RESET);
2575 goto cleanup;
2576 case COMP_RING_UNDERRUN:
2577 case COMP_RING_OVERRUN:
2578 case COMP_STOPPED_LENGTH_INVALID:
2579 goto cleanup;
2580 default:
2581 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2582 slot_id, ep_index);
2583 goto err_out;
2584 }
2585 }
2586
2587 /* Count current td numbers if ep->skip is set */
2588 if (ep->skip) {
2589 list_for_each(tmp, &ep_ring->td_list)
2590 td_num++;
2591 }
2592
2593 /* Look for common error cases */
2594 switch (trb_comp_code) {
2595 /* Skip codes that require special handling depending on
2596 * transfer type
2597 */
2598 case COMP_SUCCESS:
2599 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2600 break;
2601 if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
2602 ep_ring->last_td_was_short)
2603 trb_comp_code = COMP_SHORT_PACKET;
2604 else
2605 xhci_warn_ratelimited(xhci,
2606 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2607 slot_id, ep_index);
2608 break;
2609 case COMP_SHORT_PACKET:
2610 break;
2611 /* Completion codes for endpoint stopped state */
2612 case COMP_STOPPED:
2613 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2614 slot_id, ep_index);
2615 break;
2616 case COMP_STOPPED_LENGTH_INVALID:
2617 xhci_dbg(xhci,
2618 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2619 slot_id, ep_index);
2620 break;
2621 case COMP_STOPPED_SHORT_PACKET:
2622 xhci_dbg(xhci,
2623 "Stopped with short packet transfer detected for slot %u ep %u\n",
2624 slot_id, ep_index);
2625 break;
2626 /* Completion codes for endpoint halted state */
2627 case COMP_STALL_ERROR:
2628 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2629 ep_index);
2630 status = -EPIPE;
2631 break;
2632 case COMP_SPLIT_TRANSACTION_ERROR:
2633 xhci_dbg(xhci, "Split transaction error for slot %u ep %u\n",
2634 slot_id, ep_index);
2635 status = -EPROTO;
2636 break;
2637 case COMP_USB_TRANSACTION_ERROR:
2638 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2639 slot_id, ep_index);
2640 status = -EPROTO;
2641 break;
2642 case COMP_BABBLE_DETECTED_ERROR:
2643 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2644 slot_id, ep_index);
2645 status = -EOVERFLOW;
2646 break;
2647 /* Completion codes for endpoint error state */
2648 case COMP_TRB_ERROR:
2649 xhci_warn(xhci,
2650 "WARN: TRB error for slot %u ep %u on endpoint\n",
2651 slot_id, ep_index);
2652 status = -EILSEQ;
2653 break;
2654 /* completion codes not indicating endpoint state change */
2655 case COMP_DATA_BUFFER_ERROR:
2656 xhci_warn(xhci,
2657 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2658 slot_id, ep_index);
2659 status = -ENOSR;
2660 break;
2661 case COMP_BANDWIDTH_OVERRUN_ERROR:
2662 xhci_warn(xhci,
2663 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2664 slot_id, ep_index);
2665 break;
2666 case COMP_ISOCH_BUFFER_OVERRUN:
2667 xhci_warn(xhci,
2668 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2669 slot_id, ep_index);
2670 break;
2671 case COMP_RING_UNDERRUN:
2672 /*
2673 * When the Isoch ring is empty, the xHC will generate
2674 * a Ring Overrun Event for IN Isoch endpoint or Ring
2675 * Underrun Event for OUT Isoch endpoint.
2676 */
2677 xhci_dbg(xhci, "underrun event on endpoint\n");
2678 if (!list_empty(&ep_ring->td_list))
2679 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2680 "still with TDs queued?\n",
2681 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2682 ep_index);
2683 goto cleanup;
2684 case COMP_RING_OVERRUN:
2685 xhci_dbg(xhci, "overrun event on endpoint\n");
2686 if (!list_empty(&ep_ring->td_list))
2687 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2688 "still with TDs queued?\n",
2689 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2690 ep_index);
2691 goto cleanup;
2692 case COMP_MISSED_SERVICE_ERROR:
2693 /*
2694 * When encounter missed service error, one or more isoc tds
2695 * may be missed by xHC.
2696 * Set skip flag of the ep_ring; Complete the missed tds as
2697 * short transfer when process the ep_ring next time.
2698 */
2699 ep->skip = true;
2700 xhci_dbg(xhci,
2701 "Miss service interval error for slot %u ep %u, set skip flag\n",
2702 slot_id, ep_index);
2703 goto cleanup;
2704 case COMP_NO_PING_RESPONSE_ERROR:
2705 ep->skip = true;
2706 xhci_dbg(xhci,
2707 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2708 slot_id, ep_index);
2709 goto cleanup;
2710
2711 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2712 /* needs disable slot command to recover */
2713 xhci_warn(xhci,
2714 "WARN: detect an incompatible device for slot %u ep %u",
2715 slot_id, ep_index);
2716 status = -EPROTO;
2717 break;
2718 default:
2719 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2720 status = 0;
2721 break;
2722 }
2723 xhci_warn(xhci,
2724 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2725 trb_comp_code, slot_id, ep_index);
2726 goto cleanup;
2727 }
2728
2729 do {
2730 /* This TRB should be in the TD at the head of this ring's
2731 * TD list.
2732 */
2733 if (list_empty(&ep_ring->td_list)) {
2734 /*
2735 * Don't print wanings if it's due to a stopped endpoint
2736 * generating an extra completion event if the device
2737 * was suspended. Or, a event for the last TRB of a
2738 * short TD we already got a short event for.
2739 * The short TD is already removed from the TD list.
2740 */
2741
2742 if (!(trb_comp_code == COMP_STOPPED ||
2743 trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2744 ep_ring->last_td_was_short)) {
2745 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2746 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2747 ep_index);
2748 }
2749 if (ep->skip) {
2750 ep->skip = false;
2751 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2752 slot_id, ep_index);
2753 }
2754 if (trb_comp_code == COMP_STALL_ERROR ||
2755 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2756 trb_comp_code)) {
2757 xhci_handle_halted_endpoint(xhci, ep, NULL,
2758 EP_HARD_RESET);
2759 }
2760 goto cleanup;
2761 }
2762
2763 /* We've skipped all the TDs on the ep ring when ep->skip set */
2764 if (ep->skip && td_num == 0) {
2765 ep->skip = false;
2766 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2767 slot_id, ep_index);
2768 goto cleanup;
2769 }
2770
2771 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2772 td_list);
2773 if (ep->skip)
2774 td_num--;
2775
2776 /* Is this a TRB in the currently executing TD? */
2777 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2778 td->last_trb, ep_trb_dma, false);
2779
2780 /*
2781 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2782 * is not in the current TD pointed by ep_ring->dequeue because
2783 * that the hardware dequeue pointer still at the previous TRB
2784 * of the current TD. The previous TRB maybe a Link TD or the
2785 * last TRB of the previous TD. The command completion handle
2786 * will take care the rest.
2787 */
2788 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2789 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2790 goto cleanup;
2791 }
2792
2793 if (!ep_seg) {
2794 if (!ep->skip ||
2795 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2796 /* Some host controllers give a spurious
2797 * successful event after a short transfer.
2798 * Ignore it.
2799 */
2800 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2801 ep_ring->last_td_was_short) {
2802 ep_ring->last_td_was_short = false;
2803 goto cleanup;
2804 }
2805 /* HC is busted, give up! */
2806 xhci_err(xhci,
2807 "ERROR Transfer event TRB DMA ptr not "
2808 "part of current TD ep_index %d "
2809 "comp_code %u\n", ep_index,
2810 trb_comp_code);
2811 trb_in_td(xhci, ep_ring->deq_seg,
2812 ep_ring->dequeue, td->last_trb,
2813 ep_trb_dma, true);
2814 return -ESHUTDOWN;
2815 }
2816
2817 skip_isoc_td(xhci, td, ep, status);
2818 goto cleanup;
2819 }
2820 if (trb_comp_code == COMP_SHORT_PACKET)
2821 ep_ring->last_td_was_short = true;
2822 else
2823 ep_ring->last_td_was_short = false;
2824
2825 if (ep->skip) {
2826 xhci_dbg(xhci,
2827 "Found td. Clear skip flag for slot %u ep %u.\n",
2828 slot_id, ep_index);
2829 ep->skip = false;
2830 }
2831
2832 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2833 sizeof(*ep_trb)];
2834
2835 trace_xhci_handle_transfer(ep_ring,
2836 (struct xhci_generic_trb *) ep_trb);
2837
2838 /*
2839 * No-op TRB could trigger interrupts in a case where
2840 * a URB was killed and a STALL_ERROR happens right
2841 * after the endpoint ring stopped. Reset the halted
2842 * endpoint. Otherwise, the endpoint remains stalled
2843 * indefinitely.
2844 */
2845
2846 if (trb_is_noop(ep_trb)) {
2847 if (trb_comp_code == COMP_STALL_ERROR ||
2848 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2849 trb_comp_code))
2850 xhci_handle_halted_endpoint(xhci, ep, td,
2851 EP_HARD_RESET);
2852 goto cleanup;
2853 }
2854
2855 td->status = status;
2856
2857 /* update the urb's actual_length and give back to the core */
2858 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2859 process_ctrl_td(xhci, ep, ep_ring, td, ep_trb, event);
2860 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2861 process_isoc_td(xhci, ep, ep_ring, td, ep_trb, event);
2862 else
2863 process_bulk_intr_td(xhci, ep, ep_ring, td, ep_trb, event);
2864cleanup:
2865 handling_skipped_tds = ep->skip &&
2866 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2867 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2868
2869 /*
2870 * Do not update event ring dequeue pointer if we're in a loop
2871 * processing missed tds.
2872 */
2873 if (!handling_skipped_tds)
2874 inc_deq(xhci, xhci->event_ring);
2875
2876 /*
2877 * If ep->skip is set, it means there are missed tds on the
2878 * endpoint ring need to take care of.
2879 * Process them as short transfer until reach the td pointed by
2880 * the event.
2881 */
2882 } while (handling_skipped_tds);
2883
2884 return 0;
2885
2886err_out:
2887 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2888 (unsigned long long) xhci_trb_virt_to_dma(
2889 xhci->event_ring->deq_seg,
2890 xhci->event_ring->dequeue),
2891 lower_32_bits(le64_to_cpu(event->buffer)),
2892 upper_32_bits(le64_to_cpu(event->buffer)),
2893 le32_to_cpu(event->transfer_len),
2894 le32_to_cpu(event->flags));
2895 return -ENODEV;
2896}
2897
2898/*
2899 * This function handles all OS-owned events on the event ring. It may drop
2900 * xhci->lock between event processing (e.g. to pass up port status changes).
2901 * Returns >0 for "possibly more events to process" (caller should call again),
2902 * otherwise 0 if done. In future, <0 returns should indicate error code.
2903 */
2904static int xhci_handle_event(struct xhci_hcd *xhci)
2905{
2906 union xhci_trb *event;
2907 int update_ptrs = 1;
2908 u32 trb_type;
2909 int ret;
2910
2911 /* Event ring hasn't been allocated yet. */
2912 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2913 xhci_err(xhci, "ERROR event ring not ready\n");
2914 return -ENOMEM;
2915 }
2916
2917 event = xhci->event_ring->dequeue;
2918 /* Does the HC or OS own the TRB? */
2919 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2920 xhci->event_ring->cycle_state)
2921 return 0;
2922
2923 trace_xhci_handle_event(xhci->event_ring, &event->generic);
2924
2925 /*
2926 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2927 * speculative reads of the event's flags/data below.
2928 */
2929 rmb();
2930 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
2931 /* FIXME: Handle more event types. */
2932
2933 switch (trb_type) {
2934 case TRB_COMPLETION:
2935 handle_cmd_completion(xhci, &event->event_cmd);
2936 break;
2937 case TRB_PORT_STATUS:
2938 handle_port_status(xhci, event);
2939 update_ptrs = 0;
2940 break;
2941 case TRB_TRANSFER:
2942 ret = handle_tx_event(xhci, &event->trans_event);
2943 if (ret >= 0)
2944 update_ptrs = 0;
2945 break;
2946 case TRB_DEV_NOTE:
2947 handle_device_notification(xhci, event);
2948 break;
2949 default:
2950 if (trb_type >= TRB_VENDOR_DEFINED_LOW)
2951 handle_vendor_event(xhci, event, trb_type);
2952 else
2953 xhci_warn(xhci, "ERROR unknown event type %d\n", trb_type);
2954 }
2955 /* Any of the above functions may drop and re-acquire the lock, so check
2956 * to make sure a watchdog timer didn't mark the host as non-responsive.
2957 */
2958 if (xhci->xhc_state & XHCI_STATE_DYING) {
2959 xhci_dbg(xhci, "xHCI host dying, returning from "
2960 "event handler.\n");
2961 return 0;
2962 }
2963
2964 if (update_ptrs)
2965 /* Update SW event ring dequeue pointer */
2966 inc_deq(xhci, xhci->event_ring);
2967
2968 /* Are there more items on the event ring? Caller will call us again to
2969 * check.
2970 */
2971 return 1;
2972}
2973
2974/*
2975 * Update Event Ring Dequeue Pointer:
2976 * - When all events have finished
2977 * - To avoid "Event Ring Full Error" condition
2978 */
2979static void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
2980 union xhci_trb *event_ring_deq)
2981{
2982 u64 temp_64;
2983 dma_addr_t deq;
2984
2985 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2986 /* If necessary, update the HW's version of the event ring deq ptr. */
2987 if (event_ring_deq != xhci->event_ring->dequeue) {
2988 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2989 xhci->event_ring->dequeue);
2990 if (deq == 0)
2991 xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n");
2992 /*
2993 * Per 4.9.4, Software writes to the ERDP register shall
2994 * always advance the Event Ring Dequeue Pointer value.
2995 */
2996 if ((temp_64 & (u64) ~ERST_PTR_MASK) ==
2997 ((u64) deq & (u64) ~ERST_PTR_MASK))
2998 return;
2999
3000 /* Update HC event ring dequeue pointer */
3001 temp_64 &= ERST_PTR_MASK;
3002 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
3003 }
3004
3005 /* Clear the event handler busy flag (RW1C) */
3006 temp_64 |= ERST_EHB;
3007 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
3008}
3009
3010/*
3011 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
3012 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
3013 * indicators of an event TRB error, but we check the status *first* to be safe.
3014 */
3015irqreturn_t xhci_irq(struct usb_hcd *hcd)
3016{
3017 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3018 union xhci_trb *event_ring_deq;
3019 irqreturn_t ret = IRQ_NONE;
3020 u64 temp_64;
3021 u32 status;
3022 int event_loop = 0;
3023
3024 spin_lock(&xhci->lock);
3025 /* Check if the xHC generated the interrupt, or the irq is shared */
3026 status = readl(&xhci->op_regs->status);
3027 if (status == ~(u32)0) {
3028 xhci_hc_died(xhci);
3029 ret = IRQ_HANDLED;
3030 goto out;
3031 }
3032
3033 if (!(status & STS_EINT))
3034 goto out;
3035
3036 if (status & STS_HCE) {
3037 xhci_warn(xhci, "WARNING: Host Controller Error\n");
3038 goto out;
3039 }
3040
3041 if (status & STS_FATAL) {
3042 xhci_warn(xhci, "WARNING: Host System Error\n");
3043 xhci_halt(xhci);
3044 ret = IRQ_HANDLED;
3045 goto out;
3046 }
3047
3048 /*
3049 * Clear the op reg interrupt status first,
3050 * so we can receive interrupts from other MSI-X interrupters.
3051 * Write 1 to clear the interrupt status.
3052 */
3053 status |= STS_EINT;
3054 writel(status, &xhci->op_regs->status);
3055
3056 if (!hcd->msi_enabled) {
3057 u32 irq_pending;
3058 irq_pending = readl(&xhci->ir_set->irq_pending);
3059 irq_pending |= IMAN_IP;
3060 writel(irq_pending, &xhci->ir_set->irq_pending);
3061 }
3062
3063 if (xhci->xhc_state & XHCI_STATE_DYING ||
3064 xhci->xhc_state & XHCI_STATE_HALTED) {
3065 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
3066 "Shouldn't IRQs be disabled?\n");
3067 /* Clear the event handler busy flag (RW1C);
3068 * the event ring should be empty.
3069 */
3070 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
3071 xhci_write_64(xhci, temp_64 | ERST_EHB,
3072 &xhci->ir_set->erst_dequeue);
3073 ret = IRQ_HANDLED;
3074 goto out;
3075 }
3076
3077 event_ring_deq = xhci->event_ring->dequeue;
3078 /* FIXME this should be a delayed service routine
3079 * that clears the EHB.
3080 */
3081 while (xhci_handle_event(xhci) > 0) {
3082 if (event_loop++ < TRBS_PER_SEGMENT / 2)
3083 continue;
3084 xhci_update_erst_dequeue(xhci, event_ring_deq);
3085 event_ring_deq = xhci->event_ring->dequeue;
3086
3087 /* ring is half-full, force isoc trbs to interrupt more often */
3088 if (xhci->isoc_bei_interval > AVOID_BEI_INTERVAL_MIN)
3089 xhci->isoc_bei_interval = xhci->isoc_bei_interval / 2;
3090
3091 event_loop = 0;
3092 }
3093
3094 xhci_update_erst_dequeue(xhci, event_ring_deq);
3095 ret = IRQ_HANDLED;
3096
3097out:
3098 spin_unlock(&xhci->lock);
3099
3100 return ret;
3101}
3102
3103irqreturn_t xhci_msi_irq(int irq, void *hcd)
3104{
3105 return xhci_irq(hcd);
3106}
3107
3108/**** Endpoint Ring Operations ****/
3109
3110/*
3111 * Generic function for queueing a TRB on a ring.
3112 * The caller must have checked to make sure there's room on the ring.
3113 *
3114 * @more_trbs_coming: Will you enqueue more TRBs before calling
3115 * prepare_transfer()?
3116 */
3117static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
3118 bool more_trbs_coming,
3119 u32 field1, u32 field2, u32 field3, u32 field4)
3120{
3121 struct xhci_generic_trb *trb;
3122
3123 trb = &ring->enqueue->generic;
3124 trb->field[0] = cpu_to_le32(field1);
3125 trb->field[1] = cpu_to_le32(field2);
3126 trb->field[2] = cpu_to_le32(field3);
3127 /* make sure TRB is fully written before giving it to the controller */
3128 wmb();
3129 trb->field[3] = cpu_to_le32(field4);
3130
3131 trace_xhci_queue_trb(ring, trb);
3132
3133 inc_enq(xhci, ring, more_trbs_coming);
3134}
3135
3136/*
3137 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
3138 * FIXME allocate segments if the ring is full.
3139 */
3140static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
3141 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
3142{
3143 unsigned int num_trbs_needed;
3144 unsigned int link_trb_count = 0;
3145
3146 /* Make sure the endpoint has been added to xHC schedule */
3147 switch (ep_state) {
3148 case EP_STATE_DISABLED:
3149 /*
3150 * USB core changed config/interfaces without notifying us,
3151 * or hardware is reporting the wrong state.
3152 */
3153 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
3154 return -ENOENT;
3155 case EP_STATE_ERROR:
3156 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
3157 /* FIXME event handling code for error needs to clear it */
3158 /* XXX not sure if this should be -ENOENT or not */
3159 return -EINVAL;
3160 case EP_STATE_HALTED:
3161 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
3162 break;
3163 case EP_STATE_STOPPED:
3164 case EP_STATE_RUNNING:
3165 break;
3166 default:
3167 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
3168 /*
3169 * FIXME issue Configure Endpoint command to try to get the HC
3170 * back into a known state.
3171 */
3172 return -EINVAL;
3173 }
3174
3175 while (1) {
3176 if (room_on_ring(xhci, ep_ring, num_trbs))
3177 break;
3178
3179 if (ep_ring == xhci->cmd_ring) {
3180 xhci_err(xhci, "Do not support expand command ring\n");
3181 return -ENOMEM;
3182 }
3183
3184 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
3185 "ERROR no room on ep ring, try ring expansion");
3186 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
3187 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
3188 mem_flags)) {
3189 xhci_err(xhci, "Ring expansion failed\n");
3190 return -ENOMEM;
3191 }
3192 }
3193
3194 while (trb_is_link(ep_ring->enqueue)) {
3195 /* If we're not dealing with 0.95 hardware or isoc rings
3196 * on AMD 0.96 host, clear the chain bit.
3197 */
3198 if (!xhci_link_trb_quirk(xhci) &&
3199 !(ep_ring->type == TYPE_ISOC &&
3200 (xhci->quirks & XHCI_AMD_0x96_HOST)))
3201 ep_ring->enqueue->link.control &=
3202 cpu_to_le32(~TRB_CHAIN);
3203 else
3204 ep_ring->enqueue->link.control |=
3205 cpu_to_le32(TRB_CHAIN);
3206
3207 wmb();
3208 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
3209
3210 /* Toggle the cycle bit after the last ring segment. */
3211 if (link_trb_toggles_cycle(ep_ring->enqueue))
3212 ep_ring->cycle_state ^= 1;
3213
3214 ep_ring->enq_seg = ep_ring->enq_seg->next;
3215 ep_ring->enqueue = ep_ring->enq_seg->trbs;
3216
3217 /* prevent infinite loop if all first trbs are link trbs */
3218 if (link_trb_count++ > ep_ring->num_segs) {
3219 xhci_warn(xhci, "Ring is an endless link TRB loop\n");
3220 return -EINVAL;
3221 }
3222 }
3223
3224 if (last_trb_on_seg(ep_ring->enq_seg, ep_ring->enqueue)) {
3225 xhci_warn(xhci, "Missing link TRB at end of ring segment\n");
3226 return -EINVAL;
3227 }
3228
3229 return 0;
3230}
3231
3232static int prepare_transfer(struct xhci_hcd *xhci,
3233 struct xhci_virt_device *xdev,
3234 unsigned int ep_index,
3235 unsigned int stream_id,
3236 unsigned int num_trbs,
3237 struct urb *urb,
3238 unsigned int td_index,
3239 gfp_t mem_flags)
3240{
3241 int ret;
3242 struct urb_priv *urb_priv;
3243 struct xhci_td *td;
3244 struct xhci_ring *ep_ring;
3245 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3246
3247 ep_ring = xhci_triad_to_transfer_ring(xhci, xdev->slot_id, ep_index,
3248 stream_id);
3249 if (!ep_ring) {
3250 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3251 stream_id);
3252 return -EINVAL;
3253 }
3254
3255 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3256 num_trbs, mem_flags);
3257 if (ret)
3258 return ret;
3259
3260 urb_priv = urb->hcpriv;
3261 td = &urb_priv->td[td_index];
3262
3263 INIT_LIST_HEAD(&td->td_list);
3264 INIT_LIST_HEAD(&td->cancelled_td_list);
3265
3266 if (td_index == 0) {
3267 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3268 if (unlikely(ret))
3269 return ret;
3270 }
3271
3272 td->urb = urb;
3273 /* Add this TD to the tail of the endpoint ring's TD list */
3274 list_add_tail(&td->td_list, &ep_ring->td_list);
3275 td->start_seg = ep_ring->enq_seg;
3276 td->first_trb = ep_ring->enqueue;
3277
3278 return 0;
3279}
3280
3281unsigned int count_trbs(u64 addr, u64 len)
3282{
3283 unsigned int num_trbs;
3284
3285 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3286 TRB_MAX_BUFF_SIZE);
3287 if (num_trbs == 0)
3288 num_trbs++;
3289
3290 return num_trbs;
3291}
3292
3293static inline unsigned int count_trbs_needed(struct urb *urb)
3294{
3295 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3296}
3297
3298static unsigned int count_sg_trbs_needed(struct urb *urb)
3299{
3300 struct scatterlist *sg;
3301 unsigned int i, len, full_len, num_trbs = 0;
3302
3303 full_len = urb->transfer_buffer_length;
3304
3305 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3306 len = sg_dma_len(sg);
3307 num_trbs += count_trbs(sg_dma_address(sg), len);
3308 len = min_t(unsigned int, len, full_len);
3309 full_len -= len;
3310 if (full_len == 0)
3311 break;
3312 }
3313
3314 return num_trbs;
3315}
3316
3317static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3318{
3319 u64 addr, len;
3320
3321 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3322 len = urb->iso_frame_desc[i].length;
3323
3324 return count_trbs(addr, len);
3325}
3326
3327static void check_trb_math(struct urb *urb, int running_total)
3328{
3329 if (unlikely(running_total != urb->transfer_buffer_length))
3330 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3331 "queued %#x (%d), asked for %#x (%d)\n",
3332 __func__,
3333 urb->ep->desc.bEndpointAddress,
3334 running_total, running_total,
3335 urb->transfer_buffer_length,
3336 urb->transfer_buffer_length);
3337}
3338
3339static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3340 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3341 struct xhci_generic_trb *start_trb)
3342{
3343 /*
3344 * Pass all the TRBs to the hardware at once and make sure this write
3345 * isn't reordered.
3346 */
3347 wmb();
3348 if (start_cycle)
3349 start_trb->field[3] |= cpu_to_le32(start_cycle);
3350 else
3351 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3352 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3353}
3354
3355static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3356 struct xhci_ep_ctx *ep_ctx)
3357{
3358 int xhci_interval;
3359 int ep_interval;
3360
3361 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3362 ep_interval = urb->interval;
3363
3364 /* Convert to microframes */
3365 if (urb->dev->speed == USB_SPEED_LOW ||
3366 urb->dev->speed == USB_SPEED_FULL)
3367 ep_interval *= 8;
3368
3369 /* FIXME change this to a warning and a suggestion to use the new API
3370 * to set the polling interval (once the API is added).
3371 */
3372 if (xhci_interval != ep_interval) {
3373 dev_dbg_ratelimited(&urb->dev->dev,
3374 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3375 ep_interval, ep_interval == 1 ? "" : "s",
3376 xhci_interval, xhci_interval == 1 ? "" : "s");
3377 urb->interval = xhci_interval;
3378 /* Convert back to frames for LS/FS devices */
3379 if (urb->dev->speed == USB_SPEED_LOW ||
3380 urb->dev->speed == USB_SPEED_FULL)
3381 urb->interval /= 8;
3382 }
3383}
3384
3385/*
3386 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3387 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3388 * (comprised of sg list entries) can take several service intervals to
3389 * transmit.
3390 */
3391int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3392 struct urb *urb, int slot_id, unsigned int ep_index)
3393{
3394 struct xhci_ep_ctx *ep_ctx;
3395
3396 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3397 check_interval(xhci, urb, ep_ctx);
3398
3399 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3400}
3401
3402/*
3403 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3404 * packets remaining in the TD (*not* including this TRB).
3405 *
3406 * Total TD packet count = total_packet_count =
3407 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3408 *
3409 * Packets transferred up to and including this TRB = packets_transferred =
3410 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3411 *
3412 * TD size = total_packet_count - packets_transferred
3413 *
3414 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3415 * including this TRB, right shifted by 10
3416 *
3417 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3418 * This is taken care of in the TRB_TD_SIZE() macro
3419 *
3420 * The last TRB in a TD must have the TD size set to zero.
3421 */
3422static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3423 int trb_buff_len, unsigned int td_total_len,
3424 struct urb *urb, bool more_trbs_coming)
3425{
3426 u32 maxp, total_packet_count;
3427
3428 /* MTK xHCI 0.96 contains some features from 1.0 */
3429 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3430 return ((td_total_len - transferred) >> 10);
3431
3432 /* One TRB with a zero-length data packet. */
3433 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3434 trb_buff_len == td_total_len)
3435 return 0;
3436
3437 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3438 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3439 trb_buff_len = 0;
3440
3441 maxp = usb_endpoint_maxp(&urb->ep->desc);
3442 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3443
3444 /* Queueing functions don't count the current TRB into transferred */
3445 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3446}
3447
3448
3449static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3450 u32 *trb_buff_len, struct xhci_segment *seg)
3451{
3452 struct device *dev = xhci_to_hcd(xhci)->self.controller;
3453 unsigned int unalign;
3454 unsigned int max_pkt;
3455 u32 new_buff_len;
3456 size_t len;
3457
3458 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3459 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3460
3461 /* we got lucky, last normal TRB data on segment is packet aligned */
3462 if (unalign == 0)
3463 return 0;
3464
3465 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3466 unalign, *trb_buff_len);
3467
3468 /* is the last nornal TRB alignable by splitting it */
3469 if (*trb_buff_len > unalign) {
3470 *trb_buff_len -= unalign;
3471 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3472 return 0;
3473 }
3474
3475 /*
3476 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3477 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3478 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3479 */
3480 new_buff_len = max_pkt - (enqd_len % max_pkt);
3481
3482 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3483 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3484
3485 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3486 if (usb_urb_dir_out(urb)) {
3487 if (urb->num_sgs) {
3488 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3489 seg->bounce_buf, new_buff_len, enqd_len);
3490 if (len != new_buff_len)
3491 xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n",
3492 len, new_buff_len);
3493 } else {
3494 memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len);
3495 }
3496
3497 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3498 max_pkt, DMA_TO_DEVICE);
3499 } else {
3500 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3501 max_pkt, DMA_FROM_DEVICE);
3502 }
3503
3504 if (dma_mapping_error(dev, seg->bounce_dma)) {
3505 /* try without aligning. Some host controllers survive */
3506 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3507 return 0;
3508 }
3509 *trb_buff_len = new_buff_len;
3510 seg->bounce_len = new_buff_len;
3511 seg->bounce_offs = enqd_len;
3512
3513 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3514
3515 return 1;
3516}
3517
3518/* This is very similar to what ehci-q.c qtd_fill() does */
3519int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3520 struct urb *urb, int slot_id, unsigned int ep_index)
3521{
3522 struct xhci_ring *ring;
3523 struct urb_priv *urb_priv;
3524 struct xhci_td *td;
3525 struct xhci_generic_trb *start_trb;
3526 struct scatterlist *sg = NULL;
3527 bool more_trbs_coming = true;
3528 bool need_zero_pkt = false;
3529 bool first_trb = true;
3530 unsigned int num_trbs;
3531 unsigned int start_cycle, num_sgs = 0;
3532 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3533 int sent_len, ret;
3534 u32 field, length_field, remainder;
3535 u64 addr, send_addr;
3536
3537 ring = xhci_urb_to_transfer_ring(xhci, urb);
3538 if (!ring)
3539 return -EINVAL;
3540
3541 full_len = urb->transfer_buffer_length;
3542 /* If we have scatter/gather list, we use it. */
3543 if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) {
3544 num_sgs = urb->num_mapped_sgs;
3545 sg = urb->sg;
3546 addr = (u64) sg_dma_address(sg);
3547 block_len = sg_dma_len(sg);
3548 num_trbs = count_sg_trbs_needed(urb);
3549 } else {
3550 num_trbs = count_trbs_needed(urb);
3551 addr = (u64) urb->transfer_dma;
3552 block_len = full_len;
3553 }
3554 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3555 ep_index, urb->stream_id,
3556 num_trbs, urb, 0, mem_flags);
3557 if (unlikely(ret < 0))
3558 return ret;
3559
3560 urb_priv = urb->hcpriv;
3561
3562 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3563 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3564 need_zero_pkt = true;
3565
3566 td = &urb_priv->td[0];
3567
3568 /*
3569 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3570 * until we've finished creating all the other TRBs. The ring's cycle
3571 * state may change as we enqueue the other TRBs, so save it too.
3572 */
3573 start_trb = &ring->enqueue->generic;
3574 start_cycle = ring->cycle_state;
3575 send_addr = addr;
3576
3577 /* Queue the TRBs, even if they are zero-length */
3578 for (enqd_len = 0; first_trb || enqd_len < full_len;
3579 enqd_len += trb_buff_len) {
3580 field = TRB_TYPE(TRB_NORMAL);
3581
3582 /* TRB buffer should not cross 64KB boundaries */
3583 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3584 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3585
3586 if (enqd_len + trb_buff_len > full_len)
3587 trb_buff_len = full_len - enqd_len;
3588
3589 /* Don't change the cycle bit of the first TRB until later */
3590 if (first_trb) {
3591 first_trb = false;
3592 if (start_cycle == 0)
3593 field |= TRB_CYCLE;
3594 } else
3595 field |= ring->cycle_state;
3596
3597 /* Chain all the TRBs together; clear the chain bit in the last
3598 * TRB to indicate it's the last TRB in the chain.
3599 */
3600 if (enqd_len + trb_buff_len < full_len) {
3601 field |= TRB_CHAIN;
3602 if (trb_is_link(ring->enqueue + 1)) {
3603 if (xhci_align_td(xhci, urb, enqd_len,
3604 &trb_buff_len,
3605 ring->enq_seg)) {
3606 send_addr = ring->enq_seg->bounce_dma;
3607 /* assuming TD won't span 2 segs */
3608 td->bounce_seg = ring->enq_seg;
3609 }
3610 }
3611 }
3612 if (enqd_len + trb_buff_len >= full_len) {
3613 field &= ~TRB_CHAIN;
3614 field |= TRB_IOC;
3615 more_trbs_coming = false;
3616 td->last_trb = ring->enqueue;
3617 td->last_trb_seg = ring->enq_seg;
3618 if (xhci_urb_suitable_for_idt(urb)) {
3619 memcpy(&send_addr, urb->transfer_buffer,
3620 trb_buff_len);
3621 le64_to_cpus(&send_addr);
3622 field |= TRB_IDT;
3623 }
3624 }
3625
3626 /* Only set interrupt on short packet for IN endpoints */
3627 if (usb_urb_dir_in(urb))
3628 field |= TRB_ISP;
3629
3630 /* Set the TRB length, TD size, and interrupter fields. */
3631 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3632 full_len, urb, more_trbs_coming);
3633
3634 length_field = TRB_LEN(trb_buff_len) |
3635 TRB_TD_SIZE(remainder) |
3636 TRB_INTR_TARGET(0);
3637
3638 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3639 lower_32_bits(send_addr),
3640 upper_32_bits(send_addr),
3641 length_field,
3642 field);
3643 td->num_trbs++;
3644 addr += trb_buff_len;
3645 sent_len = trb_buff_len;
3646
3647 while (sg && sent_len >= block_len) {
3648 /* New sg entry */
3649 --num_sgs;
3650 sent_len -= block_len;
3651 sg = sg_next(sg);
3652 if (num_sgs != 0 && sg) {
3653 block_len = sg_dma_len(sg);
3654 addr = (u64) sg_dma_address(sg);
3655 addr += sent_len;
3656 }
3657 }
3658 block_len -= sent_len;
3659 send_addr = addr;
3660 }
3661
3662 if (need_zero_pkt) {
3663 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3664 ep_index, urb->stream_id,
3665 1, urb, 1, mem_flags);
3666 urb_priv->td[1].last_trb = ring->enqueue;
3667 urb_priv->td[1].last_trb_seg = ring->enq_seg;
3668 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3669 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3670 urb_priv->td[1].num_trbs++;
3671 }
3672
3673 check_trb_math(urb, enqd_len);
3674 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3675 start_cycle, start_trb);
3676 return 0;
3677}
3678
3679/* Caller must have locked xhci->lock */
3680int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3681 struct urb *urb, int slot_id, unsigned int ep_index)
3682{
3683 struct xhci_ring *ep_ring;
3684 int num_trbs;
3685 int ret;
3686 struct usb_ctrlrequest *setup;
3687 struct xhci_generic_trb *start_trb;
3688 int start_cycle;
3689 u32 field;
3690 struct urb_priv *urb_priv;
3691 struct xhci_td *td;
3692
3693 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3694 if (!ep_ring)
3695 return -EINVAL;
3696
3697 /*
3698 * Need to copy setup packet into setup TRB, so we can't use the setup
3699 * DMA address.
3700 */
3701 if (!urb->setup_packet)
3702 return -EINVAL;
3703
3704 /* 1 TRB for setup, 1 for status */
3705 num_trbs = 2;
3706 /*
3707 * Don't need to check if we need additional event data and normal TRBs,
3708 * since data in control transfers will never get bigger than 16MB
3709 * XXX: can we get a buffer that crosses 64KB boundaries?
3710 */
3711 if (urb->transfer_buffer_length > 0)
3712 num_trbs++;
3713 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3714 ep_index, urb->stream_id,
3715 num_trbs, urb, 0, mem_flags);
3716 if (ret < 0)
3717 return ret;
3718
3719 urb_priv = urb->hcpriv;
3720 td = &urb_priv->td[0];
3721 td->num_trbs = num_trbs;
3722
3723 /*
3724 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3725 * until we've finished creating all the other TRBs. The ring's cycle
3726 * state may change as we enqueue the other TRBs, so save it too.
3727 */
3728 start_trb = &ep_ring->enqueue->generic;
3729 start_cycle = ep_ring->cycle_state;
3730
3731 /* Queue setup TRB - see section 6.4.1.2.1 */
3732 /* FIXME better way to translate setup_packet into two u32 fields? */
3733 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3734 field = 0;
3735 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3736 if (start_cycle == 0)
3737 field |= 0x1;
3738
3739 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3740 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3741 if (urb->transfer_buffer_length > 0) {
3742 if (setup->bRequestType & USB_DIR_IN)
3743 field |= TRB_TX_TYPE(TRB_DATA_IN);
3744 else
3745 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3746 }
3747 }
3748
3749 queue_trb(xhci, ep_ring, true,
3750 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3751 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3752 TRB_LEN(8) | TRB_INTR_TARGET(0),
3753 /* Immediate data in pointer */
3754 field);
3755
3756 /* If there's data, queue data TRBs */
3757 /* Only set interrupt on short packet for IN endpoints */
3758 if (usb_urb_dir_in(urb))
3759 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3760 else
3761 field = TRB_TYPE(TRB_DATA);
3762
3763 if (urb->transfer_buffer_length > 0) {
3764 u32 length_field, remainder;
3765 u64 addr;
3766
3767 if (xhci_urb_suitable_for_idt(urb)) {
3768 memcpy(&addr, urb->transfer_buffer,
3769 urb->transfer_buffer_length);
3770 le64_to_cpus(&addr);
3771 field |= TRB_IDT;
3772 } else {
3773 addr = (u64) urb->transfer_dma;
3774 }
3775
3776 remainder = xhci_td_remainder(xhci, 0,
3777 urb->transfer_buffer_length,
3778 urb->transfer_buffer_length,
3779 urb, 1);
3780 length_field = TRB_LEN(urb->transfer_buffer_length) |
3781 TRB_TD_SIZE(remainder) |
3782 TRB_INTR_TARGET(0);
3783 if (setup->bRequestType & USB_DIR_IN)
3784 field |= TRB_DIR_IN;
3785 queue_trb(xhci, ep_ring, true,
3786 lower_32_bits(addr),
3787 upper_32_bits(addr),
3788 length_field,
3789 field | ep_ring->cycle_state);
3790 }
3791
3792 /* Save the DMA address of the last TRB in the TD */
3793 td->last_trb = ep_ring->enqueue;
3794 td->last_trb_seg = ep_ring->enq_seg;
3795
3796 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3797 /* If the device sent data, the status stage is an OUT transfer */
3798 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3799 field = 0;
3800 else
3801 field = TRB_DIR_IN;
3802 queue_trb(xhci, ep_ring, false,
3803 0,
3804 0,
3805 TRB_INTR_TARGET(0),
3806 /* Event on completion */
3807 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3808
3809 giveback_first_trb(xhci, slot_id, ep_index, 0,
3810 start_cycle, start_trb);
3811 return 0;
3812}
3813
3814/*
3815 * The transfer burst count field of the isochronous TRB defines the number of
3816 * bursts that are required to move all packets in this TD. Only SuperSpeed
3817 * devices can burst up to bMaxBurst number of packets per service interval.
3818 * This field is zero based, meaning a value of zero in the field means one
3819 * burst. Basically, for everything but SuperSpeed devices, this field will be
3820 * zero. Only xHCI 1.0 host controllers support this field.
3821 */
3822static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3823 struct urb *urb, unsigned int total_packet_count)
3824{
3825 unsigned int max_burst;
3826
3827 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3828 return 0;
3829
3830 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3831 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3832}
3833
3834/*
3835 * Returns the number of packets in the last "burst" of packets. This field is
3836 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3837 * the last burst packet count is equal to the total number of packets in the
3838 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3839 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3840 * contain 1 to (bMaxBurst + 1) packets.
3841 */
3842static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3843 struct urb *urb, unsigned int total_packet_count)
3844{
3845 unsigned int max_burst;
3846 unsigned int residue;
3847
3848 if (xhci->hci_version < 0x100)
3849 return 0;
3850
3851 if (urb->dev->speed >= USB_SPEED_SUPER) {
3852 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3853 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3854 residue = total_packet_count % (max_burst + 1);
3855 /* If residue is zero, the last burst contains (max_burst + 1)
3856 * number of packets, but the TLBPC field is zero-based.
3857 */
3858 if (residue == 0)
3859 return max_burst;
3860 return residue - 1;
3861 }
3862 if (total_packet_count == 0)
3863 return 0;
3864 return total_packet_count - 1;
3865}
3866
3867/*
3868 * Calculates Frame ID field of the isochronous TRB identifies the
3869 * target frame that the Interval associated with this Isochronous
3870 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3871 *
3872 * Returns actual frame id on success, negative value on error.
3873 */
3874static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3875 struct urb *urb, int index)
3876{
3877 int start_frame, ist, ret = 0;
3878 int start_frame_id, end_frame_id, current_frame_id;
3879
3880 if (urb->dev->speed == USB_SPEED_LOW ||
3881 urb->dev->speed == USB_SPEED_FULL)
3882 start_frame = urb->start_frame + index * urb->interval;
3883 else
3884 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3885
3886 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3887 *
3888 * If bit [3] of IST is cleared to '0', software can add a TRB no
3889 * later than IST[2:0] Microframes before that TRB is scheduled to
3890 * be executed.
3891 * If bit [3] of IST is set to '1', software can add a TRB no later
3892 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3893 */
3894 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3895 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3896 ist <<= 3;
3897
3898 /* Software shall not schedule an Isoch TD with a Frame ID value that
3899 * is less than the Start Frame ID or greater than the End Frame ID,
3900 * where:
3901 *
3902 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3903 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3904 *
3905 * Both the End Frame ID and Start Frame ID values are calculated
3906 * in microframes. When software determines the valid Frame ID value;
3907 * The End Frame ID value should be rounded down to the nearest Frame
3908 * boundary, and the Start Frame ID value should be rounded up to the
3909 * nearest Frame boundary.
3910 */
3911 current_frame_id = readl(&xhci->run_regs->microframe_index);
3912 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3913 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3914
3915 start_frame &= 0x7ff;
3916 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3917 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3918
3919 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3920 __func__, index, readl(&xhci->run_regs->microframe_index),
3921 start_frame_id, end_frame_id, start_frame);
3922
3923 if (start_frame_id < end_frame_id) {
3924 if (start_frame > end_frame_id ||
3925 start_frame < start_frame_id)
3926 ret = -EINVAL;
3927 } else if (start_frame_id > end_frame_id) {
3928 if ((start_frame > end_frame_id &&
3929 start_frame < start_frame_id))
3930 ret = -EINVAL;
3931 } else {
3932 ret = -EINVAL;
3933 }
3934
3935 if (index == 0) {
3936 if (ret == -EINVAL || start_frame == start_frame_id) {
3937 start_frame = start_frame_id + 1;
3938 if (urb->dev->speed == USB_SPEED_LOW ||
3939 urb->dev->speed == USB_SPEED_FULL)
3940 urb->start_frame = start_frame;
3941 else
3942 urb->start_frame = start_frame << 3;
3943 ret = 0;
3944 }
3945 }
3946
3947 if (ret) {
3948 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3949 start_frame, current_frame_id, index,
3950 start_frame_id, end_frame_id);
3951 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3952 return ret;
3953 }
3954
3955 return start_frame;
3956}
3957
3958/* Check if we should generate event interrupt for a TD in an isoc URB */
3959static bool trb_block_event_intr(struct xhci_hcd *xhci, int num_tds, int i)
3960{
3961 if (xhci->hci_version < 0x100)
3962 return false;
3963 /* always generate an event interrupt for the last TD */
3964 if (i == num_tds - 1)
3965 return false;
3966 /*
3967 * If AVOID_BEI is set the host handles full event rings poorly,
3968 * generate an event at least every 8th TD to clear the event ring
3969 */
3970 if (i && xhci->quirks & XHCI_AVOID_BEI)
3971 return !!(i % xhci->isoc_bei_interval);
3972
3973 return true;
3974}
3975
3976/* This is for isoc transfer */
3977static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3978 struct urb *urb, int slot_id, unsigned int ep_index)
3979{
3980 struct xhci_ring *ep_ring;
3981 struct urb_priv *urb_priv;
3982 struct xhci_td *td;
3983 int num_tds, trbs_per_td;
3984 struct xhci_generic_trb *start_trb;
3985 bool first_trb;
3986 int start_cycle;
3987 u32 field, length_field;
3988 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3989 u64 start_addr, addr;
3990 int i, j;
3991 bool more_trbs_coming;
3992 struct xhci_virt_ep *xep;
3993 int frame_id;
3994
3995 xep = &xhci->devs[slot_id]->eps[ep_index];
3996 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3997
3998 num_tds = urb->number_of_packets;
3999 if (num_tds < 1) {
4000 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
4001 return -EINVAL;
4002 }
4003 start_addr = (u64) urb->transfer_dma;
4004 start_trb = &ep_ring->enqueue->generic;
4005 start_cycle = ep_ring->cycle_state;
4006
4007 urb_priv = urb->hcpriv;
4008 /* Queue the TRBs for each TD, even if they are zero-length */
4009 for (i = 0; i < num_tds; i++) {
4010 unsigned int total_pkt_count, max_pkt;
4011 unsigned int burst_count, last_burst_pkt_count;
4012 u32 sia_frame_id;
4013
4014 first_trb = true;
4015 running_total = 0;
4016 addr = start_addr + urb->iso_frame_desc[i].offset;
4017 td_len = urb->iso_frame_desc[i].length;
4018 td_remain_len = td_len;
4019 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
4020 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
4021
4022 /* A zero-length transfer still involves at least one packet. */
4023 if (total_pkt_count == 0)
4024 total_pkt_count++;
4025 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
4026 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
4027 urb, total_pkt_count);
4028
4029 trbs_per_td = count_isoc_trbs_needed(urb, i);
4030
4031 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
4032 urb->stream_id, trbs_per_td, urb, i, mem_flags);
4033 if (ret < 0) {
4034 if (i == 0)
4035 return ret;
4036 goto cleanup;
4037 }
4038 td = &urb_priv->td[i];
4039 td->num_trbs = trbs_per_td;
4040 /* use SIA as default, if frame id is used overwrite it */
4041 sia_frame_id = TRB_SIA;
4042 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
4043 HCC_CFC(xhci->hcc_params)) {
4044 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
4045 if (frame_id >= 0)
4046 sia_frame_id = TRB_FRAME_ID(frame_id);
4047 }
4048 /*
4049 * Set isoc specific data for the first TRB in a TD.
4050 * Prevent HW from getting the TRBs by keeping the cycle state
4051 * inverted in the first TDs isoc TRB.
4052 */
4053 field = TRB_TYPE(TRB_ISOC) |
4054 TRB_TLBPC(last_burst_pkt_count) |
4055 sia_frame_id |
4056 (i ? ep_ring->cycle_state : !start_cycle);
4057
4058 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
4059 if (!xep->use_extended_tbc)
4060 field |= TRB_TBC(burst_count);
4061
4062 /* fill the rest of the TRB fields, and remaining normal TRBs */
4063 for (j = 0; j < trbs_per_td; j++) {
4064 u32 remainder = 0;
4065
4066 /* only first TRB is isoc, overwrite otherwise */
4067 if (!first_trb)
4068 field = TRB_TYPE(TRB_NORMAL) |
4069 ep_ring->cycle_state;
4070
4071 /* Only set interrupt on short packet for IN EPs */
4072 if (usb_urb_dir_in(urb))
4073 field |= TRB_ISP;
4074
4075 /* Set the chain bit for all except the last TRB */
4076 if (j < trbs_per_td - 1) {
4077 more_trbs_coming = true;
4078 field |= TRB_CHAIN;
4079 } else {
4080 more_trbs_coming = false;
4081 td->last_trb = ep_ring->enqueue;
4082 td->last_trb_seg = ep_ring->enq_seg;
4083 field |= TRB_IOC;
4084 if (trb_block_event_intr(xhci, num_tds, i))
4085 field |= TRB_BEI;
4086 }
4087 /* Calculate TRB length */
4088 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
4089 if (trb_buff_len > td_remain_len)
4090 trb_buff_len = td_remain_len;
4091
4092 /* Set the TRB length, TD size, & interrupter fields. */
4093 remainder = xhci_td_remainder(xhci, running_total,
4094 trb_buff_len, td_len,
4095 urb, more_trbs_coming);
4096
4097 length_field = TRB_LEN(trb_buff_len) |
4098 TRB_INTR_TARGET(0);
4099
4100 /* xhci 1.1 with ETE uses TD Size field for TBC */
4101 if (first_trb && xep->use_extended_tbc)
4102 length_field |= TRB_TD_SIZE_TBC(burst_count);
4103 else
4104 length_field |= TRB_TD_SIZE(remainder);
4105 first_trb = false;
4106
4107 queue_trb(xhci, ep_ring, more_trbs_coming,
4108 lower_32_bits(addr),
4109 upper_32_bits(addr),
4110 length_field,
4111 field);
4112 running_total += trb_buff_len;
4113
4114 addr += trb_buff_len;
4115 td_remain_len -= trb_buff_len;
4116 }
4117
4118 /* Check TD length */
4119 if (running_total != td_len) {
4120 xhci_err(xhci, "ISOC TD length unmatch\n");
4121 ret = -EINVAL;
4122 goto cleanup;
4123 }
4124 }
4125
4126 /* store the next frame id */
4127 if (HCC_CFC(xhci->hcc_params))
4128 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
4129
4130 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
4131 if (xhci->quirks & XHCI_AMD_PLL_FIX)
4132 usb_amd_quirk_pll_disable();
4133 }
4134 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
4135
4136 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
4137 start_cycle, start_trb);
4138 return 0;
4139cleanup:
4140 /* Clean up a partially enqueued isoc transfer. */
4141
4142 for (i--; i >= 0; i--)
4143 list_del_init(&urb_priv->td[i].td_list);
4144
4145 /* Use the first TD as a temporary variable to turn the TDs we've queued
4146 * into No-ops with a software-owned cycle bit. That way the hardware
4147 * won't accidentally start executing bogus TDs when we partially
4148 * overwrite them. td->first_trb and td->start_seg are already set.
4149 */
4150 urb_priv->td[0].last_trb = ep_ring->enqueue;
4151 /* Every TRB except the first & last will have its cycle bit flipped. */
4152 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
4153
4154 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
4155 ep_ring->enqueue = urb_priv->td[0].first_trb;
4156 ep_ring->enq_seg = urb_priv->td[0].start_seg;
4157 ep_ring->cycle_state = start_cycle;
4158 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
4159 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
4160 return ret;
4161}
4162
4163/*
4164 * Check transfer ring to guarantee there is enough room for the urb.
4165 * Update ISO URB start_frame and interval.
4166 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
4167 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
4168 * Contiguous Frame ID is not supported by HC.
4169 */
4170int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
4171 struct urb *urb, int slot_id, unsigned int ep_index)
4172{
4173 struct xhci_virt_device *xdev;
4174 struct xhci_ring *ep_ring;
4175 struct xhci_ep_ctx *ep_ctx;
4176 int start_frame;
4177 int num_tds, num_trbs, i;
4178 int ret;
4179 struct xhci_virt_ep *xep;
4180 int ist;
4181
4182 xdev = xhci->devs[slot_id];
4183 xep = &xhci->devs[slot_id]->eps[ep_index];
4184 ep_ring = xdev->eps[ep_index].ring;
4185 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
4186
4187 num_trbs = 0;
4188 num_tds = urb->number_of_packets;
4189 for (i = 0; i < num_tds; i++)
4190 num_trbs += count_isoc_trbs_needed(urb, i);
4191
4192 /* Check the ring to guarantee there is enough room for the whole urb.
4193 * Do not insert any td of the urb to the ring if the check failed.
4194 */
4195 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
4196 num_trbs, mem_flags);
4197 if (ret)
4198 return ret;
4199
4200 /*
4201 * Check interval value. This should be done before we start to
4202 * calculate the start frame value.
4203 */
4204 check_interval(xhci, urb, ep_ctx);
4205
4206 /* Calculate the start frame and put it in urb->start_frame. */
4207 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
4208 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
4209 urb->start_frame = xep->next_frame_id;
4210 goto skip_start_over;
4211 }
4212 }
4213
4214 start_frame = readl(&xhci->run_regs->microframe_index);
4215 start_frame &= 0x3fff;
4216 /*
4217 * Round up to the next frame and consider the time before trb really
4218 * gets scheduled by hardare.
4219 */
4220 ist = HCS_IST(xhci->hcs_params2) & 0x7;
4221 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
4222 ist <<= 3;
4223 start_frame += ist + XHCI_CFC_DELAY;
4224 start_frame = roundup(start_frame, 8);
4225
4226 /*
4227 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4228 * is greate than 8 microframes.
4229 */
4230 if (urb->dev->speed == USB_SPEED_LOW ||
4231 urb->dev->speed == USB_SPEED_FULL) {
4232 start_frame = roundup(start_frame, urb->interval << 3);
4233 urb->start_frame = start_frame >> 3;
4234 } else {
4235 start_frame = roundup(start_frame, urb->interval);
4236 urb->start_frame = start_frame;
4237 }
4238
4239skip_start_over:
4240 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
4241
4242 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4243}
4244
4245/**** Command Ring Operations ****/
4246
4247/* Generic function for queueing a command TRB on the command ring.
4248 * Check to make sure there's room on the command ring for one command TRB.
4249 * Also check that there's room reserved for commands that must not fail.
4250 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4251 * then only check for the number of reserved spots.
4252 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4253 * because the command event handler may want to resubmit a failed command.
4254 */
4255static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4256 u32 field1, u32 field2,
4257 u32 field3, u32 field4, bool command_must_succeed)
4258{
4259 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4260 int ret;
4261
4262 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
4263 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4264 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
4265 return -ESHUTDOWN;
4266 }
4267
4268 if (!command_must_succeed)
4269 reserved_trbs++;
4270
4271 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4272 reserved_trbs, GFP_ATOMIC);
4273 if (ret < 0) {
4274 xhci_err(xhci, "ERR: No room for command on command ring\n");
4275 if (command_must_succeed)
4276 xhci_err(xhci, "ERR: Reserved TRB counting for "
4277 "unfailable commands failed.\n");
4278 return ret;
4279 }
4280
4281 cmd->command_trb = xhci->cmd_ring->enqueue;
4282
4283 /* if there are no other commands queued we start the timeout timer */
4284 if (list_empty(&xhci->cmd_list)) {
4285 xhci->current_cmd = cmd;
4286 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
4287 }
4288
4289 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4290
4291 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4292 field4 | xhci->cmd_ring->cycle_state);
4293 return 0;
4294}
4295
4296/* Queue a slot enable or disable request on the command ring */
4297int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4298 u32 trb_type, u32 slot_id)
4299{
4300 return queue_command(xhci, cmd, 0, 0, 0,
4301 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4302}
4303
4304/* Queue an address device command TRB */
4305int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4306 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4307{
4308 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4309 upper_32_bits(in_ctx_ptr), 0,
4310 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4311 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4312}
4313
4314int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4315 u32 field1, u32 field2, u32 field3, u32 field4)
4316{
4317 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4318}
4319
4320/* Queue a reset device command TRB */
4321int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4322 u32 slot_id)
4323{
4324 return queue_command(xhci, cmd, 0, 0, 0,
4325 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4326 false);
4327}
4328
4329/* Queue a configure endpoint command TRB */
4330int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4331 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4332 u32 slot_id, bool command_must_succeed)
4333{
4334 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4335 upper_32_bits(in_ctx_ptr), 0,
4336 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4337 command_must_succeed);
4338}
4339
4340/* Queue an evaluate context command TRB */
4341int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4342 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4343{
4344 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4345 upper_32_bits(in_ctx_ptr), 0,
4346 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4347 command_must_succeed);
4348}
4349
4350/*
4351 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4352 * activity on an endpoint that is about to be suspended.
4353 */
4354int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4355 int slot_id, unsigned int ep_index, int suspend)
4356{
4357 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4358 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4359 u32 type = TRB_TYPE(TRB_STOP_RING);
4360 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4361
4362 return queue_command(xhci, cmd, 0, 0, 0,
4363 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4364}
4365
4366int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4367 int slot_id, unsigned int ep_index,
4368 enum xhci_ep_reset_type reset_type)
4369{
4370 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4371 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4372 u32 type = TRB_TYPE(TRB_RESET_EP);
4373
4374 if (reset_type == EP_SOFT_RESET)
4375 type |= TRB_TSP;
4376
4377 return queue_command(xhci, cmd, 0, 0, 0,
4378 trb_slot_id | trb_ep_index | type, false);
4379}