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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Cryptographic API.
4 *
5 * Support for OMAP AES HW acceleration.
6 *
7 * Copyright (c) 2010 Nokia Corporation
8 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
9 * Copyright (c) 2011 Texas Instruments Incorporated
10 */
11
12#define pr_fmt(fmt) "%20s: " fmt, __func__
13#define prn(num) pr_debug(#num "=%d\n", num)
14#define prx(num) pr_debug(#num "=%x\n", num)
15
16#include <crypto/aes.h>
17#include <crypto/gcm.h>
18#include <crypto/internal/aead.h>
19#include <crypto/internal/engine.h>
20#include <crypto/internal/skcipher.h>
21#include <crypto/scatterwalk.h>
22#include <linux/dma-mapping.h>
23#include <linux/dmaengine.h>
24#include <linux/err.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/of.h>
31#include <linux/of_address.h>
32#include <linux/platform_device.h>
33#include <linux/pm_runtime.h>
34#include <linux/scatterlist.h>
35#include <linux/string.h>
36
37#include "omap-crypto.h"
38#include "omap-aes.h"
39
40/* keep registered devices data here */
41static LIST_HEAD(dev_list);
42static DEFINE_SPINLOCK(list_lock);
43
44static int aes_fallback_sz = 200;
45
46#ifdef DEBUG
47#define omap_aes_read(dd, offset) \
48({ \
49 int _read_ret; \
50 _read_ret = __raw_readl(dd->io_base + offset); \
51 pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \
52 offset, _read_ret); \
53 _read_ret; \
54})
55#else
56inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
57{
58 return __raw_readl(dd->io_base + offset);
59}
60#endif
61
62#ifdef DEBUG
63#define omap_aes_write(dd, offset, value) \
64 do { \
65 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \
66 offset, value); \
67 __raw_writel(value, dd->io_base + offset); \
68 } while (0)
69#else
70inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
71 u32 value)
72{
73 __raw_writel(value, dd->io_base + offset);
74}
75#endif
76
77static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
78 u32 value, u32 mask)
79{
80 u32 val;
81
82 val = omap_aes_read(dd, offset);
83 val &= ~mask;
84 val |= value;
85 omap_aes_write(dd, offset, val);
86}
87
88static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
89 u32 *value, int count)
90{
91 for (; count--; value++, offset += 4)
92 omap_aes_write(dd, offset, *value);
93}
94
95static int omap_aes_hw_init(struct omap_aes_dev *dd)
96{
97 int err;
98
99 if (!(dd->flags & FLAGS_INIT)) {
100 dd->flags |= FLAGS_INIT;
101 dd->err = 0;
102 }
103
104 err = pm_runtime_resume_and_get(dd->dev);
105 if (err < 0) {
106 dev_err(dd->dev, "failed to get sync: %d\n", err);
107 return err;
108 }
109
110 return 0;
111}
112
113void omap_aes_clear_copy_flags(struct omap_aes_dev *dd)
114{
115 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_IN_DATA_ST_SHIFT);
116 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_OUT_DATA_ST_SHIFT);
117 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_ASSOC_DATA_ST_SHIFT);
118}
119
120int omap_aes_write_ctrl(struct omap_aes_dev *dd)
121{
122 struct omap_aes_reqctx *rctx;
123 unsigned int key32;
124 int i, err;
125 u32 val;
126
127 err = omap_aes_hw_init(dd);
128 if (err)
129 return err;
130
131 key32 = dd->ctx->keylen / sizeof(u32);
132
133 /* RESET the key as previous HASH keys should not get affected*/
134 if (dd->flags & FLAGS_GCM)
135 for (i = 0; i < 0x40; i = i + 4)
136 omap_aes_write(dd, i, 0x0);
137
138 for (i = 0; i < key32; i++) {
139 omap_aes_write(dd, AES_REG_KEY(dd, i),
140 (__force u32)cpu_to_le32(dd->ctx->key[i]));
141 }
142
143 if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->iv)
144 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (void *)dd->req->iv, 4);
145
146 if ((dd->flags & (FLAGS_GCM)) && dd->aead_req->iv) {
147 rctx = aead_request_ctx(dd->aead_req);
148 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (u32 *)rctx->iv, 4);
149 }
150
151 val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
152 if (dd->flags & FLAGS_CBC)
153 val |= AES_REG_CTRL_CBC;
154
155 if (dd->flags & (FLAGS_CTR | FLAGS_GCM))
156 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128;
157
158 if (dd->flags & FLAGS_GCM)
159 val |= AES_REG_CTRL_GCM;
160
161 if (dd->flags & FLAGS_ENCRYPT)
162 val |= AES_REG_CTRL_DIRECTION;
163
164 omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK);
165
166 return 0;
167}
168
169static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length)
170{
171 u32 mask, val;
172
173 val = dd->pdata->dma_start;
174
175 if (dd->dma_lch_out != NULL)
176 val |= dd->pdata->dma_enable_out;
177 if (dd->dma_lch_in != NULL)
178 val |= dd->pdata->dma_enable_in;
179
180 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
181 dd->pdata->dma_start;
182
183 omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask);
184
185}
186
187static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length)
188{
189 omap_aes_write(dd, AES_REG_LENGTH_N(0), length);
190 omap_aes_write(dd, AES_REG_LENGTH_N(1), 0);
191 if (dd->flags & FLAGS_GCM)
192 omap_aes_write(dd, AES_REG_A_LEN, dd->assoc_len);
193
194 omap_aes_dma_trigger_omap2(dd, length);
195}
196
197static void omap_aes_dma_stop(struct omap_aes_dev *dd)
198{
199 u32 mask;
200
201 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
202 dd->pdata->dma_start;
203
204 omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask);
205}
206
207struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx)
208{
209 struct omap_aes_dev *dd;
210
211 spin_lock_bh(&list_lock);
212 dd = list_first_entry(&dev_list, struct omap_aes_dev, list);
213 list_move_tail(&dd->list, &dev_list);
214 rctx->dd = dd;
215 spin_unlock_bh(&list_lock);
216
217 return dd;
218}
219
220static void omap_aes_dma_out_callback(void *data)
221{
222 struct omap_aes_dev *dd = data;
223
224 /* dma_lch_out - completed */
225 tasklet_schedule(&dd->done_task);
226}
227
228static int omap_aes_dma_init(struct omap_aes_dev *dd)
229{
230 int err;
231
232 dd->dma_lch_out = NULL;
233 dd->dma_lch_in = NULL;
234
235 dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
236 if (IS_ERR(dd->dma_lch_in)) {
237 dev_err(dd->dev, "Unable to request in DMA channel\n");
238 return PTR_ERR(dd->dma_lch_in);
239 }
240
241 dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
242 if (IS_ERR(dd->dma_lch_out)) {
243 dev_err(dd->dev, "Unable to request out DMA channel\n");
244 err = PTR_ERR(dd->dma_lch_out);
245 goto err_dma_out;
246 }
247
248 return 0;
249
250err_dma_out:
251 dma_release_channel(dd->dma_lch_in);
252
253 return err;
254}
255
256static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
257{
258 if (dd->pio_only)
259 return;
260
261 dma_release_channel(dd->dma_lch_out);
262 dma_release_channel(dd->dma_lch_in);
263}
264
265static int omap_aes_crypt_dma(struct omap_aes_dev *dd,
266 struct scatterlist *in_sg,
267 struct scatterlist *out_sg,
268 int in_sg_len, int out_sg_len)
269{
270 struct dma_async_tx_descriptor *tx_in, *tx_out = NULL, *cb_desc;
271 struct dma_slave_config cfg;
272 int ret;
273
274 if (dd->pio_only) {
275 scatterwalk_start(&dd->in_walk, dd->in_sg);
276 if (out_sg_len)
277 scatterwalk_start(&dd->out_walk, dd->out_sg);
278
279 /* Enable DATAIN interrupt and let it take
280 care of the rest */
281 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
282 return 0;
283 }
284
285 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
286
287 memset(&cfg, 0, sizeof(cfg));
288
289 cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
290 cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
291 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
292 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
293 cfg.src_maxburst = DST_MAXBURST;
294 cfg.dst_maxburst = DST_MAXBURST;
295
296 /* IN */
297 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
298 if (ret) {
299 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
300 ret);
301 return ret;
302 }
303
304 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
305 DMA_MEM_TO_DEV,
306 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
307 if (!tx_in) {
308 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
309 return -EINVAL;
310 }
311
312 /* No callback necessary */
313 tx_in->callback_param = dd;
314 tx_in->callback = NULL;
315
316 /* OUT */
317 if (out_sg_len) {
318 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
319 if (ret) {
320 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
321 ret);
322 return ret;
323 }
324
325 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg,
326 out_sg_len,
327 DMA_DEV_TO_MEM,
328 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
329 if (!tx_out) {
330 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
331 return -EINVAL;
332 }
333
334 cb_desc = tx_out;
335 } else {
336 cb_desc = tx_in;
337 }
338
339 if (dd->flags & FLAGS_GCM)
340 cb_desc->callback = omap_aes_gcm_dma_out_callback;
341 else
342 cb_desc->callback = omap_aes_dma_out_callback;
343 cb_desc->callback_param = dd;
344
345
346 dmaengine_submit(tx_in);
347 if (tx_out)
348 dmaengine_submit(tx_out);
349
350 dma_async_issue_pending(dd->dma_lch_in);
351 if (out_sg_len)
352 dma_async_issue_pending(dd->dma_lch_out);
353
354 /* start DMA */
355 dd->pdata->trigger(dd, dd->total);
356
357 return 0;
358}
359
360int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
361{
362 int err;
363
364 pr_debug("total: %zu\n", dd->total);
365
366 if (!dd->pio_only) {
367 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
368 DMA_TO_DEVICE);
369 if (!err) {
370 dev_err(dd->dev, "dma_map_sg() error\n");
371 return -EINVAL;
372 }
373
374 if (dd->out_sg_len) {
375 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
376 DMA_FROM_DEVICE);
377 if (!err) {
378 dev_err(dd->dev, "dma_map_sg() error\n");
379 return -EINVAL;
380 }
381 }
382 }
383
384 err = omap_aes_crypt_dma(dd, dd->in_sg, dd->out_sg, dd->in_sg_len,
385 dd->out_sg_len);
386 if (err && !dd->pio_only) {
387 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
388 if (dd->out_sg_len)
389 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
390 DMA_FROM_DEVICE);
391 }
392
393 return err;
394}
395
396static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
397{
398 struct skcipher_request *req = dd->req;
399
400 pr_debug("err: %d\n", err);
401
402 crypto_finalize_skcipher_request(dd->engine, req, err);
403
404 pm_runtime_mark_last_busy(dd->dev);
405 pm_runtime_put_autosuspend(dd->dev);
406}
407
408int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
409{
410 pr_debug("total: %zu\n", dd->total);
411
412 omap_aes_dma_stop(dd);
413
414
415 return 0;
416}
417
418static int omap_aes_handle_queue(struct omap_aes_dev *dd,
419 struct skcipher_request *req)
420{
421 if (req)
422 return crypto_transfer_skcipher_request_to_engine(dd->engine, req);
423
424 return 0;
425}
426
427static int omap_aes_prepare_req(struct skcipher_request *req,
428 struct omap_aes_dev *dd)
429{
430 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(
431 crypto_skcipher_reqtfm(req));
432 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req);
433 int ret;
434 u16 flags;
435
436 /* assign new request to device */
437 dd->req = req;
438 dd->total = req->cryptlen;
439 dd->total_save = req->cryptlen;
440 dd->in_sg = req->src;
441 dd->out_sg = req->dst;
442 dd->orig_out = req->dst;
443
444 flags = OMAP_CRYPTO_COPY_DATA;
445 if (req->src == req->dst)
446 flags |= OMAP_CRYPTO_FORCE_COPY;
447
448 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, AES_BLOCK_SIZE,
449 dd->in_sgl, flags,
450 FLAGS_IN_DATA_ST_SHIFT, &dd->flags);
451 if (ret)
452 return ret;
453
454 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, AES_BLOCK_SIZE,
455 &dd->out_sgl, 0,
456 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags);
457 if (ret)
458 return ret;
459
460 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
461 if (dd->in_sg_len < 0)
462 return dd->in_sg_len;
463
464 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
465 if (dd->out_sg_len < 0)
466 return dd->out_sg_len;
467
468 rctx->mode &= FLAGS_MODE_MASK;
469 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
470
471 dd->ctx = ctx;
472 rctx->dd = dd;
473
474 return omap_aes_write_ctrl(dd);
475}
476
477static int omap_aes_crypt_req(struct crypto_engine *engine,
478 void *areq)
479{
480 struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
481 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req);
482 struct omap_aes_dev *dd = rctx->dd;
483
484 if (!dd)
485 return -ENODEV;
486
487 return omap_aes_prepare_req(req, dd) ?:
488 omap_aes_crypt_dma_start(dd);
489}
490
491static void omap_aes_copy_ivout(struct omap_aes_dev *dd, u8 *ivbuf)
492{
493 int i;
494
495 for (i = 0; i < 4; i++)
496 ((u32 *)ivbuf)[i] = omap_aes_read(dd, AES_REG_IV(dd, i));
497}
498
499static void omap_aes_done_task(unsigned long data)
500{
501 struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
502
503 pr_debug("enter done_task\n");
504
505 if (!dd->pio_only) {
506 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
507 DMA_FROM_DEVICE);
508 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
509 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
510 DMA_FROM_DEVICE);
511 omap_aes_crypt_dma_stop(dd);
512 }
513
514 omap_crypto_cleanup(dd->in_sg, NULL, 0, dd->total_save,
515 FLAGS_IN_DATA_ST_SHIFT, dd->flags);
516
517 omap_crypto_cleanup(dd->out_sg, dd->orig_out, 0, dd->total_save,
518 FLAGS_OUT_DATA_ST_SHIFT, dd->flags);
519
520 /* Update IV output */
521 if (dd->flags & (FLAGS_CBC | FLAGS_CTR))
522 omap_aes_copy_ivout(dd, dd->req->iv);
523
524 omap_aes_finish_req(dd, 0);
525
526 pr_debug("exit\n");
527}
528
529static int omap_aes_crypt(struct skcipher_request *req, unsigned long mode)
530{
531 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(
532 crypto_skcipher_reqtfm(req));
533 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req);
534 struct omap_aes_dev *dd;
535 int ret;
536
537 if ((req->cryptlen % AES_BLOCK_SIZE) && !(mode & FLAGS_CTR))
538 return -EINVAL;
539
540 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen,
541 !!(mode & FLAGS_ENCRYPT),
542 !!(mode & FLAGS_CBC));
543
544 if (req->cryptlen < aes_fallback_sz) {
545 skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback);
546 skcipher_request_set_callback(&rctx->fallback_req,
547 req->base.flags,
548 req->base.complete,
549 req->base.data);
550 skcipher_request_set_crypt(&rctx->fallback_req, req->src,
551 req->dst, req->cryptlen, req->iv);
552
553 if (mode & FLAGS_ENCRYPT)
554 ret = crypto_skcipher_encrypt(&rctx->fallback_req);
555 else
556 ret = crypto_skcipher_decrypt(&rctx->fallback_req);
557 return ret;
558 }
559 dd = omap_aes_find_dev(rctx);
560 if (!dd)
561 return -ENODEV;
562
563 rctx->mode = mode;
564
565 return omap_aes_handle_queue(dd, req);
566}
567
568/* ********************** ALG API ************************************ */
569
570static int omap_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,
571 unsigned int keylen)
572{
573 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
574 int ret;
575
576 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
577 keylen != AES_KEYSIZE_256)
578 return -EINVAL;
579
580 pr_debug("enter, keylen: %d\n", keylen);
581
582 memcpy(ctx->key, key, keylen);
583 ctx->keylen = keylen;
584
585 crypto_skcipher_clear_flags(ctx->fallback, CRYPTO_TFM_REQ_MASK);
586 crypto_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags &
587 CRYPTO_TFM_REQ_MASK);
588
589 ret = crypto_skcipher_setkey(ctx->fallback, key, keylen);
590 if (!ret)
591 return 0;
592
593 return 0;
594}
595
596static int omap_aes_ecb_encrypt(struct skcipher_request *req)
597{
598 return omap_aes_crypt(req, FLAGS_ENCRYPT);
599}
600
601static int omap_aes_ecb_decrypt(struct skcipher_request *req)
602{
603 return omap_aes_crypt(req, 0);
604}
605
606static int omap_aes_cbc_encrypt(struct skcipher_request *req)
607{
608 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
609}
610
611static int omap_aes_cbc_decrypt(struct skcipher_request *req)
612{
613 return omap_aes_crypt(req, FLAGS_CBC);
614}
615
616static int omap_aes_ctr_encrypt(struct skcipher_request *req)
617{
618 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR);
619}
620
621static int omap_aes_ctr_decrypt(struct skcipher_request *req)
622{
623 return omap_aes_crypt(req, FLAGS_CTR);
624}
625
626static int omap_aes_init_tfm(struct crypto_skcipher *tfm)
627{
628 const char *name = crypto_tfm_alg_name(&tfm->base);
629 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
630 struct crypto_skcipher *blk;
631
632 blk = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK);
633 if (IS_ERR(blk))
634 return PTR_ERR(blk);
635
636 ctx->fallback = blk;
637
638 crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_aes_reqctx) +
639 crypto_skcipher_reqsize(blk));
640
641 return 0;
642}
643
644static void omap_aes_exit_tfm(struct crypto_skcipher *tfm)
645{
646 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
647
648 if (ctx->fallback)
649 crypto_free_skcipher(ctx->fallback);
650
651 ctx->fallback = NULL;
652}
653
654/* ********************** ALGS ************************************ */
655
656static struct skcipher_engine_alg algs_ecb_cbc[] = {
657{
658 .base = {
659 .base.cra_name = "ecb(aes)",
660 .base.cra_driver_name = "ecb-aes-omap",
661 .base.cra_priority = 300,
662 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
663 CRYPTO_ALG_ASYNC |
664 CRYPTO_ALG_NEED_FALLBACK,
665 .base.cra_blocksize = AES_BLOCK_SIZE,
666 .base.cra_ctxsize = sizeof(struct omap_aes_ctx),
667 .base.cra_module = THIS_MODULE,
668
669 .min_keysize = AES_MIN_KEY_SIZE,
670 .max_keysize = AES_MAX_KEY_SIZE,
671 .setkey = omap_aes_setkey,
672 .encrypt = omap_aes_ecb_encrypt,
673 .decrypt = omap_aes_ecb_decrypt,
674 .init = omap_aes_init_tfm,
675 .exit = omap_aes_exit_tfm,
676 },
677 .op.do_one_request = omap_aes_crypt_req,
678},
679{
680 .base = {
681 .base.cra_name = "cbc(aes)",
682 .base.cra_driver_name = "cbc-aes-omap",
683 .base.cra_priority = 300,
684 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
685 CRYPTO_ALG_ASYNC |
686 CRYPTO_ALG_NEED_FALLBACK,
687 .base.cra_blocksize = AES_BLOCK_SIZE,
688 .base.cra_ctxsize = sizeof(struct omap_aes_ctx),
689 .base.cra_module = THIS_MODULE,
690
691 .min_keysize = AES_MIN_KEY_SIZE,
692 .max_keysize = AES_MAX_KEY_SIZE,
693 .ivsize = AES_BLOCK_SIZE,
694 .setkey = omap_aes_setkey,
695 .encrypt = omap_aes_cbc_encrypt,
696 .decrypt = omap_aes_cbc_decrypt,
697 .init = omap_aes_init_tfm,
698 .exit = omap_aes_exit_tfm,
699 },
700 .op.do_one_request = omap_aes_crypt_req,
701}
702};
703
704static struct skcipher_engine_alg algs_ctr[] = {
705{
706 .base = {
707 .base.cra_name = "ctr(aes)",
708 .base.cra_driver_name = "ctr-aes-omap",
709 .base.cra_priority = 300,
710 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
711 CRYPTO_ALG_ASYNC |
712 CRYPTO_ALG_NEED_FALLBACK,
713 .base.cra_blocksize = 1,
714 .base.cra_ctxsize = sizeof(struct omap_aes_ctx),
715 .base.cra_module = THIS_MODULE,
716
717 .min_keysize = AES_MIN_KEY_SIZE,
718 .max_keysize = AES_MAX_KEY_SIZE,
719 .ivsize = AES_BLOCK_SIZE,
720 .setkey = omap_aes_setkey,
721 .encrypt = omap_aes_ctr_encrypt,
722 .decrypt = omap_aes_ctr_decrypt,
723 .init = omap_aes_init_tfm,
724 .exit = omap_aes_exit_tfm,
725 },
726 .op.do_one_request = omap_aes_crypt_req,
727}
728};
729
730static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = {
731 {
732 .algs_list = algs_ecb_cbc,
733 .size = ARRAY_SIZE(algs_ecb_cbc),
734 },
735};
736
737static struct aead_engine_alg algs_aead_gcm[] = {
738{
739 .base = {
740 .base = {
741 .cra_name = "gcm(aes)",
742 .cra_driver_name = "gcm-aes-omap",
743 .cra_priority = 300,
744 .cra_flags = CRYPTO_ALG_ASYNC |
745 CRYPTO_ALG_KERN_DRIVER_ONLY,
746 .cra_blocksize = 1,
747 .cra_ctxsize = sizeof(struct omap_aes_gcm_ctx),
748 .cra_alignmask = 0xf,
749 .cra_module = THIS_MODULE,
750 },
751 .init = omap_aes_gcm_cra_init,
752 .ivsize = GCM_AES_IV_SIZE,
753 .maxauthsize = AES_BLOCK_SIZE,
754 .setkey = omap_aes_gcm_setkey,
755 .setauthsize = omap_aes_gcm_setauthsize,
756 .encrypt = omap_aes_gcm_encrypt,
757 .decrypt = omap_aes_gcm_decrypt,
758 },
759 .op.do_one_request = omap_aes_gcm_crypt_req,
760},
761{
762 .base = {
763 .base = {
764 .cra_name = "rfc4106(gcm(aes))",
765 .cra_driver_name = "rfc4106-gcm-aes-omap",
766 .cra_priority = 300,
767 .cra_flags = CRYPTO_ALG_ASYNC |
768 CRYPTO_ALG_KERN_DRIVER_ONLY,
769 .cra_blocksize = 1,
770 .cra_ctxsize = sizeof(struct omap_aes_gcm_ctx),
771 .cra_alignmask = 0xf,
772 .cra_module = THIS_MODULE,
773 },
774 .init = omap_aes_gcm_cra_init,
775 .maxauthsize = AES_BLOCK_SIZE,
776 .ivsize = GCM_RFC4106_IV_SIZE,
777 .setkey = omap_aes_4106gcm_setkey,
778 .setauthsize = omap_aes_4106gcm_setauthsize,
779 .encrypt = omap_aes_4106gcm_encrypt,
780 .decrypt = omap_aes_4106gcm_decrypt,
781 },
782 .op.do_one_request = omap_aes_gcm_crypt_req,
783},
784};
785
786static struct omap_aes_aead_algs omap_aes_aead_info = {
787 .algs_list = algs_aead_gcm,
788 .size = ARRAY_SIZE(algs_aead_gcm),
789};
790
791static const struct omap_aes_pdata omap_aes_pdata_omap2 = {
792 .algs_info = omap_aes_algs_info_ecb_cbc,
793 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc),
794 .trigger = omap_aes_dma_trigger_omap2,
795 .key_ofs = 0x1c,
796 .iv_ofs = 0x20,
797 .ctrl_ofs = 0x30,
798 .data_ofs = 0x34,
799 .rev_ofs = 0x44,
800 .mask_ofs = 0x48,
801 .dma_enable_in = BIT(2),
802 .dma_enable_out = BIT(3),
803 .dma_start = BIT(5),
804 .major_mask = 0xf0,
805 .major_shift = 4,
806 .minor_mask = 0x0f,
807 .minor_shift = 0,
808};
809
810#ifdef CONFIG_OF
811static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = {
812 {
813 .algs_list = algs_ecb_cbc,
814 .size = ARRAY_SIZE(algs_ecb_cbc),
815 },
816 {
817 .algs_list = algs_ctr,
818 .size = ARRAY_SIZE(algs_ctr),
819 },
820};
821
822static const struct omap_aes_pdata omap_aes_pdata_omap3 = {
823 .algs_info = omap_aes_algs_info_ecb_cbc_ctr,
824 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
825 .trigger = omap_aes_dma_trigger_omap2,
826 .key_ofs = 0x1c,
827 .iv_ofs = 0x20,
828 .ctrl_ofs = 0x30,
829 .data_ofs = 0x34,
830 .rev_ofs = 0x44,
831 .mask_ofs = 0x48,
832 .dma_enable_in = BIT(2),
833 .dma_enable_out = BIT(3),
834 .dma_start = BIT(5),
835 .major_mask = 0xf0,
836 .major_shift = 4,
837 .minor_mask = 0x0f,
838 .minor_shift = 0,
839};
840
841static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
842 .algs_info = omap_aes_algs_info_ecb_cbc_ctr,
843 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
844 .aead_algs_info = &omap_aes_aead_info,
845 .trigger = omap_aes_dma_trigger_omap4,
846 .key_ofs = 0x3c,
847 .iv_ofs = 0x40,
848 .ctrl_ofs = 0x50,
849 .data_ofs = 0x60,
850 .rev_ofs = 0x80,
851 .mask_ofs = 0x84,
852 .irq_status_ofs = 0x8c,
853 .irq_enable_ofs = 0x90,
854 .dma_enable_in = BIT(5),
855 .dma_enable_out = BIT(6),
856 .major_mask = 0x0700,
857 .major_shift = 8,
858 .minor_mask = 0x003f,
859 .minor_shift = 0,
860};
861
862static irqreturn_t omap_aes_irq(int irq, void *dev_id)
863{
864 struct omap_aes_dev *dd = dev_id;
865 u32 status, i;
866 u32 *src, *dst;
867
868 status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd));
869 if (status & AES_REG_IRQ_DATA_IN) {
870 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
871
872 BUG_ON(!dd->in_sg);
873
874 BUG_ON(_calc_walked(in) > dd->in_sg->length);
875
876 src = sg_virt(dd->in_sg) + _calc_walked(in);
877
878 for (i = 0; i < AES_BLOCK_WORDS; i++) {
879 omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src);
880
881 scatterwalk_advance(&dd->in_walk, 4);
882 if (dd->in_sg->length == _calc_walked(in)) {
883 dd->in_sg = sg_next(dd->in_sg);
884 if (dd->in_sg) {
885 scatterwalk_start(&dd->in_walk,
886 dd->in_sg);
887 src = sg_virt(dd->in_sg) +
888 _calc_walked(in);
889 }
890 } else {
891 src++;
892 }
893 }
894
895 /* Clear IRQ status */
896 status &= ~AES_REG_IRQ_DATA_IN;
897 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
898
899 /* Enable DATA_OUT interrupt */
900 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4);
901
902 } else if (status & AES_REG_IRQ_DATA_OUT) {
903 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
904
905 BUG_ON(!dd->out_sg);
906
907 BUG_ON(_calc_walked(out) > dd->out_sg->length);
908
909 dst = sg_virt(dd->out_sg) + _calc_walked(out);
910
911 for (i = 0; i < AES_BLOCK_WORDS; i++) {
912 *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i));
913 scatterwalk_advance(&dd->out_walk, 4);
914 if (dd->out_sg->length == _calc_walked(out)) {
915 dd->out_sg = sg_next(dd->out_sg);
916 if (dd->out_sg) {
917 scatterwalk_start(&dd->out_walk,
918 dd->out_sg);
919 dst = sg_virt(dd->out_sg) +
920 _calc_walked(out);
921 }
922 } else {
923 dst++;
924 }
925 }
926
927 dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total);
928
929 /* Clear IRQ status */
930 status &= ~AES_REG_IRQ_DATA_OUT;
931 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
932
933 if (!dd->total)
934 /* All bytes read! */
935 tasklet_schedule(&dd->done_task);
936 else
937 /* Enable DATA_IN interrupt for next block */
938 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
939 }
940
941 return IRQ_HANDLED;
942}
943
944static const struct of_device_id omap_aes_of_match[] = {
945 {
946 .compatible = "ti,omap2-aes",
947 .data = &omap_aes_pdata_omap2,
948 },
949 {
950 .compatible = "ti,omap3-aes",
951 .data = &omap_aes_pdata_omap3,
952 },
953 {
954 .compatible = "ti,omap4-aes",
955 .data = &omap_aes_pdata_omap4,
956 },
957 {},
958};
959MODULE_DEVICE_TABLE(of, omap_aes_of_match);
960
961static int omap_aes_get_res_of(struct omap_aes_dev *dd,
962 struct device *dev, struct resource *res)
963{
964 struct device_node *node = dev->of_node;
965 int err = 0;
966
967 dd->pdata = of_device_get_match_data(dev);
968 if (!dd->pdata) {
969 dev_err(dev, "no compatible OF match\n");
970 err = -EINVAL;
971 goto err;
972 }
973
974 err = of_address_to_resource(node, 0, res);
975 if (err < 0) {
976 dev_err(dev, "can't translate OF node address\n");
977 err = -EINVAL;
978 goto err;
979 }
980
981err:
982 return err;
983}
984#else
985static const struct of_device_id omap_aes_of_match[] = {
986 {},
987};
988
989static int omap_aes_get_res_of(struct omap_aes_dev *dd,
990 struct device *dev, struct resource *res)
991{
992 return -EINVAL;
993}
994#endif
995
996static int omap_aes_get_res_pdev(struct omap_aes_dev *dd,
997 struct platform_device *pdev, struct resource *res)
998{
999 struct device *dev = &pdev->dev;
1000 struct resource *r;
1001 int err = 0;
1002
1003 /* Get the base address */
1004 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1005 if (!r) {
1006 dev_err(dev, "no MEM resource info\n");
1007 err = -ENODEV;
1008 goto err;
1009 }
1010 memcpy(res, r, sizeof(*res));
1011
1012 /* Only OMAP2/3 can be non-DT */
1013 dd->pdata = &omap_aes_pdata_omap2;
1014
1015err:
1016 return err;
1017}
1018
1019static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
1020 char *buf)
1021{
1022 return sprintf(buf, "%d\n", aes_fallback_sz);
1023}
1024
1025static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
1026 const char *buf, size_t size)
1027{
1028 ssize_t status;
1029 long value;
1030
1031 status = kstrtol(buf, 0, &value);
1032 if (status)
1033 return status;
1034
1035 /* HW accelerator only works with buffers > 9 */
1036 if (value < 9) {
1037 dev_err(dev, "minimum fallback size 9\n");
1038 return -EINVAL;
1039 }
1040
1041 aes_fallback_sz = value;
1042
1043 return size;
1044}
1045
1046static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr,
1047 char *buf)
1048{
1049 struct omap_aes_dev *dd = dev_get_drvdata(dev);
1050
1051 return sprintf(buf, "%d\n", dd->engine->queue.max_qlen);
1052}
1053
1054static ssize_t queue_len_store(struct device *dev,
1055 struct device_attribute *attr, const char *buf,
1056 size_t size)
1057{
1058 struct omap_aes_dev *dd;
1059 ssize_t status;
1060 long value;
1061 unsigned long flags;
1062
1063 status = kstrtol(buf, 0, &value);
1064 if (status)
1065 return status;
1066
1067 if (value < 1)
1068 return -EINVAL;
1069
1070 /*
1071 * Changing the queue size in fly is safe, if size becomes smaller
1072 * than current size, it will just not accept new entries until
1073 * it has shrank enough.
1074 */
1075 spin_lock_bh(&list_lock);
1076 list_for_each_entry(dd, &dev_list, list) {
1077 spin_lock_irqsave(&dd->lock, flags);
1078 dd->engine->queue.max_qlen = value;
1079 dd->aead_queue.base.max_qlen = value;
1080 spin_unlock_irqrestore(&dd->lock, flags);
1081 }
1082 spin_unlock_bh(&list_lock);
1083
1084 return size;
1085}
1086
1087static DEVICE_ATTR_RW(queue_len);
1088static DEVICE_ATTR_RW(fallback);
1089
1090static struct attribute *omap_aes_attrs[] = {
1091 &dev_attr_queue_len.attr,
1092 &dev_attr_fallback.attr,
1093 NULL,
1094};
1095
1096static const struct attribute_group omap_aes_attr_group = {
1097 .attrs = omap_aes_attrs,
1098};
1099
1100static int omap_aes_probe(struct platform_device *pdev)
1101{
1102 struct device *dev = &pdev->dev;
1103 struct omap_aes_dev *dd;
1104 struct skcipher_engine_alg *algp;
1105 struct aead_engine_alg *aalg;
1106 struct resource res;
1107 int err = -ENOMEM, i, j, irq = -1;
1108 u32 reg;
1109
1110 dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL);
1111 if (dd == NULL) {
1112 dev_err(dev, "unable to alloc data struct.\n");
1113 goto err_data;
1114 }
1115 dd->dev = dev;
1116 platform_set_drvdata(pdev, dd);
1117
1118 aead_init_queue(&dd->aead_queue, OMAP_AES_QUEUE_LENGTH);
1119
1120 err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) :
1121 omap_aes_get_res_pdev(dd, pdev, &res);
1122 if (err)
1123 goto err_res;
1124
1125 dd->io_base = devm_ioremap_resource(dev, &res);
1126 if (IS_ERR(dd->io_base)) {
1127 err = PTR_ERR(dd->io_base);
1128 goto err_res;
1129 }
1130 dd->phys_base = res.start;
1131
1132 pm_runtime_use_autosuspend(dev);
1133 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
1134
1135 pm_runtime_enable(dev);
1136 err = pm_runtime_resume_and_get(dev);
1137 if (err < 0) {
1138 dev_err(dev, "%s: failed to get_sync(%d)\n",
1139 __func__, err);
1140 goto err_pm_disable;
1141 }
1142
1143 omap_aes_dma_stop(dd);
1144
1145 reg = omap_aes_read(dd, AES_REG_REV(dd));
1146
1147 pm_runtime_put_sync(dev);
1148
1149 dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
1150 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1151 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1152
1153 tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
1154
1155 err = omap_aes_dma_init(dd);
1156 if (err == -EPROBE_DEFER) {
1157 goto err_irq;
1158 } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) {
1159 dd->pio_only = 1;
1160
1161 irq = platform_get_irq(pdev, 0);
1162 if (irq < 0) {
1163 err = irq;
1164 goto err_irq;
1165 }
1166
1167 err = devm_request_irq(dev, irq, omap_aes_irq, 0,
1168 dev_name(dev), dd);
1169 if (err) {
1170 dev_err(dev, "Unable to grab omap-aes IRQ\n");
1171 goto err_irq;
1172 }
1173 }
1174
1175 spin_lock_init(&dd->lock);
1176
1177 INIT_LIST_HEAD(&dd->list);
1178 spin_lock_bh(&list_lock);
1179 list_add_tail(&dd->list, &dev_list);
1180 spin_unlock_bh(&list_lock);
1181
1182 /* Initialize crypto engine */
1183 dd->engine = crypto_engine_alloc_init(dev, 1);
1184 if (!dd->engine) {
1185 err = -ENOMEM;
1186 goto err_engine;
1187 }
1188
1189 err = crypto_engine_start(dd->engine);
1190 if (err)
1191 goto err_engine;
1192
1193 for (i = 0; i < dd->pdata->algs_info_size; i++) {
1194 if (!dd->pdata->algs_info[i].registered) {
1195 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1196 algp = &dd->pdata->algs_info[i].algs_list[j];
1197
1198 pr_debug("reg alg: %s\n", algp->base.base.cra_name);
1199
1200 err = crypto_engine_register_skcipher(algp);
1201 if (err)
1202 goto err_algs;
1203
1204 dd->pdata->algs_info[i].registered++;
1205 }
1206 }
1207 }
1208
1209 if (dd->pdata->aead_algs_info &&
1210 !dd->pdata->aead_algs_info->registered) {
1211 for (i = 0; i < dd->pdata->aead_algs_info->size; i++) {
1212 aalg = &dd->pdata->aead_algs_info->algs_list[i];
1213
1214 pr_debug("reg alg: %s\n", aalg->base.base.cra_name);
1215
1216 err = crypto_engine_register_aead(aalg);
1217 if (err)
1218 goto err_aead_algs;
1219
1220 dd->pdata->aead_algs_info->registered++;
1221 }
1222 }
1223
1224 err = sysfs_create_group(&dev->kobj, &omap_aes_attr_group);
1225 if (err) {
1226 dev_err(dev, "could not create sysfs device attrs\n");
1227 goto err_aead_algs;
1228 }
1229
1230 return 0;
1231err_aead_algs:
1232 for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) {
1233 aalg = &dd->pdata->aead_algs_info->algs_list[i];
1234 crypto_engine_unregister_aead(aalg);
1235 }
1236err_algs:
1237 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1238 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1239 crypto_engine_unregister_skcipher(
1240 &dd->pdata->algs_info[i].algs_list[j]);
1241
1242err_engine:
1243 if (dd->engine)
1244 crypto_engine_exit(dd->engine);
1245
1246 omap_aes_dma_cleanup(dd);
1247err_irq:
1248 tasklet_kill(&dd->done_task);
1249err_pm_disable:
1250 pm_runtime_disable(dev);
1251err_res:
1252 dd = NULL;
1253err_data:
1254 dev_err(dev, "initialization failed.\n");
1255 return err;
1256}
1257
1258static void omap_aes_remove(struct platform_device *pdev)
1259{
1260 struct omap_aes_dev *dd = platform_get_drvdata(pdev);
1261 struct aead_engine_alg *aalg;
1262 int i, j;
1263
1264 spin_lock_bh(&list_lock);
1265 list_del(&dd->list);
1266 spin_unlock_bh(&list_lock);
1267
1268 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1269 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) {
1270 crypto_engine_unregister_skcipher(
1271 &dd->pdata->algs_info[i].algs_list[j]);
1272 dd->pdata->algs_info[i].registered--;
1273 }
1274
1275 for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) {
1276 aalg = &dd->pdata->aead_algs_info->algs_list[i];
1277 crypto_engine_unregister_aead(aalg);
1278 dd->pdata->aead_algs_info->registered--;
1279 }
1280
1281 crypto_engine_exit(dd->engine);
1282
1283 tasklet_kill(&dd->done_task);
1284 omap_aes_dma_cleanup(dd);
1285 pm_runtime_disable(dd->dev);
1286
1287 sysfs_remove_group(&dd->dev->kobj, &omap_aes_attr_group);
1288}
1289
1290#ifdef CONFIG_PM_SLEEP
1291static int omap_aes_suspend(struct device *dev)
1292{
1293 pm_runtime_put_sync(dev);
1294 return 0;
1295}
1296
1297static int omap_aes_resume(struct device *dev)
1298{
1299 pm_runtime_get_sync(dev);
1300 return 0;
1301}
1302#endif
1303
1304static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume);
1305
1306static struct platform_driver omap_aes_driver = {
1307 .probe = omap_aes_probe,
1308 .remove_new = omap_aes_remove,
1309 .driver = {
1310 .name = "omap-aes",
1311 .pm = &omap_aes_pm_ops,
1312 .of_match_table = omap_aes_of_match,
1313 },
1314};
1315
1316module_platform_driver(omap_aes_driver);
1317
1318MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
1319MODULE_LICENSE("GPL v2");
1320MODULE_AUTHOR("Dmitry Kasatkin");
1321
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Cryptographic API.
4 *
5 * Support for OMAP AES HW acceleration.
6 *
7 * Copyright (c) 2010 Nokia Corporation
8 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
9 * Copyright (c) 2011 Texas Instruments Incorporated
10 */
11
12#define pr_fmt(fmt) "%20s: " fmt, __func__
13#define prn(num) pr_debug(#num "=%d\n", num)
14#define prx(num) pr_debug(#num "=%x\n", num)
15
16#include <linux/err.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/errno.h>
20#include <linux/kernel.h>
21#include <linux/platform_device.h>
22#include <linux/scatterlist.h>
23#include <linux/dma-mapping.h>
24#include <linux/dmaengine.h>
25#include <linux/pm_runtime.h>
26#include <linux/of.h>
27#include <linux/of_device.h>
28#include <linux/of_address.h>
29#include <linux/io.h>
30#include <linux/crypto.h>
31#include <linux/interrupt.h>
32#include <crypto/scatterwalk.h>
33#include <crypto/aes.h>
34#include <crypto/gcm.h>
35#include <crypto/engine.h>
36#include <crypto/internal/skcipher.h>
37#include <crypto/internal/aead.h>
38
39#include "omap-crypto.h"
40#include "omap-aes.h"
41
42/* keep registered devices data here */
43static LIST_HEAD(dev_list);
44static DEFINE_SPINLOCK(list_lock);
45
46static int aes_fallback_sz = 200;
47
48#ifdef DEBUG
49#define omap_aes_read(dd, offset) \
50({ \
51 int _read_ret; \
52 _read_ret = __raw_readl(dd->io_base + offset); \
53 pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \
54 offset, _read_ret); \
55 _read_ret; \
56})
57#else
58inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
59{
60 return __raw_readl(dd->io_base + offset);
61}
62#endif
63
64#ifdef DEBUG
65#define omap_aes_write(dd, offset, value) \
66 do { \
67 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \
68 offset, value); \
69 __raw_writel(value, dd->io_base + offset); \
70 } while (0)
71#else
72inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
73 u32 value)
74{
75 __raw_writel(value, dd->io_base + offset);
76}
77#endif
78
79static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
80 u32 value, u32 mask)
81{
82 u32 val;
83
84 val = omap_aes_read(dd, offset);
85 val &= ~mask;
86 val |= value;
87 omap_aes_write(dd, offset, val);
88}
89
90static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
91 u32 *value, int count)
92{
93 for (; count--; value++, offset += 4)
94 omap_aes_write(dd, offset, *value);
95}
96
97static int omap_aes_hw_init(struct omap_aes_dev *dd)
98{
99 int err;
100
101 if (!(dd->flags & FLAGS_INIT)) {
102 dd->flags |= FLAGS_INIT;
103 dd->err = 0;
104 }
105
106 err = pm_runtime_resume_and_get(dd->dev);
107 if (err < 0) {
108 dev_err(dd->dev, "failed to get sync: %d\n", err);
109 return err;
110 }
111
112 return 0;
113}
114
115void omap_aes_clear_copy_flags(struct omap_aes_dev *dd)
116{
117 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_IN_DATA_ST_SHIFT);
118 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_OUT_DATA_ST_SHIFT);
119 dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_ASSOC_DATA_ST_SHIFT);
120}
121
122int omap_aes_write_ctrl(struct omap_aes_dev *dd)
123{
124 struct omap_aes_reqctx *rctx;
125 unsigned int key32;
126 int i, err;
127 u32 val;
128
129 err = omap_aes_hw_init(dd);
130 if (err)
131 return err;
132
133 key32 = dd->ctx->keylen / sizeof(u32);
134
135 /* RESET the key as previous HASH keys should not get affected*/
136 if (dd->flags & FLAGS_GCM)
137 for (i = 0; i < 0x40; i = i + 4)
138 omap_aes_write(dd, i, 0x0);
139
140 for (i = 0; i < key32; i++) {
141 omap_aes_write(dd, AES_REG_KEY(dd, i),
142 (__force u32)cpu_to_le32(dd->ctx->key[i]));
143 }
144
145 if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->iv)
146 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (void *)dd->req->iv, 4);
147
148 if ((dd->flags & (FLAGS_GCM)) && dd->aead_req->iv) {
149 rctx = aead_request_ctx(dd->aead_req);
150 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (u32 *)rctx->iv, 4);
151 }
152
153 val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
154 if (dd->flags & FLAGS_CBC)
155 val |= AES_REG_CTRL_CBC;
156
157 if (dd->flags & (FLAGS_CTR | FLAGS_GCM))
158 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128;
159
160 if (dd->flags & FLAGS_GCM)
161 val |= AES_REG_CTRL_GCM;
162
163 if (dd->flags & FLAGS_ENCRYPT)
164 val |= AES_REG_CTRL_DIRECTION;
165
166 omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK);
167
168 return 0;
169}
170
171static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length)
172{
173 u32 mask, val;
174
175 val = dd->pdata->dma_start;
176
177 if (dd->dma_lch_out != NULL)
178 val |= dd->pdata->dma_enable_out;
179 if (dd->dma_lch_in != NULL)
180 val |= dd->pdata->dma_enable_in;
181
182 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
183 dd->pdata->dma_start;
184
185 omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask);
186
187}
188
189static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length)
190{
191 omap_aes_write(dd, AES_REG_LENGTH_N(0), length);
192 omap_aes_write(dd, AES_REG_LENGTH_N(1), 0);
193 if (dd->flags & FLAGS_GCM)
194 omap_aes_write(dd, AES_REG_A_LEN, dd->assoc_len);
195
196 omap_aes_dma_trigger_omap2(dd, length);
197}
198
199static void omap_aes_dma_stop(struct omap_aes_dev *dd)
200{
201 u32 mask;
202
203 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
204 dd->pdata->dma_start;
205
206 omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask);
207}
208
209struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx)
210{
211 struct omap_aes_dev *dd;
212
213 spin_lock_bh(&list_lock);
214 dd = list_first_entry(&dev_list, struct omap_aes_dev, list);
215 list_move_tail(&dd->list, &dev_list);
216 rctx->dd = dd;
217 spin_unlock_bh(&list_lock);
218
219 return dd;
220}
221
222static void omap_aes_dma_out_callback(void *data)
223{
224 struct omap_aes_dev *dd = data;
225
226 /* dma_lch_out - completed */
227 tasklet_schedule(&dd->done_task);
228}
229
230static int omap_aes_dma_init(struct omap_aes_dev *dd)
231{
232 int err;
233
234 dd->dma_lch_out = NULL;
235 dd->dma_lch_in = NULL;
236
237 dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
238 if (IS_ERR(dd->dma_lch_in)) {
239 dev_err(dd->dev, "Unable to request in DMA channel\n");
240 return PTR_ERR(dd->dma_lch_in);
241 }
242
243 dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
244 if (IS_ERR(dd->dma_lch_out)) {
245 dev_err(dd->dev, "Unable to request out DMA channel\n");
246 err = PTR_ERR(dd->dma_lch_out);
247 goto err_dma_out;
248 }
249
250 return 0;
251
252err_dma_out:
253 dma_release_channel(dd->dma_lch_in);
254
255 return err;
256}
257
258static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
259{
260 if (dd->pio_only)
261 return;
262
263 dma_release_channel(dd->dma_lch_out);
264 dma_release_channel(dd->dma_lch_in);
265}
266
267static int omap_aes_crypt_dma(struct omap_aes_dev *dd,
268 struct scatterlist *in_sg,
269 struct scatterlist *out_sg,
270 int in_sg_len, int out_sg_len)
271{
272 struct dma_async_tx_descriptor *tx_in, *tx_out = NULL, *cb_desc;
273 struct dma_slave_config cfg;
274 int ret;
275
276 if (dd->pio_only) {
277 scatterwalk_start(&dd->in_walk, dd->in_sg);
278 if (out_sg_len)
279 scatterwalk_start(&dd->out_walk, dd->out_sg);
280
281 /* Enable DATAIN interrupt and let it take
282 care of the rest */
283 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
284 return 0;
285 }
286
287 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
288
289 memset(&cfg, 0, sizeof(cfg));
290
291 cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
292 cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
293 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
294 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
295 cfg.src_maxburst = DST_MAXBURST;
296 cfg.dst_maxburst = DST_MAXBURST;
297
298 /* IN */
299 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
300 if (ret) {
301 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
302 ret);
303 return ret;
304 }
305
306 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
307 DMA_MEM_TO_DEV,
308 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
309 if (!tx_in) {
310 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
311 return -EINVAL;
312 }
313
314 /* No callback necessary */
315 tx_in->callback_param = dd;
316 tx_in->callback = NULL;
317
318 /* OUT */
319 if (out_sg_len) {
320 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
321 if (ret) {
322 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
323 ret);
324 return ret;
325 }
326
327 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg,
328 out_sg_len,
329 DMA_DEV_TO_MEM,
330 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
331 if (!tx_out) {
332 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
333 return -EINVAL;
334 }
335
336 cb_desc = tx_out;
337 } else {
338 cb_desc = tx_in;
339 }
340
341 if (dd->flags & FLAGS_GCM)
342 cb_desc->callback = omap_aes_gcm_dma_out_callback;
343 else
344 cb_desc->callback = omap_aes_dma_out_callback;
345 cb_desc->callback_param = dd;
346
347
348 dmaengine_submit(tx_in);
349 if (tx_out)
350 dmaengine_submit(tx_out);
351
352 dma_async_issue_pending(dd->dma_lch_in);
353 if (out_sg_len)
354 dma_async_issue_pending(dd->dma_lch_out);
355
356 /* start DMA */
357 dd->pdata->trigger(dd, dd->total);
358
359 return 0;
360}
361
362int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
363{
364 int err;
365
366 pr_debug("total: %zu\n", dd->total);
367
368 if (!dd->pio_only) {
369 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
370 DMA_TO_DEVICE);
371 if (!err) {
372 dev_err(dd->dev, "dma_map_sg() error\n");
373 return -EINVAL;
374 }
375
376 if (dd->out_sg_len) {
377 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
378 DMA_FROM_DEVICE);
379 if (!err) {
380 dev_err(dd->dev, "dma_map_sg() error\n");
381 return -EINVAL;
382 }
383 }
384 }
385
386 err = omap_aes_crypt_dma(dd, dd->in_sg, dd->out_sg, dd->in_sg_len,
387 dd->out_sg_len);
388 if (err && !dd->pio_only) {
389 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
390 if (dd->out_sg_len)
391 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
392 DMA_FROM_DEVICE);
393 }
394
395 return err;
396}
397
398static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
399{
400 struct skcipher_request *req = dd->req;
401
402 pr_debug("err: %d\n", err);
403
404 crypto_finalize_skcipher_request(dd->engine, req, err);
405
406 pm_runtime_mark_last_busy(dd->dev);
407 pm_runtime_put_autosuspend(dd->dev);
408}
409
410int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
411{
412 pr_debug("total: %zu\n", dd->total);
413
414 omap_aes_dma_stop(dd);
415
416
417 return 0;
418}
419
420static int omap_aes_handle_queue(struct omap_aes_dev *dd,
421 struct skcipher_request *req)
422{
423 if (req)
424 return crypto_transfer_skcipher_request_to_engine(dd->engine, req);
425
426 return 0;
427}
428
429static int omap_aes_prepare_req(struct crypto_engine *engine,
430 void *areq)
431{
432 struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
433 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(
434 crypto_skcipher_reqtfm(req));
435 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req);
436 struct omap_aes_dev *dd = rctx->dd;
437 int ret;
438 u16 flags;
439
440 if (!dd)
441 return -ENODEV;
442
443 /* assign new request to device */
444 dd->req = req;
445 dd->total = req->cryptlen;
446 dd->total_save = req->cryptlen;
447 dd->in_sg = req->src;
448 dd->out_sg = req->dst;
449 dd->orig_out = req->dst;
450
451 flags = OMAP_CRYPTO_COPY_DATA;
452 if (req->src == req->dst)
453 flags |= OMAP_CRYPTO_FORCE_COPY;
454
455 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, AES_BLOCK_SIZE,
456 dd->in_sgl, flags,
457 FLAGS_IN_DATA_ST_SHIFT, &dd->flags);
458 if (ret)
459 return ret;
460
461 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, AES_BLOCK_SIZE,
462 &dd->out_sgl, 0,
463 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags);
464 if (ret)
465 return ret;
466
467 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
468 if (dd->in_sg_len < 0)
469 return dd->in_sg_len;
470
471 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
472 if (dd->out_sg_len < 0)
473 return dd->out_sg_len;
474
475 rctx->mode &= FLAGS_MODE_MASK;
476 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
477
478 dd->ctx = ctx;
479 rctx->dd = dd;
480
481 return omap_aes_write_ctrl(dd);
482}
483
484static int omap_aes_crypt_req(struct crypto_engine *engine,
485 void *areq)
486{
487 struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
488 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req);
489 struct omap_aes_dev *dd = rctx->dd;
490
491 if (!dd)
492 return -ENODEV;
493
494 return omap_aes_crypt_dma_start(dd);
495}
496
497static void omap_aes_copy_ivout(struct omap_aes_dev *dd, u8 *ivbuf)
498{
499 int i;
500
501 for (i = 0; i < 4; i++)
502 ((u32 *)ivbuf)[i] = omap_aes_read(dd, AES_REG_IV(dd, i));
503}
504
505static void omap_aes_done_task(unsigned long data)
506{
507 struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
508
509 pr_debug("enter done_task\n");
510
511 if (!dd->pio_only) {
512 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
513 DMA_FROM_DEVICE);
514 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
515 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
516 DMA_FROM_DEVICE);
517 omap_aes_crypt_dma_stop(dd);
518 }
519
520 omap_crypto_cleanup(dd->in_sg, NULL, 0, dd->total_save,
521 FLAGS_IN_DATA_ST_SHIFT, dd->flags);
522
523 omap_crypto_cleanup(dd->out_sg, dd->orig_out, 0, dd->total_save,
524 FLAGS_OUT_DATA_ST_SHIFT, dd->flags);
525
526 /* Update IV output */
527 if (dd->flags & (FLAGS_CBC | FLAGS_CTR))
528 omap_aes_copy_ivout(dd, dd->req->iv);
529
530 omap_aes_finish_req(dd, 0);
531
532 pr_debug("exit\n");
533}
534
535static int omap_aes_crypt(struct skcipher_request *req, unsigned long mode)
536{
537 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(
538 crypto_skcipher_reqtfm(req));
539 struct omap_aes_reqctx *rctx = skcipher_request_ctx(req);
540 struct omap_aes_dev *dd;
541 int ret;
542
543 if ((req->cryptlen % AES_BLOCK_SIZE) && !(mode & FLAGS_CTR))
544 return -EINVAL;
545
546 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen,
547 !!(mode & FLAGS_ENCRYPT),
548 !!(mode & FLAGS_CBC));
549
550 if (req->cryptlen < aes_fallback_sz) {
551 skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback);
552 skcipher_request_set_callback(&rctx->fallback_req,
553 req->base.flags,
554 req->base.complete,
555 req->base.data);
556 skcipher_request_set_crypt(&rctx->fallback_req, req->src,
557 req->dst, req->cryptlen, req->iv);
558
559 if (mode & FLAGS_ENCRYPT)
560 ret = crypto_skcipher_encrypt(&rctx->fallback_req);
561 else
562 ret = crypto_skcipher_decrypt(&rctx->fallback_req);
563 return ret;
564 }
565 dd = omap_aes_find_dev(rctx);
566 if (!dd)
567 return -ENODEV;
568
569 rctx->mode = mode;
570
571 return omap_aes_handle_queue(dd, req);
572}
573
574/* ********************** ALG API ************************************ */
575
576static int omap_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,
577 unsigned int keylen)
578{
579 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
580 int ret;
581
582 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
583 keylen != AES_KEYSIZE_256)
584 return -EINVAL;
585
586 pr_debug("enter, keylen: %d\n", keylen);
587
588 memcpy(ctx->key, key, keylen);
589 ctx->keylen = keylen;
590
591 crypto_skcipher_clear_flags(ctx->fallback, CRYPTO_TFM_REQ_MASK);
592 crypto_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags &
593 CRYPTO_TFM_REQ_MASK);
594
595 ret = crypto_skcipher_setkey(ctx->fallback, key, keylen);
596 if (!ret)
597 return 0;
598
599 return 0;
600}
601
602static int omap_aes_ecb_encrypt(struct skcipher_request *req)
603{
604 return omap_aes_crypt(req, FLAGS_ENCRYPT);
605}
606
607static int omap_aes_ecb_decrypt(struct skcipher_request *req)
608{
609 return omap_aes_crypt(req, 0);
610}
611
612static int omap_aes_cbc_encrypt(struct skcipher_request *req)
613{
614 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
615}
616
617static int omap_aes_cbc_decrypt(struct skcipher_request *req)
618{
619 return omap_aes_crypt(req, FLAGS_CBC);
620}
621
622static int omap_aes_ctr_encrypt(struct skcipher_request *req)
623{
624 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR);
625}
626
627static int omap_aes_ctr_decrypt(struct skcipher_request *req)
628{
629 return omap_aes_crypt(req, FLAGS_CTR);
630}
631
632static int omap_aes_prepare_req(struct crypto_engine *engine,
633 void *req);
634static int omap_aes_crypt_req(struct crypto_engine *engine,
635 void *req);
636
637static int omap_aes_init_tfm(struct crypto_skcipher *tfm)
638{
639 const char *name = crypto_tfm_alg_name(&tfm->base);
640 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
641 struct crypto_skcipher *blk;
642
643 blk = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK);
644 if (IS_ERR(blk))
645 return PTR_ERR(blk);
646
647 ctx->fallback = blk;
648
649 crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_aes_reqctx) +
650 crypto_skcipher_reqsize(blk));
651
652 ctx->enginectx.op.prepare_request = omap_aes_prepare_req;
653 ctx->enginectx.op.unprepare_request = NULL;
654 ctx->enginectx.op.do_one_request = omap_aes_crypt_req;
655
656 return 0;
657}
658
659static void omap_aes_exit_tfm(struct crypto_skcipher *tfm)
660{
661 struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
662
663 if (ctx->fallback)
664 crypto_free_skcipher(ctx->fallback);
665
666 ctx->fallback = NULL;
667}
668
669/* ********************** ALGS ************************************ */
670
671static struct skcipher_alg algs_ecb_cbc[] = {
672{
673 .base.cra_name = "ecb(aes)",
674 .base.cra_driver_name = "ecb-aes-omap",
675 .base.cra_priority = 300,
676 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
677 CRYPTO_ALG_ASYNC |
678 CRYPTO_ALG_NEED_FALLBACK,
679 .base.cra_blocksize = AES_BLOCK_SIZE,
680 .base.cra_ctxsize = sizeof(struct omap_aes_ctx),
681 .base.cra_module = THIS_MODULE,
682
683 .min_keysize = AES_MIN_KEY_SIZE,
684 .max_keysize = AES_MAX_KEY_SIZE,
685 .setkey = omap_aes_setkey,
686 .encrypt = omap_aes_ecb_encrypt,
687 .decrypt = omap_aes_ecb_decrypt,
688 .init = omap_aes_init_tfm,
689 .exit = omap_aes_exit_tfm,
690},
691{
692 .base.cra_name = "cbc(aes)",
693 .base.cra_driver_name = "cbc-aes-omap",
694 .base.cra_priority = 300,
695 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
696 CRYPTO_ALG_ASYNC |
697 CRYPTO_ALG_NEED_FALLBACK,
698 .base.cra_blocksize = AES_BLOCK_SIZE,
699 .base.cra_ctxsize = sizeof(struct omap_aes_ctx),
700 .base.cra_module = THIS_MODULE,
701
702 .min_keysize = AES_MIN_KEY_SIZE,
703 .max_keysize = AES_MAX_KEY_SIZE,
704 .ivsize = AES_BLOCK_SIZE,
705 .setkey = omap_aes_setkey,
706 .encrypt = omap_aes_cbc_encrypt,
707 .decrypt = omap_aes_cbc_decrypt,
708 .init = omap_aes_init_tfm,
709 .exit = omap_aes_exit_tfm,
710}
711};
712
713static struct skcipher_alg algs_ctr[] = {
714{
715 .base.cra_name = "ctr(aes)",
716 .base.cra_driver_name = "ctr-aes-omap",
717 .base.cra_priority = 300,
718 .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
719 CRYPTO_ALG_ASYNC |
720 CRYPTO_ALG_NEED_FALLBACK,
721 .base.cra_blocksize = 1,
722 .base.cra_ctxsize = sizeof(struct omap_aes_ctx),
723 .base.cra_module = THIS_MODULE,
724
725 .min_keysize = AES_MIN_KEY_SIZE,
726 .max_keysize = AES_MAX_KEY_SIZE,
727 .ivsize = AES_BLOCK_SIZE,
728 .setkey = omap_aes_setkey,
729 .encrypt = omap_aes_ctr_encrypt,
730 .decrypt = omap_aes_ctr_decrypt,
731 .init = omap_aes_init_tfm,
732 .exit = omap_aes_exit_tfm,
733}
734};
735
736static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = {
737 {
738 .algs_list = algs_ecb_cbc,
739 .size = ARRAY_SIZE(algs_ecb_cbc),
740 },
741};
742
743static struct aead_alg algs_aead_gcm[] = {
744{
745 .base = {
746 .cra_name = "gcm(aes)",
747 .cra_driver_name = "gcm-aes-omap",
748 .cra_priority = 300,
749 .cra_flags = CRYPTO_ALG_ASYNC |
750 CRYPTO_ALG_KERN_DRIVER_ONLY,
751 .cra_blocksize = 1,
752 .cra_ctxsize = sizeof(struct omap_aes_gcm_ctx),
753 .cra_alignmask = 0xf,
754 .cra_module = THIS_MODULE,
755 },
756 .init = omap_aes_gcm_cra_init,
757 .ivsize = GCM_AES_IV_SIZE,
758 .maxauthsize = AES_BLOCK_SIZE,
759 .setkey = omap_aes_gcm_setkey,
760 .setauthsize = omap_aes_gcm_setauthsize,
761 .encrypt = omap_aes_gcm_encrypt,
762 .decrypt = omap_aes_gcm_decrypt,
763},
764{
765 .base = {
766 .cra_name = "rfc4106(gcm(aes))",
767 .cra_driver_name = "rfc4106-gcm-aes-omap",
768 .cra_priority = 300,
769 .cra_flags = CRYPTO_ALG_ASYNC |
770 CRYPTO_ALG_KERN_DRIVER_ONLY,
771 .cra_blocksize = 1,
772 .cra_ctxsize = sizeof(struct omap_aes_gcm_ctx),
773 .cra_alignmask = 0xf,
774 .cra_module = THIS_MODULE,
775 },
776 .init = omap_aes_gcm_cra_init,
777 .maxauthsize = AES_BLOCK_SIZE,
778 .ivsize = GCM_RFC4106_IV_SIZE,
779 .setkey = omap_aes_4106gcm_setkey,
780 .setauthsize = omap_aes_4106gcm_setauthsize,
781 .encrypt = omap_aes_4106gcm_encrypt,
782 .decrypt = omap_aes_4106gcm_decrypt,
783},
784};
785
786static struct omap_aes_aead_algs omap_aes_aead_info = {
787 .algs_list = algs_aead_gcm,
788 .size = ARRAY_SIZE(algs_aead_gcm),
789};
790
791static const struct omap_aes_pdata omap_aes_pdata_omap2 = {
792 .algs_info = omap_aes_algs_info_ecb_cbc,
793 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc),
794 .trigger = omap_aes_dma_trigger_omap2,
795 .key_ofs = 0x1c,
796 .iv_ofs = 0x20,
797 .ctrl_ofs = 0x30,
798 .data_ofs = 0x34,
799 .rev_ofs = 0x44,
800 .mask_ofs = 0x48,
801 .dma_enable_in = BIT(2),
802 .dma_enable_out = BIT(3),
803 .dma_start = BIT(5),
804 .major_mask = 0xf0,
805 .major_shift = 4,
806 .minor_mask = 0x0f,
807 .minor_shift = 0,
808};
809
810#ifdef CONFIG_OF
811static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = {
812 {
813 .algs_list = algs_ecb_cbc,
814 .size = ARRAY_SIZE(algs_ecb_cbc),
815 },
816 {
817 .algs_list = algs_ctr,
818 .size = ARRAY_SIZE(algs_ctr),
819 },
820};
821
822static const struct omap_aes_pdata omap_aes_pdata_omap3 = {
823 .algs_info = omap_aes_algs_info_ecb_cbc_ctr,
824 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
825 .trigger = omap_aes_dma_trigger_omap2,
826 .key_ofs = 0x1c,
827 .iv_ofs = 0x20,
828 .ctrl_ofs = 0x30,
829 .data_ofs = 0x34,
830 .rev_ofs = 0x44,
831 .mask_ofs = 0x48,
832 .dma_enable_in = BIT(2),
833 .dma_enable_out = BIT(3),
834 .dma_start = BIT(5),
835 .major_mask = 0xf0,
836 .major_shift = 4,
837 .minor_mask = 0x0f,
838 .minor_shift = 0,
839};
840
841static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
842 .algs_info = omap_aes_algs_info_ecb_cbc_ctr,
843 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
844 .aead_algs_info = &omap_aes_aead_info,
845 .trigger = omap_aes_dma_trigger_omap4,
846 .key_ofs = 0x3c,
847 .iv_ofs = 0x40,
848 .ctrl_ofs = 0x50,
849 .data_ofs = 0x60,
850 .rev_ofs = 0x80,
851 .mask_ofs = 0x84,
852 .irq_status_ofs = 0x8c,
853 .irq_enable_ofs = 0x90,
854 .dma_enable_in = BIT(5),
855 .dma_enable_out = BIT(6),
856 .major_mask = 0x0700,
857 .major_shift = 8,
858 .minor_mask = 0x003f,
859 .minor_shift = 0,
860};
861
862static irqreturn_t omap_aes_irq(int irq, void *dev_id)
863{
864 struct omap_aes_dev *dd = dev_id;
865 u32 status, i;
866 u32 *src, *dst;
867
868 status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd));
869 if (status & AES_REG_IRQ_DATA_IN) {
870 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
871
872 BUG_ON(!dd->in_sg);
873
874 BUG_ON(_calc_walked(in) > dd->in_sg->length);
875
876 src = sg_virt(dd->in_sg) + _calc_walked(in);
877
878 for (i = 0; i < AES_BLOCK_WORDS; i++) {
879 omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src);
880
881 scatterwalk_advance(&dd->in_walk, 4);
882 if (dd->in_sg->length == _calc_walked(in)) {
883 dd->in_sg = sg_next(dd->in_sg);
884 if (dd->in_sg) {
885 scatterwalk_start(&dd->in_walk,
886 dd->in_sg);
887 src = sg_virt(dd->in_sg) +
888 _calc_walked(in);
889 }
890 } else {
891 src++;
892 }
893 }
894
895 /* Clear IRQ status */
896 status &= ~AES_REG_IRQ_DATA_IN;
897 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
898
899 /* Enable DATA_OUT interrupt */
900 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4);
901
902 } else if (status & AES_REG_IRQ_DATA_OUT) {
903 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
904
905 BUG_ON(!dd->out_sg);
906
907 BUG_ON(_calc_walked(out) > dd->out_sg->length);
908
909 dst = sg_virt(dd->out_sg) + _calc_walked(out);
910
911 for (i = 0; i < AES_BLOCK_WORDS; i++) {
912 *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i));
913 scatterwalk_advance(&dd->out_walk, 4);
914 if (dd->out_sg->length == _calc_walked(out)) {
915 dd->out_sg = sg_next(dd->out_sg);
916 if (dd->out_sg) {
917 scatterwalk_start(&dd->out_walk,
918 dd->out_sg);
919 dst = sg_virt(dd->out_sg) +
920 _calc_walked(out);
921 }
922 } else {
923 dst++;
924 }
925 }
926
927 dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total);
928
929 /* Clear IRQ status */
930 status &= ~AES_REG_IRQ_DATA_OUT;
931 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
932
933 if (!dd->total)
934 /* All bytes read! */
935 tasklet_schedule(&dd->done_task);
936 else
937 /* Enable DATA_IN interrupt for next block */
938 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
939 }
940
941 return IRQ_HANDLED;
942}
943
944static const struct of_device_id omap_aes_of_match[] = {
945 {
946 .compatible = "ti,omap2-aes",
947 .data = &omap_aes_pdata_omap2,
948 },
949 {
950 .compatible = "ti,omap3-aes",
951 .data = &omap_aes_pdata_omap3,
952 },
953 {
954 .compatible = "ti,omap4-aes",
955 .data = &omap_aes_pdata_omap4,
956 },
957 {},
958};
959MODULE_DEVICE_TABLE(of, omap_aes_of_match);
960
961static int omap_aes_get_res_of(struct omap_aes_dev *dd,
962 struct device *dev, struct resource *res)
963{
964 struct device_node *node = dev->of_node;
965 int err = 0;
966
967 dd->pdata = of_device_get_match_data(dev);
968 if (!dd->pdata) {
969 dev_err(dev, "no compatible OF match\n");
970 err = -EINVAL;
971 goto err;
972 }
973
974 err = of_address_to_resource(node, 0, res);
975 if (err < 0) {
976 dev_err(dev, "can't translate OF node address\n");
977 err = -EINVAL;
978 goto err;
979 }
980
981err:
982 return err;
983}
984#else
985static const struct of_device_id omap_aes_of_match[] = {
986 {},
987};
988
989static int omap_aes_get_res_of(struct omap_aes_dev *dd,
990 struct device *dev, struct resource *res)
991{
992 return -EINVAL;
993}
994#endif
995
996static int omap_aes_get_res_pdev(struct omap_aes_dev *dd,
997 struct platform_device *pdev, struct resource *res)
998{
999 struct device *dev = &pdev->dev;
1000 struct resource *r;
1001 int err = 0;
1002
1003 /* Get the base address */
1004 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1005 if (!r) {
1006 dev_err(dev, "no MEM resource info\n");
1007 err = -ENODEV;
1008 goto err;
1009 }
1010 memcpy(res, r, sizeof(*res));
1011
1012 /* Only OMAP2/3 can be non-DT */
1013 dd->pdata = &omap_aes_pdata_omap2;
1014
1015err:
1016 return err;
1017}
1018
1019static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
1020 char *buf)
1021{
1022 return sprintf(buf, "%d\n", aes_fallback_sz);
1023}
1024
1025static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
1026 const char *buf, size_t size)
1027{
1028 ssize_t status;
1029 long value;
1030
1031 status = kstrtol(buf, 0, &value);
1032 if (status)
1033 return status;
1034
1035 /* HW accelerator only works with buffers > 9 */
1036 if (value < 9) {
1037 dev_err(dev, "minimum fallback size 9\n");
1038 return -EINVAL;
1039 }
1040
1041 aes_fallback_sz = value;
1042
1043 return size;
1044}
1045
1046static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr,
1047 char *buf)
1048{
1049 struct omap_aes_dev *dd = dev_get_drvdata(dev);
1050
1051 return sprintf(buf, "%d\n", dd->engine->queue.max_qlen);
1052}
1053
1054static ssize_t queue_len_store(struct device *dev,
1055 struct device_attribute *attr, const char *buf,
1056 size_t size)
1057{
1058 struct omap_aes_dev *dd;
1059 ssize_t status;
1060 long value;
1061 unsigned long flags;
1062
1063 status = kstrtol(buf, 0, &value);
1064 if (status)
1065 return status;
1066
1067 if (value < 1)
1068 return -EINVAL;
1069
1070 /*
1071 * Changing the queue size in fly is safe, if size becomes smaller
1072 * than current size, it will just not accept new entries until
1073 * it has shrank enough.
1074 */
1075 spin_lock_bh(&list_lock);
1076 list_for_each_entry(dd, &dev_list, list) {
1077 spin_lock_irqsave(&dd->lock, flags);
1078 dd->engine->queue.max_qlen = value;
1079 dd->aead_queue.base.max_qlen = value;
1080 spin_unlock_irqrestore(&dd->lock, flags);
1081 }
1082 spin_unlock_bh(&list_lock);
1083
1084 return size;
1085}
1086
1087static DEVICE_ATTR_RW(queue_len);
1088static DEVICE_ATTR_RW(fallback);
1089
1090static struct attribute *omap_aes_attrs[] = {
1091 &dev_attr_queue_len.attr,
1092 &dev_attr_fallback.attr,
1093 NULL,
1094};
1095
1096static const struct attribute_group omap_aes_attr_group = {
1097 .attrs = omap_aes_attrs,
1098};
1099
1100static int omap_aes_probe(struct platform_device *pdev)
1101{
1102 struct device *dev = &pdev->dev;
1103 struct omap_aes_dev *dd;
1104 struct skcipher_alg *algp;
1105 struct aead_alg *aalg;
1106 struct resource res;
1107 int err = -ENOMEM, i, j, irq = -1;
1108 u32 reg;
1109
1110 dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL);
1111 if (dd == NULL) {
1112 dev_err(dev, "unable to alloc data struct.\n");
1113 goto err_data;
1114 }
1115 dd->dev = dev;
1116 platform_set_drvdata(pdev, dd);
1117
1118 aead_init_queue(&dd->aead_queue, OMAP_AES_QUEUE_LENGTH);
1119
1120 err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) :
1121 omap_aes_get_res_pdev(dd, pdev, &res);
1122 if (err)
1123 goto err_res;
1124
1125 dd->io_base = devm_ioremap_resource(dev, &res);
1126 if (IS_ERR(dd->io_base)) {
1127 err = PTR_ERR(dd->io_base);
1128 goto err_res;
1129 }
1130 dd->phys_base = res.start;
1131
1132 pm_runtime_use_autosuspend(dev);
1133 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
1134
1135 pm_runtime_enable(dev);
1136 err = pm_runtime_resume_and_get(dev);
1137 if (err < 0) {
1138 dev_err(dev, "%s: failed to get_sync(%d)\n",
1139 __func__, err);
1140 goto err_pm_disable;
1141 }
1142
1143 omap_aes_dma_stop(dd);
1144
1145 reg = omap_aes_read(dd, AES_REG_REV(dd));
1146
1147 pm_runtime_put_sync(dev);
1148
1149 dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
1150 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1151 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1152
1153 tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
1154
1155 err = omap_aes_dma_init(dd);
1156 if (err == -EPROBE_DEFER) {
1157 goto err_irq;
1158 } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) {
1159 dd->pio_only = 1;
1160
1161 irq = platform_get_irq(pdev, 0);
1162 if (irq < 0) {
1163 err = irq;
1164 goto err_irq;
1165 }
1166
1167 err = devm_request_irq(dev, irq, omap_aes_irq, 0,
1168 dev_name(dev), dd);
1169 if (err) {
1170 dev_err(dev, "Unable to grab omap-aes IRQ\n");
1171 goto err_irq;
1172 }
1173 }
1174
1175 spin_lock_init(&dd->lock);
1176
1177 INIT_LIST_HEAD(&dd->list);
1178 spin_lock_bh(&list_lock);
1179 list_add_tail(&dd->list, &dev_list);
1180 spin_unlock_bh(&list_lock);
1181
1182 /* Initialize crypto engine */
1183 dd->engine = crypto_engine_alloc_init(dev, 1);
1184 if (!dd->engine) {
1185 err = -ENOMEM;
1186 goto err_engine;
1187 }
1188
1189 err = crypto_engine_start(dd->engine);
1190 if (err)
1191 goto err_engine;
1192
1193 for (i = 0; i < dd->pdata->algs_info_size; i++) {
1194 if (!dd->pdata->algs_info[i].registered) {
1195 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1196 algp = &dd->pdata->algs_info[i].algs_list[j];
1197
1198 pr_debug("reg alg: %s\n", algp->base.cra_name);
1199
1200 err = crypto_register_skcipher(algp);
1201 if (err)
1202 goto err_algs;
1203
1204 dd->pdata->algs_info[i].registered++;
1205 }
1206 }
1207 }
1208
1209 if (dd->pdata->aead_algs_info &&
1210 !dd->pdata->aead_algs_info->registered) {
1211 for (i = 0; i < dd->pdata->aead_algs_info->size; i++) {
1212 aalg = &dd->pdata->aead_algs_info->algs_list[i];
1213
1214 pr_debug("reg alg: %s\n", aalg->base.cra_name);
1215
1216 err = crypto_register_aead(aalg);
1217 if (err)
1218 goto err_aead_algs;
1219
1220 dd->pdata->aead_algs_info->registered++;
1221 }
1222 }
1223
1224 err = sysfs_create_group(&dev->kobj, &omap_aes_attr_group);
1225 if (err) {
1226 dev_err(dev, "could not create sysfs device attrs\n");
1227 goto err_aead_algs;
1228 }
1229
1230 return 0;
1231err_aead_algs:
1232 for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) {
1233 aalg = &dd->pdata->aead_algs_info->algs_list[i];
1234 crypto_unregister_aead(aalg);
1235 }
1236err_algs:
1237 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1238 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1239 crypto_unregister_skcipher(
1240 &dd->pdata->algs_info[i].algs_list[j]);
1241
1242err_engine:
1243 if (dd->engine)
1244 crypto_engine_exit(dd->engine);
1245
1246 omap_aes_dma_cleanup(dd);
1247err_irq:
1248 tasklet_kill(&dd->done_task);
1249err_pm_disable:
1250 pm_runtime_disable(dev);
1251err_res:
1252 dd = NULL;
1253err_data:
1254 dev_err(dev, "initialization failed.\n");
1255 return err;
1256}
1257
1258static int omap_aes_remove(struct platform_device *pdev)
1259{
1260 struct omap_aes_dev *dd = platform_get_drvdata(pdev);
1261 struct aead_alg *aalg;
1262 int i, j;
1263
1264 spin_lock_bh(&list_lock);
1265 list_del(&dd->list);
1266 spin_unlock_bh(&list_lock);
1267
1268 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1269 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) {
1270 crypto_unregister_skcipher(
1271 &dd->pdata->algs_info[i].algs_list[j]);
1272 dd->pdata->algs_info[i].registered--;
1273 }
1274
1275 for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) {
1276 aalg = &dd->pdata->aead_algs_info->algs_list[i];
1277 crypto_unregister_aead(aalg);
1278 dd->pdata->aead_algs_info->registered--;
1279 }
1280
1281 crypto_engine_exit(dd->engine);
1282
1283 tasklet_kill(&dd->done_task);
1284 omap_aes_dma_cleanup(dd);
1285 pm_runtime_disable(dd->dev);
1286
1287 sysfs_remove_group(&dd->dev->kobj, &omap_aes_attr_group);
1288
1289 return 0;
1290}
1291
1292#ifdef CONFIG_PM_SLEEP
1293static int omap_aes_suspend(struct device *dev)
1294{
1295 pm_runtime_put_sync(dev);
1296 return 0;
1297}
1298
1299static int omap_aes_resume(struct device *dev)
1300{
1301 pm_runtime_get_sync(dev);
1302 return 0;
1303}
1304#endif
1305
1306static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume);
1307
1308static struct platform_driver omap_aes_driver = {
1309 .probe = omap_aes_probe,
1310 .remove = omap_aes_remove,
1311 .driver = {
1312 .name = "omap-aes",
1313 .pm = &omap_aes_pm_ops,
1314 .of_match_table = omap_aes_of_match,
1315 },
1316};
1317
1318module_platform_driver(omap_aes_driver);
1319
1320MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
1321MODULE_LICENSE("GPL v2");
1322MODULE_AUTHOR("Dmitry Kasatkin");
1323