1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 *          mxser.c  -- MOXA Smartio/Industio family multiport serial driver.
   4 *
   5 *      Copyright (C) 1999-2006  Moxa Technologies (support@moxa.com).
   6 *	Copyright (C) 2006-2008  Jiri Slaby <jirislaby@gmail.com>
   7 *
   8 *      This code is loosely based on the 1.8 moxa driver which is based on
   9 *	Linux serial driver, written by Linus Torvalds, Theodore T'so and
  10 *	others.
  11 *
  12 *	Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
  13 *	<alan@lxorguk.ukuu.org.uk>. The original 1.8 code is available on
  14 *	www.moxa.com.
  15 *	- Fixed x86_64 cleanness
  16 */
  17
  18#include <linux/module.h>
  19#include <linux/errno.h>
  20#include <linux/signal.h>
  21#include <linux/sched.h>
  22#include <linux/timer.h>
  23#include <linux/interrupt.h>
  24#include <linux/tty.h>
  25#include <linux/tty_flip.h>
  26#include <linux/serial.h>
  27#include <linux/serial_reg.h>
  28#include <linux/major.h>
  29#include <linux/string.h>
  30#include <linux/fcntl.h>
  31#include <linux/ptrace.h>
  32#include <linux/ioport.h>
  33#include <linux/mm.h>
  34#include <linux/delay.h>
  35#include <linux/pci.h>
  36#include <linux/bitops.h>
  37#include <linux/slab.h>
  38#include <linux/ratelimit.h>
  39
  40#include <asm/io.h>
  41#include <asm/irq.h>
  42#include <linux/uaccess.h>
  43
  44/*
  45 *	Semi-public control interfaces
  46 */
  47
  48/*
  49 *	MOXA ioctls
  50 */
  51
  52#define MOXA			0x400
  53#define MOXA_SET_OP_MODE	(MOXA + 66)
  54#define MOXA_GET_OP_MODE	(MOXA + 67)
  55
  56#define RS232_MODE		0
  57#define RS485_2WIRE_MODE	1
  58#define RS422_MODE		2
  59#define RS485_4WIRE_MODE	3
  60#define OP_MODE_MASK		3
  61
  62/* --------------------------------------------------- */
  63
  64/*
  65 * Follow just what Moxa Must chip defines.
  66 *
  67 * When LCR register (offset 0x03) is written the following value, the Must chip
  68 * will enter enhanced mode. And a write to EFR (offset 0x02) bit 6,7 will
  69 * change bank.
  70 */
  71#define MOXA_MUST_ENTER_ENHANCED	0xBF
  72
  73/* when enhanced mode is enabled, access to general bank register */
  74#define MOXA_MUST_GDL_REGISTER		0x07
  75#define MOXA_MUST_GDL_MASK		0x7F
  76#define MOXA_MUST_GDL_HAS_BAD_DATA	0x80
  77
  78#define MOXA_MUST_LSR_RERR		0x80	/* error in receive FIFO */
  79/* enhanced register bank select and enhanced mode setting register */
  80/* This works only when LCR register equals to 0xBF */
  81#define MOXA_MUST_EFR_REGISTER		0x02
  82#define MOXA_MUST_EFR_EFRB_ENABLE	0x10 /* enhanced mode enable */
  83/* enhanced register bank set 0, 1, 2 */
  84#define MOXA_MUST_EFR_BANK0		0x00
  85#define MOXA_MUST_EFR_BANK1		0x40
  86#define MOXA_MUST_EFR_BANK2		0x80
  87#define MOXA_MUST_EFR_BANK3		0xC0
  88#define MOXA_MUST_EFR_BANK_MASK		0xC0
  89
  90/* set XON1 value register, when LCR=0xBF and change to bank0 */
  91#define MOXA_MUST_XON1_REGISTER		0x04
  92
  93/* set XON2 value register, when LCR=0xBF and change to bank0 */
  94#define MOXA_MUST_XON2_REGISTER		0x05
  95
  96/* set XOFF1 value register, when LCR=0xBF and change to bank0 */
  97#define MOXA_MUST_XOFF1_REGISTER	0x06
  98
  99/* set XOFF2 value register, when LCR=0xBF and change to bank0 */
 100#define MOXA_MUST_XOFF2_REGISTER	0x07
 101
 102#define MOXA_MUST_RBRTL_REGISTER	0x04
 103#define MOXA_MUST_RBRTH_REGISTER	0x05
 104#define MOXA_MUST_RBRTI_REGISTER	0x06
 105#define MOXA_MUST_THRTL_REGISTER	0x07
 106#define MOXA_MUST_ENUM_REGISTER		0x04
 107#define MOXA_MUST_HWID_REGISTER		0x05
 108#define MOXA_MUST_ECR_REGISTER		0x06
 109#define MOXA_MUST_CSR_REGISTER		0x07
 110
 111#define MOXA_MUST_FCR_GDA_MODE_ENABLE	0x20 /* good data mode enable */
 112#define MOXA_MUST_FCR_GDA_ONLY_ENABLE	0x10 /* only good data put into RxFIFO */
 113
 114#define MOXA_MUST_IER_ECTSI		0x80 /* enable CTS interrupt */
 115#define MOXA_MUST_IER_ERTSI		0x40 /* enable RTS interrupt */
 116#define MOXA_MUST_IER_XINT		0x20 /* enable Xon/Xoff interrupt */
 117#define MOXA_MUST_IER_EGDAI		0x10 /* enable GDA interrupt */
 118
 119#define MOXA_MUST_RECV_ISR		(UART_IER_RDI | MOXA_MUST_IER_EGDAI)
 120
 121/* GDA interrupt pending */
 122#define MOXA_MUST_IIR_GDA		0x1C
 123#define MOXA_MUST_IIR_RDA		0x04
 124#define MOXA_MUST_IIR_RTO		0x0C
 125#define MOXA_MUST_IIR_LSR		0x06
 126
 127/* received Xon/Xoff or specical interrupt pending */
 128#define MOXA_MUST_IIR_XSC		0x10
 129
 130/* RTS/CTS change state interrupt pending */
 131#define MOXA_MUST_IIR_RTSCTS		0x20
 132#define MOXA_MUST_IIR_MASK		0x3E
 133
 134#define MOXA_MUST_MCR_XON_FLAG		0x40
 135#define MOXA_MUST_MCR_XON_ANY		0x80
 136#define MOXA_MUST_MCR_TX_XON		0x08
 137
 138#define MOXA_MUST_EFR_SF_MASK		0x0F /* software flow control on chip mask value */
 139#define MOXA_MUST_EFR_SF_TX1		0x08 /* send Xon1/Xoff1 */
 140#define MOXA_MUST_EFR_SF_TX2		0x04 /* send Xon2/Xoff2 */
 141#define MOXA_MUST_EFR_SF_TX12		0x0C /* send Xon1,Xon2/Xoff1,Xoff2 */
 142#define MOXA_MUST_EFR_SF_TX_NO		0x00 /* don't send Xon/Xoff */
 143#define MOXA_MUST_EFR_SF_TX_MASK	0x0C /* Tx software flow control mask */
 144#define MOXA_MUST_EFR_SF_RX_NO		0x00 /* don't receive Xon/Xoff */
 145#define MOXA_MUST_EFR_SF_RX1		0x02 /* receive Xon1/Xoff1 */
 146#define MOXA_MUST_EFR_SF_RX2		0x01 /* receive Xon2/Xoff2 */
 147#define MOXA_MUST_EFR_SF_RX12		0x03 /* receive Xon1,Xon2/Xoff1,Xoff2 */
 148#define MOXA_MUST_EFR_SF_RX_MASK	0x03 /* Rx software flow control mask */
 149
 150#define	MXSERMAJOR	 174
 151
 152#define MXSER_BOARDS		4	/* Max. boards */
 153#define MXSER_PORTS_PER_BOARD	8	/* Max. ports per board */
 154#define MXSER_PORTS		(MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
 155#define MXSER_ISR_PASS_LIMIT	100
 156
 157#define WAKEUP_CHARS		256
 158
 159#define MXSER_BAUD_BASE		921600
 160#define MXSER_CUSTOM_DIVISOR	(MXSER_BAUD_BASE * 16)
 161
 162#define PCI_DEVICE_ID_MOXA_RC7000	0x0001
 163#define PCI_DEVICE_ID_MOXA_CP102	0x1020
 164#define PCI_DEVICE_ID_MOXA_CP102UL	0x1021
 165#define PCI_DEVICE_ID_MOXA_CP102U	0x1022
 166#define PCI_DEVICE_ID_MOXA_CP102UF	0x1023
 167#define PCI_DEVICE_ID_MOXA_C104		0x1040
 168#define PCI_DEVICE_ID_MOXA_CP104U	0x1041
 169#define PCI_DEVICE_ID_MOXA_CP104JU	0x1042
 170#define PCI_DEVICE_ID_MOXA_CP104EL	0x1043
 171#define PCI_DEVICE_ID_MOXA_POS104UL	0x1044
 172#define PCI_DEVICE_ID_MOXA_CB108	0x1080
 173#define PCI_DEVICE_ID_MOXA_CP112UL	0x1120
 174#define PCI_DEVICE_ID_MOXA_CT114	0x1140
 175#define PCI_DEVICE_ID_MOXA_CP114	0x1141
 176#define PCI_DEVICE_ID_MOXA_CB114	0x1142
 177#define PCI_DEVICE_ID_MOXA_CP114UL	0x1143
 178#define PCI_DEVICE_ID_MOXA_CP118U	0x1180
 179#define PCI_DEVICE_ID_MOXA_CP118EL	0x1181
 180#define PCI_DEVICE_ID_MOXA_CP132	0x1320
 181#define PCI_DEVICE_ID_MOXA_CP132U	0x1321
 182#define PCI_DEVICE_ID_MOXA_CP134U	0x1340
 183#define PCI_DEVICE_ID_MOXA_CB134I	0x1341
 184#define PCI_DEVICE_ID_MOXA_CP138U	0x1380
 185#define PCI_DEVICE_ID_MOXA_C168		0x1680
 186#define PCI_DEVICE_ID_MOXA_CP168U	0x1681
 187#define PCI_DEVICE_ID_MOXA_CP168EL	0x1682
 188
 189#define MXSER_NPORTS(ddata)		((ddata) & 0xffU)
 190#define MXSER_HIGHBAUD			0x0100
 191
 192enum mxser_must_hwid {
 193	MOXA_OTHER_UART		= 0x00,
 194	MOXA_MUST_MU150_HWID	= 0x01,
 195	MOXA_MUST_MU860_HWID	= 0x02,
 196};
 197
 198static const struct {
 199	u8 type;
 200	u8 fifo_size;
 201	u8 rx_high_water;
 202	u8 rx_low_water;
 203	speed_t max_baud;
 204} Gpci_uart_info[] = {
 205	{ MOXA_OTHER_UART,	 16, 14,  1, 921600 },
 206	{ MOXA_MUST_MU150_HWID,	 64, 48, 16, 230400 },
 207	{ MOXA_MUST_MU860_HWID, 128, 96, 32, 921600 }
 208};
 209#define UART_INFO_NUM	ARRAY_SIZE(Gpci_uart_info)
 210
 211
 212/* driver_data correspond to the lines in the structure above
 213   see also ISA probe function before you change something */
 214static const struct pci_device_id mxser_pcibrds[] = {
 215	{ PCI_DEVICE_DATA(MOXA, C168,		8) },
 216	{ PCI_DEVICE_DATA(MOXA, C104,		4) },
 217	{ PCI_DEVICE_DATA(MOXA, CP132,		2) },
 218	{ PCI_DEVICE_DATA(MOXA, CP114,		4) },
 219	{ PCI_DEVICE_DATA(MOXA, CT114,		4) },
 220	{ PCI_DEVICE_DATA(MOXA, CP102,		2 | MXSER_HIGHBAUD) },
 221	{ PCI_DEVICE_DATA(MOXA, CP104U,		4) },
 222	{ PCI_DEVICE_DATA(MOXA, CP168U,		8) },
 223	{ PCI_DEVICE_DATA(MOXA, CP132U,		2) },
 224	{ PCI_DEVICE_DATA(MOXA, CP134U,		4) },
 225	{ PCI_DEVICE_DATA(MOXA, CP104JU,	4) },
 226	{ PCI_DEVICE_DATA(MOXA, RC7000,		8) }, /* RC7000 */
 227	{ PCI_DEVICE_DATA(MOXA, CP118U,		8) },
 228	{ PCI_DEVICE_DATA(MOXA, CP102UL,	2) },
 229	{ PCI_DEVICE_DATA(MOXA, CP102U,		2) },
 230	{ PCI_DEVICE_DATA(MOXA, CP118EL,	8) },
 231	{ PCI_DEVICE_DATA(MOXA, CP168EL,	8) },
 232	{ PCI_DEVICE_DATA(MOXA, CP104EL,	4) },
 233	{ PCI_DEVICE_DATA(MOXA, CB108,		8) },
 234	{ PCI_DEVICE_DATA(MOXA, CB114,		4) },
 235	{ PCI_DEVICE_DATA(MOXA, CB134I,		4) },
 236	{ PCI_DEVICE_DATA(MOXA, CP138U,		8) },
 237	{ PCI_DEVICE_DATA(MOXA, POS104UL,	4) },
 238	{ PCI_DEVICE_DATA(MOXA, CP114UL,	4) },
 239	{ PCI_DEVICE_DATA(MOXA, CP102UF,	2) },
 240	{ PCI_DEVICE_DATA(MOXA, CP112UL,	2) },
 241	{ }
 242};
 243MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
 244
 245static int ttymajor = MXSERMAJOR;
 246
 247/* Variables for insmod */
 248
 249MODULE_AUTHOR("Casper Yang");
 250MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
 251module_param(ttymajor, int, 0);
 252MODULE_LICENSE("GPL");
 253
 254struct mxser_board;
 255
 256struct mxser_port {
 257	struct tty_port port;
 258	struct mxser_board *board;
 259
 260	unsigned long ioaddr;
 261	unsigned long opmode_ioaddr;
 262
 263	u8 rx_high_water;
 264	u8 rx_low_water;
 265	int type;		/* UART type */
 266
 267	u8 x_char;		/* xon/xoff character */
 268	u8 IER;			/* Interrupt Enable Register */
 269	u8 MCR;			/* Modem control register */
 270	u8 FCR;			/* FIFO control register */
 271
 272	struct async_icount icount; /* kernel counters for 4 input interrupts */
 273	unsigned int timeout;
 274
 275	u8 read_status_mask;
 276	u8 ignore_status_mask;
 277	u8 xmit_fifo_size;
 278
 279	spinlock_t slock;
 280};
 281
 282struct mxser_board {
 283	unsigned int idx;
 284	unsigned short nports;
 285	int irq;
 286	unsigned long vector;
 287
 288	enum mxser_must_hwid must_hwid;
 289	speed_t max_baud;
 290
 291	struct mxser_port ports[] __counted_by(nports);
 292};
 293
 294static DECLARE_BITMAP(mxser_boards, MXSER_BOARDS);
 295static struct tty_driver *mxvar_sdriver;
 296
 297static u8 __mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set,
 298		bool restore_LCR)
 299{
 300	u8 oldlcr, efr;
 301
 302	oldlcr = inb(baseio + UART_LCR);
 303	outb(MOXA_MUST_ENTER_ENHANCED, baseio + UART_LCR);
 304
 305	efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
 306	efr &= ~clear;
 307	efr |= set;
 308
 309	outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
 310
 311	if (restore_LCR)
 312		outb(oldlcr, baseio + UART_LCR);
 313
 314	return oldlcr;
 315}
 316
 317static u8 mxser_must_select_bank(unsigned long baseio, u8 bank)
 318{
 319	return __mxser_must_set_EFR(baseio, MOXA_MUST_EFR_BANK_MASK, bank,
 320			false);
 321}
 322
 323static void mxser_set_must_xon1_value(unsigned long baseio, u8 value)
 324{
 325	u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0);
 326	outb(value, baseio + MOXA_MUST_XON1_REGISTER);
 327	outb(oldlcr, baseio + UART_LCR);
 328}
 329
 330static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value)
 331{
 332	u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0);
 333	outb(value, baseio + MOXA_MUST_XOFF1_REGISTER);
 334	outb(oldlcr, baseio + UART_LCR);
 335}
 336
 337static void mxser_set_must_fifo_value(struct mxser_port *info)
 338{
 339	u8 oldlcr = mxser_must_select_bank(info->ioaddr, MOXA_MUST_EFR_BANK1);
 340	outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER);
 341	outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTI_REGISTER);
 342	outb(info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER);
 343	outb(oldlcr, info->ioaddr + UART_LCR);
 344}
 345
 346static void mxser_set_must_enum_value(unsigned long baseio, u8 value)
 347{
 348	u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2);
 349	outb(value, baseio + MOXA_MUST_ENUM_REGISTER);
 350	outb(oldlcr, baseio + UART_LCR);
 351}
 352
 353static u8 mxser_get_must_hardware_id(unsigned long baseio)
 354{
 355	u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2);
 356	u8 id = inb(baseio + MOXA_MUST_HWID_REGISTER);
 357	outb(oldlcr, baseio + UART_LCR);
 358
 359	return id;
 360}
 361
 362static void mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set)
 363{
 364	__mxser_must_set_EFR(baseio, clear, set, true);
 365}
 366
 367static void mxser_must_set_enhance_mode(unsigned long baseio, bool enable)
 368{
 369	mxser_must_set_EFR(baseio,
 370			enable ? 0 : MOXA_MUST_EFR_EFRB_ENABLE,
 371			enable ? MOXA_MUST_EFR_EFRB_ENABLE : 0);
 372}
 373
 374static void mxser_must_no_sw_flow_control(unsigned long baseio)
 375{
 376	mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_MASK, 0);
 377}
 378
 379static void mxser_must_set_tx_sw_flow_control(unsigned long baseio, bool enable)
 380{
 381	mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_TX_MASK,
 382			enable ? MOXA_MUST_EFR_SF_TX1 : 0);
 383}
 384
 385static void mxser_must_set_rx_sw_flow_control(unsigned long baseio, bool enable)
 386{
 387	mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_RX_MASK,
 388			enable ? MOXA_MUST_EFR_SF_RX1 : 0);
 389}
 390
 391static enum mxser_must_hwid mxser_must_get_hwid(unsigned long io)
 392{
 393	u8 oldmcr, hwid;
 394	int i;
 395
 396	outb(0, io + UART_LCR);
 397	mxser_must_set_enhance_mode(io, false);
 398	oldmcr = inb(io + UART_MCR);
 399	outb(0, io + UART_MCR);
 400	mxser_set_must_xon1_value(io, 0x11);
 401	if (inb(io + UART_MCR) != 0) {
 402		outb(oldmcr, io + UART_MCR);
 403		return MOXA_OTHER_UART;
 404	}
 405
 406	hwid = mxser_get_must_hardware_id(io);
 407	for (i = 1; i < UART_INFO_NUM; i++) /* 0 = OTHER_UART */
 408		if (hwid == Gpci_uart_info[i].type)
 409			return hwid;
 410
 411	return MOXA_OTHER_UART;
 412}
 413
 414static bool mxser_16550A_or_MUST(struct mxser_port *info)
 415{
 416	return info->type == PORT_16550A || info->board->must_hwid;
 417}
 418
 419static void mxser_process_txrx_fifo(struct mxser_port *info)
 420{
 421	unsigned int i;
 422
 423	if (info->type == PORT_16450 || info->type == PORT_8250) {
 424		info->rx_high_water = 1;
 425		info->rx_low_water = 1;
 426		info->xmit_fifo_size = 1;
 427		return;
 428	}
 429
 430	for (i = 0; i < UART_INFO_NUM; i++)
 431		if (info->board->must_hwid == Gpci_uart_info[i].type) {
 432			info->rx_low_water = Gpci_uart_info[i].rx_low_water;
 433			info->rx_high_water = Gpci_uart_info[i].rx_high_water;
 434			info->xmit_fifo_size = Gpci_uart_info[i].fifo_size;
 435			break;
 436		}
 437}
 438
 439static void __mxser_start_tx(struct mxser_port *info)
 440{
 441	outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
 442	info->IER |= UART_IER_THRI;
 443	outb(info->IER, info->ioaddr + UART_IER);
 444}
 445
 446static void mxser_start_tx(struct mxser_port *info)
 447{
 448	unsigned long flags;
 449
 450	spin_lock_irqsave(&info->slock, flags);
 451	__mxser_start_tx(info);
 452	spin_unlock_irqrestore(&info->slock, flags);
 453}
 454
 455static void __mxser_stop_tx(struct mxser_port *info)
 456{
 457	info->IER &= ~UART_IER_THRI;
 458	outb(info->IER, info->ioaddr + UART_IER);
 459}
 460
 461static bool mxser_carrier_raised(struct tty_port *port)
 462{
 463	struct mxser_port *mp = container_of(port, struct mxser_port, port);
 464
 465	return inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD;
 466}
 467
 468static void mxser_dtr_rts(struct tty_port *port, bool active)
 469{
 470	struct mxser_port *mp = container_of(port, struct mxser_port, port);
 471	unsigned long flags;
 472	u8 mcr;
 473
 474	spin_lock_irqsave(&mp->slock, flags);
 475	mcr = inb(mp->ioaddr + UART_MCR);
 476	if (active)
 477		mcr |= UART_MCR_DTR | UART_MCR_RTS;
 478	else
 479		mcr &= ~(UART_MCR_DTR | UART_MCR_RTS);
 480	outb(mcr, mp->ioaddr + UART_MCR);
 481	spin_unlock_irqrestore(&mp->slock, flags);
 482}
 483
 484static int mxser_set_baud(struct tty_struct *tty, speed_t newspd)
 485{
 486	struct mxser_port *info = tty->driver_data;
 487	unsigned int quot = 0, baud;
 488	unsigned char cval;
 489	u64 timeout;
 490
 491	if (newspd > info->board->max_baud)
 492		return -1;
 493
 494	if (newspd == 134) {
 495		quot = 2 * MXSER_BAUD_BASE / 269;
 496		tty_encode_baud_rate(tty, 134, 134);
 497	} else if (newspd) {
 498		quot = MXSER_BAUD_BASE / newspd;
 499		if (quot == 0)
 500			quot = 1;
 501		baud = MXSER_BAUD_BASE / quot;
 502		tty_encode_baud_rate(tty, baud, baud);
 503	} else {
 504		quot = 0;
 505	}
 506
 507	/*
 508	 * worst case (128 * 1000 * 10 * 18432) needs 35 bits, so divide in the
 509	 * u64 domain
 510	 */
 511	timeout = (u64)info->xmit_fifo_size * HZ * 10 * quot;
 512	do_div(timeout, MXSER_BAUD_BASE);
 513	info->timeout = timeout + HZ / 50; /* Add .02 seconds of slop */
 514
 515	if (quot) {
 516		info->MCR |= UART_MCR_DTR;
 517		outb(info->MCR, info->ioaddr + UART_MCR);
 518	} else {
 519		info->MCR &= ~UART_MCR_DTR;
 520		outb(info->MCR, info->ioaddr + UART_MCR);
 521		return 0;
 522	}
 523
 524	cval = inb(info->ioaddr + UART_LCR);
 525
 526	outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR);	/* set DLAB */
 527
 528	outb(quot & 0xff, info->ioaddr + UART_DLL);	/* LS of divisor */
 529	outb(quot >> 8, info->ioaddr + UART_DLM);	/* MS of divisor */
 530	outb(cval, info->ioaddr + UART_LCR);	/* reset DLAB */
 531
 532	if (C_BAUD(tty) == BOTHER) {
 533		quot = MXSER_BAUD_BASE % newspd;
 534		quot *= 8;
 535		if (quot % newspd > newspd / 2) {
 536			quot /= newspd;
 537			quot++;
 538		} else
 539			quot /= newspd;
 540
 541		mxser_set_must_enum_value(info->ioaddr, quot);
 542	} else {
 543		mxser_set_must_enum_value(info->ioaddr, 0);
 544	}
 545
 546	return 0;
 547}
 548
 549static void mxser_handle_cts(struct tty_struct *tty, struct mxser_port *info,
 550		u8 msr)
 551{
 552	bool cts = msr & UART_MSR_CTS;
 553
 554	if (tty->hw_stopped) {
 555		if (cts) {
 556			tty->hw_stopped = false;
 557
 558			if (!mxser_16550A_or_MUST(info))
 559				__mxser_start_tx(info);
 560			tty_wakeup(tty);
 561		}
 562		return;
 563	} else if (cts)
 564		return;
 565
 566	tty->hw_stopped = true;
 567	if (!mxser_16550A_or_MUST(info))
 568		__mxser_stop_tx(info);
 569}
 570
 571/*
 572 * This routine is called to set the UART divisor registers to match
 573 * the specified baud rate for a serial port.
 574 */
 575static void mxser_change_speed(struct tty_struct *tty,
 576			       const struct ktermios *old_termios)
 577{
 578	struct mxser_port *info = tty->driver_data;
 579	unsigned cflag, cval;
 580
 581	cflag = tty->termios.c_cflag;
 582
 583	if (mxser_set_baud(tty, tty_get_baud_rate(tty))) {
 584		/* Use previous rate on a failure */
 585		if (old_termios) {
 586			speed_t baud = tty_termios_baud_rate(old_termios);
 587			tty_encode_baud_rate(tty, baud, baud);
 588		}
 589	}
 590
 591	/* byte size and parity */
 592	cval = UART_LCR_WLEN(tty_get_char_size(tty->termios.c_cflag));
 593
 594	if (cflag & CSTOPB)
 595		cval |= UART_LCR_STOP;
 596	if (cflag & PARENB)
 597		cval |= UART_LCR_PARITY;
 598	if (!(cflag & PARODD))
 599		cval |= UART_LCR_EPAR;
 600	if (cflag & CMSPAR)
 601		cval |= UART_LCR_SPAR;
 602
 603	info->FCR = 0;
 604	if (info->board->must_hwid) {
 605		info->FCR |= UART_FCR_ENABLE_FIFO |
 606			MOXA_MUST_FCR_GDA_MODE_ENABLE;
 607		mxser_set_must_fifo_value(info);
 608	} else if (info->type != PORT_8250 && info->type != PORT_16450) {
 609		info->FCR |= UART_FCR_ENABLE_FIFO;
 610		switch (info->rx_high_water) {
 611		case 1:
 612			info->FCR |= UART_FCR_TRIGGER_1;
 613			break;
 614		case 4:
 615			info->FCR |= UART_FCR_TRIGGER_4;
 616			break;
 617		case 8:
 618			info->FCR |= UART_FCR_TRIGGER_8;
 619			break;
 620		default:
 621			info->FCR |= UART_FCR_TRIGGER_14;
 622			break;
 623		}
 624	}
 625
 626	/* CTS flow control flag and modem status interrupts */
 627	info->IER &= ~UART_IER_MSI;
 628	info->MCR &= ~UART_MCR_AFE;
 629	tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
 630	if (cflag & CRTSCTS) {
 631		info->IER |= UART_IER_MSI;
 632		if (mxser_16550A_or_MUST(info)) {
 633			info->MCR |= UART_MCR_AFE;
 634		} else {
 635			mxser_handle_cts(tty, info,
 636					inb(info->ioaddr + UART_MSR));
 637		}
 638	}
 639	outb(info->MCR, info->ioaddr + UART_MCR);
 640	tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
 641	if (~cflag & CLOCAL)
 642		info->IER |= UART_IER_MSI;
 643	outb(info->IER, info->ioaddr + UART_IER);
 644
 645	/*
 646	 * Set up parity check flag
 647	 */
 648	info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 649	if (I_INPCK(tty))
 650		info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 651	if (I_BRKINT(tty) || I_PARMRK(tty))
 652		info->read_status_mask |= UART_LSR_BI;
 653
 654	info->ignore_status_mask = 0;
 655
 656	if (I_IGNBRK(tty)) {
 657		info->ignore_status_mask |= UART_LSR_BI;
 658		info->read_status_mask |= UART_LSR_BI;
 659		/*
 660		 * If we're ignore parity and break indicators, ignore
 661		 * overruns too.  (For real raw support).
 662		 */
 663		if (I_IGNPAR(tty)) {
 664			info->ignore_status_mask |=
 665						UART_LSR_OE |
 666						UART_LSR_PE |
 667						UART_LSR_FE;
 668			info->read_status_mask |=
 669						UART_LSR_OE |
 670						UART_LSR_PE |
 671						UART_LSR_FE;
 672		}
 673	}
 674	if (info->board->must_hwid) {
 675		mxser_set_must_xon1_value(info->ioaddr, START_CHAR(tty));
 676		mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(tty));
 677		mxser_must_set_rx_sw_flow_control(info->ioaddr, I_IXON(tty));
 678		mxser_must_set_tx_sw_flow_control(info->ioaddr, I_IXOFF(tty));
 679	}
 680
 681
 682	outb(info->FCR, info->ioaddr + UART_FCR);
 683	outb(cval, info->ioaddr + UART_LCR);
 684}
 685
 686static u8 mxser_check_modem_status(struct tty_struct *tty,
 687				struct mxser_port *port)
 688{
 689	u8 msr = inb(port->ioaddr + UART_MSR);
 690
 691	if (!(msr & UART_MSR_ANY_DELTA))
 692		return msr;
 693
 694	/* update input line counters */
 695	if (msr & UART_MSR_TERI)
 696		port->icount.rng++;
 697	if (msr & UART_MSR_DDSR)
 698		port->icount.dsr++;
 699	if (msr & UART_MSR_DDCD)
 700		port->icount.dcd++;
 701	if (msr & UART_MSR_DCTS)
 702		port->icount.cts++;
 703	wake_up_interruptible(&port->port.delta_msr_wait);
 704
 705	if (tty_port_check_carrier(&port->port) && (msr & UART_MSR_DDCD)) {
 706		if (msr & UART_MSR_DCD)
 707			wake_up_interruptible(&port->port.open_wait);
 708	}
 709
 710	if (tty_port_cts_enabled(&port->port))
 711		mxser_handle_cts(tty, port, msr);
 712
 713	return msr;
 714}
 715
 716static void mxser_disable_and_clear_FIFO(struct mxser_port *info)
 717{
 718	u8 fcr = UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT;
 719
 720	if (info->board->must_hwid)
 721		fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
 722
 723	outb(fcr, info->ioaddr + UART_FCR);
 724}
 725
 726static int mxser_activate(struct tty_port *port, struct tty_struct *tty)
 727{
 728	struct mxser_port *info = container_of(port, struct mxser_port, port);
 729	unsigned long flags;
 730	int ret;
 731
 732	ret = tty_port_alloc_xmit_buf(port);
 733	if (ret < 0)
 734		return ret;
 735
 736	spin_lock_irqsave(&info->slock, flags);
 737
 738	if (!info->type) {
 739		set_bit(TTY_IO_ERROR, &tty->flags);
 740		spin_unlock_irqrestore(&info->slock, flags);
 741		ret = 0;
 742		goto err_free_xmit;
 743	}
 744
 745	/*
 746	 * Clear the FIFO buffers and disable them
 747	 * (they will be reenabled in mxser_change_speed())
 748	 */
 749	mxser_disable_and_clear_FIFO(info);
 750
 751	/*
 752	 * At this point there's no way the LSR could still be 0xFF;
 753	 * if it is, then bail out, because there's likely no UART
 754	 * here.
 755	 */
 756	if (inb(info->ioaddr + UART_LSR) == 0xff) {
 757		spin_unlock_irqrestore(&info->slock, flags);
 758		if (capable(CAP_SYS_ADMIN)) {
 759			set_bit(TTY_IO_ERROR, &tty->flags);
 760			return 0;
 761		}
 762
 763		ret = -ENODEV;
 764		goto err_free_xmit;
 765	}
 766
 767	/*
 768	 * Clear the interrupt registers.
 769	 */
 770	(void) inb(info->ioaddr + UART_LSR);
 771	(void) inb(info->ioaddr + UART_RX);
 772	(void) inb(info->ioaddr + UART_IIR);
 773	(void) inb(info->ioaddr + UART_MSR);
 774
 775	/*
 776	 * Now, initialize the UART
 777	 */
 778	outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR);	/* reset DLAB */
 779	info->MCR = UART_MCR_DTR | UART_MCR_RTS;
 780	outb(info->MCR, info->ioaddr + UART_MCR);
 781
 782	/*
 783	 * Finally, enable interrupts
 784	 */
 785	info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
 786
 787	if (info->board->must_hwid)
 788		info->IER |= MOXA_MUST_IER_EGDAI;
 789	outb(info->IER, info->ioaddr + UART_IER);	/* enable interrupts */
 790
 791	/*
 792	 * And clear the interrupt registers again for luck.
 793	 */
 794	(void) inb(info->ioaddr + UART_LSR);
 795	(void) inb(info->ioaddr + UART_RX);
 796	(void) inb(info->ioaddr + UART_IIR);
 797	(void) inb(info->ioaddr + UART_MSR);
 798
 799	clear_bit(TTY_IO_ERROR, &tty->flags);
 800	kfifo_reset(&port->xmit_fifo);
 801
 802	/*
 803	 * and set the speed of the serial port
 804	 */
 805	mxser_change_speed(tty, NULL);
 806	spin_unlock_irqrestore(&info->slock, flags);
 807
 808	return 0;
 809err_free_xmit:
 810	tty_port_free_xmit_buf(port);
 811	return ret;
 812}
 813
 814/*
 815 * To stop accepting input, we disable the receive line status interrupts, and
 816 * tell the interrupt driver to stop checking the data ready bit in the line
 817 * status register.
 818 */
 819static void mxser_stop_rx(struct mxser_port *info)
 820{
 821	info->IER &= ~UART_IER_RLSI;
 822	if (info->board->must_hwid)
 823		info->IER &= ~MOXA_MUST_RECV_ISR;
 824
 825	outb(info->IER, info->ioaddr + UART_IER);
 826}
 827
 828/*
 829 * This routine will shutdown a serial port
 830 */
 831static void mxser_shutdown_port(struct tty_port *port)
 832{
 833	struct mxser_port *info = container_of(port, struct mxser_port, port);
 834	unsigned long flags;
 835
 836	spin_lock_irqsave(&info->slock, flags);
 837
 838	mxser_stop_rx(info);
 839
 840	/*
 841	 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
 842	 * here so the queue might never be waken up
 843	 */
 844	wake_up_interruptible(&info->port.delta_msr_wait);
 845
 846	info->IER = 0;
 847	outb(0x00, info->ioaddr + UART_IER);
 848
 849	/* clear Rx/Tx FIFO's */
 850	mxser_disable_and_clear_FIFO(info);
 851
 852	/* read data port to reset things */
 853	(void) inb(info->ioaddr + UART_RX);
 854
 855
 856	if (info->board->must_hwid)
 857		mxser_must_no_sw_flow_control(info->ioaddr);
 858
 859	spin_unlock_irqrestore(&info->slock, flags);
 860
 861	/* make sure ISR is not running while we free the buffer */
 862	synchronize_irq(info->board->irq);
 863
 864	tty_port_free_xmit_buf(port);
 865}
 866
 867/*
 868 * This routine is called whenever a serial port is opened.  It
 869 * enables interrupts for a serial port, linking in its async structure into
 870 * the IRQ chain.   It also performs the serial-specific
 871 * initialization for the tty structure.
 872 */
 873static int mxser_open(struct tty_struct *tty, struct file *filp)
 874{
 875	struct tty_port *tport = tty->port;
 876	struct mxser_port *port = container_of(tport, struct mxser_port, port);
 877
 878	tty->driver_data = port;
 879
 880	return tty_port_open(tport, tty, filp);
 881}
 882
 883static void mxser_flush_buffer(struct tty_struct *tty)
 884{
 885	struct mxser_port *info = tty->driver_data;
 886	unsigned long flags;
 887
 888	spin_lock_irqsave(&info->slock, flags);
 889	kfifo_reset(&info->port.xmit_fifo);
 890
 891	outb(info->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
 892		info->ioaddr + UART_FCR);
 893
 894	spin_unlock_irqrestore(&info->slock, flags);
 895
 896	tty_wakeup(tty);
 897}
 898
 899static void mxser_close(struct tty_struct *tty, struct file *filp)
 900{
 901	tty_port_close(tty->port, tty, filp);
 902}
 903
 904static ssize_t mxser_write(struct tty_struct *tty, const u8 *buf, size_t count)
 905{
 906	struct mxser_port *info = tty->driver_data;
 907	unsigned long flags;
 908	size_t written;
 909	bool is_empty;
 910
 911	spin_lock_irqsave(&info->slock, flags);
 912	written = kfifo_in(&info->port.xmit_fifo, buf, count);
 913	is_empty = kfifo_is_empty(&info->port.xmit_fifo);
 914	spin_unlock_irqrestore(&info->slock, flags);
 915
 916	if (!is_empty && !tty->flow.stopped)
 917		if (!tty->hw_stopped || mxser_16550A_or_MUST(info))
 918			mxser_start_tx(info);
 919
 920	return written;
 921}
 922
 923static int mxser_put_char(struct tty_struct *tty, u8 ch)
 924{
 925	struct mxser_port *info = tty->driver_data;
 926	unsigned long flags;
 927	int ret;
 928
 929	spin_lock_irqsave(&info->slock, flags);
 930	ret = kfifo_put(&info->port.xmit_fifo, ch);
 931	spin_unlock_irqrestore(&info->slock, flags);
 932
 933	return ret;
 934}
 935
 936
 937static void mxser_flush_chars(struct tty_struct *tty)
 938{
 939	struct mxser_port *info = tty->driver_data;
 940
 941	if (kfifo_is_empty(&info->port.xmit_fifo) || tty->flow.stopped ||
 942			(tty->hw_stopped && !mxser_16550A_or_MUST(info)))
 943		return;
 944
 945	mxser_start_tx(info);
 946}
 947
 948static unsigned int mxser_write_room(struct tty_struct *tty)
 949{
 950	struct mxser_port *info = tty->driver_data;
 951
 952	return kfifo_avail(&info->port.xmit_fifo);
 953}
 954
 955static unsigned int mxser_chars_in_buffer(struct tty_struct *tty)
 956{
 957	struct mxser_port *info = tty->driver_data;
 958
 959	return kfifo_len(&info->port.xmit_fifo);
 960}
 961
 962/*
 963 * ------------------------------------------------------------
 964 * friends of mxser_ioctl()
 965 * ------------------------------------------------------------
 966 */
 967static int mxser_get_serial_info(struct tty_struct *tty,
 968		struct serial_struct *ss)
 969{
 970	struct mxser_port *info = tty->driver_data;
 971	struct tty_port *port = &info->port;
 972	unsigned int closing_wait, close_delay;
 973
 974	mutex_lock(&port->mutex);
 975
 976	close_delay = jiffies_to_msecs(info->port.close_delay) / 10;
 977	closing_wait = info->port.closing_wait;
 978	if (closing_wait != ASYNC_CLOSING_WAIT_NONE)
 979		closing_wait = jiffies_to_msecs(closing_wait) / 10;
 980
 981	ss->type = info->type;
 982	ss->line = tty->index;
 983	ss->port = info->ioaddr;
 984	ss->irq = info->board->irq;
 985	ss->flags = info->port.flags;
 986	ss->baud_base = MXSER_BAUD_BASE;
 987	ss->close_delay = close_delay;
 988	ss->closing_wait = closing_wait;
 989	ss->custom_divisor = MXSER_CUSTOM_DIVISOR,
 990	mutex_unlock(&port->mutex);
 991	return 0;
 992}
 993
 994static int mxser_set_serial_info(struct tty_struct *tty,
 995		struct serial_struct *ss)
 996{
 997	struct mxser_port *info = tty->driver_data;
 998	struct tty_port *port = &info->port;
 999	speed_t baud;
1000	unsigned long sl_flags;
1001	unsigned int old_speed, close_delay, closing_wait;
1002	int retval = 0;
1003
1004	if (tty_io_error(tty))
1005		return -EIO;
1006
1007	mutex_lock(&port->mutex);
1008
1009	if (ss->irq != info->board->irq ||
1010			ss->port != info->ioaddr) {
1011		mutex_unlock(&port->mutex);
1012		return -EINVAL;
1013	}
1014
1015	old_speed = port->flags & ASYNC_SPD_MASK;
1016
1017	close_delay = msecs_to_jiffies(ss->close_delay * 10);
1018	closing_wait = ss->closing_wait;
1019	if (closing_wait != ASYNC_CLOSING_WAIT_NONE)
1020		closing_wait = msecs_to_jiffies(closing_wait * 10);
1021
1022	if (!capable(CAP_SYS_ADMIN)) {
1023		if ((ss->baud_base != MXSER_BAUD_BASE) ||
1024				(close_delay != port->close_delay) ||
1025				(closing_wait != port->closing_wait) ||
1026				((ss->flags & ~ASYNC_USR_MASK) != (port->flags & ~ASYNC_USR_MASK))) {
1027			mutex_unlock(&port->mutex);
1028			return -EPERM;
1029		}
1030		port->flags = (port->flags & ~ASYNC_USR_MASK) |
1031				(ss->flags & ASYNC_USR_MASK);
1032	} else {
1033		/*
1034		 * OK, past this point, all the error checking has been done.
1035		 * At this point, we start making changes.....
1036		 */
1037		port->flags = ((port->flags & ~ASYNC_FLAGS) |
1038				(ss->flags & ASYNC_FLAGS));
1039		port->close_delay = close_delay;
1040		port->closing_wait = closing_wait;
1041		if ((port->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST &&
1042				(ss->baud_base != MXSER_BAUD_BASE ||
1043				ss->custom_divisor !=
1044				MXSER_CUSTOM_DIVISOR)) {
1045			if (ss->custom_divisor == 0) {
1046				mutex_unlock(&port->mutex);
1047				return -EINVAL;
1048			}
1049			baud = ss->baud_base / ss->custom_divisor;
1050			tty_encode_baud_rate(tty, baud, baud);
1051		}
1052
1053		info->type = ss->type;
1054
1055		mxser_process_txrx_fifo(info);
1056	}
1057
1058	if (tty_port_initialized(port)) {
1059		if (old_speed != (port->flags & ASYNC_SPD_MASK)) {
1060			spin_lock_irqsave(&info->slock, sl_flags);
1061			mxser_change_speed(tty, NULL);
1062			spin_unlock_irqrestore(&info->slock, sl_flags);
1063		}
1064	} else {
1065		retval = mxser_activate(port, tty);
1066		if (retval == 0)
1067			tty_port_set_initialized(port, true);
1068	}
1069	mutex_unlock(&port->mutex);
1070	return retval;
1071}
1072
1073/*
1074 * mxser_get_lsr_info - get line status register info
1075 *
1076 * Purpose: Let user call ioctl() to get info when the UART physically
1077 *	    is emptied.  On bus types like RS485, the transmitter must
1078 *	    release the bus after transmitting. This must be done when
1079 *	    the transmit shift register is empty, not be done when the
1080 *	    transmit holding register is empty.  This functionality
1081 *	    allows an RS485 driver to be written in user space.
1082 */
1083static int mxser_get_lsr_info(struct mxser_port *info,
1084		unsigned int __user *value)
1085{
1086	unsigned char status;
1087	unsigned int result;
1088	unsigned long flags;
1089
1090	spin_lock_irqsave(&info->slock, flags);
1091	status = inb(info->ioaddr + UART_LSR);
1092	spin_unlock_irqrestore(&info->slock, flags);
1093	result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
1094	return put_user(result, value);
1095}
1096
1097static int mxser_tiocmget(struct tty_struct *tty)
1098{
1099	struct mxser_port *info = tty->driver_data;
1100	unsigned char control;
1101	unsigned long flags;
1102	u8 msr;
1103
1104	if (tty_io_error(tty))
1105		return -EIO;
1106
1107	spin_lock_irqsave(&info->slock, flags);
1108	control = info->MCR;
1109	msr = mxser_check_modem_status(tty, info);
1110	spin_unlock_irqrestore(&info->slock, flags);
1111
1112	return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
1113		    ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
1114		    ((msr & UART_MSR_DCD) ? TIOCM_CAR : 0) |
1115		    ((msr & UART_MSR_RI) ? TIOCM_RNG : 0) |
1116		    ((msr & UART_MSR_DSR) ? TIOCM_DSR : 0) |
1117		    ((msr & UART_MSR_CTS) ? TIOCM_CTS : 0);
1118}
1119
1120static int mxser_tiocmset(struct tty_struct *tty,
1121		unsigned int set, unsigned int clear)
1122{
1123	struct mxser_port *info = tty->driver_data;
1124	unsigned long flags;
1125
1126	if (tty_io_error(tty))
1127		return -EIO;
1128
1129	spin_lock_irqsave(&info->slock, flags);
1130
1131	if (set & TIOCM_RTS)
1132		info->MCR |= UART_MCR_RTS;
1133	if (set & TIOCM_DTR)
1134		info->MCR |= UART_MCR_DTR;
1135
1136	if (clear & TIOCM_RTS)
1137		info->MCR &= ~UART_MCR_RTS;
1138	if (clear & TIOCM_DTR)
1139		info->MCR &= ~UART_MCR_DTR;
1140
1141	outb(info->MCR, info->ioaddr + UART_MCR);
1142	spin_unlock_irqrestore(&info->slock, flags);
1143	return 0;
1144}
1145
1146static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg,
1147		struct async_icount *cprev)
1148{
1149	struct async_icount cnow;
1150	unsigned long flags;
1151	int ret;
1152
1153	spin_lock_irqsave(&info->slock, flags);
1154	cnow = info->icount;	/* atomic copy */
1155	spin_unlock_irqrestore(&info->slock, flags);
1156
1157	ret =	((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) ||
1158		((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) ||
1159		((arg & TIOCM_CD)  && (cnow.dcd != cprev->dcd)) ||
1160		((arg & TIOCM_CTS) && (cnow.cts != cprev->cts));
1161
1162	*cprev = cnow;
1163
1164	return ret;
1165}
1166
1167/* We should likely switch to TIOCGRS485/TIOCSRS485. */
1168static int mxser_ioctl_op_mode(struct mxser_port *port, int index, bool set,
1169		int __user *u_opmode)
1170{
1171	int opmode, p = index % 4;
1172	int shiftbit = p * 2;
1173	u8 val;
1174
1175	if (port->board->must_hwid != MOXA_MUST_MU860_HWID)
1176		return -EFAULT;
1177
1178	if (set) {
1179		if (get_user(opmode, u_opmode))
1180			return -EFAULT;
1181
1182		if (opmode & ~OP_MODE_MASK)
1183			return -EINVAL;
1184
1185		spin_lock_irq(&port->slock);
1186		val = inb(port->opmode_ioaddr);
1187		val &= ~(OP_MODE_MASK << shiftbit);
1188		val |= (opmode << shiftbit);
1189		outb(val, port->opmode_ioaddr);
1190		spin_unlock_irq(&port->slock);
1191
1192		return 0;
1193	}
1194
1195	spin_lock_irq(&port->slock);
1196	opmode = inb(port->opmode_ioaddr) >> shiftbit;
1197	spin_unlock_irq(&port->slock);
1198
1199	return put_user(opmode & OP_MODE_MASK, u_opmode);
1200}
1201
1202static int mxser_ioctl(struct tty_struct *tty,
1203		unsigned int cmd, unsigned long arg)
1204{
1205	struct mxser_port *info = tty->driver_data;
1206	struct async_icount cnow;
1207	unsigned long flags;
1208	void __user *argp = (void __user *)arg;
1209
1210	if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE)
1211		return mxser_ioctl_op_mode(info, tty->index,
1212				cmd == MOXA_SET_OP_MODE, argp);
1213
1214	if (cmd != TIOCMIWAIT && tty_io_error(tty))
1215		return -EIO;
1216
1217	switch (cmd) {
1218	case TIOCSERGETLSR:	/* Get line status register */
1219		return  mxser_get_lsr_info(info, argp);
1220		/*
1221		 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
1222		 * - mask passed in arg for lines of interest
1223		 *   (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
1224		 * Caller should use TIOCGICOUNT to see which one it was
1225		 */
1226	case TIOCMIWAIT:
1227		spin_lock_irqsave(&info->slock, flags);
1228		cnow = info->icount;	/* note the counters on entry */
1229		spin_unlock_irqrestore(&info->slock, flags);
1230
1231		return wait_event_interruptible(info->port.delta_msr_wait,
1232				mxser_cflags_changed(info, arg, &cnow));
1233	default:
1234		return -ENOIOCTLCMD;
1235	}
1236	return 0;
1237}
1238
1239	/*
1240	 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1241	 * Return: write counters to the user passed counter struct
1242	 * NB: both 1->0 and 0->1 transitions are counted except for
1243	 *     RI where only 0->1 is counted.
1244	 */
1245
1246static int mxser_get_icount(struct tty_struct *tty,
1247		struct serial_icounter_struct *icount)
1248
1249{
1250	struct mxser_port *info = tty->driver_data;
1251	struct async_icount cnow;
1252	unsigned long flags;
1253
1254	spin_lock_irqsave(&info->slock, flags);
1255	cnow = info->icount;
1256	spin_unlock_irqrestore(&info->slock, flags);
1257
1258	icount->frame = cnow.frame;
1259	icount->brk = cnow.brk;
1260	icount->overrun = cnow.overrun;
1261	icount->buf_overrun = cnow.buf_overrun;
1262	icount->parity = cnow.parity;
1263	icount->rx = cnow.rx;
1264	icount->tx = cnow.tx;
1265	icount->cts = cnow.cts;
1266	icount->dsr = cnow.dsr;
1267	icount->rng = cnow.rng;
1268	icount->dcd = cnow.dcd;
1269	return 0;
1270}
1271
1272/*
1273 * This routine is called by the upper-layer tty layer to signal that
1274 * incoming characters should be throttled.
1275 */
1276static void mxser_throttle(struct tty_struct *tty)
1277{
1278	struct mxser_port *info = tty->driver_data;
1279
1280	if (I_IXOFF(tty)) {
1281		if (info->board->must_hwid) {
1282			info->IER &= ~MOXA_MUST_RECV_ISR;
1283			outb(info->IER, info->ioaddr + UART_IER);
1284		} else {
1285			info->x_char = STOP_CHAR(tty);
1286			outb(0, info->ioaddr + UART_IER);
1287			info->IER |= UART_IER_THRI;
1288			outb(info->IER, info->ioaddr + UART_IER);
1289		}
1290	}
1291
1292	if (C_CRTSCTS(tty)) {
1293		info->MCR &= ~UART_MCR_RTS;
1294		outb(info->MCR, info->ioaddr + UART_MCR);
1295	}
1296}
1297
1298static void mxser_unthrottle(struct tty_struct *tty)
1299{
1300	struct mxser_port *info = tty->driver_data;
1301
1302	/* startrx */
1303	if (I_IXOFF(tty)) {
1304		if (info->x_char)
1305			info->x_char = 0;
1306		else {
1307			if (info->board->must_hwid) {
1308				info->IER |= MOXA_MUST_RECV_ISR;
1309				outb(info->IER, info->ioaddr + UART_IER);
1310			} else {
1311				info->x_char = START_CHAR(tty);
1312				outb(0, info->ioaddr + UART_IER);
1313				info->IER |= UART_IER_THRI;
1314				outb(info->IER, info->ioaddr + UART_IER);
1315			}
1316		}
1317	}
1318
1319	if (C_CRTSCTS(tty)) {
1320		info->MCR |= UART_MCR_RTS;
1321		outb(info->MCR, info->ioaddr + UART_MCR);
1322	}
1323}
1324
1325/*
1326 * mxser_stop() and mxser_start()
1327 *
1328 * This routines are called before setting or resetting tty->flow.stopped.
1329 * They enable or disable transmitter interrupts, as necessary.
1330 */
1331static void mxser_stop(struct tty_struct *tty)
1332{
1333	struct mxser_port *info = tty->driver_data;
1334	unsigned long flags;
1335
1336	spin_lock_irqsave(&info->slock, flags);
1337	if (info->IER & UART_IER_THRI)
1338		__mxser_stop_tx(info);
1339	spin_unlock_irqrestore(&info->slock, flags);
1340}
1341
1342static void mxser_start(struct tty_struct *tty)
1343{
1344	struct mxser_port *info = tty->driver_data;
1345	unsigned long flags;
1346
1347	spin_lock_irqsave(&info->slock, flags);
1348	if (!kfifo_is_empty(&info->port.xmit_fifo))
1349		__mxser_start_tx(info);
1350	spin_unlock_irqrestore(&info->slock, flags);
1351}
1352
1353static void mxser_set_termios(struct tty_struct *tty,
1354			      const struct ktermios *old_termios)
1355{
1356	struct mxser_port *info = tty->driver_data;
1357	unsigned long flags;
1358
1359	spin_lock_irqsave(&info->slock, flags);
1360	mxser_change_speed(tty, old_termios);
1361	spin_unlock_irqrestore(&info->slock, flags);
1362
1363	if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
1364		tty->hw_stopped = false;
1365		mxser_start(tty);
1366	}
1367
1368	/* Handle sw stopped */
1369	if ((old_termios->c_iflag & IXON) && !I_IXON(tty)) {
1370		tty->flow.stopped = 0;
1371
1372		if (info->board->must_hwid) {
1373			spin_lock_irqsave(&info->slock, flags);
1374			mxser_must_set_rx_sw_flow_control(info->ioaddr, false);
1375			spin_unlock_irqrestore(&info->slock, flags);
1376		}
1377
1378		mxser_start(tty);
1379	}
1380}
1381
1382static bool mxser_tx_empty(struct mxser_port *info)
1383{
1384	unsigned long flags;
1385	u8 lsr;
1386
1387	spin_lock_irqsave(&info->slock, flags);
1388	lsr = inb(info->ioaddr + UART_LSR);
1389	spin_unlock_irqrestore(&info->slock, flags);
1390
1391	return !(lsr & UART_LSR_TEMT);
1392}
1393
1394/*
1395 * mxser_wait_until_sent() --- wait until the transmitter is empty
1396 */
1397static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
1398{
1399	struct mxser_port *info = tty->driver_data;
1400	unsigned long expire, char_time;
1401
1402	if (info->type == PORT_UNKNOWN)
1403		return;
1404
1405	if (info->xmit_fifo_size == 0)
1406		return;		/* Just in case.... */
1407
1408	/*
1409	 * Set the check interval to be 1/5 of the estimated time to
1410	 * send a single character, and make it at least 1.  The check
1411	 * interval should also be less than the timeout.
1412	 *
1413	 * Note: we have to use pretty tight timings here to satisfy
1414	 * the NIST-PCTS.
1415	 */
1416	char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size;
1417	char_time = char_time / 5;
1418	if (char_time == 0)
1419		char_time = 1;
1420	if (timeout && timeout < char_time)
1421		char_time = timeout;
1422
1423	char_time = jiffies_to_msecs(char_time);
1424
1425	/*
1426	 * If the transmitter hasn't cleared in twice the approximate
1427	 * amount of time to send the entire FIFO, it probably won't
1428	 * ever clear.  This assumes the UART isn't doing flow
1429	 * control, which is currently the case.  Hence, if it ever
1430	 * takes longer than info->timeout, this is probably due to a
1431	 * UART bug of some kind.  So, we clamp the timeout parameter at
1432	 * 2*info->timeout.
1433	 */
1434	if (!timeout || timeout > 2 * info->timeout)
1435		timeout = 2 * info->timeout;
1436
1437	expire = jiffies + timeout;
1438
1439	while (mxser_tx_empty(info)) {
1440		msleep_interruptible(char_time);
1441		if (signal_pending(current))
1442			break;
1443		if (time_after(jiffies, expire))
1444			break;
1445	}
1446}
1447
1448/*
1449 * This routine is called by tty_hangup() when a hangup is signaled.
1450 */
1451static void mxser_hangup(struct tty_struct *tty)
1452{
1453	struct mxser_port *info = tty->driver_data;
1454
1455	mxser_flush_buffer(tty);
1456	tty_port_hangup(&info->port);
1457}
1458
1459/*
1460 * mxser_rs_break() --- routine which turns the break handling on or off
1461 */
1462static int mxser_rs_break(struct tty_struct *tty, int break_state)
1463{
1464	struct mxser_port *info = tty->driver_data;
1465	unsigned long flags;
1466	u8 lcr;
1467
1468	spin_lock_irqsave(&info->slock, flags);
1469	lcr = inb(info->ioaddr + UART_LCR);
1470	if (break_state == -1)
1471		lcr |= UART_LCR_SBC;
1472	else
1473		lcr &= ~UART_LCR_SBC;
1474	outb(lcr, info->ioaddr + UART_LCR);
1475	spin_unlock_irqrestore(&info->slock, flags);
1476
1477	return 0;
1478}
1479
1480static bool mxser_receive_chars_new(struct mxser_port *port, u8 status)
1481{
1482	enum mxser_must_hwid hwid = port->board->must_hwid;
1483	u8 gdl;
1484
1485	if (hwid == MOXA_OTHER_UART)
1486		return false;
1487	if (status & (UART_LSR_BRK_ERROR_BITS | MOXA_MUST_LSR_RERR))
1488		return false;
1489
1490	gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER);
1491	if (hwid == MOXA_MUST_MU150_HWID)
1492		gdl &= MOXA_MUST_GDL_MASK;
1493
1494	while (gdl--) {
1495		u8 ch = inb(port->ioaddr + UART_RX);
1496		if (!tty_insert_flip_char(&port->port, ch, 0))
1497			port->icount.buf_overrun++;
1498	}
1499
1500	return true;
1501}
1502
1503static u8 mxser_receive_chars_old(struct tty_struct *tty,
1504		                struct mxser_port *port, u8 status)
1505{
1506	enum mxser_must_hwid hwid = port->board->must_hwid;
1507	int ignored = 0;
1508	int max = 256;
1509	u8 ch;
1510
1511	do {
1512		if (max-- < 0)
1513			break;
1514
1515		ch = inb(port->ioaddr + UART_RX);
1516		if (hwid && (status & UART_LSR_OE))
1517			outb(port->FCR | UART_FCR_CLEAR_RCVR,
1518					port->ioaddr + UART_FCR);
1519		status &= port->read_status_mask;
1520		if (status & port->ignore_status_mask) {
1521			if (++ignored > 100)
1522				break;
1523		} else {
1524			u8 flag = 0;
1525			if (status & UART_LSR_BRK_ERROR_BITS) {
1526				if (status & UART_LSR_BI) {
1527					flag = TTY_BREAK;
1528					port->icount.brk++;
1529
1530					if (port->port.flags & ASYNC_SAK)
1531						do_SAK(tty);
1532				} else if (status & UART_LSR_PE) {
1533					flag = TTY_PARITY;
1534					port->icount.parity++;
1535				} else if (status & UART_LSR_FE) {
1536					flag = TTY_FRAME;
1537					port->icount.frame++;
1538				} else if (status & UART_LSR_OE) {
1539					flag = TTY_OVERRUN;
1540					port->icount.overrun++;
1541				}
1542			}
1543			if (!tty_insert_flip_char(&port->port, ch, flag)) {
1544				port->icount.buf_overrun++;
1545				break;
1546			}
1547		}
1548
1549		if (hwid)
1550			break;
1551
1552		status = inb(port->ioaddr + UART_LSR);
1553	} while (status & UART_LSR_DR);
1554
1555	return status;
1556}
1557
1558static u8 mxser_receive_chars(struct tty_struct *tty,
1559		struct mxser_port *port, u8 status)
1560{
1561	if (!mxser_receive_chars_new(port, status))
1562		status = mxser_receive_chars_old(tty, port, status);
1563
1564	tty_flip_buffer_push(&port->port);
1565
1566	return status;
1567}
1568
1569static void mxser_transmit_chars(struct tty_struct *tty, struct mxser_port *port)
1570{
1571	int count;
1572
1573	if (port->x_char) {
1574		outb(port->x_char, port->ioaddr + UART_TX);
1575		port->x_char = 0;
1576		port->icount.tx++;
1577		return;
1578	}
1579
1580	if (kfifo_is_empty(&port->port.xmit_fifo) || tty->flow.stopped ||
1581			(tty->hw_stopped && !mxser_16550A_or_MUST(port))) {
1582		__mxser_stop_tx(port);
1583		return;
1584	}
1585
1586	count = port->xmit_fifo_size;
1587	do {
1588		u8 c;
1589
1590		if (!kfifo_get(&port->port.xmit_fifo, &c))
1591			break;
1592
1593		outb(c, port->ioaddr + UART_TX);
1594		port->icount.tx++;
1595	} while (--count > 0);
1596
1597	if (kfifo_len(&port->port.xmit_fifo) < WAKEUP_CHARS)
1598		tty_wakeup(tty);
1599
1600	if (kfifo_is_empty(&port->port.xmit_fifo))
1601		__mxser_stop_tx(port);
1602}
1603
1604static bool mxser_port_isr(struct mxser_port *port)
1605{
1606	struct tty_struct *tty;
1607	u8 iir, status;
1608	bool error = false;
1609
1610	iir = inb(port->ioaddr + UART_IIR);
1611	if (iir & UART_IIR_NO_INT)
1612		return true;
1613
1614	iir &= MOXA_MUST_IIR_MASK;
1615	tty = tty_port_tty_get(&port->port);
1616	if (!tty) {
1617		status = inb(port->ioaddr + UART_LSR);
1618		outb(port->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
1619				port->ioaddr + UART_FCR);
1620		inb(port->ioaddr + UART_MSR);
1621
1622		error = true;
1623		goto put_tty;
1624	}
1625
1626	status = inb(port->ioaddr + UART_LSR);
1627
1628	if (port->board->must_hwid) {
1629		if (iir == MOXA_MUST_IIR_GDA ||
1630		    iir == MOXA_MUST_IIR_RDA ||
1631		    iir == MOXA_MUST_IIR_RTO ||
1632		    iir == MOXA_MUST_IIR_LSR)
1633			status = mxser_receive_chars(tty, port, status);
1634	} else {
1635		status &= port->read_status_mask;
1636		if (status & UART_LSR_DR)
1637			status = mxser_receive_chars(tty, port, status);
1638	}
1639
1640	mxser_check_modem_status(tty, port);
1641
1642	if (port->board->must_hwid) {
1643		if (iir == 0x02 && (status & UART_LSR_THRE))
1644			mxser_transmit_chars(tty, port);
1645	} else {
1646		if (status & UART_LSR_THRE)
1647			mxser_transmit_chars(tty, port);
1648	}
1649
1650put_tty:
1651	tty_kref_put(tty);
1652
1653	return error;
1654}
1655
1656/*
1657 * This is the serial driver's generic interrupt routine
1658 */
1659static irqreturn_t mxser_interrupt(int irq, void *dev_id)
1660{
1661	struct mxser_board *brd = dev_id;
1662	struct mxser_port *port;
1663	unsigned int int_cnt, pass_counter = 0;
1664	unsigned int i, max = brd->nports;
1665	int handled = IRQ_NONE;
1666	u8 irqbits, bits, mask = BIT(max) - 1;
1667
1668	while (pass_counter++ < MXSER_ISR_PASS_LIMIT) {
1669		irqbits = inb(brd->vector) & mask;
1670		if (irqbits == mask)
1671			break;
1672
1673		handled = IRQ_HANDLED;
1674		for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
1675			if (irqbits == mask)
1676				break;
1677			if (bits & irqbits)
1678				continue;
1679			port = &brd->ports[i];
1680
1681			int_cnt = 0;
1682			spin_lock(&port->slock);
1683			do {
1684				if (mxser_port_isr(port))
1685					break;
1686			} while (int_cnt++ < MXSER_ISR_PASS_LIMIT);
1687			spin_unlock(&port->slock);
1688		}
1689	}
1690
1691	return handled;
1692}
1693
1694static const struct tty_operations mxser_ops = {
1695	.open = mxser_open,
1696	.close = mxser_close,
1697	.write = mxser_write,
1698	.put_char = mxser_put_char,
1699	.flush_chars = mxser_flush_chars,
1700	.write_room = mxser_write_room,
1701	.chars_in_buffer = mxser_chars_in_buffer,
1702	.flush_buffer = mxser_flush_buffer,
1703	.ioctl = mxser_ioctl,
1704	.throttle = mxser_throttle,
1705	.unthrottle = mxser_unthrottle,
1706	.set_termios = mxser_set_termios,
1707	.stop = mxser_stop,
1708	.start = mxser_start,
1709	.hangup = mxser_hangup,
1710	.break_ctl = mxser_rs_break,
1711	.wait_until_sent = mxser_wait_until_sent,
1712	.tiocmget = mxser_tiocmget,
1713	.tiocmset = mxser_tiocmset,
1714	.set_serial = mxser_set_serial_info,
1715	.get_serial = mxser_get_serial_info,
1716	.get_icount = mxser_get_icount,
1717};
1718
1719static const struct tty_port_operations mxser_port_ops = {
1720	.carrier_raised = mxser_carrier_raised,
1721	.dtr_rts = mxser_dtr_rts,
1722	.activate = mxser_activate,
1723	.shutdown = mxser_shutdown_port,
1724};
1725
1726/*
1727 * The MOXA Smartio/Industio serial driver boot-time initialization code!
1728 */
1729
1730static void mxser_initbrd(struct mxser_board *brd, bool high_baud)
1731{
1732	struct mxser_port *info;
1733	unsigned int i;
1734	bool is_mu860;
1735
1736	brd->must_hwid = mxser_must_get_hwid(brd->ports[0].ioaddr);
1737	is_mu860 = brd->must_hwid == MOXA_MUST_MU860_HWID;
1738
1739	for (i = 0; i < UART_INFO_NUM; i++) {
1740		if (Gpci_uart_info[i].type == brd->must_hwid) {
1741			brd->max_baud = Gpci_uart_info[i].max_baud;
1742
1743			/* exception....CP-102 */
1744			if (high_baud)
1745				brd->max_baud = 921600;
1746			break;
1747		}
1748	}
1749
1750	if (is_mu860) {
1751		/* set to RS232 mode by default */
1752		outb(0, brd->vector + 4);
1753		outb(0, brd->vector + 0x0c);
1754	}
1755
1756	for (i = 0; i < brd->nports; i++) {
1757		info = &brd->ports[i];
1758		if (is_mu860) {
1759			if (i < 4)
1760				info->opmode_ioaddr = brd->vector + 4;
1761			else
1762				info->opmode_ioaddr = brd->vector + 0x0c;
1763		}
1764		tty_port_init(&info->port);
1765		info->port.ops = &mxser_port_ops;
1766		info->board = brd;
1767
1768		/* Enhance mode enabled here */
1769		if (brd->must_hwid != MOXA_OTHER_UART)
1770			mxser_must_set_enhance_mode(info->ioaddr, true);
1771
1772		info->type = PORT_16550A;
1773
1774		mxser_process_txrx_fifo(info);
1775
1776		info->port.close_delay = 5 * HZ / 10;
1777		info->port.closing_wait = 30 * HZ;
1778		spin_lock_init(&info->slock);
1779
1780		/* before set INT ISR, disable all int */
1781		outb(inb(info->ioaddr + UART_IER) & 0xf0,
1782			info->ioaddr + UART_IER);
1783	}
1784}
1785
1786static int mxser_probe(struct pci_dev *pdev,
1787		const struct pci_device_id *ent)
1788{
1789	struct mxser_board *brd;
1790	unsigned int i, base;
1791	unsigned long ioaddress;
1792	unsigned short nports = MXSER_NPORTS(ent->driver_data);
1793	struct device *tty_dev;
1794	int retval = -EINVAL;
1795
1796	i = find_first_zero_bit(mxser_boards, MXSER_BOARDS);
1797	if (i >= MXSER_BOARDS) {
1798		dev_err(&pdev->dev, "too many boards found (maximum %d), board "
1799				"not configured\n", MXSER_BOARDS);
1800		goto err;
1801	}
1802
1803	brd = devm_kzalloc(&pdev->dev, struct_size(brd, ports, nports),
1804			GFP_KERNEL);
1805	if (!brd)
1806		goto err;
1807
1808	brd->idx = i;
1809	__set_bit(brd->idx, mxser_boards);
1810	base = i * MXSER_PORTS_PER_BOARD;
1811
1812	retval = pcim_enable_device(pdev);
1813	if (retval) {
1814		dev_err(&pdev->dev, "PCI enable failed\n");
1815		goto err_zero;
1816	}
1817
1818	/* io address */
1819	ioaddress = pci_resource_start(pdev, 2);
1820	retval = pci_request_region(pdev, 2, "mxser(IO)");
1821	if (retval)
1822		goto err_zero;
1823
1824	brd->nports = nports;
1825	for (i = 0; i < nports; i++)
1826		brd->ports[i].ioaddr = ioaddress + 8 * i;
1827
1828	/* vector */
1829	ioaddress = pci_resource_start(pdev, 3);
1830	retval = pci_request_region(pdev, 3, "mxser(vector)");
1831	if (retval)
1832		goto err_zero;
1833	brd->vector = ioaddress;
1834
1835	/* irq */
1836	brd->irq = pdev->irq;
1837
1838	mxser_initbrd(brd, ent->driver_data & MXSER_HIGHBAUD);
1839
1840	retval = devm_request_irq(&pdev->dev, brd->irq, mxser_interrupt,
1841			IRQF_SHARED, "mxser", brd);
1842	if (retval) {
1843		dev_err(&pdev->dev, "request irq failed");
1844		goto err_relbrd;
1845	}
1846
1847	for (i = 0; i < nports; i++) {
1848		tty_dev = tty_port_register_device(&brd->ports[i].port,
1849				mxvar_sdriver, base + i, &pdev->dev);
1850		if (IS_ERR(tty_dev)) {
1851			retval = PTR_ERR(tty_dev);
1852			for (; i > 0; i--)
1853				tty_unregister_device(mxvar_sdriver,
1854					base + i - 1);
1855			goto err_relbrd;
1856		}
1857	}
1858
1859	pci_set_drvdata(pdev, brd);
1860
1861	return 0;
1862err_relbrd:
1863	for (i = 0; i < nports; i++)
1864		tty_port_destroy(&brd->ports[i].port);
1865err_zero:
1866	__clear_bit(brd->idx, mxser_boards);
1867err:
1868	return retval;
1869}
1870
1871static void mxser_remove(struct pci_dev *pdev)
1872{
1873	struct mxser_board *brd = pci_get_drvdata(pdev);
1874	unsigned int i, base = brd->idx * MXSER_PORTS_PER_BOARD;
1875
1876	for (i = 0; i < brd->nports; i++) {
1877		tty_unregister_device(mxvar_sdriver, base + i);
1878		tty_port_destroy(&brd->ports[i].port);
1879	}
1880
1881	__clear_bit(brd->idx, mxser_boards);
1882}
1883
1884static struct pci_driver mxser_driver = {
1885	.name = "mxser",
1886	.id_table = mxser_pcibrds,
1887	.probe = mxser_probe,
1888	.remove = mxser_remove
1889};
1890
1891static int __init mxser_module_init(void)
1892{
1893	int retval;
1894
1895	mxvar_sdriver = tty_alloc_driver(MXSER_PORTS, TTY_DRIVER_REAL_RAW |
1896			TTY_DRIVER_DYNAMIC_DEV);
1897	if (IS_ERR(mxvar_sdriver))
1898		return PTR_ERR(mxvar_sdriver);
1899
1900	/* Initialize the tty_driver structure */
1901	mxvar_sdriver->name = "ttyMI";
1902	mxvar_sdriver->major = ttymajor;
1903	mxvar_sdriver->minor_start = 0;
1904	mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
1905	mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
1906	mxvar_sdriver->init_termios = tty_std_termios;
1907	mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
1908	tty_set_operations(mxvar_sdriver, &mxser_ops);
1909
1910	retval = tty_register_driver(mxvar_sdriver);
1911	if (retval) {
1912		printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family "
1913				"tty driver !\n");
1914		goto err_put;
1915	}
1916
1917	retval = pci_register_driver(&mxser_driver);
1918	if (retval) {
1919		printk(KERN_ERR "mxser: can't register pci driver\n");
1920		goto err_unr;
1921	}
1922
1923	return 0;
1924err_unr:
1925	tty_unregister_driver(mxvar_sdriver);
1926err_put:
1927	tty_driver_kref_put(mxvar_sdriver);
1928	return retval;
1929}
1930
1931static void __exit mxser_module_exit(void)
1932{
1933	pci_unregister_driver(&mxser_driver);
1934	tty_unregister_driver(mxvar_sdriver);
1935	tty_driver_kref_put(mxvar_sdriver);
1936}
1937
1938module_init(mxser_module_init);
1939module_exit(mxser_module_exit);