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1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2022 Linaro Ltd.
5 */
6
7/* DOC: IPA Interrupts
8 *
9 * The IPA has an interrupt line distinct from the interrupt used by the GSI
10 * code. Whereas GSI interrupts are generally related to channel events (like
11 * transfer completions), IPA interrupts are related to other events related
12 * to the IPA. Some of the IPA interrupts come from a microcontroller
13 * embedded in the IPA. Each IPA interrupt type can be both masked and
14 * acknowledged independent of the others.
15 *
16 * Two of the IPA interrupts are initiated by the microcontroller. A third
17 * can be generated to signal the need for a wakeup/resume when an IPA
18 * endpoint has been suspended. There are other IPA events, but at this
19 * time only these three are supported.
20 */
21
22#include <linux/types.h>
23#include <linux/interrupt.h>
24#include <linux/pm_runtime.h>
25#include <linux/pm_wakeirq.h>
26
27#include "ipa.h"
28#include "ipa_reg.h"
29#include "ipa_endpoint.h"
30#include "ipa_power.h"
31#include "ipa_uc.h"
32#include "ipa_interrupt.h"
33
34/**
35 * struct ipa_interrupt - IPA interrupt information
36 * @ipa: IPA pointer
37 * @irq: Linux IRQ number used for IPA interrupts
38 * @enabled: Mask indicating which interrupts are enabled
39 */
40struct ipa_interrupt {
41 struct ipa *ipa;
42 u32 irq;
43 u32 enabled;
44};
45
46/* Process a particular interrupt type that has been received */
47static void ipa_interrupt_process(struct ipa_interrupt *interrupt, u32 irq_id)
48{
49 struct ipa *ipa = interrupt->ipa;
50 const struct reg *reg;
51 u32 mask = BIT(irq_id);
52 u32 offset;
53
54 reg = ipa_reg(ipa, IPA_IRQ_CLR);
55 offset = reg_offset(reg);
56
57 switch (irq_id) {
58 case IPA_IRQ_UC_0:
59 case IPA_IRQ_UC_1:
60 /* For microcontroller interrupts, clear the interrupt right
61 * away, "to avoid clearing unhandled interrupts."
62 */
63 iowrite32(mask, ipa->reg_virt + offset);
64 ipa_uc_interrupt_handler(ipa, irq_id);
65 break;
66
67 case IPA_IRQ_TX_SUSPEND:
68 /* Clearing the SUSPEND_TX interrupt also clears the
69 * register that tells us which suspended endpoint(s)
70 * caused the interrupt, so defer clearing until after
71 * the handler has been called.
72 */
73 ipa_power_suspend_handler(ipa, irq_id);
74 fallthrough;
75
76 default: /* Silently ignore (and clear) any other condition */
77 iowrite32(mask, ipa->reg_virt + offset);
78 break;
79 }
80}
81
82/* IPA IRQ handler is threaded */
83static irqreturn_t ipa_isr_thread(int irq, void *dev_id)
84{
85 struct ipa_interrupt *interrupt = dev_id;
86 struct ipa *ipa = interrupt->ipa;
87 u32 enabled = interrupt->enabled;
88 const struct reg *reg;
89 struct device *dev;
90 u32 pending;
91 u32 offset;
92 u32 mask;
93 int ret;
94
95 dev = &ipa->pdev->dev;
96 ret = pm_runtime_get_sync(dev);
97 if (WARN_ON(ret < 0))
98 goto out_power_put;
99
100 /* The status register indicates which conditions are present,
101 * including conditions whose interrupt is not enabled. Handle
102 * only the enabled ones.
103 */
104 reg = ipa_reg(ipa, IPA_IRQ_STTS);
105 offset = reg_offset(reg);
106 pending = ioread32(ipa->reg_virt + offset);
107 while ((mask = pending & enabled)) {
108 do {
109 u32 irq_id = __ffs(mask);
110
111 mask ^= BIT(irq_id);
112
113 ipa_interrupt_process(interrupt, irq_id);
114 } while (mask);
115 pending = ioread32(ipa->reg_virt + offset);
116 }
117
118 /* If any disabled interrupts are pending, clear them */
119 if (pending) {
120 dev_dbg(dev, "clearing disabled IPA interrupts 0x%08x\n",
121 pending);
122 reg = ipa_reg(ipa, IPA_IRQ_CLR);
123 iowrite32(pending, ipa->reg_virt + reg_offset(reg));
124 }
125out_power_put:
126 pm_runtime_mark_last_busy(dev);
127 (void)pm_runtime_put_autosuspend(dev);
128
129 return IRQ_HANDLED;
130}
131
132static void ipa_interrupt_enabled_update(struct ipa *ipa)
133{
134 const struct reg *reg = ipa_reg(ipa, IPA_IRQ_EN);
135
136 iowrite32(ipa->interrupt->enabled, ipa->reg_virt + reg_offset(reg));
137}
138
139/* Enable an IPA interrupt type */
140void ipa_interrupt_enable(struct ipa *ipa, enum ipa_irq_id ipa_irq)
141{
142 /* Update the IPA interrupt mask to enable it */
143 ipa->interrupt->enabled |= BIT(ipa_irq);
144 ipa_interrupt_enabled_update(ipa);
145}
146
147/* Disable an IPA interrupt type */
148void ipa_interrupt_disable(struct ipa *ipa, enum ipa_irq_id ipa_irq)
149{
150 /* Update the IPA interrupt mask to disable it */
151 ipa->interrupt->enabled &= ~BIT(ipa_irq);
152 ipa_interrupt_enabled_update(ipa);
153}
154
155void ipa_interrupt_irq_disable(struct ipa *ipa)
156{
157 disable_irq(ipa->interrupt->irq);
158}
159
160void ipa_interrupt_irq_enable(struct ipa *ipa)
161{
162 enable_irq(ipa->interrupt->irq);
163}
164
165/* Common function used to enable/disable TX_SUSPEND for an endpoint */
166static void ipa_interrupt_suspend_control(struct ipa_interrupt *interrupt,
167 u32 endpoint_id, bool enable)
168{
169 struct ipa *ipa = interrupt->ipa;
170 u32 mask = BIT(endpoint_id % 32);
171 u32 unit = endpoint_id / 32;
172 const struct reg *reg;
173 u32 offset;
174 u32 val;
175
176 WARN_ON(!test_bit(endpoint_id, ipa->available));
177
178 /* IPA version 3.0 does not support TX_SUSPEND interrupt control */
179 if (ipa->version == IPA_VERSION_3_0)
180 return;
181
182 reg = ipa_reg(ipa, IRQ_SUSPEND_EN);
183 offset = reg_n_offset(reg, unit);
184 val = ioread32(ipa->reg_virt + offset);
185
186 if (enable)
187 val |= mask;
188 else
189 val &= ~mask;
190
191 iowrite32(val, ipa->reg_virt + offset);
192}
193
194/* Enable TX_SUSPEND for an endpoint */
195void
196ipa_interrupt_suspend_enable(struct ipa_interrupt *interrupt, u32 endpoint_id)
197{
198 ipa_interrupt_suspend_control(interrupt, endpoint_id, true);
199}
200
201/* Disable TX_SUSPEND for an endpoint */
202void
203ipa_interrupt_suspend_disable(struct ipa_interrupt *interrupt, u32 endpoint_id)
204{
205 ipa_interrupt_suspend_control(interrupt, endpoint_id, false);
206}
207
208/* Clear the suspend interrupt for all endpoints that signaled it */
209void ipa_interrupt_suspend_clear_all(struct ipa_interrupt *interrupt)
210{
211 struct ipa *ipa = interrupt->ipa;
212 u32 unit_count;
213 u32 unit;
214
215 unit_count = DIV_ROUND_UP(ipa->endpoint_count, 32);
216 for (unit = 0; unit < unit_count; unit++) {
217 const struct reg *reg;
218 u32 val;
219
220 reg = ipa_reg(ipa, IRQ_SUSPEND_INFO);
221 val = ioread32(ipa->reg_virt + reg_n_offset(reg, unit));
222
223 /* SUSPEND interrupt status isn't cleared on IPA version 3.0 */
224 if (ipa->version == IPA_VERSION_3_0)
225 continue;
226
227 reg = ipa_reg(ipa, IRQ_SUSPEND_CLR);
228 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, unit));
229 }
230}
231
232/* Simulate arrival of an IPA TX_SUSPEND interrupt */
233void ipa_interrupt_simulate_suspend(struct ipa_interrupt *interrupt)
234{
235 ipa_interrupt_process(interrupt, IPA_IRQ_TX_SUSPEND);
236}
237
238/* Configure the IPA interrupt framework */
239struct ipa_interrupt *ipa_interrupt_config(struct ipa *ipa)
240{
241 struct device *dev = &ipa->pdev->dev;
242 struct ipa_interrupt *interrupt;
243 const struct reg *reg;
244 unsigned int irq;
245 int ret;
246
247 ret = platform_get_irq_byname(ipa->pdev, "ipa");
248 if (ret <= 0) {
249 dev_err(dev, "DT error %d getting \"ipa\" IRQ property\n",
250 ret);
251 return ERR_PTR(ret ? : -EINVAL);
252 }
253 irq = ret;
254
255 interrupt = kzalloc(sizeof(*interrupt), GFP_KERNEL);
256 if (!interrupt)
257 return ERR_PTR(-ENOMEM);
258 interrupt->ipa = ipa;
259 interrupt->irq = irq;
260
261 /* Start with all IPA interrupts disabled */
262 reg = ipa_reg(ipa, IPA_IRQ_EN);
263 iowrite32(0, ipa->reg_virt + reg_offset(reg));
264
265 ret = request_threaded_irq(irq, NULL, ipa_isr_thread, IRQF_ONESHOT,
266 "ipa", interrupt);
267 if (ret) {
268 dev_err(dev, "error %d requesting \"ipa\" IRQ\n", ret);
269 goto err_kfree;
270 }
271
272 ret = dev_pm_set_wake_irq(dev, irq);
273 if (ret) {
274 dev_err(dev, "error %d registering \"ipa\" IRQ as wakeirq\n", ret);
275 goto err_free_irq;
276 }
277
278 return interrupt;
279
280err_free_irq:
281 free_irq(interrupt->irq, interrupt);
282err_kfree:
283 kfree(interrupt);
284
285 return ERR_PTR(ret);
286}
287
288/* Inverse of ipa_interrupt_config() */
289void ipa_interrupt_deconfig(struct ipa_interrupt *interrupt)
290{
291 struct device *dev = &interrupt->ipa->pdev->dev;
292
293 dev_pm_clear_wake_irq(dev);
294 free_irq(interrupt->irq, interrupt);
295 kfree(interrupt);
296}
1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2022 Linaro Ltd.
5 */
6
7/* DOC: IPA Interrupts
8 *
9 * The IPA has an interrupt line distinct from the interrupt used by the GSI
10 * code. Whereas GSI interrupts are generally related to channel events (like
11 * transfer completions), IPA interrupts are related to other events related
12 * to the IPA. Some of the IPA interrupts come from a microcontroller
13 * embedded in the IPA. Each IPA interrupt type can be both masked and
14 * acknowledged independent of the others.
15 *
16 * Two of the IPA interrupts are initiated by the microcontroller. A third
17 * can be generated to signal the need for a wakeup/resume when an IPA
18 * endpoint has been suspended. There are other IPA events, but at this
19 * time only these three are supported.
20 */
21
22#include <linux/types.h>
23#include <linux/interrupt.h>
24#include <linux/pm_runtime.h>
25
26#include "ipa.h"
27#include "ipa_reg.h"
28#include "ipa_endpoint.h"
29#include "ipa_interrupt.h"
30
31/**
32 * struct ipa_interrupt - IPA interrupt information
33 * @ipa: IPA pointer
34 * @irq: Linux IRQ number used for IPA interrupts
35 * @enabled: Mask indicating which interrupts are enabled
36 * @handler: Array of handlers indexed by IPA interrupt ID
37 */
38struct ipa_interrupt {
39 struct ipa *ipa;
40 u32 irq;
41 u32 enabled;
42 ipa_irq_handler_t handler[IPA_IRQ_COUNT];
43};
44
45/* Returns true if the interrupt type is associated with the microcontroller */
46static bool ipa_interrupt_uc(struct ipa_interrupt *interrupt, u32 irq_id)
47{
48 return irq_id == IPA_IRQ_UC_0 || irq_id == IPA_IRQ_UC_1;
49}
50
51/* Process a particular interrupt type that has been received */
52static void ipa_interrupt_process(struct ipa_interrupt *interrupt, u32 irq_id)
53{
54 bool uc_irq = ipa_interrupt_uc(interrupt, irq_id);
55 struct ipa *ipa = interrupt->ipa;
56 const struct ipa_reg *reg;
57 u32 mask = BIT(irq_id);
58 u32 offset;
59
60 /* For microcontroller interrupts, clear the interrupt right away,
61 * "to avoid clearing unhandled interrupts."
62 */
63 reg = ipa_reg(ipa, IPA_IRQ_CLR);
64 offset = ipa_reg_offset(reg);
65 if (uc_irq)
66 iowrite32(mask, ipa->reg_virt + offset);
67
68 if (irq_id < IPA_IRQ_COUNT && interrupt->handler[irq_id])
69 interrupt->handler[irq_id](interrupt->ipa, irq_id);
70
71 /* Clearing the SUSPEND_TX interrupt also clears the register
72 * that tells us which suspended endpoint(s) caused the interrupt,
73 * so defer clearing until after the handler has been called.
74 */
75 if (!uc_irq)
76 iowrite32(mask, ipa->reg_virt + offset);
77}
78
79/* IPA IRQ handler is threaded */
80static irqreturn_t ipa_isr_thread(int irq, void *dev_id)
81{
82 struct ipa_interrupt *interrupt = dev_id;
83 struct ipa *ipa = interrupt->ipa;
84 u32 enabled = interrupt->enabled;
85 const struct ipa_reg *reg;
86 struct device *dev;
87 u32 pending;
88 u32 offset;
89 u32 mask;
90 int ret;
91
92 dev = &ipa->pdev->dev;
93 ret = pm_runtime_get_sync(dev);
94 if (WARN_ON(ret < 0))
95 goto out_power_put;
96
97 /* The status register indicates which conditions are present,
98 * including conditions whose interrupt is not enabled. Handle
99 * only the enabled ones.
100 */
101 reg = ipa_reg(ipa, IPA_IRQ_STTS);
102 offset = ipa_reg_offset(reg);
103 pending = ioread32(ipa->reg_virt + offset);
104 while ((mask = pending & enabled)) {
105 do {
106 u32 irq_id = __ffs(mask);
107
108 mask ^= BIT(irq_id);
109
110 ipa_interrupt_process(interrupt, irq_id);
111 } while (mask);
112 pending = ioread32(ipa->reg_virt + offset);
113 }
114
115 /* If any disabled interrupts are pending, clear them */
116 if (pending) {
117 dev_dbg(dev, "clearing disabled IPA interrupts 0x%08x\n",
118 pending);
119 reg = ipa_reg(ipa, IPA_IRQ_CLR);
120 offset = ipa_reg_offset(reg);
121 iowrite32(pending, ipa->reg_virt + offset);
122 }
123out_power_put:
124 pm_runtime_mark_last_busy(dev);
125 (void)pm_runtime_put_autosuspend(dev);
126
127 return IRQ_HANDLED;
128}
129
130void ipa_interrupt_irq_disable(struct ipa *ipa)
131{
132 disable_irq(ipa->interrupt->irq);
133}
134
135void ipa_interrupt_irq_enable(struct ipa *ipa)
136{
137 enable_irq(ipa->interrupt->irq);
138}
139
140/* Common function used to enable/disable TX_SUSPEND for an endpoint */
141static void ipa_interrupt_suspend_control(struct ipa_interrupt *interrupt,
142 u32 endpoint_id, bool enable)
143{
144 struct ipa *ipa = interrupt->ipa;
145 u32 mask = BIT(endpoint_id % 32);
146 u32 unit = endpoint_id / 32;
147 const struct ipa_reg *reg;
148 u32 offset;
149 u32 val;
150
151 WARN_ON(!test_bit(endpoint_id, ipa->available));
152
153 /* IPA version 3.0 does not support TX_SUSPEND interrupt control */
154 if (ipa->version == IPA_VERSION_3_0)
155 return;
156
157 reg = ipa_reg(ipa, IRQ_SUSPEND_EN);
158 offset = ipa_reg_n_offset(reg, unit);
159 val = ioread32(ipa->reg_virt + offset);
160
161 if (enable)
162 val |= mask;
163 else
164 val &= ~mask;
165
166 iowrite32(val, ipa->reg_virt + offset);
167}
168
169/* Enable TX_SUSPEND for an endpoint */
170void
171ipa_interrupt_suspend_enable(struct ipa_interrupt *interrupt, u32 endpoint_id)
172{
173 ipa_interrupt_suspend_control(interrupt, endpoint_id, true);
174}
175
176/* Disable TX_SUSPEND for an endpoint */
177void
178ipa_interrupt_suspend_disable(struct ipa_interrupt *interrupt, u32 endpoint_id)
179{
180 ipa_interrupt_suspend_control(interrupt, endpoint_id, false);
181}
182
183/* Clear the suspend interrupt for all endpoints that signaled it */
184void ipa_interrupt_suspend_clear_all(struct ipa_interrupt *interrupt)
185{
186 struct ipa *ipa = interrupt->ipa;
187 u32 unit_count;
188 u32 unit;
189
190 unit_count = roundup(ipa->endpoint_count, 32);
191 for (unit = 0; unit < unit_count; unit++) {
192 const struct ipa_reg *reg;
193 u32 val;
194
195 reg = ipa_reg(ipa, IRQ_SUSPEND_INFO);
196 val = ioread32(ipa->reg_virt + ipa_reg_n_offset(reg, unit));
197
198 /* SUSPEND interrupt status isn't cleared on IPA version 3.0 */
199 if (ipa->version == IPA_VERSION_3_0)
200 continue;
201
202 reg = ipa_reg(ipa, IRQ_SUSPEND_CLR);
203 iowrite32(val, ipa->reg_virt + ipa_reg_n_offset(reg, unit));
204 }
205}
206
207/* Simulate arrival of an IPA TX_SUSPEND interrupt */
208void ipa_interrupt_simulate_suspend(struct ipa_interrupt *interrupt)
209{
210 ipa_interrupt_process(interrupt, IPA_IRQ_TX_SUSPEND);
211}
212
213/* Add a handler for an IPA interrupt */
214void ipa_interrupt_add(struct ipa_interrupt *interrupt,
215 enum ipa_irq_id ipa_irq, ipa_irq_handler_t handler)
216{
217 struct ipa *ipa = interrupt->ipa;
218 const struct ipa_reg *reg;
219
220 if (WARN_ON(ipa_irq >= IPA_IRQ_COUNT))
221 return;
222
223 interrupt->handler[ipa_irq] = handler;
224
225 /* Update the IPA interrupt mask to enable it */
226 interrupt->enabled |= BIT(ipa_irq);
227
228 reg = ipa_reg(ipa, IPA_IRQ_EN);
229 iowrite32(interrupt->enabled, ipa->reg_virt + ipa_reg_offset(reg));
230}
231
232/* Remove the handler for an IPA interrupt type */
233void
234ipa_interrupt_remove(struct ipa_interrupt *interrupt, enum ipa_irq_id ipa_irq)
235{
236 struct ipa *ipa = interrupt->ipa;
237 const struct ipa_reg *reg;
238
239 if (WARN_ON(ipa_irq >= IPA_IRQ_COUNT))
240 return;
241
242 /* Update the IPA interrupt mask to disable it */
243 interrupt->enabled &= ~BIT(ipa_irq);
244
245 reg = ipa_reg(ipa, IPA_IRQ_EN);
246 iowrite32(interrupt->enabled, ipa->reg_virt + ipa_reg_offset(reg));
247
248 interrupt->handler[ipa_irq] = NULL;
249}
250
251/* Configure the IPA interrupt framework */
252struct ipa_interrupt *ipa_interrupt_config(struct ipa *ipa)
253{
254 struct device *dev = &ipa->pdev->dev;
255 struct ipa_interrupt *interrupt;
256 const struct ipa_reg *reg;
257 unsigned int irq;
258 int ret;
259
260 ret = platform_get_irq_byname(ipa->pdev, "ipa");
261 if (ret <= 0) {
262 dev_err(dev, "DT error %d getting \"ipa\" IRQ property\n",
263 ret);
264 return ERR_PTR(ret ? : -EINVAL);
265 }
266 irq = ret;
267
268 interrupt = kzalloc(sizeof(*interrupt), GFP_KERNEL);
269 if (!interrupt)
270 return ERR_PTR(-ENOMEM);
271 interrupt->ipa = ipa;
272 interrupt->irq = irq;
273
274 /* Start with all IPA interrupts disabled */
275 reg = ipa_reg(ipa, IPA_IRQ_EN);
276 iowrite32(0, ipa->reg_virt + ipa_reg_offset(reg));
277
278 ret = request_threaded_irq(irq, NULL, ipa_isr_thread, IRQF_ONESHOT,
279 "ipa", interrupt);
280 if (ret) {
281 dev_err(dev, "error %d requesting \"ipa\" IRQ\n", ret);
282 goto err_kfree;
283 }
284
285 ret = enable_irq_wake(irq);
286 if (ret) {
287 dev_err(dev, "error %d enabling wakeup for \"ipa\" IRQ\n", ret);
288 goto err_free_irq;
289 }
290
291 return interrupt;
292
293err_free_irq:
294 free_irq(interrupt->irq, interrupt);
295err_kfree:
296 kfree(interrupt);
297
298 return ERR_PTR(ret);
299}
300
301/* Inverse of ipa_interrupt_config() */
302void ipa_interrupt_deconfig(struct ipa_interrupt *interrupt)
303{
304 struct device *dev = &interrupt->ipa->pdev->dev;
305 int ret;
306
307 ret = disable_irq_wake(interrupt->irq);
308 if (ret)
309 dev_err(dev, "error %d disabling \"ipa\" IRQ wakeup\n", ret);
310 free_irq(interrupt->irq, interrupt);
311 kfree(interrupt);
312}